GD25VE32CTIG [GIGADEVICE]
Uniform Sector Dual and Quad Serial Flash;
| 型号： | GD25VE32CTIG |
| 厂家： | 
GigaDevice |
| 描述： | Uniform Sector Dual and Quad Serial Flash |
| 文件： | 总63页 (文件大小：1346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
GD25VE32C
DATASHEET
1
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
Contents
1. FEATURES ................................................................................................................................................................ 4
2. GENERAL DESCRIPTION......................................................................................................................................5
3. MEMORY ORGANIZATION ....................................................................................................................................7
4. DEVICE OPERATION ..............................................................................................................................................8
5. DATA PROTECTION................................................................................................................................................9
6. STATUS REGISTER............................................................................................................................................... 11
7. COMMANDS DESCRIPTION ............................................................................................................................... 13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
WRITE ENABLE (WREN) (06H)......................................................................................................................... 16
WRITE DISABLE (WRDI) (04H) ......................................................................................................................... 16
WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) .................................................................................. 16
READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) .................................................................................. 17
WRITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H)................................................................................ 17
READ DATA BYTES (READ) (03H).................................................................................................................... 18
READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) .............................................................................. 19
DUAL OUTPUT FAST READ (3BH)...................................................................................................................... 19
QUAD OUTPUT FAST READ (6BH) ..................................................................................................................... 20
7.10. DUAL I/O FAST READ (BBH)............................................................................................................................. 20
7.11. QUAD I/O FAST READ (EBH)............................................................................................................................. 22
7.12. QUAD I/O WORD FAST READ (E7H) .................................................................................................................. 23
7.13. SET BURST WITH WRAP (77H) ........................................................................................................................... 25
7.14. PAGE PROGRAM (PP) (02H) ............................................................................................................................... 26
7.15. QUAD PAGE PROGRAM (32H)............................................................................................................................. 27
7.16. FAST PAGE PROGRAM (FPP) (F2H).................................................................................................................... 28
7.17. SECTOR ERASE (SE) (20H)................................................................................................................................. 29
7.18. 32KB BLOCK ERASE (BE) (52H) ....................................................................................................................... 29
7.19. 64KB BLOCK ERASE (BE) (D8H) ...................................................................................................................... 30
7.20. CHIP ERASE (CE) (60/C7H) ............................................................................................................................... 30
7.21. DEEP POWER-DOWN (DP) (B9H)....................................................................................................................... 31
7.22. RELEASE FROM DEEP POWER-DOWN OR HIGH PERFORMANCE MODE AND READ DEVICE ID (RDI) (ABH)...... 32
7.23. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H)........................................................................................ 33
7.24. DUAL I/O READ MANUFACTURE ID/ DEVICE ID (92H)...................................................................................... 34
7.25. QUAD I/O READ MANUFACTURE ID/ DEVICE ID (94H) ..................................................................................... 35
7.26. READ IDENTIFICATION (RDID) (9FH)................................................................................................................ 36
7.27. HIGH PERFORMANCE MODE (HPM) (A3H)........................................................................................................ 37
7.28. PROGRAM/ERASE SUSPEND (PES) (75H) ........................................................................................................... 37
7.29. PROGRAM/ERASE RESUME (PER) (7AH) ........................................................................................................... 38
7.30. ERASE SECURITY REGISTERS (44H) ................................................................................................................... 38
7.31. PROGRAM SECURITY REGISTERS (42H).............................................................................................................. 39
7.32. READ SECURITY REGISTERS (48H)..................................................................................................................... 40
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Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.33. ENABLE RESET (66H) AND RESET (99H)............................................................................................................ 40
7.34. READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH)................................................................................. 41
8. ELECTRICAL CHARACTERISTICS ................................................................................................................... 46
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
POWER-ON TIMING....................................................................................................................................... 46
INITIAL DELIVERY STATE........................................................................................................................... 46
ABSOLUTE MAXIMUM RATINGS............................................................................................................... 46
CAPACITANCE MEASUREMENT CONDITIONS ....................................................................................... 47
DC CHARACTERISTICS................................................................................................................................. 48
AC CHARACTERISTICS................................................................................................................................. 49
9. ORDERING INFORMATION ................................................................................................................................. 52
9.1.
10.
VALID PART NUMBERS ...................................................................................................................................... 53
PACKAGE INFORMATION............................................................................................................................... 54
10.1. PACKAGE SOP8 208MIL ................................................................................................................................... 54
10.2. PACKAGE VSOP8 208MIL................................................................................................................................. 55
10.3. PACKAGE DIP8 300MIL .................................................................................................................................... 56
10.4. PACKAGE WSON8 (6*5MM).............................................................................................................................. 57
10.5. PACKAGE TFBGA-24BALL (6*4 BALL ARRAY)................................................................................................ 58
10.6. PACKAGE TFBGA-24BALL (5*5 BALL ARRAY)................................................................................................ 59
10.7. PACKAGE USON8 (3*3MM)............................................................................................................................... 60
10.8. PACKAGE USON8 (3*4MM)............................................................................................................................... 61
10.9. PACKAGE SOP8 150MIL ................................................................................................................................... 62
11.
REVISION HISTORY.......................................................................................................................................... 63
3
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
1. FEATURES
◆ 32M-bit Serial Flash
-4096K-byte
◆ Fast Program/Erase Speed
-Page Program time: 0.6ms typical
-Sector Erase time: 50ms typical
-Block Erase time: 0.15/0.25s typical
-Chip Erase time: 15s typical
-256 bytes per programmable page
◆ Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆ Flexible Architecture
-Uniform Sector of 4K-byte
-Uniform Block of 32/64K-byte
◆ High Speed Clock Frequency
-104MHz for fast read with 30PF load
-Dual I/O Data transfer up to 208Mbits/s
-Quad I/O Data transfer up to 416Mbits/s
◆ Low Power Consumption
-20mA maximum active current
-4uA maximum power down current
◆ Advanced Security Features(1)
◆ Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top/Bottom Block protection
-3*1024-Byte Security Registers With OTP Locks
-Discoverable parameters (SFDP) register
◆ Single Power Supply Voltage
◆
Minimum 100,000 Program/Erase Cycles
-Full voltage range: 2.1~3.6V
◆ Data Retention
◆ Package Information
-SOP8 (208mil)
-20-year data retention typical
-SOP8 (150mil)
◆ Allows XIP (execute in place) Operation
-VSOP8 (208mil)
-Continuous Read With 8/16/32/64-byte Wrap
-DIP8 (300mil)
-WSON8 (6*5mm)
-USON8 (3*3mm)
-USON8 (3*4mm)
-TFBGA24 (6*4 ball array)
-TFBGA24 (5*5 ball array)
Note: 1.Please contact GigaDevice for details.
4
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
2. GENERAL DESCRIPTION
The GD25VE32C (32M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 208Mbits/s and the Quad I/O & Quad output data is transferred with speed of 416Mbits/s.
CONNECTION DIAGRAM
CS#
SO
1
2
3
4
8
7
6
5
VCC
CS#
SO
1
2
8
7
6
5
VCC
HOLD#
SCLK
HOLD#
SCLK
Top View
Top View
WP#
VSS
WP# 3
SI
VSS
4
SI
8–LEAD SOP/VSOP/DIP
8–LEAD WSON/USON
Top View
Top View
5
NC
NC
NC
NC
NC
NC
NC
NC
4
3
2
1
4
WP#
NC
NC VCC
HOLD# NC
NC
VCC WP# HOLD# NC
3
VSS
NC
NC
SI
NC
NC
NC
NC
NC
NC
VSS NC
SI
2
1
SCLK CS# SO
SCLK CS#
SO
NC
A
NC
B
NC
NC
NC
E
NC
F
NC
B
NC
C
NC
D
NC
E
A
C
D
24-BALL TFBGA
(6x4 ball array)
24-BALL TFBGA
(5x5 ball array)
PIN DESCRIPTION
Pin Name
CS#
I/O
I
Description
Chip Select Input
SO (IO1)
WP# (IO2)
VSS
I/O
I/O
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
SI (IO0)
SCLK
I/O
I
Data Input (Data Input Output 0)
Serial Clock Input
HOLD# (IO3)
VCC
I/O
Hold Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
BLOCK DIAGRAM
Write Control
Logic
WP#(IO2)
Status
Register
Flash
Memory
High Voltage
Generators
HOLD#(IO3)
SCLK
SPI
Command &
Control Logic
Page Address
Latch/Counter
CS#
Column Decode And
256-Byte Page Buffer
SI(IO0)
SO(IO1)
Byte Address
Latch/Counter
6
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
3. MEMORY ORGANIZATION
GD25VE32C
Each device has
Each block has
Each sector has
Each page has
4M
16K
64/32K
256/128
16/8
4K
16
-
256
bytes
pages
sectors
blocks
-
-
-
1024
64/128
-
-
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25VE32C 64K Bytes Block Sector Architecture
Block
Sector
Address range
1023
……
1008
1007
……
992
……
……
……
……
……
……
47
3FF000H
……
3FFFFFH
……
63
3F0000H
3EF000H
……
3F0FFFH
3EFFFFH
……
62
……
……
2
3E0000H
……
3E0FFFH
……
……
……
……
……
……
……
……
……
……
……
02F000H
……
02FFFFH
……
……
32
020000H
01F000H
……
020FFFH
01FFFFH
……
31
1
……
16
010000H
00F000H
……
010FFFH
00FFFFH
……
15
0
……
0
000000H
000FFFH
7
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25VE32C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the
rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25VE32C supports Dual SPI operation when using the “Dual Output Fast Read” (3BH), “Dual I/O Fast Read”
(BBH) and “Read Manufacture ID/ Device ID Dual I/O” (92H) commands. These commands allow data to be transferred to
or from the device at twice the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become
bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25VE32C supports Quad SPI operation when using the “Quad Output Fast Read” (6BH), ”Quad I/O Fast
Read”(EBH), “Quad I/O Word Fast Read” (E7H), “Read Manufacture ID/ Device ID Quad I/O” (94H) and “Quad Page
Program” (32H) commands. These commands allow data to be transferred to or from the device at four times the rate of
the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and
WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status
Register to be set.
Hold
The HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated
data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure 1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
8
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
5. DATA PROTECTION
The GD25VE32C provide the following data protection methods:
◆
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
-Software reset (66H+99H)
◆
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory
array that can be read but not change.
◆
◆
Hardware Protection Mode: WP# goes low to protect the writable bits of Status Register.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command and reset command (66H+99H).
Table1.0 GD25VE32C Protected area size (CMP=0)
Status Register Content
Memory Content
Addresses
BP4
X
BP3
X
BP2
0
BP1
0
BP0
0
Blocks
NONE
Density
NONE
64KB
Portion
NONE
NONE
0
0
0
0
1
63
3F0000H-3FFFFFH
3E0000H-3FFFFFH
3C0000H-3FFFFFH
380000H-3FFFFFH
300000H-3FFFFFH
200000H-3FFFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-1FFFFFH
000000H-3FFFFFH
3FF000H-3FFFFFH
3FE000H-3FFFFFH
3FC000H-3FFFFFH
3F8000H-3FFFFFH
3F8000H-3FFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
0
0
0
1
0
62 to 63
60 to 63
56 to 63
48 to 63
32 to 63
128KB
256KB
512KB
1MB
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
2MB
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
X
0
0 to 1
0 to 3
0 to 7
0 to 15
0 to 31
0 to 63
63
64KB
128KB
256KB
512KB
1MB
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
2MB
4MB
4KB
Top Block
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
63
8KB
63
16KB
32KB
32KB
4KB
63
63
0
0
8KB
0
16KB
32KB
0
9
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
1
1
1
1
0
0
000000H-007FFFH
32KB
Bottom Block
Table1.1 GD25VE32C Protected area size (CMP=1)
Memory Content
Status Register Content
BP4
X
BP3
X
BP2
0
BP1
0
BP0
0
Blocks
ALL
Addresses
Density
4MB
Portion
ALL
000000H-3FFFFFH
000000H-3EFFFFH
000000H-3DFFFFH
000000H-3BFFFFH
000000H-37FFFFH
000000H-2FFFFFH
000000H-1FFFFFH
0
0
0
0
1
0 to 62
0 to 61
0 to 59
0 to 55
0 to 47
0 to 31
4032KB
3968KB
3840KB
3584KB
3MB
Lower 63/64
Lower 31/32
Lower 15/16
Lower 7/8
Lower 3/4
Lower 1/2
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
2MB
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
X
0
1 to 63
2 to 63
4 to 63
8 to 63
16 to 63
32 to 63
NONE
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
010000H-3FFFFFH
020000H-3FFFFFH
040000H-3FFFFFH
080000H-3FFFFFH
100000H-3FFFFFH
200000H-3FFFFFH
NONE
4032KB
3968KB
3840KB
3584KB
3MB
Upper 63/64
Upper 31/32
Upper 15/16
Upper 7/8
Upper 3/4
Upper 1/2
NONE
2MB
NONE
000000H-3FEFFFH
000000H-3FDFFFH
000000H-3FBFFFH
000000H-3F7FFFH
000000H-3F7FFFH
001000H-3FFFFFH
002000H-3FFFFFH
004000H-3FFFFFH
008000H-3FFFFFH
008000H-3FFFFFH
4092KB
4088KB
4080KB
4064KB
4064KB
4092KB
4088KB
4080KB
4064KB
4064KB
L-1023/1024
L-511/512
L-255/256
L-127/128
L-127/128
U-1023/1024
U-511/512
U-255/256
U-127/128
U-127/128
10
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
6. STATUS REGISTER
S23
S22
S21
S20
S19
S18
S17
S16
Reserved
DRV1
DRV0
HPF
Reserved
Reserved
Reserved
Reserved
S15
S14
S13
LB3
S12
LB2
S11
LB1
S10
S9
S8
SUS1
CMP
SUS2
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set.
The Chip Erase (CE) command is executed, if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block
Protect (BP2, BP1, and BP0) bits are 1 and CMP=1.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1 SRP0 #WP
Status Register
Description
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
0
0
0
1
0
1
1
0
1
X
0
Software Protected
WP#=0, the Status Register locked and cannot be written
to.
Hardware Protected
Hardware Unprotected
Power Supply Lock-Down(1)(2)
One Time Program(2)
WP#=1, the Status Register is unlocked and can be written
to after a Write Enable command, WEL=1.
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot be
written to.
1
X
X
1
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
11
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
2. This feature is available on special order. (GD25VE32CxxSx) Please contact GigaDevice for details.
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD#
pins are tied directly to the power supply or ground)
LB3, LB2, LB1, bits.
The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the
write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are
unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time
Programmable, once they are set to 1, the Security Registers will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0
bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details.
The default setting is CMP=0.
SUS1, SUS2 bit
The SUS1 and SUS2 bit are read only bits in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the
SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Program/Erase Resume (7AH) command, software reset (66H+99H)
command as well as a power-down, power-up cycle.
HPF bit
The High Performance Flag (HPF) bit is read only bit, that indicates the status of High Performance Mode (HPM). When
HPF bit is set to 1, it means the device is in High Performance Mode, When HPF bit is set to 0 (default), it means the device
is not in High Performance Mode.
DRV1, DRV0 bits
The DRV1&DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1,DRV0
Driver Strength
100%
00
01
10
11
75% (default)
50%
25%
12
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, with
most significant bit first on SI, and each bit is latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might
be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command
sequence has been completed. For the commands of Read, Fast Read, Read Status Register or Release from Deep Power-
Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high
after any bit of the data-out sequence is being shifted out.
For the commands of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command
is rejected, and is not executed. That means CS# must be driven high when the number of clock pulses after CS# being
driven low is an exact multiple of eight. For Page Program, if CS# is driven high at any time the input byte is not a full byte,
nothing will happen and WEL will not be reset.
Table2. Commands (Standard/Dual/Quad SPI)
Command Name
Byte 1 Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
Write Enable
06H
04H
50H
Write Disable
Volatile SR
Write Enable
Read Status Register-
1
05H
35H
15H
(S7-S0)
(continuous)
(continuous)
(continuous)
Read Status Register-
2
(S15-S8)
(S23-S16)
Read Status Register-
3
Write Status Register-1 01H
Write Status Register-2 31H
Write Status Register-3 11H
S7-S0
S15-S8
S23-S16
A23-A16
Read Data
03H
A15-A8
A7-A0
(D7-D0)
(Next
(continuous)
byte)
Fast Read
Dual Output
Fast Read
Dual I/O
Fast Read
Quad Output
Fast Read
Quad I/O
Fast Read
Quad I/O Word
Fast Read(7)
Page Program
0BH
3BH
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
dummy
dummy
(D7-D0)
(D7-D0)(1)
(continuous)
(continuous)
BBH
6BH
EBH
E7H
A23-A8(2)
A23-A16
A7-A0
M7-M0(2)
(D7-D0)(1) (Next
byte)
(Next
byte)
(D7-D0)(3)
(continuous)
(continuous)
(continuous)
(continuous)
A15-A8
A7-A0
dummy
A23-A0
M7-M0(4)
dummy(5)
dummy(6)
(D7-D0)(3) (Next
byte)
(D7-D0)(3) (Next
(Next
byte)
A23-A0
(Next
byte)
M7-M0(4)
A23-A16
byte)
02H
32H
F2H
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
D7-D0
D7-D0(3)
D7-D0
Next byte
continuous
continuous
continuous
Quad Page Program
Fast Page Program
A23-A16
A23-A16
Next byte
Next byte
Sector Erase
20H
52H
D8H
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
Block Erase(32K)
Block Erase(64K)
13
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
Chip Erase
C7/60
H
Enable Reset
Reset
66H
99H
Set Burst with Wrap
77H
75H
7AH
ABH
dummy(9)
W7-W0
Program/Erase
Suspend
Program/Erase
Resume
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
dummy
dummy
dummy
dummy
(DID7-
DID0)
(continuous)
ABH
Deep Power-Down
Manufacturer/
Device ID
B9H
90H
dummy
A23-A8
00H
(MID7-
MID0)
(DID7-
DID0)
(continuous)
(continuous)
Manufacturer/
Device ID by Dual I/O
(MID7-
MID0)
(DID7-
DID0)
A7-A0,
M7-M0
92H
Manufacturer/
Device ID by Quad I/O
dummy
(10) (MID7-
MID0)
(DID7-
DID0)
A23-A0,
M7-M0
94H
9FH
(continuous)
(continuous)
Read Identification
(MID7-
MID0)
(JDID15-
JDID8)
(JDID7-
JDID0)
High Performance
Mode
dummy
dummy
dummy
A3H
5AH
Read Serial Flash
Discoverable
Parameter
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
(continuous)
Erase Security
Registers(8)
44H
42H
48H
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
Program Security
Registers(8)
D7-D0
D7-D0
continuous
Read Security
Registers(8)
dummy
(D7-D0)
(continuous)
NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
IO1 = A23, A21, A19, A17, A15, A13, A11, A9
A6, A4, A2, A0, M6, M4, M2, M0
A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
4. Quad Input Address
14
Uniform Sector
Dual and Quad Serial Flash
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
GD25VE32C
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
8. Security Registers Address:
Security Register1: A23-A16=00H, A15-A10=000100b, A9-A0=Byte Address;
Security Register2: A23-A16=00H, A15-A10=001000b, A9-A0=Byte Address;
Security Register3: A23-A16=00H, A15-A10=001100b, A9-A0=Byte Address.
9. Dummy bits and Wrap Bits
IO0 = (x, x, x, x, x, x, W4,x)
IO1 = (x, x, x, x, x, x, W5, x)
IO2 = (x, x, x, x, x, x, W6, x)
IO3 = (x, x, x, x, x, x, x, x)
10. Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …)
IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1, …)
IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2, …)
IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3, …)
Table of ID Definitions:
GD25VE32C
Operation Code
9FH
MID7-MID0
ID15-ID8
ID7-ID0
16
C8
C8
42
90H/92H/94H
ABH
15
15
15
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)
bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status
Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS#
goes low sending the Write Enable command CS# goes high.
Figure 2. Write Enable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
06H
High-Z
SO
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:
CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-
up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase,
Erase/Program Security Registers and Reset commands.
Figure 3. Write Disable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
04H
High-Z
SO
7.3. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the
system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or
affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command
must be issued prior to a Write Status Register command, and any other commands can't be inserted between them.
Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command
will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status
Register bit values.
16
Uniform Sector
Dual and Quad Serial Flash
Figure 4. Write Enable for Volatile Status Register Sequence Diagram
GD25VE32C
CS#
SCLK
0
1
2
3
4
5
6
7
Command(50H)
High-Z
SI
SO
7.4. Read Status Register (RDSR) (05H or 35H or 15H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress,
it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Status Register continuously. For command code “05H” / “35H” / “15H”, the SO will output Status Register bits
S7~S0 / S15-S8 / S16-S23.
Figure 5. Read Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
Command
05H or 35H or 15H
Register0/1/2
Register0/1/2
SO
High-Z
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
7.5. Write Status Register (WRSR) (01H or 31H or 11H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S23, S20, S19, S18, S17, S16, S15, S10, S1 and
S0 of the Status Register. CS# must be driven high after the eighth bit of the data byte has been latched in. If not, the Write
Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register
cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed
Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is
reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write
Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits
17
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect
(WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is
not executed once the Hardware Protected Mode is entered.
Figure 6. Write Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register in
SCLK
Command
01H/31H/11H
SI
7
6
5
4
3
2 1 0
MSB
High-Z
SO
7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the
rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max
frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 7. Read Data Bytes Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Command
03H
24-bit address
23 22 21
MSB
3
2
1
0
Data Out1
Data Out2
High-Z
SO
7
6
5
4
3
2
1
0
MSB
18
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at
that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first
byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte
of data is shifted out.
Figure 8. Read Data Bytes at Higher Speed Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
0BH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
7.8. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is
latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure 9. The first byte addressed can be at any location. The address
is automatically incremented to the next higher address after each byte of data is shifted out.
Figure 9. Dual Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
3BH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
SI
6
4
2
0
6
4
2
0
6
7
Data Out1
Data Out2
SO
7
5
3
1
7
5
3
1
MSB
MSB
19
Uniform Sector
Dual and Quad Serial Flash
7.9. Quad Output Fast Read (6BH)
GD25VE32C
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is
latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
and IO0. The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit
(QE) of Status Register (S9) must be set to enable for the Quad Output Fast Read command.
Figure 10. Quad Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
6BH
24-bit address
23 22 21
SI(IO0)
3
2
1
0
SO(IO1)
High-Z
High-Z
High-Z
WP#(IO2)
HOLD#(IO3)
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Byte1 Byte2 Byte3 Byte4
7.10. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input
the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, and each bit is latched in on
the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command
sequence is shown in followed Figure11. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-4) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Dual
I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command
sequence is shown in followed Figure12. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command
requires the command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used
to reset (M5-4) before issuing normal command.
20
Uniform Sector
Dual and Quad Serial Flash
Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4≠ (1, 0))
GD25VE32C
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
BBH
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
SO(IO1)
7
Dummy
M7-4
A23-16
A15-8
A7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
Figure 12. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
6
4
2
0
6
4
2
0
6
4
5
2
3
0
1
6
7
4
5
7
5
3
1
7
5
3
1
7
A23-16
A15-8
A7-0
M7-4
Dummy
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
21
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.11. Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the
3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, and
each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,
IO1, IO2, IO3. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit
(QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next
Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The
command sequence is shown in followed Figure14. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the
next command requires the command code, thus returning to normal operation. A “Continuous Read Mode” Reset command
can be used to reset (M5-4) before issuing normal command.
Figure 13. Quad I/O Fast Read Sequence Diagram (M5-4≠ (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
EBH
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Figure 14. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
SO(IO1)
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
22
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with
Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap
Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited
to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command,
once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary
automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache
afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap”
command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation
while W6-W5 is used to specify the length of the wrap around section within a page.
7.12. Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest
address bit (A0) must be equal 0 and there are only 2-dummy clocks. The command sequence is shown in followed Figure15.
The first byte addressed can be at any location. The address is automatically incremented to the next higher address after
each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O
Word Fast read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then
the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command
code. The command sequence is shown in followed Figure16. If the “Continuous Read Mode” bits (M5-4) do not equal to
(1, 0), the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read
Mode” Reset command can be used to reset (M5-4) before issuing normal command.
Figure 15. Quad I/O Word Fast Read Sequence Diagram (M5-4≠ (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
E7H
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
Dummy
A23-16 A15-8 A7-0 M7-0
Byte1 Byte2 Byte3
23
Uniform Sector
Dual and Quad Serial Flash
Figure 16. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))
GD25VE32C
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
WP#(IO2)
HOLD#(IO3)
Dummy
A23-16 A15-8 A7-0 M7-0
Byte1 Byte2 Byte3
Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst
with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap
Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be limited
to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command,
once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary
automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache
afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap”
command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation
while W6-W5 is used to specify the length of the wrap around section within a page.
24
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.13. Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read”
command to access a fixed length of 8/16/32/64-byte section within a 256-byte page.
The Set Burst with Wrap command sequence: CS# goes low Send Set Burst with Wrap command Send 24
dummy bits Send 8 bits “Wrap bits” CS# goes high.
W4=0
W4=1 (default)
W6,W5
Wrap Around
Wrap Length
8-byte
Wrap Around
Wrap Length
0, 0
0, 1
1, 0
1, 1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
16-byte
32-byte
64-byte
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O
Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the
“Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set
W4=1.
Figure 17. Set Burst with Wrap Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
77H
SI(IO0)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
5
6
x
x
x
x
x
SO(IO1)
x
x
x
WP#(IO2)
HOLD#(IO3)
W6-W4
25
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.14. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address
bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data
that goes beyond the end of the current page are programmed from the start address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The
Page Program command sequence: CS# goes low sending Page Program command 3-byte address on SI at least
1 byte data on SI CS# goes high. The command sequence is shown in Figure18. If more than 256 bytes are sent to the
device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within
the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses
without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data
byte has been latched in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and
BP0) is not executed.
Figure 18. Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Command
02H
24-bit address
23 22 21
MSB
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
26
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.15. Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use
Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The
quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes
and at least one data byte on IO pins.
The command sequence is shown in Figure19. If more than 256 bytes are sent to the device, previously latched data
are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than
256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on
the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in;
otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the
Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) is not executed.
Figure 19.Quad Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
32H
24-bit address
23 22 21
MSB
Byte1 Byte2
SI(IO0)
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Byte11Byte12
SCLK
Byte253
Byte256
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
27
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.16. Fast Page Program (FPP) (F2H)
The Fast Page Program (FPP) command is used to program the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Fast Page Program (FPP) command is entered by driving CS# Low, followed by the command code, three
address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted
data that goes beyond the end of the current page are programmed from the start address of the same page (from the
address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence.
The Page Program command sequence: CS# goes low sending Page Program command 3-byte address on SI
at least 1 byte data on SI CS# goes high.
The command sequence is shown in Figure20. If more than 256 bytes are sent to the device, previously latched data
are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than
256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on
the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in;
otherwise the Fast Page Program (FPP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Fast Page Program (FPP) command is not executed when it is applied to a page protected by the Block Protect
(BP4, BP3, BP2, BP1, BP0).
Figure 20. Fast Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Command
F2H
24-bit address
23 22 21
MSB
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
28
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.17. Sector Erase (SE) (20H)
The Sector Erase (SE) command is used to erase all the data of the chosen sector. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered
by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-byte address on SI
CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the
Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected
by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit (see Table1&1a) is not executed.
Figure 21. Sector Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
20H
24 Bits Address
23 22
MSB
2
1
0
7.18. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside
the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the
sequence.
The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-byte address
on SI CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the
last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure 22. 32KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
52H
24 Bits Address
23 22
2
1
0
MSB
29
Uniform Sector
Dual and Quad Serial Flash
7.19. 64KB Block Erase (BE) (D8H)
GD25VE32C
The 64KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside
the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the
sequence.
The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command 3-byte address
on SI CS# goes high. The command sequence is shown in Figure23. CS# must be driven high after the eighth bit of the
last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure 23. 64KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
D8H
24 Bits Address
23 22
MSB
2
1
0
7.20. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is used to erase all the data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving
CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the
sequence.
The Chip Erase command sequence: CS# goes low sending Chip Erase command CS# goes high. The
command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been
latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and
is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block
Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip Erase (CE) command is ignored if one or more sectors are
protected.
Figure 24. Chip Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60H or C7H
30
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.21. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode
(the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the
device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the
Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP)
command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI) command or software reset command. The Release from Deep Power-Down
and Read Device ID (RDI) command releases the device from Deep Power-Down mode , also allows the Device ID of the
device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after Power-
Up.
The Deep Power-Down command sequence: CS# goes low sending Deep Power-Down command CS# goes
high. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the command code has
been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires
a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-
Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure 25. Deep Power-Down Sequence Diagram
CS#
tDP
0
1 2 3 4 5 6 7
SCLK
SI
Command
B9H
Stand-by mode Deep Power-down mode
31
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.22. Release from Deep Power-Down or High Performance Mode and Read
Device ID (RDI) (ABH)
TheReleasefromPower-Down or High Performance Mode/Device IDcommandisamulti-purpose command. It can be
used to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic
identification (ID) number.
To release the device from the Power-Down state or High Performance Mode, the command is issued by driving the
CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure26. Release from Power-Down
will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other
command are accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the
CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure27. The Device ID value for the
GD25VE32C is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The
command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same
as previously described, and shown in Figure27, except that after CS# is driven high it must remain high for a time
duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other
command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or
Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure 26. Release Power-Down Sequence or High Performance Mode Sequence Diagram
CS#
tRES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
ABH
Deep Power-down mode
Stand-by mode
Figure 27. Release Power-Down/Read Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
tRES2
Command
ABH
3 Dummy Bytes
23 22
MSB
SI
2
1
0
Device ID
SO
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode Stand-by Mode
32
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.23. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command
that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure28. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure 28. Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
24-bit address
23 22 21
SI
90H
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Device ID
Manufacturer ID
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
33
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.24. Dual I/O Read Manufacture ID/ Device ID (92H)
The Dual I/O Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure29. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure 29. Dual I/O Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
92H
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
7
A23-16
A15-8
A7-0
M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
MFR ID
(Repeat)
MFR ID
Device ID
Device ID
(Repeat)
MFR ID
(Repeat)
Device ID
(Repeat)
34
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.25. Quad I/O Read Manufacture ID/ Device ID (94H)
The Quad I/O Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.
The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address
(A23-A0) of 000000H , and 4 dummy clocks. After which, the Manufacturer ID and the Device ID are shifted out on the
falling edge of SCLK with most significant bit (MSB) first as shown in Figure30. If the 24-bit address is initially set to 000001H,
the Device ID will be read first.
Figure 30. Quad I/O Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
94H
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
MFR ID DID
A23-16 A15-8 A7-0 M7-0
Dummy
CS#
24 25 26 27 28 29 30 31
SCLK
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
MFR ID DID
MFR ID DID
(Repeat()Repeat)
(Repeat()Repeat)
35
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.26. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes
of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the
device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is
followed by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock.
The command sequence is shown in Figure31. The Read Identification (RDID) command is terminated by driving CS# high
at any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode,
the device waits to be selected, so that it can receive, decode and execute commands.
Figure 31. Read Identification ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
9FH
Command
Manufacturer ID
7
6
5
4
3
2
1
0
SO
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Memory Type
JDID15-JDID8
Capacity
JDID7-JDID0
MSB
MSB
36
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.27. High Performance Mode (HPM) (A3H)
The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when
operating at high frequencies (see fC3 in AC Electrical Characteristics). This command allows pre-charging of internal
charge pumps so the voltages required for accessing the flash memory array are readily available. The command
sequence: CS# goes lowSending A3H command Sending 3-dummy byteCS# goes high. See Figure32. After
the HPM command is executed, the device will maintain a slightly higher standby current (Icc9) than standard SPI
operation. The Release from Power-Down or HPM command (ABH) can be used to return to standard SPI standby
current (Icc1). In addition, Power-Down command (B9H) will also release the device from HPM mode back to standard
SPI standby state.
Figure 32. High Performance Mode Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
t HPM
Command
A3H
3 Dummy Bytes
23 22
MSB
SI
2
1
0
SO
High Performance Mode
7.28. Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Status Register command (01H/31H/11H) and
Erase/Program Security Registers command (44H,42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page
Program command (02H / 32H) are not allowed during Program suspend. The Write Status Register command
(01H/31H/11H) and Erase Security Registers command (44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not
allowed during Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase
operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status
Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the
SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be
cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend.
A power-off during the suspend period will reset the device and release the suspend state. The command sequence is show
below.
37
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
Figure 33. Program/Erase Suspend Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
tSUS
Command
75H
High-Z
SO
Accept read command
7.29. Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after
a Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the
SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared
from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase
operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a
Program/Erase Suspend is active. The command sequence is show in Figure35.
Figure 34. Program/Erase Resume Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
7AH
SO
Resume Erase/Program
7.30. Erase Security Registers (44H)
The GD25VE32C provides three 1024-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information separately from
the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low sending Erase Security Registers command
3-byte address on SI CS# goes high. The command sequence is shown in Figure36. CS# must be driven high after the
eighth bit of the last address byte has been latched in; otherwise the Erase Security Registers command is not executed.
As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the
Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress
(WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security
Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set
to 1, the Security Registers will be permanently locked; the Erase Security Register command will be ignored.
38
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
Address
A23-16
A15-12
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
00H
0 0 0 1
0 0 1 0
0 0 1 1
Byte Address
Byte Address
Byte Address
00H
0 0
00H
0 0
Figure 35. Erase Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
44H
24 Bits Address
23 22
MSB
SI
2
1
0
7.31. Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. Each security register contains
four pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch
(WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered
by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon
as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Register will be permanently locked. Program
Security Registers command will be ignored.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
0 0
00H
0 0
Figure 36. Program Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
42H
24-bit address
23 22 21
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 1024
Data Byte 2
Data Byte 3
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
39
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
7.32. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte
address (A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at
that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first
byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte
of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the
command is completed by driving CS# high.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
0 0
00H
0 0
Figure 37. Read Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
48H
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
7.33. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its
default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch
status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting (M7-
M0) and Wrap Bit Setting (W6-W4).
The “Reset (99H)” command sequence as follow: CS# goes low Sending Enable Reset command CS# goes
high CS# goes low Sending Reset command CS# goes high. Once the Reset command is accepted by the device,
the device will take approximately tRST_E / tRST to reset. During this period, no command will be accepted. Data corruption
may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is
accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the
Reset command sequence.
40
Uniform Sector
Dual and Quad Serial Flash
Figure 38. Enable Reset and Reset command Sequence Diagram
GD25VE32C
CS#
SCLK
SI
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6 7
Command
66H
Command
99H
High-Z
SO
7.34. Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can
be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard
of JEDEC Standard No.216.
Figure 39. Read Serial Flash Discoverable Parameter command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
5AH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
41
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
Table3. Signature and Parameter Identification Data Values
Description
Comment
Add(H)
(Byte)
DW Add
(Bit)
Data
Data
SFDP Signature
Fixed:50444653H
00H
01H
02H
03H
04H
05H
06H
07H
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
53H
46H
44H
50H
00H
01H
01H
FFH
53H
46H
44H
50H
00H
01H
01H
FFH
SFDP Minor Revision Number
SFDP Major Revision Number
Start from 00H
Start from 01H
Number of Parameters Headers Start from 00H
Unused
Contains 0xFFH and can never
be changed
ID number (JEDEC)
00H: It indicates a JEDEC
specified header
08H
09H
0AH
0BH
07:00
15:08
23:16
31:24
00H
00H
01H
09H
00H
00H
01H
09H
Parameter Table Minor
Revision Number
Start from 0x00H
Parameter Table Major
Revision Number
Start from 0x01H
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
0CH
0DH
0EH
0FH
07:00
15:08
23:16
31:24
30H
00H
00H
FFH
30H
00H
00H
FFH
Unused
Contains 0xFFH and can never
be changed
ID Number
It is indicates GigaDevice
manufacturer ID
10H
11H
12H
13H
07:00
15:08
23:16
31:24
C8H
00H
01H
03H
C8H
00H
01H
03H
(GigaDevice Manufacturer ID)
Parameter Table Minor
Revision Number
Start from 0x00H
Parameter Table Major
Revision Number
Start from 0x01H
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
Parameter Table Pointer (PTP)
First address of GigaDevice
Flash Parameter table
14H
15H
16H
17H
07:00
15:08
23:16
31:24
60H
00H
00H
FFH
60H
00H
00H
FFH
Unused
Contains 0xFFH and can never
be changed
42
Uniform Sector
Dual and Quad Serial Flash
Table4. Parameter Table (0): JEDEC Flash Parameter Tables
GD25VE32C
Description
Comment
Add(H)
(Byte)
DW Add
(Bit)
Data
Data
00: Reserved; 01: 4KB erase;
10: Reserved;
Block/Sector Erase Size
01:00
02
01b
1b
11: not support 4KB erase
0: 1Byte, 1: 64Byte or larger
Write Granularity
Write Enable Instruction
Requested for Writing to
Volatile
0: Nonvolatile status bit
1: Volatile status bit
03
0b
(BP status register bit)
30H
E5H
Status Registers
0: Use 50H Op code,
Write Enable Op code Select for 1: Use 06H Op code,
Writing to Volatile Status
Registers
Note: If target flash status register
04
0b
is Nonvolatile, then bits 3 and 4
must be set to 00b.
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Op code
31H
32H
15:08
16
20H
1b
20H
F1H
FFH
(1-1-2) Fast Read
0=Not support, 1=Support
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
clocking
18:17
19
00b
0b
0=Not support, 1=Support
(1-2-2) Fast Read
0=Not support, 1=Support
0=Not support, 1=Support
0=Not support, 1=Support
20
21
1b
1b
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
22
1b
23
1b
Unused
33H
31:24
31:00
FFH
Flash Memory Density
(1-4-4) Fast Read Number of
Wait states
37H:34H
01FFFFFFH
0 0000b: Wait states (Dummy
Clocks) not support
04:00
00100b
38H
39H
3AH
3BH
44H
EBH
08H
6BH
(1-4-4) Fast Read Number of
Mode Bits
000b:Mode Bits not support
07:05
15:08
20:16
010b
EBH
(1-4-4) Fast Read Op code
(1-1-4) Fast Read Number of
Wait states
0 0000b: Wait states (Dummy
Clocks) not support
01000b
(1-1-4) Fast Read Number of
Mode Bits
000b:Mode Bits not support
23:21
31:24
000b
6BH
(1-1-4) Fast Read Op code
43
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
Add(H)
(Byte)
DW Add
(Bit)
Description
Comment
Data
Data
(1-1-2) Fast Read Number of 0 0000b: Wait states (Dummy
04:00
01000b
Wait states
Clocks) not support
3CH
3DH
3EH
3FH
08H
3BH
42H
BBH
(1-1-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
07:05
15:08
20:16
000b
3BH
(1-1-2) Fast Read Op code
(1-2-2) Fast Read Number
of Wait states
0 0000b: Wait states (Dummy
Clocks) not support
00010b
(1-2-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
23:21
010b
(1-2-2) Fast Read Op code
31:24
00
BBH
0b
(2-2-2) Fast Read
Unused
0=not support 1=support
0=not support 1=support
03:01
04
111b
0b
40H
EEH
(4-4-4) Fast Read
Unused
07:05
31:08
15:00
111b
0xFFH
0xFFH
Unused
43H:41H
45H:44H
0xFFH
0xFFH
Unused
(2-2-2) Fast Read Number
of Wait states
0 0000b: Wait states (Dummy
Clocks) not support
20:16
23:21
00000b
000b
46H
00H
(2-2-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
(2-2-2) Fast Read Op code
47H
31:24
15:00
FFH
FFH
Unused
49H:48H
0xFFH
0xFFH
(4-4-4) Fast Read Number of 0 0000b: Wait states (Dummy
20:16
00000b
Wait states
Clocks) not support
4AH
00H
(4-4-4) Fast Read Number
of Mode Bits
000b: Mode Bits not support
23:21
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
000b
FFH
0CH
20H
0FH
52H
10H
D8H
00H
FFH
(4-4-4) Fast Read Op code
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
FFH
0CH
20H
0FH
52H
10H
D8H
00H
FFH
Sector/block size=2^N bytes
Sector Type 1 Size
0x00b: this sector type don’t exist
Sector Type 1 erase Op code
Sector Type 2 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 2 erase Op code
Sector Type 3 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 3 erase Op code
Sector Type 4 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 4 erase Op code
44
Uniform Sector
Dual and Quad Serial Flash
Table5. Parameter Table (1): GigaDevice Flash Parameter Tables
GD25VE32C
Add(H)
(Byte)
DW Add
(Bit)
Description
Comment
Data
Data
2000H=2.000V
Vcc Supply Maximum Voltage
2700H=2.700V
3600H=3.600V
1650H=1.650V
2100H=2.100V
2250H=2.250V
2350H=2.350V
2700H=2.700V
61H:60H
63H:62H
15:00
31:16
3600H
2100H
3600H
Vcc Supply Minimum Voltage
2100H
HW Reset# pin
HW Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
00
01
02
03
0b
1b
1b
Deep Power Down Mode
SW Reset
0=not support 1=support
Should be issue Reset
Enable(66H)
1b
1001
1001b
(99H)
1b
SW Reset Op code
65H:64H
11:04
F99EH
before Reset cmd.
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
12
13
14
15
0=not support 1=support
0=not support 1=support
1b
1b
1b
Wrap-Around Read mode
Wrap-Around Read mode Op
code
66H
67H
23:16
77H
77H
64H
08H:support
around read
16H:8B&16B
8B
wrap-
Wrap-Around Read data length
31:24
64H
32H:8B&16B&32B
64H:8B&16B&32B&64B
0=not support 1=support
Individual block lock
00
01
0b
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
Individual block lock Op code
Individual block lock Volatile
protect bit default protect status
Secured OTP
09:02
10
FFH
0b
0=protect 1=unprotect
EBFCH
6BH:68H
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
Read Lock
Permanent Lock
Unused
13
1b
15:14
31:16
11b
Unused
FFFFH
FFFFH
45
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
8. ELECTRICAL CHARACTERISTICS
8.1. POWER-ON TIMING
Figure 40. Power-on Timing Sequence Diagram
VCC
VCC(max.)
VCC(min.)
VPWD(max.)
Chip Selection is not allowed
tVSL
Full Device
Access
Allowed
tPWD
Time
Table6. Power-Up Timing and Write Inhibit Threshold
Symbol
tVSL
Parameter
Min.
5
Max.
Unit
ms
V
VCC (min.) to device operation
VWI
Write Inhibit Voltage
1.5
2.1
0.5
VPWD
tPWD
VCC voltage needed to below VPWD for ensuring initialization will occur
The minimum duration for ensuring initialization will occur
V
300
us
8.2. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register
bits are set to 0, except DRV0 bit (S21) is set to 1.
8.3. ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
℃
℃
V
Ambient Operating Temperature
Storage Temperature
-40 to 85
-65 to 150
Applied Input / Output Voltage
Transient Input / Output Voltage (note: overshoot)
VCC
-0.6 to VCC+0.4
-2.0 to VCC+2.0
-0.6 to 4.2
V
V
46
Uniform Sector
Dual and Quad Serial Flash
Figure 41. Maximum Negative/positive Overshoot Diagram
GD25VE32C
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
8.4. CAPACITANCE MEASUREMENT CONDITIONS
Symbol
CIN
Parameter
Min.
Typ.
Max.
Unit
Conditions
VIN=0V
Input Capacitance
6
8
pF
pF
pF
ns
V
COUT
CL
Output Capacitance
VOUT=0V
Load Capacitance
30
Input Rise And Fall time
Input Pulse Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Figure 42. Input Test Waveform and Measurement Level Diagram
Input timing reference level
0.7VCC
Output timing reference level
0.5VCC
0.8VCC
0.1VCC
AC Measurement Level
0.2VCC
Note: Input pulse rise and fall time are <5ns
47
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
8.5. DC CHARACTERISTICS
(T= -40℃~85℃, VCC=2.1~3.6V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
VIN=VCC or VSS
Deep Power-Down Current CS#=VCC,
VIN=VCC or VSS
1
5
μA
ICC2
0.1
4
μA
CLK=0.1VCC /
0.9VCC
15
13
20
mA
at 104MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /
0.9VCC
ICC3
Operating Current (Read)
Operating Current (PP)
18
mA
at 80MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
ICC8
ICC9
VIL
20
20
mA
mA
mA
mA
mA
mA
V
Operating Current (WRSR) CS#=VCC
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
High Performance Current
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
20
20
20
0.6
1.2
-0.5
0.2VCC
VCC+0.4
0.2
VIH
Input High Voltage
0.7VCC
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100μA
IOH =-100μA
V
VCC-0.2
V
48
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
8.6. AC CHARACTERISTICS
(T= -40℃~85℃, VCC=2.1~3.6V, CL=30pf)
Symbol
Parameter
Min.
Typ.
Max.
Unit.
Serial Clock Frequency For: Dual I/O (BBH), Quad I/O
(EBH), Quad Output (6BH) (Dual I/O & Quad I/O, without
High Performance Mode), on 2.7V-3.6V power supply
Serial Clock Frequency For: Dual I/O (BBH), Quad I/O
(EBH), Quad Output (6BH) (Dual I/O & Quad I/O, without
High Performance Mode), on 2.3V-2.7V power supply
Serial Clock Frequency For: Dual I/O (BBH), Quad I/O
(EBH), Quad Output (6BH) (Dual I/O & Quad I/O, without
High Performance Mode), on 2.1V-2.3V power supply
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O
(EBH), Quad Output (6BH) (Dual I/O & Quad I/O, with
High Performance Mode), on 2.1V-3.6V power supply
Serial Clock Frequency For: Read (03H)
Serial Clock High Time
FC
DC.
80
MHz
fC1
fC2
fC3
DC.
DC.
DC.
80
30
MHz
MHz
MHz
104
60
fR
DC.
4
MHz
ns
tCLH
tCLL
Serial Clock Low Time
4
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
tCLQV
tWHSL
tSHWL
tDP
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
0.1
0.1
5
V/ns
V/ns
ns
CS# Active Setup Time
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
CS# Not Active Hold Time
5
ns
CS# High Time (Read/Write)
20
ns
Output Disable Time
6
ns
Output Hold Time
1.2
2
ns
Data In Setup Time
ns
Data In Hold Time
2
ns
HOLD# Low Setup Time (Relative to Clock)
HOLD# High Setup Time (Relative to Clock)
HOLD# High Hold Time (Relative to Clock)
HOLD# Low Hold Time (Relative to Clock)
HOLD# Low To High-Z Output
5
ns
5
ns
5
ns
5
ns
6
6
7
ns
HOLD# High To Low-Z Output
ns
Clock Low To Output Valid
ns
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic Signature
Read
20
ns
100
ns
20
20
20
μs
tRES1
tRES2
μs
μs
CS# High To Standby Mode With Electronic Signature
49
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
Read
tSUS
tRST
CS# High To Next Command After Suspend
20
30
μs
μs
CS# High To Next Command After Reset (Except From
Erase)
tRST_E
tW
CS# High To Next Command After Reset (From Erase)
12
40
ms
ms
μs
μs
ms
ms
s
Write Status Register Cycle Time
Byte Program Time (First Byte)
Additional Byte Program Time (After First Byte)
Page Programming Time
5
tBP1
tBP2
tPP
30
50
2.5
0.6
50
12
2.4
tSE
Sector Erase Time (4K Bytes)
Block Erase Time (32K Bytes)
Block Erase Time (64K Bytes)
Chip Erase Time (GD25VE32C)
200/300(1)
0.8/1.6(2)
1.2/2.0(3)
30
tBE1
tBE2
tCE
0.15
0.25
15
s
s
Note:
1. Max Value 4KB tSE with<50K cycles is 200ms and >50K & <100k cycles is 300ms.
2. Max Value 32KB tBE with<50K cycles is 0.8s and >50K & <100k cycles is 1.6s.
3. Max Value 64KB tBE with<50K cycles is 1.2s and >50K & <100k cycles is 2.0s.
50
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
Figure 43. Serial Input Timing Diagram
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tCLCH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
SI
MSB
High-Z
LSB
SO
Figure 44. Output Timing Diagram
CS#
tCLH
tSHQZ
SCLK
tCLQV
tCLQV
tCLQX
tCLL
tCLQX
SO
SI
LSB
Least significant address bit (LIB) in
Figure 45. Hold Timing Diagram
CS#
tCHHL
tHLCH
tHHCH
tHHQX
SCLK
tCHHH
tHLQZ
SO
HOLD#
SI do not care during HOLD operation.
51
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
9. ORDERING INFORMATION
GD XX X XX X X X X X
Packing Type
T or no mark: Tube
Y:Tray
R:Tape & Reel
Green Code
G:Pb Free & Halogen Free Green Package
S: Pb Free & Halogen Free Green Package
&SRP1 Function
Temperature Range
I:Industrial(-40°C to +85°C)
M:Mobile(-40°C to +85°C)
Package Type
P: DIP8 300mil
S:SOP8 208mil
V:VSOP8 208mil
W: WSON8 (6*5mm)
Z:TFBGA24(6*4 Ball Array)
B:TFBGA24(5*5 Ball Array)
H: USON8 (3*3mm)
N: USON8 (3*4mm)
T: SOP8 150mil
Generation
C: C Version
Density
32: 32Mb
Series
VE:2.5V,4KB Uniform Sector
Product Family
25:SPI Interface Flash
52
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
9.1. Valid Part Numbers
Please contact Gigadevice regional sales for the latest product selection and available form factors.
Product Number
GD25VE32CPIG
GD25VE32CPIS
GD25VE32CTIG
GD25VE32CTIS
GD25VE32CSIG
GD25VE32CSIS
GD25VE32CVIG
GD25VE32CVIS
GD25VE32CWIG
GD25VE32CWIS
GD25VE32CHIG
GD25VE32CHIS
GD25VE32CNIG
GD25VE32CNIS
GD25VE32CZIG
GD25VE32CZIS
GD25VE32CBIG
GD25VE32CBIS
GD25VE32CPMG
GD25VE32CPMS
GD25VE32CTMG
GD25VE32CTMS
GD25VE32CSMG
GD25VE32CSMS
GD25VE32CVMG
GD25VE32CVMS
GD25VE32CWMG
GD25VE32CWMS
GD25VE32CHMG
GD25VE32CHMS
GD25VE32CNMG
GD25VE32CNMS
GD25VE32CZMG
GD25VE32CZMS
GD25VE32CBMG
GD25VE32CBMS
Density
32Mbit
Package Type
DIP8 300mil
Temperature
-40℃ to +85℃
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
SOP8 150mil
SOP8 208mil
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
-40℃ to +85℃
VSOP8 208mil
WSON8 (6*5mm)
USON8 (3*3mm)
USON8 (3*4mm)
TFBGA24 (6*4 Ball Array)
TFBGA24 (5*5 Ball Array)
DIP8 300mil
SOP8 150mil
SOP8 208mil
VSOP8 208mil
WSON8 (6*5mm)
USON8 (3*3mm)
USON8 (3*4mm)
TFBGA24 (6*4 Ball Array)
TFBGA24 (5*5 Ball Array)
53
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
10.PACKAGE INFORMATION
10.1. Package SOP8 208MIL
D
E
E1
L1
L
θ
“A”
b
Base Metal
A
A2
c
Detail “A”
A1
b
e
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
Min
-
-
0.05
0.15
0.25
1.70
1.80
1.90
0.31
0.41
0.51
0.15
0.20
0.25
5.13
5.23
5.33
7.70
7.90
8.10
5.18
5.28
5.38
0.50
-
0
-
mm Nom
Max
1.27
1.31
2.16
0.85
8
Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.
54
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
10.2. Package VSOP8 208MIL
θ
8
5
E1
E
L1
L
1
4
C
D
A2
A
A1
b
e
Seating plane
0.10
Dimensions
Symbol
A
A1
A2
b
D
E
E1
e
L
θ
Unit
Min
0.05
0.10
0.75
0.80
0.35
0.42
5.18
5.28
7.70
7.90
5.18
5.28
0.50
0.65
0
mm
Nom
Max
Min
1.27
1.00
0.04
0.15
0.85
0.48
5.38
8.10
5.38
0.80
10
0
0.002
0.004
0.006
0.030
0.032
0.034
0.014
0.016
0.020
0.204
0.206
0.210
0.303
0.311
0.319
0.204
0.206
0.210
0.020
0.026
0.031
Inch
Nom
Max
0.050
10
Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.
55
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
10.3. Package DIP8 300MIL
4
1
E
11°
E1
R0.005xDP0.020
11°
5°
C
eB
5
8
D
A2
L
A1
b
e
b1
Dimensions
Symbol
Unit
A1
A2
b
b1
C
D
E
E1
e
eB
L
Min
0.38
3.00
1.27
0.38
0.20
9.05
7.62
7.94
8.26
6.12
7.62
3.04
3.30
3.56
0.12
0.13
0.14
mm
Nom
Max
Min
0.72
3.25
1.46
0.46
0.28
9.32
6.38
2.54
8.49
1.05
3.50
1.65
0.54
0.34
9.59
6.64
9.35
0.015
0.028
0.041
0.118
0.128
0.138
0.05
0.015
0.018
0.021
0.008
0.011
0.014
0.356
0.367
0.378
0.300
0.313
0.326
0.242
0.252
0.262
0.333
0.345
0.357
Inch Nom
Max
0.058
0.065
0.1
Note：Both package length and width do not include mold flash.
56
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
10.4. Package WSON8 (6*5mm)
c
D
E
A1
A
Top View
Side View
L
b
e
E2
D2
Bottom View
Dimensions
Symbol
A
A1
c
b
D
D2
E
E2
e
L
Unit
Min
0.70
0.75
0.80
0.00
0.02
0.05
0.180
0.203
0.250
0.35
0.40
0.50
5.90
6.00
6.10
3.30
3.40
3.50
4.90
5.00
5.10
3.90
4.00
4.10
0.50
0.60
0.75
mm
Nom
Max
1.27
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These lead
shapes are compatible with each other.
57
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
10.5. Package TFBGA-24BALL (6*4 ball array)
1
2
3
4
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
e
SD
E1
E
SE
e
D
D1
Φb
Dimensions
Symbol
Unit
A
A1
A2
b
D
D1
E
E1
e
SE
SD
Min
0.25
0.30
0.35
0.40
5.95
6.00
6.05
3.00
BSC
7.95
8.00
8.05
5.00
BSC
1.00
BSC
0.50
TYP
0.50
TYP
mm Nom
Max
0.85
1.20
0.35
0.45
Min
0.010
0.014
0.234
0.236
0.238
0.118 0.313
0.197
BSC
0.039 0.020 0.020
BSC TYP TYP
BSC
Inch Nom
Max
0.012 0.033 0.016
0.047 0.014 0.018
0.315
0.317
Note：Both package length and width do not include mold flash.
58
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
10.6. Package TFBGA-24BALL (5*5 ball array)
5
1
2
3
4
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
e
E
E1
SE
e
D
Φb
D1
Dimensions
Symbol
Unit
A
A1
A2
b
D
D1
E
E1
e
SE
SD
Min
0.26
0.31
0.35
0.40
5.90
6.00
4.00
BSC
7.90
8.00
8.10
4.00
BSC
1.00
BSC
1.00
TYP
1.00
TYP
mm Nom
Max
0.85
1.20
0.36
0.45
6.10
Min
0.010
0.014
0.232
0.236
0.240
0.157 0.311
0.157
BSC
0.039 0.039 0.039
BSC TYP TYP
BSC
Inch Nom
Max
0.012 0.033 0.016
0.047 0.014 0.018
0.315
0.319
Note：Both package length and width do not include mold flash.
59
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
10.7. Package USON8 (3*3mm)
c
D
E
A1
A
Top View
Side View
L
0.45
e
b
E1
D1
Bottom View
Dimensions
Symbol
Unit
A
A1
c
b
D
D1
E
E1
e
L
Min
0.50
0.55
0.60
0.00
0.02
0.05
0.10
0.15
0.20
0.20
2.90
3.00
3.10
1.60
1.70
1.80
2.90
3.00
3.10
2.10
2.20
2.30
0.35
0.40
0.45
mm Nom
Max
0.25
0.30
0.50
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other.
60
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
10.8. Package USON8 (3*4mm)
c
D
E
A1
A
Top View
D1
Side View
L
b
E1
e
Bottom View
Dimensions
Symbol
Unit
A
A1
c
b
D
D1
E
E1
e
L
Min
0.50
0.55
0.60
0.00
0.02
0.05
0.10
0.15
0.20
0.25
0.30
0.35
2.90
3.00
3.10
0.10
0.20
0.30
3.90
4.00
4.10
0.70
0.80
0.90
0.50
0.60
0.70
mm
Nom
Max
0.80
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other.
61
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
10.9. Package SOP8 150MIL
D
E
E1
h
L1
L
“A”
θ
b
Base Metal
A2
A
c
Detail “A”
A1
b
e
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
h
θ
Min
-
-
0.10
0.15
0.25
1.25
1.45
1.55
0.31
0.41
0.51
0.10
0.20
0.25
4.80
4.90
5.00
5.80
6.00
6.20
3.80
3.90
4.00
0.40
-
0.25
-
0°
-
mm Nom
Max
1.27
1.04
1.75
0.90
0.50
8°
Note:
1. Both the package length and width include the mold flash.
2. Seating plane: Max. 0.1mm.
62
Uniform Sector
Dual and Quad Serial Flash
GD25VE32C
11. REVISION HISTORY
Version No
Description
Page
All
Date
1.0
Initial Release
2016-8-18
Modify the applying voltage of fc from 3.0-3.6V to 2.7-3.6V
Modify the applying voltage of fc1 from 2.7-3.0V to 2.3-2.7V
Modify the applying voltage of fc2 from 2.1-2.7V to 2.1-2.3V
Modify Icc9 from 400-800uA to 0.6-1.2mA
P49
P49
1.1
1.2
P49
2017-8-8
P48
Modify tw max. value from 30ms to 40ms
P50
Modify the description of the SOP8 USON8, WSON8 and
TFBGA24 (5x5 ball array) packages
P54, 57, 59,
60, 61, 62
P52
Add Packing Type: T or no mark: Tube
2017-12-4
Modify Icc2 max value from 1uA to 4uA
P48
Delete tRST_P and tRST_R
P50
Add tRST, of which the max value is 30us
P50
63
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