GD5F1GQ4RF9IH [GIGADEVICE]
SPI(x1/x2/x4) NAND Flash;型号: | GD5F1GQ4RF9IH |
厂家: | GigaDevice |
描述: | SPI(x1/x2/x4) NAND Flash |
文件: | 总49页 (文件大小:1622K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SPI(x1/x2/x4) NAND Flash
1G
GD5F1GQ4xFxxH
DATASHEET
1
SPI(x1/x2/x4) NAND Flash
Contents
1G
1
2
FEATURE...........................................................................................................................................................4
GENERAL DESCRIPTION...............................................................................................................................5
2.1 PRODUCT LIST ............................................................................................................................................................... 6
2.2 CONNECTION DIAGRAM .................................................................................................................................................. 7
2.3 PIN DESCRIPTION........................................................................................................................................................... 7
2.4 BLOCK DIAGRAM ........................................................................................................................................................... 8
3
4
5
ARRAY ORGANIZATION .................................................................................................................................9
MEMORY MAPPING.......................................................................................................................................10
DEVICE OPERATION.....................................................................................................................................11
5.1 SPI MODES ................................................................................................................................................................ 11
5.2 HOLD MODE ............................................................................................................................................................. 12
5.3 WRITE PROTECTION ..................................................................................................................................................... 12
5.4 POWER OFF TIMING..................................................................................................................................................... 12
6
7
COMMANDS DESCRIPTION.........................................................................................................................13
WRITE OPERATIONS ....................................................................................................................................14
7.1 WRITE ENABLE (WREN) (06H) ..................................................................................................................................... 14
7.2 WRITE DISABLE (WRDI) (04H) ..................................................................................................................................... 14
8
9
FEATURE OPERATIONS...............................................................................................................................15
8.1 GET FEATURES (0FH) AND SET FEATURES (1FH) ............................................................................................................... 15
READ OPERATIONS......................................................................................................................................17
9.1 PAGE READ................................................................................................................................................................. 17
9.2 PAGE READ TO CACHE (13H)......................................................................................................................................... 17
9.3 READ FROM CACHE (03H) ............................................................................................................................................ 18
9.4 FAST READ FROM CACHE (0BH)..................................................................................................................................... 18
9.5 READ FROM CACHE X2 (3BH)........................................................................................................................................ 19
9.6 READ FROM CACHE X4 (6BH)........................................................................................................................................ 19
9.7 READ FROM CACHE DUAL IO (BBH) ............................................................................................................................... 20
9.8 READ FROM CACHE QUAD IO (EBH)............................................................................................................................... 21
10
11
READ ID (9FH)............................................................................................................................................22
PROGRAM OPERATIONS.........................................................................................................................23
11.1 PAGE PROGRAM ........................................................................................................................................................ 23
11.2 PROGRAM LOAD (PL) (02H) ....................................................................................................................................... 24
11.3 PROGRAM LOAD X4 (PL X4) (32H)............................................................................................................................... 25
11.4 PROGRAM EXECUTE (PE) (10H)................................................................................................................................... 26
11.5 INTERNAL DATA MOVE ............................................................................................................................................... 27
11.6 PROGRAM LOAD RANDOM DATA (84H) ........................................................................................................................ 27
2
SPI(x1/x2/x4) NAND Flash
1G
11.7 PROGRAM LOAD RANDOM DATA X4 (C4H/34H)............................................................................................................ 28
ERASE OPERATIONS ...............................................................................................................................29
12.1 BLOCK ERASE (D8H) .................................................................................................................................................. 29
RESET OPERATIONS................................................................................................................................30
13.1 SOFT RESET (FFH) ..................................................................................................................................................... 30
ADVANCED FEATURES............................................................................................................................31
12
13
14
14.1 OTP REGION ............................................................................................................................................................ 31
14.2 BLOCK PROTECTION ................................................................................................................................................... 32
14.3 STATUS REGISTER AND DRIVER REGISTER........................................................................................................................ 33
14.4 ASSISTANT BAD BLOCK MANAGEMENT .......................................................................................................................... 34
14.5 INTERNAL ECC .......................................................................................................................................................... 35
15
16
17
18
19
20
21
22
23
POWER ON TIMING...................................................................................................................................36
ABSOLUTE MAXIMUM RATINGS............................................................................................................37
CAPACITANCE MEASUREMENT CONDITIONS....................................................................................38
DC CHARACTERISTIC..............................................................................................................................39
AC CHARACTERISTICS............................................................................................................................40
PERFORMANCE TIMING ..........................................................................................................................41
ORDERING INFORMATION ......................................................................................................................43
PACKAGE INFORMATION ........................................................................................................................44
REVISION HISTORY...................................................................................................................................48
3
SPI(x1/x2/x4) NAND Flash
1G
1
FEATURE
◆1Gb SLC NAND Flash
◆Program/Erase/Read Speed
- Page Program time: 400us typical
- Block Erase time: 3ms typical
◆Page Size
- 2048 bytes + 64 bytes
- Page read time: 80us maximum(w/I ECC)
◆Standard, Dual, Quad SPI
◆Reliability
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD#
- Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3
- Endurance: 100K program/erase cycles
- Data retention: 10 Years
◆Low Power Consumption
◆High Speed Clock Frequency
- 40mA maximum active current
- 90uA(1) maximum standby current
- 120MHz for fast read with 30PF load
- Quad I/O Data transfer up to 480Mbits/s
◆Enhanced access performance
- 2kbyte cache for fast random read
- Cache read and cache program
◆ Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Register protection with WP# Pin
- Top or Bottom, Block selection combination
◆Advanced Feature for NAND
- Internal ECC option, per 528bytes
- Internal data move by page with ECC
◆Advanced security Features
- 8K-Byte OTP Region (4 page OTP)
◆The first block(Block0) is guaranteed to be a valid block
◆Single Power Supply Voltage
at the time of shipment.
- Full voltage range for 1.8V: 1.7V ~ 2.0V
- Full voltage range for 3.3V: 2.7V ~ 3.6V
Note 1: When Temperature is 105℃, the maximum standby current is 200uA
4
SPI(x1/x2/x4) NAND Flash
2 GENERAL DESCRIPTION
1G
SPI (Serial Peripheral Interface) NAND Flash provides an ultra cost-effective while high density non-volatile memory
storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive
alternative to SPI-NOR and standard parallel NAND Flash, with advanced features:
• Total pin count is 8, including VCC and GND
• Density is 1Gbit
• Superior write performance and cost per bit over SPI-NOR
• Significant low cost than parallel NAND
This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the
same pin out from one density to another. The command sets resemble common SPI-NOR command sets, modified to
handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash
memory, with specified designed features to ease host management:
• User-selectable internal ECC. ECC code is generated internally during a page program operation. When a page
is read to the cache register, the ECC code is detect and correct the errors when necessary. The 64-bytes spare area
is available even when internal ECC enabled. The device outputs corrected data and returns an ECC error status.
• Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage
collection task, without need of shift in and out of data.
•Power on Read with internal ECC. The device will automatically read first page of fist block to cache after power
on, then host can directly read data from cache for easy boot. Also the data is promised correctly by internal ECC.
It is programmed and read in page-based operations, and erased in block-based operations. Data is transferred to or
from the NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest
to I/O control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as
a data buffer for the NAND Flash memory array operation. The cache register functions as the buffer memory to enable
page and random data READ/WRITE and copy back operations. These devices also use a SPI status register that reports
the status of device operation.
5
SPI(x1/x2/x4) NAND Flash
1G
2.1 Product List
Page Size
Product Number
GD5F1GQ4RFFIH
GD5F1GQ4RFFJH
GD5F1GQ4RFFFH
GD5F1GQ4RFZIH
GD5F1GQ4RFZJH
GD5F1GQ4RFZFH
GD5F1GQ4RF9IH
GD5F1GQ4RF9JH
GD5F1GQ4RF9FH
GD5F1GQ4UFYIH
GD5F1GQ4UFYJH
GD5F1GQ4UFYFH
GD5F1GQ4UFFIH
GD5F1GQ4UFFJH
GD5F1GQ4UFFFH
GD5F1GQ4UFZIH
GD5F1GQ4UFZJH
GD5F1GQ4UFZFH
Density
Voltage
Package Type
Temperature
-40℃ to 85℃
-40℃ to 105℃
-40℃ to 85℃
-40℃ to 85℃
-40℃ to 105℃
-40℃ to 85℃
-40℃ to 85℃
-40℃ to 105℃
-40℃ to 85℃
-40℃ to 85℃
-40℃ to 105℃
-40℃ to 85℃
-40℃ to 85℃
-40℃ to 105℃
-40℃ to 85℃
-40℃ to 85℃
-40℃ to 105℃
-40℃ to 85℃
SOP16 300mil
1.7V to 2.0V
TFBGA24(6*4 Ball Array)
LGA8(6*8mm)
1Gbit
2Kbyte + 64Byte
WSON8(8*6mm)
2.7V to 3.6V
SOP16 300mil
TFBGA24(6*4 Ball Array)
6
SPI(x1/x2/x4) NAND Flash
2.2 Connection Diagram
1G
CS#
SO
1
2
8
7
VCC
1
2
3
4
5
6
7
8
HOLD#
VCC
NC
16
15
14
13
12
11
10
9
SCLK
SI
HOLD#
Top View
NC
WP# 3
VSS
6 SCLK
5 SI
NC
NC
Top View
4
NC
NC
NC
CS#
SO
NC
8–LEAD WSON
VSS
WP#
16-LEAD SOP
Top View
4
3
2
1
HOLD#
SI
WP#
NC
NC VCC
NC
NC
VSS
NC
NC
NC
NC
NC
NC
SCLK CS# SO
NC
A
NC
B
NC
NC
NC
E
NC
F
C
D
24-BALL TFBGA
Figure2-1 Connection Diagram
2.3 Pin Description
Pin Name
CS#
I/O
Description
I
Chip Select input, active low
SO/SIO1
WP#/SIO2
VSS
I/O
Serial Data Output / Serial Data Input Output 1
I/O
Write Protect, active low / Serial Data Input Output 2
Ground
Ground
I/O
SI/SIO0
SCLK
Serial Data Input / Serial Data Input Output 0
Serial Clock input
I
HOLD#/SIO3
VCC
I/O
Hold input, active low / Serial Data Input Output3
Power Supply
Supply
7
SPI(x1/x2/x4) NAND Flash
1G
2.4 Block Diagram
Figure2-2 Block Diagram
WP#/
SIO2
HOLD#/
RESET#/
SIO3
SCLK SI/SIO0 SO/SIO1
CS#
Serial NAND controler
Vcc
Vss
NAND
memory
core
Cache
memory
ECC and status register
8
SPI(x1/x2/x4) NAND Flash
3 ARRAY ORGANIZATION
1G
Each device has
1G
Each block has
Each page has
128M+4M
1024 x 64
1024
128K+4K
2K+64
bytes
pages
blocks
64
-
-
-
Figure3-1. Array Organization
SO
SI
Cache Register
2048
64
64
2048
Data Register
1 page = (2K + 64 bytes)
1 block = (2K + 64 bytes) x 64 pages
= (128K + 4K) bytes
Per device:
1Gb: 1024Blocks
1 device:
For 1G: = (128K +4K) bytes x 1024 blocks
= 1Gb
1 block
9
SPI(x1/x2/x4) NAND Flash
4 MEMORY MAPPING
1G
<
6
7
1
8
2
15 >
Blocks
RA<15:6>
0
1023
Pages
RA<5:0>
0
1
63
Bytes
CA<11:0>
0
1
2
2111
Note:
1. CA: Column Address. The 12-bit address is capable of addressing from 0 to 4095 bytes; however, only bytes 0
through 2111 are valid. Bytes 2112 through 4095 of each page are “out of bounds,” do not exist in the device,
and cannot be addressed.
2. RA: Row Address. RA<5:0> selects a page inside a block, and RA<15:6> selects a block:
10
SPI(x1/x2/x4) NAND Flash
5 DEVICE OPERATION
1G
5.1 SPI Modes
SPI NAND supports two SPI modes:
• CPOL = 0, CPHA = 0 (Mode 0)
• CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All timing
diagrams shown in this data sheet are mode 0. See Figure5-1 for more details.
Figure5-1. SPI Modes Sequence Diagram
CPOL CPHA
0
0
SCLK
1
1
SCLK
SI
MSB
LSB
SO
CS#
MSB
LSB
Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3).
Standard SPI
SPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO).
Dual SPI
SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow
data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command
the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1.
Quad SPI
SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow
data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command
the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1, and WP# and HOLD# pins become SIO2 and SIO3.
11
SPI(x1/x2/x4) NAND Flash
1G
5.2 HOLD Mode
The HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated
data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low
(if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of
HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure5-2. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
5.3 Write Protection
SPI NAND provides Hardware Protection Mode besides the Software Mode. Write Protect (WP#) prevents the block lock
bits (BP0, BP1, BP2 and INV, CMP) from being over written. If the BRWD bit is set to 1 and WP# is LOW, the block protect
bits cannot be altered.
5.4 Power Off Timing
Please do not turn off the power before Write/Erase operation is complete. Avoid using the device when the battery is low.
Power shortage and/or power failure before Write/Erase operation is complete will cause loss of data and/or
damage to data.
12
SPI(x1/x2/x4) NAND Flash
6 COMMANDS DESCRIPTION
1G
Table6-1. Commands Set
Command Name
Write Enable
Byte 1
06H
Byte 2
Byte 3
Byte 4
Byte 5
Byte N
Write Disable
04H
Get Features
0FH
A7-A0
(D7-D0)
(D7-D0)
A15-A8
Wrap(9)
Set Feature
1FH
A7-A0
dummy(1)
A7-A0
A7-A 0(8)
Page Read (to cache)
Read From Cache
Fast Read From Cache
Read From Cache x 2
Read From Cache x 4
Read From Cache Dual IO
Read From Cache Quad IO
Read ID(5)
13H
A23-A16
03H
dummy(2) A15-A8
dummy(2) A15-A8
dummy(2) A15-A8
dummy(2) A15-A8
(D7-D0)
0BH
A7-A0
dummy(2)
dummy(2)
dummy(2)
(D7-D0)
3BH
A7-A0
(D7-D0)x2
(D7-D0)x4
6BH
A7-A0
BBH
EBH
9FH
A15-A0
A15-A0(4) (D7-D0)x4
dummy(3)
(D7-D0)x2
MID
DID
DID
Program Load
02H
A15-A8
A15-A8
A23-A16
A15-A8
A15-A8
A23-A16
A7-A0
A7-A0
A15-A8
A7-A0
A7-A0
A15-A8
(D7-D0)
(D7-D0)x4
A7-A0
Next byte
Next byte
Byte N
Byte N
Program Load x4
Program Execute
Program Load Random Data
Program Load Random Data x4
Block Erase(128K)
Reset(6)
32H
10H
84H(7)
C4H/34H(7)
D8H
FFH
(D7-D0)
(D7-D0)x4
A7-A0
Next byte
Next byte
Byte N
Byte N
Notes:
1. The dummy byte can be inputted or not.
2. The x8 clock = dummy<7:0>.
3. The x8 clock = dummy<7:0>, D7-D0.
4. The x8 clock = A15-A0, dummy<7:0>, D7-D0.
5. MID is Manufacture ID (C8h for GigaDevice), DID is Device ID.
6. Reset command:
• During busy, Reset will reset PAGE READ/PROGRAM/ERASE operation.
• During idle, Reset will reset status register bits P_FAIL/E_FAIL/ECCS bits.
7. Those commands are only available in Internal Data Move operation.
8. A0 need be 0 for the 03H command.
9. The output would be updated by real-time, until CS# is driven high.
13
SPI(x1/x2/x4) NAND Flash
7 WRITE OPERATIONS
1G
7.1 Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit
must be set prior to following operations that change the contents of the memory array:
• Page program
• OTP program/OTP protection
• Block erase
The WEL bit can be cleared after a reset command.
Figure7-1. Write Enable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
06H
High-Z
SO
7.2 Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is also reset by following
condition:
• Page program
• OTP program/OTP protection
• Block erase
Figure7-2. Write Disable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
04H
High-Z
SO
14
SPI(x1/x2/x4) NAND Flash
8 FEATURE OPERATIONS
1G
8.1 Get Features (0FH) and Set Features (1FH)
The GET FEATURES (0FH) and SET FEATURES (1FH) commands are used to monitor the device status and alter the
device behavior. These commands use a 1-byte feature address to determine which feature is to be read or modified.
Features such as OTP and block locking can be enabled or disabled by setting specific feature bits (shown in the following
table). The status register is mostly read, except WEL, which is a writable bit with the WRITE ENABLE (06H) command.
When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise
specified in the following table, once the device is set, it remains set, even if a RESET (FFH) command is issued.
Table8-1. Features Settings
Register Addr.
Protection A0H
Feature B0H
7
6
5
4
3
2
1
0
BRWD
Reserved
BP2
BP1
BP0
INV
CMP
Reserved
QE
OTP_PRT
Reserved
Reserved
OTP_EN Reserved ECC_EN Reserved Reserved Reserved
ECCS2 ECCS1 ECCS0 P_FAIL E_FAIL WEL
DS_IO[1] DS_IO[0] Reserved Reserved Reserved Reserved
Status
C0H
OIP
Feature D0H
Reserved
Note: If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed.
If QE is enabled, the quad IO operations can be executed.
All the reserved bits must be held low when the feature is set.
00h is the default data byte value for Output Driver Register after power-up.
These registers are write/read type, except for Register of Status (C0H) is read only.
Figure8-2. Get Features Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1 byte address
SCLK
SI
Command
0FH
7
6
5
4
3
2
1
0
Data byte
MSB
SO
High-Z
7
6
5
4
3
2
1
0
MSB
Note: The output would be updated by real-time, until CS# is driven high.
15
SPI(x1/x2/x4) NAND Flash
1G
The set features command supports a dummy byte mode after the data byte as well. The features in the feature byte B0H
are all volatile except OTP_PRT bit.
Figure8-3. Set Features Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
SI
Data byte
Command
1FH
1 byte address
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
SO
High-Z
16
SPI(x1/x2/x4) NAND Flash
9 READ OPERATIONS
1G
9.1 Page Read
The PAGE READ (13H) command transfers the data from the NAND Flash array to the cache register. The command
sequence is as follows:
• 13H (PAGE READ to cache)
• 0FH (GET FEATURES command to read the status)
• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH (Read from cache
dual IO)/EBH (Read from cache quad IO)
The PAGE READ command requires a 24-bit address. After the block/page addresses are registered, the device starts
the transfer from the main array to the cache register, and is busy for tRD time. During this time, the GET FEATURE (0FH)
command can be issued to monitor the status. Followed the page read operation, the RANDOM DATAREAD
(03H/0BH/3BH/6BH/BBH/EBH) command must be issued in order to read out the data from cache. The output data starts
at the initial address specified in the command, and will continue until CS# is pulled high to terminate this operation.
Refer waveforms to view the entire READ operation.
9.2 Page Read to Cache (13H)
Figure9-1.Page Read to cache Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
13H
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
1 byte address
SLK
SI
tCS
Get Feature
0FH
7
6
5
4
3
2
1
0
MSB
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7
6
5
4
3
2
1
0
7
MSB
17
SPI(x1/x2/x4) NAND Flash
9.3 Read From Cache (03H)
1G
Figure9-2. Read From Cache Sequence Diagram
CS#
8
9 10 11 12 13 14 15 16
Dummy Byte
0
1
2
3
4
5
6
7
17 18 19 20 21
A15-0
30 31
SCLK
Command
03H
SI
7
6
5
4
3
2
1
0
15 14 12 11
13
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39
SCLK
SI
Byte 0
Byte 1
6 5
SO
7
6
5
4
3
2
1
0
7
MSB
MSB
9.4 Fast Read From Cache (0BH)
Figure9-3. Read From Cache Sequence Diagram
CS#
8
9 10 11 12 13 14 15 16
Dummy Byte
0
1
2
3
4
5
6
7
17 18 19 20 21
A15-0
30 31
SCLK
Command
0BH
SI
7
6
5
4
3
2
1
0
15 14 13 12 11
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39
Dummy Byte
40 41 42 43 44 45 46 47
SCLK
SI
7
6
5
4
3
2
1
0
Byte 0
Byte 1
6 5
SO
7
6
5
4
3
2
1
0
7
MSB
MSB
18
SPI(x1/x2/x4) NAND Flash
9.5 Read From Cache x2 (3BH)
1G
Figure9-4. Read From Cache x2 Sequence Diagram
CS#
8
9 10 11 12 13 14 15 16
Dummy Byte
0
1
2
3
4
5
6
7
17 18 19 20 21
A15-0
30 31
SCLK
Command
3BH
SI
7
6
5
4
3
2
1
0
15 14 12 11
13
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39
Dummy Byte
40 41 42 43 44 45 46 47
SCLK
SI
7
6
5
4
3
2
1
0
6
4
2
0
1
6
7
4
2
0
1
6
7
4
2
Byte 0
Byte 1
Byte 2
SO
7
5
3
5
3
5
3
MSB
MSB
9.6 Read From Cache x4 (6BH)
The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command.
Figure9-5. Read From Cache x4 Sequence Diagram
CS#
8
9 10 11 12 13 14 15 16
Dummy Byte
0
1
2
3
4
5
6
7
17 18 19 20 21
A15-0
30 31
SCLK
SI
Command
6BH
7
6
5
4
3
2
1
0
15 14 12 11
13
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39
Dummy Byte
40 41 42 43 44 45 46 47
SCLK
7
6
5
4
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(SIO0)
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
Byte0 Byte1 Byte2 Byte3
19
SPI(x1/x2/x4) NAND Flash
9.7 Read From Cache Dual IO (BBH)
1G
The Read from Cache Dual I/O command (BBH) is similar to the Read form Cache x2 command (3BH), followed by a 12bit
column address for the starting byte address and a dummy byte by SIO0 and SIO1, each bit being latched in during the
rising edge of SCLK, then the cache contents are shifted out 2-bit per clock cycle from SIO0 and SIO1. The first address
byte can be at any location. The address increments automatically to the next higher address after each byte of data shifted
out until the end of whole page.
Figure9-6. Read From Cache Dual IO Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
BBH
SI(SIO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(SIO1)
7
A7-0
Dummy
Byte0
Dummy, A11-8
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(SIO0)
SO(SIO1)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
Byte1
Byte2
Byte3
Byte4
20
SPI(x1/x2/x4) NAND Flash
9.8 Read From Cache Quad IO (EBH)
1G
The Read from Cache Quad IO command is similar to the Read from Cache x4 command, followed a 12-bit column address
for the starting byte address and a dummy byte by SIO0, SIO1, SIO3, SIO4, each bit being latched in during the rising
edge of SCLK, then the cache contents are shifted out 4-bit per clock cycle from SIO0, SIO1, SIO2, SIO3. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out until the end of whole page. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read
from cache quad IO command.
Figure9-7. Read From Cache Quad IO Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
EBH
SI(SIO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(SIO1)
5
6
7
WP#(SIO2)
HOLD#(SIO3)
Byte0 Byte1
Dummy
Dummy, A11-A8
A7-0
21
SPI(x1/x2/x4) NAND Flash
1G
10 Read ID (9FH)
The READ ID command is used to identify the NAND Flash device.
• The READ ID command outputs the Manufacturer ID and the device ID. See Table10-1 for details.
Figure10-1. Read ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
SI
9FH
Manufacturer ID
High-Z
SO
7
6
5
4
3
2
1
0
CS#
17 18 19 20 21 22 23
25 26 27 28 29 30 31
16
24
SCLK
SI
Device ID(Byte 1)
Device ID(Byte 2)
SO
7
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
Table10-1. READ ID Table
ID
Description
Part No
Value
Page Size
Manufacture ID (GigaDevice)
SPI NAND 3.3V
GD5F1GQ4UFxxH
GD5F1GQ4RFxxH
GD5F1GQ4UFxxH
GD5F1GQ4RFxxH
GD5F1GQ4UFxxH
GD5F1GQ4RFxxH
C8h
SPI NAND 1.8V
Device ID
(Byte 1)
SPI NAND 1Gbit 3.3V
SPI NAND 1Gbit 1.8V
SPI NAND 1Gbit 3.3V
SPI NAND 1Gbit 1.8V
B9h
A9h
48h
2Kbyte +
64Byte
Device ID
(Byte 2)
22
SPI(x1/x2/x4) NAND Flash
11 PROGRAM OPERATIONS
1G
11.1 Page Program
The PAGE PROGRAM operation sequence programs 1 byte to 2112 bytes of data with in a page. The page program
sequence is as follows:
• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4)
• 06H (WRITE ENABLE)
• 10H (PROGRAM EXECUTE)
• 0FH (GET FEATURE command to read the status)
Firstly, a PROGRAM LOAD (02H/32H) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4
dummy bits and a 12-bit column address, then the data bytes to be programmed. The data bytes are loaded into a cache
register that is 2112 bytes long. If more than 2112 bytes are loaded, then those additional bytes are ignored by the cache
register. The command sequence ends when CS# goes from LOW to HIGH. Figure11-1 shows the PROGRAMLOAD
operation. Secondly, prior to performing the PROGRAM EXECUTE operation, a WRITE ENABLE (06H) command must
be issued. As with any command that changes the memory contents, the WRITEENABLE must be executed in order to set
the WEL bit. If this command is not issued, then the rest of the program sequence is ignored.
Note:
1.
2.
3.
The contents of Cache Register doesn’t reset when Program Load (02h) command, Program Random Load (84h) command and
RESET (FFh) command.
When Program Execute (10h) command was issued just after Program Load (02h) command, SPI-NAND controller outputs 0xFF
data to the NAND for the address that data was not loaded by Program Load (02h) command.
When Program Execute (10h) command was issued just after Program Load Random Data (84h) command, SPI-NAND controller
outputs contents of Cache Register to the NAND.
4. The addressing should be done in sequential order in a block.
23
SPI(x1/x2/x4) NAND Flash
11.2 Program Load (PL) (02H)
1G
Figure11-1. Program Load Sequence Diagram
CS#
10 11 12 13 14
0
1
2
3
4
5
6
7
8
9
22 23
SCLK
Command
02H
Dummy<3:0>, A11-A0
SI
0
0
0
0 11 10
3
2
1
0
CS#
16912
16919
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Data Byte0
Data Byte1
Data Byte 2111
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
.
24
SPI(x1/x2/x4) NAND Flash
11.3 Program Load x4 (PL x4) (32H)
1G
The Program Load x4 command (32H) is similar to the Program Load command (02H) but with the capability to input the
data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown below. The Quad Enable bit (QE)
of feature (B0[0]) must be set to enable the program load x4 command.
Figure11-2. Program Load x4 Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
SCLK
Command
32H
Dummy<3:0>, A11-A0
15 14 13
Byte0 Byte1 Byte2 Byte3
SI(SIO0)
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Byte
2111
Byte4 Byte5 Byte6
Byte7 Byte8 Byte9 Byte10Byte11
SI(SIO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
0
1
2
3
SO(SIO1)
5
6
7
WP#(SIO2)
HOLD#(SIO3)
25
SPI(x1/x2/x4) NAND Flash
11.4 Program Execute (PE) (10H)
1G
After the data is loaded, a PROGRAM EXECUTE (10H) command must be issued to initiate the transfer of data from the
cache register to the main array. PROGRAM EXECUTE consists of an 8-bit Op code, followed by a 24-bit address. After
the page/block address is registered, the memory device starts the transfer from the cache register to the main array, and
is busy for tPROG time. This operation is shown in Figure11-3. During this busy time, the status register can be polled to
monitor the status of the operation (refer to Status Register). When the operation completes successfully, the next series
of data can be loaded with the PROGRAM LOAD command.
Figure11-3. Program Execute Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
10H
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
tCS
Status register address
get feature
0FH
7
6
5
4
3
2
1
0
MSB
High-Z
SO
CS#
SCLK
SI
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Status register data out
Status register data out
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
MSB
MSB
26
SPI(x1/x2/x4) NAND Flash
11.5 Internal Data Move
1G
The INTERNAL DATA MOVE command sequence programs or replaces data in a page with existing data. The
INTERNAL DATA MOVE command sequence is as follows:
• 13H (PAGE READ to cache)
• Optional 84H/C4H/34H (PROGRAM LOAD RANDOM DATA)
• 06H (WRITE ENABLE)
• 10H (PROGRAM EXECUTE)
• 0FH (GET FEATURE command to read the status)
Prior to performing an internal data move operation, the target page content must be read out into the cache register by
issuing a PAGE READ (13H) command. The PROGRAM LOAD RANDOM DATA (84H/C4H/34H) command can be
issued, if user wants to update bytes of data in the page. New data is loaded in the 12-bit column address. If the random
data is not sequential, another PROGRAM LOAD RANDOM DATA (84H/C4H/34H) command must be issued with the
new column address. After the data is loaded, the WRITE ENABLE command must be issued, and the PROGRAM
EXECUTE (10H) command can be issued to start the programming operation.
11.6 Program Load Random Data (84H)
This command consists of an 8-bit Op code, followed by 4 dummy bits, and a 12-bit column address. New data is loaded
in the column address provided with the 12 bits. If the random data is not sequential, then another PROGRAM LOAD
RANDOM DATA (84H) command must be issued with a new column address, see Figure11-4 for details. This command is
only available during internal data move sequence.
Figure11-4. Program Load Random Data Sequence Diagram
CS#
10 11 12 13 14
0
1
2
3
4
5
6
7
8
9
22 23
SCLK
SI
Dummy<3:0>, A11-A0
Command
84H
0
0
0 0 11 10
3
2
1
0
CS#
16912
16919
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Data Byte0
Data Byte1
Data Byte 2111
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
27
SPI(x1/x2/x4) NAND Flash
1G
11.7 Program Load Random Data x4 (C4H/34H)
The Program Load Random Data x4 command (C4H/34H) is similar to the Program Load Random Data command (84H)
but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown
below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable for the program load random data x4 command.
SeeFigure11-5 for details. Those two commands are only available during internal data move sequence.
Figure11-5. Program Load Random Data x4 Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
SCLK
Command
C4H/34H
Dummy<3:0>, A11-A0
15 14 13
Byte0 Byte1
SI(SIO0)
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Byte10Byte11
SCLK
Byte
2111
SI(SIO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
28
SPI(x1/x2/x4) NAND Flash
12 ERASE OPERATIONS
1G
12.1 Block Erase (D8H)
Figure12-1. Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
D8H
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SLK
SI
tCS
Status register address
get feature
0FH
7
6
5
4
3
2
1
0
MSB
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out
Status register data out
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
MSB
MSB
The BLOCK ERASE (D8H) command is used to erase at the block level. The blocks are organized as 64 pages per
block, 2112 bytes per page (2048 + 64 bytes). Each block is132 Kbytes. The BLOCK ERASE command (D8H) operates
on one block at a time. The command sequence for the BLOCK ERASE operation is as follows:
• 06H (WRITE ENBALE command)
• D8H (BLOCK ERASE command)
• 0FH (GET FEATURES command to read the status register)
Prior to performing the BLOCK ERASE operation, a WRITE ENABLE (06H) command must be issued. As with any
command that changes the memory contents, the WRITEENABLE command must be executed in order to set the WEL
bit. If the WRITE ENABLE command is not issued, then the rest of the erase sequence is ignored. A WRITE ENABLE
command must be followed by a BLOCK ERASE (D8H) command. This command requires a 24-bit address. After the
row address is registered, the control logic automatically controls timing and erase-verify operations. The device is busy
for tERS time during the BLOCK ERASE operation. The GET FEATURES (0FH) command can be used to monitor the
status of the operation.
When
a
block erase operation is in progress, user can issue normal read from cache commands
(03H/0BH/3BH/6BH/BBH/EBH) to read the data in the cache.
29
SPI(x1/x2/x4) NAND Flash
13 RESET OPERATIONS
1G
13.1 Soft Reset (FFH)
Figure13-1. Reset Sequence Diagram
CS#
tCS
0
1
2
3
4
5
6
7
SCLK
Command
FFH
SI
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SLK
SI
Status register address
get feature
0FH
7
6
5
4
3
2
1
0
MSB
High-Z
SO
CS#
SCLK
SI
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Status register data out
Status register data out
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
MSB
MSB
The RESET (FFH) command stops all operations. For example, in case of a program or erase or read operation, the
reset command can make the device enter the wait state.
During a cache program or cache read, a reset can also stops the previous operation and the pending operation. The
OIP status can be read from 300ns after the reset command is sent.
30
SPI(x1/x2/x4) NAND Flash
14 ADVANCED FEATURES
1G
14.1 OTP Region
The serial device offers a protected, One-Time Programmable NAND Flash memory area. 4 full pages (2112 bytes per
page) are available on the device. Customers can use the OTP area any way they want, like programming serial
numbers, or other data, for permanent storage. When delivered from factory, feature bit OTP_PRT is 0.
To access the OTP feature, the user must set feature bits OTP_EN/OTP_PRT by SET FEATURES command. When the
OTP is ready for access, pages 00h–03H can be programmed in sequential order by PROGRAM LOAD (02H) and
PROGRAM EXECUTE(10H) commands ( when not yet protected), and read out by PAGE READ (13H) command and
output data by READ from CACHE(03H/0BH/3BH/6BH/BBH/EBH).
Table14-1. OTP States
OTP_PRT
OTP_EN
State
x
0
1
0
1
1
Normal operation
Access OTP region, read and program data.
1. When the device power on state OTP_PRT is 0, user can set feature
bit OTP_PRT and OTP_EN to 1, then issue PROGRAM EXECUTE
(10H) to lock OTP, and after that OTP_PRT will permanently remain 1.
2. When the device power on state OTP_PRT is 1, user can only read the
OTP region data.
Note: The OTP space cannot be erased and after it has been protected, it cannot be programmed again, please use this
function carefully.
Access to OTP data
• Issue the SET FEATURES command (1FH)
• Set feature bit OTP_EN
• Issue the PAGE PROGRAM (only when OTP_PRT is 0) or PAGE READ command
Protect OTP region
Only when the following steps are completed, the OTP_PRT will be set and users can get this feature out with 0FH
command.
• Issue the SET FEATURES command (1FH)
• Set feature bit OTP_EN and OTP_PRT
• 06H (WRITE ENABLE)
• Issue the PROGRAM EXECUTE (10H) command.
31
SPI(x1/x2/x4) NAND Flash
1G
14.2 Block Protection
The block lock feature provides the ability to protect the entire device, or ranges of blocks, from the PROGRAM and ERASE
operations. After power-up, the device is in the “locked” state, i.e., feature bits BP0, BP1and BP2are set to 1, INV, CMP
and BRWD are set to 0. To unlock all the blocks, or a range of blocks, the SET FEATURES command must be issued to
alter the state of protection feature bits. When BRWD is set and WP# is LOW, none of the writable protection feature bits
can be set. Also, when a PROGRAM/ERASE command is issued to a locked block, status bit OIP remains 0.When an
ERASE command is issued to a locked block, the erase failure, 04H, is returned. When a PROGRAM command is issued
to a locked block, program failure,08h is returned.
Table14-1. Block Lock Register Block Protect Bits
CMP
INV
BP2
BP1
BP0
Protect Row Address
1G
Protect Rows
NONE
None—all unlocked
Upper 1/64 locked
Upper 1/32 locked
Upper 1/16 locked
Upper 1/8 locked
Upper 1/4 locked
Upper 1/2 locked
All locked (default)
Lower 1/64 locked
Lower 1/32 locked
Lower 1/16 locked
Lower 1/8 locked
Lower 1/4 locked
Lower 1/2 locked
Lower 63/64 locked
Lower31/32 locked
Lower 15/16 locked
Lower7/8 locked
Lower3/4 locked
Block0
x
0
0
0
0
0
0
x
x
0
0
0
0
0
0
x
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
FC00h ~ FFFFh
F800h ~ FFFFh
F000h ~ FFFFh
E000h ~ FFFFh
C000h ~ FFFFh
8000h ~ FFFFh
0000h ~ FFFFh
0000h ~ 03FFh
0000h ~ 07FFh
0000h ~ 0FFFh
0000h ~ 1FFFh
0000h ~ 3FFFh
0000h ~ 7FFFh
0000h ~ FBFFh
0000h ~ F7FFh
0000h ~ EFFFh
0000h ~ DFFFh
0000h ~ BFFFh
0000h ~ 003Fh
0400h ~ FFFFh
0800h ~ FFFFh
1000h ~ FFFFh
2000h ~ FFFFh
4000h ~ FFFFh
0000h ~ 003Fh
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
Upper 63/64 locked
Upper31/32 locked
Upper 15/16 locked
Upper7/8 locked
Upper3/4 locked
Block0
When WP# is not LOW, user can issue bellows commands to alter the protection states as want.
• Issue SET FEATURES register write (1FH)
• Issue the feature bit address (A0h) and the feature bits combination as the table
32
SPI(x1/x2/x4) NAND Flash
14.3 Status Register and Driver Register
1G
The NAND Flash device has a 16-bit status register that software can read during the device operation for operation state
query. The status register can be read by issuing the GET FEATURES (0FH)command, followed by the feature address
C0h (see FEATURE OPERATION). The Output Driver Register can be set and read by issuing the SET FEATURE (0FH)
and GET FEATURE command followed by the feature address D0h (see FEATURE OPERATION)..
Table14-2. Status Register Bit Descriptions
Bit
Bit Name
Program
Fail
Description
P_FAIL
This bit indicates that a program failure has occurred (P_FAIL set to 1). It will also be
set if the user attempts to program an invalid address or a protected region, including
the OTP area. This bit is cleared during the PROGRAM EXECUTE command
sequence or a RESET command (P_FAIL = 0).
E_FAIL
WEL
Erase Fail
This bit indicates that an erase failure has occurred (E_FAIL set to 1). It will also be
set if the user attempts to erase a locked region. This bit is cleared (E_FAIL = 0) at
the start of the BLOCK ERASE command sequence or the RESET command.
This bit indicates the current status of the write enable latch (WEL) and must be set
(WEL = 1), prior to issuing a PROGRAM EXECUTE or BLOCK ERASE command. It
is set by issuing the WRITE ENABLE command. WEL can also be disabled (WEL =
0), by issuing the WRITE DISABLE command.
Write
Enable
Latch
OIP
Operation
This bit is set (OIP = 1 ) when a PROGRAM EXECUTE, PAGE READ, BLOCK
In Progress ERASE, or RESET command is executing, indicating the device is busy. When the bit
is 0, the interface is in the ready state.
ECCS2~ECCS0 ECC Status ECCS2~ECCS0 provides ECC status as the following table.
Table14-3. ECC Status
ECCS2
ECCS1
ECCS0
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No bit errors were detected during the previous read algorithm.
Bit errors(<3) were detected and corrected.
Bit errors(=4) were detected and corrected.
Bit errors(=5) were detected and corrected.
Bit errors(=6) were detected and corrected.
Bit errors(=7) were detected and corrected.
Bit errors(=8) were detected and corrected.
Bit errors>8, error exceeded. And cannot be corrected.
33
SPI(x1/x2/x4) NAND Flash
Table14-4. Driver Register Bits Descriptions
DS_S0
1G
DS_S1
Driver Strength
0
0
1
1
0
1
0
1
50%
25%
75%
100%
14.4 Assistant Bad Block Management
As a NAND Flash, the device may have blocks that are invalid when shipped from the factory, and a minimum number of
valid blocks (NVB) of the total available blocks are specified. An invalid block is one that contains at least one page that has
more bad bits than can be corrected by the minimum required ECC. Additional bad blocks may develop with use. However,
the total number of available blocks will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices may contain bad blocks, they can be used reliably in systems that provide bad-
block management and error-correction algorithms, which ensure data integrity. Internal circuitry isolates each block from
other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by
programming the Bad Block Mark (00h) to the first spare area location in each bad block. This method is compliant with
ONFI Factory Defect Mapping requirements. See the following table I bad-block mark.
System software should initially check the first spare area location for non-FFH data I first page of each block prior to
performing any program or erase operations on the NAND Flash device. A bad-block table can then be created, enabling
system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid
blocks may be marginal, it may not be possible to recover the bad-block marking if the block is erased.
To simplify the system requirement and guard the data integration, GigaDevice SPI NAND provides assistant Management
options as below.
Table14-5. Bad Block Mark information
Description
Density
Requirement
Minimum number of valid blocks (NVB
Total available blocks per die
First spare area location
)
1G
1G
1004
1024
Byte 2048
Bad-block mark
00h(use non FFH to check)
34
SPI(x1/x2/x4) NAND Flash
1G
14.5 Internal ECC
The serial device offers data corruption protection by offering optional internal ECC.READs and PROGRAMs with internal
ECC can be enabled or disabled by setting feature bit ECC_EN. ECC is enabled after device power up, so the default
READ and PROGRAM commands operate with internal ECC in the “active” state. To enable/disable ECC, perform the
following command sequence:
• Issue the SET FEATURES command (1FH).
• Set the feature bit ECC_EN as you want:
1. To enable ECC, Set ECC_EN to 1.
2. To disable ECC, Clear ECC_EN to 0.
During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the page
is written to the NAND Flash array.
During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated
and compared with the ECC code value read from the array. If error bits are detected, the error is corrected in the cache
register. Only corrected data is output on the I/O bus. The ECC status bit indicates whether or not the error correction was
successful. The ECC Protection table below shows the ECC protection scheme used throughout a page.
With internal ECC, the user must accommodate the following:
• Spare area definitions provided in the ECC Protection table below.
• ECC can protect according main and spare areas. WRITEs to the ECC area are ignored.
Table14-6. ECC Protection and Spare Area
Min Byte Address
Max Byte Address
ECC Protected Area
Description
000h
200h
400h
600h
800h
810h
820h
830h
1FFh
3FFh
5FFh
7FFh
80Fh
81Fh
82Fh
83Fh
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Main 0
User data 0
Main 1
User data 1
Main 2
User data 2
Main 3
User data 3
Spare 0
Spare 1
Spare 2
Spare 3
User meta data 0(1)
User meta data 1
User meta data 2
User meta data 3
Note1:800H is reserved for initial bad block mark, and please check the initial bad block mark with internal ECC off.
35
SPI(x1/x2/x4) NAND Flash
15 POWER ON TIMING
1G
Figure15-1. Power on Timing Sequence
Vcc(max)
Vcc(min)
VWI
Chip Selection is not allowed
tVSL
Device is fully
accessible
Time
Table15-1. Power-On Timing and Write Inhibit Threshold for 1.8V/3.3V
Symbol
Parameter
VCC(min) To CS# Low
Write Inhibit Voltage
Min
Max
Unit
tVSL
5
ms
1.8V
3.3V
1.7
2.5
VWI
V
36
SPI(x1/x2/x4) NAND Flash
16 ABSOLUTE MAXIMUM RATINGS
1G
Parameter
Ambient Operating Temperature
Storage Temperature
Applied Input/Output Voltage
VCC
Value
Unit
℃
℃
V
-40 to 105
-55 to 125
-0.6 to 4.0
-0.6 to 4.0
V
37
SPI(x1/x2/x4) NAND Flash
1G
17 CAPACITANCE MEASUREMENT CONDITIONS
Symbol
CIN
Parameter
Min
Typ
Max
6
Unit
pF
pF
pF
ns
V
Conditions
Input Capacitance
VIN=0V
COUT
CL
Output Capacitance
8
VOUT=0V
Load Capacitance
30
Input Rise And Fall time
Input Pulse Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Figure17-1. Input Test Waveform and Measurement Level
Input timing reference level
0.7VCC
Output timing reference level
0.5VCC
0.8VCC
0.1VCC
AC Measurement Level
0.2VCC
Note: Input pulse rise and fall time are<5ns
38
SPI(x1/x2/x4) NAND Flash
18 DC CHARACTERISTIC
1G
(T= -40℃~105℃, VCC=1.7~2.0V/2.7~3.6V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
90(1)
μA
VIN=VCC or VSS
CLK=0.1VCC /
0.9VCC
40
30
mA
mA
at 120MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /
0.9VCC
ICC2
Operating Current (Read)
at 80MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC3
ICC4
VIL
Operation Current (PP)
Operation Current (BE)
Input Low Voltage
40
40
mA
mA
V
CS#=VCC
0.2VCC
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =1.6mA
0.4
V
IOH =-100μA
V
Note: 1. When Temperature is 105℃, the maximum standby current is 200uA
39
SPI(x1/x2/x4) NAND Flash
19 AC CHARACTERISTICS
1G
(T= -40℃~105℃, VCC=1.7~2.0V/2.7~3.6V, CL=30pf)
Symbol
FC
Parameter
Serial Clock Frequency For: all command
Serial Clock High Time
Min.
DC.
4
Typ.
Max.
Unit.
MHz
ns
120
tCH
tCL
Serial Clock Low Time
4
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
0.2
0.2
5
V/ns
V/ns
ns
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
CS# Not Active Hold Time
5
ns
5
ns
tSHSL/tCS CS# High Time
Output Disable Time
20
ns
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
tCLQV
tWHSL
tSHWL
20
ns
Output Hold Time
2
2
2
5
5
5
5
ns
Data In Setup Time
ns
Data In Hold Time
ns
Hold# Low Setup Time (relative to Clock)
Hold# High Setup Time (relative to Clock)
Hold# High Hold Time (relative to Clock)
Hold# Low Hold Time (relative to Clock)
Hold# Low To High-Z Output
Hold# HighTo Low-Z Output
Clock Low To Output Valid
ns
ns
ns
ns
15
15
8
ns
ns
ns
WP# Setup Time Before CS# Low
WP# Hold Time After CS# High
20
ns
100
ns
40
SPI(x1/x2/x4) NAND Flash
20 PERFORMANCE TIMING
1G
Symbol
TRST
Parameter
CS# High To Next Command After Reset(FFh)
Read From Array
Min.
Typ.
Max.
500
80
Unit.
us
tRD
us
tPROG
tBERS
Page Programming Time
0.4
3
0.7
5
ms
ms
Block Erase Time
Figure20-1. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCLCH
tCHDX
SI
MSB
High-Z
LSB
SO
Figure20-2. Output Timing
CS#
tCH
tSHQZ
SCLK
tCLQV
tCLQV
tCLQX
tCL
tCLQX
SO
SI
LSB
Least significant address bit (LIB) in
41
SPI(x1/x2/x4) NAND Flash
1G
Figure20-3. Hold Timing
CS#
tCHHL
tHLCH
tCHHH
tHHCH
tHHQX
SCLK
tHLQZ
SO
HOLD#
SI do not care during HOLD operation.
Figure20-4. Reset Timing
FFh
OIP
OIP
tRST
Note: The maximum tRST depends on different operations.
Idle:
maximum tRST = 5us;
maximum tRST = 5us;
Read:
Program: maximum tRST = 10us;
Erase: maximum tRST = 500us;
42
SPI(x1/x2/x4) NAND Flash
21 ORDERING INFORMATION
1G
GD XX XX XX X X X X X X
Packing Type
T or No mark: Tube
R: Tape & Reel
Y: Tray
GD Prefix
Green Code
G: Pb Free & Halogen Free Green Package
S: G + special function (HW Reset + UID +
Parameter Page)
H: Pb Free & Halogen Free Green Package +
Half of Spare Size
Temperature Range
I: Industrial(-40C to +85C)
J:Industrial(-40 to +105 )
F: Industrial+(1) (-40 ꢀto +85 )
Package Type
Y: WSON8 (6*8mm)
F: SOP16 300mil
Z:TFBGA24(6*4 Ball Array)
9: LGA8 6*8mm
Generation
B: B Version
C: C Version
E: E Version
F: F Version
Voltage
U:3.3V(2.7~3.6V)
R:1.8V(1.7~2.0V)
Interface
Q4: Qua SPI x1/x2/x4
Density
1G: 1Gb 2G: 2Gb
4G: 4Gb 8G: 8Gb
Product Family
5F: SPI NAND Flash
Note: (1) Industrial+: Full Function Test for Automotive application and no AECQ
43
SPI(x1/x2/x4) NAND Flash
22 PACKAGE INFORMATION
1G
c
D
E
A1
Top View
L
A
Side View
b
e
E2
D2
Bottom View
Figure22-1. WSON8 (8*6mm)
Dimensions
Symbol
Unit
A
A1
0.00
c
b
D
D2
3.30
E
E2
4.20
e
L
Min
0.70
0.180
0.203
0.250
0.007
0.008
0.010
0.35
7.90
5.90
0.45
mm
Nom
Max
Min
0.75
0.02
0.05
0
0.40
8.00
3.40
6.00
4.30
1.27
0.50
0.80
0.45
8.10
3.50
6.05
4.40
0.55
0.028
0.030
0.032
0.014
0.016
0.018
0.311
0.315
0.319
0.130
0.134
0.138
0.232
0.236
0.238
0.165
0.169
0.173
0.018
0.020
0.022
Inch Nom
Max
0.001
0.002
0.05
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These lead
shapes are compatible with each other.
44
SPI(x1/x2/x4) NAND Flash
1G
Figure22-2. SOP16 300MIL
D
E1
E
h
L1
L
h
θ
“A”
b
c
Base Metal
A
A2
A1
Detail “A”
b
e
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
h
θ
Min
-
0.10
0.20
0.30
2.05
-
0.31
0.41
0.51
0.10
0.25
0.33
10.20 10.10
10.30 10.30
10.40 10.50
7.40
7.50
7.60
0.40
-
0.25
-
0
mm
Nom
Max
Min
-
1.27
0.05
1.40
5
8
2.65
2.55
1.27
0.016
0.75
0.010
-
-
-
0.004 0.081 0.012 0.004 0.402 0.398 0.291
0.008 0.016 0.010 0.406 0.406 0.295
0
Inch
Nom
Max
-
0.055
0.197
0.104 0.012 0.100 0.020 0.013 0.409 0.413 0.299
0.05
0.030 0.315
Note: Both package length and width do not include mold flash.
45
SPI(x1/x2/x4) NAND Flash
1G
Figure22-3. TFBGA-24BALL (6*4 ball array)
1
2
3
4
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
e
SD
E1
E
SE
e
D
D1
Φb
Dimensions
Symbol
Unit
A
A1
A2
b
D
D1
E
E1
e
SE
SD
Min
0.25
0.30
0.35
0.70
0.80
0.85
0.35
0.40
0.45
5.90
6.00
7.90
8.00
3.00
BSC
5.00
BSC
1.00
BSC
0.50
TYP
0.50
TYP
mm
Nom
Max
Min
1.20
6.10
8.10
0.010 0.028 0.014
0.012 0.031 0.016
0.232
0.236
0.240
0.311
0.315
0.319
0.118
BSC
0.197
BSC
0.039
BSC
0.020
TYP
0.020
TYP
Inch Nom
Max
0.047 0.014 0.034 0.018
Note:Both package length and width do not include mold flash.
46
SPI(x1/x2/x4) NAND Flash
1G
Figure22-4. GD Type1 LGA8 (6*8 mm)
D2
A
D
L
2
A2
A
Lead Type design Gap
c
Soldermask
LAND PAD
A1
Dimensions
Symbol
A
A2
A1
c
b
D
D2
E
E2
e
L
Unit
GD
GD
Type1
Type1
Min
0.70
0.15
0.18
0.21
0.35
0.40
0.45
7.90
8.00
3.30
3.40
5.90
6.00
4.20
4.30
0.45
0.50
mm
Nom
Max
Min
0.02
0.53
1.27
0.05
0.80
8.10
3.50
6.10
4.40
0.55
0.028
0.006 0.014
0.311
0.315
0.319
0.130
0.134
0.138
0.232
0.165
0.018
0,020
0.022
Inch
Nom
Max
0.001
0.021
0.007
0.008
0.016
0.018
0.236 0.169
0.240 0.173
0.031
47
SPI(x1/x2/x4) NAND Flash
23 REVISION HISTORY
1G
Version No
Description
Date
Page
1.0
Initial Release
2018-10-18
Add “Power Off Timing” in Device Operation.
Update the Important Notice. “Customers shall discard the device
according to the local environmental law.”
12
49
1.1
2019-3-22
Correct “ABSOLUTE MAXIMUM RATINGS” Applied Input/ Output
Voltage
37
48
SPI(x1/x2/x4) NAND Flash
1G
Important Notice
This document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The
Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the
property of their respective owner and referred to for identification purposes only.
The Company makes no warranty of any kind, express or implied, with regard to this document or any Product,
including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company
does not assume any liability arising out of the application or use of any Product described in this document. Any information
provided in this document is provided only for reference purposes. It is the responsibility of the user of this document to
properly design, program, and test the functionality and safety of any application made of this information and any resulting
product. Except for customized products which has been expressly identified in the applicable agreement, the Products
are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications
only. The Products are not designed, intended, or authorized for use as components in systems designed or intended for
the operation of weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control
instruments, airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical
devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or Product could cause personal injury, death, property or
environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the
Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, and
customers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage,
or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold the
Company as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products.
Information in this document is provided solely in connection with the Products. The Company reserves the right to
make changes, corrections, modifications or improvements to this document and the Products and services described
herein at any time, without notice.
49
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