GS81302D19E-375IT [GSI]
DDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165;
| 型号： | GS81302D19E-375IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | DDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165 双倍数据速率 静态存储器 |
| 文件： | 总33页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS81302D07/10/19/37E-400/375/333/300
400 MHz–300 MHz
144Mb SigmaQuad-II+TM
Burst of 4 SRAM
165-Bump BGA
Commercial Temp
Industrial Temp
1.8 V V
DD
1.8 V and 1.5 V I/O
Features
• 2.0 clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
Bottom View
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
SigmaQuad™ Family Overview
Clocking and Addressing Schemes
The GS81302D07/10/19/37E are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302D07/10/19/37E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
The GS81302D07/10/19/37E SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Separate I/O SigmaQuad-II+ B4 RAMs always
transfer data in four packets, A0 and A1 are internally set to 0
for the first read or write transfer, and automatically
incremented by 1 for the next transfers. Because the LSBs are
tied off internally, the address field of a SigmaQuad-II+ B4
RAM is always two address pins less than the advertised index
depth (e.g., the 8M x 18 has a 2M addressable index).
Parameter Synopsis
-400
2.5 ns
0.45 ns
-375
-333
-300
3.3 ns
0.45 ns
tKHKH
tKHQV
2.66 ns
0.45 ns
3.0 ns
0.45 ns
Rev: 1.02b 6/2010
1/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
16M x 8 SigmaQuad-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
CQ
SA
SA
W
NW1
K
SA
R
SA
SA
CQ
NC/SA
(288Mb)
NC
NC
NC
SA
K
NW0
SA
SA
NC
NC
Q3
C
D
E
F
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
D4
NC
NC
D5
NC
NC
Q4
NC
Q5
V
SA
NC
V
NC
NC
NC
NC
NC
NC
NC
D2
D3
NC
Q2
NC
NC
ZQ
D1
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
NC
Q1
K
L
NC
Q6
NC
D6
NC
NC
Q7
SA
V
NC
NC
NC
NC
NC
SA
NC
NC
NC
Q0
D0
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
NC
D7
V
V
NC
SS
SS
SS
SS
V
SA
SA
SA
SA
SA
SA
SA
V
NC
NC
NC
TDI
NC
TCK
SA
SA
QVLD
ODT
SA
SA
NC
TMS
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.
2. B5 is the expansion address.
Rev: 1.02b 6/2010
2/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
16M x 9 SigmaQuad-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
CQ
SA
SA
W
NC
K
SA
R
SA
SA
CQ
NC/SA
(288Mb)
NC
NC
NC
SA
K
BW0
SA
SA
NC
NC
Q4
C
D
E
F
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
D5
NC
NC
D6
NC
NC
Q5
NC
Q6
V
SA
NC
V
NC
NC
NC
NC
NC
NC
NC
D3
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
NC
Q2
K
L
NC
Q7
NC
D7
NC
NC
Q8
SA
V
NC
NC
NC
NC
NC
SA
NC
NC
NC
NC
D0
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
NC
D8
V
V
SS
SS
SS
SS
V
SA
SA
SA
SA
SA
SA
SA
V
NC
TCK
SA
SA
QVLD
ODT
SA
SA
TMS
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8.
2. B5 is the expansion address.
Rev: 1.02b 6/2010
3/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
8M x 18 SigmaQuad-II+ SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
NC
(288Mb
SA)
A
CQ
SA
SA
W
BW1
K
R
SA
SA
CQ
B
C
D
E
F
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
Q9
NC
D9
SA
NC
SA
K
BW0
SA
SA
NC
NC
NC
NC
NC
NC
NC
Q7
NC
D6
NC
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
D10
Q10
Q11
D12
Q13
V
NC
V
SS
SS
SS
SS
D11
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
Q12
D13
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
NC
D14
Q14
D15
D16
Q16
Q17
SA
NC
Q4
K
L
NC
Q15
NC
V
NC
NC
NC
NC
NC
SA
D3
NC
Q1
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
SS
SS
SS
SS
D17
NC
V
SA
SA
SA
SA
SA
SA
SA
V
NC
D0
SA
SA
QVLD
ODT
SA
SA
TCK
TMS
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. A7 is the expansion address.
Rev: 1.02b 6/2010
4/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
4M x 36 SigmaQuad-II+ SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
NC
(288Mb
SA)
A
CQ
SA
W
BW2
K
BW1
R
SA
SA
CQ
B
C
D
E
F
Q27
D27
D28
Q29
Q30
D30
Doff
D31
Q32
Q33
D33
D34
Q35
TDO
Q18
Q28
D20
D29
Q21
D22
D18
D19
Q19
Q20
D21
Q22
SA
BW3
SA
K
BW0
SA
SA
D17
D16
Q16
Q15
D14
Q13
Q17
Q7
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
V
NC
V
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
D15
D6
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
Q14
D13
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
Q31
D32
Q24
Q34
D26
D35
TCK
D23
Q23
D24
D25
Q25
Q26
SA
D12
Q12
D11
D10
Q10
Q9
Q4
K
L
V
D3
Q11
Q1
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
SS
SS
SS
SS
V
SA
SA
SA
SA
SA
SA
SA
V
D9
SA
SA
QVLD
ODT
SA
SA
D0
SA
TMS
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
3. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35
4. Pin A2 is the Expansion Address.
Rev: 1.02b 6/2010
5/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Pin Description Table
Symbol
Description
Synchronous Address Inputs
Synchronous Read
Type
Input
Input
Input
Input
Comments
—
SA
R
W
Active Low
Active Low
Active Low
Synchronous Write
BW0–BW3
Synchronous Byte Writes
Active Low
(x8 only)
NW0–NW1
Synchronous Nybble Writes
Input
K
Input Clock
Input Clock
Input
Input
Active High
K
Active Low
TMS
TDI
TCK
TDO
VREF
Test Mode Select
Input
—
Test Data Input
Input
—
Test Clock Input
Input
—
Test Data Output
Output
Input
—
HSTL Input Reference Voltage
Output Impedance Matching Input
Synchronous Data Outputs
Synchronous Data Inputs
Disable DLL when low
Output Echo Clock
—
ZQ
Qn
Input
—
Output
Input
—
Dn
—
Active Low
—
Input
Doff
CQ
CQ
VDD
Output
Output
Supply
Output Echo Clock
—
Power Supply
1.8 V Nominal
VDDQ
VSS
Isolated Output Buffer Supply
Supply
1.8 V or 1.5 V Nominal
Power Supply: Ground
Q Valid Output
Supply
Output
Input
—
—
—
—
—
QVLD
ODT
On-Die Termination
No Connect
NC
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to V , output impedance is set to minimum value and it cannot be connected to ground or left
DDQ
unconnected.
Rev: 1.02b 6/2010
6/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
Alternating Read-Write Operations
SigmaQuad-II+ SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for
details.
SigmaQuad-II+ B4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A Low on
the Read Enable pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Clocking
in a High on the Read Enable pin, R, begins a read port deselect cycle.
SRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R High causes chip disable. A Low on
the Write Enable pin, W, and a High on the Read Enable pin, R, begins a write cycle. W is always ignored if the previous command
was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and
finally by the next rising edge of K.
Rev: 1.02b 6/2010
7/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Power-Up Sequence for SigmaQuad-II+ SRAMs
For compatibility across all vendors it is recommended that SigmaQuad-II+ SRAMs must be powered-up in a specific sequence in
order to avoid undefined operations.
Power-Up Sequence
1. Power-up and maintain Doff at Low state.
1a. Apply V
1b. Apply V
1c. Apply V
.
DD
.
DDQ
(may also be applied at the same time as V
).
REF
DDQ
2. After voltages are within specification range, and clocks (K, K) are stablized, change Doff to High.
3. An additional 2048 clock cycles are required to lock the DLL after it has been enabled.
Note: The DLL may be reset by driving the Doff pin Low or by stopping the K clocks for at least 30 ns. 2048 cycles of clean
K clocks are always required to relock the DLL after it has been stabilized.
DLL Constraints
The DLL synchronizes to either K clock. These clocks should have Low phase jitter (t
).
KVar
• The DLL cannot operate at a frequency lower than that specified by the t
operating clock frequency.
maximum specification for the desired
KHKH
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause
undefined errors or failures during the initial stage.
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 2048k is required for DLL lock.
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4-beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NWx” may be substituted in all the discussion above.
Rev: 1.02b 6/2010
8/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
D9–D17
Don’t Care
Data In
Beat 1
Beat 2
Beat 3
Beat 4
0
1
0
1
1
0
0
0
Data In
Don’t Care
Data In
Data In
Don’t Care
Data In
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Written
Unchanged
Unchanged
Written
Written
Written
Unchanged
Written
Beat 1
Beat 2
Beat 3
Beat 4
Rev: 1.02b 6/2010
9/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaQuad-II+ SRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock (K/K)
input receivers. Input termination can be enabled or disabled via the ODT pin (6R). When the ODT pin is tied Low (or left
floating —the pin has a small pull-down resistor), input termination is disabled. When the ODT pin is tied High, input termination
is enabled. Termination impedance is programmed via the same RQ resistor (connected between the ZQ pin and V ) used to
SS
program output driver impedance, and is nominally RQ*0.6 Thevenin-equivalent when RQ is between 175Ω and 250Ω. Periodic
readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manner
as for driver impedance (see above).
Note:
When ODT = 1, Data (D), Byte Write (BW), and Clock (K, K) input termination is always enabled. Consequently, D, BW, K, K
inputs should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are tri-stated, the
input termination will pull the signal to V
/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver
DDQ
to enter a meta-stable state and prevent the SRAM from operating within specification.
Rev: 1.02b 6/2010
10/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Separate I/O SigmaQuad II+ B4 SRAM Truth Table
Previous
Operation
Current
Operation
A
R
W
D
D
D
D
Q
Q
Q
Q
K ↑
K ↑
(tn)
K ↑
(tn)
K ↑
(tn)
K ↑
(tn)
K ↑
K ↑
(tn+1½
K ↑
K ↑
(tn+2½
K ↑
(tn+2)
K ↑
(tn+2½
K ↑
K ↑
(tn+3½)
(tn-1
)
(tn+1
)
)
(tn+2
)
)
)
(tn+3
)
Deselect
Write
X
X
X
V
V
V
V
1
1
X
1
0
X
0
1
X
1
0
X
0
X
Deselect
Deselect
Deselect
Write
X
D2
X
X
D3
X
—
—
—
D2
—
D2
—
—
—
—
D3
—
D3
—
Hi-Z
Hi-Z
Q2
Hi-Z
Hi-Z
Q3
—
—
—
—
Read
—
—
Deselect
Deselect
Read
D0
X
D1
X
Hi-Z
Q0
Hi-Z
Q1
—
—
Read
Q2
—
Q3
—
Write
D0
D2
D1
D3
Q2
Q3
Write
Read
Q0
Q1
Q2
Q3
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Users should not clock in metastable addresses.
Rev: 1.02b 6/2010
11/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
x36 Byte Write Enable (BWn) Truth Table
BW0
BW1
BW2
BW3
D0–D8
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Don’t Care
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Data In
Data In
x18 Byte Write Enable (BWn) Truth Table
BW0
BW1
D0–D8
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
1
0
1
0
1
1
0
0
Don’t Care
Data In
Data In
x09 Byte Write Enable (BWn) Truth Table
BW0
D0–D8
Don’t Care
Data In
1
0
1
0
Don’t Care
Data In
Rev: 1.02b 6/2010
12/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Nybble Write Clock Truth Table
NW
NW
NW
NW
Current Operation
D
D
D
D
K ↑
K ↑
(tn+1½
K ↑
K ↑
(tn+2½
K ↑
(tn)
K ↑
K ↑
(tn+1½
K ↑
K ↑
(tn+2½)
(tn+1
)
)
(tn+2
)
)
(tn+1
)
)
(tn+2
)
Write
T
T
F
T
F
F
F
T
T
F
F
F
T
F
D0
D0
X
D2
X
D3
X
D4
X
Dx stored if NWn = 0 in all four data transfers
Write
T
F
F
F
F
F
T
F
F
Dx stored if NWn = 0 in 1st data transfer only
Write
D1
X
X
X
Dx stored if NWn = 0 in 2nd data transfer only
Write
X
D2
X
X
Dx stored if NWn = 0 in 3rd data transfer only
Write
X
X
D3
X
Dx stored if NWn = 0 in 4th data transfer only
Write Abort
F
X
X
X
No Dx stored in any of the four data transfers
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
x8 Nybble Write Enable (NWn) Truth Table
NW0
NW1
D0–D3
Don’t Care
Data In
D4–D7
Don’t Care
Don’t Care
Data In
1
0
1
0
1
1
0
0
Don’t Care
Data In
Data In
Rev: 1.02b 6/2010
13/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
State Diagram
Power-Up
Read NOP
Write NOP
READ
WRITE
READ
WRITE
Load New
Load New
Read Address
D Count = 0
READ
D Count = 2
WRITE
Write Address
D Count = 2
D Count = 0
WRITE
Always
READ
D Count = 2
Always
D Count = 2
DDR Read
DDR Write
D Count = D Count + 1
D Count = D Count + 1
READ
Always
WRITE
Always
D Count = 1
D Count = 1
Increment
Increment
Read Address
Write Address
Notes:
1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+0, next internal burst address is A0+1.
2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is
true for “WRITE” and “WRITE”.
3. Read and write state machine can be active simultaneously.
4. State machine control timing sequence is controlled by K.
Rev: 1.02b 6/2010
14/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
VDD
Description
Value
Unit
Voltage on VDD Pins
Voltage in VDDQ Pins
Voltage in VREF Pins
–0.5 to 2.9
V
VDDQ
VREF
VI/O
–0.5 to VDD
V
–0.5 to VDDQ
V
V
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
Voltage on I/O Pins
VIN
VTIN
IIN
Input Voltage (Address, Control, Data, Clock)
Input Voltage (TCK, TMS, TDI)
Input Current on Any Pin
V
V
+/–100
+/–100
125
mA dc
mA dc
IOUT
TJ
Output Current on Any I/O Pin
Maximum Junction Temperature
Storage Temperature
oC
oC
TSTG
–55 to 125
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Supply Voltage
Symbol
VDD
Min.
1.7
Typ.
1.8
—
Max.
1.9
Unit
V
VDDQ
VREF
VDD
I/O Supply Voltage
Reference Voltage
1.4
V
VDDQ/2 – 0.05
VDDQ/2 + 0.05
—
V
Note:
The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal inputs. The power
DD DDQ REF
down sequence must be the reverse. V
must not exceed V .
DD
DDQ
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Ambient Temperature
(Commercial Range Versions)
TA
0
25
70
°C
Ambient Temperature
(Industrial Range Versions)
TA
–40
25
85
°C
Rev: 1.02b 6/2010
15/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
HSTL I/O DC Input Characteristics
Parameter
Input Reference Voltage
Input High Voltage
Symbol
VREF
VIH1
Min
Max
Units
Notes
—
VDDQ /2 – 0.05
VREF + 0.1
VDDQ /2 + 0.05
VDDQ + 0.3
VREF – 0.1
VDDQ + 0.3
0.3 * VDDQ
V
V
V
V
V
1
VIL1
Input Low Voltage
–0.3
1
VIH2
0.7 * VDDQ
2,3
2,3
Input High Voltage
VIL2
–0.3
Input Low Voltage
Notes:
1. Parameters apply to K, K, SA, D, R, W, BW during normal operation and JTAG boundary scan testing.
2. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing.
3. Parameters apply to ZQ during JTAG boundary scan testing only.
HSTL I/O AC Input Characteristics
Parameter
Input Reference Voltage
Symbol
VREF
VIH1
Min
Max
Units
Notes
—
VDDQ /2 – 0.08
VREF + 0.2
VDDQ /2 + 0.08
VDDQ + 0.5
VREF – 0.2
VDDQ + 0.5
V
V
V
V
V
1,2,3
1,2,3
4,5
Input High Voltage
Input Low Voltage
Input High Voltage
VIL1
–0.5
VIH2
VDDQ – 0.2
VIL2
Input Low Voltage
–0.5
0.2
4,5
Notes:
1.
V
and V
apply for pulse widths less than one-quarter of the cycle time.
IL(MIN)
IH(MAX)
2. Input rise and fall times must be a minimum of 1 V/ns, and within 10% of each other.
3. Parameters apply to K, K, SA, D, R, W, BW during normal operation and JTAG boundary scan testing.
4. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing.
5. Parameters apply to ZQ during JTAG boundary scan testing only.
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 1.8 V)
A
DD
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
Typ.
Max.
Unit
pF
Input Capacitance
Output Capacitance
Clock Capacitance
4
6
5
5
7
6
COUT
CCLK
VOUT = 0 V
VIN = 0 V
pF
pF
Note:
This parameter is sample tested.
Rev: 1.02b 6/2010
16/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
AC Test Conditions
Parameter
Input high level
Conditions
1.25
Input low level
0.25 V
2 V/ns
Max. input slew rate
Input reference level
Output reference level
0.75
VDDQ/2
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
DQ
RQ = 250 Ω (HSTL I/O)
V
= 0.75 V
REF
50Ω
VT == 0.75 V
Input and Output Leakage Characteristics
Parameter
Symbol
Test Conditions
Min.
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDDQ
–2 uA
2 uA
IILDOFF
IIL ODT
VIN = 0 to VDDQ
VIN = 0 to VDDQ
Doff
–20 uA
–2 uA
2 uA
ODT
20 uA
Output Disable,
VOUT = 0 to VDDQ
IOL
Output Leakage Current
–2 uA
2 uA
Rev: 1.02b 6/2010
17/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
VOH1
Min.
Max.
Units
Notes
1, 3
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
V
V
V
V
Output High Voltage
Output Low Voltage
Output High Voltage
VOL1
2, 3
VOH2
4, 5
VOL2
Vss
0.2
4, 6
Output Low Voltage
Notes:
1.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).
DDQ OH DDQ
OH
2.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤350Ω).
OL
DDQ
OL
DDQ
3. Parameter tested with RQ = 250Ω and V
4. 0Ω ≤ RQ ≤ ∞Ω
= 1.5 V
DDQ
5.
I
= –1.0 mA
OH
6.
I
= 1.0 mA
OL
Rev: 1.02b 6/2010
18/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Operating Currents
-400
-375
-333
-300
Parameter
Symbol
Test Conditions
Notes
0°
to
–40°
to
0°
to
–40°
to
0°
to
–40°
to
0°
to
–40°
to
70°C
85°C
70°C
85°C
70°C
85°C
70°C
85°C
Operating
Current (x36):
DDR
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
1235
mA
1245
mA
1170
mA
1180
mA
1055
mA
1065
mA
965
mA
IDD
IDD
IDD
IDD
975 mA
2, 3
2, 3
2, 3
2, 3
Operating
Current (x18):
DDR
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
1120
mA
1130
mA
1060
mA
1070
mA
960
mA
970
mA
880
mA
890
mA
Operating
Current (x9):
DDR
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
1120
mA
1130
mA
1060
mA
1070
mA
960
mA
970
mA
880
mA
890
mA
Operating
Current (x8):
DDR
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
1120
mA
1130
mA
1060
mA
1070
mA
960
mA
970
mA
880
mA
890
mA
Device deselected,
OUT = 0 mA, f = Max,
All Inputs ≤ 0.2 V
or ≥ VDD – 0.2 V
StandbyCurrent
(NOP): DDR
260
mA
270
mA
255
mA
265
mA
245
mA
255
mA
235
mA
245
mA
I
ISB1
2, 4
Notes:
1. Power measured with output pins floating.
2. Minimum cycle, I = 0 mA
OUT
3. Operating current is calculated with 50% read cycles and 50% write cycles.
4. Standby Current is only after all pending read and write burst operations are completed.
Rev: 1.02b 6/2010
19/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
AC Electrical Characteristics
-400
-375
-333
-300
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Clock
tKHKH
tKVar
K, K Clock Cycle Time
2.5
—
8.4
0.2
—
—
—
—
—
—
2.66
—
8.4
0.2
—
—
—
—
—
—
3.0
—
8.4
0.2
—
—
—
—
—
—
3.3
—
8.4
0.2
—
—
—
—
—
—
ns
ns
tK Variable
4
tKHKL
tKLKH
tKHKH
tKHKH
tKLock
tKReset
K, K Clock High Pulse Width
K, K Clock Low Pulse Width
K to K High
0.4
0.4
0.4
0.4
cycle
cycle
ns
0.4
0.4
0.4
0.4
1.06
1.06
2048
30
1.13
1.13
2048
30
1.28
1.28
2048
30
1.40
1.40
2048
30
K to K High
ns
DLL Lock Time
cycle
ns
5
K Static to DLL reset
Output Times
tKHQV
tKHQX
K, K Clock High to Data Output Valid
—
–0.45
—
0.45
—
—
–0.45
—
0.45
—
—
–0.45
—
0.45
—
—
–0.45
—
0.45
—
ns
ns
ns
ns
ns
ns
ns
K, K Clock High to Data Output Hold
K, K Clock High to Echo Clock Valid
K, K Clock High to Echo Clock Hold
CQ, CQ High Output Valid
tKHCQV
tKHCQX
tCQHQV
tCQHQX
tQVLD
0.45
—
0.45
—
0.45
—
0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
0.2
—
0.2
—
0.2
—
0.2
—
CQ, CQ High Output Hold
–0.2
–0.2
–0.2
–0.2
–0.2
–0.2
–0.2
–0.2
CQ, CQ High to QVLD
0.2
0.2
0.2
0.2
tCQHCQH
tCQHCQH
CQ Phase Distortion
1.0
—
1.08
—
1.25
—
1.40
—
ns
tKHQZ
K Clock High to Data Output High-Z
—
0.45
—
—
0.45
—
—
0.45
—
—
0.45
—
ns
ns
tKHQX1
K Clock High to Data Output Low-Z
Setup Times
–0.45
–0.45
–0.45
–0.45
tAVKH
tIVKH
Address Input Setup Time
0.4
0.4
—
—
0.4
0.4
—
—
0.4
0.4
—
—
0.4
0.4
—
—
ns
ns
1
2
Control Input Setup Time
(R, W)
Control Input Setup Time
(BWX)
tIVKH
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
ns
ns
3
tDVKH
Data Input Setup Time
Hold Times
tKHAX
tKHIX
Address Input Hold Time
0.4
0.4
—
—
0.4
0.4
—
—
0.4
0.4
—
—
0.4
0.4
—
—
ns
ns
1
2
Control Input Hold Time
(R, W)
Control Input Hold Time
(BWX)
tKHIX
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
ns
ns
3
tKHDX
Data Input Hold Time
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W.
3. Control singles are BW0, BW1 and (BW2, BW3 for x36).
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V and input clock are stable.
V
DD
DD
Rev: 1.02b 6/2010
20/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Rev: 1.02b 6/2010
21/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Rev: 1.02b 6/2010
22/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Rev: 1.02b 6/2010
23/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DD
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the
falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state
machine. An undriven TMS input will produce the same result as a logic one input level.
TMS
TDI
Test Mode Select
Test Data In
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed
between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP
In Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to
the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input
level.
Output that is active depending on the state of the TAP state machine. Output changes in response to the
falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
TDO
Test Data Out
Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Rev: 1.02b 6/2010
24/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
GSI Technology
See BSDL Model
JEDEC Vendor
ID Code
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
0
8
1
7
1
6
0
5
1
4
1
3
0
2
0
1
1
0
1
Bit #
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
Rev: 1.02b 6/2010
25/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
Rev: 1.02b 6/2010
26/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
SAMPLE-Z
010
1
GSI
SAMPLE/PRELOAD
GSI
011
100
101
110
111
GSI private instruction.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
GSI private instruction.
1
1
1
1
1
GSI
GSI private instruction.
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.02b 6/2010
27/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
VILJ
Min.
–0.3
Max.
Unit Notes
0.3 * VDD
VDD +0.3
Test Port Input Low Voltage
V
V
1
1
VIHJ
0.7 * VDD
Test Port Input High Voltage
IINHJ
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
–300
–1
1
100
1
uA
uA
uA
V
2
IINLJ
3
IOLJ
–1
4
VOHJ
VOLJ
VOHJC
VOLJC
VDD – 0.2
—
0.2
—
0.1
5, 6
5, 7
5, 8
5, 9
—
V
VDD – 0.1
V
—
V
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < V
+1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
ILJn
3. 0 V ≤ V ≤ V
IN
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V supply.
DD
6.
7.
8.
9.
I
I
I
I
= –2 mA
OHJ
= + 2 mA
OLJ
= –100 uA
= +100 uA
OHJC
OLJC
JTAG Port AC Test Conditions
Parameter
Input high level
Input low level
Conditions
JTAG Port AC Test Load
VDD – 0.2 V
TDO
0.2 V
*
Input slew rate
1 V/ns
50Ω
30pF
V
DD/2
Input reference level
V
/2
DD
VDD/2
Output reference level
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.02b 6/2010
28/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
TDI
tTH
tTH
tTS
tTS
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
Max
—
Unit
ns
TCK Cycle Time
50
—
20
20
10
10
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
ns
ns
—
ns
—
ns
tTH
—
ns
Rev: 1.02b 6/2010
29/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Package Dimensions—165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.60 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
15±0.05
B
0.20(4x)
SEATING PLANE
C
Ordering Information—GSI SigmaQuad-II+ SRAM
Speed
(MHz)
2
1
Org
Type
Package
T
Part Number
A
16M x 8
16M x 8
16M x 8
16M x 8
16M x 8
GS81302D07E-400
GS81302D07E-375
GS81302D07E-333
GS81302D07E-300
GS81302D07E-400I
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
400
375
333
300
400
C
C
C
C
I
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS81302DxxE-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.02b 6/2010
30/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Ordering Information—GSI SigmaQuad-II+ SRAM (Continued)
Speed
(MHz)
2
1
Org
Type
Package
T
Part Number
A
16M x 8
16M x 8
16M x 8
16M x 8
16M x 8
16M x 8
16M x 8
16M x 8
16M x 8
16M x 8
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
16M x 9
8M x 18
8M x 18
8M x 18
8M x 18
8M x 18
GS81302D07E-375I
GS81302D07E-333I
GS81302D07E-300I
GS81302D07GE-400
GS81302D07GE-375
GS81302D07GE-333
GS81302D07GE-300
GS81302D07GE-400I
GS81302D07GE-375I
GS81302D07GE-333I
GS81302D07GE-300I
GS81302D10E-400
GS81302D10E-375
GS81302D10E-333
GS81302D07E-300
GS81302D10E-400I
GS81302D10E-375I
GS81302D10E-333I
GS81302D10E-300I
GS81302D10GE-400
GS81302D10GE-375
GS81302D10GE-333
GS81302D10GE-300
GS81302D10GE-400I
GS81302D10GE-375I
GS81302D10GE-333I
GS81302D10GE-300I
GS81302D19E-400
GS81302D19E-375
GS81302D19E-333
GS81302D19E-300
GS81302D19E-400I
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
165-bump BGA
165-bump BGA
375
333
300
400
375
333
300
400
375
333
300
400
375
333
300
400
375
333
300
400
375
333
300
400
375
333
300
400
375
333
300
400
I
I
165-bump BGA
I
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
165-bump BGA
C
C
C
C
I
I
I
I
C
C
C
C
I
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
I
165-bump BGA
I
165-bump BGA
I
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
165-bump BGA
C
C
C
C
I
I
I
I
C
C
C
C
I
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS81302DxxE-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.02b 6/2010
31/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
Ordering Information—GSI SigmaQuad-II+ SRAM (Continued)
Speed
(MHz)
2
1
Org
Type
Package
T
Part Number
A
8M x 18
8M x 18
8M x 18
8M x 18
8M x 18
8M x 18
8M x 18
8M x 18
8M x 18
8M x 18
8M x 18
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
4M x 36
GS81302D19E-375I
GS81302D19E-333I
GS81302D19E-300I
GS81302D19AGE-400
GS81302D19AGE-375
GS81302D19GE-333
GS81302D19GE-300
GS81302D19GE-400I
GS81302D19GE-375I
GS81302D19GE-333I
GS81302D19GE-300I
GS81302D37E-400
GS81302D37AE-375
GS81302D37E-333
GS81302D37E-300
GS81302D37E-400I
GS81302D37E-375I
GS81302D37E-333I
GS81302D37E-300I
GS81302D37GE-400
GS81302D37GE-375
GS81302D37GE-333
GS81302D37GE-300
GS81302D37GE-400I
GS81302D37GE-375I
GS81302D37GE-333I
GS81302D37GE-300I
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
SigmaQuad-II+ B4 SRAM
165-bump BGA
165-bump BGA
375
333
300
400
375
333
300
400
375
333
300
400
375
333
300
400
375
333
300
400
375
333
300
400
375
333
300
I
I
165-bump BGA
I
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
165-bump BGA
C
C
C
C
I
I
I
I
C
C
C
C
I
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
I
165-bump BGA
I
165-bump BGA
I
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
C
C
C
C
I
I
I
I
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS81302DxxE-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.02b 6/2010
32/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS81302D07/10/19/37E-400/375/333/300
SigmaQuad-II+ SRAM Revision History
File Name
Format/Content
Description of changes
81302Dxx_r1
Creation of datasheet
• Revised Pinout
• Revised JTAG Port AC Test Condtions;
• Corrected Ordering Information Table
• Updated 165 BGA Package Drawing
• Revised AC Electrical Characteristics Table
• Added On-Die Termination feature
• (Rev1.01a: Corrected TM reference in page 1 banner)
GS81302Dxx_r1.01
Content
• Rev1.01 n/a for Q
GS81302Dxx_r1.01
81302Dxx_r1.02
• Corrected QVLD typo in AC Char table
Added QVLD max numbers in AC Char table
(Rev1.02b: removed CQ reference from SAMPLE-Z section in
JTAG Tap Instruction Set Summary)
Rev: 1.02b 6/2010
33/33
© 2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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