GS8150V36AGB-357IT [GSI]
Late-Write SRAM, 512KX36, 1.4ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119;型号: | GS8150V36AGB-357IT |
厂家: | GSI TECHNOLOGY |
描述: | Late-Write SRAM, 512KX36, 1.4ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119 静态存储器 内存集成电路 |
文件: | 总23页 (文件大小:327K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
GS8150V36AB-357/333/300/250
250 MHz–357 MHz
119-Bump BGA
Commercial Temp
Industrial Temp
512K x 36
1.8 V V
DD
18Mb Register-Register Late Write SRAM 1.5 V or 1.8 V HSTL I/O
Features
Functional Description
• Register-Register Late Write mode, Pipelined Read mode
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• ZQ controlled programmable output drivers
• Dual Cycle Deselect
Because GS8150V36A is a synchronous device, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
• Fully coherent read and write pipelines
• Byte write operation (9-bit bytes)
• Differential HSTL clock inputs, K and K
• Asynchronous output enable
• Sleep mode via ZZ
GS8150V36A supports pipelined reads utilizing a rising-edge-
triggered output register. It also utilizes a Dual Cycle Deselect
(DCD) output deselect protocol.
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• JEDEC-standard 119-bump BGA package
• RoHS-compliant 119-bump BGA package available
GS8150V36A is implemented with high performance HSTL
technology and is packaged in a 119-bump BGA.
Family Overview
Mode Control
GS8150V36A is a 18,874,368-bit (18Mb) high performance
SRAM. This family of wide, very low voltage HSTL I/O
SRAMs is designed to operate at the speeds needed to
implement economical high performance cache systems.
There are two mode control select pins (M1 and M2), which
allow the user to set the correct read protocol for the design.
The GS8150V36A supports single clock Pipeline mode, which
directly affects the two mode control select pins. In order for
the part to fuction correctly, and as specified, M1 must be tied
to V and M2 must be tied to V or V . This must be set
SS
DD
DDQ
at power-up and should not be changed during operation.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Parameter Synopsis
-357
-333
-300
-250
Unit
Pipeline
Cycle
tKHQV
2.8
1.4
3.0
1.5
3.3
1.6
4.0
2.0
ns
ns
Curr (x36)
650
600
550
500
mA
Rev: 1.09 1/2013
1/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
GS8150V36 Pinout—119-Bump BGA—Top View (Package B)
1
2
3
A
4
NC
NC
VDD
ZQ
SS
G
5
A
6
7
VDDQ
NC
A
A
VDDQ
NC
A
B
C
D
E
F
A
A
A
A
NC
A
A
A
A
NC
DQC
DQC
VDDQ
DQC
DQC
VDDQ
DQD
DQD
VDDQ
DQD
DQD
NC
DQC
DQC
DQC
DQC
DQC
VDD
DQD
DQD
DQD
DQD
DQD
A
VSS
VSS
VSS
BC
VSS
VSS
VSS
BB
DQB
DQB
DQB
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQA
A
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
DQA
NC
NC
NC
VDD
CK
CK
SW
A
G
H
J
VSS
VREF
VSS
BD
VSS
VREF
VSS
BA
K
L
VSS
VSS
VSS
M1
A
VSS
VSS
VSS
M2
A
M
N
P
R
T
A
VDD
NC
NC
A
NC
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
U
Rev: 1.09 1/2013
2/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
GS8150V36A BGA Pin Description
Symbol
Type
Description
I
Address Inputs
A
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
BA, BB, BC, BD
NC
CK
CK
SW
G
Clock Input Signal; active high
Clock Input Signal; active low
Write Enable; active low
I
I
I
Output Enable; active low
I
Sleep mode control; active high
ZZ
Read Operation Protocol Select—Selects Register-Register read operations; must be tied low in this
device
I
I
M1
M2
Read Operation Protocol Select—Selects Register-Register read operations; must be tied high in this
device
I
I
FLXDrive-II™ Output Impedance Control
Synchronous Select Input
Scan Test Mode Select
Scan Test Data In
ZQ
SS
I
TMS
TDI
I
O
I
Scan Test Data Out
TDO
TCK
Scan Test Clock
V
I
Input Reference Voltage
REF
V
I
I
I
Core power supply
I/O and Core Ground
DD
V
SS
V
Output driver power supply
DDQ
Rev: 1.09 1/2013
3/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
Read Operations
Pipelined Read
A read cycle begins when the RAM captures logic 0 on SS and logic 1 on SW at the rising edge of K (and the falling edge of K).
Address inputs captured on that clock edge are propigated into the RAM, which delivers data to the input of the output registers.
The second rising edge of K fires the output registers and releases read data to the output drivers. If G is held active low, the
drivers drive the data onto the output pins. Read data is sustained on the output pins as long as G is held low or until the next rising
edge of K, at which point the outputs may update to new data or deselect, depending on what control command was registered at
the second rising edge of K.
Dual Cycle Deselect
Chip deselect (SS = logic 1) is pipelined to the same degree as read data. Therefore, a deselect command entered on the rising edge
of K is acted upon in response to the next rising edge of K.
Write Operations
Write operations are initiated when the write enable input signal (SW) and chip select (SS) are captured at logic 0 on a rising edge
of the K clock (and falling edge of the K clock).
Late Write
In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late
Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT
SRAMs.
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Byte write control
inputs are captured by the same clock edge used to capture SW.
Example of x36 Byte Write Truth Table
Function
SW
H
L
Ba
X
Bb
X
Bc
X
Bd
X
Read
Write Byte A
L
H
L
H
H
L
H
H
H
L
Write Byte B
L
H
H
H
L
Write Byte C
L
H
H
L
Write Byte D
Write all Bytes
L
H
L
L
L
Write Abort
L
H
H
H
H
FLXDrive-II™ HSTL Output Driver Impedance Control
HSTL I/O SigmaRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V via an
SS
external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value
of the desired SRAM driver impedance. The allowable range of RQ to guarantee impedance matching with specified tolerance is
between 150Ω and 300Ω. Periodic readjustment of the output driver impedance occurs automatically because driver impedance is
affected by drifts in supply voltage and die temperature. A clock cycle counter periodically triggers an impedance evaluation,
resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the
optimum level. The output driver is implemented with discrete binary weighted impedance steps. The SRAM requires 32K start-up
clock cycles, selected or deselected, after VDD reaches its operating range to reach its programmed output driver impedance.
Rev: 1.09 1/2013
4/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
Register-Register Late Write, Pipelined Read Truth Table
DQ
DQ
CK
ZZ
SS
SW Bx
G
Current Operation
(t )
(t
)
n
n+1
Hi-Z
Hi-Z
Hi-Z
X
↑
↑
1
0
0
0
X
1
0
0
X
X
1
1
X
X
X
X
X
X
1
0
Sleep (Power Down) mode
Hi-Z
***
Deselect
Read
Hi-Z/
***
Q(t )
↑
↑
↑
Read
n
D(t )
0
0
0
0
0
0
0
0
0
0
X
1
X
X
X
Write All Bytes
Write Bytes with Bx = 0
Write (Abort)
***
***
***
n
D(t )
n
↑
Hi-Z
Notes:
1. If one or more Bx = 0, then B = “T” else B = “F”.
2. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”.
3. “***” indicates that the DQ input requirement/output state and CQ output state are determined by the previous operation.
4. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
5. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
6. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces
of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
Rev: 1.09 1/2013
5/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
Voltage on V Pins
–0.5 to 2.5
V
V
DD
DD
V
Voltage in V
Pins
DDQ
–0.5 to 2.4
DDQ
V
–0.5 to V
+ 0.5 (≤ 2.5 V max.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
V
I/O
V
–0.5 to V + 0.5 (≤ 2.5 V max.)
DDQ
V
IN
I
+/–100
+/–100
125
mA dc
mA dc
IN
I
OUT
o
T
Maximum Junction Temperature
Storage Temperature
C
J
T
–55 to 125
ºC
STG
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Supply Voltage
Symbol
Min.
1.7
Typ.
1.8
Max.
1.95
1.95
1.6
Unit
Notes
V
V
V
V
DD
V
1.8 V I/O Supply Voltage
1.5 V I/O Supply Voltage
1.7
1.8
1
1
DDQ
V
1.4
1.5
DDQ
Ambient Temperature
(Commercial Range Versions)
T
0
25
25
70
85
°C
°C
A
Ambient Temperature
(Industrial Range Versions)
T
–40
2
A
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ V
≤ 1.6 V (i.e., 1.5 V I/O)
DDQ
and 1.7 V ≤ V
≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.
DDQ
2. The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 1.09 1/2013
6/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
HSTL I/O DC Input Characteristics
Parameter
DC Input Logic High
Symbol
Min
Typ
—
Max
Units Notes
V
(dc)
V
+ 100
V
+ 300
DDQ
mV
mV
IH
REF
V (dc)
V
V
– 100
+ 300
DC Input Logic Low
–300
100
—
IL
REF
V
(dc)
(dc)
(dc)
(dc)
DC Clock Input Differential Voltage
—
mV
V
2
1
DIF
DDQ
V
DC Voltage
V
V
/2 – 0.1
V
DDQ
/2 + 0.1
+ 300
—
REF
REF
DDQ
V
V
DDQ
Clock Input Voltag
–300
600
—
V
CK
V
Clock Input Commone Mode Voltage
750
900
V
CM
Notes:
1. The peak to peak AC component superimposed on V
may not exceed 5% of the DC component of V
.
REF
REF
2. SRAM performance is a function of clock input differential voltage (V ).
DIF
3. To guarantee AC characteristics, V ,V ,Trise and Tfall of inputs and clocks must be within 10% of each other.
IH IL
4. For devices supplied with HSTL I/O input buffers.Compatible with both 1.8 V and 1.5 V I/O drivers.
5. See AC Input Definition drawing below.
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units
mV
Notes
3,4
V
(ac)
V
+ 200
REF
AC Input Logic High
—
IH
V (ac)
V
– 200
REF
AC Input Logic Low
—
800
—
mV
3,4
IL
V
(ac)
(ac)
AC Clock Input Differential Voltage
—
mV
2,3
DIF
V
Peak to Peak AC Voltage
V
5% V
(DC)
REF
mV
1
REF
REF
Notes:
1. The peak to peak AC component superimposed on V
may not exceed 5% of the DC component of V
.
REF
REF
2. SRAM performance is a function of clock input differential voltage (V ). The RAM can be operated with a single ended clocking with
DIF
either CK or CK tied to V
.
REF
3. To guarantee AC characteristics, V ,V ,Trise and Tfall of inputs and clocks must be within 10% of each other.
IH IL
4. For devices supplied with HSTL I/O input buffers.Compatible with both 1.8 V and 1.5 V I/O drivers.
5. See AC Input Definition drawing below.
Rev: 1.09 1/2013
7/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
HSTL I/O AC Input Definitions
V
DDQ
V
(AC)
(DC)
IH
V
IH
V
REF
V
(DC)
(AC)
IL
V
IH
V
SS
Differential Voltage and Common Mode Voltage
Common Mode and Differential Voltage
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
VCM
K
K#
VCM
VDIF
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
Rev: 1.09 1/2013
8/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 1.0 V
50%
DD
V
SS
50%
V
DD
V
– 1.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 1.8 V)
A
DD
Parameter
Symbol
Test conditions
Max.
Unit
pF
C
V
= 0 V
= 0 V
Input Capacitance
4
5
5
IN
IN
C
V
OUT
Output Capacitance
pF
OUT
C
V = 0 V
IN
Output Capacitance (Clock)
pF
IN(CK)
Note:
This parameter is sample tested.
AC Test Conditions
Parameter
Conditions
1.25 V
Input high level
Input low level
0.25 V
Input rise/fall time (10% to 90%)
Input reference level
0.5 ns/0.5 ns
V
/2
DDQ
Clock input reference level
Output reference level
Differential cross point
/2
V
DDQ
Clock (V
Clock (V
V
)
0.75 V
0.75 V
1.5 V
DIF
)
CM
DDQ
RQ
250Ω
Rev: 1.09 1/2013
9/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
AC Test Load Diagram
50Ω
Device Under Test
V
/2
50Ω
50Ω
DDQ
V
= 1.5 V
DDQ
5pF
25Ω
V
/2
DDQ
50Ω
ZQ
V
/2
DDQ
5pF
RQ = 250Ω
Input and Output Leakage Characteristics
Parameter
Symbol
Test Conditions
Min.
Max
Notes
Input Leakage Current
(except mode pins)
I
V
= 0 to V
–2 uA
2 uA
—
IL
IN
DDQ
ZQ, MCH, MCL, EP2, EP3
Pin Input Current
I
V
= 0 to V
–50 uA
–2 uA
50 uA
2 uA
—
—
INM
IN
DDQ
Output Disable,
= 0 to V
I
Output Leakage Current
OL
V
OUT
DDQ
Operating Currents
-357
-333
-300
–40°C
-250
–40°C
0°C
to
–40°C
to
0°C
to
–40°C
to
0°C
to
0°C
to
Parameter Config. Symbol
Test Conditions
to
to
70°C
+85°C
70°C
+85°C
70°C
+85°C
70°C
+85°C
SS ≤ VIL Max.
Operating
Current
tKHKH ≥ tKHKH Min.
All other inputs
IDD
x36
—
650 mA 660 mA 600 mA 610 mA 550 mA 560 mA 500 mA 510 mA
VIL ≥ VIN ≥ VIH
Device Deselected
All inputs
VSS + 0.10 V
HSTL
Deselect
Current
IDD3
150 mA 160 mA 150 mA 160 mA 150 mA 160 mA 150 mA 160 mA
≥ VIN
≥
VDD – 0.10 V
Rev: 1.09 1/2013
10/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
AC Electrical Characteristics
-357
Min
-333
Min
-300
Min
-250
Min
Parameter
Symbol
Unit Notes
Max
—
Max
—
Max
—
Max
—
Clock Cycle Time
Clock High Time
tKHKH
tKHKL
tKLKH
tKHQX1
tKHQV
tKHQX
tKHQZ
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tBVKH
tKHBX
tDVKH
tKHDX
tGLQV
tGLQX
tGHQZ
tZZE
2.8
1.1
1.1
0.5
—
3.0
1.2
1.2
0.5
—
3.3
1.3
1.3
0.5
4.0
1.5
1.5
0.5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
1
—
—
—
—
Clock Low Time
—
—
—
—
Clock High to Output Low-Z
Clock High to Output Valid
Clock High to Output Invalid
Clock High to Output High-Z
Address Valid to Clock High
Clock High to Address Don’t Care
Enable Valid to Clock High
Clock High to Enable Don’t Care
Write Valid to Clock High
—
—
—
—
1.4
—
1.5
—
1.6
—
2.0
—
—
—
1
0.5
—
0.5
—
0.5
0.5
—
1.4
—
1.5
—
1.6
—
2.0
—
0.5
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
0.4
—
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.5
0.4
—
0.7
0.4
0.7
0.4
0.7
0.4
0.7
0.4
0.5
0.4
0.8
0.5
0.8
0.5
0.8
0.5
0.8
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Clock High to Write Don’t Care
Byte Write Valid to Clock High
Clock High to Byte Write Don’t Care
Data In Valid to Clock High
Clock High to Data In Don’t Care
Output Enable Low to Output Data Valid
Output Enable Low to Output Data Low-Z
Output Enable High to Output Data High-Z
Sleep Mode Enable Time
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.4
—
1.5
—
1.6
—
2.0
—
0
0
0
0
—
1.4
15
—
—
1.5
15
—
1.6
15
—
—
2.0
15
—
—
—
—
—
Sleep Mode Recovery Time
Notes:
tZZR
20
20
20
20
1. Measured at 100 mV from steady state. Not 100% tested.
2. Guaranteed by design. Not 100% tested.
Rev: 1.09 1/2013
11/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
G Controlled Read-Write
Read A1
KHKL
Read A2
Read A0
Write A3
Write A4
Read A5
Read A4
Read A6
Read A7
KHKH
KLKH
K
tAVKH
tKHAX
A1
A2
A0
A3
A4
A5
A4
A6
A7
A
G
tWVKH
tKHWX
SW
tWVKH
tKHWX
BWx
KHQX
GLQV
GLQX
Q1
DVKH
KHDX
KHQV
GHQZ
KHQX1
Q2
D3
D4
Q5
Q4
Q6
DQn
Note:
K is not shown; assumes K tied to V
or out of phase with K
REF
SS Controlled Read-Write
Read A1
KHKL
Read A2
Deselect
Write A3
Write A4
Read A5
Read A4
Read A6
Read A7
KHKH
KLKH
K
A
tAVKH
tKHAX
A1
A2
A3
A4
A5
A4
A6
A7
tEVKH
tKHEX
SS
tWVKH
tKHWX
SW
BWx
DQn
tBVKH
tKHBX
KHQZ
tDVKH
tKHDX
KHQX1
Q1
KHQV
Q2
KHQX
Q4
D3
D4
Q5
Note:
K is not shown; assumes K tied to V
or out of phase with K
REF
Rev: 1.09 1/2013
12/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
ZZ Timing
Read A1
KHKL
Read A2
Deselect
Clock is a Don't care during Sleep ModeRead A1
Read A2
Read A3
KHKH
KLKH
K
A
tAVKH
tKHAX
A1
A2
A1
A2
A3
tEVKH
tKHEX
SS
tWVKH
tKHWX
SW
SWx
Begin ISB
ZZR
ZZ
ZZE
Q2
KHQX
KHQX1
Q1
KHQV
Q1
DQn
Note:
K is not shown; assumes K tied to V
or out of phase with K
REF
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
Rev: 1.09 1/2013
13/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
JTAG Port Registers
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Rev: 1.09 1/2013
14/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.09 1/2013
15/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
Tap Controller Instruction Set
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
I/O
Configuration
Not Used
ID Code
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
1
1
x36
x18
X
X
X
X
X
X
X
X
0
0
0
0
0
0
X
X
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.09 1/2013
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GS8150V36AB-357/333/300/250
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
1
1
Exit2 DR
Exit2 IR
0
0
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Rev: 1.09 1/2013
17/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.09 1/2013
18/23
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
DQ
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
*
50Ω
30pF
Input slew rate
V
/2
V
V
/2
Input reference level
DDQ
DDQ
* Distributed Test Jig Capacitance
/2
Output reference level
DDQ
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
RFU
010
011
TDO.
1
1
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
100
101
110
111
1
1
1
1
GSI
RFU
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.09 1/2013
19/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
TDI
tTH
tTS
tTH
tTS
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
50
—
Max
—
Unit
ns
TCK Cycle Time
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
ns
20
20
10
10
ns
—
ns
—
ns
tTH
—
ns
Rev: 1.09 1/2013
20/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
TOP VIEW
BOTTOM VIEW
A1
A1
S
Ø0.10
C
S
S
S
Ø0.30 C A
B
Ø0.60~0.90 (119x)
1
2
3
4
5
6
7
7
6
5
4 3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
M
N
P
R
T
U
K
L
M
N
P
R
T
U
B
1.27
7.62
14±0.10
A
0.20(4x)
SEATING PLANE
C
Rev: 1.09 1/2013
21/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
Ordering Information
Speed
(MHz)
2
1
Org
Type
T
Part Number
A
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
GS8150V36AB-357
GS8150V36AB-333
GS8150V36AB-300
GS8150V36AB-250
GS8150V36AB-357I
GS8150V36AB-333I
GS8150V36AB-300I
GS8150V36AB-250I
GS8150V36AGB-357
GS8150V36AGB-333
GS8150V36AGB-300
GS8150V36AGB-250
GS8150V36AGB-357I
GS8150V36AGB-333I
GS8150V36AGB-300I
GS8150V36AGB-250I
Register-Register Late Write SRAM
Register-Register Late Write SRAM
357MHz
333 MHz
300 MHz
250 MHz
357 MHz
333 MHz
300 MHz
250 MHz
357MHz
333 MHz
300 MHz
250 MHz
357 MHz
333 MHz
300 MHz
250 MHz
C
C
C
C
I
Register-Register Late Write SRAM
Register-Register Late Write SRAM
Register-Register Late Write SRAM
Register-Register Late Write SRAM
I
Register-Register Late Write SRAM
I
Register-Register Late Write SRAM
I
RoHS-compliant Register-Register Late Write SRAM
RoHS-compliant Register-Register Late Write SRAM
RoHS-compliant Register-Register Late Write SRAM
RoHS-compliant Register-Register Late Write SRAM
RoHS-compliant Register-Register Late Write SRAM
RoHS-compliant Register-Register Late Write SRAM
RoHS-compliant Register-Register Late Write SRAM
RoHS-compliant Register-Register Late Write SRAM
C
C
C
C
I
I
I
512K x 36
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8150V36AB-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.09 1/2013
22/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8150V36AB-357/333/300/250
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
8150VxxA_r1
• Corrected L3 from VSS to NC
• Updated entire format
• Placed corrected BGA diagram in document
8150VxxA_r1;
8150VxxA_r1_01
Content/Format
• Updated format
• Added variation information to 119 BGA mechanical drawing
8150VxxA_r1_01;
8150VxxA_r1_02
Content/Format
Content
• Updated AC Characteristics table
• Updated /G Controlled Read-Write timing diagram
8150VxxA_r1_02;
8150VxxA_r1_03
• Pb-free information added
8150VxxA_r1_03;
8150VxxA_r1_04
Content
• Changed V to max 3.6 V for 8150xxA
8150VxxA_r1_04;
8150VxxA_r1_05
DD
Content
• Updated Abs Max section
• Changed all Pb-free references to RoHS-compliant
8150VxxA_r1_05;
8150VxxA_r1_06
Content
• Updated Power Supplies table on page 7
• Updated for MP status
8150VxxA_r1_06;
8150VxxA_r1_07
Content
8150VxxA_r1_07;
8150VxxA_r1_08
Content
• Removed x18 configuration
8150VxxA_r1_08;
8150VxxA_r1_08
Content
Rev: 1.09 1/2013
23/23
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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