GS8160EV18AGT-300IT [GSI]
Cache SRAM, 1MX18, 5ns, CMOS, PQFP100, TQFP-100;
| 型号： | GS8160EV18AGT-300IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Cache SRAM, 1MX18, 5ns, CMOS, PQFP100, TQFP-100 静态存储器 |
| 文件： | 总24页 (文件大小：490K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
350 MHz–150 MHz
100-Pin TQFP
Commercial Temp
Industrial Temp
1M x 18, 512K x 32, 512K x 36
1.8 V VDD
1.8 V I/O
18Mb Sync Burst SRAMs
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edge-
triggered Data Output Register.
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
DCD Pipelined Reads
The GS8160EV18/32/36AT is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS8160EV18/32/36AT is an 18,874,368-bit (16,777,216-
bit for x32 version) high performance synchronous SRAM
with a 2-bit burst address counter. Although of a type
originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Controls
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
Core and Interface Voltages
The GS8160EV18/32/36AT operates on a 1.8 V power supply.
All input are 1.8 V compatible. Separate output power (V
)
DDQ
pins are used to decouple output noise from the internal circuits
and are 1.8 V compatible.
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
Parameter Synopsis
-350 -333 -300 -250 -200 -150 Unit
tKQ
1.8
2.85
2.0
3.0
2.2
3.3
2.3
4.0
2.7
5.0
3.3
6.7
ns
ns
tCycle
Pipeline
3-1-1-1
395
455
370
430
335
390
280
330
230
270
185
210
mA
mA
Curr (x18)
Curr (x32/x36)
tKQ
4.5
4.5
4.7
4.7
5.0
5.0
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
Flow
Through
2-1-1-1
tCycle
270
305
250
285
230
270
210
240
185
205
170
190
mA
mA
Curr (x18)
Curr (x32/x36)
Rev: 1.00a 6/2003
1/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
GS8160EV18A 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
NC
2
NC
DDQ
3
V
4
DDQ
SS
V
NC
V
5
SS
NC
NC
6
DQPA
DQA
DQA
7
DQB
DQB
V
8
9
1M x 18
Top View
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
DDQ
SS
V
DDQ
DQA
DQB
DQA
DQB
FT
V
SS
NC
V
DD
V
NC
DD
ZZ
V
SS
DQA
DQA
DQB
DQB6
V
V
V
DD
DDQ
SS
V
SS
DQA
DQA
NC
DQB
DQB
DQPB
NC
NC
V
V
SS
DDQ
SS
V
V
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00a 6/2003
2/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
GS8160EV32A 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
DQB
DQB
V
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
DDQ
3
V
4
DDQ
V
V
5
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
6
7
8
9
512K x 32
Top View
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
DDQ
SS
V
V
DDQ
DQB
DQC
DQB
DQC
FT
V
SS
NC
V
DD
V
NC
DD
ZZ
V
SS
DQA
DQA
V
DQD
DQD
V
DDQ
DDQ
SS
V
V
SS
DQA
DQA
DQA
DQA
DQD3
DQD
DQD
DQD
V
V
V
SS
DDQ
SS
V
DDQ
DQA
DQA
NC
DQD
DQD
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00a 6/2003
3/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
GS8160EV36A 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPB
DQB
DQPC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQB
DQC
3
V
V
V
4
DDQ
DDQ
SS
V
5
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
6
7
8
9
512K x 36
Top View
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
DDQ
SS
V
V
DDQ
DQB
DQC
DQB
DQC
FT
V
SS
NC
V
DD
NC
SS
V
DD
ZZ
V
DQA
DQA
DQD
DQD
V
V
V
DDQ
DDQ
SS
V
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
DDQ
SS
V
V
DDQ
DQA
DQD
DQA
DQD
DQPA
DQPD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00a 6/2003
4/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
TQFP Pin Description
Symbol
A0, A1
A
Type
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
I
I
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
NC
—
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Clock Input Signal; active high
BW
I
I
I
I
I
I
I
I
I
I
I
I
I
BA, BB, BC, BD
CK
GW
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
E1
E2
Chip Enable; active high
E3
Chip Enable; active low
G
ADV
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
ADSP, ADSC
ZZ
LBO
Linear Burst Order mode; active low
Core power supply
V
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 1.00a 6/2003
5/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
GS8160EV18/32/36A Block Diagram
RegisteQr
A0–An
D
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
A
Load
LBO
ADV
CK
Memory
Array
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
36
36
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
FT
G
0
Power Down
Control
DQx1–DQx9
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.00a 6/2003
6/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Mode Pin Functions
Mode Name
Pin
Name
State
Function
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Burst Order Control
LBO
H
L
Output Register Control
FT
H or NC
L or NC
H
Active
Power Down Control
Note:
ZZ
Standby, I = I
DD SB
There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00a 6/2003
7/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
Read
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.00a 6/2003
8/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Synchronous Truth Table
Operation
State
Address
Used
2
3
4
Diagram
E1
ADSP ADSC ADV
E
W
DQ
5
Key
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
None
None
X
X
H
L
X
X
L
L
X
L
X
X
X
X
X
X
L
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
F
F
T
T
T
X
X
X
X
X
X
X
X
High-Z
None
X
L
L
H
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.00a 6/2003
9/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)
control inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.00a 6/2003
10/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.00a 6/2003
11/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 3.6
DD
DD
V
Voltage in V
Pins
DDQ
–0.5 to 3.6
V
DDQ
V
–0.5 to V
+0.5 (≤ 3.6 V max.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
I/O
V
–0.5 to V +0.5 (≤ 3.6 V max.)
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Rev: 1.00a 6/2003
12/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Power Supply Voltage Ranges
Parameter
Symbol
Min.
1.6
Typ.
1.8
Max.
2.0
Unit
V
Notes
V
1.8 V Supply Voltage
DD1
1.8 V V
I/O Supply Voltage
V
1.6
1.8
2.0
V
DDQ
DDQ1
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
V
Range Logic Levels
Parameter
DDQ
Symbol
Min.
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
V
0.6*V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
DD
V
Input Low Voltage
V
0.3*V
DD
–0.3
—
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
0.6*V
V
+ 0.3
DDQ
—
1,3
1,3
DDQ
IHQ
DD
V
V
0.3*V
DD
–0.3
—
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Recommended Operating Temperatures
Parameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
°C
Notes
T
Ambient Temperature (Commercial Range Versions)
2
2
A
T
Ambient Temperature (Industrial Range Versions)
Note:
–40
25
85
°C
A
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.00a 6/2003
13/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
pF
I/O
Note: These parameters are sample tested.
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Input slew rate
V
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50Ω
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
Rev: 1.00a 6/2003
14/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
≥ V ≥ V
IN
–1 uA
–1 uA
1 uA
100 uA
DD
IH
IH
I
ZZ Input Current
FTInput Current
IN1
0 V ≤ V ≤ V
IN
V
≥ V ≥ V
IN
–100 uA
–1 uA
1 uA
1 uA
DD
IL
IL
I
IN2
0 V ≤ V ≤ V
IN
I
Output Disable, V
= 0 to V
Output Leakage Current
Output High Voltage
Output Low Voltage
–1 uA
– 0.4 V
DDQ
1 uA
—
OL
OUT
DD
V
I
= –4 mA, V
= 1.6 V
V
OH
OH
DDQ
V
I
= 4 mA, V = 1.6 V
OL DD
—
0.4 V
OL
Rev: 1.00a 6/2003
15/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Rev: 1.00a 6/2003
16/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
AC Electrical Characteristics
-350
-333
-300
-250
-200
-150
Parameter
Symbol
Unit
Min
Max
—
1.8
—
—
—
—
—
4.5
—
—
—
—
—
Min
Max
—
2.0
—
—
—
—
—
4.7
—
—
—
—
—
Min
Max
—
2.2
—
—
—
—
—
5.0
—
—
—
—
—
Min
Max
—
2.3
—
—
—
—
—
5.5
—
—
—
—
—
Min
Max
—
2.7
—
—
—
—
—
6.5
—
—
—
—
—
Min
6.7
—
Max
—
3.3
—
—
—
—
—
7.5
—
—
—
—
—
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
2.85
—
3.0
—
3.3
—
4.0
—
5.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.0
1.0
1.0
0.1
4.5
—
1.0
1.0
1.0
0.1
4.7
—
1.0
1.0
1.0
0.1
5.0
—
1.0
1.0
1.2
0.2
5.5
—
1.0
1.0
1.4
0.4
6.5
—
1.0
1.0
1.5
0.5
7.5
—
Pipeline
tLZ1
tS
Hold time
tH
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
tKQX
3.0
3.0
1.3
0.3
1.0
3.0
3.0
1.4
0.4
1.0
3.0
3.0
1.4
0.4
1.3
3.0
3.0
1.5
0.5
1.3
3.0
3.0
1.5
0.5
1.3
3.0
3.0
1.5
0.5
1.5
Flow
Through
tLZ1
tS
Hold time
tH
Clock HIGH Time
tKH
Clock LOW Time
tKL
1.2
1.0
—
1.2
1.0
—
1.5
1.0
—
1.5
1.0
—
1.5
1.0
—
1.7
1.0
—
ns
ns
Clock to Output in
High-Z
tHZ1
1.8
2.0
2.2
2.3
2.7
3.0
G to Output Valid
G to output in Low-Z
G to output in High-Z
ZZ setup time
tOE
—
0
1.8
—
1.8
—
—
—
—
0
2.0
—
2.0
—
—
—
—
0
2.2
—
2.2
—
—
—
—
0
2.3
—
2.3
—
—
—
—
0
2.7
—
2.7
—
—
—
—
0
3.3
—
3.0
—
—
—
ns
ns
ns
ns
ns
ns
tOLZ1
tOHZ1
tZZS2
tZZH2
tZZR
—
5
—
5
—
5
—
5
—
5
—
5
ZZ hold time
1
1
1
1
1
1
ZZ recovery
20
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.00a 6/2003
17/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Rev: 1.00a 6/2003
18/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Rev: 1.00a 6/2003
19/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs (like this one) do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.00a 6/2003
20/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
TQFP Package Drawing
θ
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
—
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
—
0.10
7°
θ
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.00a 6/2003
21/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
350/4.5
333/4.7
300/5
1M x 18
1M x 18
GS8160EV18AT-350
GS8160EV18AT-333
GS8160EV18AT-300
GS8160EV18AT-250
GS8160EV18AT-200
GS8160EV18AT-150
GS8160EV32AT-350
GS8160EV32AT-333
GS8160EV32AT-300
GS8160EV32AT-250
GS8160EV32AT-200
GS8160EV32AT-150
GS8160EV36AT-350
GS8160EV36AT-333
GS8160EV36AT-300
GS8160EV36AT-250
GS8160EV36AT-200
GS8160EV36AT-150
GS8160EV18AT-350I
GS8160EV18AT-333I
GS8160EV18AT-300I
GS8160EV18AT-250I
GS8160EV18AT-200I
GS8160EV18AT-150I
GS8160EV32AT-350I
GS8160EV32AT-333I
GS8160EV32AT-300I
GS8160EV32AT-250I
GS8160EV32AT-200I
GS8160EV32AT-150I
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
1M x 18
1M x 18
250/5.5
200/6.5
150/7.5
350/4.5
333/4.7
300/5
1M x 18
1M x 18
512K x 32
512K x 32
512K x 32
512K x 32
512K x 32
512K x 32
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
250/5.5
200/6.5
150/7.5
350/4.5
333/4.7
300/5
250/5.5
200/6.5
150/7.5
350/4.5
333/4.7
300/5
1M x 18
I
1M x 18
I
1M x 18
250/5.5
200/6.5
150/7.5
350/4.5
333/4.7
300/5
I
1M x 18
I
1M x 18
I
512K x 32
512K x 32
512K x 32
512K x 32
512K x 32
512K x 32
Notes:
I
I
I
250/5.5
200/6.5
150/7.5
I
I
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160EV18A-.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00a 6/2003
22/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
Notes:
GS8160EV36AT-350I
GS8160EV36AT-333I
GS8160EV36AT-300I
GS8160EV36AT-250I
GS8160EV36AT-200I
GS8160EV36AT-150I
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
350/4.5
333/4.7
300/5
I
I
I
I
I
I
250/5.5
200/6.5
150/7.5
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160EV18A-.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00a 6/2003
23/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160EV18/32/36AT-350/333/300/250/225/200/150
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
GS8160EVxxA_r1
Rev: 1.00a 6/2003
24/24
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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