GS820H32AT-4I [GSI]
64K x 32 2M Synchronous Burst SRAM; 64K ×32的2M同步突发SRAM
| 型号： | GS820H32AT-4I |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | 64K x 32 2M Synchronous Burst SRAM |
| 文件： | 总23页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS820H32AT/Q-150/138/133/117/100/66
150Mhz - 66Mhz
9ns - 18ns
3.3V VDD
3.3V & 2.5V I/O
TQFP, QFP
Commercial Temp
Industrial Temp
64K x 32
2M Synchronous Burst SRAM
Flow Through / Pipeline Reads
Features
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FP-
BGA). Holding the FT mode pin/bump low, places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
• FT pin for user configurable flow through or pipelined operation.
• Single Cycle Deselect (SCD) Operation.
• High Output Drive current.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or QFP package.
Pipelined Reads
The GS820H32A is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available. SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
-150
Pipeline tCycle 6.6ns 7.25ns 7.5ns 8.5ns 10ns 12.5ns
3-1-1-1 3.8ns 4ns 4ns 4.5 5ns 6ns
IDD 270mA 245mA 240mA 210mA 180mA 150mA
Flow tCycle 10.5ns 15ns 15ns 15ns 15ns 20ns
Through tKQ 9ns 9.7ns 10ns 11ns 12ns 18ns
2-1-1-1 IDD 170mA 120mA 120mA 120mA 120mA 95mA
-138
-133
-117
-100
-66
tKQ
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
Functional Description
The GS820H32A operates on a 3.3V power supply and all inputs/
outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ)
pins are used to de-couple output noise from the internal circuit.
Applications
The GS820H32A is a 2,097,152 bit high performance synchronous
SRAM with a 2 bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPU’s, the device now finds application in synchronous
SRAM applications ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Rev: 1.04 3/2000
1/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
E
GS820H32AT/Q-150/138/133/117/100/66
GS820H32A 100 Pin TQFP and QFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB8
DQB7
VDDQ
VSS
DQC8
DQC7
VDDQ
2
3
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
5
DQB6
DQB5
DQB4
DQB3
VSS
6
7
8
9
64K x 32
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQB2
DQB1
VSS
VDDQ
DQC2
DQC1
FT
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
VDDQ
DQD7
DQD8
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.04 3/2000
2/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
TQFP Pin Description
Pin Location
Symbol
Type
Description
37, 36
A0, A1
I
Address field LSB’s and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49
A2-15
I
Address Inputs
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8
I/O
Data Input and Output pins.
18, 19, 22, 23, 24, 25, 28, 29
16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30
NC
BW
No Connect
Byte Write. Writes all enabled bytes. Active Low.
Byte Write Enable for DQA, DQB Data I/O’s. Active Low.
Byte Write Enable for DQC, DQD Data I/O’s. Active Low.
Clock Input Signal. Active High.
87
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
93, 94
BA, BB
BC, BD
CK
95, 96
89
88
GW
Global Write Enable. Writes all bytes. Active Low.
Chip Enable. Active Low.
98, 92
E1, E3
E2
97
Chip Enable. Active High.
86
G
Output Enable. Active Low.
83
ADV
ADSP, ADSC
ZZ
Burst address counter advance enable. Active Low.
Address Strobe (Processor, Cache Controller). Active Low.
Sleep Mode control. Active High.
84, 85
64
14
31
FT
Flow Through or Pipeline mode. Active Low.
Linear Burst Order mode. Active Low.
Core power supply.
LBO
VDD
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
VSS
I/O and Core Ground.
VDDQ
Output driver power supply.
H
Rev: 1.04 3/2000
3/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
E
GS820H32AT/Q-150/138/133/117/100/66
GS820H32A Block Diagram
Register
A0-An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
32
32
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
FT
G
Power Down
Control
DQx1-DQx8
ZZ
Rev: 1.04 3/2000
4/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Mode Pin Functions
Mode Name
Pin Name State
Function
L
LBO
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Burst Order Control
H or NC
L
Output Register Control
FT
H or NC
L or NC
Active
Power Down Control
Note:
ZZ
Standby, I = I
H
DD SB
There are pull up devices on LBO and FT pins and a pull down device on and ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
B
A
B
B
B
C
B
D
Notes
1
X
X
X
X
Read
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte A
Write byte B
Write byte C
Write byte D
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.04 3/2000
5/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Synchronous Truth Table
State
2
3
4
Diagram
Operation
Address Used
E
1
ADSP ADSC ADV
E
W
DQ
5
Key
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Note:
None
None
X
X
H
L
X
F
F
T
T
T
X
X
X
X
X
X
X
X
X
L
L
X
L
X
X
X
X
X
X
L
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
None
X
L
L
H
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
1. X = Don’t Care, H = High, L = Low.
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.04 3/2000
6/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CR
CW
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
Rev: 1.04 3/2000
7/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.04 3/2000
8/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
-0.5 to 4.6
DD
DD
V
Voltage in V
Pins
-0.5 to V
DD
V
DDQ
DDQ
V
Voltage on Clock Input Pin
Voltage on I/O Pins
-0.5 to 6
-0.5 to V +0.5 (£ 4.6 V max.)
V
CK
I/O
V
V
V
DDQ
V
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
-0.5 to V +0.5 (£ 4.6 V max.)
IN
DD
I
+/- 20
+/- 20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
-55 to 125
-55 to 125
STG
BIAS
C
o
T
Temperature Under Bias
C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
Supply Voltage
3.135
2.375
1.7
3.3
2.5
---
3.6
V
V
DD
V
V
I/O Supply Voltage
Input High Voltage
Input Low Voltage
1
2
2
3
3
DDQ
DD
V
V +0.3
DD
V
IH
V
-0.3
0
---
0.8
V
IL
T
Ambient Temperature (Commercial Range Versions)
25
25
70
85
°C
°C
A
T
Ambient Temperature (Industrial Range Versions)
Note:
-40
A
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V £ VDDQ £ 2.375V (i.e. 2.5V I/O)
and 3.6V £ VDDQ £ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be -2V > Vi < V +2V with a pulse width not to exceed 20% tKC.
DD
Rev: 1.04 3/2000
9/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD+-2.0V
VSS
50%
VDD
50%
VSS-2.0V
20% tKC
VIL
Capacitance
o
(T =25 C, f=1MHZ, V =3.3V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
C
V =3.3V
DD
Control Input Capacitance
Input Capacitance
3
4
6
4
5
7
pF
pF
pF
I
C
V =0V
IN
IN
C
V
=0V
OUT
Output Capacitance
OUT
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating
Layer Board
Symbol
TQFP Max
QFP Max
Unit
Notes
R
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
single
four
40
24
9
TBD
TBD
TBD
°C/W
°C/W
°C/W
1,2,4
1,2,4
3,4
QJA
R
QJA
R
Junction to Case (TOP)
Notes:
QJC
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
4. For x18 configuration, consult factory.
Rev: 1.04 3/2000
10/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
AC Test Conditions
Parameter
Conditions
Input high level
Input low level
2.3V
0.2V
Input slew rate
1V/ns
Input reference level
Output reference level
Output load
1.25V
1.25V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t , t , t and t
.
OHZ
LZ HZ OLZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5V
Output Load 1
DQ
225W
225W
DQ
*
50W
VT=1.25V
30pF
*
5pF
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
-1uA
1uA
IL
V
³ V ³ V
-1uA
-1uA
1uA
300uA
DD
IN
IH
IH
I
ZZ Input Current
INZZ
0V £ V £ V
IN
V
³ V ³ V
-300uA
-1uA
1uA
1uA
DD
IN
IL
IL
I
Mode Pin Input Current
Output Leakage Current
INM
0V £ V £ V
IN
Output Disable,
= 0 to V
I
-1uA
1uA
OL
V
OUT
DD
V
I
= - 8mA, V =2.375V
Output High Voltage
Output High Voltage
Output Low Voltage
1.7V
2.4V
OH
OH
DDQ
V
I
= -8mA, V =3.135V
OH
OH
DDQ
V
I
= 8mA
OL
0.4V
OL
Rev: 1.04 3/2000
11/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Operating Currents
-150
-138
-133
Parameter
Test Conditions
Symbol
0 to 70°C
-40 to
85°C
0 to 70°C
-40 to
85°C
0 to 70°C
-40 to
85°C
IDD
Pipeline
Device Selected;
All other inputs
³ VIH or £ VIL
270mA
170mA
275mA
175mA
245mA
120mA
250mA
125mA
240mA
120mA
245mA
125mA
Operating
Current
IDD
Flow-Thru
Output open
Standby
Current
ISB
Flow-Thru
ZZ ³ VDD - 0.2V
10mA
15mA
10mA
15mA
10mA
15mA
IDD
Pipeline
90mA
45mA
95mA
50mA
80mA
40mA
85mA
45mA
80mA
40mA
85mA
45mA
Device Deselected;
All other inputs
³ VIH or £ VIL
Deselect
Current
IDD
Flow-Thru
Operating Currents
-117
-100
-66
Parameter
Test Conditions
Symbol
0 to 70°C
-40 to
85°C
0 to 70°C
-40 to
85°C
0 to 70°C
-40 to
85°C
IDD
Pipeline
Device Selected;
All other inputs
³ VIH or £ VIL
210mA
120mA
215mA
125mA
180mA
120mA
185mA
125mA
150mA
95mA
155mA
100mA
Operating
Current
IDD
Flow-Thru
Output open
Standby
Current
ISB
Flow-Thru
ZZ ³ VDD - 0.2V
10mA
15mA
10mA
15mA
10mA
15mA
IDD
Pipeline
70mA
40mA
75mA
45mA
60mA
40mA
65mA
45mA
50mA
40mA
55mA
45mA
Device Deselected;
All other inputs
³ VIH or £ VIL
Deselect
Current
IDD
Flow-Thru
Rev: 1.04 3/2000
12/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
AC Electrical Characteristics
-150
-138
-133
-117
-100
-66
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
tKC
tKQ
6.6
---
--- 7.25 ---
7.5
---
2
---
4
8.5
---
2
---
4.5
---
10
12.5
ns
ns
ns
ns
3.8
---
---
2
4
5
6
Pipeline
tKQX
1.5
1.5
---
---
---
---
2
2
2
2
1
---
2
2
2
---
tLZ
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKC
tKQ
10.5 ---
15
---
3
---
9.7
---
---
---
---
4
15
---
3
---
10
---
---
---
---
4
15
---
3
---
11
---
---
---
---
4
15
20
ns
ns
ns
ns
ns
ns
ns
ns
---
3
9.0
---
---
---
---
12
18
Flow-
Thru
tKQX
3
3
3
3
3
3
4
4
1
3
3
3
3
tLZ
tKH
tKL
1.8
1.8
1.9
1.9
1.9
1.9
1.5
---
2
Clock LOW Time
2
1
Clock to Output in High-Z
G to Output Valid
1.5 3.8 1.5
1.5
---
5
5
6
6
tHZ
tOE
---
0
3.8
---
4
---
0
4
4
4
1
G to output in Low-Z
G to output in High-Z
---
4
0
---
4
0
---
4
0
0
ns
ns
tOLZ
1
---
---
---
---
5
6
tOHZ
tS
Setup time
Hold time
1.7
0.5
---
---
2
---
---
2
---
---
2
---
---
2
2
ns
ns
tH
0.5
0.5
0.5
0.5
0.5
2
ZZ setup time
ZZ hold time
ZZ recovery
5
1
---
---
---
5
1
---
---
---
5
1
---
---
---
5
1
---
---
---
5
1
5
1
ns
ns
ns
tZZS
tZZH
2
tZZR
20
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.04 3/2000
13/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Write Cycle Timing
Single Write
Burst Write
Deselected
Write
CK
tH
tS
ADSP is blocked by E1 inactive
tKC
tKL
tKH
ADSP
tS tH
ADSC initiated write
ADSC
tH
tS
ADV
ADV must be inactive for ADSP Write
tH
tS
WR2
WR3
WR1
A0-An
tS tH
GW
BW
tH
tS
tS
tH
WR2
WR3
WR1
BA - BD
tS
tH
tH
E1 masks ADSP
E1
tS
Deselected with E2
E2
tS tH
E2 and E3 only sampled with ADSP or ADSC
E3
G
tS
Write specified byte for 2A and all bytes for 2B, 2C& 2D
tH
Hi-Z
D2C
D2D
D3A
DQA - DQD
D1A
D2A
D2B
Rev: 1.04 3/2000
14/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
E
GS820H32AT/Q-150/138/133/117/100/66
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tKH
tS
tS
tH
ADSP is blocked by E1 inactive
tKC
ADSP
ADSC
ADV
tH
ADSC initiated read
tH
tS
Suspend Burst
Suspend Burst
tS
tH
RD1
RD2
RD3
A0-An
GW
tS
tS
tH
tH
BW
BA - BD
E1
tH
tS
E1 masks ADSP
tH
tH
tS
tS
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
E3
tOHZ
tOE
G
tKQX
tKQX
tOLZ
Q2B
Q2C
Q3A
Q2A
Q1A
Q2D
DQA-DQD
Hi-Z
tLZ
tHZ
tKQ
Rev: 1.04 3/2000
15/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Flow Through Read-Write Cycle Timing
Single Write
tKC
Burst Read
Single Read
CK
tH
tS
ADSP is blocked by E inactive
ADSC initiated read
tKH tKL
ADSP
ADSC
tS
tH
tS tH
ADV
tS
tH
RD2
RD1
WR1
A0-An
tS
tS
tH
GW
tH
BW
tS
tH
BA - BD
WR1
tS
tS
tS
tH
tH
tH
E1 masks ADSP
E1
E2 and E3 only sampled with ADSP and ADSC
E2
Deselected with E3
E3
tOHZ
tOE
G
tS
tH
tKQ
Hi-Z
DQA - DQD
Q1A
D1A
Q2A
Q2A
Q2B
Q2C
Q2D
Burst wrap around to it’s initial state
Rev: 1.04 3/2000
16/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Pipelined SCD Read Cycle Timing
Single Read
Burst Read
tKC
CK
tKL
tKH
tH
tH
tS
ADSP is blocked by E1 inactive
ADSP
ADSC
tS
ADSC initiated read
tS
tH
Suspend Burst
ADV
tH
tS
RD2
RD3
RD1
An
GW
BW
tS
tS
tH
tH
BWA - BWD
E1
tH
tH
tH
tS
E1 masks ADSP
tS
tS
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
E3
tOE
G
tOHZ
tKQX
tKQX
tOLZ
tLZ
Hi-Z
DQA - DQD
Q1A
Q2A
Q2B
Q2D
Q3A
tHZ
Q2C
tKQ
Rev: 1.04 3/2000
17/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Pipelined SCD Read - Write Cycle Timing
Single Write
tKC
Single Read
Burst Read
tKL
CK
ADSP
ADSC
tH
tS
tKH
ADSP is blocked by E inactive
ADSC initiated read
tS
tH
tS tH
ADV
tS
tH
RD2
WR1
RD1
A0-An
tS
tS
tH
GW
tH
BW
tH
tS
WR1
BA - BWD
tS
tS
tS
tH
tH
tH
E1 masks ADSP
E1
E2 and E3 only sampled with ADSP and ADSC
E2
E3
Deselected with E3
tOE
tOHZ
G
tS
tH
tKQ
Hi-Z
Q1A
D1A
Q2A
Q2B
Q2C
Q2D
DQa - DQd
Rev: 1.04 3/2000
18/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in
a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in
transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to
manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised
to avoid excessive bus contention.
Rev: 1.04 3/2000
19/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
GS 820H32A Output Driver Characteristics
120.0
100.0
Pull Down Drivers
80.0
60.0
40.0
20.0
0.0
VD D Q
I O u t
VO u t
VS S
-20.0
-40.0
-60.0
Pull Up Drivers
-80.0
-100.0
-120.0
-140.0
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD HD
3.3V PD HD
3.1V PD HD
3.1V PU HD
3.3V PU HD
3.6V PU HD
Rev: 1.04 3/2000
20/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
TQFP and QFP Package Drawing
q
L
c
L1
e
b
A1
A2
E1
E
TQFP
QFP
Symbol
Description
Min. Nom. Max Min. Nom. Max
A1
A2
b
Standoff
Body Thickness
Lead Width
0.05
1.35
0.20
0.09
21.9
19.9
15.9
13.9
0.10
1.40
0.30
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
0.25
2.55
0.20
0.10
22.95
19.9
17.0
13.9
0.35
2.72
0.30
0.15
23.2
20.0
17.2
14.0
0.65
0.80
1.60
0.45
2.90
0.40
0.20
23.45
20.1
17.4
14.1
c
Lead Thickness
Terminal Dimension
Package Body
Terminal Dimension
Package Body
Lead Pitch
D
22.0
20.0
16.0
14.0
0.65
0.60
1.00
D1
E
E1
e
L
Foot Length
0.45
0.75
.60
1.00
L1
Y
Lead Length
Coplanarity
0.10
0.10
q
Lead Angle
0°
7°
0°
7°
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion
Rev: 1.04 3/2000
21/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
2
Speed
T
3
A
1
Org
Type
Package
Status
Part Number
(Mhz/
ns)
64K x 32 GS820H32AT-150
64K x 32 GS820H32A2T-138
64K x 32 GS820H32AT-133
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
QFP
150/9
138/9.7
133/10
117/11
100/12
66/18
C
C
C
C
C
C
I
64K x 32
64K x 32
64K x 32
GS820H32AT-4
GS820H32AT-5
GS820H32AT-6
64K x 32 GS820H32AT-150I
64K x 32 GS820H32AT-138I
64K x 32 GS820H32AT-133I
150/9
Not Available
138/9.7
133/10
117/11
100/12
66/18
I
I
64K x 32
64K x 32
64K x 32
GS820H32AT-4I
GS820H32AT-5I
GS820H32AT-6I
I
I
I
64K x 32 GS820H32AQ-150
64K x 32 GS820H32AQ-138
64K x 32 GS820H32AQ-133
150/9
C
C
C
C
C
C
I
QFP
138/9.7
133/10
117/11
100/12
66/18
QFP
64K x 32
64K x 32
64K x 32
GS820H32AQ-4
GS820H32AQ-5
GS820H32AQ-6
QFP
QFP
QFP
64K x 32 GS820H32AQ-150I
64K x 32 GS820H32AQ-138I
64K x 32 GS820H32AQ-133I
QFP
150/9
Not Available
QFP
138/9.7
133/10
117/11
100/12
66/18
I
QFP
I
64K x 32
64K x 32
64K x 32
Notes:
GS820H32AQ-4I
GS820H32AQ-5I
GS820H32AQ-6I
QFP
I
QFP
I
QFP
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS820H32AT-100IT.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Rev: 1.04 3/2000
22/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS820H32AT/Q-150/138/133/117/100/66
Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Revisions
New
• First Release of A version. Added “A” Version to 82032T/Q, 820E32TQ, and
820H32TQ
GS82032 Rev 1.03 2/
2000D;GS820321.04 3/2000E
Content
Rev: 1.04 3/2000
23/23
© 2000, Giga Semiconductor, Inc.
E
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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