GS82583ED18GK-675I [GSI]
8Mb x 36 and 16Mb x 18 organizations available;型号: | GS82583ED18GK-675I |
厂家: | GSI TECHNOLOGY |
描述: | 8Mb x 36 and 16Mb x 18 organizations available |
文件: | 总26页 (文件大小:470K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
GS82583ED18/36GK-675/625/550/500
Up to 675 MHz
260-Pin BGA
Commercial Temp
Industrial Temp
288Mb SigmaQuad-IIIe™
Burst of 4 SRAM
1.3V V
DD
1.2V, 1.3V, or 1.5V V
DDQ
Features
Clocking and Addressing Schemes
• 8Mb x 36 and 16Mb x 18 organizations available
• 675 MHz maximum operating frequency
• 675 MT/s peak transaction rate (in millions per second)
• 97 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
The GS82583ED18/36GK SigmaQuad-IIIe SRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• Burst of 4 Read and Write operations
• 3 cycle Read Latency
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
• 1.3V nominal core voltage
• 1.2V, 1.3V, or 1.5V HSTL I/O interface
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
Each internal read and write operation in a SigmaQuad-IIIe B4
SRAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B4 SRAM is always two address
pins less than the advertised index depth (e.g. the 16M x 18 has
4M addressable index).
SigmaQuad-IIIe™ Family Overview
SigmaQuad-IIIe SRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
SRAMs. Although very similar to GSI's second generation of
networking SRAMs (the SigmaQuad-II/SigmaDDR-II family),
these third generation devices offer several new features that
help enable significantly higher performance.
Parameter Synopsis
V
Speed Grade
Max Operating Frequency
Read Latency
DD
-675
-625
-550
-500
675 MHz
625 MHz
550 MHz
500 MHz
3 cycles
3 cycles
3 cycles
3 cycles
1.25V to 1.35V
1.25V to 1.35V
1.25V to 1.35V
1.25V to 1.35V
Rev: 1.06 8/2017
1/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
16M x 18 Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
NC
(RSVD)
MCH
(CFG)
MCL
V
V
V
V
V
V
V
V
V
V
DD
ZQ
PZT1
PZT0
A
B
C
D
E
F
DD
DDQ
DD
DDQ
DDQ
DD
DDQ
MCH
(B4M)
NC
(RSVD)
MCH
(SIOM)
V
NU
V
NU
V
V
SS
MVQ
D0
Q0
SS
O
SS
I
SS
V
V
V
V
V
NU
V
NU
Q17
D17
SA
SA
DDQ
DDQ
SS
DD
SS
DDQ
I
DDQ
O
V
NU
V
NU
V
V
V
V
SA
SA
SA
D1
Q1
SS
O
SS
I
DDQ
DDQ
SS
SS
V
V
V
V
V
NU
V
NU
V
Q16
D16
SA
SA
DDQ
DD
SS
SS
SS
DD
I
DDQ
O
V
NU
V
NU
V
V
V
V
SA
SA
D2
Q2
SS
O
O
SS
I
DD
DDQ
DD
SS
SS
NU
NU
V
V
NU
NU
NU
V
Q15
Q14
D15
D14
SA
MZT1
W
SA
D3
Q3
G
H
J
I
SS
SS
I
O
O
V
V
V
V
V
NU
V
DDQ
SA
SA
DDQ
DDQ
DDQ
DDQ
DDQ
I
V
NU
V
NU
V
V
V
V
SA
SA
D4
Q4
SS
O
SS
I
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
DDQ
CQ1
CQ1
KD1
KD1
CK
CK
KD0
KD0
CQ0
CQ0
K
L
DDQ
REF
DD
DD
DD
DD
REF
V
V
V
V
V
V
SS
QVLD1
QVLD0
SS
ss
DDQ
DDQ
SS
V
V
V
V
V
NU
V
NU
V
Q13
D13
SA
SA
M
N
P
R
T
SS
SS
SS
SS
SS
I
SS
O
SS
NU
V
NU
V
V
V
V
V
DDQ
DLL
R
MCH
D5
D6
Q5
Q6
O
DDQ
I
DDQ
DDQ
DDQ
DDQ
NU
NU
V
V
NU
NU
Q12
D12
SA
MZT0
SA
O
I
SS
SS
I
O
O
V
V
V
V
V
NU
V
NU
V
Q11
D11
MCH
RST
SS
SS
DD
DDQ
DD
I
SS
SS
NU
V
NU
V
V
V
V
V
V
V
V
SA
SA
D7
Q7
O
DDQ
I
DD
SS
SS
SS
DD
DDQ
NC
(576 Mb)
NC
(RSVD)
NC
(1152 Mb)
V
V
V
V
NU
V
NU
V
Q10
D10
U
V
W
Y
SS
SS
DDQ
DDQ
I
SS
O
SS
SA
(x18)
NU
I
(B2)
NU
V
NU
V
V
V
V
V
DDQ
D8
Q8
O
DDQ
I
DDQ
SS
DD
SS
DDQ
NC
(RSVD)
V
V
NU
V
NU
V
Q9
D9
TCK
TDO
MCL
ZT
MCL
TMS
TDI
SS
SS
I
SS
O
SS
NC
(RSVD)
V
V
V
V
V
V
V
MCL
DD
DDQ
DD
DDQ
DDQ
DD
DDQ
DD
Notes:
1. Pins 6W, 7A, 8W, and 8Y must be tied Low in this device.
2. Pins 5R and 9N must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low.
8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.06 8/2017
2/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
8M x 36 Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
NC
(RSVD)
MCL
(CFG)
MCL
V
V
V
V
V
V
V
V
DD
ZQ
PZT1
PZT0
A
B
C
D
E
F
DD
DDQ
DD
DDQ
DDQ
DD
DDQ
MCH
(B4M)
NC
(RSVD)
MCH
(SIOM)
V
V
V
V
SS
Q35
D35
MVQ
D0
Q0
SS
SS
SS
V
V
V
V
V
V
V
DDQ
Q26
D26
SA
SA
D9
Q9
DDQ
DDQ
SS
DD
SS
DDQ
V
V
V
V
V
V
SS
Q34
D34
SA
SA
SA
D1
Q1
SS
SS
DDQ
DDQ
SS
V
V
V
V
V
V
V
DDQ
Q25
D25
SA
SA
D10
Q10
DDQ
DD
SS
SS
SS
DD
V
V
V
V
V
V
V
Q33
D33
D32
SA
SA
D2
Q2
SS
SS
DD
DDQ
DD
SS
SS
V
V
Q24
Q23
Q32
D24
D23
SA
MZT1
W
SA
D3
D11
D12
Q3
Q11
Q12
G
H
J
SS
SS
V
V
V
V
V
V
DDQ
SA
SA
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
Q31
D31
SA
SA
D4
Q4
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
DDQ
CQ1
CQ1
KD1
KD1
CK
CK
KD0
KD0
CQ0
CQ0
K
L
DDQ
REF
DD
DD
DD
DD
REF
V
V
V
V
V
V
SS
QVLD1
QVLD0
SS
SS
DDQ
DDQ
SS
V
V
V
V
V
V
V
Q22
D22
SA
SA
D13
Q13
M
N
P
R
T
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
DDQ
Q30
Q29
D30
D29
DLL
R
MCH
D5
D6
Q5
Q6
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
Q21
D21
SA
MZT0
SA
D14
Q14
SS
SS
V
V
V
V
V
V
V
Q20
D20
MCH
RST
D15
Q15
SS
SS
DD
DDQ
DD
SS
SS
V
V
V
V
V
V
V
DDQ
Q28
D28
SA
SA
D7
Q7
DDQ
DD
SS
SS
SS
DD
NC
(576 Mb)
NC
(RSVD)
NC
(1152 Mb)
V
V
V
V
V
V
Q19
D19
D16
Q16
U
V
W
Y
SS
SS
DDQ
DDQ
SS
SS
NU
(x18)
NU
I
(B2)
I
V
V
V
V
V
V
V
DDQ
Q27
D27
D8
Q8
DDQ
DDQ
SS
DD
SS
DDQ
NC
(RSVD)
V
V
V
V
Q18
D18
TCK
TDO
MCL
MCL
TMS
TDI
D17
Q17
SS
SS
SS
SS
NC
(RSVD)
V
V
V
V
V
V
V
V
ZT
MCL
DD
DDQ
DD
DDQ
DDQ
DD
DDQ
DD
Notes:
1. Pins 6W, 7A, 8W, and 8Y must be tied Low in this device.
2. Pins 5R and 9N must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low.
8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.06 8/2017
3/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Pin Description
Symbol
Description
Type
SA
Address — Read or Write Address is registered on CK.
Input
Write Data — Registered on KD and KD during Write operations.
D[17:0] - x18 and x36.
D[35:0]
Q[35:0]
Input
D[35:18] - x36 only.
Read Data — Aligned with CQ and CQ during Read operations.
Q[17:0] - x18 and x36.
Output
Q[35:18] - x36 only.
QVLD[1:0]
CK, CK
Read Data Valid — Driven high one half cycle before valid Read Data.
Output
Input
Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing
control, and for output timing control.
Write Data Input Clocks — Dual single-ended. Used for latching write data inputs.
KD0, KD0: latch Write Data (D[17:0] in x36, D[8:0] in x18).
KD[1:0],
KD[1:0]
Input
KD1, KD1: latch Write Data (D[35:18] in x36, D[17:9] in x18).
CQ[1:0],
CQ[1:0]
Read Data Output Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs.
Facilitate source-synchronous operation.
Output
R
Read Enable — Registered on CK. R = 0 initiates a Read operation.
Write Enable — Registered on CK. W = 0 initiates a Write operation.
Input
Input
W
DLL Enable — Weakly pulled High internally.
DLL = 0: disables internal DLL.
DLL
Input
DLL = 1: enables internal DLL.
Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
RST
ZQ
Input
Input
Input
Driver Impedance Control Resistor Input — Must be connected to V through an external resistor RQ to
SS
program driver impedance.
ODT Impedance Control Resistor Input — Must be connected to V through an external resistor RT to
SS
ZT
program ODT impedance.
ODT Mode Select — Set the ODT state globally for all input groups. Must be tied High or Low.
MZT[1:0] = 00: disables ODT on all input groups, regardless of PZT[1:0].
MZT[1:0] = 01: enables strong ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 10: enables weak ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 11: reserved.
MZT[1:0]
PZT[1:0]
Input
Input
ODT Configuration Select — Set the ODT state for various combinations of input groups when MZT[1:0] =
01 or 10. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Rev: 1.06 8/2017
4/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Symbol
Description
Type
I/O Voltage Select — Indicates what voltage is supplied to the V
pins. Must be tied High or Low.
DDQ
MVQ = 0: Configure for 1.2V or 1.3V nominal V
.
MVQ
Input
DDQ
MVQ = 1: Configure for 1.5V nominal V
.
DDQ
V
Core Power Supply
—
—
—
DD
V
I/O Power Supply
DDQ
V
Input Reference Voltage — Input buffer reference voltage.
REF
V
Ground
—
SS
TCK
TMS
TDI
JTAG Clock — Weakly pulled Low internally.
JTAG Mode Select — Weakly pulled High internally.
JTAG Data Input — Weakly pulled High internally.
JTAG Data Output
Input
Input
Input
Output
Input
TDO
MCH
Must Connect High — May be tied to V
directly or via a 1k resistor.
DDQ
Must Connect Low — May be tied to V directly or via a 1k resistor.
MCL
NC
Input
—
SS
No Connect — There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
Not Used Input — There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be
tied/driven High.
NU
Input
I
Not Used Output — There is an internal chip connection to these output pins, but they are unused by the
device. The drivers are tri-stated internally. They should be left unconnected.
NU
Output
O
Rev: 1.06 8/2017
5/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Power-Up and Reset Requirements
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
, V , V , V and inputs.
V
SS
DD
DDQ
REF
Power supplies must power down simultaneously, or in the reverse sequence.
After power supplies power up, the following start-up sequence must be followed.
Step 1 (Recommended, but not required): Assert RST High for at least 1ms.
While RST is asserted high:
• The DLL is disabled.
• The states of R, and W control inputs are ignored.
Note: If possible, RST should be asserted High before input clocks begin toggling, and remain asserted High until input clocks are
stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM.
Step 2: Begin toggling input clocks.
After input clocks begin toggling, but not necessarily within specification:
• Q are placed in the non-Read state, and remain so until the first Read operation.
• QVLD are driven Low, and remain so until the first Read operation.
• CQ, CQ begin toggling, but not necessarily within specification.
Step 3: Wait until input clocks are stable and toggling within specification.
Step 4: De-assert RST Low (if asserted High).
Step 5: Wait at least 160K (163,840) cycles.
During this time:
• Driver and ODT impedances are calibrated. Can take up to 160K cycles.
Note: The DLL pin may be asserted High or de-asserted Low during this time. If asserted High, DLL synchronization begins
immediately after the driver and ODT impedances are calibrated. If de-asserted Low, DLL synchronization begins after the DLL
pin is asserted High (see Step 6). In either case, Step 7 must follow thereafter.
Step 6: Assert DLL pin High (if de-asserted Low).
Step 7: Wait at least 64K (65,536) cycles for the DLL to lock.
After the DLL has locked:
• CQ, CQ begin toggling within specification.
Step 8: Begin initiating Read and Write operations.
Reset Usage
Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence
described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted
Low (as in Step 4 above), Steps 5~7 above must be followed before Read and Write operations are initiated.
Note: Memory array content may be perturbed/corrupted when RST is asserted High.
Rev: 1.06 8/2017
6/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
DLL Operation
A DLL is implemented in these devices to control all output timing. It uses the CK input clock as a source, and is enabled when all
of the following conditions are met:
1. RST is de-asserted Low, and
2. The DLL pin is asserted High, and
3. CK cycle time t
(max), as specified in the AC Timing Specifications section.
KHKH
Once enabled, the DLL requires 64K stable clock cycles in order to lock/synchronize properly.
When the DLL is enabled, it aligns output clocks and read data to input clocks, and it generates all mid-cycle output timing. See the
Output Timing section for more information.
The DLL can tolerate changes in input clock frequency due to clock jitter (i.e. such jitter will not cause the DLL to lose lock/
synchronization), provided the cycle-to-cycle jitter does not exceed 200ps (see “t
” in the AC Timing Specifications section
KJITcc
for more information). However, the DLL must be resynchronized (i.e. disabled and then re-enabled) whenever the nominal input
clock frequency is changed.
The DLL is disabled when any of the following conditions are met:
1. RST is asserted High, or
2. The DLL pin is de-asserted Low, or
3. CK is stopped for at least 30ns, or CK cycle time 30ns.
Clock Truth Table
Previous
Operation
SA
R
W
Current Operation
D
Q
CK CK CK
KD
KD
KD
KD
CQ
(t
CQ
(t
CQ
(t
CQ
(t
)
n–1
(t )
(t )
(t )
(t )
(t
)
(t
)
(t
)
(t
)
)
)
)
(t
)
n
n
n
n
n+1
n+1½
n+2
—
—
—
n+2½
n+3
n+3½
n+4
n+4½
NOP
Write
Read
NOP
Read
NOP
Write
X
X
X
V
V
V
V
1
1
X
1
X
0
0
1
X
1
NOP
NOP
NOP
Write
Write
Read
Read
X
X
—
0 / High-Z
0 / High-Z
—
—
—
—
—
D3
X
D4
X
—
—
Q3
Q4
0
D1
D1
X
D2
D2
X
D3
D3
—
D4
D4
—
0 / High-Z
0
Q3
Q4
Q2
Q2
X
X
Q1
Q1
Q3
Q3
Q4
Q4
D3
D4
—
—
Notes:
1. 1 = High; 0 = Low; V = Valid; X = don’t care.
2. D1, D2, D3, and D4 indicate the first, second, third, and fourth pieces of Write Data transferred during Write operations.
3. Q1, Q2, Q3, and Q4 indicate the first, second, third, and fourth pieces of Read Data transferred during Read operations.
4. When D ODT is enabled, Q pins are driven Low for one cycle in response to NOP and Write commands, 3 cycles after the command is
sampled, except when preceded by a Read command. When D ODT is disabled, Q pins are tri-stated for one cycle in response to NOP
and Write commands, 3 cycles after the command is sampled, except when preceded by a Read command.
Rev: 1.06 8/2017
7/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Input Timing
These devices utilize three pairs of positive and negative input clocks, CK & CK and KD[1:0] & KD[1:0], to latch the various
synchronous inputs. Specifically:
CK latches all address (SA) inputs.
CK latches all control (R, W) inputs.
KD[1:0] and KD[1:0] latch particular write data (D) inputs, as follows:
• KD0 and KD0 latch D[17:0] in x36, and D[8:0] in x18.
• KD1 and KD1 latch D[35:18] in x36, and D[17:9] in x18.
Output Timing
These devices provide two pairs of positive and negative output clocks (aka “echo clocks”), CQ[1:0] & CQ[1:0], whose timing is
tightly aligned with read data in order to enable reliable source-synchronous data transmission.
These devices utilize a DLL to control output timing. When the DLL is enabled, it generates 0 and 180 phase clocks from CK
that control read data output clock (CQ, CQ), read data (Q), and read data valid (QVLD) output timing, as follows:
• CK+0 generates CQ[1:0], CQ[1:0], Q1 active, and Q2 inactive.
• .CK+180 generates CQ[1:0], CQ[1:0], Q1 inactive, Q2 active, and QVLD active/inactive.
Note: Q1 and Q2 indicate the first and second pieces of read data transferred in any given clock cycle during Read operations.
When the DLL is enabled, CQ is aligned to CK. See the AC Timing Specifications for more information.
CQ[1:0] and CQ[1:0] align with particular Q and QVLD outputs, as follows:
• CQ0 and CQ0 align with Q[17:0], QVLD0 in x36 devices, and Q[8:0], QVLD0 in x18 devices.
• CQ1 and CQ1 align with Q[35:18], QVLD1 in x36 devices, and Q[17:9], QVLD0 in x18 devices.
Rev: 1.06 8/2017
8/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Driver Impedance Control
Programmable Driver Impedance is implemented on the following output signals:
• CQ, CQ, Q, QVLD.
Driver impedance is programmed by connecting an external resistor RQ between the ZQ pin and V
.
SS
Driver impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system.
Output Signal
Pull-Down Impedance (R
)
Pull-Up Impedance (R
)
OUTL
OUTH
CQ, CQ, Q, QVLD
RQ*0.2 15%
RQ*0.2 15%
Notes:
1.
2. The mismatch between R
R
and R
apply when 175 RQ 225.
OUTL
OUTH
and R
is less than 10%, guaranteed by design.
OUTL
OUTH
ODT Impedance Control
Programmable ODT Impedance is implemented on the following input signals:
• CK, CK, KD, KD, SA, R, W, D.
ODT impedance is programmed by connecting an external resistor RT between the ZT pin and V
.
SS
ODT impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system
Input Signal
PZT[1:0] MZT[1:0] Pull-Down Impedance (R
)
Pull-Up Impedance (R
)
INL
INH
X0
X1
0X
1X
XX
01
10
XX
01
10
01
10
disabled
RT 15%
RT*2 20%
disabled
disabled
RT 15%
RT*2 20%
disabled
CK, CK, KD, KD
SA, R, W
D
RT 15%
RT*2 20%
RT 15%
RT*2 20%
RT 15%
RT*2 20%
RT 15%
RT*2 20%
XX
Notes:
1. When MZT[1:0] = 00, ODT is disabled on all inputs. MZT[1:0] = 11 is reserved for future use.
2. and R apply when 105 RT 135
3. The mismatch between R and R is less than 10%, guaranteed by design.
R
INL
INH
INL
INH
4. All ODT is disabled during JTAG EXTEST and SAMPLE-Z instructions.
Note: When ODT impedance is enabled on a particular input, that input should always be driven High or Low; it should never be
tri-stated (i.e., in a High- Z state). If the input is tri-stated, the ODT will pull the signal to V / 2 (i.e., to the switch point of the
DDQ
diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it normally would.
This could result in the device’s operating currents being higher.
Rev: 1.06 8/2017
9/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Absolute Maximum Ratings
Parameter
Symbol
Rating
Units Notes
V
Core Supply Voltage
I/O Supply Voltage when MVQ = 0
I/O Supply Voltage when MVQ = 1
Input Voltage
-0.3 to +1.4
V
V
DD
V
-0.3 to V
DDQ
DD
V
-0.3 to +1.8
DDQ
V
-0.3 to V
+ 0.3
DDQ
V
IN
T
Junction Temperature
0 to 125
C
C
J
T
Storage Temperature
-55 to 125
STG
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recom-
mended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions for an extended period of time may
affect reliability of this component.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units Notes
V
Core Supply Voltage
1.25
1.15
1.45
0
1.3
1.2 or 1.3
1.5
1.35
V
V
DD
V
V
I/O Supply Voltage when MVQ = 0
I/O Supply Voltage when MVQ = 1
Commercial Junction Temperature
Industrial Junction Temperature
DDQ
DD
V
1.55
85
V
DDQ
T
—
C
C
JC
T
-40
—
100
JI
Note: For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
V , V , V , V , and Inputs.
SS DD DDQ REF
Power supplies must power down simultaneously, or in the reverse sequence.
Thermal Impedances
JA (C°/W)
JA (C°/W)
JA (C°/W)
Package
JB (C°/W)
JC (C°/W)
Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s
FBGA
12.94
10.47
9.51
2.93
0.33
Rev: 1.06 8/2017
10/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
I/O Capacitance
Parameter
Symbol
Min
Max
Units Notes
C
Input Capacitance
Output Capacitance
—
—
5.0
5.5
pF
pF
1, 3
2, 3
IN
C
OUT
Notes:
1. V = V /2.
IN
DDQ
2.
V
= V /2.
OUT DDQ
3. T = 25C, f = 1 MHz.
A
Input Electrical Characteristics - 1.2V or 1.3V I/O (MVQ = 0)
Parameter
Symbol
Min
Typ
Max
Units Notes
V
0.48 * V
0.52 * V
DDQ
DC Input Reference Voltage
DC Input High Voltage (HS)
DC Input Low Voltage (HS)
DC Input High Voltage (LS)
DC Input Low Voltage (LS)
AC Input Reference Voltage
AC Input High Voltage (HS)
AC Input Low Voltage (HS)
AC Input High Voltage (LS)
AC Input Low Voltage (LS)
0.50 * V
V
V
V
V
V
V
V
V
V
V
—
1, 6
2, 6
7
REFdc
DDQ
DDQ
V
V
+ 0.08
V
+ 0.15
- 0.08
+ 0.15
0.80 * V
0.20 * V
V
IH1dc
REF
DDQ
DDQ
DDQ
V
V
-0.15
0.75 * V
IL1dc
REF
V
V
IH2dc
DDQ
DDQ
DDQ
V
0.25 * V
0.53 * V
-0.15
0
7
IL2dc
DDQ
DDQ
V
0.47 * V
0.50 * V
3
REFac
DDQ
DDQ
V
V
+ 0.15
V
+ 0.25
- 0.15
+ 0.25
0.80 * V
0.20 * V
V
1, 4~6
2, 4~6
4, 7
4, 7
IH1ac
REF
DDQ
DDQ
DDQ
V
V
-0.25
- 0.2
IL1ac
REF
V
V
V
IH2ac
DDQ
DDQ
DDQ
V
-0.25
0
0.2
IL2ac
Notes:
1. “Typ” parameter applies when Controller R
= 40 and SRAM R = R = 120.
INH INL
OUTH
OUTL
2. “Typ” parameter applies when Controller R
= 40 and SRAM R = R = 120.
INH
INL
3.
V
is equal to V
plus noise.
REFdc
REFac
IH
4. V max and V min apply for pulse widths less than one-quarter of the cycle time.
IL
5. Input rise and fall times must be a minimum of 1V/ns, and within 10% of each other.
6. Parameters apply to High Speed Inputs: CK, CK, KD, KD, SA, D, R, W.
7. Parameters apply to Low Speed Inputs: RST, DLL, MZT, PZT, MVQ.
Rev: 1.06 8/2017
11/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Input Electrical Characteristics - 1.5V I/O (MVQ = 1)
Parameter
Symbol
Min
Typ
Max
Units Notes
V
0.48 * V
0.52 * V
DDQ
DC Input Reference Voltage
DC Input High Voltage (HS)
DC Input Low Voltage (HS)
DC Input High Voltage (LS)
DC Input Low Voltage (LS)
AC Input Reference Voltage
AC Input High Voltage (HS)
AC Input Low Voltage (HS)
AC Input High Voltage (LS)
AC Input Low Voltage (LS)
0.50 * V
V
V
V
V
V
V
V
V
V
V
—
1, 6
2, 6
7
REFdc
DDQ
DDQ
V
V
+ 0.1
V
+ 0.15
- 0.1
0.80 * V
0.20 * V
V
IH1dc
REF
DDQ
DDQ
DDQ
V
V
-0.15
0.75 * V
IL1dc
REF
V
V
+ 0.15
IH2dc
DDQ
DDQ
DDQ
V
0.25 * V
0.53 * V
-0.15
0
7
IL2dc
DDQ
DDQ
V
0.47 * V
0.50 * V
3
REFac
DDQ
DDQ
V
V
+ 0.2
V
+ 0.25
- 0.2
0.80 * V
0.20 * V
V
1, 4~6
2, 4~6
4, 7
4, 7
IH1ac
REF
DDQ
DDQ
DDQ
V
V
-0.25
IL1ac
REF
V
V
- 0.2
V
+ 0.25
IH2ac
DDQ
DDQ
DDQ
V
-0.25
0
0.2
IL2ac
Notes:
1. “Typ” parameter applies when Controller R
= 40 and SRAM R = R = 120.
INH INL
OUTH
OUTL
2. “Typ” parameter applies when Controller R
= 40 and SRAM R = R = 120.
INH
INL
3.
V
is equal to V
plus noise.
REFdc
REFac
IH
4. V max and V min apply for pulse widths less than one-quarter of the cycle time.
IL
5. Input rise and fall times must be a minimum of 1V/ns, and within 10% of each other.
6. Parameters apply to High Speed Inputs: CK, CK, KD, KD, SA, D, R, W.
7. Parameters apply to Low Speed Inputs: RST, DLL, MZT, PZT, MVQ.
Output Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Units Notes
V
V
V
+ 0.15
DDQ
DC Output High Voltage
DC Output Low Voltage
AC Output High Voltage
AC Output Low Voltage
—
-0.15
—
0.80 * V
V
V
V
V
1, 3
2, 3
1, 3
2, 3
OHdc
DDQ
V
0.20 * V
0.80 * V
0.20 * V
—
OLdc
DDQ
DDQ
DDQ
V
+ 0.25
DDQ
OHac
V
-0.25
—
OLac
Note:
1. “Typ” parameter applies when SRAM R
= 40 and Controller R = R = 120.
INH INL
OUTH
OUTL
2. “Typ” parameter applies when SRAM R
= 40 and Controller R = R = 120.
INH
INL
3. Parameters apply to: CQ, CQ, Q, QVLD.
Rev: 1.06 8/2017
12/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Leakage Currents
Parameter
Symbol
Min
Max
Units Notes
I
-2
-20
-2
2
2
uA
uA
uA
uA
1, 2
1, 3
1, 4
5, 6
LI1
I
Input Leakage Current
LI2
I
20
2
LI3
I
Output Leakage Current
-2
LO
Notes:
1. V = V to V .
DDQ
IN
SS
2. Parameters apply to CK, CK, KD, KD, SA, D, R, W when ODT is disabled.
Parameters apply to MZT, PZT, MVQ.
3. Parameters apply to DLL, TMS, TDI (weakly pulled up).
4. Parameters apply to RST, TCK (weakly pulled down).
5.
V
= V to V
.
DDQ
OUT
SS
6. Parameters apply to CQ, CQ, Q, QVLD, TDO.
Operating Currents
V
(nom)
Parameter
Symbol
500 MHz
550 MHz
625 MHz
675 MHz
Units
DD
1.3V
1.3V
I
x18 Operating Current
x36 Operating Current
1200
1360
1300
1480
1450
1660
1550
1780
mA
mA
DD
I
DD
Notes:
1.
2. Applies at 100% alternating Reads and Writes.
I
= 0 mA; V = V or V .
IN IH IL
OUT
Rev: 1.06 8/2017
13/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
AC Test Conditions - 1.2V I/O (MVQ = 0)
Parameter
Symbol
Conditions
Units
V
Core Supply Voltage
I/O Supply Voltage
Input Reference Voltage
Input High Level
1.25 to 1.35
1.15 to 1.25
0.6
V
V
V
V
DD
V
DDQ
V
REF
V
0.9
IH
V
Input Low Level
Input Rise and Fall Time
0.3
2.0
0.6
V
V/ns
V
IL
—
—
Input and Output Reference Level
Note: Output Load Conditions RQ = 200. Refer to figure below.
AC Test Conditions - 1.5V I/O (MVQ = 1)
Parameter
Symbol
Conditions
Units
V
Core Supply Voltage
I/O Supply Voltage
Input Reference Voltage
Input High Level
1.25 to 1.35
1.45 to 1.55
0.75
V
V
V
V
DD
V
DDQ
V
REF
V
1.25
IH
V
Input Low Level
Input Rise and Fall Time
0.25
2.0
V
V/ns
V
IL
—
—
Input and Output Reference Level
0.75
Note: Output Load Conditions RQ = 200. Refer to figure below.
AC Test Output Load
50
Output
50
V
/2
DDQ
5 pF
Rev: 1.06 8/2017
14/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
AC Timing Specifications (independent of device speed grade)
Parameter
Symbol
Min
Max
Units Notes
Input Clock Timing
t
Clk High Pulse Width
Clk Low Pulse Width
0.45
—
—
cycles
cycles
cycles
ps
1
1
KHKL
t
0.45
KLKH
t
Clk High to Clk High
0.45
0.55
+200
60
2
KHKH
t
Clk High to Write Data Clk High
Clk Cycle-to-Cycle Jitter
DLL Lock Time
-200
3
KHKDH
t
—
ps
1,4,5
6
KJITcc
t
65,536
—
cycles
ns
Klock
t
Clk Static to DLL Reset
30
Output Timing
-0.4
—
7,12
Kreset
t
Clk High to Output Valid / Hold
Clk High to Echo Clock High
+0.4
ns
ns
ps
ps
8
9
KHQV/X
t
-0.4
+0.4
KHCQH
t
Echo Clk High to Output Valid / Hold
Echo Clk High to Echo Clock High
-150
+150
10,12
11,12
CQHQV/X
t
t
(min) - 100
t (max) + 100
KHKH
CQHCQH
KHKH
Notes:
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.
1. Parameters apply to CK, CK, KD, KD.
2. Parameter specifiesCK CK and KD KD requirements.
3. Parameter specifies CK KD and CK KD requirements.
4. Parameter specifies Cycle-to-Cycle (C2C) Jitter (i.e. the maximum variation from clock rising edge to the next clock rising edge).
As such, it limits Period Jitter (i.e. the maximum variation in clock cycle time from nominal) to 30ps.
And as such, it limits Absolute Jitter (i.e. the maximum variation in clock rising edge from its nominal position) to 15ps.
5. The device can tolerated C2C Jitter greater than 60ps, up to a maximum of 200ps. However, when using a device from a particular speed
grade, t (min) of that speed grade must be derated (increased) by half the difference between the actual C2C Jitter and 60ps. For
KHKH
example, if the actual C2C Jitter is 100ps, then t
(min) for the -675 speed grade is derated to 1.5ns (1.48ns + 0.5*(100ps - 60ps)).
KHKH
6.
V
slew rate must be < 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once V and input clock are stable.
DD DD
7. Parameter applies to CK.
8. Parameters apply to Q, and are referenced to CK.
9. Parameter specifies CK CQ timing.
10. Parameters apply to Q, QVLD and are referenced to CQ & CQ.
11. Parameter specifies CQ CQ timing.
12. Parameters are not tested. They are guaranteed by design, and verified through extensive corner-lot characterization.
Rev: 1.06 8/2017
15/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
AC Timing Specifications (variable with device speed grade)
–675
–625
–550
–500
Parameter
Symbol
Units Notes
Min Max Min Max Min Max Min Max
Input Clock Timing
t
Clk Cycle Time
1.48
6.0
1.6
6.0
1.8
6.0
2.0
6.0
ns
1
2
KHKH
Input Setup & Hold Timing
t
Input Valid to Clk High
Clk High to Input Hold
150
150
—
—
160
160
—
—
180
180
—
—
200
200
—
—
ps
ps
IVKH
t
KHIX
Notes:
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.
1. Parameters apply to CK, CK, KD, KD.
2. Parameters apply to SA, and are referenced to CK.
Parameters apply to R, W, and are referenced to CK.
Parameters apply to D, and are referenced to KD & KD.
Rev: 1.06 8/2017
16/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Read and Write Timing Diagram
Read
Write
Read
NOP
NOP
Write
Read
Write
Read
Write
NOP
KD
KD
D
tKHKH
tKHKL tKLKH tKHKH
tIVKH
tKHIX
tIVKH
tKHIX
D21 D22 D23 D24
D41 D42 D43 D44 D61 D62 D63 D64 D81
tKHKDH
tKHKDH
CK
tKHKH
tKHKL tKLKH tKHKH
CK
tIVKH tKHIX
SA A1
A2
A3
A4
A5
A6
A7
A8
tIVKH tKHIX
R
W
tKHQV
tKHQX
Q11 Q12 Q13 Q14 Q31 Q32 Q33 Q34
Q51 Q52 Q53
Q
QVLD
tCQHQX
tCQHQV
tCQHQX
tCQHQX
tKHCQH
tCQHQV
tCQHQV
CQ
tCQHCQH
CQ
Rev: 1.06 8/2017
17/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
JTAG Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1
functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller,
etc.), SRAM, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices
contain a TAP Controller and multiple TAP Registers. The TAP Registers consist of one Instruction Register and multiple Data
Registers.
The TAP consists of the following four signals:
Pin
Pin Name
I/O
Description
TCK
Test Clock
I
Induces (clocks) TAP Controller state transitions.
Inputs commands to the TAP Controller.
Sampled on the rising edge of TCK.
TMS
TDI
Test Mode Select
Test Data In
I
I
Inputs data serially to the TAP Registers.
Sampled on the rising edge of TCK.
Outputs data serially from the TAP Registers.
Driven from the falling edge of TCK.
TDO
Test Data Out
O
Concurrent TAP and Normal SRAM Operation
According to IEEE std. 1149.1, most public TAP Instructions do not disrupt normal device operation. In these devices, the only
exceptions are EXTEST and SAMPLE-Z. See the Tap Registers section for more information.
Disabling the TAP
When JTAG is not used, TCK should be tied Low to prevent clocking the SRAM. TMS and TDI should either be tied High through
a pull-up resistor or left unconnected. TDO should be left unconnected.
JTAG DC Operating Conditions
Parameter
Symbol
Min
Max
Units Notes
V
0.75 * V
V
+ 0.15
DDQ
JTAG Input High Voltage
JTAG Input Low Voltage
JTAG Output High Voltage
JTAG Output Low Voltage
V
V
V
V
1
TIH
DDQ
V
0.25 * V
—
–0.15
– 0.2
1
TIL
DDQ
V
V
2, 3
2, 4
TOH
DDQ
V
—
0.2
TOL
Notes:
1. Parameters apply to TCK, TMS, and TDI.
2. Parameters apply to TDO.
3.
I
= –2.0 mA.
TOH
TOL
4.
I
= 2.0 mA.
Rev: 1.06 8/2017
18/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
JTAG AC Timing Specifications
Parameter
Symbol
Min
Max
Units
t
TCK Cycle Time
TCK High Pulse Width
50
20
20
10
10
10
10
10
10
—
0
—
—
—
—
—
—
—
—
—
10
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
THTH
t
THTL
t
TCK Low Pulse Width
TLTH
t
TMS Setup Time
MVTH
t
TMS Hold Time
THMX
t
TDI Setup Time
DVTH
t
TDI Hold Time
THDX
t
Capture Setup Time (Address, Control, Data, Clock)
Capture Hold Time (Address, Control, Data, Clock)
TCK Low to TDO Valid
CS
t
CH
t
TLQV
t
TCK Low to TDO Hold
TLQX
JTAG Timing Diagram
tTHTL
tTLTH
tTHTH
TCK
TMS
TDI
tMVTH tTHMX
tDVTH tTHDX
tTLQV
tTLQX
TDO
Rev: 1.06 8/2017
19/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
TAP Controller
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations
associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK.
The TAP Controller enters the Test-Logic Reset state in one of two ways:
1. At power up.
2. When a logic 1 is applied to TMS for at least 5 consecutive rising edges of TCK.
The TDI input receiver is sampled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
The TDO output driver is enabled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
TAP Controller State Diagram
1
0
Test-Logic Reset
0
1
1
1
Run-Test / Idle
Select DR-Scan
Select IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
Shift-DR
0
Shift-IR
0
1
Exit1-DR
0
1
Exit1-IR
0
1
1
Pause-DR
1
0
Pause-IR
1
0
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
Rev: 1.06 8/2017
20/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
TAP Registers
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output
data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: Instruction Registers (IR), which are
manipulated via the IR states in the TAP Controller, and Data Registers (DR), which are manipulated via the DR states in the TAP
Controller.
Instruction Register (IR - 3 bits)
The Instruction Register stores the various TAP Instructions supported by SRAM. It is loaded with the IDCODE instruction (logic
001) at power-up, and when the TAP Controller is in the Test-Logic Reset and Capture-IR states. It is inserted between TDI and
TDO when the TAP Controller is in the Shift-IR state, at which time it can be loaded with a new instruction. However, newly
loaded instructions are not executed until the TAP Controller has reached the Update-IR state.
The Instruction Register is 3 bits wide, and is encoded as follows:
Code
(2:0)
Instruction
Description
Loads the logic states of all signals composing the SRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
Also transfers the contents of the Boundary Scan Register associated with output signals (Q, QVLD,
CQ, CQ) directly to their corresponding output pins. However, newly loaded Boundary Scan Register
contents do not appear at the output pins until the TAP Controller has reached the Update-DR state.
Also disables all ODT.
000
EXTEST
See the Boundary Scan Register description for more information.
Loads a predefined device- and manufacturer-specific identification code into the ID Register when the
TAP Controller is in the Capture-DR state, and inserts the ID Register between TDI and TDO when the
TAP Controller is in the Shift-DR state.
001
010
IDCODE
See the ID Register description for more information.
Loads the logic states of all signals composing the SRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
Also disables all ODT.
SAMPLE-Z
Also forces Q output drivers to a High-Z state.
See the Boundary Scan Register description for more information.
011
100
PRIVATE
SAMPLE
Reserved for manufacturer use only.
Loads the logic states of all signals composing the SRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between
TDI and TDO when the TAP Controller is in the Shift-DR state.
See the Boundary Scan Register description for more information.
101
110
PRIVATE
PRIVATE
Reserved for manufacturer use only.
Reserved for manufacturer use only.
Loads a logic 0 into the Bypass Register when the TAP Controller is in the Capture-DR state, and
inserts the Bypass Register between TDI and TDO when the TAP Controller is in the Shift-DR state.
See the Bypass Register description for more information.
111
BYPASS
Rev: 1.06 8/2017
21/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Bypass Register (DR - 1 bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic
0 when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the Capture-DR state. It is
inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP
Controller is in the Shift-DR state.
ID Register (DR - 32 bits)
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE
instruction has been loaded into the Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between
TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the
Shift-DR state.
The ID Register is 32 bits wide, and is encoded as follows:
See BSDL Model
(31:12)
GSI ID
(11:1)
Start Bit
(0)
XXXX XXXX XXXX XXXX XXXX
0001 1011 001
1
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB,
and the LSB serially shifts data out through TDO.
Boundary Scan Register (DR - 129 bits)
The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the TAP pins)
plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the logic states of all
signals composing the SRAM’s I/O ring when the EXTEST, SAMPLE, or SAMPLE-Z instruction has been loaded into the
Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between TDI and TDO when the EXTEST,
SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the Shift-DR state.
Additionally, the contents of the Boundary Scan Register associated with the SRAM outputs (Q, QVLD, CQ, CQ) are driven
directly to the corresponding SRAM output pins when the EXTEST instruction is selected. However, after the EXTEST instruction
has been selected, any new data loaded into Boundary Scan Register when the TAP Controller is in the Shift-DR state does not
appear at the output pins until the TAP Controller has reached the Update-DR state.
The value captured in the boundary scan register for NU pins is determined by the external pin state. The value captured in the
boundary scan register for NC pins is 0 regardless of the external pin state. The value captured in the Internal Cell (Bit 129) is 1.
Output Driver State During EXTEST
EXTEST allows the Internal Cell (Bit 129) in the Boundary Scan Register to control the state of Q drivers. That is, when Bit 129 =
1, Q drivers are enabled (i.e., driving High or Low), and when Bit 129 = 0, Q drivers are disabled (i.e., forced to High-Z state). See
the Boundary Scan Register section for more information.
ODT State During EXTEST and SAMPLE-Z
ODT on all inputs is disabled during EXTEST and SAMPLE-Z.
Rev: 1.06 8/2017
22/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Boundary Scan Register Bit Order Assignment
The table below depicts the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and Bit 129 is the
MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out
through TDO.
Bit
1
Pad
7L
Bit
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Pad
12F
11G
13G
10G
12G
11H
13H
10J
Bit
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pad
12W
10W
8V
Bit
85
Pad
1T
4R
2R
3P
1P
4P
2P
3N
1N
4M
2M
3L
Bit
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
Pad
1C
2
7K
86
3C
3
9L
87
2B
4
9K
9U
8T
88
4B
5
8J
89
5A
6
7H
9R
8P
90
6A
7
9H
91
6B
8
7G
8G
9F
9N
8M
6M
7N
5N
7P
92
6C
9
12J
93
5D
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
13K
13L
11L
94
6E
8E
95
5F
7D
96
6G
5H
9D
12M
10M
13N
11N
12P
10P
13P
11P
12R
10R
13T
11T
12U
10U
13V
11V
97
1L
8C
6P
98
1K
2J
6J
7B
5R
6T
99
5K
8B
100
101
102
103
104
105
106
107
108
109
110
111
112
4J
5L
9B
7U
5U
6V
1H
3H
2G
4G
1G
3G
2F
4F
1E
3E
2D
4D
Internal
7A
9A
10B
12B
11C
13C
10D
12D
11E
13E
10F
6W
7Y
4W
2W
3V
1V
4U
2U
3T
Rev: 1.06 8/2017
23/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
260-Pin BGA Package Drawing (Package GK)
C
Ø0.08 S
Ø0.22 S C
B S
A S
Ø0.50~Ø0.70(260x)
PIN #1 CORNER
13 12 11 10
9 8 7 6 5 4 3
2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
13.20 0.05
14.00 0.05
B
1.00
A
12.00
0.05(4X)
HEAT SPREADER
4–R0.5 (MAX)
C
SEATING PLANE
Ball Pitch:
1.00 Substrate Thickness: 0.51
0.60 Mold Thickness:
Ball Diameter:
—
Rev: 1.06 8/2017
24/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Ordering Information — GSI SigmaQuad-IIIe SRAM
Speed
(MHz)
T
Org
Part Number
Type
Package
A
16M x 18
16M x 18
16M x 18
16M x 18
16M x 18
16M x 18
16M x 18
16M x 18
8M x 36
8M x 36
8M x 36
8M x 36
8M x 36
8M x 36
8M x 36
8M x 36
GS82583ED18GK-675
GS82583ED18GK-625
GS82583ED18GK-550
GS82583ED18GK-500
GS82583ED18GK-675I
GS82583ED18GK-625I
GS82583ED18GK-550I
GS82583ED18GK-500I
GS82583ED36GK-675
GS82583ED36GK-625
GS82583ED36GK-550
GS82583ED36GK-500
GS82583ED36GK-675I
GS82583ED36GK-625I
GS82583ED36GK-550I
GS82583ED36GK-500I
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
SigmaQuad-IIIe B4
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
ROHS-Compliant 260-Pin BGA
675
625
550
500
675
625
550
500
675
625
550
500
675
625
550
500
C
C
C
C
I
I
I
I
C
C
C
C
I
I
I
I
Note: C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.06 8/2017
25/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ED18/36GK-675/625/550/500
Revision History
Rev. Code
Types of Changes
Format or Content
Revisions
GS82583ED1836GK_r1_01
GS82583ED1836GK_r1_02
—
• Initial public release.
Content
• Removed leaded BGA package support.
• Miscellaneous cleanup.
• Corrected write data input latency.
GS82583ED1836GK_r1_03
GS82583ED1836GK_r1_04
Content
Content
• Changed V spec to 1.3V 50mV.
DD
• Added package thermal impedances.
• Revised t
specs.
CQHCQH
• Removed Preliminary banner.
GS82583ED1836GK_r1_05
GS82583ED1836GK_r1_06
Content
Content
• Added I specs.
DD
• Removed ECCRAM references.
Rev: 1.06 8/2017
26/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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