GS8320ZV18T-150T [GSI]
ZBT SRAM, 2MX18, 7.5ns, CMOS, PQFP100, TQFP-100;
| 型号： | GS8320ZV18T-150T |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | ZBT SRAM, 2MX18, 7.5ns, CMOS, PQFP100, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总23页 (文件大小：629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
250 MHz–133 MHz
100-Pin TQFP
Commercial Temp
Industrial Temp
36Mb Pipelined and Flow Through
Synchronous NBT SRAMs
1.8 V V
DD
1.8 V I/O
Because it is a synchronous device, address, data inputs, and
Features
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
The GS8320ZV18/36T may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
Functional Description
The GS8320ZV18/36T is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
The GS8320ZV18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
t
2.5 2.7 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
KQ
Pipeline
3-1-1-1
tCycle
Curr (x18) 285 265 245 220 210 185 mA
Curr (x32/x36) 350 320 295 260 240 215 mA
t
6.5 7.0 7.5 8.0 8.5 8.5 ns
6.5 7.0 7.5 8.0 8.5 8.5 ns
KQ
Flow
Through
2-1-1-1
tCycle
Curr (x18) 205 195 185 175 165 155 mA
Curr (x32/x36) 235 225 210 200 190 175 mA
Rev: 1.01 10/2004
1/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
GS8320ZV18T Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
NC
V
DDQ
DDQ
SS
V
NC
DQPA
DQA
DQA
V
V
V
SS
NC
NC
DQB
DQB
2M x 18
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
DDQ
SS
V
DDQ
DQA
DQA
DQB
DQB
V
FT
SS
NC
V
V
DD
DD
V
DD
ZZ
V
SS
DQA
DQA
DQB
DQB
DDQ
V
V
V
DQA
DQA
NC
NC
V
V
NC
NC
NC
DDQ
SS
V
SS
DQB
DQB
DQPB
NC
V
SS
DDQ
SS
V
DDQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.01 10/2004
2/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
GS8320ZV36T Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPB
DQB
DQPC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB
DQC
V
V
V
DDQ
DDQ
SS
V
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
1M x 36
Top View
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
DDQ
SS
V
DDQ
DQB
DQB
DQC
DQC
FT
V
SS
NC
V
V
DD
DD
SS
V
ZZ
DD
V
DQA
DQA
DQD
DQD
V
V
V
DDQ
DDQ
SS
V
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
DDQ
SS
V
V
DDQ
DQA
DQD
DQA
DQD
DQPA
DQPD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.01 10/2004
3/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
100-Pin TQFP Pin Descriptions
Symbol
A0, A1
A
Type
In
Description
Burst Address Inputs; Preload the burst counter
In
Address Inputs
Clock Input Signal
CK
In
BA
In
Byte Write signal for data inputs DQA1-DQA9; active low
Byte Write signal for data inputs DQB1-DQB9; active low
Byte Write signal for data inputs DQC1-DQC9; active low
Byte Write signal for data inputs DQD1-DQD9; active low
Write Enable; active low
BB
In
BC
In
BD
In
W
In
E1
In
Chip Enable; active low
E2
In
Chip Enable; Active High. For self decoded depth expansion
Chip Enable; Active Low. For self decoded depth expansion
Output Enable; active low
E3
In
G
In
ADV
CKE
DQA
DQB
DQC
DQD
ZZ
In
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
Byte A Data Input and Output pins
In
I/O
I/O
I/O
I/O
In
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
LBO
In
V
In
Core power supply
DD
V
In
In
Ground
Output driver power supply
No Connect
SS
V
DDQ
NC
—
Rev: 1.01 10/2004
4/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
GS8320ZV18/36 NBT SRAM Functional Block Diagram
s
n s e e S A m p
i t r e W D r i v e r
s
Rev: 1.01 10/2004
5/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, & BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.01 10/2004
6/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Synchronous Truth Table
Operation
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
R
B
R
B
W
B
B
D
D
D
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
L
L
L
L
L
L
L
L
H
L
H
X
H
X
L
X
X
X
X
L
L
X
L
H
X
H
X
H
X
X
X
X
L
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
Q
Q
1,10
2
External
Next
H
H
X
X
X
X
X
X
High-Z
Dummy Read, Continue Burst
Write Cycle, Begin Burst
H
L
X
L
X
L
High-Z 1,2,10
External
Next
D
D
3
Write Cycle, Continue Burst
Write Abort, Continue Burst
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
H
H
L
X
X
X
X
X
L
X
X
H
X
X
X
X
X
H
X
1,3,10
Next
H
X
X
X
High-Z 1,2,3,10
High-Z
None
None
L
High-Z
None
L
High-Z
1
Deselect Cycle
D
D
None
L-H
L
L
L
H
L
H
L
X
L
High-Z
Deselect Cycle, Continue
Sleep Mode
None
None
L-H
X
L
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
High-Z
High-Z
-
1
4
Clock Edge Ignore, Stall
Current
L-H
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.01 10/2004
7/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Pipeline and Flow Through Read Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B and D represent input command
codes ,as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipeline and Flow Through Read/Write Control State Diagram
Rev: 1.01 10/2004
8/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
W
B
Intermediate
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.01 10/2004
9/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Flow Through Mode Data I/O State Diagram
R
W
B
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.01 10/2004
10/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
Burst Order Control
LBO
H
L
Output Register Control
Power Down Control
FT
ZZ
H or NC
L or NC
H
Active
Standby, I = I
DD SB
Note:
There is a pull-up device FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the
default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.01 10/2004
11/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
ZZ
tZZR
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V or V
on pipelined parts and V on flow
DD
DDQ
SS
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.01 10/2004
12/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 3.6
DD
DD
V
Voltage in V
Pins
DDQ
–0.5 to 3.6
V
DDQ
V
–0.5 to V
+0.5 (≤ 3.6 V max.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
I/O
V
–0.5 to V +0.5 (≤ 3.6 V max.)
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol
Min.
1.6
Typ.
1.8
Max.
2.0
Unit
V
Notes
V
1.8 V Supply Voltage
DD1
1.8 V V
I/O Supply Voltage
V
1.6
1.8
2.0
V
DDQ
DDQ1
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Rev: 1.01 10/2004
13/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Logic Levels
Parameter
Symbol
Min.
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
Input Low Voltage
V
0.6*V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
DD
V
V
0.3*V
DD
–0.3
—
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
0.6*V
V
+ 0.3
DDQ
—
1,3
1,3
DDQ
IHQ
DD
V
V
0.3*V
DD
–0.3
—
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
3.
V
(max) is voltage on V
pins plus 0.3 V.
IHQ
DDQ
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
pF
I/O
Note:
These parameters are sample tested.
Rev: 1.01 10/2004
14/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Input slew rate
V
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50Ω
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
≥ V ≥ V
IN
–1 uA
–1 uA
1 uA
100 uA
DD
IH
IH
I
I
ZZ Input Current
FT Input Current
IN1
IN2
0 V ≤ V ≤ V
IN
V
≥ V ≥ V
IN
–100 uA
–1 uA
1 uA
1 uA
DD
IL
IL
0 V ≤ V ≤ V
IN
I
Output Disable, V
= 0 to V
= 1.6 V
Output Leakage Current
Output High Voltage
Output Low Voltage
–1 uA
1 uA
—
OL
OUT
DD
V
I
= –4 mA, V
V
– 0.4 V
DDQ
OH1
OH
DDQ
V
I
= 4 mA, V = 1.6 V
OL DD
—
0.4 V
OL1
Rev: 1.01 10/2004
15/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Rev: 1.01 10/2004
16/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
AC Electrical Characteristics
-250
-225
-200
-166
-150
-133
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
tKC
tKQ
4.0
—
—
2.5
—
—
—
—
—
5.5
—
—
—
—
—
—
4.4
—
—
2.7
—
—
—
—
—
6.0
—
—
—
—
—
—
5.0
—
—
3.0
—
—
—
—
—
6.5
—
—
—
—
—
—
6.0
—
—
3.5
—
—
—
—
—
7.0
—
—
—
—
—
—
6.7
—
—
3.8
—
—
—
—
—
7.5
—
—
—
—
—
—
7.5
—
1.5
1.5
1.5
0.5
8.5
—
3.0
3.0
1.5
0.5
1.7
2
—
4.0
—
—
—
—
—
8.5
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock to Output Valid
Clock to Output Invalid
Pipeline
tKQX
1.5
1.5
1.2
0.2
5.5
—
3.0
3.0
1.5
0.5
1.3
1.5
1.5
1.5
1.3
0.3
6.0
—
3.0
3.0
1.5
0.5
1.3
1.5
1.5
1.5
1.4
0.4
6.5
—
3.0
3.0
1.5
0.5
1.3
1.5
1.5
1.5
1.5
0.5
7.0
—
3.0
3.0
1.5
0.5
1.3
1.5
1.5
1.5
1.5
0.5
7.5
—
3.0
3.0
1.5
0.5
1.5
1.7
1
Clock to Output in Low-Z
tLZ
Setup time
Hold time
tS
tH
Clock Cycle Time
Clock to Output Valid
tKC
tKQ
tKQX
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
Flow
Through
1
tLZ
tS
tH
Hold time
Clock HIGH Time
Clock LOW Time
tKH
tKL
Clock to Output in
High-Z
1
1.5
2.5
1.5
2.7
1.5
3.0
1.5
3.0 1.5 3.0 1.5 3.0
ns
tHZ
G to Output Valid
G to output in Low-Z
G to output in High-Z
ZZ setup time
tOE
—
0
2.5
—
2.5
—
—
—
—
0
2.7
—
2.7
—
—
—
—
0
3.0
—
3.0
—
—
—
—
0
3.5
—
3.0
—
—
—
—
0
3.8
—
3.0
—
—
—
—
0
4.0
—
3.0
—
—
—
ns
ns
ns
ns
ns
ns
1
tOLZ
1
—
5
—
5
—
5
—
5
—
5
—
5
tOHZ
2
tZZS
2
ZZ hold time
1
1
1
1
1
1
tZZH
ZZ recovery
tZZR
20
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.01 10/2004
17/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Pipeline Mode Timing (NBT)
Write A
Write B
Write B+1
tKL
tKH
Read C
tKC
Cont
Read D
Write E
Read F
DESELECT
CK
CKE
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
E*
ADV
W
Bn
A
B
C
D
E
F
G
A0–An
DQa–DQd
tH
tLZ
tHZ
tS
D(A)
tKQ
tKQX
D(E)
D(B)
D(B+1)
Q(C)
Q(D)
tOLZ
Q(F)
tOHZ
tOE
G
*Note: E=High(False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.01 10/2004
18/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1 Read C
tKL
Cont
Read D
Write E
Read F
Write G
tKH
tKC
CK
CKE
E
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
ADV
W
Bn
A0–An
A
B
C
D
E
F
G
tKQ
tLZ
tH
tKQ
tLZ
D(B+1)
tKQX
tS
D(A)
tHZ
Q(D)
tKQX
D(G)
DQ
G
D(B)
Q(C)
D(E)
Q(F)
tOLZ
tOE
tOHZ
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.01 10/2004
19/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
TQFP Package Drawing (Package T)
θ
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
0.10
7°
θ
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.01 10/2004
20/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Ordering Information—GSI NBT Synchronous SRAM
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
GS8320ZV18T-250
GS8320ZV18T-225
GS8320ZV18T-200
GS8320ZV18T-166
GS8320ZV18T-150
GS8320ZV18T-133
GS8320ZV36T-250
GS8320ZV36T-225
GS8320ZV36T-200
GS8320ZV36T-166
GS8320ZV36T-150
GS8320ZV36T-133
GS8320ZV18T-250I
GS8320ZV18T-225I
GS8320ZV18T-200I
GS8320ZV18T-166I
GS8320ZV18T-150I
GS8320ZV18T-133I
GS8320ZV36T-250I
GS8320ZV36T-225I
GS8320ZV36T-200I
GS8320ZV36T-166I
GS8320ZV36T-150I
GS8320ZV36T-133I
GS8320ZV18GT-250
GS8320ZV18GT-225
GS8320ZV18GT-200
GS8320ZV18GT-166
GS8320ZV18GT-150
GS8320ZV18GT-133
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
TQFP
TQFP
250/6
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
C
C
C
C
C
C
C
C
C
C
C
C
I
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
I
TQFP
I
TQFP
I
TQFP
I
TQFP
I
TQFP
I
TQFP
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
I
TQFP
I
TQFP
I
TQFP
I
TQFP
I
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
C
C
C
C
C
C
225/6.5
200/7.5
166/8.5
150/10
133/11
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320ZV36T-166IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.01 10/2004
21/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
Ordering Information—GSI NBT Synchronous SRAM
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
GS8320ZV36GT-250
GS8320ZV36GT-225
GS8320ZV36GT-200
GS8320ZV36GT-166
GS8320ZV36GT-150
GS8320ZV36GT-133
GS8320ZV18GT-250I
GS8320ZV18GT-225I
GS8320ZV18GT-200I
GS8320ZV18GT-166I
GS8320ZV18GT-150I
GS8320ZV18GT-133I
GS8320ZV36GT-250I
GS8320ZV36GT-225I
GS8320ZV36GT-200I
GS8320ZV36GT-166I
GS8320ZV36GT-150I
GS8320ZV36GT-133I
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
Pb-free TQFP
250/6
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
C
C
C
C
C
C
I
225/6.5
200/7.5
166/8.5
150/10
133/11
250/6
I
I
I
I
I
I
225/6.5
200/7.5
166/8.5
150/10
133/11
I
I
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320ZV36T-166IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.01 10/2004
22/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8320ZV18/36T-250/225/200/166/150/133
36Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
8320ZV18_r1
• Updated format
• Added Pb-free information for TQFP package
8320ZV18_r1; 8320ZV18_r1_01
Content/Format
Rev: 1.01 10/2004
23/23
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明