GS84018CGT-250IT [GSI]
Cache SRAM, 256KX18, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100;
| 型号： | GS84018CGT-250IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Cache SRAM, 256KX18, 5.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总22页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS84018/32/36CGT-250/200/166/150
TQFP
Commercial Temp
Industrial Temp
250 MHz–150 MHz
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
3.3 V V
DD
3.3 V and 2.5 V I/O
counter may be configured to count in either linear or
Features
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
• FT pin for user-configurable flow through or pipelined
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
Flow Through/Pipeline Reads
• 2.5 V or 3.3 V I/O supply
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (pin 14 in the TQFP and
bump 5R in the BGA). Holding the FT mode pin/bump low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipelined mode, activating the rising-edge-triggered
Data Output Register.
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock control, registered, address, data, and control
• Internal self-timed write cycle
SCD Pipelined Reads
• Automatic power-down for portable applications
• RoHS-compliant 100-lead TQFP package
The GS84018/32/36CGT is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Functional Description
Applications
The GS84018/32/36CGT is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS84018/32/36CGT is
available in a JEDEC standard 100-lead TQFP package.
Byte Write and Global Write
Byte write operation is performed by using byte write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Controls
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
Core and Interface Voltages
The GS84018/32/36CGT operates on a 3.3 V power supply
and all inputs/outputs are 3.3 V- and 2.5 V-compatible.
Separate output power (V
) pins are used to de-couple
DDQ
output noise from the internal circuit.
Parameter Synopsis
-250
-200
-166
-150
Unit
tKQ
2.5
4.0
3.0
5.0
3.0
5.0
3.8
6.7
ns
ns
tCycle
Pipeline
3-1-1-1
Curr (x18)
Curr (x32/x36)
195
225
170
195
160
185
140
160
mA
mA
tKQ
5.5
5.5
6.5
6.5
6.5
6.5
7.5
7.5
ns
ns
tCycle
Flow Through
2-1-1-1
Curr (x18)
Curr (x32/x36)
160
180
140
160
135
155
128
145
mA
mA
Rev: 1.01 11/2014
1/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
GS84018C 100-Pin TQFP Pinout (Package GT)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
V
NC
DQPA
DQA
DQA
V
DDQ
DDQ
V
SS
SS
NC
NC
DQB
DQB
256K x 18
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
VDDQ
DQA
DQA
V
NC
VDD
ZZ
DQA
DQA
VDDQ
Top View
V
DDQ
DQB
DQB
FT
SS
V
DD
NC
V
SS
DQB
DQB
V
DDQ
V
V
SS
SS
DQA
DQA
NC
NC
V
VDDQ
NC
NC
DQB
DQB
DQPB
NC
V
SS
SS
V
DDQ
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either V or V . These pins can also be left floating.
DD
SS
Rev: 1.01 11/2014
2/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
GS84032C 100-Pin TQFP Pinout (Package GT)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
DQB
DQB
V
NC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
DDQ
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
128K x 32
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
FT
V
SS
NC
V
DD
V
NC
DD
ZZ
V
SS
DQA
DQA
V
DQD
DQD
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
NC
DQD
DQD
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
Rev: 1.01 11/2014
3/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
GS84036C 100-Pin TQFP Pinout (Package GT)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPB
DQB
DQB
DQPC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
V
DDQ
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
128K x 36
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
FT
V
SS
NC
V
DD
V
NC
DD
ZZ
DQA
DQA
V
SS
DQD
DQD
V
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
DQPA
DQD
DQD
DQPD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
Rev: 1.01 11/2014
4/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
TQFP Pin Description
Symbol
A0, A1
A
Type
Description
I
Address field LSBs and Address Counter preset Inputs
Address Inputs
I
In
In
In
In
I
BA
Byte Write signal for data inputs DQA; active low
Byte Write signal for data inputs DQB; active low
Byte Write signal for data inputs DQC; active low
Byte Write signal for data inputs DQD; active low
Byte Write—Writes all enabled bytes; active low
Clock Input Signal; active high
BB
BC
BD
BW
CK
I
GW
I
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
E1, E3
E2
I
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
ADSP, ADSC
DQA
DQB
DQ
I
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
9th Data I/O Pin; Byte A
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
DQD
DQPA
DQPB
DQPC
DQPD
ZZ
9th Data I/O Pin; Byte B
9th Data I/O Pin; Byte C
9th Data I/O Pin; Byte D
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
LBO
I
V
I
DD
V
I
I
-
I/O and Core Ground
Output driver power supply
No Connect
SS
V
DDQ
NC
Rev: 1.01 11/2014
5/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
GS84018/32/36CGT Block Diagram
Register
A0–An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
36
36
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E3
E2
D
Q
Register
D
Q
FT
G
1
Power Down
Control
DQxn–DQxn
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.01 11/2014
6/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
Burst Order Control
Output Register Control
Power Down Control
LBO
H
L
FT
ZZ
H or NC
L or NC
H
Active
Standby, IDD = ISB
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
A[1:0]
A[1:0]
01
A[1:0]
10
A[1:0]
11
1st address
2nd address
3rd address
4th address
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
10
11
00
00
11
10
11
00
01
11
00
01
00
01
10
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.01 11/2014
7/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
Write No Bytes
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.01 11/2014
8/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Synchronous Truth Table
State
Diagram
Key
Address
Used
3
Operation
E1
E2
E3
ADSP
ADSC
ADV
W
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
None
None
X
X
L
L
L
L
H
L
L
L
X
H
X
H
X
H
X
H
X
L
H
X
H
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
X
X
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
None
X
X
L
X
X
L
High-Z
None
X
L
High-Z
None
X
X
H
H
H
X
X
X
X
X
X
X
X
X
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
R
H
H
H
X
H
X
H
X
H
X
W
CR
CR
CW
CW
L
H
H
H
H
H
H
H
H
Next
Next
Next
Current
Current
Current
Current
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.01 11/2014
9/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CR
CW
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
Rev: 1.01 11/2014
10/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.01 11/2014
11/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
VDD
VDDQ
VI/O
Description
Value
–0.5 to 4.6
Unit
V
Voltage on VDD Pins
Voltage in VDDQ Pins
–0.5 to 4.6
V
–0.5 to VDD +0.5 ( 4.6 V max.)
–0.5 to VDD +0.5 ( 4.6 V max.)
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
VIN
V
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
1.5
oC
oC
TSTG
–55 to 125
–55 to 125
TBIAS
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol
VDD3
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
3.3 V Supply Voltage
VDD2
2.5 V Supply Voltage
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
2.5 V VDDQ I/O Supply Voltage
VDDQ3
VDDQ2
3.0
3.3
3.6
V
2.3
2.5
2.7
V
V
Range Logic Levels
DD3
Parameter
Symbol
VIH
Min.
2.0
Typ.
—
Max.
Unit
V
VDD + 0.3
Input High Voltage
Input Low Voltage
VIL
–0.3
—
0.8
V
Note:
(max) must be met for any instantaneous value of V
V
.
DD
IH
Rev: 1.01 11/2014
12/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
V
Range Logic Levels
DD2
Parameter
Symbol
VIH
Min.
Typ.
—
Max.
Unit
V
0.6*VDD
VDD + 0.3
0.3*VDD
Input High Voltage
Input Low Voltage
VIL
–0.3
—
V
Note:
(max) must be met for any instantaneous value of V
V
.
DD
IH
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Junction Temperature
(Commercial Range Versions)
TJ
0
25
25
85
C
C
Junction Temperature
(Industrial Range Versions)*
TJ
–40
100
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Thermal Impedance
Test PCB
Substrate
JA (C°/W)
Airflow = 0 m/s
JA (C°/W)
Airflow = 1 m/s
JA (C°/W)
Airflow = 2 m/s
Package
JB (C°/W)
JC (C°/W)
100 TQFP
4-layer
38.7
33.5
31.9
27.6
10.6
Notes:
1. Thermal Impedance data is based on a number of samples from multiple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
DD
V
SS
50%
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Note:
Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Rev: 1.01 11/2014
13/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
Typ.
Max.
Unit
pF
Input Capacitance
4
6
5
7
CI/O
VOUT = 0 V
Input/Output Capacitance
pF
Note:
These parameters are sample tested.
AC Test Conditions
Parameter
Conditions
VDD – 0.2 V
Input high level
Input low level
0.2 V
1 V/ns
VDD/2
Input slew rate
Input reference level
VDDQ/2
Output reference level
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
Rev: 1.01 11/2014
14/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Rev: 1.01 11/2014
15/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
AC Electrical Characteristics
-250
-200
-166
-150
Parameter
Symbol
Min
4.0
—
Max
—
Min
5.5
—
Max
—
Min
6.0
—
Max
—
Min
6.7
—
Max
—
Clock Cycle Time
tKC
tKQ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock to Output Valid
2.5
—
3.0
—
3.5
—
3.8
—
Clock to Output Invalid
Pipeline
tKQX
1.5
1.5
1.2
0.2
5.5
—
1.5
1.5
1.4
0.4
6.5
—
1.5
1.5
1.5
0.5
7.0
—
1.5
1.5
1.5
0.5
7.5
—
tLZ1
tS
Clock to Output in Low-Z
—
—
—
—
Setup time
Hold time
—
—
—
—
tH
—
—
—
—
Clock Cycle Time
Clock to Output Valid
tKC
tKQ
tKQX
—
—
—
—
5.5
—
6.5
—
7.0
—
7.5
—
Clock to Output Invalid
2.0
2.0
1.5
0.5
1.3
1.5
1.5
—
2.0
2.0
1.5
0.5
1.3
1.5
1.5
—
2.0
2.0
1.5
0.5
1.3
1.5
1.5
—
2.0
2.0
1.5
0.5
1.3
1.5
1.5
—
Flow
Through
tLZ1
tS
Clock to Output in Low-Z
Setup time
—
—
—
—
—
—
—
—
Hold time
tH
—
—
—
—
Clock HIGH Time
Clock LOW Time
Clock to Output in High-Z
G to Output Valid
G to output in Low-Z
tKH
tKL
—
—
—
—
—
—
—
—
tHZ1
tOE
2.5
2.5
—
3.0
3.0
—
3.0
3.5
—
3.0
3.8
—
tOLZ1
tOHZ1
tZZS2
0
0
0
0
G to output in High-Z
ZZ setup time
ZZ hold time
—
5
2.5
—
—
—
—
5
3.0
—
—
—
—
5
3.0
—
—
—
—
5
3.0
—
—
—
ns
ns
ns
ns
tZZH2
tZZR
1
1
1
1
ZZ recovery
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.01 11/2014
16/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Pipeline Mode Timing
Begin
Read A Cont
Single Read
Cont
Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont
Deselect
Single Write
tKL
Burst Read
tKH
tKC
CK
ADSP
tS
tS
tH
ADSC initiated read
ADSC
ADV
tS
tH
tH
A
B
C
A0–An
GW
tS
tS
tH
tH
BW
tS
Ba–Bd
E1
tS
tS
tS
Deselected with E1
tH
E1 masks ADSP
tH
tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
G
tS
D(B)
tKQ
tKQX
tHZ
tOE
tOHZ
Q(A)
tH
tLZ
Q(C)
Q(C+1)
Q(C+2) Q(C+3)
DQa–DQd
Rev: 1.01 11/2014
17/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Flow Through Mode Timing
Begin
Read A Cont
tKH
Cont
Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont
Deselect
tKL
tKC
CK
Fixed High
ADSP
tS
tH
tS
tH
ADSC initiated read
ADSC
ADV
A0–An
GW
tS
tH
tS
tH
A
B
C
tS
tH
tS
tH
BW
tS
tH
Ba–Bd
E1
tS
tS
Deselected with E1
tH
tH
E2 and E3 only sampled with ADSC
E2
tS
tH
E3
G
tH
tS
tKQ
tLZ
tHZ
tOE
tOHZ
D(B)
tKQX
Q(A)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
DQa–DQd
Rev: 1.01 11/2014
18/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
Setup
Hold
ADSP
ADSC
tZZR
tZZS
tZZH
ZZ
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.01 11/2014
19/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
TQFP Package Drawing (Package GT)
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
0.10
7
0
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.01 11/2014
20/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
T
Part Number
J
(MHz/ns)
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
GS84018CGT-250
GS84018CGT-200
GS84018CGT-166
GS84018CGT-150
GS84032CGT-250
GS84032CGT-200
GS84032CGT-166
GS84032CGT-150
GS84036CGT-250
GS84036CGT-200
GS84036CGT-166
GS84036CGT-150
GS84018CGT-250I
GS84018CGT-200I
GS84018CGT-166I
GS84018CGT-150I
GS84032CGT-250I
GS84032CGT-200I
GS84032CGT-166I
GS84032CGT-150I
GS84036CGT-250I
GS84036CGT-200I
GS84036CGT-166I
GS84036CGT-150I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
250/5.5
200/6.5
166/7
C
C
C
C
C
C
C
C
C
C
C
C
I
150/7.5
250/5.5
200/6.5
166/7
150/7.5
250/5.5
200/6.5
166/7
150/7.5
250/5.5
200/6.5
166/7
I
I
150/7.5
250/5.5
200/6.5
166/7
I
I
I
I
150/7.5
250/5.5
200/6.5
166/7
I
I
I
I
150/7.5
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032CGT-250T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. C = Commercial Temperature Range. I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.01 11/2014
21/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84018/32/36CGT-250/200/166/150
9Mb Sync SRAM Datasheet Revision History
Types of Changes
Format or Content
File Name
Revisions
• Creation of datasheet
84036CGT_r1
• Added x18 and x32 configurations
840xxCGT_r1_01
Content
Rev: 1.01 11/2014
22/22
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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