GS840H18AB-200T [GSI]
Standard SRAM, 256KX18, 7.5ns, CMOS, PBGA119;
| 型号： | GS840H18AB-200T |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Standard SRAM, 256KX18, 7.5ns, CMOS, PBGA119 静态存储器 |
| 文件： | 总31页 (文件大小：944K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
TQFP, BGA
Commercial Temp
Industrial Temp
200 MHz–100 MHz
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
3.3 V V
DD
3.3 V and 2.5 V I/O
Burst mode, subsequent burst addresses are generated
Features
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
• FT pin for user configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) Operation
• High output drive current
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (Pin 14 in the TQFP and
Bump 5R in the BGA, ). Holding the FT mode pin/bump low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-dge-triggered
Data Output Register.
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs\
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP or 119-Bump BGA
package.
SCD Pipelined Reads
The GS840H18/32/36A is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
-200 -180 -166 -150 -100
Unit
tCycle 5.0
5.5
3.2
6.0
3.5
170
6.6
3.8
155
10
4.5
105
ns
ns
mA
Pipeline
3-1-1-1
tKQ
IDD
3.0
205 185
Byte Write and Global Write
Flow
tKQ
7.5
8
9.1
8.5
10
105
10
10
105
12
15
80
ns
ns
mA
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Through tCycle 8.8
2-1-1-1
IDD
115 115
Functional Description
Sleep Mode
Applications
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
The GS840H18/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS840H18/32/36A is
available in a JEDEC-standard 100-lead TQFP or 119-Bump
BGA package.
Core and Interface Voltages
The GS840H18/32/36A operates on a 3.3 V power supply and
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Rev: 1.08 3/2001
1/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
GS840H18A 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A17
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
VDDQ
DQA5
VSS
NC
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
FT
VDD
NC
VSS
DQB5
DQB6
VDDQ
5
6
7
8
9
256K x 18
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.08 3/2001
2/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
GS840H32A 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB8
DQB7
VVDDQDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
DQC8
DQC7
VDDQ
2
3
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
VSS
DQD1
DQD2
VDDQ
5
6
7
8
9
128K x 32
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.08 3/2001
3/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
GS840H36A 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
DQC9
DQC8
DQC7
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
5
6
7
8
9
128K x 36
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
VSS
DQD1
DQD2
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
DQD9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.08 3/2001
4/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
TQFP Pin Description
Pin Location
Symbol
Type
Description
37, 36
A0, A1
I
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46,
47, 48, 49, 50
A2–A16
I
I
Address Inputs
80
A17
Address Inputs (x18 versions)
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
I/O
Data Input and Output pins (x32, x36 Version)
18, 19, 22, 23, 24, 25, 28, 29
DQA9, DQB9,
DQC9, DQD9
51, 80, 1, 30
I/O
—
Data Input and Output pins (x36 Version)
No Connect (x32 Version)
51, 80, 1, 30
NC
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQA1–DQA9
DQB1–DQB9
I/O
Data Input and Output pins (x18 Version)
51, 52, 53, 56, 57
75, 78, 79
NC
—
No Connect (x18 Version)
1, 2, 3, 6, 7
25, 28, 29, 30
87
BW
I
I
Byte Write—Writes all enabled bytes; active low
93, 94
BA, BB
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/Os; active low
(x32, x36 Version)
95, 96
BC, BD
I
95, 96
NC
CK
—
I
No Connect (x18 Version)
Clock Input Signal; active high
89
88
GW
I
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
98, 92
E1, E3
E2
I
97
I
Chip Enable; active high
86
G
I
Output Enable; active low
83
ADV
ADSP, ADSC
ZZ
I
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
84, 85
I
64
I
14
31
FT
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
LBO
VDD
I
15, 41, 65, 91
I
VSS
VDDQ
NC
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
16, 38, 39, 42, 43, 66
I
I
I/O and Core Ground
Output driver power supply
No Connect
—
Rev: 1.08 3/2001
5/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
GS840H18A Pad Out
119-Bump BGA—Top View
1
2
3
4
ADSP
ADSC
VDD
NC
5
6
7
A
B
C
D
E
F
VDDQ
NC
A6
A7
A8
A9
VDDQ
NC
E2
A4
A15
A14
VSS
VSS
VSS
NC
VSS
NC
VSS
BA
E3
NC
A5
A3
A16
NC
DQB1
NC
NC
VSS
VSS
VSS
BB
DQA9
NC
NC
DQB2
NC
E1
DQA8
VDDQ
DQA6
NC
VDDQ
NC
G
DQA7
NC
DQB3
NC
VDD
DQB5
NC
ADV
GW
VDD
CK
G
H
J
DQB4
VDDQ
NC
VSS
NC
VSS
NC
VSS
VSS
VSS
LBO
A11
NC
DQA5
VDD
NC
VDDQ
DQA4
NC
K
L
DQB6
VDDQ
DQB8
NC
NC
DQA3
NC
DQB7
NC
BW
A1
VSS
VSS
VSS
FT
VDDQ
NC
M
N
P
R
T
DQA2
NC
DQB9
A2
A0
DQA1
NC
NC
VDD
NC
A13
NC
A10
A12
NC
A17
ZZ
VDDQ
NC
NC
NC
VDDQ
U
Rev: 1.08 3/2001
6/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
GS840H32A Pad Out
119-Bump BGA—Top View
1
2
3
4
ADSP
ADSC
VDD
NC
5
6
7
A
B
C
D
E
F
VDDQ
NC
A6
A7
A8
A9
VDDQ
NC
E2
A4
A15
A14
VSS
VSS
VSS
BB
E3
NC
A5
A3
A16
NC
DQC4
DQC3
VDDQ
DQC2
DQC1
VDDQ
DQD1
DQD2
VDDQ
DQD3
DQD4
NC
NC
VSS
VSS
VSS
BC
NC
DQB4
DQB3
VDDQ
DQB2
DQB1
VDDQ
DQA1
DQA2
VDDQ
DQA3
DQA4
NC
DQC8
DQC7
DQC6
DQC5
VDD
DQD5
DQD6
DQD78
DQD8
NC
E1
DQB8
DQB7
DQB6
DQB5
VDD
DQA5
DQA6
DQA7
DQA8
NC
G
ADV
GW
VDD
CK
G
H
J
VSS
NC
VSS
BD
VSS
NC
VSS
BA
K
L
NC
VSS
VSS
VSS
LBO
A10
NC
BW
A1
VSS
VSS
VSS
FT
M
N
P
R
T
A0
A2
VDD
A11
NC
A13
NC
NC
A12
NC
NC
ZZ
VDDQ
NC
NC
VDDQ
U
Rev: 1.08 3/2001
7/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
GS840H36APad Out
119-Bump BGA—Top View
1
2
3
4
ADSP
ADSC
VDD
NC
5
6
7
A
B
C
D
E
F
VDDQ
NC
A6
A7
A8
A9
VDDQ
NC
E2
A4
A15
A14
VSS
VSS
VSS
BB
E3
NC
A5
A3
A16
NC
DQC4
DQC3
VDDQ
DQC2
DQC1
VDDQ
DQD1
DQD2
VDDQ
DQD3
DQD4
NC
DQC9
DQC8
DQC7
DQC6
DQC5
VDD
VSS
VSS
VSS
BC
DQB9
DQB8
DQB7
DQB6
DQB5
VDD
DQA5
DQA6
DQA7
DQA8
DQA9
A13
DQB4
DQB3
VDDQ
DQB2
DQB1
VDDQ
DQA1
DQA2
VDDQ
DQA3
DQA4
NC
E1
G
ADV
GW
VDD
CK
G
H
J
VSS
NC
VSS
BD
VSS
NC
VSS
BA
DQD5
DQD6
DQD78
DQD8
DQD9
A2
K
L
NC
VSS
VSS
VSS
LBO
A10
NC
BW
A1
VSS
VSS
VSS
FT
M
N
P
R
T
A0
VDD
A11
NC
NC
NC
A12
NC
NC
ZZ
VDDQ
NC
NC
VDDQ
U
Rev: 1.08 3/2001
8/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
BGA Pin Description
Pin Location
Symbol
Type
Description
N4, P4
A0, A1
I
Address field LSBs and Address Counter Preset Inputs
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, R2, R6, T3, T5
An
I
Address Inputs
T4
An
NC
An
—
—
I
Address Input (x32/36 Versions)
No Connect (x32/36 Versions)
Address Input (x18 Version)
T2, T6
T2, T6
K7, K6, L7, L6, M6, N7, N6, P7
H7, H6, G7, G6, F6, E7, E6, D7
H1, H2, G1, G2, F2, E1, E2, D1
K1, K2, L1, L2, M2, N1, N2, P1
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
I/O
Data Input and Output pins (x32/36 Versions)
Data Input and Output pins (x36 Version)
DQA9, DQB9,
DQC9, DQD9
P6, D6, D2, P2
I/O
P6, D6, D2, P2
L5, G5, G3, L3
NC
—
I
No Connect (x32 Version)
BA, BB, BC, BD
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2 DQB1–DQB9
DQA1–DQA9
I/O
I
Data Input and Output pins (x18 Version)
Byte Write Enable for DQA, DQB I/Os; active low ( x18 Version)
No Connect
L5, G3
BA, BB
B1, C1, R1, T1, U2, J3, U3, D4, L4,
U4, J5, U5, U6, B7, C7, R7
NC
—
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, B1, E1, F2, G1, H2, K1, L2, N2,
P1, G5, L3, T4
NC
—
No Connect (x18 Version)
K4
CK
BW
I
I
I
I
I
I
I
I
I
I
I
I
Clock Input Signal; active high
Byte Write—Writes all enabled bytes; active low
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
M4
H4
GW
E4, B6
E1, E3
E2
B2
Chip Enable; active high
F4
G
Output Enable; active low
G4
ADV
ADSP, ADSC
ZZ
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
A4, B4
T7
R5
R3
FT
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
LBO
VDD
J2, C4, J4, R4, J6
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
VSS
I
I
I/O and Core Ground
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
VDDQ
Output driver power supply
Rev: 1.08 3/2001
9/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
GS840H18/32/36A Block Diagram
Register
A0–An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
36
36
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E3
E2
D
Q
Register
D
Q
FT
G
1
Power Down
Control
DQx0–DQx9
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.08 3/2001
10/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Mode Pin Functions
Mode Name
Pin
Name
State
Function
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Burst Order Control
LBO
H or NC
L
Output Register Control
FT
H or NC
L or NC
H
Active
Power Down Control
ZZ
Standby, IDD = ISB
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
B
A
B
B
B
C
B
D
Notes
1
X
H
L
X
H
H
L
X
H
H
H
L
X
H
H
H
H
L
Read
H
1
Write byte A
Write byte B
Write byte C
Write byte D
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.08 3/2001
11/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Synchronous Truth Table
Operation
State
Address
Used
2
3
4
Diagram
E1
ADSP ADSC ADV
E
W
DQ
5
Key
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
None
None
X
X
H
L
X
X
L
L
X
L
X
X
X
X
X
X
L
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
F
F
T
T
T
X
X
X
X
X
X
X
X
High-Z
None
X
L
L
H
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
1. X = Don’t Care, H = High, L = Low.
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.08 3/2001
12/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CR
CW
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
Rev: 1.08 3/2001
13/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.08 3/2001
14/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
VDD
Description
Value
Unit
Voltage on VDD Pins
–0.5 to 4.6
V
V
VDDQ
VCK
Voltage in VDDQ Pins
–0.5 to VDD
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
V
VI/O
–0.5 to VDDQ+0.5 (£ 4.6 V max.)
V
VIN
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
–0.5 to VDD+0.5 (£ 4.6 V max.)
V
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
TSTG
TBIAS
1.5
oC
oC
–55 to 125
–-55 to 125
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Symbol
VDD
VDDQ
VIH
Min.
Typ.
Max.
Unit
Notes
Supply Voltage
3.135
2.375
1.7
3.3
2.5
—
3.6
VDD
V
V
I/O Supply Voltage
Input High Voltage
Input Low Voltage
1
2
2
3
3
VDD+0.3
V
VIL
–0.3
0
—
0.8
70
85
V
TA
Ambient Temperature (Commercial Range Versions)
25
25
°C
°C
TA
Ambient Temperature (Industrial Range Versions)
–40
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V £ VDDQ £ 2.375V (i.e. 2.5V I/O)
and 3.6V £ VDDQ £ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be -2V > Vi < VDD+2V with a pulse width not to exceed 20% tKC.
Rev: 1.08 3/2001
15/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD+-2.0V
VSS
50%
VDD
50%
VSS-2.0V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Symbol
Test conditions
VDD = 3.3 V
Typ.
Max.
Unit
CI
Control Input Capacitance
Input Capacitance
3
4
6
4
5
7
pF
pF
pF
CIN
VIN = 0 V
COUT
VOUT = 0 V
Output Capacitance
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating
Layer Board
Symbol
RQJA
TQFP Max BGA Max
Unit
Notes
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
single
four
—
40
24
9
38
21
5
°C/W
°C/W
°C/W
1,2,4
1,2,4
3,4
RQJA
RQJC
Junction to Case (TOP)
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
4. For x18 configuration, consult factory.
Rev: 1.08 3/2001
16/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
AC Test Conditions
Parameter
Conditions
Input high level
Input low level
2.3 V
0.2 V
Input slew rate
1 V/ns
1.25 V
1.25 V
Fig. 1& 2
Input reference level
Output reference level
Output load
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
.
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225W
225W
DQ
30pF*
50W
VT = 1.25 V
5pF*
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ³ VIN ³ VIH
0 V £ VIN £ VIH
–1 uA
–1 uA
1 uA
300 uA
IINZZ
ZZ Input Current
VDD ³ VIN ³ VIL
0 V £ VIN £ VIL
–300 uA
–1 uA
1 uA
1 uA
IINM
IOL
Mode Pin Input Current
Output Leakage Current
Output Disable,
VOUT = 0 to VDD
–1 uA
1 uA
VOH
VOH
VOL
IOH = –8 mA, VDDQ = 2.375 V
IOH = –8 mA, VDDQ = 3.135 V
IOL = 8 mA
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
—
—
—
0.4 V
Rev: 1.08 3/2001
17/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Operating Currents
-200
-180
-166
-150
-100
Test
Conditions
Parameter
Symbol
Unit
0 to –40to 0 to –40to 0 to –40to 0 to –40to 0 to –40to
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
IDD
Pipeline
Device Selected;
All other inputs
³ VIH or £ VIL
205
115
20
235
145
30
185
115
20
195
125
30
170
105
20
180
115
30
155
105
20
165
115
30
105
80
20
20
20
15
115
90
30
30
30
25
mA
mA
mA
mA
mA
mA
Operating
Current
IDD
Flow-Thru
Output open
ISB
Pipeline
ZZ ³ VDD –
Standby
Current
0.2 V
ISB
Flow-Thru
20
30
20
30
20
30
20
30
IDD
Pipeline
Device
Deselected;
All other inputs
³ VIH or £ VIL
40
70
35
45
30
40
30
40
Deselect
Current
IDD
Flow-Thru
25
55
20
30
20
30
20
30
Rev: 1.08 3/2001
18/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
AC Electrical Characteristics
-200
-180
-166
-150
-100
Parameter
Symbol
Unit
Min
Max
—
Min
Max
—
Min
6.0
—
Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock Cycle Time
tKC
tKQ
5.0
—
5.5
—
—
3.5
—
6.7
—
—
3.8
—
10
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.0
—
3.2
—
Pipeline
tKQX
1.5
1.5
8.8
—
1.5
1.5
9.1
—
1.5
1.5
10.0
—
1.5
1.5
10.0
—
1.5
1.5
15.0
—
—
—
—
12.0
—
—
—
—
5
tLZ1
tKC
—
—
—
—
—
—
—
—
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQ
7.5
—
8.0
—
8.5
—
10.0
—
Flow-
Thru
tKQX
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
tLZ1
tKH
tKL
—
—
—
—
—
—
—
—
Clock LOW Time
—
—
—
—
tHZ1
tOE
Clock to Output in High-Z
G to Output Valid
3.0
3.0
—
3.2
3.2
—
3.5
3.5
—
3.8
3.8
—
5
tOLZ1
G to output in Low-Z
0
0
0
0
0
—
tOHZ1
tS
G to output in High-Z
Setup time
—
1.5
0.5
5
3.0
—
—
—
—
1.5
0.5
5
3.2
—
—
—
—
1.5
0.5
5
3.5
—
—
—
—
1.5
0.5
5
3.8
—
—
—
—
1.5
0.5
5
5
ns
ns
ns
ns
—
—
—
Hold time
tH
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.08 3/2001
19/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Write Cycle Timing
Single Write
Burst Write
Deselected
Write
CK
tH
tS
ADSP is blocked by E1 inactive
tKC
tKL
tKH
ADSP
tS tH
ADSC initiated write
ADSC
tH
tS
ADV
ADV must be inactive for ADSP Write
tH
tS
WR2
WR3
WR1
A0–An
tS tH
GW
BW
tH
tS
tS
tH
WR3
WR1
WR2
BA–BD
tS
tH
tH
E1 masks ADSP
E1
tS
Deselected with E2
E2
tS tH
E2 and E3 only sampled with ADSP or ADSC
E3
G
tS
Write specified byte for 2a and all bytes for 2b, 2c& 2d
D2c D2d D3a
tH
Hi-Z
DQA–DQD
D1a
D2a
D2b
Rev: 1.08 3/2001
20/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tS
tKH
tH
ADSP is blocked by E1 inactive
ADSC initiated read
tKC
ADSP
ADSC
ADV
tS tH
tH
tS
Suspend Burst
Suspend Burst
tS
tH
RD1
RD2
RD3
A0–An
GW
tS
tS
tH
tH
BW
BA–BD
E1
tH
tS
E1 masks ADSP
tS tH
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
tS
tH
E3
G
tOHZ
tOE
tKQX
tKQX
tOLZ
Q2b
Q2c
Q3a
Q1a
Q2a
Q2d
DQA–DQD
Hi-Z
tLZ
tHZ
tKQ
Rev: 1.08 3/2001
21/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Flow Through Read-Write Cycle Timing
Single Write
Burst Read
Single Read
CK
tS tH
tKC
ADSP is blocked by E inactive
ADSC initiated read
tKH tKL
ADSP
ADSC
tS tH
tS tH
ADV
tS
tH
RD2
RD1
WR1
A0–An
tS
tS
tH
GW
tH
BW
tS
tH
BA–BD
WR1
tS
tS
tS
tH
E1 masks ADSP
E1
tH
tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
Deselected with E3
tOHZ
tOE
G
tS
D1a
tH
tKQ
Hi-Z
DQA–DQD
Q1a
Q2a
Q2a
Q2b
Q2c
Q2d
Burst wrap around to it’s initial state
Rev: 1.08 3/2001
22/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Pipelined SCD Read Cycle Timing
Single Read
Burst Read
CK
tKL
tKH
tH
tH
tS
tKC
ADSP is blocked by E1 inactive
ADSP
ADSC
tS
ADSC initiated read
tS tH
Suspend Burst
ADV
tH
tS
RD2
RD3
RD1
A0–A17
GW
tS
tS
tH
tH
BW
BWA–BWD
E1
tH
tS
E1 masks ADSP
tS tH
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
E3
tS
tH
tOE
G
tOHZ
tKQX
tKQX
tOLZ
tLZ
Hi-Z
DQA–DQD
Q1a
Q2a
Q2b
Q3a
tHZ
Q2d
Q2c
tKQ
Rev: 1.08 3/2001
23/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Pipelined SCD Read-Write Cycle Timing
Single Write
Single Read
Burst Read
tKL
CK
tH
tS
tKH
tKC
ADSP is blocked by E inactive
ADSC initiated read
ADSP
ADSC
tS tH
tS tH
ADV
tS
tH
RD2
RD1
WR1
A0–An
tS
tS
tH
GW
tH
BW
tH
tS
WR1
BWA–BWD
tS
tH
E1 masks ADSP
E1
tS tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
tH
tS
Deselected with E3
tOE
tOHZ
G
tS
tH
tKQ
Hi-Z
Q1a
D1a
Q2a
Q2b
Q2c
DQA–DQD
Q2d
Rev: 1.08 3/2001
24/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings) but greater care must be exercised to avoid excessive bus contention.
Rev: 1.08 3/2001
25/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
GS840H18/32/36A Output Driver Characteristics
120.0
100.0
Pull Down Drivers
80.0
60.0
40.0
20.0
0.0
VDDQ
I Out
VOut
VSS
-20.0
-40.0
-60.0
Pull Up Drivers
-80.0
-100.0
-120.0
-140.0
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD HD
3.3V PD HD
3.1V PD HD
3.1V PU HD
3.3V PU HD
3.6V PU HD
Rev: 1.08 3/2001
26/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
TQFP Package Drawing
q
L
c
Symbol
Description
Standoff
Min. Nom. Max
L1
A1
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
A2
Body Thickness
Lead Width
b
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
—
D1
e
E
E1
Package Body
Lead Pitch
13.9
—
e
b
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
q
—
0.10
7°
0°
—
A1
Notes:
A2
E1
E
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion
Rev: 1.08 3/2001
27/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Package Dimensions—119-Pin BGA
Pin 1
Corner
A
7 6 5 4 3 2
1
A
B
C
D
E
F
G
H
J
G
D
B
P
S
K
L
M
N
P
R
T
U
R
N
Bottom View
Top View
Package Dimensions—119-Pin BGA
Symbol
Description
Width
Min. Nom. Max
13.8 14.0 14.2
21.8 22.0 22.2
A
B
Length
C
Package Height (including ball)
Ball Size
—
—
2.40
D
0.60 0.75 0.90
0.50 0.60 0.70
E
Ball Height
F
Package Height (excluding balls)
Width between Balls
Package Height above board
Cut-out Package Width
Foot Length
—
—
1.46 1.70
1.27
G
—
K
0.80 0.90 1.00
N
—
—
—
—
—
12.00
19.50
7.62
—
—
—
—
—
P
R
Width of package between balls
Length of package between balls
Variance of Ball Height
S
T
20.32
0.15
Unit: mm
Side View
Rev: 1.08 3/2001
28/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Ordering Information for GSI Synchronous Burst RAMS
2
T
3
Speed
A
1
Org
Type
Package
Status
Part Number
(MHz/ns)
200/7.5
180/8
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
GS840H18AT-200
GS840H18AT-180
GS840H18AT-166
GS840H18AT-150
GS840H18AT-100
GS840H32AT-200
GS840H32AT-180
GS840H32AT-166
GS840H32AT-150
GS840H32AT-100
GS840H36AT-200
GS840H36AT-180
GS840H36AT-166
GS840H36AT-150
GS840H36AT-100
GS840H18AT-200I
GS840H18AT-180I
GS840H18AT-166I
GS840H18AT-150I
GS840H18AT-100I
GS840H32AT-200I
GS840H32AT-180I
GS840H32AT-166I
GS840H32AT-150I
GS840H32AT-100I
GS840H36AT-200I
GS840H36AT-180I
GS840H36AT-166I
GS840H36AT-150I
GS840H36AT-100I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
166/8.5
150/10
100/12
200/7.5
180/8
166/8.5
150/10
100/12
200/7.5
180/8
166/8.5
150/10
100/12
200/7.5
180/8
Not Available
Not Available
Not Available
I
166/8.5
150/10
100/12
200/7.5
180/8
I
I
I
I
I
166/8.5
150/10
100/12
200/7.5
180/8
I
I
I
I
I
166/8.5
150/10
100/12
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AT-7.5T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.08 3/2001
29/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
2
T
3
Speed
A
1
Org
Type
Package
Status
Part Number
(MHz/ns)
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
GS84018AB-200
GS840H18AB-180
GS840H18AB-166
GS840H18AB-150
GS840H18AB-100
GS840H32AB-200
GS840H32AB-180
GS840H32AB-166
GS840H32AB-150
GS840H32AB-100
GS840H36AB-200
GS840H36AB-180
GS840H36AB-166
GS840H36AB-150
GS840H36AB-100
GS840H18AB-200I
GS840H18AB-180I
GS840H18AB-166I
GS840H18AB-150I
GS840H18AB-100I
GS840H32AB-200I
GS840H32AB-180I
GS840H32AB-166I
GS840H32AB-150I
GS840H32AB-100I
GS840H36AB-200I
GS840H36AB-180I
GS840H36AB-166I
GS840H36AB-150I
GS840H36AB-100I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
200/7.5
180/8
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
166/8.5
150/10
100/12
200/7.5
180/8
166/8.5
150/10
100/12
200/7.5
180/8
166/8.5
150/10
100/12
200/7.5
180/8
Not Available
Not Available
Not Available
I
166/8.5
150/10
100/12
200/7.5
180/8
I
I
I
I
I
166/8.5
150/10
100/12
200/7.5
180/8
I
I
I
I
I
166/8.5
150/10
100/12
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AT-7.5T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.08 3/2001
30/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Revision History
Types of Changes
Format or Content
Rev. Code: Old;
Page /Revisions;Reason
New
• Document/Continued changing to new format.
• First Datasheet for this part.
GS840H18/32/36 Rev 1.02c
5/1999;
GS840H18/32/36A 1.00First
Release 8/1999D
Format/Typos
Content
• Took “E” out of 840HE...in Core and Interface Voltages.
• Pin outs/New small caps format.
• Timing Diagrams/New format.
Format/Typos
Content
• Block Diagrams/New small caps format.
GS840H18/32/36A1.00 8/
1999;GS840H18/32/36A1.01
9/1999E
• Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to
DQB3.
• Pin Description/Rearranged Address Inputs to match order on
TQFP Pinout.
• TQFP Package Diagram/Corrected Dimension D Max from
20.1 to 22.1.
• Fixed Ordering information and speed bins.
• Took out Fine Pitch BGA Package. Package change in
progress.
GS840H18/32/36A1.01 9/
1999E;GS840H18/32/
36A1.02
• New GSI Logo
• Took “Pin” out of heading for consistency.
GS840H18/32/36A1.0210-
11/1999;GS840H18/32/
36A1.032/2000G
Format
• Corrected all part order numbers
GS840H18/32/36A1.032/
2000G; 840H18A_r1_04
Content
Content
Content
• Updated pin description table
840H18A_r1_04;
840H18A_r1_05
• Updated BGA pin description table to meet JEDEC standard
840H18A_r1_05;
840H18A_r1_06
• Updated table on page 1
• Updated Operating Currents table on page 18
• Updated AC Electrical Characteristics table on page 19
• Added 150 MHz and 100 MHz
• Updated format to comply with Technical Publications
standards
840H18A_r1_06;
840H18A_r1_07
Content/Format
Content
• Reduced IDD by 20 mA in table on page 1 and Operating
Currents table
840H18A_r1_07;
840E18_r1_08
Rev: 1.08 3/2001
31/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
相关型号：
©2020 ICPDF网 联系我们和版权申明