GS840H18AGB-166IT [GSI]
Cache SRAM, 256KX18, 8.5ns, CMOS, PBGA119, FBGA-119;
| 型号： | GS840H18AGB-166IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Cache SRAM, 256KX18, 8.5ns, CMOS, PBGA119, FBGA-119 静态存储器 内存集成电路 |
| 文件： | 总28页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS840H18/32/36AGT/B-180/166/150/100
TQFP, BGA
Commercial Temp
Industrial Temp
180 MHz–100 MHz
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
3.3 V V
DD
3.3 V and 2.5 V I/O
internally and are controlled by ADV. The burst address
Features
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
• FT pin for user-configurable flow through or pipelined
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
Flow Through/Pipeline Reads
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock control, registered, address, data, and control
• Internal self-timed write cycle
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (pin 14 in the TQFP and
bump 5R in the BGA). Holding the FT mode pin/bump low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipelined mode, activating the rising-edge-triggered
Data Output Register.
• Automatic power-down for portable applications
• JEDEC standard 119-Bump BGA package
• RoHS-compliant 100-lead TQFP and 119-Bump BGA
packages
SCD Pipelined Reads
The GS840H18/32/36A is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Functional Description
Applications
The GS840H18/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS840H18/32/36A is
available in a JEDEC standard 100-lead TQFP or 119-Bump
BGA package.
Byte Write and Global Write
Byte write operation is performed by using byte write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
Core and Interface Voltages
The GS840H18/32/36A operates on a 3.3 V power supply and
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
) pins are used to de-couple output noise
DDQ
from the internal circuit.
Parameter Synopsis
–180
–166
–150
–100
tCycle
tKQ
IDD
5.5 ns
3.0 ns
335 mA
6.0 ns
3.5 ns
310 mA
6.6 ns
3.8 ns
280 mA
10 ns
4.5 ns
190 mA
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tKQ
tCycle
IDD
8 ns
9 ns
210 mA
8.5 ns
10 ns
190 mA
10 ns
12 ns
165 mA
12 ns
15 ns
135 mA
Rev: 1.13 12/2013
1/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
GS840H18A 100-Pin TQFP Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
V
NC
DQPA
DQA
DQA
V
DDQ
DDQ
V
SS
SS
NC
NC
DQB
DQB
256K x 18
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
VDDQ
DQA
DQA
V
NC
VDD
ZZ
DQA
DQA
VDDQ
Top View
V
DDQ
DQB
DQB
FT
SS
V
DD
NC
V
SS
DQB
DQB
V
DDQ
V
V
SS
SS
DQA
DQA
NC
NC
V
VDDQ
NC
NC
DQB
DQB
DQPB
NC
V
SS
SS
V
DDQ
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either V or V . These pins can also be left floating.
DD
SS
Rev: 1.13 12/2013
2/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
GS840H32A 100-Pin TQFP Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
DQB
DQB
V
NC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
DDQ
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
128K x 32
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
FT
V
SS
NC
V
DD
V
NC
DD
ZZ
V
SS
DQA
DQA
V
DQD
DQD
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
NC
DQD
DQD
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either V or V . These pins can also be left floating.
DD
SS
Rev: 1.13 12/2013
3/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
GS840H36A 100-Pin TQFP Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPB
DQB
DQB
DQPC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
V
DDQ
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
128K x 36
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
FT
V
SS
NC
V
DD
V
NC
DD
ZZ
DQA
DQA
V
SS
DQD
DQD
V
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
DQPA
DQD
DQD
DQPD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either V or V . These pins can also be left floating.
DD
SS
Rev: 1.13 12/2013
4/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
TQFP Pin Description
Symbol
A0, A1
A
Type
Description
I
Address field LSBs and Address Counter preset Inputs
I
In
In
In
In
I
Address Inputs
Byte Write signal for data inputs DQA; active low
Byte Write signal for data inputs DQB; active low
Byte Write signal for data inputs DQC; active low
Byte Write signal for data inputs DQD; active low
Byte Write—Writes all enabled bytes; active low
Clock Input Signal; active high
BA
BB
BC
BD
BW
CK
I
GW
I
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
E1, E3
E2
I
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
ADSP, ADSC
DQA
DQB
DQ
I
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
9th Data I/O Pin; Byte A
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
DQD
DQPA
DQPB
DQPC
DQPD
ZZ
9th Data I/O Pin; Byte B
9th Data I/O Pin; Byte C
9th Data I/O Pin; Byte D
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
LBO
I
V
I
DD
V
I
I
-
I/O and Core Ground
Output driver power supply
No Connect
SS
V
DDQ
NC
Rev: 1.13 12/2013
5/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
GS840H18A Pad Out—119-Bump BGA—Top View (Package B)
1
2
A
3
A
A
A
4
5
A
A
A
6
A
7
A
B
C
D
E
F
V
ADSP
ADSC
V
DDQ
DDQ
NC
E2
E3
NC
NC
A
V
A
NC
NC
DD
DQB
NC
NC
DQB
NC
DQB
NC
V
V
V
NC
E1
V
V
V
DQPA
NC
DQA
NC
DQA
SS
SS
SS
SS
SS
SS
DQA
V
G
V
DDQ
DDQ
G
H
J
NC
BB
ADV
GW
NC
DQA
DQB
V
V
NC
SS
SS
V
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
K
L
NC
DQB
NC
DQB
NC
DQPB
A
V
CK
NC
BW
A1
V
NC
DQA
NC
DQA
NC
A
DQA
SS
SS
DQB
NC
BA
NC
V
V
V
V
DDQ
M
N
P
R
T
DDQ
SS
SS
SS
SS
SS
SS
DQB
V
V
V
V
NC
NC
NC
NC
A0
DQA
NC
ZZ
LBO
A
V
FT
A
DD
A
NC
A
V
NC
NC
NC
NC
NC
V
DDQ
U
DDQ
Rev: 1.13 12/2013
6/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
GS840H32A Pad Out—119-Bump BGA—Top View (Package B)
1
2
A
3
A
A
A
4
5
A
A
A
6
7
A
B
C
D
E
F
V
ADSP
ADSC
A
V
DDQ
DDQ
NC
E2
E3
NC
NC
A
V
A
NC
DD
DQC
DQC
NC
DQC
DQC
DQC
DQC
V
V
V
NC
E1
V
V
V
NC
DQB
DQB
DQB
DQB
DQB
DQB
SS
SS
SS
SS
SS
SS
V
G
V
DDQ
DDQ
G
H
J
DQC
BC
ADV
GW
BB
DQB
DQC
V
V
DQB
SS
SS
V
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
K
L
DQD
DQD
DQD
DQD
DQD
NC
V
CK
NC
BW
A1
V
DQA
DQA
DQA
DQA
NC
DQA
SS
SS
DQD
BD
BA
DQA
V
V
V
V
DDQ
M
N
P
R
T
DDQ
SS
SS
SS
SS
SS
SS
DQD
V
V
V
V
DQA
DQD
NC
A0
DQA
NC
ZZ
A
LBO
A
V
FT
A
A
DD
NC
NC
A
NC
V
NC
NC
NC
NC
NC
V
DDQ
U
DDQ
Rev: 1.13 12/2013
7/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
GS840H36A Pad Out—119-Bump BGA—Top View (Package B)
1
2
A
3
A
A
A
4
5
A
A
A
6
A
7
A
B
C
D
E
F
V
ADSP
ADSC
V
DDQ
DDQ
NC
E2
E3
NC
NC
A
V
A
NC
DD
DQC
DQC
DQPC
DQC
DQC
DQC
DQC
V
V
V
NC
E1
V
V
V
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
SS
SS
SS
SS
SS
SS
V
G
V
DDQ
DDQ
G
H
J
DQC2
BC
ADV
GW
BB
DQB2
DQC
V
V
DQB
SS
SS
V
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
K
L
DQD
DQD
DQD
DQD
DQD
DQPD
A
V
CK
NC
BW
A1
V
DQA
DQA
DQA
DQA
DQPA
A
DQA
SS
SS
DQD
BD
BA
DQA
V
V
V
V
DDQ
M
N
P
R
T
DDQ
SS
SS
SS
SS
SS
SS
DQD
V
V
V
V
DQA
DQD
NC
A0
DQA
NC
ZZ
LBO
A
V
FT
A
DD
NC
NC
A
NC
V
NC
NC
NC
NC
NC
V
DDQ
U
DDQ
Rev: 1.13 12/2013
8/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
BGA Pin Description
Symbol
A0, A1
A
Type
Description
I
Address field LSBs and Address Counter Preset Inputs
I
Address Inputs
Byte Write signal for data inputs DQA; active low
Byte Write signal for data inputs DQB; active low
Byte Write signal for data inputs DQC; active low
Byte Write signal for data inputs DQD; active low
Clock Input Signal; active high
BA
In
BB
In
BC
In
BD
In
CK
I
BW
I
Byte Write—Writes all enabled bytes; active low
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
GW
I
E1, E3
E2
I
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
ADSP, ADSC
DQA
DQB
DQ
I
I
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
9th Data I/O Pin; Byte A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
DQD
DQPA
DQPB
DQPC
DQPD
ZZ
9th Data I/O Pin; Byte B
9th Data I/O Pin; Byte C
9th Data I/O Pin; Byte D
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
FT
I
LBO
VDD
I
I
VSS
I
I/O and Core Ground
VDDQ
NC
I
Output driver power supply
-
No Connect
Rev: 1.13 12/2013
9/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
GS840H18/32/36A Block Diagram
Register
A0–An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
36
36
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E3
E2
D
Q
Register
D
Q
FT
G
1
Power Down
Control
DQxn–DQxn
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.13 12/2013
10/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
Write No Bytes
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.13 12/2013
11/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Synchronous Truth Table
State
Diagram
Key
Address
Used
3
Operation
E1
E2
E3
ADSP
ADSC
ADV
W
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
None
None
X
X
L
L
L
L
H
L
L
L
X
H
X
H
X
H
X
H
X
L
H
X
H
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
X
X
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
None
X
X
L
X
X
L
High-Z
None
X
L
High-Z
None
X
X
H
H
H
X
X
X
X
X
X
X
X
X
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
R
H
H
H
X
H
X
H
X
H
X
W
CR
CR
CW
CW
L
H
H
H
H
H
H
H
H
Next
Next
Next
Current
Current
Current
Current
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.13 12/2013
12/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
Rev: 1.13 12/2013
13/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.13 12/2013
14/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
DD
DD
V
Voltage in V
Pins
DDQ
–0.5 to 4.6
V
DDQ
V
–0.5 to V
+0.5 ( 4.6 V max.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
I/O
V
–0.5 to V +0.5 ( 4.6 V max.)
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
Notes
V
3.3 V Supply Voltage
V
V
V
DD
3.3 V V
I/O Supply Voltage
V
3.0
3.3
3.6
DDQ
DDQ
DDQ3
2.5 V V
I/O Supply Voltage
V
2.3
2.5
2.7
DDQ2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Rev: 1.13 12/2013
15/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Logic Levels
Parameter
Symbol
Min.
2.0
Typ.
—
Max.
Unit
V
Notes
1
V
Input High Voltage
Input Low Voltage
V
V
+ 0.3
DD
DD
IH
V
V
–0.3
2.0
—
0.8
V
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
I/O Input High Voltage
I/O Input Low Voltage
V
V
V
+ 0.3
—
V
1,3
1,3
1,3
1,3
DDQ3
IHQ3
DDQ
V
V
V
–0.3
0.6*V
—
0.8
V
DDQ3
ILQ3
V
+ 0.3
—
V
DDQ2
IHQ2
DD
DDQ
V
V
0.3*V
DD
–0.3
—
V
DDQ2
ILQ2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
3.
V
(max) is voltage on V
pins plus 0.3 V.
DDQ
IHQ
Recommended Operating Temperatures
Parameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
C
Notes
T
Ambient Temperature (Commercial Range Versions)
2
2
A
T
Ambient Temperature (Industrial Range Versions)
–40
25
85
C
A
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
50% tKC
V
+ 2.0 V
DD
V
SS
50%
50%
V
DD
V
– 2.0 V
SS
50% tKC
V
IL
Rev: 1.13 12/2013
16/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
pF
I/O
Note:
These parameters are sample tested.
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Input slew rate
V
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
Rev: 1.13 12/2013
17/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
V V
IN
–1 uA
–1 uA
1 uA
100 uA
DD
IH
IH
I
ZZ Input Current
IN1
0 V V V
IN
V
V V
IN
–100 uA
–1 uA
1 uA
1 uA
DD
IL
IL
I
FT, SCD, ZQ Input Current
IN2
0 V V V
IN
I
Output Disable, V
= 0 to V
DD
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
–1 uA
1.7 V
2.4 V
—
1 uA
—
OL
OUT
DDQ
DDQ
V
I
I
= –8 mA, V
= –8 mA, V
= 2.375 V
= 3.135 V
OH2
OH
OH
V
—
OH3
V
I
= 8 mA
OL
0.4 V
OL
Operating Currents
-180
-166
-150
-100
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
Parameter
Test Conditions
Symbol
Unit
70°C
85°C
70°C
85°C
70°C
85°C
70°C
85°C
IDD
Pipeline
Device Selected;
All other inputs
VIH or VIL
Output open
335
345
220
30
310
320
200
30
280
165
20
290
175
30
190
135
20
200
145
30
mA
mA
mA
mA
mA
mA
Operating
Current
IDD
Flow Through
210
20
20
55
40
190
20
ISB
Pipeline
ZZ VDD –
Standby
Current
0.2 V
ISB
Flow Through
30
20
30
20
30
20
30
IDD
Pipeline
65
50
60
50
60
40
50
Device Deselected;
All other inputs
VIH or VIL
Deselect
Current
IDD
Flow Through
50
40
50
35
45
35
45
Rev: 1.13 12/2013
18/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
AC Electrical Characteristics
-180
-166
-150
-100
Parameter
Symbol
Unit
Min
5.5
—
Max
—
Min
6.0
—
Max
—
Min
6.7
—
Max
—
Min
10
Max
—
Clock Cycle Time
tKC
tKQ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock to Output Valid
3.0
—
3.5
—
3.8
—
—
4.5
—
Pipeline
1.5
Clock to Output Invalid
tKQX
1.5
1.5
9.0
—
1.5
1.5
10.0
—
1.5
1.5
15.0
—
1
Clock to Output in Low-Z
Clock Cycle Time
—
—
1.5
12.0
—
—
—
tLZ
tKC
tKQ
—
—
—
—
Clock to Output Valid
8.0
—
8.5
—
10.0
—
12.0
—
Flow
Through
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQX
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
1
—
—
—
—
tLZ
tKH
tKL
—
—
—
—
Clock LOW Time
—
—
—
—
1
Clock to Output in High-Z
G to Output Valid
3.2
3.2
—
3.5
3.5
—
3.8
3.8
—
5
tHZ
tOE
5
1
G to output in Low-Z
0
0
0
0
—
tOLZ
1
G to output in High-Z
Setup time
—
1.5
0.5
5
3.2
—
—
—
—
1.5
0.5
5
3.5
—
—
—
—
1.5
0.5
5
3.8
—
—
—
—
2.0
0.5
5
5
ns
ns
ns
ns
tOHZ
tS
tH
—
—
—
Hold time
2
ZZ setup time
tZZS
2
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
tZZH
tZZR
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.13 12/2013
19/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Pipeline Mode Timing
Begin
Read A Cont
Single Read
Cont
Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont
Deselect
Single Write
tKL
Burst Read
tKH
tKC
CK
ADSP
tS
tS
tH
ADSC initiated read
ADSC
ADV
tS
tH
tH
A
B
C
A0–An
GW
tS
tS
tH
tH
BW
tS
Ba–Bd
E1
tS
tS
tS
Deselected with E1
tH
E1 masks ADSP
tH
tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
G
tS
D(B)
tKQ
tKQX
tHZ
tOE
tOHZ
Q(A)
tH
tLZ
Q(C)
Q(C+1)
Q(C+2) Q(C+3)
DQa–DQd
Rev: 1.13 12/2013
20/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Flow Through Mode Timing
Begin
Read A Cont
tKH
Cont
Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont
Deselect
tKL
tKC
CK
Fixed High
ADSP
tS
tH
tS
tH
ADSC initiated read
ADSC
ADV
A0–An
GW
tS
tH
tS
tH
A
B
C
tS
tH
tS
tH
BW
tS
tH
Ba–Bd
E1
tS
tS
Deselected with E1
tH
tH
E2 and E3 only sampled with ADSC
E2
tS
tH
E3
G
tH
tS
tKQ
tLZ
tHZ
tOE
tOHZ
D(B)
tKQX
Q(A)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
DQa–DQd
Rev: 1.13 12/2013
21/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
Setup
Hold
ADSP
ADSC
tZZR
tZZS
tZZH
ZZ
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.13 12/2013
22/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
TQFP Package Drawing (Package GT)
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
0.10
7
0
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.13 12/2013
23/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
TOP VIEW
BOTTOM VIEW
A1
S
A1
Ø0.10
C
S
S
S
Ø0.30 C A
B
Ø0.60~0.90 (119x)
1
2
3
4
5
6
7
7
6
5
4 3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
M
N
P
K
L
M
N
P
R
T
U
R
T
U
B
1.27
7.62
14±0.10
A
0.20(4x)
SEATING PLANE
C
Rev: 1.13 12/2013
24/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
GS840H18AGT-180
GS840H18AGT-166
GS840H18AGT-150
GS840H18AGT-100
GS840H32AGT-180
GS840H32AGT-166
GS840H32AGT-150
GS840H32AGT-100
GS840H36AGT-180
GS840H36AGT-166
GS840H36AGT-150
GS840H36AGT-100
GS840H18AGT-180I
GS840H18AGT-166I
GS840H18AGT-150I
GS840H18AGT-100I
GS840H32AGT-180I
GS840H32AGT-166I
GS840H32AGT-150I
GS840H32AGT-100I
GS840H36AGT-180I
GS840H36AGT-166I
GS840H36AGT-150I
GS840H36AGT-100I
GS840H18AB-180
GS840H18AB-166
GS840H18AB-150
GS840H18AB-100
GS840H32AB-180
GS840H32AB-166
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
119 BGA (var. 1)
180/8
166/8.5
150/10
100/12
180/8
C
C
C
C
C
C
C
C
C
C
C
C
I
166/8.5
150/10
100/12
180/8
166/8.5
150/10
100/12
180/8
166/8.5
150/10
100/12
180/8
I
C
C
I
166/8.5
150/10
100/12
180/8
I
C
C
I
166/8.5
150/10
100/12
180/8
I
C
C
C
C
C
C
C
C
119 BGA (var. 1)
166/8.5
150/10
100/12
180/8
119 BGA (var. 1)
119 BGA (var. 1)
119 BGA (var. 1)
128K x 32
119 BGA (var. 1)
166/8.5
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840H32AGT-180T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. C = Commercial Temperature Range. I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.13 12/2013
25/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
Ordering Information for GSI Synchronous Burst RAMs (Continued)
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
150/10
100/12
180/8
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
256K x 18
128K x 32
128K x 32
128K x 32
128K x 32
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
GS840H32AB-150
GS840H32AB-100
GS840H36AB-180
GS840H36AB-166
GS840H36AB-150
GS840H36AB-100
GS840H18AB-180I
GS840H18AB-166I
GS840H18AB-150I
GS840H18AB-100I
GS840H32AB-180I
GS840H32AB-166I
GS840H32AB-150I
GS840H32AB-100I
GS840H36AB-180I
GS840H36AB-166I
GS840H36AB-150I
GS840H36AB-100I
GS840H36AGB-180
GS840H36AGB-166
GS840H36AGB-150
GS840H36AGB-100
GS840H36AGB-180I
GS840H36AGB-166I
GS840H36AGB-150I
GS840H36AGB-100I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
119 BGA (var. 1)
119 BGA (var. 1)
C
C
C
C
C
C
I
119 BGA (var. 1)
119 BGA (var. 1)
166/8.5
150/10
100/12
180/8
119 BGA (var. 1)
119 BGA (var. 1)
119 BGA (var. 1)
119 BGA (var. 1)
166/8.5
150/10
100/12
180/8
I
119 BGA (var. 1)
C
C
I
119 BGA (var. 1)
119 BGA (var. 1)
119 BGA (var. 1)
166/8.5
150/10
100/12
180/8
I
119 BGA (var. 1)
C
C
I
119 BGA (var. 1)
119 BGA (var. 1)
119 BGA (var. 1)
166/8.5
150/10
100/12
180/8
I
119 BGA (var. 1)
C
C
C
C
C
C
I
119 BGA (var. 1)
RoHS-compliant 119 BGA (var. 1)
RoHS-compliant 119 BGA (var. 1)
RoHS-compliant 119 BGA (var. 1)
RoHS-compliant 119 BGA (var. 1)
RoHS-compliant 119 BGA (var. 1)
RoHS-compliant 119 BGA (var. 1)
RoHS-compliant 119 BGA (var. 1)
RoHS-compliant 119 BGA (var. 1)
166/8.5
150/10
100/12
180/8
166/8.5
150/10
100/12
I
C
C
128K x 36
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840H32AGT-180T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. C = Commercial Temperature Range. I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.13 12/2013
26/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
4Mb Burst Datasheet Revision History
Types of Changes
Rev. Code: Old;
Page /Revisions;Reason
New
Format or Content
Format/Typos
Content
• Document/Continued changing to new format.
•
GS84018/32/36 Rev 1.02c 5/
1999;
GS84018/32/36 8/1999D
• Took “E” out of 840HE...in Core and Interface Voltages.
• Pin outs/New small caps format.
• Timing Diagrams/New format.
Format/Typos
• Block Diagrams/New small caps format.
GS84018/32/36 8/
1999;GS84018/32/36 9/
1999E
• Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to
DQB3.
• Pin Description/Rearranged Address Inputs to match order on
TQFP Pinout.
Content
• TQFP Package Diagram/Corrected Dimension D Max from
20.1 to 22.1.
•
GS84018/32/36 9/
1999E;GS84018/32/36
• New GSI Logo
• Took “Pin” out of heading for consistency.
GS84018/32/3610-11/
1999;GS84018/32/362/
2000G
Format
• Corrected all part order numbers
GS84018/32/362/2000G;
840H18A_r1_04
Content
Content
Content
• Updated pin description table
840H18A_r1_04;
840H18A_r1_05
• Updated BGA pin description table to meet JEDEC standard
840H18A_r1_05;
840H18A_r1_06
• Updated table on page 1
• Updated Operating Currents table on page 18
• Updated AC Electrical Characteristics table on page 19
• Added 150 MHz and 100 MHz
840H18A_r1_06;
840H18A_r1_07
Content/Format
• Updated format to comply with Technical Publications
standards
• Reduced I by 20 mA in table on page 1 and Operating
840H18A_r1_07;
840E18_r1_08
DD
Content
Content
Currents table
• Removed 200 MHz references from entire datasheet
840H18A_r1_08;
840H18_r1_09
• Updated format
• Matched current numbers to NBT parts
• Removed Preliminary banner
840H18A_r1_09;
840H18A_r1_10
Content
Content
• Added Pb-free TQFP information
• Added variation number to 119 BGA information
840H18A_r1_10;
840H18A_r1_11
Rev: 1.13 12/2013
27/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36AGT/B-180/166/150/100
4Mb Burst Datasheet Revision History
• Added note to TQFP pinouts (pg. 2, 3, 4)
• Updated Power Supply Voltage Ranges table (pg. 16)
• Updated Logic Level tables (pg. 17)
• Changed Pb-free to RoHS-compliant (entire document)
• Added RoHS-compliant 119 BGA (pg. 1, 27, 28, 29, 30)
• Rev1.12a: updated coplanarity for 119 BGA mechanical,
removed status column from Ordering Information table.
840H18A_r1_11;
840H18A_r1_12
Content
• Removed 5/6 RoHS TQFP package references due to EOL
840H18A_r1_12;
840H18A_r1_13
Content
Rev: 1.13 12/2013
28/28
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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