GS8644ZV36GE-150T_技术文档

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GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

250 MHz–133MHz

119-, 165-, & 209-Pin BGA

Commercial Temp

Industrial Temp

72Mb Pipelined and Flow Through

Synchronous NBT SRAM

1.8 V V

DD

1.8 V I/O

Features

Because it is a synchronous device, address, data inputs, and

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

• 1.8 V +10%/–10% core power supply and I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 9Mb, 18Mb, and 36Mb

devices

The GS8644ZV18/36/72 may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-, 165- or 209-bump BGA package

Functional Description

The GS8644ZV18/36/72 is a 72Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS8644ZV18/36/72 is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 119-bump, 165-bump or 209-bump BGA package.

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

t

(x18/x36)

2.3 2.5 2.7 2.9 3.3 3.5 ns

2.6 2.7 2.8 2.9 3.3 3.5 ns

4.0 4.4 5.0 6.0 6.7 7.5 ns

KQ

t

(x72)

KQ

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x36)

Curr (x72)

385 360 335 305 295 265 mA

450 415 385 345 325 295 mA

540 505 460 405 385 345 mA

t

6.5 6.5 6.5 8.0 8.5 8.5 ns

KQ

Flow

tCycle

Through

2-1-1-1

Curr (x18)

Curr (x36)

Curr (x72)

265 265 265 255 240 225 mA

290 290 290 280 265 245 mA

345 345 345 335 315 300 mA

Rev: 1.03 11/2004

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

GS8644ZV72C Pad Out—209-Bump BGA—Top View (Package C)

1

2

3

4

5

6

ADV

W

7

A

8

9

10

11

A

B

C

D

DQG

A

E2

BG

BD

NC

A

E3

BB

BE

NC

A

DQB

A

B

C

D

BC

BH

NC

A

BF

BA

E1

G

NC

V

SS

V

E

F

DQPG

DQC

NC

DQPC

DQC

NC

DQPF

DQF

NC

DQPB

DQF

NC

E

F

DDQ

DD

DDQ

V

SS

ZQ

MCH

MCL

MCH

CKE

FT

SS

V

G

H

J

G

H

J

DDQ

DD

DDQ

V

SS

DDQ

DD

DDQ

V

K

L

CK

NC

K

L

SS

DD

SS

DD

V

DDQ

DQH

DQPD

DQH

DQPH

DQA

DQPA

DQA

DQPE

DDQ

V

SS

M

N

P

R

MCL

MCH

ZZ

M

N

P

R

SS

V

DDQ

DD

DDQ

V

SS

DD

SS

DD

SS

V

DDQ

DD

DDQ

V

SS

T

U

V

DQD

NC

A

NC

A

LBO

A

NC

A

NC

A

DQE

T

U

V

SS

NC

A

NC

A

A1

A0

A

W

TMS

TDI

A

TDO

TCK

W

2

11 x 19 Bump BGA—14 x 22 mm Body—1 mm Bump Pitch

Rev: 1.03 11/2004

2/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

GS8644ZV72 209-Bump BGA Pin Description

Symbol

A0, A1

A

Type

Description

Address field LSBs and Address Counter Preset Inputs.

Address Inputs

I

DQ^A

DQB

DQC

DQD

DQE

DQF

DQG

DQH

I/O

Data Input and Output pins

I

Byte Write Enable for DQA, DQB I/Os; active low

Byte Write Enable for DQC, DQD I/Os; active low

Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

No Connect

B^A, BB

B^C,BD

I

B^E, BF, BG,BH

NC

CK

E¹

—

I

Clock Input Signal; active high

Chip Enable; active low

I

Chip Enable; active low

E³

I

Chip Enable; active high

E²

I

Output Enable; active low

G

I

Burst address counter advance enable

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Must Connect High

ADV

ZZ

I

FT

I

LBO

MCH

MCL

W

I

Must Connect High

Must Connect Low

I

Write Enable; active low

FLXDrive Output Impedance Control

Low = Low Impedance [High Drive],

High = High Impedance [Low Drive]

ZQ

Clock Enable; active low

CKE

Rev: 1.03 11/2004

3/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

GS8644ZV72 209-Bump BGA Pin Description (Continued)

Symbol

TMS

Type

Description

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

I

TDI

O

I

TDO

TCK

V

I

Core power supply

DD

V

I

I/O and Core Ground

SS

V

Output driver power supply

DDQ

Rev: 1.03 11/2004

4/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

GS8644ZV36B Pad Out—119-Bump BGA—Top View (Package B)

1

2

A

3

A

4

A

5

A

6

A

7

V

DDQ

A

B

C

D

E

F

A

B

C

D

E

F

DDQ

NC

E2

ADV

E3

NC

V

A

DD

V

DQC

DQPC

DQC

ZQ

E1

G

DQPB

DQB

SS

V

DDQ

G

H

J

DQC

BC

A

BB

DQB

G

H

J

V

SS

W

SS

V

NC

DDQ

DD

DDQ

V

K

L

DQD

DQPD

A

CK

NC

CKE

A1

DQA

DQPA

A

DQA

K

L

SS

BD

BA

V

M

N

P

R

T

M

N

P

R

T

DDQ

SS

DDQ

V

DQD

NC

DQA

NC

SS

V

A0

SS

V

LBO

A

FT

A

DD

NC

A

TCK

2

A

ZZ

V

U

TMS

TDI

TDO

NC

U

DDQ

7 x 17 Bump BGA—14 x 22 mm Body—1.27 mm Bump Pitch

Rev: 1.03 11/2004

5/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

GS8644ZV18B Pad Out—119-Bump BGA—Top View (Package B)

1

2

A

3

A

4

A

5

A

6

A

7

V

DDQ

A

B

C

D

E

F

A

B

C

D

E

F

DDQ

NC

E2

ADV

E3

NC

V

A

DD

V

DQB

NC

DQB

NC

DQB

NC

ZQ

E1

G

DQPA

NC

DQA

NC

DQA

NC

SS

V

DQA

V

DDQ

G

H

J

NC

BB

A

NC

DQA

NC

G

H

J

V

DQB

W

SS

V

NC

DDQ

DD

DDQ

V

K

L

NC

DQB

NC

CK

NC

CKE

A1

NC

DQA

NC

DQA

NC

A

DQA

NC

K

L

SS

DQB

NC

BA

V

M

N

P

R

T

DQB

NC

M

N

P

R

T

DDQ

SS

DDQ

V

DQB

NC

A

NC

DQA

NC

SS

V

DQPB

A

A0

SS

V

LBO

A

FT

A

DD

A

TCK

2

A

ZZ

V

U

TMS

TDI

TDO

NC

U

DDQ

7 x 17 Bump BGA—14 x 22 mm Body—1.27 mm Bump Pitch

Rev: 1.03 11/2004

6/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

GS8644ZV18/36 119-Bump BGA Pin Description

Symbol

A0, A1

A

Type

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

I

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

B^A, BB, BC, BD

I

—

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

No Connect

NC

CK

CKE

W

Clock Input Signal; active high

Clock Enable; active low

I

Write Enable; active low

E¹

I

Chip Enable; active low

E³

I

Chip Enable; active low

E²

I

Chip Enable; active high

G

I

Output Enable; active low

ADV

ZZ

I

Burst address counter advance enable

Sleep mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

I

FT

I

LBO

I

FLXDrive Output Impedance Control

Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

ZQ

I

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

TMS

TDI

O

I

TDO

TCK

V

I

Core power supply

I/O and Core Ground

DD

V

I

SS

V

I

Output driver power supply

DDQ

BPR1999.05.18

Rev: 1.03 11/2004

7/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

165 Bump BGA—x18 Common I/O—Top View (Package E)

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

NC

A

E1

BB

NC

E3

CKE

ADV

A

B

C

D

E

F

NC

A

NC

E2

NC

BA

CK

W

G

A

NC

ZQ

NC

DQPA

DQA

ZZ

V

DDQ

SS

DD

SS

DD

DDQ

NC

DQB

MCH

NC

V

NC

G

H

J

NC

G

H

J

FT

NC

DQB

DQPB

NC

V

DQA

NC

A

NC

DDQ

K

L

NC

V

NC

K

L

NC

M

N

P

R

NC

M

N

P

R

NC

V

NC

TDI

NC

A1

A0

NC

V

NC

DDQ

SS

DDQ

A

TDO

TCK

A

NC

LBO

A

TMS

A

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

Rev: 1.03 11/2004

8/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

165 Bump BGA—x36 Common I/O—Top View (Package E)

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

NC

A

E1

BC

BB

E3

CKE

ADV

A

NC

A

B

C

D

E

F

NC

DQPC

DQC

FT

A

E2

BD

BA

CK

W

G

A

NC

DQPB

DQB

ZZ

NC

V

NC

DDQ

SS

DD

SS

DD

DDQ

DQC

MCH

DQD

NC

V

DQB

ZQ

G

H

J

G

H

J

NC

DQD

DQPD

NC

V

DQA

NC

DQA

DQPA

NC

DDQ

K

L

V

K

L

M

N

P

R

M

N

P

R

V

NC

TDI

NC

A1

A0

NC

V

SS

DDQ

SS

DDQ

A

TDO

TCK

A

LBO

A

TMS

A

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

Rev: 1.03 11/2004

9/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

GS8644ZV18/36E 165-Bump BGA Pin Description

Symbol

A0, A1

A

Type

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

I

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

B^A, BB, BC, BD

I

—

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

No Connect

NC

CK

CKE

W

Clock Input Signal; active high

Clock Enable; active low

I

Write Enable; active low

E¹

I

Chip Enable; active low

E³

I

Chip Enable; active low

E²

I

Chip Enable; active high

FT

I

Flow Through / Pipeline Mode Control

Output Enable; active low

G

I

ADV

I

Burst address counter advance enable; active high

FLXDrive Output Impedance Control

Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

ZQ

I

ZZ

I

Sleep mode control; active high

Linear Burst Order mode; active low

Scan Test Mode Select

Scan Test Data In

LBO

TMS

TDI

I

O

I

Scan Test Data Out

TDO

TCK

MCH

Scan Test Clock

—

I

Must Connect High

V

Core power supply

DD

V

I

I/O and Core Ground

SS

V

Output driver power supply

DDQ

Rev: 1.03 11/2004

10/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle

read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device

activation is accomplished by asserting all three of the Chip Enable inputs (E¹, E2, and E3). Deassertion of any one of the Enable

inputs will deactivate the device.

Function

Read

W

H

L

BA

X

BB

X

BC

X

BD

X

Write Byte “a”

Write Byte “b”

Write Byte “c”

Write Byte “d”

Write all Bytes

Write Abort/NOP

L

H

L

H

L

H

L

H

L

H

L

H

L

H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three

chip enables (E¹, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control

logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At

the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.

The Byte Write Enable inputs (B^A, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write

cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,

matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At

the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is

required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the

use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after

new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow

Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability

to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late

write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address

and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of

clock.

Rev: 1.03 11/2004

11/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

Synchronous Truth Table

Operation

Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes

Read Cycle, Begin Burst

Read Cycle, Continue Burst

NOP/Read, Begin Burst

R

B

R

B

W

B

D

External

L-H

L

H

L

H

X

H

X

L

X

L

X

L

H

X

H

X

H

X

L

X

L

Q

1,10

2

External

H

X

High-Z

Dummy Read, Continue Burst

Write Cycle, Begin Burst

H

L

X

L

X

L

High-Z 1,2,10

External

D

3

Write Cycle, Continue Burst

Write Abort, Continue Burst

Deselect Cycle, Power Down

H

L

X

L

X

H

X

H

X

1,3,10

X

High-Z 1,2,3,10

High-Z

None

L

High-Z

None

L

High-Z

1

Deselect Cycle

D

None

L-H

L

H

L

H

L

X

L

High-Z

Deselect Cycle, Continue

Sleep Mode

None

L-H

X

L

X

H

X

L

H

L

High-Z

-

1

4

Clock Edge Ignore, Stall

Current

L-H

Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-

lect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W

pin is sampled low but no Byte Write pins are active so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during

write cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write

signals are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Rev: 1.03 11/2004

12/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

Pipelined and Flow Through Read Write Control State Diagram

D

B

Deselect

R

D

W

New Read

New Write

R

W

B

R

W

R

Burst Read

Burst Write

B

D

Key

Notes

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Synchronous Truth Table.

Current State (n)

Next State (n+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Current State

Next State

Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram

Rev: 1.03 11/2004

13/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

Pipeline Mode Data I/O State Diagram

Intermediate

R

W

B

Intermediate

B

R

Data Out

(Q Valid)

High Z

(Data In)

W

D

Intermediate

D

Intermediate

W

R

High Z

B

D

Intermediate

Key

Notes

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Current State (n)

Next State (n+2)

Intermediate State (N+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Intermediate

State

Current State

Next State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.03 11/2004

14/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

Flow Through Mode Data I/O State Diagram

R

W

B

R

Data Out

(Q Valid)

High Z

(Data In)

W

D

W

R

High Z

B

D

Key

Notes

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Current State (n)

Next State (n+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Current State

Next State

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Rev: 1.03 11/2004

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GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from

read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address

generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when

driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write

the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into

Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been

accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst

sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables

below for details.

FLXDrive™

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive

strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Mode Pin Functions

Mode Name

Pin Name

State

Function

Linear Burst

Interleaved Burst

Flow Through

Pipeline

L

Burst Order Control

LBO

H

L

Output Register Control

Power Down Control

FT

ZZ

ZQ

H or NC

L or NC

H

Active

Standby, I = I

DD SB

L

High Drive (Low Impedance)

Low Drive (High Impedance)

FLXDrive Output Impedance Control

H or NC

Note:

There are pull-up devices onthe ZQ and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip

will operate in the default states as specified in the above tables.

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Burst Counter Sequences

Linear Burst Sequence

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

4th address

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of

SB

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKH

tKC

tKL

CK

tZZR

tZZS

tZZH

ZZ

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal. Not

all vendors offer this option, however most mark the pin V or V on pipelined parts and V on flow through parts. GSI NBT

DD

DDQ

SS

SRAMs are fully compatible with these sockets. Other vendors mark the pin as a No Connect (NC). GSI RAMs have an internal

pull-up device on the FT pin so a floating FT pin will result in pipelined operation. If the part being replaced is a pipelined mode

part, the GSI RAM is fully compatible with these sockets. In the unlikely event the part being replaced is a Flow Through device,

the pin will need to be pulled low for correct operation.

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Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

–0.5 to 3.6

DD

V

Voltage in V

Pins

DDQ

–0.5 to 3.6

V

DDQ

V

–0.5 to V

+0.5 (≤ 3.6 V max.)

DDQ

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

V

I/O

V

–0.5 to V +0.5 (≤ 3.6 V max.)

V

IN

DD

I

+/–20

mA

W

IN

I

OUT

P

1.5

D

o

T

–55 to 125

C

STG

o

T

Temperature Under Bias

C

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Power Supply Voltage Ranges

Parameter

Symbol

Min.

1.6

Typ.

1.8

Max.

2.0

Unit

V

Notes

V

1.8 V Supply Voltage

DD1

1.8 V V

I/O Supply Voltage

V

1.6

1.8

2.0

V

DDQ

DDQ1

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

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V

Range Logic Levels

Parameter

DDQ

Symbol

Min.

Typ.

—

Max.

Unit

Notes

V

Input High Voltage

V

0.6*V

V

+ 0.3

DD

V

1

DD

IH

DD

V

Input Low Voltage

V

0.3*V

DD

–0.3

—

1

DD

IL

V

I/O Input High Voltage

I/O Input Low Voltage

V

0.6*V

V

+ 0.3

DDQ

—

1,3

DDQ

IHQ

DD

V

0.3*V

DD

–0.3

—

DDQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.

V

(max) is voltage on V

pins plus 0.3 V.

IHQ

DDQ

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKC

V

+ 2.0 V

50%

DD

V

SS

50%

V

DD

V

– 2.0 V

SS

20% tKC

V

IL

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 2.5 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

8

Max.

10

Unit

pF

C

V

= 0 V

Input Capacitance

IN

C

V

OUT

= 0 V

Input/Output Capacitance

12

14

pF

I/O

Note:

These parameters are sample tested.

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AC Test Conditions

Parameter

Conditions

V

– 0.2 V

Input high level

Input low level

DD

0.2 V

1 V/ns

/2

Input slew rate

V

Input reference level

DD

V

/2

Output reference level

Output load

DDQ

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Output Load 1

DQ

*

50Ω

30pF

V

DDQ/2

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–1 uA

1 uA

IL

V

≥ V ≥ V

IN

–1 uA

1 uA

100 uA

DD

IH

I

ZZ Input Current

IN1

IN2

0 V ≤ V ≤ V

IN

V

≥ V ≥ V

IN

–100 uA

–1 uA

1 uA

DD

IL

FT and ZQ Input Current

0 V ≤ V ≤ V

IN

I

Output Disable, V

= 0 to V

= 1.6 V

Output Leakage Current

Output High Voltage

Output Low Voltage

–1 uA

1 uA

—

OL

OUT

DD

V

I

= –4 mA, V

V

– 0.4 V

DDQ

OH1

OH

DDQ

V

I

= 4 mA, V = 1.6 V

OL DD

—

0.4 V

OL1

Rev: 1.03 11/2004

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AC Electrical Characteristics

-250

-225

-200

-166

-150

-133

Parameter

Symbol

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time

tKC

tKQ

4.0

—

4.4

—

5.0

—

6.0

—

6.7

—

7.5

—

ns

Clock to Output Valid

(x18/x36)

—

2.3

—

2.5

—

2.7

—

2.9

—

3.3

—

3.5

Clock to Output Valid

tKQ

—

2.6

—

2.7

—

2.8

—

2.9

—

3.3

—

3.5

ns

(x72)

Pipeline

Clock to Output Invalid

Clock to Output in Low-Z

Setup time

tKQX

1.0

1.3

0.2

6.5

—

3.0

1.5

0.5

1.3

1.5

—

6.5

—

1.0

1.3

0.3

6.5

—

3.0

1.5

0.5

1.3

1.5

—

6.5

—

1.0

1.4

0.4

6.5

—

3.0

1.5

0.5

1.3

1.5

—

6.5

—

1.0

1.5

0.5

7.0

—

3.0

1.5

0.5

1.3

1.5

—

7.0

—

1.0

1.5

0.5

7.5

—

3.0

1.5

0.5

1.5

1.7

—

7.5

—

1.0

1.5

0.5

8.5

—

3.0

1.5

0.5

1.7

2

—

8.5

—

ns

1

tLZ

tS

tH

Hold time

Clock Cycle Time

Clock to Output Valid

tKC

tKQ

tKQX

Clock to Output Invalid

Clock to Output in Low-Z

Setup time

Flow

Through

1

tLZ

tS

tH

Hold time

Clock HIGH Time

Clock LOW Time

tKH

tKL

Clock to Output in

High-Z

1

1.0

2.3

1.0

2.5

1.0

2.7

1.0

2.9 1.0 3.0 1.0 3.0

ns

tHZ

(x18/x36)

Clock to Output in

High-Z

1

1.0

2.6

2.3

1.0

2.7

2.5

1.0

2.8

2.7

1.0

2.9 1.0 3.0 1.0 3.0

ns

tHZ

(x72)

G to Output Valid

(x18/x36)

tOE

—

2.9

—

3.3

—

3.5

G to Output Valid

(x72)

—

0

2.6

—

2.3

—

0

2.7

—

2.5

—

0

2.8

—

2.7

—

0

2.9

—

2.9

—

0

3.3

—

3.0

—

0

3.5

—

3.0

ns

1

G to output in Low-Z

tOLZ

G to output in High-Z

(x18/x36)

1

—

tOHZ

G to output in High-Z

(x72)

1

—

2.6

—

2.7

—

2.8

—

2.9

—

3.0

—

3.0

ns

tOHZ

2

ZZ setup time

ZZ hold time

ZZ recovery

5

1

—

5

1

—

5

1

—

5

1

—

5

1

—

5

1

—

ns

tZZS

2

tZZH

tZZR

20

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

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Pipeline Mode Timing (NBT)

Write A

Read B

Suspend

tKH

Read C

tKC

Write D

writeno-op

Read E

Deselect

tKL

CK

A

tH

tS

A

B

C

D

E

tS

CKE

E*

ADV

W

tH

tS

Bn

tH

tLZ

tKQ

tHZ

tS

D(A)

tKQX

Q(B)

Q(C)

D(D)

Q(E)

DQ

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GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

Flow Through Mode Timing (NBT)

Write A

Write B

Write B+1 Read C

tKL

Cont

Read D

Write E

Read F

Write G

tKH

tKC

CK

CKE

E

tH

tS

ADV

W

Bn

A0–An

A

B

C

D

E

F

G

tKQ

tLZ

tH

tKQ

tLZ

D(B+1)

tKQX

tS

D(A)

tHZ

Q(D)

tKQX

D(G)

DQ

G

D(B)

Q(C)

D(E)

Q(F)

tOLZ

tOE

tOHZ

*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DDQ

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Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

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JTAG TAP Block Diagram (2-die module)

·

Boundary Scan Register

·

0

Bypass Register

2

1 0

2

1 0

Instruction Register

TDO

TDI

TDO

ID Code Register

31 30 29

2 1

0

·

· · ·

31 30 29

2 1

0

·

· · ·

Control Signals

Test Access Port (TAP) Controller

Control Signals

Test Access Port (TAP) Controller

TMS

·

TCK

·

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

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JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

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EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is

still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

Rev: 1.03 11/2004

28/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

JTAG Port AC Test Conditions

Parameter

Conditions

JTAG Port AC Test Load

V

– 0.2 V

Input high level

Input low level

DQ

DD

0.2 V

1 V/ns

*

50Ω

30pF

Input slew rate

V

/2

Input reference level

DDQ

V

/2

DDQ

/2

Output reference level

DDQ

* Distributed Test Jig Capacitance

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

JTAG TAP Instruction Set Summary

Instruction

EXTEST

Code

000

Description

Notes

1

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

IDCODE

001

1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

010

011

TDO.

1

Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

100

101

110

111

1

GSI

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Rev: 1.03 11/2004

29/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

V

0.6 * V

V

+0.3

DD

1.8 V Test Port Input High Voltage

1.8 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

V

1

IHJ

DD

V

0.3 * V

1

–0.3

–300

–1

ILJ

DD

I

uA

V

2

INHJ

I

100

1

3

INLJ

I

–1

4

OLJ

V

1.7

—

5, 6

5, 7

5, 8

5, 9

OHJ

V

—

0.4

—

V

OLJ

V

– 100 mV

DDQ

Test Port Output CMOS High

V

OHJC

V

Test Port Output CMOS Low

—

100 mV

V

OLJC

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V

+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.

V

≤ V ≤ V

ILJ

IN

DDn

3. 0 V ≤ V ≤ V

IN

ILJn

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V

supply.

DDQ

6.

7.

8.

9.

I

= –4 mA

OHJ

= + 4 mA

OLJ

= –100 uA

= +100 uA

OHJC

JTAG Port Timing Diagram

tTKC

tTKH

tTKL

TCK

tTH

tTS

TDI

TMS

TDO

tTKQ

tTH

tTS

Parallel SRAM input

Rev: 1.03 11/2004

30/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

JTAG Port AC Electrical Characteristics

Parameter

TCK Cycle Time

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

50

—

Max

Unit

ns

—

20

—

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

20

10

ns

tTH

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications

Engineering Department at: apps@gsitechnology.com.

Rev: 1.03 11/2004

31/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

209 BGA Package Drawing (Package C)

14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array

C A1

A

Side View

D

aaa

D1

e

Bottom View

∅b

e

Symbol

Min

—

Typ

—

Max

1.70

0.60

0.70

0.38

22.1

Units

mm

Symbol

Min

—

Typ

18.0 (BSC)

14.0

Max

—

Units

mm

A

A1

∅b

c

D1

E

0.40

0.50

0.31

21.9

0.50

0.60

0.36

22.0

13.9

—

14.1

—

E1

e

10.0 (BSC)

1.00 (BSC)

0.15

—

D

aaa

—

Rev 1.0

Rev: 1.03 11/2004

32/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

Package Dimensions—165-Bump FPBGA (Package E; Variation 1)

A1

1

TOP VIEW

3 4 5 6 7 8 9 10 11

BOTTOM VIEW

M

A1

Ø0.10

C

M

Ø0.25 C AB

Ø0.44~0.64(165x)

2

11 10 9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

I

A

B

C

D

E

F

G

H

J

K

L

M

N

P

K

L

M

N

P

R

A

1.0

10.0

1.0

15±0.05

B

0.20(4x)

SEATING PLANE

C

Rev: 1.03 11/2004

33/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

Package Dimensions—119-Bump FPBGA (Package B, Variation 2)

TOP VIEW

BOTTOM VIEW

A1

S

Ø0.10

C

S

Ø0.30 C A

B

Ø0.60~0.90 (119x)

1

2

3

4

5

6

7

6

5

4 3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

B

1.27

7.62

14±0.10

A

0.20(4x)

SEATING PLANE

C

Rev: 1.03 11/2004

34/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

Ordering Information for GSI Synchronous Burst RAMs

2

Speed

3

1

Org

Type

Package

T

Part Number

A

(MHz/ns)

250/6.5

225/6.5

200/6.5

166/8

4M x 18

2M x 36

1M x 72

GS8644ZV18B-250

GS8644ZV18B-225

GS8644ZV18B-200

GS8644ZV18B-166

GS8644ZV18B-150

GS8644ZV18B-133

GS8644ZV18E-250

GS8644ZV18E-225

GS8644ZV18E-200

GS8644ZV18E-166

GS8644ZV18E-150

GS8644ZV18E-133

GS8644ZV36B-250

GS8644ZV36B-225

GS8644ZV36B-200

GS8644ZV36B-166

GS8644ZV36B-150

GS8644ZV36B-133

GS8644ZV36E-250

GS8644ZV36E-225

GS8644ZV36E-200

GS8644ZV36E-166

GS8644ZV36E-150

GS8644ZV36E-133

GS8644ZV72C-250

GS8644ZV72C-225

GS8644ZV72C-200

GS8644ZV72C-166

GS8644ZV72C-150

GS8644ZV72C-133

NBT Pipeline/Flow Through

119 BGA (var. 2)

165 BGA (var. 1)

119 BGA (var. 2)

165 BGA (var. 1)

209 BGA

C

150/8.5

133/8.5

250/6.5

225/6.5

200/6.5

166/8

150/8.5

133/8.5

250/6.5

225/6.5

200/6.5

166/8

150/8.5

133/8.5

250/6.5

225/6.5

200/6.5

166/8

150/8.5

133/8.5

250/6.5

225/6.5

200/6.5

166/8

209 BGA

150/8.5

133/8.5

209 BGA

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8644ZV18B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.03 11/2004

35/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

Ordering Information for GSI Synchronous Burst RAMs (Continued)

2

Speed

3

1

Org

Type

Package

T

Part Number

A

(MHz/ns)

250/6.5

225/6.5

200/6.5

166/8

4M x 18

2M x 36

1M x 72

GS8644ZV18B-250I

GS8644ZV18B-225I

GS8644ZV18B-200I

GS8644ZV18B-166I

GS8644ZV18B-150I

GS8644ZV18B-133I

GS8644ZV18E-250I

GS8644ZV18E-225I

GS8644ZV18E-200I

GS8644ZV18E-166I

GS8644ZV18E-150I

GS8644ZV18E-133I

GS8644ZV36B-250I

GS8644ZV36B-225I

GS8644ZV36B-200I

GS8644ZV36B-166I

GS8644ZV36B-150I

GS8644ZV36B-133I

GS8644ZV36E-250I

GS8644ZV36E-225I

GS8644ZV36E-200I

GS8644ZV36E-166I

GS8644ZV36E-150I

GS8644ZV36E-133I

GS8644ZV72C-250I

GS8644ZV72C-225I

GS8644ZV72C-200I

GS8644ZV72C-166I

GS8644ZV72C-150I

GS8644ZV72C-133I

NBT Pipeline/Flow Through

119 BGA (var. 2)

165 BGA (var. 1)

119 BGA (var. 2)

165 BGA (var. 1)

209 BGA

I

150/8.5

133/8.5

250/6.5

225/6.5

200/6.5

166/8

150/8.5

133/8.5

250/6.5

225/6.5

200/6.5

166/8

150/8.5

133/8.5

250/6.5

225/6.5

200/6.5

166/8

150/8.5

133/8.5

250/6.5

225/6.5

200/6.5

166/8

209 BGA

150/8.5

133/8.5

209 BGA

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8644ZV18B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.03 11/2004

36/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

72Mb Sync SRAM Datasheet Revision History

Types of Changes

Format or Content

DS/DateRev. Code: Old;

Page;Revisions;Reason

New

• Creation of new datasheet

8644ZVxx_r1

• Updated Operating Currents table

8644ZVxx_r1;

Content

• Updated FT AC Characteristics for tKQ

8644ZVxx_r1_01

• Updated FT tKQ and PL tS/tH and FT current numbers for 250

and 225 MHz (match 200 MHz)

8644ZVxx_r1_01;

8644ZVxx_r1_02

• Updated basic format

• Updated Synchronous Truth Table

• Added thermal characteristics to mechanical drawings

• Updated JTAG section for module

• Updated format

8644ZVxx_r1_02;

8644ZVxx_r1_03

Format/Content

• Added variation information to package mechanicals

Rev: 1.03 11/2004

37/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS8644ZV36GE-150T
厂家：	GSI TECHNOLOGY
描述：	ZBT SRAM, 2MX36, 7.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165 静态存储器内存集成电路
文件：	总37页 (文件大小：1133K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS8644ZV36GE-150T [GSI]

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