GS8662R36GE-333I [GSI]
72Mb SigmaCIO DDR-II Burst of 4 SRAM; 72MB SigmaCIO DDR- II突发的4 SRAM
| 型号： | GS8662R36GE-333I |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| 文件： | 总37页 (文件大小：1816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
333 MHz–167 MHz
165-Bump BGA
Commercial Temp
Industrial Temp
72Mb SigmaCIO DDR-II
Burst of 4 SRAM
1.8 V V
DD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaCIO™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, 36Mb and future
144Mb devices
Bottom View
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
SigmaCIO™ Family Overview
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
The GS8662R08/09/18/36E are built in compliance with the
SigmaCIO DDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662R08/09/18/36E SigmaCIO SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs
always transfer data in four packets. When a new address is
loaded, A0 and A1 preset an internal 2 bit linear address
counter. The counter increments by 1 for each beat of a burst of
four data transfer. The counter always wraps to 00 after
reaching 11, no matter where it starts.
Clocking and Addressing Schemes
The GS8662R08/09/18/36E SigmaCIO DDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer
data in four packets. When a new address is loaded, the LSBs
are internally set to 0 for the first read or write transfer, and
incremented by 1 for the next 3 transfers. Because the LSBs
are tied off internally, the address field of a x8 SigmaCIO
DDR-II B4 RAM is always two address pins less than the
advertised index depth (e.g., the 4M x 18 has a 1024K
addressable index).
Parameter Synopsis
-333
-300
3.3 ns
-250
4.0 ns
-200
-167
tKHKH
tKHQV
3.0 ns
5.0 ns
6.0 ns
0.5 ns
0.45 ns 0.45 ns 0.45 ns 0.45 ns
Rev: 1.01 9/2005
1/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
2M x 36 SigmaCIO DDR-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
MCL/SA
(144Mb)
A
CQ
SA
R/W
BW2
K
BW1
LD
SA
SA
CQ
B
C
D
E
F
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
DQ27
NC
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
SA
BW3
SA
K
BW0
SA1
SA
NC
NC
NC
NC
NC
NC
NC
DQ17
NC
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
V
V
SA0
V
SS
SS
SS
SS
DQ29
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
DQ15
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DQ30
DQ31
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
NC
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
NC
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
V
NC
NC
NC
NC
NC
SA
DQ33
NC
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
DQ11
NC
SS
SS
SS
SS
DQ35
NC
V
SA
SA
SA
SA
C
SA
SA
SA
V
SA
SA
SA
SA
DQ9
TMS
TCK
C
2
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35
2. MCL = Must Connect Low
Rev: 1.01 9/2005
2/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
4M x 18 SigmaCIO DDR-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ
SA
SA
R/W
BW1
K
NC
LD
SA
SA
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
DQ9
NC
NC
NC
SA
NC
SA
K
BW0
SA1
SA
NC
NC
NC
NC
NC
NC
NC
DQ7
NC
DQ8
NC
V
V
SA0
V
SS
SS
SS
SS
NC
DQ10
DQ11
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
NC
V
V
V
V
V
V
V
V
NC
DQ6
DQ5
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DQ12
NC
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
DQ13
V
V
V
NC
V
V
V
V
REF
ZQ
REF
DDQ
DDQ
NC
NC
NC
DQ14
NC
NC
DQ4
NC
NC
K
L
V
NC
NC
NC
NC
NC
SA
DQ3
DQ2
NC
DQ15
NC
V
V
V
V
V
NC
DDQ
SS
SS
SS
SS
M
N
P
R
NC
V
V
DQ1
NC
SS
SS
SS
SS
NC
DQ16
DQ17
SA
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
NC
SA
SA
SA
SA
NC
DQ0
TDI
TCK
C
TMS
2
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17
2. MCL = Must Connect Low
Rev: 1.01 9/2005
3/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
8M x 9 SigmaCIO DDR-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ
SA
SA
R/W
NC
K
NC
LD
SA
SA
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
NC
NC
NC
NC
SA
NC
SA
K
BW
SA
SA
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ4
NC
V
V
NC
V
SS
SS
SS
SS
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DQ5
NC
V
V
V
V
V
V
V
V
DQ3
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
DQ6
V
V
V
NC
V
V
V
V
ZQ
REF
DDQ
DDQ
REF
NC
NC
NC
NC
NC
NC
DQ8
SA
NC
DQ2
NC
K
L
NC
DQ7
NC
V
NC
NC
NC
NC
NC
SA
NC
NC
NC
V
V
V
V
V
DQ1
NC
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
NC
SS
SS
SS
SS
NC
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
NC
NC
SA
SA
SA
SA
NC
DQ0
TDI
TCK
C
TMS
2
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to
0 at the beginning of each access.
2. MCL = Must Connect Low
Rev: 1.01 9/2005
4/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
8M x 8 SigmaCIO DDR-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ
SA
SA
R/W
NW1
K
NC
LD
SA
SA
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
NC
NC
NC
NC
SA
NC
SA
K
NW0
SA
SA
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ3
NC
NC
DQ2
NC
NC
ZQ
V
V
NC
V
SS
SS
SS
SS
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DQ4
NC
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
DQ5
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
NC
NC
NC
NC
DQ7
SA
NC
DQ1
NC
NC
DQ0
NC
NC
NC
TDI
K
L
NC
DQ6
NC
V
NC
NC
NC
NC
NC
SA
NC
NC
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
NC
SS
SS
SS
SS
NC
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
NC
SA
SA
SA
SA
NC
TCK
C
TMS
2
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to
0 at the beginning of each access.
2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7
3. MCL = Must Connect Low
Rev: 1.01 9/2005
5/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Pin Description Table
Symbol
Description
Synchronous Address Inputs
No Connect
Type
Input
—
Comments
—
SA
NC
R
—
Synchronous Read
Synchronous Write
Input
Input
Active High
Active Low
W
Active Low
x18/x36 only
BW0–BW3
NW0–NW1
Synchronous Byte Writes
Nybble Write Control Pin
Input
Input
Active Low
x8 only
LD
K
Synchronous Load Pin
Input Clock
Input
Input
Active Low
Active High
K
Input Clock
Input
Active Low
C
Output Clock
Input
Active High
C
Output Clock
Input
Active Low
TMS
TDI
TCK
TDO
Test Mode Select
Test Data Input
Input
—
Input
—
Test Clock Input
Input
—
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Must Connect Low
Data I/O
Output
Input
—
V
—
REF
ZQ
MCL
DQ
Input
—
—
—
Input/Output
Input
Three State
Active Low
—
Doff
CQ
Disable DLL when low
Output Echo Clock
Output Echo Clock
Power Supply
Output
Output
Supply
CQ
—
V
1.8 V Nominal
DD
V
Isolated Output Buffer Supply
Power Supply: Ground
Supply
Supply
1.5 V Nominal
—
DDQ
V
SS
Note:
NC = Not Connected to die or any other pin
Rev: 1.01 9/2005
6/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs
are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated
in the timing diagrams. It is not possible to stop a burst once it starts. Four beats of data are always transferred. This means that it is
possible to load new addresses every other K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are
inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the four beat read data transfer
and then execute the deselect command, returning the output drivers to high-Z.A high on the LD# pin prevents the RAM from
loading read or write command
inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations.
SigmaCIO DDR-II B4 SRAM Read Cycles
The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst
transfer in
response to a read command, if the previous command captured was a read or write command, the Address, LD# and R/W# pins
are ignored. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes pipelined
reads. The read command is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces
data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The second beat of data
is transferred on the next rising edge of C, then on the next rising edge of C# and finally on the next rising edge of C, for a total of
four transfers per address load.
SigmaCIO DDR-II B4 SRAM Write Cycles
The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst
transfer in response to a write command, if the previous command captured was a read or write command, the Address, LD# and R/
W# pins are ignored at the next rising edge of K. If the previous command captured was a deselect, the control pin status is
checked.The SRAM executes “late write” data transfers. Data in is due at the device inputs on the rising edge of K following the
rising edge of K clock used to clock in the write command and the write address. To complete the remaining three beats of the burst
of four write transfer the SRAM captures data in on the next rising edge of K#, the following rising edge of K and finally on the
next rising edge of K#, for a total of four transfers per address load.
Rev: 1.01 9/2005
7/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
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Power-Up Sequence for SigmaQuad-II SRAMs
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
Power-Up Sequence
1. Power-up and maintain Doff at low state.
1a. Apply VDD
.
1b. Apply VDDQ
.
1c. Apply VREF (may also be applied at the same time as VDDQ).
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note:
If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become
stablized.
DLL Constraints
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar on page 20).
• The DLL cannot operate at a frequency lower than 119 MHz.
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during
the initial stage.
Power-Up Sequence (Doff controlled)
Power UP Interval
Unstable Clocking Interval
DLL Locking Interval (1024 Cycles)
Normal Operation
K
K
V
DD
V
DDQ
V
REF
Doff
Power-Up Sequence (Doff tied High)
Power UP Interval
Unstable Clocking Interval
Stop Clock Interval
30ns Min
DLL Locking Interval (1024 Cycles)
Normal Operation
K
K
V
DD
V
DDQ
V
REF
Doff
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
Rev: 1.01 9/2005
8/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device,
“Nybble Write Enable” and “NBx” may be substituted in all the discussion above.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample
BW0
BW1
D0–D8
D9–D17
Time
Beat 1
Beat 2
Beat 3
Beat 4
0
1
0
1
1
0
0
0
Data In
Don’t Care
Data In
Don’t Care
Data In
Data In
Don’t Care
Data In
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Written
Unchanged
Unchanged
Written
Written
Written
Unchanged
Written
Beat 1
Beat 2
Beat 3
Beat 4
Output Register Control
SigmaCIO DDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the
Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing
of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of
the K and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the
RAM to function as a conventional pipelined read SRAM.
Rev: 1.01 9/2005
9/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
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Example Four Bank Depth Expansion Schematic
LD
LD
3
2
LD
LD
1
0
R/W
A –A
0
n
K
Bank 3
Bank 1
Bank 2
Bank 0
A
A
A
A
LD
LD
LD
LD
R/W
R/W
R/W
R/W
CQ
K
CQ
K
CQ
K
CQ
DQ
K
DQ
C
DQ
C
DQ
C
C
C
DQ –
1
CQ
Note:
For simplicity BWn (or NWn), K, and C are not shown.
Rev: 1.01 9/2005
10/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaCIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected
to V via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
SS
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is
producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.
Common I/O SigmaCIO DDR-II B4 SRAM Truth Table
DQ
K
LD
R/W
Operation
n
A + 0
A + 1
A + 2
A + 3
↑
1
0
X
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Deselect
Write
↑
D@K
D@K
D@K
D@K
n+1
n+1
n+1
n+2
n+2
n+2
n+2
n+3
Q@K
or
Q@K
or
Q@K
or
Q@K
or
↑
0
1
Read
C
C
C
C
n+1
n+2
n+2
n+3
Note:
Q is controlled by K clocks if C clocks are not used.
Rev: 1.01 9/2005
11/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
B4 Byte Write Clock Truth Table
BW
BW
BW
BW
Current Operation
D
D
D
D
K ↑
K ↑
n+1
K ↑
n+2
K ↑
n+2½
K ↑
n+1
K ↑
n+1½
K ↑
n+2
K ↑
n+2½
K ↑
(tn+1½
(t
)
)
(t
)
(t
)
(t
)
(t
)
(t
)
(t
)
(t )
n
Write
T
T
F
T
F
F
F
T
T
D0
D2
D3
D4
Dx stored if BWn = 0 in all four data transfers
Write
T
F
F
F
F
F
T
F
F
F
F
F
T
F
D0
X
X
D1
X
X
X
X
X
Dx stored if BWn = 0 in 1st data transfer only
Write
Dx stored if BWn = 0 in 2nd data transfer only
Write
X
D2
X
X
Dx stored if BWn = 0 in 3rd data transfer only
Write
X
X
D3
X
Dx stored if BWn = 0 in 4th data transfer only
Write Abort
F
X
X
X
No Dx stored in any of the four data transfers
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.
Rev: 1.01 9/2005
12/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
B4 Nybble Write Clock Truth Table
NW
NW
NW
NW
Current Operation
D
D
D
D
K ↑
K ↑
n+1
K ↑
n+1½
K ↑
n+2
K ↑
n+2½
K ↑
n+1
K ↑
n+1½
K ↑
n+2
K ↑
n+2½
(t
)
(t
)
(t
)
(t
)
(t
)
(t
)
(t
)
(t
)
(t )
n
Write
T
T
T
T
D0
D2
D3
D4
Dx stored if NWn = 0 in all four data transfers
Write
T
F
F
F
F
T
F
F
F
F
F
T
F
F
F
F
F
T
F
D0
X
X
D1
X
X
X
X
X
Dx stored if NWn = 0 in 1st data transfer only
Write
Dx stored if NWn = 0 in 2nd data transfer only
Write
X
D2
X
X
Dx stored if NWn = 0 in 3rd data transfer only
Write
X
X
D3
X
Dx stored if NWn = 0 in 4th data transfer only
Write Abort
F
X
X
X
No Dx stored in any of the four data transfers
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
Rev: 1.01 9/2005
13/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
x36 Byte Write Enable (BWn) Truth Table
BW0 BW1 BW2 BW3
D0–D8
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Don’t Care
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Data In
Data In
x18 Byte Write Enable (BWn) Truth Table
BW0 BW1
D0–D8
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
1
0
1
0
1
1
0
0
Don’t Care
Data In
Data In
x8 Nybble Write Enable (NWn) Truth Table
NW0 NW1
D0–D3
Don’t Care
Data In
D4–D7
Don’t Care
Don’t Care
Data In
1
0
1
0
1
1
0
0
Don’t Care
Data In
Data In
Rev: 1.01 9/2005
14/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
B4 State Diagram
Power-Up
LOAD
NOP
LOAD
LOAD
LOAD
Load New
Address
LOAD
READ
WRITE
LOAD
DDR Read
DDR Write
READ
WRITE
Always
Always
Increment
Read Address
Increment
Write Address
Notes:
1. The internal burst address counter is a 4-bit linear counter (i.e., when first address is A0, next internal burst address is A0+1).
2. “READ” refers to read active status with R/W = High, “WRITE” refers to write inactive status with R/W = Low.
3. “LOAD” refers to read new address active status with LD = Low, “LOAD” refers to read new address inactive status with LD = High.
Rev: 1.01 9/2005
15/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
Voltage on V Pins
DD
–0.5 to 2.9
V
DD
V
Voltage in V
Voltage in V
Pins
Pins
–0.5 to V
V
V
DDQ
DDQ
REF
DD
V
–0.5 to V
REF
DDQ
V
–0.5 to V
–0.5 to V
+0.5 (≤ 2.9 V max.)
Voltage on I/O Pins
V
I/O
DDQ
DDQ
V
+0.5 (≤ 2.9 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
V
IN
I
+/–100
+/–100
125
mA dc
mA dc
IN
I
Output Current on Any I/O Pin
Maximum Junction Temperature
Storage Temperature
OUT
o
T
C
J
o
T
–55 to 125
C
STG
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Supply Voltage
Symbol
Min.
1.7
Typ.
1.8
Max.
1.9
Unit
V
V
V
V
DD
V
I/O Supply Voltage
Reference Voltage
1.7
1.8
1.9
DDQ
V
0.68
—
0.95
REF
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ V
≤ 1.6 V (i.e., 1.5 V I/O)
DDQ
and 1.7 V ≤ V
≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.
DDQ
2. The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal inputs. The
DD DDQ REF
power down sequence must be the reverse. V
must not exceed V ..
DDQ
DD
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Ambient Temperature
(Commercial Range Versions)
T
0
25
70
°C
A
Ambient Temperature
(Industrial Range Versions)
T
–40
25
85
°C
A
Rev: 1.01 9/2005
16/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
HSTL I/O DC Input Characteristics
Parameter
DC Input Logic High
Symbol
Min
Max
Units
Notes
V
(dc)
V
+ 0.10
V
V
+ 0.3 V
DD
V
V
1
1
IH
REF
V (dc)
– 0.10
DC Input Logic Low
–0.3 V
IL
REF
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers
2. These are DC test criteria. DC design criteria is V
± 50 mV. The AC V /V levels are defined separately for measuring timing parame-
REF
IH IL
ters.
3. V (Min) DC = –0.3 V, V (Min) AC = –1.5 V (pulse width ≤ 3 ns).
IL
IL
4.
V
(Max) DC = V
+ 0.3 V, V (Max) AC = V
+ 0.85 V (pulse width ≤ 3 ns).
DDQ
IH
DDQ
IH
HSTL I/O AC Input Characteristics
Parameter
AC Input Logic High
Symbol
Min
Max
Units
Notes
3,4
V
(ac)
V
+ 0.20
REF
—
V
V
V
IH
V (ac)
V
– 0.20
REF
AC Input Logic Low
—
3,4
IL
V
Peak to Peak AC Voltage
V
(ac)
5% V
(DC)
REF
—
1
REF
REF
Notes:
1. The peak to peak AC component superimposed on V
may not exceed 5% of the DC component of V
.
REF
REF
2. To guarantee AC characteristics, V ,V , Trise, and Tfall of inputs and clocks must be within 10% of each other.
IH IL
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKHKH
V
+ 1.0 V
DD
V
SS
50%
50%
V
DD
V
– 1.0 V
SS
20% tKHKH
V
IL
Rev: 1.01 9/2005
17/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 3.3 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
Output Capacitance
Clock Capacitance
4
6
5
5
7
6
IN
IN
C
V
OUT
= 0 V
pF
OUT
C
—
pF
CLK
Note:
This parameter is sample tested.
AC Test Conditions
Parameter
Conditions
V
Input high level
Input low level
DDQ
0 V
Max. input slew rate
Input reference level
2 V/ns
V
V
/2
/2
DDQ
DDQ
Output reference level
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
DQ
RQ = 250 Ω (HSTL I/O)
V
= 0.75 V
REF
50Ω
VT = V /2
DDQ
Input and Output Leakage Characteristics
Parameter
Symbol
Test Conditions
Min.
Max
Notes
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–2 uA
2 uA
IL
V
≥ V ≥ V
IN
–100 uA
–2 uA
2 uA
2 uA
DD
IL
IL
I
Doff
INDOFF
0 V ≤ V ≤ V
IN
Output Disable,
= 0 to V
I
Output Leakage Current
–2 uA
2 uA
OL
V
OUT
DDQ
Rev: 1.01 9/2005
18/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
Min.
Max.
Units Notes
V
V
/2
V
Output High Voltage
Output Low Voltage
Output High Voltage
V
V
V
V
1, 3
2, 3
4, 5
4, 6
OH1
DDQ
DDQ
V
V
/2
DDQ
Vss
OL1
V
V
– 0.2
V
DDQ
OH2
DDQ
V
Output Low Voltage
Vss
0.2
OL2
Notes:
1.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).
DDQ OH DDQ
OH
2.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).
OL
DDQ
OL
DDQ
3. Parameter tested with RQ = 250Ω and V
= 1.5 V or 1.8 V
DDQ
4. Minimum Impedance mode, ZQ = V
SS
5.
6.
I
I
= –1.0 mA
= 1.0 mA
OH
OL
Operating Currents
-333
-300
-250
-200
-167
Parameter
Symbol
Test Conditions
Notes
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
VDD = Max, IOUT = 0 mA
Operating Current (x36):
DDR
IDD
IDD
IDD
IDD
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2, 3
2, 3
2, 3
2, 3
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
Operating Current (x18):
DDR
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
Operating Current (x9):
DDR
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
Operating Current (x8):
DDR
Cycle Time ≥ tKHKH Min
Device deselected,
IOUT = 0 mA, f = Max,
Standby Current (NOP):
DDR
ISB1
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2, 4
All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V
Notes:
1.
2.
Power measured with output pins floating.
Minimum cycle, IOUT = 0 mA
Operating current is calculated with 50% read cycles and 50% write cycles.
Standby Current is only after all pending read and write burst operations are completed.
3.
4.
Rev: 1.01 9/2005
19/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
AC Electrical Characteristics
-333
-300
-250
-200
-167
Parameter
Symbol
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock
tKHKH
tCHCH
K, K Clock Cycle Time
C, C Clock Cycle Time
3.0
—
3.5
0.2
—
3.3
—
4.2
0.2
—
4.0
—
6.3
0.2
—
5.0
—
7.88
0.2
—
6.0
—
8.4
0.2
—
ns
ns
ns
tKCVar
tTKC Variable
5
tKHKL
tCHCL
K, K Clock High Pulse Width
C, C Clock High Pulse Width
1.2
1.32
1.6
2.0
2.4
tKLKH
tCLCH
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
1.2
—
—
1.32
—
—
1.6
—
—
2.0
—
—
2.4
—
—
ns
ns
K to K High
C to C High
tKHKH
1.35
0
1.49
0
1.8
0
2.2
0
2.7
0
tKHCH
tKCLock
tKCReset
K, K Clock High to C, C Clock High
DLL Lock Time
1.3
—
1.45
—
1.8
—
2.3
—
2.8
—
ns
cycle
ns
1024
30
1024
30
1024
30
1024
30
1024
30
6
K Static to DLL reset
—
—
—
—
—
Output Times
tKHQV
tCHQV
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
—
0.45
—
—
0.45
—
—
0.45
—
—
0.45
—
—
–0.5
—
0.5
—
ns
ns
ns
ns
3
3
tKHQX
tCHQX
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
–0.45
—
–0.45
—
–0.45
—
–0.45
—
tKHCQV
tCHCQV
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
0.45
—
0.45
—
0.45
—
0.45
—
0.5
—
tKHCQX
tCHCQX
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
–0.45
–0.45
–0.45
–0.45
–0.5
tCQHQV
tCQHQX
tKHQZ
tCHQZ
tKHQX1
tCHQX1
CQ, CQ High Output Valid
CQ, CQ High Output Hold
—
0.25
—
—
0.27
—
—
0.30
—
—
0.35
—
—
0.40
—
ns
ns
7
7
–0.25
–0.27
–0.30
–0.35
–0.40
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
—
0.45
—
—
0.45
—
—
0.45
—
—
0.45
—
—
0.5
—
ns
ns
3
3
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
–0.45
–0.45
–0.45
–0.45
–0.5
Setup Times
tAVKH
tIVKH
Address Input Setup Time
0.4
0.4
—
—
—
0.4
0.4
0.3
—
—
—
0.5
0.5
—
—
—
0.6
0.6
0.4
—
—
—
0.7
0.7
0.5
—
—
—
ns
ns
ns
Control Input Setup Time
Data Input Setup Time
2
tDVKH
0.28
0.35
Rev: 1.01 9/2005
20/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
AC Electrical Characteristics (Continued)
-333
-300
-250
-200
-167
Parameter
Symbol
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Hold Times
tKHAX
tKHIX
Address Input Hold Time
0.4
0.4
—
—
—
0.4
0.4
0.3
—
—
—
0.5
0.5
—
—
—
0.6
0.6
0.4
—
—
—
0.7
0.7
0.5
—
—
—
ns
ns
ns
Control Input Hold Time
tKHDX
Data Input Hold Time
0.28
0.35
Notes:
1.
2.
3.
4.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
If C, C are tied high, K, K become the references for C, C timing parameters
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN
parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two
SRAMs on the same board to be at such different voltages and temperatures.
5.
6.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
7.
Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard
bands and test setup variations.
Rev: 1.01 9/2005
21/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Rev: 1.01 9/2005
22/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Rev: 1.01 9/2005
23/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Rev: 1.01 9/2005
24/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Rev: 1.01 9/2005
25/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with the current IEEE Standard, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DD
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.
JTAG Port Registers
Overview
The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.01 9/2005
26/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.01 9/2005
27/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
ID Register Contents
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
1
1
1
1
x36
x18
x9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
x8
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.01 9/2005
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© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
JTAG Tap Controller State Diagram
Test Logic Reset
0
1
1
1
1
Run Test Idle
Select DR
0
Select IR
0
0
1
1
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
0
0
Exit2 DR
1
Exit2 IR
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
Rev: 1.01 9/2005
29/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
RFU
010
TDO.
1
Forces all RAM output drivers to High-Z.
011
100
Do not use this instruction; Reserved for Future Use.
1
1
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
RFU
RFU
101
110
111
Do not use this instruction; Reserved for Future Use.
Do not use this instruction; Reserved for Future Use.
Places Bypass Register between TDI and TDO.
1
1
1
BYPASS
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.01 9/2005
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© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
Min.
1.7
Typ.
1.8
—
Max.
Unit
V
1.9
V
V
V
V
V
DDQ
V
V
+ 0.3
DD
1.3
IH
V
–0.3
1.4
—
0.5
IL
Output High Voltage (I = –2 mA)
V
V
DD
—
—
OH
OH
Output Low Voltage (I = 2 mA)
V
V
0.4
OL
OL
SS
Note: The input level of SRAM pin is to follow the SRAM DC specification.
JTAG Port AC Test Conditions
Parameter
Symbol
Min
Unit
V /V
Input High/Low Level
Input Rise/Fall Time
1.3/0.5
1.0/1.0
0.9
V
ns
V
IH IL
TR/TF
Input and Output Timing Reference Level
Notes:
1. Distributed scope and test jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.01 9/2005
31/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
TDI
tTH
tTH
tTS
tTS
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
Min.
50
20
20
5
Max
—
—
—
—
—
—
—
—
—
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
TCK Cycle Time
CHCH
t
t
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
CHCL
CLCH
t
t
MVCH
CHMX
5
t
t
5
DVCH
CHDX
5
t
t
5
SVCH
CHSX
5
t
0
CLQV
Rev: 1.01 9/2005
32/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Package Dimensions—165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.60 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
15±0.05
B
0.20(4x)
SEATING PLANE
C
Rev: 1.01 9/2005
33/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Ordering Information—GSI SigmaCIO DDR-II SRAM
2
Org
Part Number1
Type
Package
Speed (MHz)
TA
C
C
C
C
C
I
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
GS8662R08E-333
GS8662R08E-300
GS8662R08E-250
GS8662R08E-200
GS8662R08E-167
GS8662R08E-333I
GS8662R08E-300I
GS8662R08E-250I
GS8662R08E-200I
GS8662R08E-167I
GS8662R09E-333
GS8662R09E-300
GS8662R09E-250
GS8662R09E-200
GS8662R09E-167
GS8662R09E-333I
GS8662R09E-300I
GS8662R09E-250I
GS8662R09E-200I
GS8662R09E-167I
GS8662R18E-333
GS8662R18E-300
GS8662R18E-250
GS8662R18E-200
GS8662R18E-167
GS8662R18E-333I
GS8662R18E-300I
GS8662R18E-250I
GS8662R18E-200I
GS8662R18E-167I
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
333
300
250
200
167
333
300
250
200
167
333
300
250
200
167
333
300
250
200
167
333
300
250
200
167
333
300
250
200
167
I
I
I
I
C
C
C
C
C
I
I
I
I
I
C
C
C
C
C
I
I
I
I
4M x 18
I
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS866x36E-300T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.01 9/2005
34/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Ordering Information—GSI SigmaCIO DDR-II SRAM
2
Org
Part Number1
Type
Package
Speed (MHz)
TA
C
C
C
C
C
I
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
GS8662R36E-333
GS8662R36E-300
GS8662R36E-250
GS8662R36E-200
GS8662R36E-167
GS8662R36E-333I
GS8662R36E-300I
GS8662R36E-250I
GS8662R36E-200I
GS8662R36E-167I
GS8662R08GE-333
GS8662R08GE-300
GS8662R08GE-250
GS8662R08GE-200
GS8662R08GE-167
GS8662R08GE-333I
GS8662R08GE-300I
GS8662R08GE-250I
GS8662R08GE-200I
GS8662R08GE-167I
GS8662R09GE-333
GS8662R09GE-300
GS8662R09GE-250
GS8662R09GE-200
GS8662R09GE-167
GS8662R09GE-333I
GS8662R09GE-300I
GS8662R09GE-250I
GS8662R09GE-200I
GS8662R09GE-167I
GS8662R18GE-333
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
165-bump BGA
333
300
250
200
167
333
300
250
200
167
333
300
250
200
167
333
300
250
200
167
333
300
250
200
167
333
300
250
200
167
333
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
I
165-bump BGA
I
165-bump BGA
I
165-bump BGA
I
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
C
C
C
C
C
I
I
I
I
I
C
C
C
C
C
I
I
I
I
I
4M x 18
C
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS866x36E-300T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.01 9/2005
35/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Ordering Information—GSI SigmaCIO DDR-II SRAM
2
Org
Part Number1
Type
Package
Speed (MHz)
TA
C
C
C
C
I
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
GS8662R18GE-300
GS8662R18GE-250
GS8662R18GE-200
GS8662R18GE-167
GS8662R18GE-333I
GS8662R18GE-300I
GS8662R18GE-250I
GS8662R18GE-200I
GS8662R18GE-167I
GS8662R36GE-333
GS8662R36GE-300
GS8662R36GE-250
GS8662R36GE-200
GS8662R36GE-167
GS8662R36GE-333I
GS8662R36GE-300I
GS8662R36GE-250I
GS8662R36GE-200I
GS8662R36GE-167I
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
SigmaCIO DDR-II B4 SRAM
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
300
250
200
167
333
300
250
200
167
333
300
250
200
167
333
300
250
200
167
I
I
I
I
C
C
C
C
C
I
I
I
I
2M x 36
I
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS866x36E-300T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.01 9/2005
36/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Revision History
Types of
Changes
Format or
Content
Rev. Code: Old; New
Revisions
• Creation of new datasheet
GS8662Rxx_r1
Format
• Added RoHS-compliant information
GS8662Rxx_r1; GS8662Rxx_r1_01
Content
Rev: 1.01 9/2005
37/37
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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