GS8662T20AGE-375IT [GSI]

DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165;
GS8662T20AGE-375IT
型号: GS8662T20AGE-375IT
厂家: GSI TECHNOLOGY    GSI TECHNOLOGY
描述:

DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

双倍数据速率 静态存储器
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中文:  中文翻译
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Preliminary  
GS8662T20/38AE-450/400/375/333/300  
450 MHz–300 MHz  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
72Mb SigmaCIO DDR-II+  
Burst of 2 SRAM  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
Features  
• 2.5 Clock Latency  
• Simultaneous Read and Write SigmaCIO™ Interface  
• Common I/O bus  
• JEDEC-standard pinout and package  
• Double Data Rate interface  
• Byte Write (x36 and x18) and Nybble Write (x8) function  
• Burst of 2 Read and Write  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
• Pipelined read operation with self-timed Late Write  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• Pin-compatible with present 9Mb, 18Mb, 36Mb and future  
144Mb devices  
Bottom View  
165-Bump, 15 mm x 17 mm BGA  
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
1 mm Bump Pitch, 11 x 15 Bump Array  
SigmaCIOFamily Overview  
Clocking and Addressing Schemes  
The GS8662T20/38AE are built in compliance with the  
SigmaCIO DDR-II+ SRAM pinout standard for Common I/O  
synchronous SRAMs. They are 75,497,472-bit (72Mb)  
SRAMs. The GS8662T20/38AE SigmaCIO SRAMs are just  
one element in a family of low power, low voltage HSTL I/O  
SRAMs designed to operate at the speeds needed to implement  
economical high performance networking systems.  
The GS8662T20/38AE SigmaCIO DDR-II+ SRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are independent single-ended clock  
inputs, not differential inputs to a single differential clock input  
buffer.  
Common I/O x36 and x18 SigmaCIO DDR-II+ B2RAMs  
always transfer data in two packets. When a new address is  
loaded, A0 presets an internal 1 bit address counter. The  
counter increments by 1 (toggles) for each beat of a burst of  
two data transfer.  
Common I/O x8 SigmaCIO DDR-II+ B2 RAMs always  
transfer data in two packets. When a new address is loaded,  
the LSB is internally set to 0 for the first read or write transfer,  
and incremented by 1 for the next transfer. Because the LSB  
is tied off internally, the address field of a x8 SigmaCIO DDR-  
II+ B4 RAM is always one address pin less than the advertised  
index depth (e.g., the 4M x 18 has a 2048K addressable index).  
Parameter Synopsis  
-450  
-400  
-375  
-333  
3.3 ns  
0.45 ns  
-300  
3.0 ns  
0.45 ns  
tKHKH  
tKHQV  
2.22 ns  
0.45 ns  
2.5 ns  
2.67 ns  
0.45 ns  
0.45 ns  
Rev: 1.00b 10/2009  
1/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
2M x 36 SigmaCIO DDR-II SRAM—Top View  
1
2
3
4
5
6
7
8
9
10  
11  
MCL/SA  
(144Mb)  
A
CQ  
SA  
R/W  
BW2  
K
BW1  
LD  
SA  
SA  
CQ  
B
C
D
E
F
NC  
NC  
NC  
NC  
NC  
NC  
Doff  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
DQ27  
NC  
DQ18  
DQ28  
DQ19  
DQ20  
DQ21  
DQ22  
SA  
BW3  
SA  
K
BW0  
SA  
SA  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
DQ17  
NC  
DQ8  
DQ7  
DQ16  
DQ6  
DQ5  
DQ14  
ZQ  
V
V
NC  
V
SS  
SS  
SS  
SS  
DQ29  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS  
SS  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
V
V
V
V
V
V
V
V
DQ15  
NC  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DQ30  
DQ31  
V
V
V
V
V
V
V
V
V
V
V
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
G
H
J
V
V
V
NC  
V
V
V
V
REF  
REF  
DDQ  
DDQ  
NC  
NC  
DQ32  
DQ23  
DQ24  
DQ34  
DQ25  
DQ26  
SA  
NC  
DQ13  
DQ12  
NC  
DQ4  
DQ3  
DQ2  
DQ1  
DQ10  
DQ0  
TDI  
K
L
V
NC  
NC  
NC  
NC  
NC  
SA  
DQ33  
NC  
V
V
V
V
V
DDQ  
SS  
SS  
SS  
SS  
M
N
P
R
V
V
DQ11  
NC  
SS  
SS  
SS  
SS  
DQ35  
NC  
V
SA  
SA  
SA  
SA  
QVLD  
NC  
SA  
SA  
SA  
V
SA  
SA  
SA  
SA  
DQ9  
TMS  
TCK  
2
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch  
Notes:  
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to  
DQ27:DQ35  
2. MCL = Must Connect Low  
Rev: 1.00b 10/2009  
2/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
4M x 18 SigmaCIO DDR-II SRAM—Top View  
1
2
3
4
5
6
7
8
9
10  
11  
A
B
C
D
E
F
CQ  
SA  
SA  
R/W  
BW1  
K
NC  
LD  
SA  
SA  
CQ  
NC  
NC  
NC  
NC  
NC  
NC  
Doff  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
DQ9  
NC  
NC  
NC  
SA  
NC  
SA  
K
BW0  
SA  
SA  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
DQ7  
NC  
DQ8  
NC  
V
V
NC  
V
SS  
SS  
SS  
SS  
NC  
DQ10  
DQ11  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
NC  
V
V
V
V
V
V
V
V
NC  
DQ6  
DQ5  
NC  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DQ12  
NC  
V
V
V
V
V
V
V
V
V
V
V
NC  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
G
H
J
DQ13  
V
V
V
NC  
V
V
V
V
REF  
ZQ  
REF  
DDQ  
DDQ  
NC  
NC  
NC  
DQ14  
NC  
NC  
DQ4  
NC  
NC  
K
L
V
NC  
NC  
NC  
NC  
NC  
SA  
DQ3  
DQ2  
NC  
DQ15  
NC  
V
V
V
V
V
NC  
DDQ  
SS  
SS  
SS  
SS  
M
N
P
R
NC  
V
V
DQ1  
NC  
SS  
SS  
SS  
SS  
NC  
DQ16  
DQ17  
SA  
V
SA  
SA  
SA  
SA  
QVLD  
NC  
SA  
SA  
SA  
V
NC  
NC  
SA  
SA  
SA  
SA  
NC  
DQ0  
TDI  
TCK  
TMS  
2
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch  
Notes:  
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17  
2. MCL = Must Connect Low  
Rev: 1.00b 10/2009  
3/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Pin Description Table  
Description  
Synchronous Address Inputs  
No Connect  
Type  
Input  
Comments  
Symbol  
SA  
NC  
High: Read  
Low: Write  
Synchronous Read/Write  
Synchronous Byte Writes  
Input  
Input  
R/W  
Active Low  
x18/x36 only  
BW0–BW3  
Synchronous Load Pin  
Input Clock  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Active Low  
LD  
K
Active High  
Input Clock  
Active Low  
K
Test Mode Select  
Test Data Input  
TMS  
TDI  
TCK  
TDO  
Test Clock Input  
Test Data Output  
HSTL Input Reference Voltage  
V
REF  
Output Impedance Matching Input  
Must Connect Low  
Data I/O  
Input  
ZQ  
MCL  
DQ  
Three State  
Active Low  
Input/Output  
Input  
Disable DLL when low  
Output Echo Clock  
Output Echo Clock  
Doff  
CQ  
Output  
Output  
CQ  
V
Power Supply  
Isolated Output Buffer Supply  
Power Supply: Ground  
Q Valid Output  
Supply  
Supply  
Supply  
Output  
1.8 V Nominal  
DD  
V
1.5 V or 1.8 V Nominal  
DDQ  
V
SS  
QVLD  
Notes:  
1. NC = Not Connected to die or any other pin  
2. When ZQ pin is directly connected to V , output impedance is set to minimum value and it cannot be connected to ground or left  
DDQ  
unconnected.  
3. K, or K cannot be set to V  
voltage.  
REF  
Rev: 1.00b 10/2009  
4/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Background  
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.  
Therefore, the SigmaCIO DDR-II+ SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs  
are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed  
Common I/O SRAM data bandwidth in half.  
Burst Operations  
Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will  
respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in  
the timing diagrams. It is not possible to stop a burst once it starts. Two beats of data are always transferred. This means that it is  
possible to load new addresses every K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted.  
Deselect Cycles  
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to  
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer  
and then execute the deselect command, returning the output drivers to high-Z. A high on the LD pin prevents the RAM from  
loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer  
operations.  
SigmaCIO DDR-II+ B2 SRAM Read Cycles  
The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read  
command (LD low and R/W high) is clocked into the SRAM by a rising edge of K.  
SigmaCIO DDR-II+ B2 SRAM Write Cycles  
The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers.  
Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command  
(LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures  
data in on the next rising edge of K, for a total of two transfers per address load.  
Rev: 1.00b 10/2009  
5/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Rev: 1.00b 10/2009  
6/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Power-Up Sequence for SigmaQuad-II+ SRAMs  
For compatibility across all vendors it is recommended that SigmaQuad-II+ SRAMs be powered-up in a spe-  
cific sequence in order to avoid undefined operations.  
Power-Up Sequence  
1. Power-up and maintain Doff at low state.  
1a. Apply V  
1b. Apply V  
1c. Apply V  
.
DD  
.
DDQ  
(may also be applied at the same time as V  
).  
REF  
DDQ  
2. After voltages are within specification range, and clocks (K, K) are stablized, change Doff to high.  
3. An additional 2048 clock cycles are required to lock the DLL after it has been enabled.  
Note:  
The DLL may be reset by driving the Doff pin low or by stopping the K clocks for at least 30ns. 2048 cycles  
of clean K clocks are always required to re-lock the DLL after reset.  
DLL Constraints  
The DLL synchronizes to either K clock. These clocks should have low phase jitter (t  
).  
KCVar  
• The DLL cannot operate at a frequency lower than that specified by the t  
maximum specification for the desired  
KHKH  
operating clock frequency.  
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause  
undefined errors or failures during the initial stage.  
Note: If the frequency is changed, DLL reset is required. After reset, a minimum of 2048 cycles is required  
for DLL lock.  
Rev: 1.00b 10/2009  
7/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Special Functions  
Byte Write and Nybble Write Control  
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with  
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be  
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low  
during the data in sample times in a write sequence.  
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18  
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any  
write sequence.  
Example x18 RAM Write Sequence using Byte Write Enables  
Data In Sample  
BW0  
BW1  
D0–D8  
D9–D17  
Time  
Beat 1  
Beat 2  
0
1
1
0
Data In  
Don’t Care  
Data In  
Don’t Care  
Resulting Write Operation  
Byte 1  
D0–D8  
Byte 2  
D9–D17  
Byte 3  
D0–D8  
Byte 4  
D9–D17  
Written  
Unchanged  
Beat 1  
Unchanged  
Written  
Beat 2  
FLXDrive-II Output Driver Impedance Control  
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to  
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be  
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is  
between 175and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts  
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and  
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance  
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is  
implemented with discrete binary weighted impedance steps.  
Rev: 1.00b 10/2009  
8/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Common I/O SigmaCIO DDR-II+ B2 SRAM Truth Table  
DQ  
K
LD  
R/W  
Operation  
n
A + 0  
Hi-Z  
A + 1  
Hi-Z  
1
0
0
X
0
1
Deselect  
Write  
D@K  
D@K  
n+1  
n+1  
Q@K  
Q@K  
n+2  
Read  
n+2  
B2 Byte Write Clock Truth Table  
BW  
BW  
Current Operation  
D
D
K   
K   
K   
K   
K   
(t  
)
(t  
)
(t )  
(t  
)
(t  
)
n+1  
n+2  
n
n+1  
n+2  
Write  
T
T
D1  
D2  
Dx stored if BWn = 0 in both data transfers  
Write  
T
F
F
F
T
F
D1  
X
X
D2  
X
Dx stored if BWn = 0 in 1st data transfer only  
Write  
Dx stored if BWn = 0 in 2nd data transfer only  
Write Abort  
No Dx stored in either data transfer  
X
Notes:  
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.  
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.  
Rev: 1.00b 10/2009  
9/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
x36 Byte Write Enable (BWn) Truth Table  
BW0 BW1 BW2 BW3  
D0–D8  
Don’t Care  
Data In  
D9–D17  
Don’t Care  
Don’t Care  
Data In  
D18–D26  
Don’t Care  
Don’t Care  
Don’t Care  
Don’t Care  
Data In  
D27–D35  
Don’t Care  
Don’t Care  
Don’t Care  
Don’t Care  
Don’t Care  
Don’t Care  
Don’t Care  
Don’t Care  
Data In  
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Don’t Care  
Data In  
Data In  
Don’t Care  
Data In  
Don’t Care  
Don’t Care  
Data In  
Data In  
Don’t Care  
Data In  
Data In  
Data In  
Data In  
Don’t Care  
Data In  
Don’t Care  
Don’t Care  
Data In  
Don’t Care  
Don’t Care  
Don’t Care  
Don’t Care  
Data In  
Data In  
Don’t Care  
Data In  
Data In  
Data In  
Data In  
Don’t Care  
Data In  
Don’t Care  
Don’t Care  
Data In  
Data In  
Data In  
Data In  
Don’t Care  
Data In  
Data In  
Data In  
Data In  
Data In  
Data In  
x18 Byte Write Enable (BWn) Truth Table  
BW0 BW1  
D0–D8  
Don’t Care  
Data In  
D9–D17  
Don’t Care  
Don’t Care  
Data In  
1
0
1
0
1
1
0
0
Don’t Care  
Data In  
Data In  
Rev: 1.00b 10/2009  
10/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
B2 State Diagram  
Power-Up  
LOAD  
NOP  
LOAD  
LOAD  
LOAD  
Load New  
Address  
LOAD  
READ  
WRITE  
LOAD  
DDR Read  
DDR Write  
Notes:  
1. The internal address burst counter is a 1 bit counter (i.e., when first address is A0, next internal burst address is A0+1).  
2. “READ” refers to read active status with R/W = High, “WRITE” refers to write inactive status with R/W = Low.  
3. “LOAD” refers to read new address active status with LD = Low, “LOAD” refers to read new address inactive status with LD = High.  
Rev: 1.00b 10/2009  
11/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Absolute Maximum Ratings  
(All voltages reference to V  
)
SS  
Symbol  
Description  
Value  
Unit  
V
Voltage on V Pins  
DD  
–0.5 to 2.9  
V
DD  
V
Voltage in V  
Voltage in V  
Pins  
Pins  
–0.5 to V  
V
V
DDQ  
DDQ  
REF  
DD  
V
–0.5 to V  
REF  
DDQ  
V
–0.5 to V  
–0.5 to V  
+0.5 (2.9 V max.)  
Voltage on I/O Pins  
V
I/O  
DDQ  
DDQ  
V
+0.5 (2.9 V max.)  
Voltage on Other Input Pins  
Input Current on Any Pin  
V
IN  
I
+/–100  
+/–100  
125  
mA dc  
mA dc  
IN  
I
Output Current on Any I/O Pin  
Maximum Junction Temperature  
Storage Temperature  
OUT  
o
T
C
J
o
T
–55 to 125  
C
STG  
Note:  
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended  
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect  
reliability of this component.  
Recommended Operating Conditions  
Power Supplies  
Parameter  
Supply Voltage  
Symbol  
Min.  
1.7  
Typ.  
1.8  
Max.  
1.9  
Unit  
V
V
V
V
DD  
V
I/O Supply Voltage  
Reference Voltage  
1.4  
1.9  
DDQ  
V
0.68  
0.95  
REF  
Notes:  
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V V  
1.6 V (i.e., 1.5 V I/O)  
DDQ  
and 1.7 V V  
1.9 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.  
DDQ  
2. The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal inputs. The  
DD DDQ REF  
power down sequence must be the reverse. V  
must not exceed V ..  
DDQ  
DD  
Operating Temperature  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
Unit  
Ambient Temperature  
(Commercial Range Versions)  
T
0
25  
70  
C  
A
Ambient Temperature  
(Industrial Range Versions)  
T
–40  
25  
85  
C  
A
*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.  
Rev: 1.00b 10/2009  
12/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
HSTL I/O DC Input Characteristics  
Parameter  
DC Input Logic High  
Symbol  
Min  
Max  
Units  
Notes  
V
(dc)  
V
+ 0.10  
V
V
+ 0.3 V  
DD  
V
V
1
1
IH  
REF  
V (dc)  
– 0.10  
DC Input Logic Low  
–0.3 V  
IL  
REF  
Notes:  
1. Compatible with both 1.8 V and 1.5 V I/O drivers  
2. These are DC test criteria. DC design criteria is V  
± 50 mV. The AC V /V levels are defined separately for measuring timing parame-  
REF  
IH IL  
ters.  
3. V (Min) DC = –0.3 V, V (Min) AC = –1.5 V (pulse width 3 ns).  
IL  
IL  
4.  
V
(Max) DC = V  
+ 0.3 V, V (Max) AC = V  
+ 0.85 V (pulse width 3 ns).  
DDQ  
IH  
DDQ  
IH  
HSTL I/O AC Input Characteristics  
Parameter  
AC Input Logic High  
Symbol  
Min  
Max  
Units  
Notes  
2,3  
V
(ac)  
V
+ 0.20  
REF  
V
V
V
IH  
V (ac)  
V
– 0.20  
REF  
AC Input Logic Low  
2,3  
IL  
V
Peak-to-Peak AC Voltage  
V
(ac)  
5% V  
(DC)  
REF  
1
REF  
REF  
Notes:  
1. The peak-to-peak AC component superimposed on V  
may not exceed 5% of the DC component of V  
.
REF  
REF  
2. To guarantee AC characteristics, V ,V , Trise, and Tfall of inputs and clocks must be within 10% of each other.  
IH IL  
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.  
Undershoot Measurement and Timing  
Overshoot Measurement and Timing  
V
IH  
20% tKHKH  
V
+ 1.0 V  
DD  
V
SS  
50%  
50%  
V
DD  
V
– 1.0 V  
SS  
20% tKHKH  
V
IL  
Rev: 1.00b 10/2009  
13/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Capacitance  
o
(T = 25 C, f = 1 MHZ, V = 3.3 V)  
A
DD  
Parameter  
Symbol  
Test conditions  
Typ.  
Max.  
Unit  
pF  
C
V
= 0 V  
Input Capacitance  
Output Capacitance  
Clock Capacitance  
4
6
5
5
7
6
IN  
IN  
C
V
OUT  
= 0 V  
pF  
OUT  
C
pF  
CLK  
Note:  
This parameter is sample tested.  
AC Test Conditions  
Parameter  
Conditions  
V
Input high level  
Input low level  
DDQ  
0 V  
Max. input slew rate  
Input reference level  
2 V/ns  
V
V
/2  
/2  
DDQ  
DDQ  
Output reference level  
Note:  
Test conditions as specified with output loading as shown unless otherwise noted.  
AC Test Load Diagram  
DQ  
RQ = 250 (HSTL I/O)  
= 0.75 V  
V
REF  
50  
VT = V /2  
DDQ  
Input and Output Leakage Characteristics  
Parameter  
Symbol  
Test Conditions  
Min.  
Max  
Input Leakage Current  
(except mode pins)  
I
V = 0 to V  
IN DD  
–2 uA  
2 uA  
IL  
V
V V  
IN  
–100 uA  
–2 uA  
2 uA  
2 uA  
DD  
IL  
IL  
I
Doff  
INDOFF  
0 V V V  
IN  
Output Disable,  
= 0 to V  
I
Output Leakage Current  
–2 uA  
2 uA  
OL  
V
OUT  
DDQ  
Rev: 1.00b 10/2009  
14/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Programmable Impedance HSTL Output Driver DC Electrical Characteristics  
Parameter  
Symbol  
Min.  
Max.  
Units Notes  
V
V
/2  
V
Output High Voltage  
Output Low Voltage  
Output High Voltage  
V
V
V
V
1, 3  
2, 3  
4, 5  
4, 6  
OH1  
DDQ  
DDQ  
V
V
/2  
DDQ  
Vss  
OL1  
V
V
– 0.2  
V
DDQ  
OH2  
DDQ  
V
Output Low Voltage  
Vss  
0.2  
OL2  
Notes:  
1.  
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175 RQ 350  
DDQ OH DDQ  
OH  
2.  
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175  RQ 350.  
OL  
DDQ  
OL  
DDQ  
3. Parameter tested with RQ = 250and V  
= 1.5 V or 1.8 V  
DDQ  
4. 0RQ    
5.  
6.  
I
I
= –1.0 mA  
= 1.0 mA  
OH  
OL  
Rev: 1.00b 10/2009  
15/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Rev: 1.00b 10/2009  
16/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
AC Electrical Characteristics  
-450  
-400  
-375  
-333  
-300  
Parameter  
Symbol  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Clock  
tKHKH  
tKVar  
K, K Clock Cycle Time  
2.22  
8.4  
0.2  
2.5  
8.4  
0.2  
2.67  
8.4  
0.2  
3.0  
8.4  
0.2  
3.3  
8.4  
0.2  
ns  
ns  
tKC Variable  
4
tKHKL  
tKLKH  
tKHKH  
tKHKH  
tKLock  
tKReset  
K, K Clock High Pulse Width  
K, K Clock Low Pulse Width  
K to K High  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
1.4  
1.4  
2048  
30  
ns  
0.4  
0.4  
0.4  
0.4  
ns  
0.95  
0.95  
2048  
30  
1.06  
1.06  
2048  
30  
1.13  
1.13  
2048  
30  
1.28  
1.28  
2048  
30  
ns  
K to K High  
ns  
DLL Lock Time  
cycle  
ns  
6
K Static to DLL reset  
Output Times  
tKHQV  
tKHQX  
tKHCQV  
tKHCQX  
K, K Clock High to Data Output Valid  
–0.45  
0.45  
–0.45  
0.45  
0.45  
0.45  
0.45  
ns  
ns  
ns  
K, K Clock High to Data Output Hold  
K, K Clock High to Echo Clock Valid  
–0.45  
–0.45  
–0.45  
0.45  
0.45  
0.45  
0.45  
0.45  
K, K Clock High to Echo Clock Hold  
–0.45  
–0.45  
–0.45  
–0.45  
–0.45  
ns  
tCQHQV  
tCQHQX  
tQVLD  
CQ, CQ High Output Valid  
CQ, CQ High Output Hold  
CQ, CQ High to QLVD  
–0.2  
-0.2  
0.75  
0.2  
–0.2  
-0.2  
0.86  
0.2  
–0.2  
-0.2  
0.88  
0.2  
–0.2  
-0.2  
1.03  
0.2  
–0.2  
-0.2  
1.15  
0.2  
ns  
ns  
7
7
tCQHCQH  
tKHQZ  
CQ Phase Distortion  
0.45  
0.45  
0.45  
0.45  
0.45  
ns  
ns  
ns  
K Clock High to Data Output High-Z  
5
5
tKHQX1  
K Clock High to Data Output Low-Z  
Setup Times  
–0.45  
–0.45  
–0.45  
–0.45  
–0.45  
tAVKH  
tIVKH  
Address Input Setup Time  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
ns  
ns  
1
2
Control Input Setup Time  
(R, W)  
Control Input Setup Time  
(BWX) (NWX)  
tIVKH  
0.28  
0.28  
0.28  
0.28  
0.28  
0.28  
0.28  
0.28  
0.28  
0.28  
ns  
ns  
3
tDVKH  
Data Input Setup Time  
Rev: 1.00b 10/2009  
17/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
AC Electrical Characteristics (Continued)  
-450  
-400  
-375  
-333  
-300  
Parameter  
Symbol  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Hold Times  
tKHAX  
tKHIX  
Address Input Hold Time  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
ns  
ns  
1
2
Control Input Hold Time  
(R, W)  
Control Input Hold Time  
(BWX) (NWX)  
tKHIX  
0.28  
0.28  
0.28  
0.28  
0.28  
0.28  
0.28  
0.28  
0.28  
0.28  
ns  
ns  
3
tKHDX  
Data Input Hold Time  
Notes:  
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.  
2. Control singles are R/ W.  
3. Control singles are BW0, BW1 and (BW2, BW3 for x36).  
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.  
5. To avoid bus contention, at a given voltage and temperature tKHQX1 is bigger than tKHQZ. The specs as shown do not imply bus  
contention because tKHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tKHQZ, which is a  
MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and  
temperatures.  
6.  
V
slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V and input clock are stable.  
D
D
D
D
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet  
parameters reflect tester guard bands and test setup variations.  
Rev: 1.00b 10/2009  
18/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Rev: 1.00b 10/2009  
19/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Rev: 1.00b 10/2009  
20/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
JTAG Port Operation  
Overview  
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan  
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output  
DD  
drivers are powered by V  
.
DD  
Disabling the JTAG Port  
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless  
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG  
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.  
DD  
SS  
JTAG Pin Descriptions  
Pin  
Pin Name  
I/O  
Description  
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate  
from the falling edge of TCK.  
TCK  
Test Clock  
In  
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP  
TMS  
TDI  
Test Mode Select  
Test Data In  
In controller state machine. An undriven TMS input will produce the same result as a logic one input  
level.  
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers  
placed between TDI and TDO. The register placed between TDI and TDO is determined by the  
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP  
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce  
the same result as a logic one input level.  
Output that is active depending on the state of the TAP state machine. Output changes in  
Out response to the falling edge of TCK. This is the output side of the serial registers placed between  
TDI and TDO.  
TDO  
Test Data Out  
Note:  
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is  
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.  
JTAG Port Registers  
Overview  
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s  
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the  
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the  
TDI and TDO pins.  
Instruction Register  
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or  
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the  
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the  
controller is placed in Test-Logic-Reset state.  
Bypass Register  
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through  
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.  
Rev: 1.00b 10/2009  
21/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Boundary Scan Register  
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.  
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The  
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the  
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan  
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in  
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,  
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.  
JTAG TAP Block Diagram  
·
·
·
·
·
·
·
·
Boundary Scan Register  
·
·
·
0
Bypass Register  
2
1 0  
Instruction Register  
TDI  
TDO  
ID Code Register  
31 30 29  
2 1  
0
·
· · ·  
Control Signals  
Test Access Port (TAP) Controller  
TMS  
TCK  
Identification (ID) Register  
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in  
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.  
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the  
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.  
Rev: 1.00b 10/2009  
22/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
ID Register Contents  
GSI Technology  
JEDEC Vendor  
ID Code  
Not Used  
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1  
0 1 1 0 1 1 0 0 1  
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
Tap Controller Instruction Set  
Overview  
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific  
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be  
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load  
address, data or control signals into the RAM or to preload the I/O buffers.  
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.  
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired  
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the  
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this  
device is listed in the following table.  
Rev: 1.00b 10/2009  
23/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
JTAG Tap Controller State Diagram  
Test Logic Reset  
1
0
1
1
1
Run Test Idle  
Select DR  
Select IR  
0
0
0
1
1
1
1
Capture DR  
Capture IR  
0
0
Shift DR  
Shift IR  
0
0
1
1
Exit1 DR  
Exit1 IR  
0
0
Pause DR  
Pause IR  
0
0
0
0
1
1
Exit2 DR  
Exit2 IR  
1
1
Update DR  
Update IR  
1
0
1
0
Instruction Descriptions  
BYPASS  
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This  
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-  
tate testing of other devices in the scan path.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is  
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and  
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and  
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because  
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents  
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will  
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the  
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP  
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then  
places the boundary scan register between the TDI and TDO pins.  
EXTEST  
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with  
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is  
still determined by its input pins.  
Rev: 1.00b 10/2009  
24/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.  
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output  
drivers on the falling edge of TCK when the controller is in the Update-IR state.  
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-  
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-  
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR  
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-  
ated.  
IDCODE  
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and  
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction  
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.  
SAMPLE-Z  
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-  
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR  
state.  
RFU  
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.  
JTAG TAP Instruction Set Summary  
Instruction  
EXTEST  
Code  
000  
Description  
Notes  
1
Places the Boundary Scan Register between TDI and TDO.  
Preloads ID Register and places it between TDI and TDO.  
IDCODE  
001  
1, 2  
Captures I/O ring contents. Places the Boundary Scan Register between TDI and  
SAMPLE-Z  
010  
011  
TDO.  
1
1
Forces all RAM output drivers to High-Z except CQ.  
Do not use this instruction; Reserved for Future Use.  
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.  
RFU  
SAMPLE/  
PRELOAD  
Captures I/O ring contents. Places the Boundary Scan Register between TDI and  
TDO.  
100  
101  
110  
111  
1
1
1
1
GSI  
RFU  
GSI private instruction.  
Do not use this instruction; Reserved for Future Use.  
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.  
BYPASS  
Places Bypass Register between TDI and TDO.  
Notes:  
1. Instruction codes expressed in binary, MSB on left, LSB on right.  
2. Default instruction automatically loaded at power-up and in test-logic-reset state.  
Rev: 1.00b 10/2009  
25/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
JTAG Port Recommended Operating Conditions and DC Characteristics  
Parameter  
Symbol  
Min.  
0.3  
Max.  
Unit Notes  
V
0.3 * V  
Test Port Input Low Voltage  
V
V
1
1
ILJ  
DD  
V
0.6 * V  
V
+0.3  
DD  
Test Port Input High Voltage  
IHJ  
DD  
I
TMS, TCK and TDI Input Leakage Current  
TMS, TCK and TDI Input Leakage Current  
TDO Output Leakage Current  
Test Port Output High Voltage  
Test Port Output Low Voltage  
Test Port Output CMOS High  
Test Port Output CMOS Low  
300  
1  
1
uA  
uA  
uA  
V
2
INHJ  
I
100  
1
3
INLJ  
I
1  
4
OLJ  
V
V
V
– 200 mV  
0.4  
5, 6  
5, 7  
5, 8  
5, 9  
OHJ  
DD  
V
V
OLJ  
V
– 100 mV  
V
OHJC  
DD  
V
100 mV  
V
OLJC  
Notes:  
1. Input Under/overshoot voltage must be 1 V < Vi < V  
+1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.  
DDn  
2.  
V
V V  
ILJ  
IN  
DDn  
3. 0 V V V  
IN  
ILJn  
4. Output Disable, V  
= 0 to V  
DDn  
OUT  
5. The TDO output driver is served by the V supply.  
DD  
6.  
7.  
8.  
9.  
I
I
I
I
= 2 mA  
OHJ  
= + 2 mA  
OLJ  
= –100 uA  
= +100 uA  
OHJC  
OLJC  
JTAG Port AC Test Conditions  
Parameter  
Conditions  
JTAG Port AC Test Load  
TDO  
V
– 0.2 V  
Input high level  
Input low level  
DD  
0.2 V  
1 V/ns  
*
50  
30pF  
Input slew rate  
V
V
/2  
Input reference level  
DD  
V
/2  
DD  
/2  
Output reference level  
* Distributed Test Jig Capacitance  
DD  
Notes:  
1. Include scope and jig capacitance.  
2. Test conditions as shown unless otherwise noted.  
Rev: 1.00b 10/2009  
26/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
JTAG Port Timing Diagram  
tTKC  
tTKH  
tTKL  
TCK  
TDI  
tTH  
tTS  
tTH  
tTS  
TMS  
TDO  
tTKQ  
tTH  
tTS  
Parallel SRAM input  
JTAG Port AC Electrical Characteristics  
Parameter  
Symbol  
tTKC  
tTKQ  
tTKH  
tTKL  
tTS  
Min  
50  
Max  
Unit  
ns  
TCK Cycle Time  
TCK Low to TDO Valid  
TCK High Pulse Width  
TCK Low Pulse Width  
TDI & TMS Set Up Time  
TDI & TMS Hold Time  
20  
ns  
20  
20  
10  
10  
ns  
ns  
ns  
tTH  
ns  
Rev: 1.00b 10/2009  
27/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Package Dimensions—165-Bump FPBGA (Package E)  
A1 CORNER  
TOP VIEW  
BOTTOM VIEW  
A1 CORNER  
M
M
Ø0.10  
C
Ø0.25 C A B  
Ø0.40~0.60 (165x)  
1
2 3 4 5 6 7 8 9 10 11  
11 10 9 8  
7 6 5 4 3 2 1  
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0  
10.0  
1.0  
15±0.05  
B
0.20(4x)  
SEATING PLANE  
C
Rev: 1.00b 10/2009  
28/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Ordering Information—GSI SigmaCIO DDR-II+ SRAM  
Speed  
2
Org  
Part Number1  
Type  
Package  
TA  
(MHz)  
450  
400  
375  
333  
300  
450  
400  
375  
333  
300  
450  
400  
375  
333  
300  
450  
400  
375  
333  
300  
450  
400  
375  
333  
300  
450  
400  
375  
333  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
GS8662T20AE-450  
GS8662T20AE-400  
GS8662T20AE-375  
GS8662T20AE-333  
GS8662T20AE-300  
GS8662T20AE-450I  
GS8662T20AE-400I  
GS8662T20AE-375I  
GS8662T20AE-333I  
GS8662T20AE-300I  
GS8662T38AE-450  
GS8662T38AE-400  
GS8662T38AE-375  
GS8662T38AE-333  
GS8662T38AE-300  
GS8662T38AE-450I  
GS8662T38AE-400I  
GS8662T38AE-375I  
GS8662T38AE-333I  
GS8662T38AE-300I  
GS8662T20AGE-450  
GS8662T20AGE-400  
GS8662T20AGE-375  
GS8662T20AGE-333  
GS8662T20AGE-300  
GS8662T20AGE-450I  
GS8662T20AGE-400I  
GS8662T20AGE-375I  
GS8662T20AGE-333I  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
165-bump BGA  
165-bump BGA  
C
C
C
C
C
I
165-bump BGA  
165-bump BGA  
165-bump BGA  
165-bump BGA  
165-bump BGA  
I
165-bump BGA  
I
165-bump BGA  
I
165-bump BGA  
I
165-bump BGA  
C
C
C
C
C
I
165-bump BGA  
165-bump BGA  
165-bump BGA  
165-bump BGA  
165-bump BGA  
165-bump BGA  
I
165-bump BGA  
I
165-bump BGA  
I
165-bump BGA  
I
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
C
C
C
C
C
I
I
I
I
Notes:  
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8662TxxAE-300T.  
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.  
Rev: 1.00b 10/2009  
29/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Ordering Information—GSI SigmaCIO DDR-II+ SRAM (Continued)  
Speed  
2
Org  
Part Number1  
Type  
Package  
TA  
(MHz)  
300  
450  
400  
375  
333  
300  
450  
400  
375  
333  
300  
4M x 18  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
GS8662T20AGE-300I  
GS8662T38AGE-450  
GS8662T38AGE-400  
GS8662T38AGE-375  
GS8662T38AGE-333  
GS8662T38AGE-300  
GS8662T38AGE-450I  
GS8662T38AGE-400I  
GS8662T38AGE-375I  
GS8662T38AGE-333I  
GS8662T38AGE-300I  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
SigmaCIO DDR-II+ B2 SRAM  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
RoHS-compliant 165-bump BGA  
I
C
C
C
C
C
I
I
I
I
I
Notes:  
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8662TxxAE-300T.  
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.  
Rev: 1.00b 10/2009  
30/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
Preliminary  
GS8662T20/38AE-450/400/375/333/300  
Revision History  
Types of  
Changes  
Format or  
Content  
Rev. Code: Old; New  
Revisions  
• Creation of new datasheet  
GS8662TxxAE_r1  
Format  
Rev: 1.00b 10/2009  
31/31  
© 2008, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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