GS880E18GT-100I [GSI]
Cache SRAM, 512KX18, 12ns, CMOS, PQFP100, TQFP-100;
| 型号： | GS880E18GT-100I |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Cache SRAM, 512KX18, 12ns, CMOS, PQFP100, TQFP-100 静态存储器 |
| 文件： | 总25页 (文件大小：850K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
100-Pin TQFP
Commercial Temp
Industrial Temp
100 MHz–66 MHz
512K x 18, 256K x 32, 256K x 36
8Mb Sync Burst SRAMs
3.3 V V
DD
3.3 V and 2.5 V I/O
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Features
• FT pin for user-configurable flow through or pipelined
operation
• Dual Cycle Deselect (DCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
Flow Through / Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS880E18/32/36T is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
• Automatic power-down for portable applications
• 100-lead TQFP package
-11
-11.5
10 ns
-100
-80
-66
Pipeline tCycle 10 ns
10 ns 12.5 ns 15 ns
3-1-1-1
tKQ
IDD
4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns
225 mA 225 mA 225 mA 200 mA 185 mA
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Flow
Through
2-1-1-1
tKQ
tCycle
IDD
11 ns 11.5 ns 12 ns
15 ns 15 ns 15 ns
180 mA 180 mA 180 mA 175 mA 165 mA
14 ns
15 ns
18 ns
20 ns
Sleep Mode
Functional Description
Low power (Sleep mode) is attained through the assertion
(high) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Applications
The GS880E18/32/36T is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Core and Interface Voltages
The GS880E18/32/36T operates on a 3.3 V power supply, and
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
Rev: 1.11 11/2000
1/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
GS880E18 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A18
NC
NC
VDDQ
VSS
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
5
NC
6
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
7
8
9
512K x 18
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
FT
VDD
NC
ZZ
VSS
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
NC
VSS
VDDQ
NC
NC
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.11 11/2000
2/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
GS880E32 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
DQC8
DQC7
VDDQ
2
3
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
5
6
7
8
9
256K x 32
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
FT
VDD
NC
VSS
DQD1
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.11 11/2000
3/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
GS880E36 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
DQC9
DQC8
DQC7
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
5
6
7
8
9
256K x 36
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
FT
VDD
NC
VSS
DQD1
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
DQD9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.11 11/2000
4/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
TQFP Pin Description
Typ
e
Pin Location
Symbol
Description
37, 36
A0, A1
A2–A17
A18
I
I
I
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43
Address Inputs
Address Inputs
80
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
I/O
Data Input and Output pins (x32, x36 Version)
18, 19, 22, 23, 24, 25, 28, 29
DQA9, DQB9,
DQC9, DQD9
51, 80, 1, 30
51, 80, 1, 30
I/O
—
Data Input and Output pins
No Connect (x32 Version)
Data Input and Output pins
NC
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQA1–DQA9
DQB1–DQB9
I/O
51, 52, 53, 56, 57
75, 78, 79,
NC
—
No Connect
1, 2, 3, 6, 7
25, 28, 29, 30
87
BW
I
I
Byte Write—Writes all enabled bytes; active low
93, 94
BA, BB
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/Os; active low (x32, x36
Version)
95, 96
BC, BD
I
95, 96
NC
—
I
No Connect (x18 Version)
Clock Input Signal; active high
89
CK
88
GW
I
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
98, 92
E1, E3
I
97
E2
I
Chip Enable; active high
86
G
ADV
I
Output Enable; active low
83
I
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
84, 85
ADSP, ADSC
ZZ
I
64
I
14
31
FT
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
LBO
I
VDD
15, 41, 65, 91
I
VSS
VDDQ
NC
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
16, 38, 39, 42, 66
I
I
I/O and Core Ground
Output driver power supply
No Connect.
—
Rev: 1.11 11/2000
5/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
GS880E32 Block Diagram
Register
A0–An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
36
36
Register
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
FT
G
0
Power Down
Control
DQx0–DQx9
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.11 11/2000
6/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Mode Pin Functions
Mode Name
Pin Name
State
L
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Burst Order Control
Output Register Control
Power Down Control
LBO
H or NC
L
FT
ZZ
H or NC
L or NC
H
Active
Standby, IDD = ISB
Note:
There are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
B
A
B
B
B
C
B
D
Notes
1
X
H
L
X
H
H
L
X
X
Read
H
H
H
H
L
H
H
H
H
L
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.11 11/2000
7/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Synchronous Truth Table
Operation
State
2
Address
Used
E2
3
4
Diagram
E1
ADSP ADSC ADV
W
DQ
(x36only)
5
Key
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
None
None
X
X
H
L
X
F
F
T
T
T
X
X
X
X
X
X
X
X
X
L
L
X
L
X
X
X
X
X
X
L
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
None
X
L
L
H
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
1. X = Don’t Care, H = High, L = Low.
2. For x36 Version, E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.11 11/2000
8/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CR
CW
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control
inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.11 11/2000
9/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CR
CW
CW
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.11 11/2000
10/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
VDD
VDDQ
VCK
Description
Value
Unit
Voltage on VDD Pins
–0.5 to 4.6
–0.5 to VDD
V
V
V
Voltage in VDDQ Pins
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
VI/O
–0.5 to VDDQ +0.5 (£ 4.6 V max.)
V
V
VIN
–0.5 to VDD +0.5 (£ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
TSTG
TBIAS
1.5
oC
oC
–55 to 125
–55 to 125
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.
Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
VDD
VDDQ
VIH
Min.
3.135
2.375
1.7
Typ.
3.3
2.5
—
Max.
3.6
Unit
V
Notes
VDD
I/O Supply Voltage
V
1
2
2
3
3
VDD +0.3
Input High Voltage
V
VIL
Input Low Voltage
–0.3
0
—
0.8
70
85
V
TA
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
25
°C
°C
TA
–40
25
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V £ VDDQ £ 2.375 V
(i.e., 2.5 V I/O) and 3.6 V £ VDDQ £ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.
Rev: 1.11 11/2000
11/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
50%
VSS
50%
VDD
VSS – 2.0 V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance
Symbol
Test conditions
Typ.
Max.
Unit
pF
CIN
VIN = 0 V
4
6
5
7
CI/O
VOUT = 0 V
Input/Output Capacitance
pF
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
RQJA
Max
40
Unit
Notes
1,2
single
four
—
°C/W
°C/W
°C/W
RQJA
24
1,2
RQJC
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.11 11/2000
12/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3 V
0.2 V
Input slew rate
1 V/ns
Input reference level
Output reference level
Output load
1.25 V
1.25 V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225W
225W
DQ
30pF*
50W
5pF*
VT = 1.25 V
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ³ VIN ³ VIH
0 V £ VIN £ VIH
–1 uA
–1 uA
1 uA
300 uA
IINZZ
IINM
IOL
ZZ Input Current
VDD ³ VIN ³ VIL
0 V £ VIN £ VIL
–300 uA
–1 uA
1 uA
1 uA
Mode Pin Input Current
Output Leakage Current
Output Disable,
VOUT = 0 to VDD
–1 uA
1 uA
VOH
VOH
VOL
IOH = –8 mA, VDDQ = 2.375 V
IOH = –8 mA, VDDQ = 3.135 V
IOL = 8 mA
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
—
—
—
0.4 V
Rev: 1.11 11/2000
13/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Operating Currents
-11
-11.5
-100
-80
-66
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
Parameter
Test Conditions
Symbol
Unit
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
IDD
Pipeline
Device Selected;
All other inputs
³ VIH or £ VIL
225
180
30
235
190
40
225
180
30
235
190
40
225
180
30
235
190
40
200
175
30
210
185
40
185
165
30
195
175
40
mA
mA
mA
mA
mA
mA
Operating
Current
IDD
Flow-Thru
Output open
ISB
Pipeline
Standby
Current
ZZ ³ VDD - 0.2V
ISB
Flow-Thru
30
40
30
40
30
40
30
40
30
40
IDD
Pipeline
80
90
80
90
80
90
70
80
60
70
Device Deselected;
All other inputs
³ VIH or £ VIL
Deselect
Current
IDD
Flow-Thru
65
75
65
75
65
75
55
65
50
60
Rev: 1.11 11/2000
14/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
AC Electrical Characteristics
-11
-11.5
-100
-80
-66
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock Cycle Time
tKC
tKQ
10
—
—
4.0
—
10
—
—
4.0
—
10
—
—
4.0
—
12.5
—
—
4.5
—
15
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pipeline
tKQX
1.5
1.5
15.0
—
1.5
1.5
15.0
—
1.5
1.5
15.0
—
1.5
1.5
15.0
—
1.5
1.5
20
—
—
—
—
18
—
—
—
—
4.8
4.8
—
tLZ1
tKC
—
—
—
—
—
—
—
—
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQ
11.0
—
11.5
—
12.0
—
14.0
—
Flow-
Thru
tKQX
3.0
3.0
1.7
2
3.0
3.0
1.7
2
3.0
3.0
2
3.0
3.0
2
3.0
3.0
2.3
2.5
1.5
—
tLZ1
tKH
tKL
—
—
—
—
—
—
—
—
Clock LOW Time
—
—
2.2
1.5
—
—
2.2
1.5
—
—
tHZ1
tOE
Clock to Output in High-Z
G to Output Valid
1.5
—
4.0
4.0
—
1.5
—
4.2
4.2
—
4.5
4.5
—
4.5
4.5
—
tOLZ1
G to output in Low-Z
0
0
0
0
0
tOHZ1
tS
G to output in High-Z
Setup time
—
1.5
0.5
5
4.0
—
—
—
—
2.0
0.5
5
4.2
—
—
—
—
2.0
0.5
5
4.5
—
—
—
—
2.0
0.5
5
4.5
—
—
—
—
2.0
0.5
5
4.8
—
—
—
ns
ns
ns
ns
Hold time
tH
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.11 11/2000
15/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Write Cycle Timing
Single Write
Burst Write
Deselected
Write
CK
tS tH
ADSP is blocked by E inactive
tKC
tKL
tKH
ADSP
tH
tH
tS
tS
ADSC initiated write
ADSC
ADV
ADV must be inactive for ADSP Write
tH
tS
WR2
WR3
WR1
A0–An
tS tH
GW
BW
tH
tS
tS
tH
WR3
WR1
WR2
BA–BD
E1
tS
tS
tH
tH
E1 masks ADSP
Deselected with E2
E2
tS tH
E2 and E3 only sampled with ADSP or ADSC
E3
G
tS
Write specified byte for 2A and all bytes for 2B, 2c& 2D
tH
Hi-Z
D2C
D2D
D3A
DQA–DQD
D1A
D2A
D2B
Rev: 1.11 11/2000
16/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Flow Through Read-Write Cycle Timing
Single Write
tKC
Burst Read
Single Read
CK
tS tH
ADSP is blocked by E inactive
tKH tKL
ADSP
ADSC
tS tH
ADSC initiated read
tS tH
ADV
tS
tH
RD2
WR1
RD1
A0–An
tS
tS
tH
GW
tS
tH
BW
tS
tH
BA–BD
WR1
tS
tS
tS
tH
E1 masks ADSP
E1
tH
tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
Deselected with E3
tOHZ
tOE
G
tS
tH
tKQ
Hi-Z
DQA–DQD
Q1A
D1A
Q2A
Q2A
Q2B
Q2c
Q2D
Burst wrap around to it’s initial state
Rev: 1.11 11/2000
17/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tS
tKH
tH
ADSP is blocked by E inactive
tKC
ADSP
ADSC
ADV
tS tH
ADSC initiated read
tH
tS
Suspend Burst
Suspend Burst
tS
tH
RD1
RD2
RD3
A0–An
GW
tS
tS
tH
tH
BW
BA–BD
E1
tH
tS
E1 masks ADSP
tS tH
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
tS
tH
E3
G
tOHZ
tOE
tKQX
tKQX
tOLZ
Q2B
Q2C
Q3A
Q1A
Q2A
Q2D
DQA–DQD
Hi-Z
tLZ
tHZ
tKQ
Rev: 1.11 11/2000
18/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Pipelined DCD Read Cycle Timing
Single Read
Burst Read
tKL
CK
tS tH
ADSP is blocked by E1 inactive
tKC
tKH
tS tH
ADSP
ADSC
ADSC initiated read
tS
tH
Suspend Burst
ADV
A0–An
GW
tS
tH
RD1
RD3
RD2
tS
tS
tH
tH
BW
BA–BD
E1
tS tH
E1 masks ADSP
tH
tS
E2 and E3 only sampled with ADSP or ADSC
E2
tS tH
Deselected with E2
E3
tOE
G
tOHZ
tKQX
Q2A
tKQX
tOLZ
tLZ
Hi-Z
Q1A
Q2B
Q2D
Q3A
tHZ
Q2c
DQA–DQD
tKQ
Rev: 1.11 11/2000
19/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Pipelined DCD Read-Write Cycle Timing
Single Write
Single Read
Burst Read
tKL
CK
tS
tH
tKH
tKC
ADSP is blocked by E1 inactive
ADSP
tS tH
ADSC initiated read
ADSC
ADV
tS
tH
tH
tS
tH
RD2
RD1
WR1
A0–An
tS
tS
GW
BW
tH
tH
tS
WR1
BA–BD
E1
tS tH
tS tH
E1 masks ADSP
E2 and E3 only sampled with ADSP and ADSC
E2
E3
tS
tH
Deselected with E3
tOE
tOHZ
G
tS
tH
tKQ
Hi-Z
Q1A
D1A
Q2A
DQA–DQD
Q2B
Q2c
Q2D
Rev: 1.11 11/2000
20/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings) but greater care must be exercised to avoid excessive bus contention.
Rev: 1.11 11/2000
21/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Output Driver Characteristics
120.0
100.0
Pull Down Drivers
80.0
60.0
40.0
V D D Q
20.0
I O u t
0.0
V O u t
V S S
-20.0
-40.0
-60.0
-80.0
-100.0
-120.0
-140.0
Pull Up Drivers
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD HD
3.3V PD HD
3.1V PD HD
3.1V PU HD
3.3V PU HD
3.6V PU HD
Rev: 1.11 11/2000
22/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
TQFP Package Drawing
q
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
—
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
—
0.10
7°
q
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
BPR 1999.05.18
Rev: 1.11 11/2000
23/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
514K x 18
514K x 18
514K x 18
514K x 18
514K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
514K x 18
514K x 18
514K x 18
514K x 18
514K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
Notes:
GS880E18T-11
GS880E18T-11.5
GS880E18T-100
GS880E18T-80
GS880E18T-66
GS880E32T-11
GS880E32T-11.5
GS880E32T-100
GS880E32T-80
GS880E32T-66
GS880E36T-11
GS880E36T-11.5
GS880E36T-100
GS880E36T-80
GS880E36T-66
GS880E18T-11I
GS880E18T-11.5I
GS880E18T-100I
GS880E18T-80I
GS880E18T-66I
GS880E32T-11I
GS880E32T-11.5I
GS880E32T-100I
GS880E32T-80I
GS880E32T-66I
GS880E36T-11I
GS880E36T-11.5I
GS880E36T-100I
GS880E36T-80I
GS880E36T-66I
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
100/11
100/11.5
100/12
80/14
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
66/18
100/11
100/11.5
100/12
80/14
66/18
100/11
100/11.5
100/12
80/14
66/18
100/11
100/11.5
100/12
80/14
I
I
I
66/18
I
100/11
100/11.5
100/12
80/14
I
I
I
I
66/18
I
100/11
100/11.5
100/12
80/14
I
I
I
I
66/18
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880E18TT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.11 11/2000
24/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880E18/32/36T-11/11.5/100/80/66
Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page;Revisions;Reason
New
• Last Page/Fixed “GSGS..” in Ordering Information Note.
• Fromatted Pin Outs and Pin Description to new small caps.
• Formatted Block diagrams to new small caps.
Format/Typos
• Formatted Timing Diagrams to new small caps.
• Changed “Flow thru” to “Flow Through” in Timing Diagrams.
• Package Diagram/Changed “Dimesion” to “Dimension”.
GS880E18/32/36TRev1.04h
5/1999;
• 5/Fixed pin description table to match pinouts.
• Pin Description/Changed chip enables to match pins.
• Pin Description/Changed pin 80 from NC to Address Input.
• Pin Description/Rearranged Address Inputs to match order of
Pinout
1.05 9/1999I
Content
• Package Diagram/Changed Dimension D Max from 20.1 to
22.1
• Changed Flow Through Read-Write Cycle Timing Diagram for
accuracy.
• Changed order of TQFP Address Inputs to match pinout.
• Changed order of TQFP DATA Input and Output pins to
match pinout.
GS880E18/32/36T1.05 11/
1999K880E18/32/36T1.06 1/
2000L
Content
• New GSI Logo.
• Changed all speed bin information (headings, references,
tables, ordering info..) to reflect 150 - 80Mhz
GS880E18/32/36T1.06 1/
2000L;
GS880E18/32/36T1.07 3/
2000N;
Content
Content
• Corrections to AC Electrical Characteristics Table -
GS880E18/32/36T1.07 3/
2000N;
GS880E18/32/36T1.08 3/
2000O;
• Removed 150 MHz speed bin
GS880E18/32/36T1.08 3/
2000O;
• Changed 133 MHz and 117 MHz speed bins to 11 ns and
11.5 ns (100 MHz) numbers
Content/Format
880E183236_r1_09
• Updated format to comply with Technical Publications
standards
• Updated Capitance table—removed Input row and changed
Output row to I/O
880E18_r1_09;
880E18_r1_10
Content
Content
• Corrected typo in AC Electrical Characteristics table
880E18_r1_10;
880E18_r1_11
Rev: 1.11 11/2000
25/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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