GS880F32BGT-6.5IV [GSI]
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs; 512K ×18 ， 256K ×32 ， 256K ×36 9MB同步突发静态存储器
| 型号： | GS880F32BGT-6.5IV |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| 文件： | 总21页 (文件大小：895K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS880F18/32/36BT-xxxV
5.5 ns–7.5 ns
100-Pin TQFP
Commercial Temp
Industrial Temp
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Designing For Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin
option on Pin 14. Board sites for flow through Burst RAMS
Features
• Flow Through operation; Pin 14 = No Connect
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
should be designed with V connected to the FT pin location
SS
to ensure the broadest access to multiple vendor sources.
Boards designed with FT pin pads tied low may be stuffed with
GSI’s pipeline/flow through-configurable Burst RAMs or any
vendor’s flow through or configurable Burst SRAM. Boards
designed with the FT pin location tied high or floating must
employ a non-configurable flow through Burst RAM, like this
RAM, to achieve flow through functionality.
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Applications
The GS880F18/32/36BT-xxxV is a 9,437,184-bit (8,388,608-
bit for x32 version) high performance synchronous SRAM
with a 2-bit burst address counter. Although of a type
originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Core and Interface Voltages
The GS880F18/32/36BT-xxxV operates on a 1.8 V or 2.5 V
power supply. All input are 2.5 V and 1.8 V compatible.
Separate output power (V
) pins are used to decouple
DDQ
output noise from the internal circuits and are 2.5 V and 1.8 V
compatible.
Paramter Synopsis
-5.5
-6.5
-150
Unit
tKQ
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
tCycle
Flow Through
2-1-1-1
Curr (x18)
Curr (x32/x36)
160
185
140
160
128
145
mA
mA
Rev: 1.00 6/2006
1/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
GS880F18BT-xxxV 100-Pin TQFP Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
V
NC
DQPA
DQA
DQA
V
V
DQA
DQA
V
NC
V
ZZ
DQA
DQA
V
V
V
DDQ
DDQ
V
SS
SS
NC
NC
DQB
DQB
512K x 18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
Top View
V
DDQ
DDQ
DQB
DQB
NC
SS
V
DD
NC
DD
V
SS
DQB
DQB
V
DDQ
DDQ
V
SS
SS
DQA
DQA
NC
NC
V
DQB
DQB
DQPB
NC
V
SS
SS
V
V
DDQ
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00 6/2006
2/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
GS880F32BT-xxxV 100-Pin TQFP Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
DQB
DQB
V
NC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
DDQ
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
256K x 32
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
V
SS
NC
NC
V
DD
V
NC
DD
ZZ
V
SS
DQA
DQA
V
DQD
DQD2
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
NC
DQD
DQD
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00 6/2006
3/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
GS880F36BT-xxxV 100-Pin TQFP Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPB
DQB
DQB
DQPC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
V
DDQ
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
256K x 36
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
V
SS
NC
NC
V
DD
V
NC
DD
ZZ
DQA
DQA
V
SS
DQD
DQD
V
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
DQPA
DQD
DQD
DQPD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00 6/2006
4/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
TQFP Pin Description
Symbol
A0, A1
A
Type
Description
I
I
Address field LSBs and Address Counter preset Inputs
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
NC
—
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Clock Input Signal; active high
BW
I
I
I
I
I
I
I
I
I
I
I
I
BA, BB, BC, BD
CK
GW
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
E1, E3
E2
Chip Enable; active high
G
Output Enable; active low
ADV
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
ADSP, ADSC
ZZ
LBO
Linear Burst Order mode; active low
Core power supply
V
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 1.00 6/2006
5/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
GS880F18/32/36BT-xxxV Block Diagram
Register
A0–An
D
Q
A0
A0
A1
D0
D1
Q0
Q1
A1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
36
36
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
NC
G
0
Power Down
Control
DQx1–DQx9
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.00 6/2006
6/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Active
L
Burst Order Control
LBO
H
L or NC
H
Power Down Control
ZZ
Standby, I = I
DD SB
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above table.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00 6/2006
7/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
Byte Write Truth Table
Function
Read
GW
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
H
H
H
H
H
H
H
L
Read
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
L
2, 3
L
H
H
H
L
2, 3
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.00 6/2006
8/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
Synchronous Truth Table
Operation
State
Address
Used
2
3
4
Diagram
E1
ADSP ADSC ADV
E
W
DQ
5
Key
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
None
None
X
X
H
L
X
X
L
L
X
L
X
X
X
X
X
X
L
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
F
F
T
T
T
X
X
X
X
X
X
X
X
High-Z
None
X
L
L
H
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
R
L
L
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.00 6/2006
9/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)
control inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.00 6/2006
10/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.00 6/2006
11/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
DD
DD
V
Voltage on V
Pins
–0.5 to V
V
DDQ
DDQ
DD
V
–0.5 to V
+0.5 (≤ 4.6 V max.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
V
I/O
V
–0.5 to V +0.5 (≤ 4.6 V max.)
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges (1.8 V/2.5 V Version)
Parameter
Symbol
Min.
1.7
Typ.
1.8
Max.
2.0
Unit
Notes
V
1.8 V Supply Voltage
2.5 V Supply Voltage
V
V
V
V
DD1
V
2.3
2.5
2.7
DD2
1.8 V V
I/O Supply Voltage
V
V
1.7
1.8
DDQ
DDQ
DDQ1
DD
2.5 V V
I/O Supply Voltage
V
V
2.3
2.5
DDQ2
DD
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Rev: 1.00 6/2006
12/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
V
& V
Range Logic Levels
DDQ2
DDQ1
Parameter
Symbol
Min.
Typ.
—
Max.
Unit
V
Notes
V
V
Input High Voltage
V
0.6*V
V
+ 0.3
DD
1
1
DD
IH
DD
Input Low Voltage
V
0.3*V
DD
–0.3
—
V
DD
IL
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Recommended Operating Temperatures
Parameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
°C
Notes
T
Ambient Temperature (Commercial Range Versions)
2
2
A
T
Ambient Temperature (Industrial Range Versions)
–40
25
85
°C
A
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
DD
V
SS
50%
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
pF
I/O
Note:
These parameters are sample tested.
Rev: 1.00 6/2006
13/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Figure 1
Output Load 1
Input slew rate
V
DQ
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
*
50Ω
30pF
Fig. 1
Notes:
V
DDQ/2
* Distributed Test Jig Capacitance
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
I
V
≥ V ≥ 0 V
DD IN
FT, ZZ Input Current
–100 uA
–1 uA
100 uA
1 uA
IN
I
Output Disable, V
= 0 to V
Output Leakage Current
OL
OUT DD
DC Output Characteristics (1.8 V/2.5 V Version)
Parameter
Symbol
Test Conditions
Min
Max
—
V
I
= –4 mA, V
= 1.6 V
V
– 0.4 V
DDQ
1.8 V Output High Voltage
2.5 V Output High Voltage
1.8 V Output Low Voltage
2.5 V Output Low Voltage
OH1
OH
DDQ
V
I
= –8 mA, V
= 2.375 V
DDQ
1.7 V
—
OH2
OH
V
I
I
= 4 mA
= 8 mA
—
—
0.4 V
0.4 V
OL1
OL
OL
V
OL2
Rev: 1.00 6/2006
14/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
Operating Currents
-5.5
-6.5
-7.5
–40
to
Parameter
Test Conditions
Mode
Symbol
Unit
0
0
–40
0
–40
to 70°C 85°C to 70°C to 85°C to 70°C to 85°C
IDD
160
25
180
25
140
20
160
20
130
15
150
15
Device Selected;
All other inputs
≥VIH or ≤ VIL
(x32/x36) Flow Through
mA
IDDQ
Operating
Current
IDD
145
15
165
15
130
10
150
10
120
8
140
8
(x18)
Flow Through
mA
mA
Output open
IDDQ
Standby
Current
ZZ ≥ VDD – 0.2 V
ISB
Flow Through
40
60
50
65
40
50
50
55
40
50
50
55
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
Deselect
Current
IDD
Flow Through
mA
Notes:
1.
I
and I
apply to any combination of V , V , V
, and V
operation.
DD
DDQ
DD2 DD1 DDQ2
DDQ1
2. All parameters listed are worst case scenario.
AC Electrical Characteristics
-5.5
-6.5
-7.5
Parameter
Symbol
Unit
Min
5.5
—
Max
—
5.5
—
—
—
—
—
Min
6.5
—
Max
—
6.5
—
—
—
—
—
Min
7.5
—
Max
—
7.5
—
—
—
—
—
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
ns
ns
ns
ns
ns
ns
ns
tKQX
2.0
2.0
1.5
0.5
1.3
2.0
2.0
1.5
0.5
1.3
2.0
2.0
1.5
0.5
1.5
Flow Through
tLZ1
tS
Clock to Output in Low-Z
Setup time
Hold time
tH
Clock HIGH Time
tKH
Clock LOW Time
tKL
1.7
1.5
—
1.7
1.5
—
1.7
1.5
—
ns
ns
Clock to Output in
High-Z
tHZ1
2.5
3.0
3.0
G to Output Valid
G to output in Low-Z
G to output in High-Z
ZZ setup time
tOE
—
0
2.5
—
2.5
—
—
—
—
0
3.0
—
3.0
—
—
—
—
0
3.8
—
3.8
—
—
—
ns
ns
ns
ns
ns
ns
tOLZ1
tOHZ1
tZZS2
tZZH2
tZZR
—
5
—
5
—
5
ZZ hold time
1
1
1
ZZ recovery
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.00 6/2006
15/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
Flow Through Mode Timing
Begin
Read A Cont
tKH
Cont
Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont
Deselect
tKL
tKC
CK
Fixed High
ADSP
tS
tH
tS
tH
ADSC initiated read
ADSC
ADV
A0–An
GW
tS
tH
tS
tH
A
B
C
tS
tH
tS
tH
BW
tS
tH
Ba–Bd
E1
tS
tS
Deselected with E1
tH
tH
E2 and E3 only sampled with ADSC
E2
tS
tH
E3
G
tH
tS
tKQ
tLZ
tHZ
tOE
tOHZ
D(B)
tKQX
Q(A)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
DQa–DQd
Rev: 1.00 6/2006
16/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
Setup
Hold
ADSP
ADSC
tZZR
tZZS
tZZH
ZZ
Rev: 1.00 6/2006
17/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
TQFP Package Drawing (Package T)
θ
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
0.10
7°
θ
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.00 6/2006
18/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
Ordering Information for GSI Synchronous Burst RAMs
2
Voltage
Option
Speed
(ns)
3
1
4
Org
Type
Package
T
Part Number
Status
A
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
GS880F18BT-5.5V
GS880F18BT-6.5V
GS880F18BT-7.5V
GS880F32BT-5.5V
GS880F32BT-6.5V
GS880F32BT-7.5V
GS880F36BT-5.5V
GS880F36BT-6.5V
GS880F36BT-7.5V
GS880F18BT-5.5IV
GS880F18BT-6.5IV
GS880F18BT-7.5IV
GS880F32BT-5.5IV
GS880F32BT-6.5IV
GS880F32BT-7.5IV
GS880F36BT-5.5IV
GS880F36BT-6.5IV
GS880F36BT-7.5IV
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
TQFP
TQFP
5.5
6.5
7.5
5.5
6.5
7.5
5.5
6.5
7.5
5.5
6.5
7.5
5.5
6.5
7.5
5.5
6.5
7.5
5.5
6.5
7.5
5.5
6.5
7.5
5.5
6.5
7.5
5.5
6.5
C
C
C
C
C
C
C
C
C
I
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
I
TQFP
I
TQFP
I
TQFP
I
TQFP
I
TQFP
I
TQFP
I
TQFP
I
512K x 18 GS880F18BGT-5.5V
512K x 18 GS880F18BGT-6.5V
512K x 18 GS880F18BGT-7.5V
256K x 32 GS880F32BGT-5.5V
256K x 32 GS880F32BGT-6.5V
256K x 32 GS880F32BGT-7.5V
256K x 36 GS880F36BGT-5.5V
256K x 36 GS880F36BGT-6.5V
256K x 36 GS880F36BGT-7.5V
512K x 18 GS880F18BGT-5.5IV
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
C
C
C
C
C
C
C
C
C
I
512K x 18 GS880F18BGT-6.5IV
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880F18BT-5.5IVT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. MP = Mass Production. PQ = Pre-Qualification.
5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00 6/2006
19/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
Ordering Information for GSI Synchronous Burst RAMs
2
Voltage
Option
Speed
(ns)
3
1
4
Org
Type
Package
T
Part Number
Status
A
512K x 18 GS880F18BGT-7.5IV
256K x 32 GS880F32BGT-5.5IV
256K x 32 GS880F32BGT-6.5IV
256K x 32 GS880F32BGT-7.5IV
256K x 36 GS880F36BGT-5.5IV
256K x 36 GS880F36BGT-6.5IV
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
7.5
5.5
6.5
7.5
5.5
6.5
7.5
I
I
I
I
I
I
I
PQ
PQ
PQ
PQ
PQ
PQ
PQ
256K x 36 GS880F36BGT-7.5IV
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880F18BT-5.5IVT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. MP = Mass Production. PQ = Pre-Qualification.
5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00 6/2006
20/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS880F18/32/36BT-xxxV
9Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
880FxxB_V_r1
Rev: 1.00 6/2006
21/21
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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