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GS880Z18BGT-225T [GSI]

ZBT SRAM, 512KX18, 6ns, CMOS, PQFP100, TQFP-100;
GS880Z18BGT-225T
型号： GS880Z18BGT-225T
厂家： GSI TECHNOLOGY    GSI TECHNOLOGY
描述：

ZBT SRAM, 512KX18, 6ns, CMOS, PQFP100, TQFP-100

静态存储器
文件： 总23页 (文件大小：684K)
中文：  中文翻译
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GS880Z18/36BT-250/225/200/166/150/133  
100-Pin TQFP  
Commercial Temp  
Industrial Temp  
250 MHz–133 MHz  
9Mb Pipelined and Flow Through  
2.5 V or 3.3 V VDD  
2.5 V or 3.3 V I/O  
Synchronous NBT SRAM  
Features  
Functional Description  
• NBT (No Bus Turn Around) functionality allows zero wait  
read-write-read bus utilization; Fully pin-compatible with  
both pipelined and flow through NtRAM™, NoBL™ and  
ZBT™ SRAMs  
The GS880Z18/36BT is a 9Mbit Synchronous Static SRAM.  
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other  
pipelined read/double late write or flow through read/single  
late write SRAMs, allow utilization of all available bus  
bandwidth by eliminating the need to insert deselect cycles  
when the device is switched from read to write cycles.  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• User-configurable Pipeline and Flow Through mode  
• LBO pin for Linear or Interleave Burst mode  
• Pin compatible with 2M, 4M, and 18M devices  
• Byte write operation (9-bit Bytes)  
Because it is a synchronous device, address, data inputs, and  
read/ write control inputs are captured on the rising edge of the  
input clock. Burst order control (LBO) must be tied to a power  
rail for proper operation. Asynchronous inputs include the  
Sleep mode enable (ZZ) and Output Enable. Output Enable can  
be used to override the synchronous control of the output  
drivers and turn the RAM's output drivers off at any time.  
Write cycles are internally self-timed and initiated by the rising  
edge of the clock input. This feature eliminates complex off-  
chip write pulse generation required by asynchronous SRAMs  
and simplifies input signal timing.  
• 3 chip enable signals for easy depth expansion  
• ZZ Pin for automatic power-down  
• JEDEC-standard 100-lead TQFP package  
-250 -225 -200 -166 -150 -133 Unit  
Pipeline  
3-1-1-1  
t
2.5 2.7 3.0 3.4 3.8 4.0 ns  
4.0 4.4 5.0 6.0 6.7 7.5 ns  
KQ  
tCycle  
Curr (x18) 280 255 230 200 185 165 mA  
Curr (x36) 330 300 270 230 215 190 mA  
3.3 V  
2.5 V  
The GS880Z18/36BT may be configured by the user to  
operate in Pipeline or Flow Through mode. Operating as a  
pipelined synchronous device, meaning that in addition to the  
rising edge triggered registers that capture input signals, the  
device incorporates a rising-edge-triggered output register. For  
read cycles, pipelined SRAM output data is temporarily stored  
by the edge triggered output register during the access cycle  
and then released to the output drivers at the next rising edge of  
clock.  
Curr (x18) 275 250 230 195 180 165 mA  
Curr (x36) 320 295 265 225 210 185 mA  
Flow  
Through  
2-1-1-1  
t
5.5 6.0 6.5 7.0 7.5 8.5 ns  
5.5 6.0 6.5 7.0 7.5 8.5 ns  
KQ  
tCycle  
Curr (x18) 175 165 160 150 145 135 mA  
Curr (x36) 200 190 180 170 165 150 mA  
3.3 V  
2.5 V  
Curr (x18) 175 165 160 150 145 135 mA  
Curr (x36) 200 190 180 170 165 150 mA  
The GS880Z18/36BT is implemented with GSI's high  
performance CMOS technology and is available in a JEDEC-  
Standard 100-pin TQFP package.  
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles  
Clock  
Address  
A
R
B
C
R
D
E
R
F
Read/Write  
W
W
W
Flow Through  
Data I/O  
Q
D
Q
D
D
Q
E
A
B
C
D
Pipelined  
Data I/O  
Q
Q
D
Q
E
A
B
C
D
Rev: 1.00b 12/2002  
1/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.  
GS880Z18/36BT-250/225/200/166/150/133  
GS880Z18BT Pinout  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
A18  
NC  
NC  
V
SS  
NC  
DQA9  
DQA8  
DQA7  
NC  
NC  
NC  
1
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
2
3
V
4
DDQ  
DDQ  
V
V
5
SS  
NC  
NC  
6
7
8
DQB1  
DQB2  
9
512K x 18  
Top View  
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
SS  
DDQ  
SS  
V
V
DDQ  
DQA6  
DQB3  
DQB4  
FT  
DQA5  
V
SS  
NC  
V
V
DD  
DD  
SS  
V
DD  
ZZ  
V
DQA4  
DQA3  
DQB5  
DQB6  
V
V
V
DDQ  
DDQ  
SS  
V
SS  
DQA2  
DQA1  
NC  
DQB7  
DQB8  
DQB9  
NC  
NC  
V
V
V
SS  
DDQ  
SS  
V
DDQ  
NC  
NC  
NC  
NC  
NC  
NC  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
Rev: 1.00b 12/2002  
2/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
GS880Z36BT Pinout  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
DQB9  
DQB8  
DQB7  
DQC9  
DQC8  
DQC7  
1
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
2
3
V
V
4
DDQ  
DDQ  
SS  
V
V
5
SS  
DQB6  
DQB5  
DQB4  
DQB3  
DQC6  
DQC5  
DQC4  
DQC3  
6
7
8
9
256K x 36  
Top View  
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
SS  
DDQ  
SS  
V
V
DDQ  
DQB2  
DQC2  
DQC1  
FT  
DQB1  
V
SS  
NC  
V
V
DD  
DD  
SS  
V
DD  
ZZ  
V
DQA1  
DQA2  
DQD1  
DQD2  
DDQ  
V
V
V
DDQ  
SS  
V
SS  
DQA3  
DQA4  
DQA5  
DQA6  
DQD3  
DQD4  
DQD5  
DQD6  
V
V
V
SS  
DDQ  
SS  
V
DDQ  
DQA7  
DQA8  
DQA9  
DQD7  
DQD8  
DQD9  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
Rev: 1.00b 12/2002  
3/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
100-Pin TQFP Pin Descriptions  
Symbol  
Type  
In  
Description  
A0, A1  
Burst Address Inputs; Preload the burst counter  
A2–A17  
A18  
In  
Address Inputs  
Address Input (x18 Version Only)  
In  
CK  
In  
Clock Input Signal  
BA  
In  
Byte Write signal for data inputs DQA1–DQA9; active low  
Byte Write signal for data inputs DQB1–DQB9; active low  
Byte Write signal for data inputs DQC1–DQC9; active low  
Byte Write signal for data inputs DQD1–DQD9; active low  
Write Enable; active low  
BB  
In  
BC  
In  
BD  
In  
W
In  
E1  
In  
Chip Enable; active low  
E2  
In  
Chip Enable; Active High. For self decoded depth expansion  
Chip Enable; Active Low. For self decoded depth expansion  
Output Enable; active low  
E3  
G
In  
In  
ADV  
In  
Advance/Load; Burst address counter control pin  
Clock Input Buffer Enable; active low  
No Connect  
CKE  
In  
NC  
—
I/O  
I/O  
I/O  
I/O  
In  
DQA1–DQA9  
DQB1–DQB9  
DQC1–DQC9  
DQD1–DQD9  
ZZ  
Byte A Data Input and Output pins  
Byte B Data Input and Output pins  
Byte C Data Input and Output pins  
Byte D Data Input and Output pins  
Power down control; active high  
FT  
In  
Pipeline/Flow Through Mode Control; active low  
Linear Burst Order; active low  
LBO  
In  
V
In  
Core power supply  
DD  
V
In  
In  
Ground  
SS  
V
Output driver power supply  
DDQ  
Rev: 1.00b 12/2002  
4/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
GS880Z18/36B NBT SRAM Functional Block Diagram  
n s e e S A m p s  
s
i t r e W D r i v e r  
Rev: 1.00b 12/2002  
5/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Functional Details  
Clocking  
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to  
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.  
Pipeline Mode Read and Write Operations  
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle  
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device  
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable  
inputs will deactivate the device.  
Function  
Read  
W
H
L
BA  
X
BB  
X
BC  
X
BD  
X
Write Byte “a”  
Write Byte “b”  
Write Byte “c”  
Write Byte “d”  
Write all Bytes  
Write Abort/NOP  
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three  
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address  
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control  
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At  
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.  
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.  
The Byte Write Enable inputs (BA, BB, BC, & BD) determine which bytes will be written. All or none may be activated. A write  
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,  
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At  
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is  
required at the third rising edge of clock.  
Flow Through Mode Read and Write Operations  
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the  
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after  
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow  
Through mode the read pipeline is one cycle shorter than in Pipeline mode.  
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability  
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late  
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address  
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of  
clock.  
Rev: 1.00b 12/2002  
6/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Synchronous Truth Table  
Operation  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Continue  
Read Cycle, Begin Burst  
Read Cycle, Continue Burst  
NOP/Read, Begin Burst  
Dummy Read, Continue Burst  
Write Cycle, Begin Burst  
Write Cycle, Continue Burst  
NOP/Write Abort, Begin Burst  
Write Abort, Continue Burst  
Clock Edge Ignore, Stall  
Sleep Mode  
Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes  
D
D
D
D
R
B
None  
None  
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L-H High-Z  
L-H High-Z  
L-H High-Z  
L-H High-Z  
None  
L
None  
X
H
X
H
X
H
X
H
X
X
X
H
L
1
External  
Next  
L-H  
L-H  
Q
Q
X
L
X
L
H
L
L
1,10  
2
R
B
External  
Next  
H
H
X
X
X
X
X
X
L-H High-Z  
X
L
X
L
H
L
L-H High-Z 1,2,10  
W
B
External  
Next  
L-H  
L-H  
D
D
3
X
L
X
L
H
L
X
L
L
1,3,10  
2,3  
W
B
None  
H
H
X
X
L-H High-Z  
Next  
X
X
X
X
X
X
H
X
X
X
X
X
L-H High-Z 1,2,3,10  
Current  
None  
L-H  
X
-
4
High-Z  
Notes:  
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-  
lect cycle is executed first.  
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W  
pin is sampled low but no Byte Write pins are active so no write operation is performed.  
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during  
write cycles.  
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus  
will remain in High Z.  
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write  
signals are Low  
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.  
7. Wait states can be inserted by setting CKE high.  
8. This device contains circuitry that ensures all outputs are in High Z during power-up.  
9. A 2-bit burst counter is incorporated.  
10. The address counter is incriminated for all Burst continue cycles.  
Rev: 1.00b 12/2002  
7/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Pipeline and Flow Through Read Write Control State Diagram  
D
B
Deselect  
R
D
D
W
New Read  
New Write  
R
R
W
B
B
R
W
W
R
Burst Read  
Burst Write  
B
B
D
D
Key  
Notes:  
Input Command Code  
1. The Hold command (CKE Low) is not  
shown because it prevents any state change.  
ƒ
Transition  
2. W, R, B and D represent input command  
codes ,as indicated in the Synchronous Truth Table.  
Current State (n)  
Next State (n+1)  
n
n+1  
n+2  
n+3  
Clock (CK)  
Command  
ƒ
ƒ
ƒ
ƒ
Current State  
Next State  
Current State and Next State Definition for Pipeline and Flow Through Read/Write Control State Diagram  
Rev: 1.00b 12/2002  
8/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Pipeline Mode Data I/O State Diagram  
Intermediate  
Intermediate  
R
B
W
B
Intermediate  
R
Data Out  
(Q Valid)  
High Z  
(Data In)  
W
D
Intermediate  
D
Intermediate  
W
R
High Z  
B
D
Intermediate  
Key  
Notes:  
Input Command Code  
1. The Hold command (CKE Low) is not  
shown because it prevents any state change.  
ƒ
Transition  
Transition  
2. W, R, B, and D represent input command  
codes as indicated in the Truth Tables.  
Current State (n)  
Next State (n+2)  
Intermediate State (N+1)  
n
n+1  
n+2  
n+3  
Clock (CK)  
Command  
ƒ
ƒ
ƒ
ƒ
Intermediate  
State  
Current State  
Next State  
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram  
Rev: 1.00b 12/2002  
9/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Flow Through Mode Data I/O State Diagram  
R
B
W
B
R
Data Out  
(Q Valid)  
High Z  
(Data In)  
W
D
D
W
R
High Z  
B
D
Key  
Notes  
Input Command Code  
1. The Hold command (CKE Low) is not  
shown because it prevents any state change.  
ƒ
Transition  
2. W, R, B and D represent input command  
codes as indicated in the Truth Tables.  
Current State (n)  
Next State (n+1)  
n
n+1  
n+2  
n+3  
Clock (CK)  
Command  
ƒ
ƒ
ƒ
ƒ
Current State  
Next State  
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram  
Rev: 1.00b 12/2002  
10/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Burst Cycles  
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from  
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address  
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when  
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write  
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into  
Load mode.  
Burst Order  
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been  
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst  
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables  
below for details.  
Mode Pin Functions  
Mode Name  
Pin Name State  
Function  
Linear Burst  
Interleaved Burst  
Active  
L
Burst Order Control  
LBO  
H
L or NC  
Power Down Control  
ZZ  
Standby, I = I  
H
DD SB  
Note:  
There is a pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will  
operate in the default states as specified in the above tables.  
Burst Counter Sequences  
Linear Burst Sequence  
Interleaved Burst Sequence  
A[1:0] A[1:0] A[1:0] A[1:0]  
A[1:0] A[1:0] A[1:0] A[1:0]  
1st address  
2nd address  
3rd address  
4th address  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
1st address  
2nd address  
3rd address  
4th address  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Note: The burst counter wraps to initial state on the 5th clock.  
Note: The burst counter wraps to initial state on the 5th clock.  
BPR 1999.05.18  
Rev: 1.00b 12/2002  
11/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Sleep Mode  
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,  
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to  
low, the SRAM operates normally after ZZ recovery time.  
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of  
SB  
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become  
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.  
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending  
SB  
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated  
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands  
may be applied while the SRAM is recovering from Sleep mode.  
Sleep Mode Timing Diagram  
CK  
tZZR  
ZZ  
Sleep  
tZZS  
tZZH  
Designing for Compatibility  
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found  
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V or V  
on pipelined parts and V on flow  
SS  
DD  
DDQ  
through parts. GSI NBT SRAMs are fully compatible with these sockets.  
Pin 66, a No Connect (NC) on GSI’s GS880Z18B/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36B  
NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked V or V  
DD  
DDQ  
on pipelined parts and V on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity  
SS  
feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode  
applications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By  
using the pull-up resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT  
SRAMs (GS881Z18/36B), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active  
low, open drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.  
Rev: 1.00b 12/2002  
12/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Absolute Maximum Ratings  
(All voltages reference to V  
)
SS  
Symbol  
Description  
Value  
Unit  
V
V
Voltage on V Pins  
–0.5 to 4.6  
DD  
DD  
V
Voltage in V  
Pins  
DDQ  
–0.5 to 4.6  
V
DDQ  
V
–0.5 to V  
+0.5 (≤ 4.6 V max.)  
DDQ  
Voltage on I/O Pins  
Voltage on Other Input Pins  
Input Current on Any Pin  
Output Current on Any I/O Pin  
Package Power Dissipation  
Storage Temperature  
V
I/O  
V
–0.5 to V +0.5 (≤ 4.6 V max.)  
V
IN  
DD  
I
+/–20  
+/–20  
mA  
mA  
W
IN  
I
OUT  
P
1.5  
D
o
T
–55 to 125  
–55 to 125  
C
STG  
o
T
Temperature Under Bias  
C
BIAS  
Note:  
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended  
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of  
this component.  
Rev: 1.00b 12/2002  
13/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Power Supply Voltage Ranges  
Parameter  
Symbol  
Min.  
3.0  
Typ.  
3.3  
Max.  
3.6  
Unit  
Notes  
V
3.3 V Supply Voltage  
2.5 V Supply Voltage  
V
V
V
V
DD3  
V
2.3  
2.5  
2.7  
DD2  
3.3 V V  
2.5 V V  
I/O Supply Voltage  
I/O Supply Voltage  
V
3.0  
3.3  
3.6  
DDQ  
DDQ  
DDQ3  
V
2.3  
2.5  
2.7  
DDQ2  
Notes:  
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are  
evaluated for worst case in the temperature range marked on the device.  
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.  
V
Range Logic Levels  
Parameter  
DDQ3  
Symbol  
Min.  
2.0  
Typ.  
—
Max.  
Unit  
Notes  
V
Input High Voltage  
V
V
+ 0.3  
DD  
V
V
V
V
1
DD  
IH  
V
Input Low Voltage  
V
–0.3  
2.0  
—
0.8  
+ 0.3  
1
DD  
IL  
V
I/O Input High Voltage  
I/O Input Low Voltage  
V
V
—
1,3  
1,3  
DDQ  
IHQ  
DDQ  
V
V
–0.3  
—
0.8  
DDQ  
ILQ  
Notes:  
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are  
evaluated for worst case in the temperature range marked on the device.  
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.  
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.  
V
Range Logic Levels  
Parameter  
DDQ2  
Symbol  
Min.  
Typ.  
—
Max.  
Unit  
Notes  
V
Input High Voltage  
V
0.6*V  
V
+ 0.3  
DD  
V
V
V
V
1
DD  
IH  
DD  
V
Input Low Voltage  
V
0.3*V  
DD  
–0.3  
—
1
DD  
IL  
V
I/O Input High Voltage  
I/O Input Low Voltage  
V
0.6*V  
V
+ 0.3  
DDQ  
—
1,3  
1,3  
DDQ  
IHQ  
DD  
V
V
0.3*V  
DD  
–0.3  
—
DDQ  
ILQ  
Notes:  
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are  
evaluated for worst case in the temperature range marked on the device.  
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.  
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.  
Rev: 1.00b 12/2002  
14/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Recommended Operating Temperatures  
Parameter  
Symbol  
Min.  
0
Typ.  
25  
Max.  
70  
Unit  
°C  
Notes  
T
Ambient Temperature (Commercial Range Versions)  
2
2
A
T
Ambient Temperature (Industrial Range Versions)  
Note:  
–40  
25  
85  
°C  
A
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are  
evaluated for worst case in the temperature range marked on the device.  
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.  
Undershoot Measurement and Timing  
Overshoot Measurement and Timing  
V
IH  
20% tKC  
V
+ 2.0 V  
50%  
DD  
V
SS  
50%  
V
DD  
V
– 2.0 V  
SS  
20% tKC  
V
IL  
Capacitance  
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)  
A
DD  
Parameter  
Symbol  
Test conditions  
Typ.  
Max.  
Unit  
pF  
C
V
= 0 V  
Input Capacitance  
4
6
5
7
IN  
IN  
C
V
OUT  
= 0 V  
Input/Output Capacitance  
pF  
I/O  
Note: These parameters are sample tested.  
Package Thermal Characteristics  
Rating  
Junction to Ambient (at 200 lfm)  
Junction to Ambient (at 200 lfm)  
Junction to Case (TOP)  
Notes:  
Layer Board  
Symbol  
Max  
40  
Unit  
Notes  
1,2  
R
R
R
single  
four  
—
°C/W  
°C/W  
°C/W  
ΘJA  
ΘJA  
ΘJC  
24  
1,2  
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-  
ature air flow, board density, and PCB thermal resistance.  
2. SCMI G-38-87  
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1  
Rev: 1.00b 12/2002  
15/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
AC Test Conditions  
Parameter  
Conditions  
V
– 0.2 V  
Input high level  
Input low level  
DD  
0.2 V  
1 V/ns  
/2  
Input slew rate  
V
Input reference level  
DD  
V
/2  
Output reference level  
Output load  
DDQ  
Fig. 1  
Notes:  
1. Include scope and jig capacitance.  
2. Test conditions as specified with output loading as shown in Fig. 1  
unless otherwise noted.  
3. Device is deselected as defined by the Truth Table.  
Output Load 1  
DQ  
*
50Ω  
30pF  
V
DDQ/2  
* Distributed Test Jig Capacitance  
DC Electrical Characteristics  
Parameter  
Symbol  
Test Conditions  
Min  
Max  
Input Leakage Current  
(except mode pins)  
I
V = 0 to V  
IN DD  
–1 uA  
1 uA  
IL  
V
≥ V ≥ V  
IN  
–1 uA  
–1 uA  
1 uA  
100 uA  
DD  
IH  
IH  
I
I
ZZ Input Current  
FT Input Current  
IN1  
IN2  
0 V ≤ V ≤ V  
IN  
V
≥ V ≥ V  
IN  
–100 uA  
–1 uA  
1 uA  
1 uA  
DD  
IL  
IL  
0 V ≤ V ≤ V  
IN  
I
Output Disable, V  
= 0 to V  
DD  
Output Leakage Current  
Output High Voltage  
Output High Voltage  
Output Low Voltage  
–1 uA  
1.7 V  
2.4 V  
—
1 uA  
—
OL  
OUT  
DDQ  
DDQ  
V
V
I
I
= –8 mA, V  
= –8 mA, V  
= 2.375 V  
= 3.135 V  
OH2  
OH3  
OH  
OH  
—
V
I
= 8 mA  
OL  
0.4 V  
OL  
Rev: 1.00b 12/2002  
16/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Rev: 1.00b 12/2002  
17/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
AC Electrical Characteristics  
-250  
-225  
-200  
-166  
-150  
-133  
Parameter  
Symbol  
Unit  
Min Max Min Max Min Max Min Max Min Max Min Max  
Clock Cycle Time  
Clock to Output Valid  
Clock to Output Invalid  
Clock to Output in Low-Z  
Setup time  
tKC  
tKQ  
4.0  
—
—
2.5  
—
—
—
—
—
5.5  
—
—
—
—
—
—
4.4  
—
—
2.7  
—
—
—
—
—
6.0  
—
—
—
—
—
—
5.0  
—
—
3.0  
—
—
—
—
—
6.5  
—
—
—
—
—
—
6.0  
—
—
3.4  
—
—
—
—
—
7.0  
—
—
—
—
—
—
6.7  
—
—
3.8  
—
—
—
—
—
7.5  
—
—
—
—
—
—
7.5  
—
1.5  
1.5  
1.5  
0.5  
8.5  
—
3.0  
3.0  
1.5  
0.5  
1.7  
2
—
4.0  
—
—
—
—
—
8.5  
—
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tKQX  
1.5  
1.5  
1.2  
0.2  
5.5  
—
3.0  
3.0  
1.5  
0.5  
1.3  
1.5  
1.5  
1.5  
1.3  
0.3  
6.0  
—
3.0  
3.0  
1.5  
0.5  
1.3  
1.5  
1.5  
1.5  
1.4  
0.4  
6.5  
—
3.0  
3.0  
1.5  
0.5  
1.3  
1.5  
1.5  
1.5  
1.5  
0.5  
7.0  
—
3.0  
3.0  
1.5  
0.5  
1.3  
1.5  
1.5  
1.5  
1.5  
0.5  
7.5  
—
3.0  
3.0  
1.5  
0.5  
1.5  
1.7  
Pipeline  
1
tLZ  
tS  
tH  
Hold time  
Clock Cycle Time  
Clock to Output Valid  
Clock to Output Invalid  
Clock to Output in Low-Z  
Setup time  
tKC  
tKQ  
tKQX  
Flow  
Through  
1
tLZ  
tS  
tH  
Hold time  
Clock HIGH Time  
Clock LOW Time  
tKH  
tKL  
Clock to Output in  
High-Z  
1
1.5  
2.5  
1.5  
2.7  
1.5  
3.0  
1.5  
3.0 1.5 3.0 1.5 3.0  
ns  
tHZ  
G to Output Valid  
G to output in Low-Z  
G to output in High-Z  
ZZ setup time  
tOE  
—
0
2.5  
—
2.5  
—
—
—
—
0
2.7  
—
2.7  
—
—
—
—
0
3.2  
—
3.0  
—
—
—
—
0
3.5  
—
3.0  
—
—
—
—
0
3.8  
—
3.0  
—
—
—
—
0
4.0  
—
3.0  
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
1
tOLZ  
tOHZ  
1
—
5
—
5
—
5
—
5
—
5
—
5
2
tZZS  
tZZH  
2
ZZ hold time  
1
1
1
1
1
1
ZZ recovery  
tZZR  
20  
20  
20  
20  
20  
20  
Notes:  
1. These parameters are sampled and are not 100% tested.  
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold  
times as specified above.  
Rev: 1.00b 12/2002  
18/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Rev: 1.00b 12/2002  
19/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Rev: 1.00b 12/2002  
20/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
TQFP Package Drawing  
θ
L
c
L1  
Symbol  
Description  
Standoff  
Min. Nom. Max  
A1  
A2  
b
0.05  
1.35  
0.20  
0.09  
0.10  
1.40  
0.30  
—
0.15  
1.45  
0.40  
0.20  
20.1  
20.1  
16.1  
14.1  
—
Body Thickness  
Lead Width  
c
Lead Thickness  
D
Terminal Dimension 21.9  
Package Body 19.9  
Terminal Dimension 15.9  
22.0  
20.0  
16.0  
14.0  
0.65  
0.60  
1.00  
—
e
D1  
E
b
E1  
e
Package Body  
Lead Pitch  
13.9  
—
L
Foot Length  
Lead Length  
Coplanarity  
Lead Angle  
0.45  
—
0.75  
—
L1  
Y
A1  
A2  
E1  
E
—
0.10  
7°  
θ
0°  
—
Notes:  
1. All dimensions are in millimeters (mm).  
2. Package width and length do not include mold protrusion.  
BPR 1999.05.18  
Rev: 1.00b 12/2002  
21/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
Ordering Information—GSI NBT Synchronous SRAM  
2
Speed  
3
1
Org  
Type  
Package  
Status  
T
Part Number  
A
(MHz/ns)  
512K x 18  
512K x 18  
512K x 18  
512K x 18  
512K x 18  
512K x 18  
256K x 36  
256K x 36  
256K x 36  
256K x 36  
256K x 36  
256K x 36  
512K x 18  
512K x 18  
512K x 18  
512K x 18  
512K x 18  
512K x 18  
256K x 36  
256K x 36  
256K x 36  
256K x 36  
256K x 36  
256K x 36  
Notes:  
GS880Z18BT-250  
GS880Z18BT-225  
GS880Z18BT-200  
GS880Z18BT-166  
GS880Z18BT-150  
GS880Z18BT-133  
GS880Z36BT-250  
GS880Z36BT-225  
GS880Z36BT-200  
GS880Z36BT-166  
GS880Z36BT-150  
GS880Z36BT-133  
GS880Z18BT-250I  
GS880Z18BT-225I  
GS880Z18BT-200I  
GS880Z18BT-166I  
GS880Z18BT-150I  
GS880Z18BT-133I  
GS880Z36BT-250I  
GS880Z36BT-225I  
GS880Z36BT-200I  
GS880Z36BT-166I  
GS880Z36BT-150I  
GS880Z36BT-133I  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
NBT Pipeline/Flow Through  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
TQFP  
250/5.5  
225/6  
C
C
C
C
C
C
C
C
C
C
C
C
I
200/6.5  
166/7  
150/7.5  
133/8.5  
250/5.5  
225/6  
200/6.5  
166/7  
150/7.5  
133/8.5  
250/5.5  
225/6  
I
200/6.5  
166/7  
I
I
150/7.5  
133/8.5  
250/5.5  
225/6  
I
I
I
I
200/6.5  
166/7  
I
I
150/7.5  
133/8.5  
I
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: Gs880Z18BT-150IT.  
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each  
device is Pipeline/Flow Through mode-selectable by the user.  
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.  
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are  
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings  
Rev: 1.00b 12/2002  
22/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS880Z18/36BT-250/225/200/166/150/133  
9Mb Sync SRAM Data Sheet Revision History  
DS/DateRev. Code: Old;  
New  
Types of Changes  
Format or Content  
Page;Revisions;Reason  
• Creation of new datasheet  
880Z18B_r1  
Rev: 1.00b 12/2002  
23/23  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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