S8866-64 [HAMAMATSU]
Analog Circuit;
| 型号： | S8866-64 |
| 厂家： | 
HAMAMATSU CORPORATION |
| 描述： | Analog Circuit |
| 文件： | 总10页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Photodiode arrays with ampli¿er
S8866-64/-128
Photodiode array combined with signal
processing IC
The S8866-64 and S8866-128 are Si photodiode arrays combined with a signal processing IC chip. The signal processing IC
chip is formed by CMOS process and incorporates a timing generator, shift register, charge ampli¿er array, clamp circuit and
hold circuit, making the external circuit con¿guration simple. For X-ray detection applications, types (S8866-64G-02, S8866-
128G-02) with phosphor sheet af¿xed on the photosensitive area are also available.
Features
Applications
Large element pitch: 2 types available
S8866-64: 1.6 mm pitch × 64 ch
S8866-128: 0.8 mm pitch × 128 ch
Long and narrow line sensors
5 V power supply operation
Simultaneous integration by using a charge ampli¿er array
Sequential readout with a shift register
(Data rate: 500 kHz max.)
Low dark current due to zero-bias photodiode operation
Integrated clamp circuit allows low noise and wide dynamic range
Integrated timing generator allows operation at two
different pulse timings
Structure
Parameter
Element pitch
Element diffusion width
Element height
Number of elements
Effective photosensitive area length
Board material
Symbol*1
S8866-64
1.6
1.5
1.6
64
102.4
S8866-128
Unit
mm
mm
mm
-
P
W
H
-
-
-
0.8
0.7
0.8
128
102.4
mm
-
Ceramic
*1: Refer to following ¿gure.
Enlarged drawing of photosensitive area
Photodiode
W
P
KMPDC0072EA
1
www.hamamatsu.com
Photodiode arrays with ampli¿er
S8866-64/-128
Absolute maximum ratings
Parameter
Supply voltage
Reference voltage
Symbol
Vdd
Vref
Vpd
Vgain
Vms
V(CLK)
V(RESET)
V(EXTSP)
Topr
Value
Unit
V
V
V
V
V
V
V
V
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-5 to +60
-10 to +70
Photodiode voltage
Gain selection terminal voltage
Master/slave selection voltage
Clock pulse voltage
Reset pulse voltage
External start pulse voltage
Operating temperature*2
Storage temperature
°C
°C
Tstg
*2: No condensation
Recommended terminal voltage
Parameter
Supply voltage
Symbol
Vdd
Min.
4.75
Typ.
5
Max.
5.25
Unit
V
Reference voltage
Photodiode voltage
High gain
Gain selection terminal voltage
Low gain
High level*3
Master/slave selection voltage
Low level*4
Vref
Vpd
4
-
4.5
Vref
Vdd
-
Vdd
-
4.6
-
Vdd + 0.25
0.4
Vdd + 0.25
0.4
V
V
V
V
V
V
Vdd - 0.25
Vgain
Vms
0
Vdd - 0.25
0
High level
Low level
High level
Low level
3.3
0
3.3
Vdd
-
Vdd
-
Vdd
-
Vdd + 0.25
0.4
Vdd + 0.25
0.4
Vdd + 0.25
0.4
V
V
V
V
V
V
Clock pulse voltage
V(CLK)
V(RESET)
V(EXTSP)
Reset pulse voltage
0
Vdd - 0.25
0
High level
External start pulse voltage
Low level
*3: Parallel
*4: Serial at 2nd or later stages
Electrical characteristics [Ta=25 °C, Vdd=5 V, V(CLK)=V(RESET)=5 V]
S8866-64
S8866-128
Parameter
Clock pulse frequency*5
Line rate
Output impedance
Power consumption
Symbol
Unit
Min.
40
-
-
-
Typ.
-
7800
3
100
0.5
1
Max.
2000
Min.
40
-
-
-
Typ.
-
3900
3
180
0.5
1
Max.
2000
f(CLK)
LR
Zo
kHz
lines/s
kΩ
-
-
-
-
-
-
-
-
-
-
P
mW
High gain
Low gain
-
-
-
-
Charge amp feedback capacitance
Cf
pF
*5: Video data rate is 1/4 of clock pulse frequency f(CLK).
2
Photodiode arrays with ampli¿er
S8866-64/-128
Electrical and optical characteristics [Ta=25 °C, Vdd=5 V, V (CLK)=V (RESET)=5 V, Vgain=5 V (High gain), 0 V (Low gain)]
S8866-64
Typ.
300 to 1000
720
S8866-128
Typ.
300 to 1000
720
Parameter
Spectral response range
Peak sensitivity wavelength
Symbol
Unit
Min.
Max.
Min.
Max.
λ
λp
nm
nm
-
-
-
3
-
-
-
0.2
0.1
-
0.25
0.5
-
-
-
-
3
-
-
-
0.2
0.1
-
1.0
2.0
-
High gain
Low gain
0.01
0.005
3.5
0.2
0.4
18000
9000
-
2.0
1.1
0.01
0.005
3.5
0.8
1.6
4400
2200
-
1.3
0.7
Dark output voltage*6
Saturation output voltage
Saturation exposure*7
Vd
mV
V
Vsat
Esat
High gain
Low gain
High gain
Low gain
mlx · s
14400
7200
3520
1760
-
-
-
-
Photo sensitivity
S
PRNU
N
V/lx · s
%
-
-
Photo response non-uniformity*8
-
-
-
-
±10
3.0
1.7
-
±10
2.0
1.1
-
High gain
Low gain
Noise*9
mVrms
V
Output offset voltage*10
Vos
Vref
Vref
*6: Integration time ts=1 ms
*7: Measured with a 2856 K tungsten lamp.
*8: When the photodiode array is exposed to uniform light which is 50% of the saturation exposure, the photo response non-uniformity
(PRNU) is de¿ned as follows:
PRNU = ΔX/X × 100 [%]
X: average output of all elements, ΔX: difference between X and the maximum or minimum output, whichever is larger.
*9: Measured with a video data rate of 50 kHz and ts=1 ms in dark state.
*10: Video output is negative-going output with respect to the output offset voltage.
Output waveform of one element
Dark state
Saturation
output voltage
Vsat=3.5 V typ.
Output offset
voltage
Vref=4.5 V typ.
Saturation
state
1 V/div.
1 V typ.
GND
GND
GND
10 V/div.
Trigger
CLK
200 ns/div.
3
Photodiode arrays with ampli¿er
S8866-64/-128
Block diagram
EXTSP
4
Vms
5
Vdd
6
GND
7
1
2
RESET
CLK
Timing generator
3
TRIG
Shift register
Hold circuit
8
9
EOS
Video
10
11
Vref
Charge amp array
Vgain
Vpd 12
1
2
3
4
5
N-1
N
Photodiode array
KMPDC0153EA
4
Photodiode arrays with ampli¿er
S8866-64/-128
Spectral response (measurement example)
Output offset voltage vs. ambient temperature
(measurement example)
(Ta=25 °C)
0.5
4.505
4.504
4.503
4.502
4.501
4.500
4.499
4.498
4.497
0.4
0.3
0.2
0.1
0
4.496
4.495
200
400
600
800
1000
1200
0
10
20
30
40
50
60
Ambient temperature (°C)
Wavelength (nm)
KMPDB0275EA
KMPDB0288EA
Dark output voltage vs. ambient temperature
(measurement example)
(Ts=1000 ms)
1
0.1
0.01
0.001
0
10
20
30
40
50
60
Ambient temperature (°C)
KMPDB0289EA
5
Photodiode arrays with ampli¿er
S8866-64/-128
Timing chart
S8866-64
1 2 3
4 5 14151617181920
1 2 3
20 clocks
CLK
tpw(RESET1)
RESET
tpw(RESET2)
8 clocks
8 clocks
Integration time
Video output
period
Video
1
2
n-1
n
Trig
EOS
tf(CLK)
tr(CLK)
t2
tpw(CLK1)
tpw(RESET1)
tpw(RESET2)
t1
tf(RESET)
tr(RESET)
KMPDC0278EA
Parameter
Symbol
tpw(CLK)
Min.
500
0
21
20
0
-20
-20
Typ.
-
20
-
-
20
0
Max.
25000
30
-
-
30
20
20
Unit
ns
ns
CLK
CLK
ns
Clock pulse width
Clock pulse rise/fall times
Reset pulse width 1
tr(CLK), tf(CLK)
tpw(RESET1)
tpw(RESET2)
tr(RESET), tf(RESET)
t1
Reset pulse width 2
Reset pulse rise/fall times
Clock pulse-reset pulse timing 1
Clock pulse-reset pulse timing 2
ns
ns
t2
0
1. The internal timing circuit starts operation at the falling edge of CLK immediately after a RESET pulse goes Low.
2. When the falling edge of each CLK is counted as "1 clock", the video signal of the 1st channel appears between "18.5 clocks and 20
clocks". Subsequent video signals appear every 4 clocks.
3. To obtain video signals, extend the High period 3 clocks from the falling edge of CLK immediately after the RESET pulse goes Low,
to a 20 clock period.
4. The trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. The rising edge of each trigger
pulse is the recommended timing for data acquisition.
5. Signal charge integration time equals the High period of a RESET pulse. However, the charge integration does not start at the rise
of a RESET pulse but starts at the 8th clock after the rise of the RESET pulse and ends at the 8th clock after the fall of the RESET
pulse. After the RESET pulse next changes from High to Low, signals integrated within this period are sequentially read out as time-
series signals by the shift register operation. The rise and fall of a RESET pulse must be synchronized with the rise of a CLK pulse,
but the rise of a RESET pulse must be set outside the video output period. One cycle of RESET pulses cannot be set shorter than
the time equal to "36.5 + 4 × N (number of elements)" clocks.
6. The video signal after an EOS signal output becomes a high impedance state, and the video output will be inde¿nite.
6
Photodiode arrays with ampli¿er
S8866-64/-128
S8866-128
1 2 3 4 5 14151617181920
1 2 3
CLK
tpw(RESET1)
8 clocks
RESET
tpw(RESET2)
n-1
8 clocks
Integration time
Video output
period
Video
1
2
n
Trig
EOS
tf(CLK)
tr(CLK)
t2
tpw(CLK)
tpw(RESET1)
tpw(RESET2)
t1
tf(RESET)
tr(RESET)
KMPDC0289EA
Parameter
Symbol
tpw(CLK)
Min.
500
0
21
20
0
-20
-20
Typ.
-
20
-
-
20
0
Max.
25000
30
-
-
30
20
Unit
ns
ns
CLK
CLK
ns
Clock pulse width
Clock pulse rise/fall times
Reset pulse width 1
tr(CLK), tf(CLK)
tpw(RESET1)
tpw(RESET2)
tr(RESET), tf(RESET)
t1
Reset pulse width 2
Reset pulse rise/fall times
Clock pulse-reset pulse timing 1
Clock pulse-reset pulse timing 2
ns
ns
t2
0
20
1. The internal timing circuit starts operation at the falling edge of CLK immediately after a RESET pulse goes Low.
2. When the falling edge of each CLK is counted as "1 clock", the video signal of the 1st channel appears between "18.5 clocks and 20
clocks". Subsequent video signals appear every 4 clocks.
3. The trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. The rising edge of each trigger
pulse is the recommended timing for data acquisition.
4. Signal charge integration time equals the High period of a RESET pulse. However, the charge integration does not start at the rise
of a RESET pulse but starts at the 8th clock after the rise of the RESET pulse and ends at the 8th clock after the fall of the RESET
pulse.
After the RESET pulse next changes from High to Low, signals integrated within this period are sequentially read out as
time-series signals by the shift register operation. The rise and fall of a RESET pulse must be synchronized with the rise of a CLK
pulse, but the rise of a RESET pulse must be set outside the video output period. One cycle of RESET pulses cannot be set shorter
than the time equal to "16.5 + 4 × N (number of elements)" clocks.
5. The video signal after an EOS signal output becomes a high impedance state, and the video output will be inde¿nite.
7
Photodiode arrays with ampli¿er
S8866-64/-128
Dimensional outline (unit: mm)
110 1.1
25.4
P2.54 × 5 = 12.7
P2.54 × 5 = 12.7
12
Silicon resin
1
102.4
Type no.
A
Photosensitive
area
S8866-64 3.2
S8866-128 3.0
Direction of scan
Signal processing
IC chip
Photodiode 1 ch
0.5
0.25
* Length from the bottom of the board to the center of photosensitive area
Board: Ceramic
KMPDA0225EB
Pin connections
Pin no.
Symbol
RESET
CLK
Name
Note
1
2
Reset pulse
Clock pulse
Pulse input
Pulse input
3
4
5
6
Trig
EXTSP
Vms
Trigger pulse
External start pulse
Master/slave selection supply voltage
Supply voltage
Positive-going pulse output
Pulse input
Voltage input
Vdd
Voltage input
7
8
GND
EOS
Ground
End of scan
Negative-going pulse output
Negative-going output with respect to Vref
Voltage input
Voltage input
Voltage input
9
Video
Vref
Vgain
Vpd
Video output
10
11
12
Reference voltage
Gain selection terminal voltage
Photodiode voltage
Gain selection terminal voltage setting
Vdd: High gain (Cf=0.5 pF) GND: Low gain (Cf=1 pF)
8
Photodiode arrays with ampli¿er
S8866-64/-128
Setting for each readout method
Set to A in the table below in most cases.
To serially read out signals from two or more sensors linearly connected, set the 1st sensor to A and the 2nd or later sensors to B.
The CLK and RESET pulses should be shared with each sensor and the video output terminal of each sensor connected together.
Setting
Readout method
All stages of parallel readout, serial readout at 1st sensor
Serial readout at 2nd and later sensors
Vms
Vdd
GND
EXTSP
Vdd
A
B
Preceding sensor EOS should be input
[Figure 1] Connection example (parallel readout)
12 Vpd
11 Vgain
10 Vref
Vgain
+4.5 V
9
8
7
6
5
4
3
2
1
Video
EOS
EOS
GND
Vdd
10 μF
0.1 μF
+5 V
Vms
EXTSP
Trig
Trig
CLK
CLK
RESET
RESET
-
Video
+
High impedance amplifier
KMPDC0288EA
Readout circuit
Check that pulse signals meet the required pulse conditions before supplying them to the input terminals.
Video output should be ampli¿ed by an operational ampli¿er that is connected close to the sensor.
9
Photodiode arrays with ampli¿er
S8866-64/-128
Precautions for use
(1) The signal processing IC chip is protected against static electricity. However, in order to prevent possible damage to the IC chip,
take electrostatic countermeasures such as grounding yourself, as well as workbench and tools. Also protect the IC chip from surge
voltages from peripheral equipment.
(2) Gold wires for wire bonding are very thin, so they easily break if subjected to mechanical stress. The signal processing IC chip, wire
bonding section and photodiode array chip are covered with resin for protection. However, never touch these portions. Excessive
force, if applied, may break the wires or cause malfunction.
Blow air to remove dust or debris if it gets on the protective resin. Never wash them with solvent.
Signals may not be obtained if dust or debris is left or a scratch is made on the protective resin, or the signal processing IC chip or
photodiode array chip is nicked.
(3) The photodiode array characteristics may deteriorate when operated at high humidity, so put it in a hermetically sealed enclosure or case.
When installing the photodiode array on a board, be careful not to cause the board to warp.
Information described in this material is current as of May, 2011. Product specifications are subject to change without prior notice due to improvements or
other reasons. Before assembly into final products, please contact us for the delivery specification sheet to check the latest information.
The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that
one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product
use.
Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission.
www.hamamatsu.com
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8
France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1 int. 6, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
10
Cat. No. KMPD1104E02 May 2011 DN
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