HSD16M64F8VA-F13 [HANBIT]
Synchronous DRAM Module, 128Mbyte ( 16M x 64-Bit ) SMM based on 16Mx8 4Banks, 4K Ref., 3.3V; 同步DRAM模块， 128Mbyte （ 16M ×64位）的基础上16Mx8 4Banks ， 4K参考SMM 。 ， 3.3V
| 型号： | HSD16M64F8VA-F13 |
| 厂家： | 
HANBIT ELECTRONICS CO.,LTD |
| 描述： | Synchronous DRAM Module, 128Mbyte ( 16M x 64-Bit ) SMM based on 16Mx8 4Banks, 4K Ref., 3.3V |
| 文件： | 总11页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HANBit
HSD16M64F8V/VA
Synchronous DRAM Module, 128Mbyte ( 16M x 64-Bit ) SMM based on 16Mx8
4Banks, 4K Ref., 3.3V
Part No. HSD16M64F8V/VA
GENERAL DESCRIPTION
The HSD16M64F8V/VA is a 16M x 64 bit Synchronous Dynamic RAM high density memory module. The module
consists of eight CMOS 4M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages is mounted on a 120-pin,
double-sided, FR-4-printed circuit board., Two 0.1uF decoupling capacitors are mounted on the printed circuit board in
parallel for each SDRAM. The HSD16M64F8V/VA is a SMM (Stackable Memory Module) designed and is intended for
mounting into two 60-pin connector sockets. Synchronous design allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the
same device to be useful for a variety of high bandwidth, high performance memory system applications All module
components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
PIN ASSIGNMENT
FEATURES
• Part Identification
60-PIN P1 Connector
60-PIN P2 Connector
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
HSD16M64F8V :
1
2
Vcc
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Vcc
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Vss
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Vss
1
Vss
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
Vss
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Vcc
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Vcc
Stacking Height ( T = 11.3mm )
HSD16M64F8VA :
2
3
3
4
4
Stacking Height ( T = 7.3mm )
5
5
6
6
7
7
• Burst mode operation
8
8
• Auto & self refresh capability (4K Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge
of the system clock
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vcc
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Vss
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Vss
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Vcc
• 120pin-SMM type FR4-PCB design
• The used device is 16Mx8bit SRAM
• Pin assignment is compatible with
- HSD8M64F8V
DQM4
DQM5
NC
DQM0
DQM1
/WE
DQM2
DQM3
NC
DQM6
DQM7
NC(A12)
A11
CKE0
CKE1
Vcc
CLK0
CLK1
Vss
BA0
BA1
A9
- HSD32M64F8V
A10/AP
A0
A8
NC
/CAS
/RAS
/CE0
NC
A7
NC
A1
A6
/CE2
NC
A2
A5
A3
A4
Vcc
Vss
Vss
Vcc
Stackable Memory Module TOP VIEW
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HANBit
HSD16M64F8V/VA
FUNCTIONAL BLOCK DIAGRAM
DQ0-63
CLK0
CKE
CAS
CLK
CKE0
/CAS
U1
DQ0-7
/RAS
/CE0
DQM0
RAS
CE
DQM0
WE A0-A11
BA0-1
CLK1
CKE
CAS
CLK
DQ32-39
U2
RAS
CE
DQM4
BA0-1
DQM4
/CE2
WE A0-A11
CKE
CAS
CLK
DQ16-23
U3
RAS
CE
DQM2
BA0-1
DQM2
WE A0-A11
CKE
CAS
CLK
DQ48-55
U4
RAS
CE
DQM6
BA0-1
DQM6
DQM1
WE A0-A11
CKE
CAS
CLK
DQ8-15
U5
RAS
CE
DQM1
WE A0-A11 BA0-1
CKE
CAS
CLK
DQ40-47
DQM5
U6
RAS
CE
DQM5
DQM3
WE A0-A11
BA0-1
CKE
CAS
CLK
DQ24-31
U7
RAS
CE
DQM3
WE A0-A11 BA0-1
CKE
CAS
CLK
DQ56-63
DQM7
U8
RAS
CE
DQM7
WE A0-A11
BA0-1
/WE
A0 - A11
BA0-1
Vcc
Vss
Two 0.1uF Capacitors
per each SDRAM
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HSD16M64F8V/VA
PIN FUNCTION DESCRIPTION
Pin
Name
System clock
Chip enable
Input Function
CLK
/CE
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
A0 ~ A11
BA0 ~ BA1
/RAS
Address
Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
/CAS
Column
address Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
strobe
/WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data
input/output Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
mask
DQ0 ~ 63
Vcc/Vss
Data input/output
Power
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
SYMBOL
VIN ,OUT
Vcc
RATING
-1V to 4.6V
-1V to 4.6V
8W
PD
o
o
Storage Temperature
TSTG
-55 C to 150 C
Short Circuit Output Current
IOS
400mA
Notes :
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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HSD16M64F8V/VA
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) )
PARAMETER
Supply Voltage
SYMBOL
Vcc
VIH
MIN
3.0
2.0
-0.3
2.4
-
TYP.
MAX
3.6
UNIT
V
NOTE
3.3
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input leakage current
3.0
Vcc+0.3
0.8
V
1
VIL
0
-
V
2
VOH
VOL
-
V
IOH = -2mA
IOL = 2mA
3
-
0.4
V
I LI
-10
-
10
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
DESCRIPTION
SYMBOL
CCLK
MIN
20
MAX
32
UNITS
Clock
pF
pF
pF
pF
Address
CADD
20
40
/RAS, /CAS, /WE, /CS, CKE, DQM
DQ (DQ0 ~ DQ15)
C IN
20
40
COUT
32
52
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HSD16M64F8V/VA
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
TEST
CONDITION
VERSION
PARAMETER
SYMBOL
UNIT NOTE
-13
-12
-10
-10L
Burst length = 1
Operating current
ICC1
tRC ³ tRC(min)
960 960
880
880
mA
1
(One bank active)
IO = 0mA
CKE £ VIL(max)
ICC2
P
8
8
mA
mA
Precharge standby current in
power-down mode
tCC=10ns
CKE & CLK £ VIL(max)
tCC=¥
ICC2PS
CKE ³ VIH(min)
/CS ³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
CKE ³ VIH(min)
ICC2
N
160
56
Precharge standby current in
non power-down mode
mA
mA
mA
ICC2NS
CLK £ VIL(max), tCC=¥
Input signals are stable
ICC3
P
CKE £ VIL(max), tCC=10ns
25
25
Active standby current in
power-down mode
CKE&CLK £ VIL(max)
tCC=¥
ICC3PS
CKE³ VIH(min),
/CS³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
CKE³ VIH(min)
ICC3
N
240
160
Active standby current in
non power-down mode
(One bank active)
ICC3NS
CLK £VIL(max), tCC=¥
Input signals are stable
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
1200 1160 1000 1000
mA
1
2
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
tRC ³ tRC(min)
1760 1760 1680 1680
mA
mA
mA
C
12
Self refresh current
ICC6
CKE £ 0.2V
L
6.4
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
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HANBit
HSD16M64F8V/VA
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)
PARAMETER
Value
2.4/0.4
1.4
UNIT
V
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
+3.3V
V =1.4V
tt
1200W
50W
DOUT
DOUT
Z0=50W
870W
50pF*
50pF
V
V
(DC) = 2.4V, I = -2mA
OH
OH
(DC) = 0.4V, I = 2mA
OL
OL
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
UNIT
NOTE
-13
15
20
20
45
-12
-10
20
20
20
50
-10L
20
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRP(min)
16
20
20
48
ns
ns
ns
ns
1
1
1
1
20
Row precharge time
tRP(min)
20
tRAS(min)
tRAS(max)
50
Row active time
100
2
ns
Row cycle time
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
65
68
70
70
ns
CLK
-
1
2.5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
2 CLK + 20 ns
1
1
1
2
CLK
CLK
CLK
2
2
Col. address to col. address delay
3
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
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HSD16M64F8V/VA
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
(Recommand : tRDL=2CLK and tDAL=2CLK & 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-13
-12
MAX MIN
-10
MAX MIN
-10L
MAX
PARAMETER
SYMBOL
UNIT
NOTE
MIN MAX MIN
CLK cycle time CAS
7.5
-
8
-
10
10
10
12
latency=3
tCC
1000
1000
1000
1000
ns
1
CAS
latency=2
CAS
CLK to valid
output delay
5.4
-
6
-
6
6
6
7
latency=3
CAS
tSAC
ns
ns
1,2
latency=2
CAS
Output data
hold time
2.7
-
3
-
3
3
3
3
latency=3
CAS
tOH
2
latency=2
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
3
3
2
1
1
3
3
2
1
1
3
3
2
1
1
ns
ns
ns
ns
ns
3
3
3
3
3
tSS
tSH
tSLZ
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS
5.4
-
6
-
6
6
6
7
ns
ns
2
latency=3
CAS
tSHZ
latency=2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to
the parameter.
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HANBit
HSD16M64F8V/VA
SIMPLIFIED TRUTH TABLE
/R
A
S
/C
A
S
D
Q
M
CKE
CKE
n
/C
S
/W
E
BA
0,1
A10/
AP
A11,A12,
A9~A0
n-1
COMMAND
NOTE
Register
Refresh
Mode register set
Auto refresh
H
X
H
L
L
L
L
L
L
X
OP code
X
1,2
3
H
L
L
H
X
Entry
3
Self
refres
h
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
X
X
X
X
3
Bank active & row addr.
H
V
V
Row address
Auto
precharge
Read &
column
address
L
Column
Address
(A0 ~ A9)
4
disable
Auto
H
H
X
L
H
L
H
X
precharge
precharge
precharge
H
4,5
disable
Column
Address
(A0 ~ A9)
Auto
Write &
column
address
L
4
disable
X
L
H
L
L
X
V
Auto
H
4,5
6
disable
Burst Stop
H
H
X
X
L
L
L
L
H
H
L
L
X
X
X
Precharg Bank selection
V
X
L
X
e
All banks
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
X
H
L
Entry
H
Precharge power
down mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
X
7
H
L
X
H
X
X
H
No operation command
H
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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HANBit
HSD16M64F8V/VA
TIMING DIAGRAMS
Please refer to timing diagram chart (II)
PACKAGING INFORMATION
Unit : mm
HSD16M64F8V
82.68.
5.00
5.00
0.90
0.90
31
1
1
31
30.00
30
P2
30
60
P1
60
0.90
0.90
Bottom View
1.30
PM
PB
9.00
T = 11.3
8.00
4.6
MAIN BOARD
7.75
Connector Configuration
- Module PCB Bottom (PM) : 177986-2, 0.8mm Free Height Plugs, 60pins
- Main Board top (PB) : 5-179180-2,0.8mm Free Height Receptacles , 60pins
HSD16M64F8VA
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HANBit
HSD16M64F8V/VA
82.68.
5.00
5.00
0.90
0.90
31
1
1
31
30.00
30
P2
30
60
P1
60
0.90
0.90
Bottom View
1.30
PM
PB
T = 7.3
5.0
4.0
4.60
MAIN BOARD
3.75
Connector Configuration
- Module PCB Bottom (PM) : 177984-2, 0.8mm Free Height Plugs, 60pins
- Main Board top (PB) : 177983-2,0.8mm Free Height Receptacles , 60pins
ORDERING INFORMATION
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HANBit
HSD16M64F8V/VA
Part Number
Density
Org.
Package
Ref.
Vcc
Feature
MAX.frq
120 Pin
SMM
133MHz
(CL=3)
HSD16M64F8V-13
HSD16M64F8V-F13
HSD16M64F8V-12
HSD16M64F8V-F12
HSD16M64F8V-10
HSD16M64F8V-F10
HSD16M64F8VA-13
HSD16M64F8VA-F13
HSD16M64F8VA-12
HSD16M64F8VA-F12
HSD16M64F8VA-10
HSD16M64F8VA-F10
128MByte
128MByte
128MByte
128MByte
128MByte
128MByte
128MByte
128MByte
128MByte
128MByte
128MByte
128MByte
16Mx 64
16Mx 64
16Mx 64
16Mx 64
16Mx 64
16Mx 64
16Mx 64
16Mx 64
16Mx 64
16Mx 64
16Mx 64
16Mx 64
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
120 Pin
SMM
Low
133MHz
(CL=3)
Power
120 Pin
SMM
125MHz
(CL=3)
120 Pin
SMM
Low
125MHz
(CL=3)
Power
120 Pin
SMM
100MHz
(CL=2)
120 Pin
SMM
Low
100MHz
(CL=2)
Power
120 Pin
SMM
133MHz
(CL=3)
120 Pin
SMM
Low
133MHz
(CL=3)
Power
120 Pin
SMM
125MHz
(CL=3)
120 Pin
SMM
Low
125MHz
(CL=3)
Power
120 Pin
SMM
100MHz
(CL=2)
120 Pin
SMM
Low
100MHz
(CL=2)
Power
* F means Auto & Self refresh with Low-Power (3.3V)
* HSD16M64F8V
* HSD16M64F8VA
:
T = 11.3mm
T = 7.3mm
:
URL: www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
11
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