HSD16M72D18A-10L [HANBIT]

Synchronous DRAM Module 128Mbyte (16Mx72bit), DIMM with ECC based on 8Mx8, 4Banks, 4K Ref., 3.3V; 同步DRAM模组128Mbyte ( 16Mx72bit ) ,与DIMM ECC基于8Mx8 , 4Banks , 4K参考, 3.3V
HSD16M72D18A-10L
型号: HSD16M72D18A-10L
厂家: HANBIT ELECTRONICS CO.,LTD    HANBIT ELECTRONICS CO.,LTD
描述:

Synchronous DRAM Module 128Mbyte (16Mx72bit), DIMM with ECC based on 8Mx8, 4Banks, 4K Ref., 3.3V
同步DRAM模组128Mbyte ( 16Mx72bit ) ,与DIMM ECC基于8Mx8 , 4Banks , 4K参考, 3.3V

动态存储器
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HANBit  
HSD16M72D18A  
Synchronous DRAM Module 128Mbyte (16Mx72bit), DIMM with ECC based on  
8Mx8, 4Banks, 4K Ref., 3.3V  
Part No. HSD16M72D18A  
GENERAL DESCRIPTION  
The HSD16M72D18A is a 16M x 72 bit Synchronous Dynamic RAM high-density memory module. The module consists  
of eighteen CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin  
TSSOP package on a 168-pin glass-epoxy. Two 0.33uF-decoupling capacitors are mounted on the printed circuit board in  
parallel for each SDRAM. The HSD16M72D18A is a DIMM (Dual in line Memory Module) and is intended for mounting  
into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O  
transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same  
device to be useful for a variety of high bandwidth, high performance memory system applications All module  
components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.  
FEATURES  
Part Identification  
HSD16M72D18A-F/10L : 100MHz (CL=3)  
HSD16M72D18A-F/10 : 100MHz (CL=2)  
HSD16M72D18A-F/12 : 125MHz (CL=3)  
HSD16M72D18A-F/13 : 133MHz (CL=3)  
HSD16M72D18A-F/13H : 133MHz (CL=2)  
F means Auto & Self refresh with Low-Power (3.3V)  
Burst mode operation  
Auto & self refresh capability (4096 Cycles/64ms)  
LVTTL compatible inputs and outputs  
Single 3.3V ±0.3V power supply  
MRS cycle with address key programs  
- Latency (Access from column address)  
- Burst length (1, 2, 4, 8 & Full page)  
- Data scramble (Sequential & Interleave)  
All inputs are sampled at the positive going edge of the system clock  
The used device is 8M x 8bit , 4Banks SDRAM  
URL: www.hbe.co.kr  
REV 1.0 (August.2002)  
1
HANBit Electronics Co.,Ltd.  
HANBit  
HSD16M72D18A  
PIN ASSIGNMENT  
PIN Symbol PIN  
Symbol  
PIN  
Symbol  
PIN  
Symbol  
PIN  
Symbol  
PIN  
Symbol  
1
Vss  
DQ0  
DQ1  
DQ2  
DQ3  
Vcc  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
DQM1  
/CE0  
NC  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
DQ18  
DQ19  
Vcc  
85  
86  
Vss  
DQ32  
DQ33  
DQ34  
DQ35  
Vcc  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
DQM5  
/CE1  
/RAS  
Vss  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
DQ50  
DQ51  
Vcc  
2
3
87  
4
Vss  
DQ20  
NC  
88  
DQ52  
NC  
5
A0  
89  
A1  
6
A2  
NC  
90  
A3  
NC  
7
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
Vss  
A4  
CKE1  
Vss  
91  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
Vss  
A5  
NC  
8
A6  
92  
A7  
Vss  
9
A8  
DQ21  
DQ22  
DQ23  
Vss  
93  
A9  
DQ53  
DQ54  
DQ55  
Vss  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
A10  
BA1  
Vcc  
94  
BA0  
A11  
Vcc  
95  
96  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
Vcc  
Vcc  
DQ24  
DQ25  
DQ26  
DQ27  
Vcc  
97  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
Vcc  
CLK1  
NC  
DQ56  
DQ57  
DQ58  
DQ59  
Vcc  
CLK0  
Vss  
98  
99  
Vss  
NC  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
CKE0  
/CE3  
DQM6  
DQM7  
NC  
/CE2  
DQM2  
DQM3  
NC  
DQ28  
DQ29  
DQ30  
DQ31  
Vss  
DQ60  
DQ61  
DQ62  
DQ63  
Vss  
DQ14  
DQ15  
CB0  
CB1  
Vss  
DQ46  
DQ47  
CB4  
Vcc  
Vcc  
NC  
CB5  
NC  
NC  
CLK2  
NC  
Vss  
NC  
CLK3  
NC  
NC  
CB2  
CB3  
Vss  
NC  
CB6  
CB7  
Vss  
NC  
WP  
NC  
SA0  
Vcc  
SDA  
SCL  
Vcc  
SA1  
/WE  
DQM0  
DQ16  
DQ17  
/CAS  
DQM4  
DQ48  
DQ49  
SA2  
Vcc  
Vcc  
* These pins are not used in this module ** These pins should be NC in the system which does not support SPD  
*Pin Names  
VREF : Power supply for reference  
CB0~7 : Check bit (Data in/data-out)  
CLK0 ~ CLK3 : Clock input  
CKE0 ~ CKE1 : Colck enable input  
/CE0 ~ /CE3 : Chip enable input  
Vcc : Power supply  
Vss : Ground  
SDA : Serial data I/O  
SCL : Serial clock  
SA0 ~ 2 : Address in EEPROM  
URL: www.hbe.co.kr  
REV 1.0 (August.2002)  
2
HANBit Electronics Co.,Ltd.  
HANBit  
HSD16M72D18A  
FUNCTIONAL BLOCK DIAGRAM  
URL: www.hbe.co.kr  
REV 1.0 (August.2002)  
3
HANBit Electronics Co.,Ltd.  
HANBit  
HSD16M72D18A  
PIN FUNCTION DESCRIPTION  
Pin  
Name  
System clock  
Chip enable  
Input Function  
CLK  
/CE  
Active on the positive going edge to sample all inputs.  
Disables or enables device operation by masking or enabling all inputs except  
CLK, CKE and DQM  
CKE  
Clock enable  
Masks system clock to freeze operation from the next clock cycle.  
CKE should be enabled at least one cycle prior to new command.  
Disable input buffers for power down in standby.  
CKE should be enabled 1CLK+tSS prior to valid command.  
Row/column addresses are multiplexed on the same pins.  
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8  
A0 ~ A11  
BA0 ~ BA1  
/RAS  
Address  
Bank select address Selects bank to be activated during row address latch time.  
Selects bank for read/write during column address latch time.  
Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.  
Enables row access & precharge.  
/CAS  
Column  
address Latches column addresses on the positive going edge of the CLK with CAS low.  
Enables column access.  
strobe  
/WE  
Write enable  
Enables write operation and row precharge.  
Latches data in starting from CAS, WE active.  
DQM0 ~ 7  
Data  
input/output Makes data output Hi-Z, tSHZ after the clock and masks the output.  
Blocks data input when DQM active. (Byte masking)  
mask  
DQ0 ~ 63  
Vcc/Vss  
Data input/output  
Power  
Data inputs/outputs are multiplexed on the same pins.  
Power and ground for the input buffers and the core logic.  
supply/ground  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
Voltage on Any Pin Relative to Vss  
Voltage on Vcc Supply Relative to Vss  
Power Dissipation  
SYMBOL  
VIN ,OUT  
Vcc  
RATING  
-1V to 4.6V  
-1V to 4.6V  
18W  
PD  
o
o
Storage Temperature  
TSTG  
-55 C to 150 C  
Short Circuit Output Current  
IOS  
50mA  
Notes:  
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be  
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
URL: www.hbe.co.kr  
REV 1.0 (August.2002)  
4
HANBit Electronics Co.,Ltd.  
HANBit  
HSD16M72D18A  
DC OPERATING CONDITIONS  
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) )  
PARAMETER  
Supply Voltage  
SYMBOL  
Vcc  
VIH  
MIN  
3.0  
2.0  
-0.3  
2.4  
-
TYP.  
MAX  
3.6  
UNIT  
V
NOTE  
3.3  
Input High Voltage  
Input Low Voltage  
Output High Voltage  
Output Low Voltage  
3.0  
Vcc+0.3  
0.8  
V
1
VIL  
0
-
V
2
VOH  
VOL  
-
V
IOH = -2mA  
IOL = 2mA  
3
-
0.4  
V
Input leakage current  
I LI  
-10  
-
10  
uA  
Notes :  
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.  
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.  
£
£
3. Any input 0V VIN VDDQ  
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.  
CAPACITANCE  
(VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)  
DESCRIPTION  
SYMBOL  
CCLK  
MIN  
18  
MAX  
25  
UNITS  
Clock  
pF  
pF  
pF  
pF  
/RAS, /CAS,/WE,/CE, CKE, DQM  
Address  
CIN  
50  
95  
CADD  
50  
95  
DQ (DQ0 ~ DQ7)  
COUT  
13  
18  
DC CHARACTERISTICS  
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)  
TEST  
VERSION  
-12  
PARAMETER  
SYMBOL  
UNIT NOTE  
CONDITION  
-13H -13  
-10 10L  
Burst length = 1  
tRC ³ tRC(min)  
Operating current  
(One bank active)  
ICC1  
1368 1350 1350 1260 1260 mA  
1
IO = 0mA  
CKE £ VIL(max)  
tCC=10ns  
Precharge standby current  
ICC2  
P
18  
18  
mA  
mA  
in  
CKE & CLK £ VIL(max)  
tCC=¥  
power-down mode  
ICC2PS  
CKE ³ VIH(min)  
Precharge standby current  
in  
CS* ³ VIH(min), tCC=10ns  
Input signals are changed one  
time during 20ns  
mA  
ICC2N  
216  
non power-down mode  
URL: www.hbe.co.kr  
REV 1.0 (August.2002)  
5
HANBit Electronics Co.,Ltd.  
HANBit  
HSD16M72D18A  
CKE ³ VIH(min)  
CLK £ VIL(max), tCC=¥  
Input signals are stable  
CKE £ VIL(max), tCC=10ns  
CKE&CLK £ VIL(max)  
tCC=¥  
ICC2NS  
108  
ICC3  
P
36  
36  
Active standby current in  
power-down mode  
mA  
ICC3PS  
CKE³ VIH(min),  
CS*³ VIH(min), tCC=10ns  
Input signals are changed one  
time during 20ns  
ICC3  
N
360  
180  
Active standby current in  
non power-down mode  
(One bank active)  
mA  
CKE³ VIH(min)  
ICC3NS  
CLK £VIL(max), tCC=¥  
Input signals are stable  
IO = 0 mA  
Operating current  
(Burst mode)  
Page burst  
ICC4  
1980 1980 1710 1350 1350 mA  
1
2
4Banks Activated  
tCCD = 2CLKs  
Refresh current  
ICC5  
ICC6  
tRC ³ tRC(min)  
1350 1350 1350 1350 1260 mA  
mA  
mA  
Self refresh current  
CKE £ 0.2V  
Notes:  
1. Measured with outputs open.  
2. Refresh period is 64ms.  
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).  
AC OPERATING TEST CONDITIONS  
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)  
PARAMETER  
Value  
2.4/0.4  
1.4  
UNIT  
V
AC Input levels (Vih/Vil)  
Input timing measurement reference level  
Input rise and fall time  
V
tr/tf = 1/1  
1.4  
Ns  
V
Output timing measurement reference level  
Output load condition  
See Fig. 2  
URL: www.hbe.co.kr  
REV 1.0 (August.2002)  
6
HANBit Electronics Co.,Ltd.  
HANBit  
HSD16M72D18A  
+3.3V  
V =1.4V  
tt  
1200W  
50pF*  
50W  
DOUT  
DOUT  
Z0=50W  
870W  
50pF  
V
V
(DC) = 2.4V, I = -2mA  
OH  
OH  
(DC) = 0.4V, I = 2mA  
OL  
OL  
(Fig. 1) DC output load  
(Fig. 2) AC output load circuit  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
VERSION  
PARAMETER  
SYMBOL  
UNIT  
NOTE  
-13H  
14  
-13  
15  
20  
20  
45  
-12  
16  
20  
20  
48  
-10  
20  
20  
20  
50  
-10L  
20  
Row active to row active delay  
RAS to CAS delay  
tRRD(min)  
tRP(min)  
tRP(min)  
tRAS(min)  
tRAS(max)  
ns  
ns  
ns  
ns  
1
1
1
1
15  
20  
Row precharge time  
15  
20  
37  
50  
Row active time  
100  
ns  
Row cycle time  
tRC(min)  
tRDL(min)  
tDAL(min)  
tCDL(min)  
tBDL(min)  
tCCD(min)  
60  
65  
68  
2
70  
70  
ns  
1
Last data in to row precharge  
Last data in to Active delay  
Last data in to new col. address delay  
Last data in to burst stop  
CLK  
2.5  
2 CLK + 20 ns  
1
1
1
2
1
CLK  
CLK  
CLK  
2
2
3
Col. address to col. address delay  
CAS latency=3  
CAS latency=2  
Number of valid output data  
Notes :  
ea  
4
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and  
then rounding off to the next higher integer.  
2. Minimum delay is required to complete write.  
3. All parts allow every cycle column address change.  
4. In case of row precharge interrupt, auto precharge and read burst stop.  
URL: www.hbe.co.kr  
REV 1.0 (August.2002)  
7
HANBit Electronics Co.,Ltd.  
HANBit  
HSD16M72D18A  
AC CHARACTERISTICS  
(AC operating conditions unless otherwise noted)  
-13H  
-13  
-12  
-10  
-10L  
SYMB  
UNIT NOTE  
PARAMETER  
MIN  
MA  
X
MIN MAX MIN MAX MIN MAX MIN MAX  
OL  
CLK cycle  
CAS  
latency=3  
CAS  
7
7.5  
-
8
-
10  
10  
10  
12  
time  
tCC  
1000  
1000  
1000  
1000  
ns  
ns  
ns  
1
1,2  
2
7.5  
latency=2  
CAS  
CLK to valid  
5.4  
5.4  
5.4  
-
6
-
6
6
6
7
output delay latency=3  
tSAC  
CAS  
latency=2  
Output data  
hold time  
CAS  
latency=3  
CAS  
3
2
2.7  
-
3
-
3
3
3
3
tOH  
latency=2  
CLK high pulse width  
CLK low pulse width  
Input setup time  
tCH  
tCL  
2.5  
2.5  
1.5  
0.8  
1
2.5  
2.5  
1.5  
0.8  
1
3
3
2
1
1
3
3
2
1
1
3
3
2
1
1
ns  
ns  
ns  
ns  
ns  
3
3
3
3
3
tSS  
tSH  
tSLZ  
Input hold time  
CLK to output in Low-Z  
CLK to output  
in Hi-Z  
CAS  
latency=3  
CAS  
5.4  
5.4  
5.4  
-
6
-
6
6
6
7
ns  
ns  
2
tSHZ  
latency=2  
Notes :  
1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.  
3. Assumed input rise and fall time (tr & tf) = 1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to  
the parameter.  
URL: www.hbe.co.kr  
REV 1.0 (August.2002)  
8
HANBit Electronics Co.,Ltd.  
HANBit  
HSD16M72D18A  
SIMPLIFIED TRUTH TABLE  
/R  
A
S
/C  
A
S
D
Q
M
CKE  
CKE  
n
/C  
S
/W  
E
BA  
0,1  
A10/  
AP  
A11  
A9~A0  
n-1  
COMMAND  
NOTE  
Register  
Refresh  
Mode register set  
Auto refresh  
H
X
H
L
L
L
L
L
L
X
OP code  
X
1,2  
3
H
L
L
H
X
Entry  
3
Self  
refres  
h
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit  
L
H
X
X
X
X
3
Bank active & row addr.  
H
V
V
Row address  
Auto  
precharge  
Read &  
column  
address  
L
Column  
4
disable  
Auto  
H
H
X
L
H
L
H
X
Address  
precharge  
precharge  
precharge  
(A0 ~ A9)  
H
4,5  
disable  
Column  
Address  
(A0 ~ A9)  
Auto  
Write &  
column  
address  
L
4
disable  
X
L
H
L
L
X
V
Auto  
H
4,5  
6
disable  
Burst Stop  
H
H
X
X
L
L
L
L
H
H
L
L
X
X
X
Precharg Bank selection  
V
X
L
X
e
All banks  
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry  
Exit  
H
L
L
H
L
X
X
X
Clock suspend or  
active power down  
X
X
X
H
L
Entry  
H
Precharge power  
down mode  
H
L
Exit  
L
H
X
X
V
X
DQM  
H
H
X
X
X
7
H
L
X
H
X
X
H
No operation command  
H
(V=Valid, X=Don't care, H=Logic high, L=Logic low)  
Notes :  
1. OP Code : Operand code  
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)  
2. MRS can be issued only at all banks precharge state.  
A new command can be issued after 2 CLK cycles of MRS.  
3. Auto refresh functions are as same as CBR refresh of DRAM.  
The automatical precharge without row precharge command is meant by "Auto".  
Auto/self refresh can be issued only at all banks precharge state.  
4. BA0 ~ BA1 : Bank select addresses.  
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.  
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.  
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.  
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.  
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.  
5. During burst read or write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the associated bank can be issued at tRP after the end of burst.  
6. Burst stop command is valid at every burst length.  
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),  
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)  
URL: www.hbe.co.kr  
REV 1.0 (August.2002)  
9
HANBit Electronics Co.,Ltd.  
HANBit  
HSD16M72D18A  
PACKAGING INFORMATION  
Unit : inch [mm]  
PCB  
:
1.27 ±0.008 [ ±0.20 ]  
두께  
ORDERING INFORMATION  
F means Auto & Self refresh with Low-Power (3.3V)  
Part Number  
Density  
Org.  
Package  
Ref.  
Vcc  
MODE  
MAX.frq  
ECC/  
Unbuffered  
ECC/  
CL3  
133MHz  
CL2  
HSD16M72D18A-13  
HSD16M72D18A-13H  
HSD16M72D18A-12  
HSD16M72D18A-10L  
HSD16M72D18A-10  
HSD16M72D18A-F13  
128MByte  
128MByte  
128MByte  
128MByte  
128MByte  
128MByte  
16M x 72  
16M x 72  
16M x 72  
16M x 72  
16M x 72  
16M x 72  
168 Pin-DIMM  
168 Pin-DIMM  
168 Pin-DIMM  
168 Pin-DIMM  
168 Pin-DIMM  
168 Pin-DIMM  
168 Pin-DIMM  
168 Pin-DIMM  
168 Pin-DIMM  
4K  
4K  
4K  
4K  
4K  
4K  
4K  
4K  
4K  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
Unbuffered  
ECC/  
133MHz  
CL3  
Unbuffered  
ECC/  
125MHz  
CL3  
Unbuffered  
ECC/  
100MHz  
CL2  
Unbuffered  
ECC/  
100MHz  
CL3  
Unbuffered  
ECC/  
133MHz  
CL3  
HSD16M72D18A-F12 128MByte 16M x 72  
HSD16M72D18A-F10L 128MByte 16M x 72  
HSD16M72D18A-F10 128MByte 16M x 72  
125MHz  
CL3  
Unbuffered  
ECC/  
100MHz  
CL2  
Unbuffered  
ECC/  
100MHz  
Unbuffered  
URL: www.hbe.co.kr  
REV 1.0 (August.2002)  
10  
HANBit Electronics Co.,Ltd.  

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