HSD32M64B8A-F13 [HANBIT]
Synchronous DRAM Module 256Mbyte (32Mx64Bit), SO-DIMM, 4Banks, 8K Ref., 3.3V; 同步DRAM模组256Mbyte （ 32Mx64Bit ） ， SO -DIMM ， 4Banks ， 8K参考， 3.3V
| 型号： | HSD32M64B8A-F13 |
| 厂家： | 
HANBIT ELECTRONICS CO.,LTD |
| 描述： | Synchronous DRAM Module 256Mbyte (32Mx64Bit), SO-DIMM, 4Banks, 8K Ref., 3.3V |
| 文件： | 总11页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HANBit
HSD32M64B8A
Synchronous DRAM Module 256Mbyte (32Mx64Bit), SO-DIMM,
4Banks, 8K Ref., 3.3V
Part No. HSD32M64B8A
GENERAL DESCRIPTION
The HSD32M64B8A is a 32M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists
of eight CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The
HSD32M64B8A is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge
connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be
useful for a variety of high bandwidth, high performance memory system applications All module components may be
powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
• Part Identification
HSD32M64B8A-F/10L : 100MHz (CL=3)
HSD32M64B8A-F/10 : 100MHz (CL=2)
HSD32M64B8A-F/12 : 125MHz (CL=3)
HSD32M64B8A-F/13 : 133MHz (CL=3)
F means Auto & Self refresh with Low-Power (3.3V)
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 8M x 8bit x 4Banks Synchronous DRAM
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HANBit
HSD32M64B8A
PIN ASSIGNMENT
PIN Symbol PIN Symbol PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
1
Vss
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
Vss
2
Vss
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
Vss
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
DQ13
DQ14
DQ15
Vss
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
DQ45
DQ46
DQ47
Vss
97
DQ22
DQ23
VDD
98
DQ54
DQ55
VDD
A7
3
4
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
5
6
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
7
8
A6
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
NC
NC
A8
BA0
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
NC
NC
Vss
Vss
CLK0
VDD
/RAS
/WE
CKE0
VDD
/CAS
NC
A9
BA1
A10_AP
VDD
A11
VDD
DQM6
DQM7
Vss
DQM2
DQM3
Vss
/CS0
NC
A12
DQM0
DQM1
VDD
A0
DQM4
DQM5
VDD
A3
NC
NC
CLK1
Vss
DQ24
DQ25
DQ26
DQ27
VDD
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
Vss
Vss
NC
NC
A1
A4
NC
NC
A2
A5
VDD
DQ16
DQ17
DQ18
DQ19
Vss
VDD
DQ48
DQ49
DQ50
DQ51
Vss
Vss
Vss
DQ28
DQ29
DQ30
DQ31
Vss
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ40
DQ41
DQ42
DQ43
VDD
DQ44
DQ20
DQ21
DQ52
DQ53
**SDA
VDD
**SCL
VDD
** These pins should be NC in the system which does not support SPD
URL:www.hbe.co.kr
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HANBit
HSD32M64B8A
FUNCTIONAL BLOCK DIAGRAM
DQ0-63
CLKA
CKE
CAS
CLK
CKE0
/CAS
U1
DQ8-15
/RAS
/CS0
DQM0
RAS
CE
DQM1
BA0-1
WE A0-A12
CKE
CAS
CLK
U2
DQ8-15
RAS
CE
DQM1
BA0-1
DQM1
WE A0-A12
CKE
CAS
CLK
U3
CLKB
DQ16-23
RAS
CE
DQM2
BA0-1
DQM2
WE A0-A12
CKE
CAS
U4
CLK
DQ24-31
RAS
CE
DQM3
BA0-1
DQM3
WE A0-A12
CKE
CAS
CLK
U5
CLKC
DQM4
DQ32-39
RAS
CE
DQM4
BA0-1
WE A0-A12
CKE
CAS
CLK
U6
DQ40-47
RAS
CE
DQM5
BA0-1
DQM5
WE A0-A12
CLKD
DQM6
CKE
CAS
CLK
U7
DQ48-55
RAS
CE
DQM6
BA0-1
WE A0-A12
CKE
CAS
U8
CLK
DQ56-63
RAS
CE
DQM7
BA0-1
DQM7
WE A0-A12
/WE
A0 - A12
BA0-1
CLKA
Vcc
Vss
CLKB
CLKC
CLKD
Two 0.1uF Capacitors
per each SDRAM
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HSD32M64B8A
PIN FUNCTION DESCRIPTION
Pin
Name
System clock
Chip enable
Input Function
CLK
/CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
A0 ~ A12
BA0 ~ BA1
/RAS
Address
Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
/CAS
Column
address Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
strobe
/WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data
input/output Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
mask
DQ0 ~ 63
Vcc/Vss
Data input/output
Power
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
SYMBOL
VIN ,OUT
Vcc
RATING
-1V to 4.6V
-1V to 4.6V
8W
PD
o
o
Storage Temperature
TSTG
-55 C to 150 C
Short Circuit Output Current
IOS
400mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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HANBit
HSD32M64B8A
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) )
PARAMETER
Supply Voltage
SYMBOL
Vcc
VIH
MIN
3.0
2.0
-0.3
2.4
-
TYP.
MAX
3.6
UNIT
V
NOTE
3.3
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
3.0
Vcc+0.3
0.8
V
1
VIL
0
-
V
2
VOH
VOL
-
V
IOH = -2mA
IOL = 2mA
3
-
0.4
V
Input leakage current
I LI
-10
-
10
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
DESCRIPTION
SYMBOL
CCLK
MIN
2.5
2.5
2.5
4.0
MAX
4.0
UNITS
Clock
pF
pF
pF
pF
Address
CADD
5.0
/RAS, /CAS, /WE, /CS, CKE, DQM
DQ (DQ0 ~ DQ15)
C IN
5.0
COUT
6.5
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
TEST
VERSION
PARAMETER
SYMBOL
UNIT NOTE
CONDITION
Burst length = 1
-13
-12
-10
-10L
Operating current
ICC1
tRC ³ tRC(min)
960
960
880
880
mA
1
(One bank active)
IO = 0mA
CKE £ VIL(max)
tCC=10ns
ICC2
P
16
16
mA
mA
Precharge standby current in
power-down mode
CKE & CLK £ VIL(max)
tCC=¥
ICC2PS
CKE ³ VIH(min)
CS* ³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
Precharge standby current in
non power-down mode
mA
ICC2
N
128
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HANBit
HSD32M64B8A
CKE ³ VIH(min)
ICC2NS
CLK £ VIL(max), tCC=¥
Input signals are stable
CKE £ VIL(max), tCC=10ns
CKE&CLK £ VIL(max)
tCC=¥
112
ICC3
P
48
48
Active standby current in
power-down mode
mA
ICC3PS
CKE³ VIH(min),
CS*³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
CKE³ VIH(min)
ICC3
N
240
200
Active standby current in
non power-down mode
(One bank active)
mA
ICC3NS
CLK £VIL(max), tCC=¥
Input signals are stable
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
1120 1120
920
920
mA
1
2
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
1680 1680 1600 1600
mA
mA
mA
40
16
Self refresh current
CKE £ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)
PARAMETER
Value
2.4/0.4
1.4
UNIT
AC Input levels (Vih/Vil)
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
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HANBit
HSD32M64B8A
+3.3V
V =1.4V
tt
1200W
50pF*
50W
DOUT
DOUT
Z0=50W
870W
50pF
V
V
(DC) = 2.4V, I = -2mA
OH
OH
(DC) = 0.4V, I = 2mA
OL
OL
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
UNIT
NOTE
-13
15
20
20
45
-12
-10
20
20
20
50
-10L
20
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRP(min)
16
20
20
48
ns
ns
ns
ns
1
1
1
1
20
Row precharge time
tRP(min)
20
tRAS(min)
tRAS(max)
50
Row active time
100
2
ns
Row cycle time
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
65
68
70
70
ns
CLK
-
1
2.5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
2 CLK + 20 ns
1
1
1
2
CLK
CLK
CLK
2
2
Col. address to col. address delay
3
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
(Recommand : tRDL=2CLK and tDAL=2CLK & 20ns.)
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HANBit
HSD32M64B8A
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-13
-12
MAX MIN
-10
MAX MIN
-10L
PARAMETER
SYMBOL
UNIT
NOTE
MIN MAX MIN
MAX
CLK cycle time CAS
7.5
-
8
-
10
10
10
12
latency=3
tCC
1000
1000
1000
1000
ns
1
1,2
2
CAS
latency=2
CAS
CLK to valid
output delay
5.4
-
6
-
6
6
6
7
latency=3
CAS
tSAC
ns
ns
latency=2
CAS
Output data
hold time
2.7
-
3
-
3
3
3
3
latency=3
CAS
tOH
latency=2
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
3
3
2
1
1
3
3
2
1
1
3
3
2
1
1
ns
ns
ns
ns
ns
3
3
3
3
3
tSS
tSH
tSLZ
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS
5.4
-
6
-
6
6
6
7
ns
ns
2
latency=3
CAS
tSHZ
latency=2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to
the parameter.
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HANBit
HSD32M64B8A
SIMPLIFIED TRUTH TABLE
CK
/R
A
S
/C
A
S
D
Q
M
CKE
n
/C
S
/W
E
BA
0,1
A10/
AP
A11,A12,
A9~A0
E
COMMAND
NOTE
n-1
Register
Refresh
Mode register set
Auto refresh
H
X
H
L
L
L
L
L
L
X
OP code
X
1,2
3
H
L
L
H
X
Entry
Self
3
L
H
L
H
X
L
H
X
H
H
X
H
3
refresh
Exit
L
H
X
X
X
X
3
Bank active & row addr.
H
V
V
Row address
Auto
Read &
precharge
L
Column
Address
(A0 ~ A9)
4
disable
column
H
H
X
L
H
L
H
X
Auto
precharge
address
disable
H
4,5
Column
Address
(A0 ~ A9)
Auto
Write &
precharge
precharge
L
4
disable
column
X
L
H
L
L
X
V
address
Auto
H
4,5
6
disable
Burst Stop
Precharge
H
H
X
X
L
L
L
L
H
H
L
L
X
X
X
Bank selection
All banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
X
H
L
Entry
H
Precharge power
down mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
X
X
X
H
No operation command
H
H
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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HANBit
HSD32M64B8A
TIMING DIAGRAMS
Please refer to attached timing diagram chart (II)
PACKAGING INFORMATION
Unit : Inch [mm]
PCB Thickness: 1.0mm (10.0t - 1.1t)
Immersion Gold PCB Pattern
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HANBit
HSD32M64B8A
ORDERING INFORMATION
Part Number
Density
Org.
Package
Ref.
Vcc
Bank
MAX.frq
CL3
133MHz
CL3
HSD32M64B8A-13
HSD32M64B8A-12
HSD32M64B8A-10L
HSD32M64B8A-10
HSD32M64B8A-F13
HSD32M64B8A-F12
HSD32M64B8A-F10L
HSD32M64B8A-F10
256MByte
256MByte
256MByte
256MByte
256MByte
256MByte
256MByte
256MByte
32M x 64
32M x 64
32M x 64
32M x 64
32M x 64
32M x 64
32M x 64
32M x 64
144 Pin-SODIMM
144 Pin-SODIMM
144 Pin-SODIMM
144 Pin-SODIMM
144 Pin-SODIMM
144 Pin-SODIMM
144 Pin-SODIMM
144 Pin-SODIMM
8K
8K
8K
8K
8K
8K
8K
8K
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
4Bank
4Bank
4Bank
4Bank
4Bank
4Bank
4Bank
4Bank
125MHz
CL3
100MHz
CL2
100MHz
CL3
133MHz
CL3
125MHz
CL3
100MHz
CL2
100MHz
F means Auto & Self refresh with Low-Power (3.3V)
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HANBIT
HSD32M64B8W-13
Synchronous DRAM Module 256Mbyte(32Mx64-Bit), 144pin SO-DIMM, 4Banks, 8K Ref., 3.3V
HANBIT
HSD32M64B8W-13
Synchronous DRAM Module 256Mbyte(32Mx64-Bit), 144pin SODIMM, 4Banks, 8K Ref., 3.3V
DLGHANBIT
HSD32M64B8WLF-13
Synchronous DRAM Module 256Mbyte(32Mx64-Bit), 144pin SODIMM, 4Banks, 8K Ref., 3.3V
DLGHANBIT
HSD32M64D16A
Synchronous DRAM Module 256Mbyte (32Mx64bit), DIMM based on16Mx8, 4Banks, 4K Ref., 3.3V
HANBIT
HSD32M64D16A-10
Synchronous DRAM Module 256Mbyte (32Mx64bit), DIMM based on16Mx8, 4Banks, 4K Ref., 3.3V
HANBIT
HSD32M64D16A-10L
Synchronous DRAM Module 256Mbyte (32Mx64bit), DIMM based on16Mx8, 4Banks, 4K Ref., 3.3V
HANBIT
HSD32M64D16A-12
Synchronous DRAM Module 256Mbyte (32Mx64bit), DIMM based on16Mx8, 4Banks, 4K Ref., 3.3V
HANBIT
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