HSD32M64D8KP [HANBIT]
Synchronous DRAM Module 256Mbyte (32Mx64bit),DIMM Unbuffered with Based on Stacked 16Mx8, 4Banks, 4K Ref., 3.3V; 同步DRAM模组256Mbyte （ 32Mx64bit ） ，无缓冲DIMM与基于堆栈16Mx8 ， 4Banks ， 4K参考， 3.3V
| 型号： | HSD32M64D8KP |
| 厂家： | 
HANBIT ELECTRONICS CO.,LTD |
| 描述： | Synchronous DRAM Module 256Mbyte (32Mx64bit),DIMM Unbuffered with Based on Stacked 16Mx8, 4Banks, 4K Ref., 3.3V |
| 文件： | 总29页 (文件大小：813K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HANBit
HSD32M64D8KP
Synchronous DRAM Module 256Mbyte (32Mx64bit),DIMM Unbuffered with Based on
Stacked 16Mx8, 4Banks, 4K Ref., 3.3V
Part No. HSD32M64D8KP
GENERAL DESCRIPTION
The HSD32M64D8KP is a 32M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists
of sixteen CMOS 16M x 8 bit(stacking chip) with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin
glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each
SDRAM. The HSD32M64D8KP is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge
connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be
useful for a variety of high bandwidth, high performance memory system applications All module components may be
powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
• Part Identification
HSD32M64D8KP – 10L : 100MHz ( CL=3)
HSD32M64D8KP – 13
: 133MHz ( CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 4M x 8bit x 4Banks SDRAM
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HANBit
HSD32M64D8KP
PIN ASSIGNMENT
PIN Symbol PIN
Symbol
DQM1
/CS0
NC
PIN
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
DQ18
DQ19
Vcc
PIN
85
Symbol
Vss
PIN
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Symbol
DQM5
/CS1
/RAS
Vss
PIN
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
DQ50
DQ51
Vcc
1
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
2
86
DQ32
DQ33
DQ34
DQ35
Vcc
3
87
4
Vss
DQ20
NC
88
DQ52
NC
5
A0
89
A1
6
A2
NC
90
A3
NC
7
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
A4
/CKE1
Vss
91
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
A5
NC
8
A6
92
A7
Vss
9
A8
DQ21
DQ22
DQ23
Vss
93
A9
DQ53
DQ54
DQ55
Vss
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A10
BA1
Vcc
94
BA0
A11
95
96
Vcc
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
Vcc
DQ24
DQ25
DQ26
DQ27
Vcc
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
CLK1
NC
DQ56
DQ57
DQ58
DQ59
Vcc
CLK0
Vss
98
99
Vss
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
CKE0
/CS3
DQM6
DQM7
NC
/CS2
DQM2
DQM3
NC
DQ28
DQ29
DQ30
DQ31
Vss
DQ60
DQ61
DQ62
DQ63
Vss
DQ14
DQ15
CB0
CB1
Vss
DQ46
DQ47
CB4
Vcc
Vcc
NC
CB5
NC
NC
CLK2
NC
Vss
NC
CLK3
NC
NC
CB2
CB3
Vss
NC
CB6
CB7
Vss
NC
WP
NC
SA0
Vcc
SDA
SCL
Vcc
SA1
/WE
DQ16
DQ17
/CAS
DQM4
DQ48
DQ49
SA2
DQM0
Vcc
Vcc
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HANBit
HSD32M64D8KP
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vcc
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HSD32M64D8KP
PIN FUNCTION DESCRIPTION
PIN
NAME
System clock
Chip enable
INPUTT FUNCTION
CLK
/CE
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
A0 ~ A11
BA0 ~ BA1
/RAS
Address
Bank select address
Row address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
/CAS
Column
Address
strobe
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
/WE
Write enable
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
Data
input/output
mask
DQ0 ~ 63
Vcc/Vss
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Power supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
SYMBOL
VIN ,OUT
Vcc
RATING
-1.0V to 4.6V
-1.0V to 4.6V
16W
PD
o
o
Storage Temperature
TSTG
-55 C to 150 C
50mA
Short Circuit Output Current
IOS
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C))
PARAMETER
Supply Voltage
SYMBOL
Vcc
VIH
MIN
3.0
2.0
-0.3
2.4
-
TYP.
MAX
3.6
UNIT
V
NOTE
3.3
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input leakage current
3.0
Vcc+0.3
0.8
V
1
VIL
0
-
V
2
VOH
VOL
-
V
IOH = -2mA
IOL = 2mA
3
-
0.4
V
I LI
-10
-
10
uA
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HSD32M64D8KP
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
DESCRIPTION
SYMBOL
CCLK
MIN
10
40
10
10
5
MAX
14
UNITS
pF
Clock
/RAS, /CAS,/WE, CKE
CIN
60.8
15.2
15.2
7.6
pF
CKE
CCKE
CCS
pF
/CS
pF
DQM
CDQM
CADD
COUT
pF
Address
DQ (DQ0 ~ DQ7)
40
64
60.8
96
pF
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
TEST
VERSION
NOT
E
PARAMETER
SYMBOL
UNIT
CONDITION
Burst length = 1
tRC ³ tRC(min)
IO = 0mA
-13
-10L
Operating current
(One bank active)
ICC1
1440
1440
mA
1
CKE £ VIL(max)
tCC=10ns
CKE & CLK £ VIL(max)
tCC=¥
Precharge standby current
in
power-down mode
ICC2
P
32
32
mA
mA
ICC2PS
CKE ³ VIH(min)
CS* ³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
CKE ³ VIH(min)
CLK £ VIL(max), tCC=¥
Input signals are stable
ICC2
N
320
160
Precharge standby current
in
non power-down mode
mA
mA
mA
mA
ICC2NS
ICC3
ICC3PS
P
CKE £ VIL(max), tCC=10ns
CKE&CLK £ VIL(max)
tCC=¥
80
80
Active standby current in
power-down mode
CKE³ VIH(min),
CS*³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
CKE³ VIH(min)
CLK £VIL(max), tCC=¥
Input signals are stable
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
ICC3
N
480
400
Active standby current in
non power-down mode
(One bank active)
ICC3NS
Operating current
(Burst mode)
ICC4
1760
3200
1600
3040
1
2
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
mA
mA
Self refresh current
CKE £ 0.2V
C
32
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HANBiT Electronics Co., Ltd
HANBit
HSD32M64D8KP
L
12.8
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)
PARAMETER
AC Input levels (Vih/Vil)
Value
2.4/0.4
1.4
UNIT
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
+3.3V
1200W
V =1.4V
tt
DOUT
V
V
(DC) = 2.4V, I = -2mA
OH
OH
870W
50pF*
(DC) = 0.4V, I = 2mA
OL
OL
50W
DOUT
Z0=50W
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
UNIT
NOTE
-13
15
20
20
45
-10L
20
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRP(min)
ns
ns
ns
ns
1
1
1
1
20
Row precharge time
tRP(min)
20
tRAS(min)
tRAS(max)
50
Row active time
100
ns
Row cycle time
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
CAS
65
70
ns
CLK
-
1
2
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
2
2 CLK + 20 ns
1
1
1
CLK
CLK
CLK
2
2
3
Col. address to col. address delay
Number of valid output data
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2
ea
4
latency=3
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HANBiT Electronics Co., Ltd
HANBit
HSD32M64D8KP
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.5. For -L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-75
-10L
PARAMETER
SYMBOL
UNIT
NOTE
MIN
MAX
MIN
MAX
CLK cycle time
CAS latency=3
CAS latency=3
tCC
7.5
1000
10
1000
ns
ns
1
CLK to valid
output delay
Output data
hold time
tSAC
5.4
6
1,2
CAS latency=3
tOH
3
3
ns
2
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
3
3
2
1
1
ns
ns
ns
ns
ns
ns
3
3
3
3
3
2
tSS
Input hold time
tSH
CLK to output in Low-Z
CLK to output
tSLZ
tSHZ
CAS latency=3
5.4
6
in Hi-Z
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered
ie., [(tr + tf)/2-1]ns should be added to the parameter.
SIMPLIFIED TRUTH TABLE
/R
A
S
/C
A
S
D
Q
M
CKE
CKE
n
/C
S
/W
E
BA
0,1
A10/
AP
A11
A9~A0
n-1
COMMAND
NOTE
Register
Refresh
Mode register set
Auto refresh
H
H
X
H
L
L
L
L
L
L
X
OP code
X
1,2
3
L
L
H
X
Entry
Self
3
L
H
X
H
X
H
X
3
3
refres
h
Exit
L
H
X
X
X
X
H
Bank active & row address.
H
L
L
H
H
V
Row address
Auto
disable
precharge
Read &
column
address
Column
Address
(A0 ~ A9)
L
4
H
H
X
X
L
L
H
H
L
L
H
L
X
X
V
V
Auto
disable
Auto
disable
precharge
precharge
H
L
4,5
4
Write &
column
Column
Address
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HANBiT Electronics Co., Ltd
HANBit
HSD32M64D8KP
address
Auto
enable
precharge
(A0 ~ A9)
H
4,5
6
Burst Stop
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Precharg
e
Bank selection
All banks
V
L
X
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
X
H
L
Entry
H
Precharge power
down mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
X
7
H
L
X
H
X
H
X
H
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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HSD32M64D8KP
TIMING DIAGRAM
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HSD32M64D8KP
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HSD32M64D8KP
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HSD32M64D8KP
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HSD32M64D8KP
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HSD32M64D8KP
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HSD32M64D8KP
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HANBit
HSD32M64D8KP
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HANBit
HSD32M64D8KP
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HANBiT Electronics Co., Ltd
HANBit
HSD32M64D8KP
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HANBit
HSD32M64D8KP
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HANBit
HSD32M64D8KP
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HANBit
HSD32M64D8KP
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HANBiT Electronics Co., Ltd
HANBit
HSD32M64D8KP
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HANBit
HSD32M64D8KP
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HANBiT Electronics Co., Ltd
HANBit
HSD32M64D8KP
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HANBit
HSD32M64D8KP
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HSD32M64D8KP
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HANBiT Electronics Co., Ltd
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HSD32M64D8KP
* All banks precharge should be completed before Mode Resister Set cycle and auto refresh cycle
--MODE RESISTER SET CYCLE--
*Note :
1. /CS, /RAS, /CAS, /WE activation at the same clock cycle with address key will set internal mode resister
2.Minimum 2 clock cycle should be met before new /RAS activation.
3.Please refer to Mode Resister Set table
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HANBiT Electronics Co., Ltd
HANBit
HSD32M64D8KP
PACKAGING INFORMATION
Unit : mm
Front View
Rear View
ORDERING INFORMATION
Part Number
Density
Org.
Package
Ref.
Vcc
MODE
MAX.frq
CL3
133MHz
HSD32M64D8KP-13
HSD32M64D8KP-10L
256MByte
256MByte
32M x64
168 Pin-DIMM
4K
4K
3.3V
3.3V
SDRAM
SDRAM
CL3
100MHz
32M x 64 168 Pin-DIMM
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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