HSD32M72D16R-12N [HANBIT]
Synchronous DRAM Module 256Mbyte (32Mx64bit), DIMM with based on 16Mx8, 4Banks, 4K Ref., 3.3V; 同步DRAM模组256Mbyte （ 32Mx64bit ） ， DIMM基于16Mx8 ， 4Banks ， 4K参考， 3.3V
| 型号： | HSD32M72D16R-12N |
| 厂家： | 
HANBIT ELECTRONICS CO.,LTD |
| 描述： | Synchronous DRAM Module 256Mbyte (32Mx64bit), DIMM with based on 16Mx8, 4Banks, 4K Ref., 3.3V |
| 文件： | 总12页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HANBit
HSD32M64D16R
Synchronous DRAM Module256Mbyte (32Mx64bit), DIMM with based on 16Mx8,
4Banks, 4K Ref., 3.3V
Part No. HSD32M64D16R
GENERAL DESCRIPTION
The HSD32M64D16R is a 32M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists
of sixteen CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin
TSSOP package on a 168-pin glass-epoxy. One 0.22uF and two 0.0022uF decoupling capacitors are mounted on the
printed circuit board in parallel for each SDRAM. The HSD32M72D18AR is a DIMM (Dual in line Memory Module) and is
intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable
latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system
applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are
LVTTL-compatible.
FEATURES
• Part Identification
HSD32M64D16R : 100MHz (CL=2, CL=3)
HSD32M64D16R : 133MHz (CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 4M x 8bit x 4Banks SDRAM
URL:www.hbe.co.kr
REV.1.0 (August.2002).
- 1 -
HANBit Electronics Co.,Ltd
HANBit
HSD32M64D16R
PIN ASSIGNMENT
PIN Symbol
PIN
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Symbol
DQM1
/CE0
NC
PIN
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
DQ18
DQ19
Vcc
PIN
85
Symbol
Vss
PIN
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
Symbol
DQM5
/CE1
/RAS
Vss
PIN
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
DQ50
DQ51
Vcc
1
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
2
86
DQ32
DQ33
DQ34
DQ35
Vcc
3
87
4
Vss
DQ20
NC
88
DQ52
NC
5
A0
89
A1
6
A2
NC
90
A3
NC
7
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
A4
NC
91
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
A5
REGE
Vss
8
A6
Vss
92
A7
9
A8
DQ21
DQ22
DQ23
Vss
93
A9
DQ53
DQ54
DQ55
Vss
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A10
94
BA0
A11
Vcc
BA1
Vcc
95
96
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
Vcc
DQ24
DQ25
DQ26
DQ27
Vcc
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
CLK1
NC
DQ56
DQ57
DQ58
DQ59
Vcc
CLK0
Vss
98
99
Vss
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
CKE0
/CE3
DQM6
DQM7
NC
/CE2
DQM2
DQM3
NC
DQ28
DQ29
DQ30
DQ31
Vss
DQ60
DQ61
DQ62
DQ63
Vss
DQ14
DQ15
NC(CB0)
NC(CB1)
Vss
DQ46
DQ47
Vcc
NC(CB4) 133
NC(CB5) 134
Vcc
NC
NC
NC
CLK2
NC
Vss
NC
135
NC
CLK3
NC
NC
NC(CB2)
NC(CB3)
Vss
136 NC(CB6)
137 NC(CB7)
NC
WP
NC
SA0
Vcc
SDA
SCL
Vcc
138
139
140
Vss
SA1
/WE
DQ16
DQ17
/CAS
DQM4
DQ48
DQ49
SA2
DQM0
Vcc
Vcc
* These pins are not used in this module ** These pins should be NC in the system which does not support SPD
*Pin Names
A0~A11: Address input (Multiplexed)
BA0~BA1: Select bank
CLK0: Clock input
DQ0~DQ63: Data input/output
CKE0: Clock enable input
/CE0~/CE3: Chip select input
/CAS: Coulmn address strobe
DQM0~7: DQM
/RAS: Row address strobe
REGE: Register enable
/WE: Write enable
VCC: Power supply(3.3V)
*VREF:Power supply for reference
SA0~2: Address in EEPROM
NC: No connection
VSS: Ground
SDA: Serial data I/O
SCL: Serial clock
URL:www.hbe.co.kr
REV.1.0 (August.2002).
- 2 -
HANBit Electronics Co.,Ltd
HANBit
HSD32M64D16R
FUNCTIONAL BLOCK DIAGRAM
** This module not used D4 and D13. ( NO Parity)
URL:www.hbe.co.kr
REV.1.0 (August.2002).
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HANBit Electronics Co.,Ltd
HANBit
HSD32M64D16R
PIN FUNCTION DESCRIPTION
Pin
Name
System clock
Chip enable
Input Function
CLK
/CE
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
A0 ~ A11
BA0 ~ BA1
/RAS
Address
Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Row address strobe Latches row addresses on the positive going edge of the CLK with /RAS low.
Enables row access & precharge.
/CAS
Column address
strobe
Latches column addresses on the positive going edge of the CLK with /CAS low.
Enables column access.
/WE
Write enable
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
DQM0 ~ 7
REGE
Data input/output
mask
Makes data output Hi-Z, tsHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
The device operates in the transparent mode when REGE is low. When REGE is
high, the
Register enable
device operates in the registered mode. In registered mode, the Address and
control inputs are latched if CLK is held at a high or low logic level. The inputs are
strobed in the latch/flip-flop on the riging edge of CLK. REGE is tied to VDD
through 10K ohm register on PCB. So if REGE of module is floating, this module
will be operated as registerd mode.
DQ0 ~ 63
WP
Data input/output
Write Protection
Data inputs/outputs are multiplexed on the same pins.
WP pin is connected to Vcc.
When WP is “high”, EEPROM Programming will be inhibited and the entire
memory will be write-protected.
VDD/VSS
Power
Power and ground for the input buffers and the core logic.
supply/ground
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REV.1.0 (August.2002).
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HANBit Electronics Co.,Ltd
HANBit
HSD32M64D16R
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
SYMBOL
VIN ,OUT
Vcc
RATING
-1V to 4.6V
-1V to 4.6V
16W
PD
o
o
Storage Temperature
TSTG
-55 C to 150 C
Short Circuit Output Current
IOS
50mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) )
PARAMETER
Supply Voltage
SYMBOL
Vcc
VIH
MIN
3.0
2.0
-0.3
2.4
-
TYP.
MAX
3.6
UNIT
V
NOTE
3.3
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
3.0
Vcc+0.3
0.8
V
1
VIL
0
-
V
2
VOH
VOL
-
V
IOH = -2mA
IOL = 2mA
3
-
0.4
V
Input leakage current
I LI
-10
-
10
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(Vcc = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
DESCRIPTION
Input capacitance(A0~A11)
SYMBOL
CIN1
MIN
MAX
19
19
33
12
12
12
12
19
19
UNITS
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input capacitance(/RAS, /CAS,/WE)
Input capacitance(CKE0)
CIN2
CIN3
Input capacitance(CLK0)
CIN4
Input capacitance(/CE0~/CE3)
Input capacitance(DQM0~DQM7)
Input capacitance(BA0~BA1)
CIN5
CIN3
CIN3
Data input/output capacitance (DQ0 ~ DQ63)
Data input/output capacitance (CB0 ~ CB7)
COUT
COUT1
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REV.1.0 (August.2002).
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HANBit Electronics Co.,Ltd
HANBit
HSD32M64D16R
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
TEST
VERSION
-1L
PARAMETER
SYMBOL
UNIT
NOTE
CONDITION
Burst length = 1
-1H
-13
Operating current
(One bank active)
ICC1
tRC ³ tRC(min)
1760
1920
mA
1
IO = 0mA
CKE £ VIL(max)
Precharge
standby ICC2
P
16
16
mA
mA
3
3
tCC=10ns
current in power-down
mode
CKE & CLK £ VIL(max)
tCC=¥
ICC2PS
CKE ³ VIH(min)
/CE ³ VIH(min), tcc=10ns
Input signals are changed
one time during 20ns
CKE ³ VIH(min)
ICC2
N
320
Precharge
standby
current in non power-
down mode
mA
mA
mA
3
3
3
ICC2NS
CLK £ VIL(max), tcc=¥
Input signals are stable
CKE £ VIL(max), tcc=10ns
CKE&CLK £ VIL(max)
tcc=¥
112
ICC3
P
80
80
Active standby current in
power-down mode
ICC3PS
CKE³ VIH(min),
/CE³ VIH(min), tcc=10ns
Input signals are changed
one time during 20ns
CKE³ VIH(min)
ICC3
N
480
320
Active standby current in
non power-down mode
(One bank active)
ICC3NS
CLK £VIL(max), tcc=¥
Input signals are stable
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
2000
3360
2400
3520
mA
1
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
mA
mA
2
3
Self refresh current
CKE £ 0.2V
24
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1PLL & 3 Drive Ics.
4. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
URL:www.hbe.co.kr
REV.1.0 (August.2002).
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HANBit Electronics Co.,Ltd
HANBit
HSD32M64D16R
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)
PARAMETER
Value
2.4/0.4
1.4
UNIT
V
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
+3.3V
1200W
V =1.4V
tt
DOUT
870
W
50pF*
50W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
DOUT
Z0=50W
vss
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
UNIT
NOTE
-1H
20
20
20
50
-1L
20
20
20
50
-13
15
20
20
45
Row active to row active delay
/RAS to /CAS delay
tRRD(min)
tRCD(min)
tRP(min)
ns
ns
ns
ns
1
1
1
1
Row precharge time
tRAS(min)
tRAS(max)
Row active time
100
70
ns
Row cycle time
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
70
65
ns
CLK
-
1
2,5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
2
2 CLK + 20 ns
1
CLK
CLK
CLK
2
1
2
Col. address to col. address delay
1
3
CAS latency=3
CAS latency=2
2
Number of valid output data
ea
4
1
-
URL:www.hbe.co.kr
REV.1.0 (August.2002).
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HANBit Electronics Co.,Ltd
HANBit
HSD32M64D16R
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
SYMBO
L
-1H
-1L
-13
PARAMETER
UNIT
ns
NOTE
1
MIN
10
10
6
MAX
MIN
10
MAX
MIN
7.5
-
MAX
CLK cycle time CAS latency=3
CAS latency=2
tCC
tSAC
tOH
1000
1000
1000
12
CLK to valid
output delay
``Output data
hold time
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
6
7
5.4
-
ns
1,2
1,2
6
3
3
3
2.7
-
ns
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
3
3
3
2
1
1
6
7
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
2
1
1
3
tSS
tSH
tSLZ
2
Input hold time
1
CLK to output in Low-Z
1
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
6
6
5.4
-
tSHZ
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
URL:www.hbe.co.kr
REV.1.0 (August.2002).
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HANBit
HSD32M64D16R
SIMPLIFIED TRUTH TABLE
/R
A
S
/C
A
S
D
Q
M
CKE
CKE
n
/C
E
/W
E
BA
0,1
A10/
AP
A11
A9~A0
n-1
COMMAND
NOTE
Register
Refresh
Mode register set
Auto refresh
H
X
H
L
L
L
L
L
L
X
OP code
X
1,2
3
H
L
L
H
X
Entry
3
Self
refres
h
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
X
X
X
X
3
Bank active & row addr.
H
V
V
Row address
Auto
precharge
Read &
column
address
L
H
L
Column
Address
(A0 ~ A9)
4
4,5
4
disable
Auto
H
H
X
X
L
L
H
H
L
L
H
H
X
X
precharge
precharge
precharge
eable
Auto
Write &
column
address
Column
Address
(A0 ~ A9)
disable
Auto
V
L
L
L
H
4,5
6
enable
Burst Stop
H
H
X
X
L
L
H
L
H
H
X
X
X
Precharg Bank selection
V
X
L
X
e
All banks
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
X
H
L
Entry
H
Precharge power
down mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
X
7
H
L
X
H
X
X
H
No operation command
H
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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REV.1.0 (August.2002).
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HANBit Electronics Co.,Ltd
HANBit
HSD32M64D16R
TIMING DIAGRAMS
td, tr = Delay of register (74LVC162835)
Notes : 1.In case of module timing, command cycles 1CLK with respect to external input timing at the address
and input signal because of the buffering in register (74LVC162835). Therefore, Input/Output signals of read/write function
should be issued 1CLK earlier as compared to Unbuffered DIMMs.
2. DIN is to be issued 1 clock after write command in external timing because DIN is issued directly to module.
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REV.1.0 (August.2002).
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HANBit Electronics Co.,Ltd
HANBit
HSD32M64D16R
PACKAGING INFORMATION
Unit : inch [mm]
Front – Side
TOLERANCE
:
±0.008 [ ±0.20 ]
Rear-Side
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REV.1.0 (August.2002).
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HANBit Electronics Co.,Ltd
HANBit
HSD32M64D16R
ORDERING INFORMATION
Part Number
Density
Org.
Package
Ref.
Vcc
MODE
MAX.frq
CL3
100MHz
CL2
HSD32M72D16R-10L
HSD32M72D16R – 10
HSD32M72D16R – 12N
HSD32M72D16R – 13N
256MByte
256MByte
256MByte
256MByte
32M x 64 168 Pin-DIMM
32M x 64 168 Pin-DIMM
32M x 64 168 Pin-DIMM
32M x 64 168 Pin-DIMM
4K
4K
4K
4K
3.3V
3.3V
3.3V
3.3V
SDRAM
SDRAM
SDRAM
SDRAM
100MHz
CL3
125MHz
CL3
133MHz
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REV.1.0 (August.2002).
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HANBit Electronics Co.,Ltd
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HANBIT
HSD32M72D18A-13
Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V
HANBIT
HSD32M72D18A-F10
Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V
HANBIT
HSD32M72D18A-F10L
Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V
HANBIT
HSD32M72D18A-F12
Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V
HANBIT
HSD32M72D18A-F13
Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V
HANBIT
HSD32M72D18P
Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V
HANBIT
HSD32M72D18P-10
Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V
HANBIT
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