HS-1840RH [HARRIS]
Rad-Hard 16 Channel CMOS Analog Rad-Hard 16 Channel CMOS Analog; 抗辐射16通道CMOS模拟抗辐射16通道CMOS模拟
| 型号： | HS-1840RH |
| 厂家： | 
HARRIS CORPORATION |
| 描述： | Rad-Hard 16 Channel CMOS Analog Rad-Hard 16 Channel CMOS Analog |
| 文件： | 总13页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Semiconductor
HS-1840RH
Rad-Hard 16 Channel CMOS Analog
Multiplexer with High-Z Analog Input Protection
September 1997
Features
Description
• Radiation Environment
The HS-1840RH is a radiation hardened, monolithic 16
channel multiplexer constructed with the Harris Linear
Dielectric Isolation CMOS process. It is designed to provide
a high input impedance to the analog source if device power
fails (open) or the analog signal voltage inadvertently
exceeds the supply rails during powered operation. Excellent
for use in redundant applications, since the secondary
device can be operated in a standby unpowered mode
affording no additional power drain. More significantly, a very
high impedance exists between the active and inactive
devices preventing any interaction. One of sixteen channel
selection is controlled by a 4-bit binary address plus an
Enable-Inhibit input which conveniently controls the ON/OFF
operation of several multiplexers in a system. All digital
inputs have electrostatic discharge protection.
(γ)
- Gamma Rate
1 x 108 RAD(Si)/s
tle (HS-1840RH)
- Gamma Dose (γ) 2 x 105 RAD(Si)
bject (Rad-Hard 16 Channel CMOS Analog
• Low Power Consumption
tiplexer with High-Z Analog Input Protection)
• Fast Access Time 1000ns
thor ()
ywords ()
eator ()
• High Analog Input Impedance 500MΩ
During Power Loss (Open)
• Dielectrically Isolated Device Islands
• Excellent In Hi-Rel Redundant Systems
OCINFO pdfmark
• Break-Before-Make Switching
• No Latch-Up
ageMode /UseOutlines
Ordering Information
OCVIEW pdfmark
The HS-1840RH has been specifically designed to meet
exposure to radiation environments. It is available in a 28
lead Ceramic Sidebraze dual-in-line package and 28 lead
Ceramic Flatpack. It is guaranteed operational from -55oC to
+125oC.
PART
TEMP.
PKG.
NO.
o
NUMBER
RANGE ( C)
PACKAGE
HS1-1840RH-Q
-55 to 125 28 Ld CERDIP
-55 to 125 28 Ld CERDIP
-55 to 125 28 Ld CERDIP
HS1-1840RH-8
HS1-1840RH/Proto
HS1-1840RH/Sample
HS9-1840RH-Q
25
28 Ld CERDIP
-55 to 125 28 Ld FP
-55 to 125 28 Ld FP
-55 to 125 28 Ld FP
HS9-1840RH-8
HS9-1840RH/Proto
HS9-1840RH/Sample
25
28 Ld FP
Pinouts
HS1-1840RH 28 LEAD SIDEBRAZE CERDIP
HS9-1840RH 28 LEAD CERAMIC SIDEBRAZE CASE FLATPACK
CASE OUTLINE GDIP1-T28, COMPLIANT TO MIL-STD-
OUTLINE CDFP3-F28, COMPLIANT TO MIL-STD-1835 PACKAGE
1835 PACKAGE
TOP VIEW
TOP VIEW
+VS
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OUT
-VS
+VS
NC
1
2
3
4
5
6
7
8
9
28 OUT
27 -VS
26 IN 8
25 IN 7
24 IN 6
23 IN 5
22 IN 4
21 IN 3
2
NC
IN 8
3
IN 16
IN 7
4
NC
IN 15
IN 6
5
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 14
IN 5
6
IN 13
IN 4
7
IN 12
IN 3
8
IN 11
IN 2
9
IN 10
IN 1
10
11
12
13
14
IN 9
ENABLE
ADDR A0
ADDR A1
ADDR A2
20
IN 2
GND
(+5VS) VREF
ADDR A3
IN 10 10
IN 9 11
19 IN 1
18 ENABLE
17 ADDR A0
16 ADDR A1
15 ADDR A2
GND 12
(+5VS) VREF 13
ADDR A3 14
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 3992.1
Spec Number 518022
Copyright © Harris Corporation 1997
1
HS-1840RH
Functional Diagram
IN 1
A0
1
P
A1
A2
A3
DIGITAL
ADDRESS
OUT
1
P
EN
IN 16
ADDRESS INPUT
BUFFER AND
LEVEL SHIFTER
DECODERS
MULTIPLEX
SWITCHES
Truth Table
A3
A2
X
L
A1
X
L
A0
X
L
EN
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
“ON” CHANNEL
X
L
None
1
L
L
L
H
L
2
L
L
H
H
L
3
L
L
H
L
4
L
H
H
H
H
L
5
L
L
H
L
6
L
H
H
L
7
L
H
L
8
H
H
H
H
H
H
H
H
9
L
L
H
L
10
11
12
13
14
15
16
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
Spec Number 518022
2
Specifications HS-1840RH
Absolute Maximum Ratings
Reliability Information
Supply Voltage Between Pins 1 and 27 . . . . . . . . . . . . . . . . . . +40V Thermal Resistance . . . . . . . . . . . . . . . . . .
θ
θ
JC
JA
o
o
+VSUPPLY to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V
-VSUPPLY to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20V
Sidebraze Package . . . . . . . . . . . . . . . . . 83.1 C/W 19.1 C/W
Flatpack Package . . . . . . . . . . . . . . . . . . 49.1 C/W 16.5 C/W
o
o
VREF to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V Total Power Dissipation (Note)
Analog Input Overvoltage
Sidebraze CerDIP Package. . . . . . . . . . . . . . . . . . . . . . . 1600mW
+VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25V (Power On/Off)
-VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V (Power On/Off)
Digital Input Overvoltage
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . 1400mW
ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
o
o
+VEN, +VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VREF +4V
-VEN, -VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -4V
Continuous Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mA
NOTE: For DIP Derate 20.4mW/ C above T = +95 C
A
o
o
For Flatpack Derate 18.5mW/ C above T = +95 C
A
o
o
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C
o
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +275 C
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage (±VSUPPLY) . . . . . . . . . . . . . . . . . . . . ±15V Logic Low Level (VAL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8V
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C Logic High Level (VAH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V
VREF (Pin 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested. Unless Otherwise Specified: V- = -15V, V+ = +15V, VREF = +5V, VAH = +4.0V, VAL = 0.8V
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
UNITS
o
o
Analog Signal Range
VS
7, 8A, 8B
-55 C, +25 C,
-5
+15
V
o
+125 C
o
o
Input Leakage
Current, Address, or
Enable Pins
IAH
IAL
Measure Inputs Sequentially
Ground All Unused Pins
1, 2, 3
-55 C, +25 C,
-1000 1000
nA
o
+125 C
o
Leakage Current Into
the Source Terminal of
an “Off” Switch
+IS(OFF)
-IS(OFF)
VS = +10V, All Unused Inputs
and Output = -10V, VEN = 4V
1
2, 3
1
+25 C
-10
-100
-10
10
100
10
nA
nA
nA
nA
nA
nA
o
o
+125 C,-55 C
o
VS = -10V, All Unused Inputs,
Output = +10V, VEN = 4V
+25 C
o
o
2, 3
1
+125 C, -55 C
-100
-50
100
50
o
Leakage Current into
the Source Terminal of
an “Off” Switch With
Power “Off”
+IS(OFF)
Power Off
V+, V-, VREF, A0, A1, A2, A3,A4,
EN = GND, Unused Inputs Tied to
GND, VS = +25V
+25 C
o
o
2, 3
+125 C, -55 C
-100
100
o
o
Leakage Current Into
the Source Terminal of
an “Off” Switch With
Overvoltage Applied
+IS(OFF)
VS = +25V, VD = 0V, VEN = 4V
1, 2, 3
1, 2, 3
-55 C, +25 C,
-1000 1000
-1000 1000
nA
nA
o
Overvoltage All Unused Inputs Tied to GND
+125 C
o
o
-IS(OFF) VS = -25V, VD = 0V, VEN = 4V All
Overvoltage Unused Inputs Tied to GND
-55 C, +25 C,
o
+125 C
o
Leakage Current Into
the Drain Terminal of
an “Off” Switch
+ID(OFF)
-ID(OFF)
+ID(OFF)
VD = +10V, VEN = 4V All Unused
Inputs = -10V
1
2, 3
1
+25 C
-10
-100
-10
10
100
10
nA
nA
nA
nA
nA
o
o
+125 C, -55 C
o
VD = -10V, VEN = 4V All Unused
Inputs = +10V
+25 C
o
o
2, 3
1, 2, 3
+125 C, -55 C
-100
100
o
o
Leakage Current Into
the Drain Terminal of
an “Off” Switch With
Overvoltage Applied
VS = +25V, Measure VD,
-55 C, +25 C,
-1000 1000
-1000 1000
o
Overvoltage VEN = 4V, All Unused Inputs to
GND
+125 C
o
o
-ID(OFF)
VS = -25V, Measure VD,
1, 2, 3
-55 C, +25 C,
nA
o
Overvoltage All Unused Inputs to GND
+125 C
Spec Number 518022
3
Specifications HS-1840RH
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Guaranteed and 100% Tested. Unless Otherwise Specified: V- = -15V, V+ = +15V, VREF = +5V, VAH = +4.0V, VAL = 0.8V
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
-10
MAX
10
UNITS
nA
o
Leakage Current from
an “On” Driver into the
Switch (Drain & Source)
+ID(ON)
VS = +10V, VD = +10V, VEN =
0.8V All Unused Inputs = -10V
1
2, 3
1
+25 C
o
o
+125 C, -55 C
-100
-10
100
10
nA
o
-ID(ON)
VS = -10V, VD = -10V, VEN =
0.8V, All Unused Inputs = +10V
+25 C
nA
o
o
2, 3
1, 2, 3
+125 C, -55 C
-100
50
100
1000
nA
o
o
Switch On Resistance
+15V R(ON) VS = +15V, ID = -1mA,
VEN = 0.8V
-55 C, +25 C,
Ω
o
+125 C
o
o
-5V R(ON)
VS = -5V, ID = +1mA, VEN = 0.8V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-55 C, +25 C,
50
50
-
4000
2500
0.5
-
Ω
o
+125 C
o
o
+5V R(ON) VS = +5V, ID = -1mA, VEN = 0.8V
-55 C, +25 C,
Ω
o
+125 C
o
o
Positive Supply
Current
I(+)
I(-)
VEN = 0.8V
VEN = 0.8V
VEN = 4.0V
VEN = 4.0V
-55 C, +25 C,
mA
mA
mA
mA
o
+125 C
o
o
Negative Supply
Current
-55 C, +25 C,
-0.5
-
o
+125 C
o
o
Positive Standby
Supply Current
+ISBY
-ISBY
-55 C, +25 C,
0.5
-
o
+125 C
o
o
Negative Standby
Supply Current
-55 C, +25 C,
-0.5
o
+125 C
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested. Unless Otherwise Specified: V- = -15V, V+ = +15V, VREF = +5V, VAH = +4.0V, VAL = 0.8V
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
-
UNITS
ns
o
Break-Before-Make
Time Delay
TD
RL = 1000Ω, CL = 50pF
9
+25 C
25
5
-
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Propagation Delay
Times: Address Inputs
to I/O Channels
TON(A),
TOFF(A)
RL = 10kΩ, CL = 50pF
RL = 1000Ω, CL = 50pF
+25 C
600
1000
ns
o
o
10, 11
+125 C, -55 C
-
ns
o
Enable to I/O
TON(EN),
TOFF(EN)
9
+25 C
-
-
600
ns
ns
o
o
10, 11
+125 C, -55 C
1000
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized At: V- = -15V, V+ = +15V, VREF = +5V, VAH = +4.0V, VAL = 0.8V, Unless Otherwise Specified
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTE
TEMPERATURE
MIN
MAX
UNITS
o
Capacitance Address
Input
CA
+VS = -VS = 0V, f = 1MHz
1
+25 C
-
7
pF
o
Capacitance Channel
Input
CS(OFF)
+VS = -VS = 0V, f = 1MHz
+VS = -VS = 0V, f = 1MHz
1
1
1
+25 C
-
-
5
50
-
pF
pF
dB
o
Capacitance Channel
Output
CD(OFF)
TOFF(EN)
+25 C
o
Off Isolation
VISO
VEN = 4.0V, f = 200kHz, CL = 7pF,
+25 C
45
RL = 1kΩ, VS = 3.0VRMS
NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters and not directly tested. These parameters are
characterized upon initial design and after major process and/or design changes.
Spec Number 518022
4
Specifications HS-1840RH
TABLE 4. POST 200K RAD(Si) ELECTRICAL CHARACTERISTICS
Tested, per MIL-STD-883. Unless Otherwise Specified: V- = -15V, V+ = +15V, VREF = +5V, VAH = +4.5V, VAL = 0.5V
LIMITS
MIN MAX
-1000 1000
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS
UNITS
o
Input Leakage Current,
Address, or Enable Pins
IAH
IAL
Measure Inputs Sequentially,
Ground All Unused Pins
1
1
1
1
+25 C
nA
o
Leakage Current Into
the Source Terminal of
an “Off” Switch
+IS(OFF)
VS = +10V, All Unused Inputs
and Output = -10V, VEN = 4.5V
+25 C
-100
-100
-100
100
100
100
nA
nA
nA
o
-IS(OFF)
VS = -10V, All Unused Inputs and
Output = +10V, VEN = 4.5V
+25 C
o
Leakage Current into
the Source Terminal of
an “Off” Switch With
Power “Off”
+IS(OFF)
Power Off
V+, V-, VREF, A0, A1, A2, A3, A4,
EN = GND, Unused Inputs Tied to
GND, VS = +25V
+25 C
o
Leakage Current Into
the Source Terminal of Overvoltage All Unused Inputs Tied to GND
an “Off” Switch With
+IS(OFF)
VS = +25V, VD = 0V, VEN = 4.5V
1
1
1
1
1
+25 C
-1500 1500
-1500 1500
nA
nA
nA
nA
nA
o
-IS(OFF)
VS = -25V, VD = 0V, VEN = 4.5V
+25 C
Overvoltage Applied
Overvoltage All Unused Inputs Tied to GND
o
Leakage Current Into
the Drain Terminal of
an “Off” Switch
+ID(OFF)
-ID(OFF)
+ID(OFF)
VD = +10V, VEN = 4.5V
All Unused Inputs = -10V
+25 C
-100
-100
100
100
o
VD = -10V, VEN = 4.5V
All Unused Inputs = +10V
+25 C
o
Leakage Current Into
the Drain Terminal of
an “Off” Switch With
Overvoltage Applied
VS = +25V, Measure VD,
+25 C
-1000 1000
-1000 1000
Overvoltage VEN = 4.5V
All Unused Inputs to GND
o
-ID(OFF)
VS = -25V, Measure VD,
Overvoltage VEN = 4.5V
All Unused Inputs to GND
1
1
1
+25 C
nA
nA
nA
o
Leakage Current from
an “On” Driver into the
Switch (Drain & Source)
+ID(ON)
VS = +10V, VD = +10V,
VEN = 0.5V
All Unused Inputs = -10V
+25 C
-100
-100
100
100
o
-ID(ON)
VS = -10V, VD = -10V,
VEN = 0.5V
+25 C
All Unused Inputs = +10V
o
Switch On Resistance
+15V R(ON) VS = +15V, ID = -1mA, VEN = 0.5V
-5V R(ON) VS = -5V, ID = +1mA, VEN = 0.5V
+5V R(ON) VS = +5V, ID = -1mA, VEN = 0.5V
1
1
1
1
+25 C
50
50
50
-
1000
4000
2500
0.50
Ω
Ω
o
+25 C
o
+25 C
Ω
o
Positive Supply
Current
I(+)
VEN = 0.5V
+25 C
mA
o
Negative Supply
Current
I(-)
VEN = 0.5V
1
1
1
9
9
+25 C
-0.50
-
0.50
-
mA
mA
mA
ns
o
Positive Standby
Supply Current
+I(SBY)
-I(SBY)
TD
VEN = 4.5V
+25 C
-
o
Negative Standby
Supply Current
VEN = 4.5V
+25 C
-0.50
o
Make-Before-Break
Time Delay
RL = 1000Ω, CL = 50pf
RL = 10KΩ, CL = 50pf
+25 C
5
-
-
o
Propagation Delay
Times: Address Inputs
to I/O Channels
TON (A)
TOFF (A)
+25 C
3000
ns
o
Enable to I/O
TON (EN)
RL = 1000Ω, CL = 50pf
9
+25 C
-
3000
ns
TOFF (EN)
Spec Number 518022
5
Specifications HS-1840RH
TABLE 5. DC POST BURN-IN DELTA ELECTRICAL CHARACTERISTICS
Guaranteed, per MIL-STD-883, Method 1019. Unless Otherwise Specified: V- = -15V, V+ = +15V, VREF = +5V, VAH = +4.0V, VAL = 0.8V
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
UNITS
o
Input Leakage Current,
Address, or Enable
Pins
IAH
IAL
Measure Inputs Sequentially,
Ground All Unused Pins
1
+25 C
-100
100
nA
o
Leakage Current Into
the Source Terminal of
an “Off” Switch
+IS(OFF)
-IS(OFF)
+ID(OFF)
-ID(OFF)
+ ID(ON)
VS = +10V, All Unused Inputs &
Output = -10V, VEN = 4.0V
1
1
1
1
1
+25 C
-20
-20
-20
-20
-20
20
20
20
20
20
nA
nA
nA
nA
nA
o
VS = -10V, All Unused Inputs &
Output = +10V, VEN = 4.0V
+25 C
o
Leakage Current Into
the Drain Terminal of
an “Off” Switch
VD = +10V, VEN = 4.0V
All Unused Inputs = -10V
+25 C
o
VD = -10V, VEN = 4.0V
All Unused Inputs = +10V
+25 C
o
Leakage Current from
an “On” Driver into the
Switch (Drain & Source)
VS = +10V, VD = +10V,
VEN = 0.8V
All Unused Inputs = -10V
+25 C
o
-ID(ON)
VS = -10V, VD = -10V,
VEN = 0.8V
1
+25 C
-20
20
nA
All Unused Inputs = +10V
o
Switch On Resistance
+15V R(ON) VS = +15V, ID = -1mA,
VEN = 0.8V
1
1
1
1
1
1
+25 C
-150
-250
-50
150
250
50
Ω
o
-5V R(ON)
VS = -5V, ID = +1mA,
VEN = 0.8V
+25 C
Ω
o
Positive Supply
Current
I(+)
VEN = 0.8V
VEN = 0.8V
VEN = 4.0V
VEN = 4.0V
+25 C
µA
µA
µA
µA
o
Negative Supply
Current
I(-)
+25 C
-50
50
o
Positive Standby
Supply Current
+ISBY
-ISBY
+25 C
-50
50
o
Negative Standby
Supply Current
+25 C
-50
50
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
-Q SUBGROUPS
-8 SUBGROUPS
Initial Test
Interim Test
PDA
100%/5004
100%/5004
1
1
N/A
1
1
100%/5004
1
Final Test
Group A
Group B
100%/5004
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Samples/5005
Samples/5005
Samples/5005
Samples/5005
Samples/5005
Samples/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
B5
1, 2, 3
1, 7
N/A
N/A
Others
Group C
N/A
1, 2, 3
1, 7
Group D
1, 7
Group E, Subgroup 2
1, 7
1, 7
Spec Number 518022
6
HS-1840RH
Performance Characteristics and Test Circuits
ACCESS TIME vs LOGIC LEVEL (HIGH)
4.0V
0.8V
A3
A2
A1
A0
IN 1
15V, 0V
50%
IN 2 -
IN 15
VA
50Ω
VA
IN 16
0V, 15V
VOUT
0.8V
EN
GND
VOUT
50pF
10K
50%
tA
0V
BREAK-BEFORE-MAKE DELAY (tOPEN)
4.0V
+5V
A3
A2
A1
A0
EN
IN 1
IN 2 -
IN 15
VA
50Ω
0.8V
VA
IN 16
OUT
VOUT
VOUT
0.8V
GND
50%
50%
1K
50pF
tOPEN
ENABLE DELAY (tON(EN), tOFF(EN))
4.0V
VA
+10V
A3
A2
A1
A0
IN 1
0.8V
IN 2 -
IN 16
OUTPUT
10%
VOUT
EN
90%
1K
50pF
VA
50Ω
VOUT
tON(EN)
tOFF(EN)
Spec Number 518022
7
HS-1840RH
Burn-In/Life Test Circuits
R
R
+VS
+VS
-VS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
-VS
2
R
R
3
3
R
R
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
10
11
F5
GND
GND
F4
12
13
14
F1
F3
F2
VR
R
DYNAMIC BURN-IN AND LIFE TEST CIRCUIT
STATIC BURN-IN TEST CIRCUIT
NOTES:
NOTES:
1
VS+ = +15.5V ±0.5V, VS- = -15.5V ±0.5V
R = 1kΩ ±5%, / W
4
R = 1kΩ ±5%
C1 = C2 = 0.01µF minimum, 1 each per socket, minimum
VS+ = 15.5V ±0.5V, VS- = -15.5V ±0.5V, VR = 15.5 ±0.5V
C1 = C2 = 0.01µF ±10%, 1 each per socket, minimum
D1 = D2 = 1N4002, 1 each per board, minimum
Input Signals: square wave, 50% duty cycle, 0V to 15V peak ±10%
F1 = 100kHz; F2 = F1/2; F3 = F1/4; F4 = F1/8; F5 = F1/16
NOTES:
1. The above test circuits are utilized for all package types.
2. The Dynamic Test Circuit is utilized for all life testing.
Irradiation Circuit
HS-1840RH 28 LEAD DIP
+15V
1
2
28
-15V
NC
NC
27
26
25
24
23
22
21
20
19
18
17
16
15
1KΩ
3
+1V
4
5
6
7
8
9
10
11
12
13
14
+5V
NOTE: All irradiation testing is performed in the 28 lead CerDIP package.
Spec Number 518022
8
HS-1840RH
Schematic Diagrams
ADDRESS INPUT BUFFER AND LEVEL SHIFTER
V
REF
LEVEL SHIFTER
V+
P
P
P
P
P
P
P
P
P
LEVEL
SHIFTED
ADDRESS
TO
OVERVOLTAGE
PROTECTION
R2
P
N
R5
R6
R7
DECODE
V
REF
LEVEL
R3
R4
SHIFTED
ADDRESS
TO
R8
D2
R1
N
N
N
N
N
N
N
N
N
ADD
IN.
DECODE
200Ω
D1
V-
ADDRESS DECODER
MULTIPLEX SWITCH
V+
+V
P
P
P
P
P
TO
SWITCH
N
N
N
N
N
P
N
P
N
IN
A0 OR A0
S
D
P
FROM
DECODE
A1 OR A1
A2 OR A2
OUT
A3 OR A3
ENABLE
V-
V-
Spec Number 518022
9
HS-1840RH
Harris - Space Level Product Flow
SEM - Traceable to Diffusion Method 2018, Modified
Room Temperature Electrical Tests (T1)
This device does not meet MIL-STD-883 Method 2018.3 Class Burn-In Delta Calculation (T0-T1)
S minimum metal step coverage of 50%. The metal does meet
PDA Calculation 3% Functional
5% Subgroups 1, 7, ∆
Dynamic Burn-In 240 Hours at +125oC or equivalent
the intent of the Class S requirement by meeting the current
density requirement of <2E5 A/cm2. Calculation based on con-
tinuous current of 10mA. Data can be provided upon request.
Method 1015 Condition A
Wafer Lot Acceptance Method 5007
Electrical Tests Subgroups 1, 7, 9 (T2)
Burn-In Delta Calculation (T0 - T2)
Internal Visual Inspection (Note 1)
Gamma Radiation Assurance Tests Method 1019
100% Nondestructive Bond Pull Method 2023
Customer Pre-Cap Visual Inspection (Notes 1, 2)
Temperature Cycling Method 1010 Condition C
Constant Acceleration Method 2001 Y1 30KG
PDA Calculation 3% Functional
5% Subgroups 1, 7, ∆
Electrical Test +125oC, -55oC
Alternate Group A Inspection Method 5005
Fine and Gross Leak Tests Method 1014
Customer Source Inspection (Note 2)
Group B Inspection (Notes 2, 4) Method 5005
Group D Inspection (Notes 2, 4) Method 5005
External Visual Inspection Method 2009
Data Package Generation (Note 3)
Particle Impact Noise Detection Method 2020,
Condition A 20G
Marking and Serialization
X-Ray Inspection Method 2012
Initial Electrical Tests (T0)
Static Burn-In 72 Hour, +125oC (Min) Method 1015
Condition A
NOTES:
1. Visual Inspection is performed to MIL-STD-883 Method 2010, Condition A.
2. These steps are optional, and should be listed on the purchase order if required.
3. Data package contains: Assembly Attributes (post seal)
o
o
o
Test Attributes (includes Group A) -55 C, +25 C, +125 C
Shippable Serial Number List
Radiation Testing Certificate of Conformance
Wafer Lot Acceptance Report (includes SEM report)
X-Ray Report and Film
Test Variables Data, (Table 5 Parameters only)
o
+25 C Initial Test
o
+25 C Interim Test 1
o
+25 C Interim Test 2
o
+25 C Delta Over Burn-In
4. Group B data package contains Attributes Data and Variables Data, (Table 5 Parameters only). Group D data package contains Attributes only.
Harris -8 Product Flow
Internal Visual Inspection, Alternate Condition B (Note 1)
Gamma Radiation Assurance Tests Method 1019
Customer Pre-Cap Visual Inspection (Notes 1, 2)
Temperature Cycling Method 1010 Condition C (50 Cycles)
Constant Acceleration Method 2001 Y1 30kG
Fine and Gross Leak Tests Method 1014
Marking
Electrical Tests Subgroups 1, 7, 9 (T1) Method 5004
PDA Calculation 5% Subgroups 1, 7 Method 5004
Electrical Test +125oC, -55oC Method 5004
Alternate Group A Inspection Method 5005
Customer Source Inspection (Note 2)
Group B Inspection (Notes 2, 4) Method 5005 (Optional)
Group C Inspection (Notes 2, 4) Method 5005 (Optional)
Group D Inspection (Notes 2, 4) Method 5005 (Optional)
External Visual Inspection Method 2009
Initial Electrical Tests (T0)
Dynamic Burn-In 160 Hours, +125oC Method 1015 or
Equivalent Condition D
Data Package Generation (Note 3)
NOTES:
1. Visual inspection is performed to MIL-STD-883 Method 2010, Alternate Condition B.
2. These steps are optional, and should be listed on the purchase order if required.
3. Data Package Contents:
o
o
o
Test Attributes (including Group A) -55 C, +25 C, +125 C
Radiation Testing Certificate of Conformance
4. Group B, C and D data package contains Attributes Data only.
Spec Number 518022
10
HS-1840RH
Metallization Topology
DIE DIMENSIONS:
110 x 159 x 11mils
METALLIZATION:
Type: Al
Thickness: 12.5kÅ ± 2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ± 1kÅ
DIE ATTACH:
Material: Gold Eutectic
Temperature: Sidebrazed CerDIP - 460oC (Max)
Flatpack - 460oC (Max)
WORST CASE CURRENT DENSITY: Modified SEM
LEAD TEMPERATURE (10s Soldering): <275oC
PROCESS: CMOS-DI
Metallization Mask Layout
HS-1840RH
ENABLE
IN8
-V
A0
A1
OUT
A2
A3
VREF
+V
IN16
GND
Spec Number 518022
11
HS-1840RH
Ceramic Dual-In-Line Frit Seal Packages (CerDIP)
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
c1 LEAD FINISH
-D-
E
-A-
INCHES MILLIMETERS
MIN
BASE
METAL
(c)
SYMBOL
MAX
0.232
0.026
0.023
0.065
0.045
0.018
0.015
1.490
0.610
MIN
-
MAX
5.92
NOTES
b1
A
b
-
-
M
M
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
0.66
2
-B-
(b)
b1
b2
b3
c
0.58
3
SECTION A-A
S
S
S
D
bbb
C A - B
D
1.65
-
1.14
4
BASE
PLANE
Q
0.46
2
A
-C-
SEATING
PLANE
c1
D
0.38
3
L
α
37.85
15.49
5
S1
b2
eA
A A
e
E
0.500
12.70
5
e
0.100 BSC
2.54 BSC
-
b
C A - B
eA/2
c
eA
eA/2
L
0.600 BSC
0.300 BSC
15.24 BSC
7.62 BSC
-
M
S
S
M
S
S
D
ccc
D
aaa
C A - B
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
28
28
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
Spec Number 518022
12
HS-1840RH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B)
28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
A
e
INCHES MILLIMETERS
MIN
PIN NO. 1
ID AREA
SYMBOL
MAX
0.115
0.022
0.019
0.009
0.006
0.740
0.520
0.550
-
MIN
1.14
0.38
0.38
0.10
0.10
-
MAX
2.92
0.56
0.48
0.23
0.15
18.80
13.21
13.97
-
NOTES
D
A
b
0.045
0.015
0.015
0.004
0.004
-
-
-
-A-
-B-
S1
b1
c
-
-
b
c1
D
-
E1
3
-
M
S
S
M
S
C
S
D
0.004
Q
H
A - B
D
0.036
H
A - B
E
0.460
-
11.68
-
E
E1
E2
E3
e
3
-
-D-
A
0.180
0.030
4.57
0.76
-H-
-C-
-
-
7
-
L
E2
L
E3
E3
0.050 BSC
1.27 BSC
SEATING AND
BASE PLANE
c1
LEAD FINISH
k
0.008
0.250
0.026
0.00
-
0.015
0.370
0.045
-
0.20
6.35
0.66
0.00
-
0.38
9.40
1.14
-
2
-
L
BASE
METAL
Q
S1
M
N
8
6
-
(c)
b1
M
0.0015
0.04
M
28
28
-
(b)
SECTION A-A
Rev. 0 5/18/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
Spec Number 518022
13
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