HB28A512IA1_技术文档

HB28A896IA1/HB28A512IA1

IDE Card

ADE-203-1330 (Z)

Preliminary

Rev. 0.0

May. 14, 2002

Description

HB28A896IA1, HB28A512IA1 are IDE card. This card complies with ATA-5 specification standard and is

suitable for the usage of data storage memory medium for PC or any other electric equipment. This card is

equipped with Hitachi 256 Mega bit Flash memory HN29W51214WT8SR. By using this card it is possible to

operate good performance for a system which have ATA interface.

Features

•

Conform to ANSI AT Attachment-5 (ATA-5) specification standard

Control maximum 28 pieces of Hitachi 256 Mega bit Flash memory

5 V power supplies are used

Support density 896 Mega bytes and 512 Mega bytes

Data write is 300,000 cycle

High reliability based on internal ECC (Error Correcting Code) function

Data reliability is less than 1 error in 10¹⁴bits read

Preliminary: The specification of this device are subject to change without notice. Please contact your

nearest Hitachi’s Sales Dept. regarding specification.

HB28A896IA1, HB28A512IA1

Card Line Up*¹

Total sectors/ Sectors/

Number of Number of

Type No.

Card density Capacity*⁴

card*³

track*²

63

head

cylinder

HB29A512IA1 896 MB

HB29A896IA1 512 MB

896,974,848 byte

512,483,328 byte

1,751,904

1,000,944

16

1738

63

16

993

Notes: 1. These data are written in ID.

2. Total tracks = number of head × number of cylinder.

3. Total sectors/card = sectors/track × number of head × number of cylinder.

4. It is the logical address capacity including the area which is used for file system.

2

HB28A896IA1, HB28A512IA1

Card Pin Assignment

Pin No.

1

Signal name

Pin No.

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

Signal name

Pin No.

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

Signal name

GND

D3

2

3

D4

4

D5

A2

5

D6

A1

VCC

6

D7

A0

7

-CS0

D0

8

D1

9

D2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

-IOIS16

GND

-CSEL

1

*

-RESET

IORDY

DMARQ

-DMACK

-DASP

-PDIAG

D8

1

*

D11

D12

D13

D14

D15

-CS1

INTRQ

V_CC

D9

1

*

D10

1

-IORD

-IOWR

*

GND

Note: 1. Host system should not connect these pin.

3

HB28A896IA1, HB28A512IA1

Card Pin Explanation

Host Interface Pin Explanation

Signal name

Direction Pin No.

Description

-RESET

I

58

This signal is active low host reset pin. Once the host asserts

-RESET, the host must keep -RESET asserting for at least 25

µs.

A2 to A0

I

27, 28, 29 Address bus of Host I/F is A2 to A0. A2 is MSB and A0 is LSB.

D15 to D0

I/O

41, 40, 39 Data bus of Host I/F is D15 to D0. D0 is the LSB of the even

38, 37, 66 byte of the word. D8 is the LSB of the odd byte of the word.

65, 64, 6

5, 4, 3

2, 32, 31

30

-CS0

-CS1

I

7, 42

-CS1 is used for selecting the Alternate Status Register and

the Device Control Register. -CS0 is used for the other task

file registers.

-IOWR

45

-IOWR is used for control of write data in I/O task file area.

STOP

(Ultra DMA mode)

This signal must be negated prior to initiation of an Ultra DMA

burst. And this signal must be negated before data is

transferred in an Ultra DMA burst. Assertion during an Ultra

DMA burst flowing indicates the termination of the Ultra DMA

burst.

-IORD

I

44

-IORD is used for control of read data in I/O task file area.

-HDMARDY

(Ultra DMA data-in)

-HDMARDY is a data flow control signal. The host shall assert

this signal to indicate that the host is ready to receive Ultra

DMA data-in bursts. The host may negate this signal to

indicate that the host pauses an Ultra DMA data-in burst.

HSTROBE

(Ultra DMA data-out)

HSTROBE is a data strobe signal. Both the rising and falling

edges of HSTROBE latch the data of D15 to D0 into this card.

Stopping generating HSTROBE edges indicates that the host

pauses an Ultra DMA data-out burst.

-DMACK

-IOCS16

I

61

33

This signal is used for response to asserting DMARQ to initiate

DMA transfers.

O

This output signal is asserted low when this device is expecting

a word data transfer cycle. Initial mode is 16-bit. If the user

issues a Set Feature Command to put the device in Byte

access mode, the card permits 8-bit accesses.

INTRQ

O

16

60

This signal is the active high Interrupt Request to the host.

DMARQ

This signal is asserted high when the card is ready to DMA

data transfers.

-PDIAG

I/O

63

-PDIAG is the Pass Diagnostic signal in Master/Slave

handshake protocol.

4

HB28A896IA1, HB28A512IA1

Signal name

Direction Pin No.

Description

IORDY

O

59

IORDY is used at PIO modes 3 and above. IORDY is negated

to extend the host transfer cycle of any host register access

(Read or Write) when the device is not ready to respond to a

data transfer request.

DSTROBE

(Ultra DMA data-in)

DSTROBE is a data strobe signal. The host latches the data

of D15 to D0 at both the rising and falling edge of DSTROBE.

Stopping generating DSTROBE edges indicates that the

device pauses an Ultra DMA data-in burst.

-DDMARDY

(Ultra DMA data-out)

-DDMARDY is a data flow control signal. The card asserts this

signal to indicate that the device is ready to receive Ultra DMA

data-out bursts. The card negates this signal to indicate that

the device pauses an Ultra DMA data-in burst.

-DASP

-CSEL

I/O

I

62

56

-DASP is the Device Active/Slave Present signal in the

Master/Slave handshake protocol.

5

HB28A896IA1, HB28A512IA1

Card Block Diagram

SDRAM

(Data buffer)

16

Flash memory

16

Flash bus A

16

Controller

Flash bus B

Reset IC

X'tal

6

HB28A896IA1, HB28A512IA1

Card Function Explanation

Register Construction

•

Task File region

Data register

Error register

Feature register

Sector Count register

Sector Number register

Cylinder Low register

Cylinder High register

Device Head register

Status register

Alternate Status register

Command register

Device Control register

7

HB28A896IA1, HB28A512IA1

Host Access Specifications

Read I/O Function

Mode

-CS1

-CS0

A2 to A0

-IORD

-IOWR

D15 to D8

High-Z

D7 to D0

High-Z

Invalid mode

L

×

Standby

mode

H

High-Z

Data register

access

H

L

H

L

0

L

H

odd byte

even byte

status out

data out

Alternate

status access

6H

1-7H

×

Other task file H

access

Note: ×: L or H

Write I/O Function

Mode

-CS1

-CS0

A2 to A0

-IORD

-IOWR

D15 to D8

don’t care

D7 to D0

don’t care

Invalid mode

L

×

Standby

mode

H

Data register

access

H

L

0

H

L

odd byte

even byte

control in

Device

control

register

access

H

6H

don’t care

Other task file H

access

L

1-7H

H

L

don’t care

data in

Note: ×: L or H

8

HB28A896IA1, HB28A512IA1

Task File Register Specification

These registers are used for reading and writing the storage data in this disk. The decoded addresses are

shown as follows.

I/O map

-CS1

-CS0

A2

0

A1

0

A0

0

-IORD

-IOWR

0

1

0

Data register

0

1

Error register

Feature register

0

1

0

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Device head register

Status register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Device head register

Command register

Device control register

0

1

0

1

0

1

0

1

0

Alt. status register

1. Data register: This register is a 16-bit register that has read/write ability, and it is used for transferring 1

sector data between the disk and the host. This register can be accessed in word mode and byte mode.

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

D15 to D0

2. Error register: This register is a read only register, and it is used for analyzing the error content at the

disk accessing. This register is valid when the BSY bit in Status register and Alternate Status register are set

to "0" (Ready).

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

ICRC

UNC

0

IDNF

0

ABRT

0

bit

Name

Function

7

ICRC (Interface CRC error)

This bit is set to one when an interface CRC error has occured

during an Ultra DMA data transfer. The content of this bit is not

applicable for Multiword DMA data transfer.

6

UNC (Data ECC error)

This bit is set when Uncorrectable error is occurred at reading the

disk.

4

2

IDNF (ID Not Found)

The requested sector cannot be found.

ABRT (ABoRTed command)

This bit is set if the command has been aborted because of the disk

status condition. (Not ready, Write fault, Invalid command, etc.)

9

HB28A896IA1, HB28A512IA1

3. Feature register: This register is write only register, and provides information regarding features of the

device which the host wishes to utilize.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Feature byte

4. Sector count register: This register contains the numbers of sectors of data requested to be transferred on

a read or write operation between the host and the disk. If the value of this register is zero, a count of 256

sectors is specified. This register's initial value is "01H".

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Sector count byte

5. Sector number register: This register contains the starting sector number which is started by following

sector transfer command.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Sector number byte

6. Cylinder low register: This register contains the low 8-bit of the starting cylinder address which is

started by following sector transfer command.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Cylinder low byte

7. Cylinder high register: This register contains the high 8-bit of the starting cylinder address which is

started by following sector transfer command.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Cylinder high byte

8. Device head register: This register is used for selecting the Device number and Head number for the

following command.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

1

LBA

1

DEV

Head number

10

HB28A896IA1, HB28A512IA1

bit

7

Name

1

Function

This bit is set to "1".

6

LBA

LBA is a flag to select either Cylinder / Head / Sector (CHS) or

Logical Block Address (LBA) mode. When LBA=0, CHS mode is

selected. When LBA=1, LBA mode is selected. In LBA mode, the

Logical Block Address is interrupted as follows:

LBA07-LBA00: Sector number Register.

LBA15-LBA08: Cylinder low Register.

LBA23-LBA16: Cylinder high Register.

LBA27-LBA24: Head number in Device head register.

5

4

1

This bit is set to "1".

DEV (DEVice select)

This bit is used for selecting the Master (Device 0) and Slave

(Device 1) in Master/Slave organization.

3 to 0 Head number

This bit is used for selecting the Head number for the following

command. Bit 3 is MSB.

9. Status register: This register is read only register, and it indicates the disk status of command and reset

execution. Other bits are invalid when BSY bit is "1". When this register is read, H_INTRQ is negated.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

BSY

DRDY

DWF

DSC

DRQ

CORR

IDX

ERR

bit

Name

BSY (BuSY)

Function

7

This bit is set when the disk internal operation is executing. When

this bit is set to "1", other bits in this register are invalid.

6

DRDY (Device ReaDY)

If this bit and DSC bit are set to "1", the disk is capable of receiving

the read or write or seek requests.

5

4

3

DWF (Device Write Fault)

DSC (Device Seek Complete)

DRQ (Data ReQuest)

This bit is set if this disk indicates the write fault status.

This bit is set when the device seek complete.

This bit is set when the information can be transferred between the

host and Data register. This bit is cleared when the disk receives

the other command.

2

CORR (CORRected data)

This bit is set when a correctable data error has been occurred and

the data has been corrected.

1

0

IDX (InDeX)

This bit is always set to "0".

ERR (ERRor)

This bit is set when the previous command has ended in some type

of error. The error information is set in Error register. This bit is

cleared by the next command.

11

HB28A896IA1, HB28A512IA1

10. Alternate status register: This register is the same as Status register physically, so the bit assignment

refers to previous item of Status register. But this register is different from Status register that INTRQ is not

negated when data read.

11. Command register: This register is write only register, and it is used for writing the command at

executing the device operation. The command code is written in the command register, after the parameter is

written in the Task File registers during the disk is Ready state.

12. Device control register: This register is write only register, and it is used for controlling the disk

interrupt request and issuing an ATA soft reset to the disk.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

×

SRST

nIEN

0

bit

Name

Function

7 to 3 ×

don't care

2

SRST (Software ReSeT)

This bit is set to "1" in order to force the disk to perform Task File

Reset operation. Once the host sets SRST bit to "1", SRST bit must

be kept to "1" for at least 5 µs. The disk remains in Reset until this

bit is reset to "0". While BSY bit is set to "1" in Status register as a

result of executing either the power-on or hardware reset protocol,

the host must not set SRST bit to "1" in Device Control register.

1

0

nIEN (Interrupt ENable)

0

This bit is used for enabling INTRQ. When this bit is set to "0",

INTRQ is enabled. When this bit is set to "1", INTRQ is disabled.

This bit is set to "0".

12

HB28A896IA1, HB28A512IA1

ATA Command specifications

This table summarizes the ATA command set with the paragraphs. Following shows the support commands

and command codes which are written in command registers.

ATA Command Set

No.

1

Command set

Code

C0h

03h

FR

N

SC

Y

SN

Y

CY

Y

DR

Y

HD

Y

LBA

Y

CFA ERASE SECTORS

2

CFA REQUEST EXTENDED ERROR

CODE

N

Y

N

3

4

CFA TRANSLATE SECTORS

87h

N

Y

CFA WRITE MULTIPLE WITHOUT

ERASE

CDh

5

CFA WRITE SECTORS WITHOUT

ERASE

38h

N

Y

6

CHECK POWER MODE

EXECUTE DEVICE DIAGNOSTIC

FLUSH CACHE

98h,E5h

90h

N

03h

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

7

8

E7h

9

FORMAT TRACK

IDENTIFY DEVICE

IDLE

50h

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

ECh

97h,E3h

95h,E1h

91h

IDLE IMMEDIATE

INITIALIZE DEVICE PARAMETERS

NOP

00h

READ BUFFER

E4h

READ DMA

C8h,C9h

C4h

READ MULTIPLE

READ NATIVE MAX ADDRESS

READ LONG SECTOR

READ SECTOR(S)

READ VERIFY SECTOR(S)

RECALIBRATE

F8h

22h,23h

20h,21h

40h,41h

1Xh

SEEK

7Xh

SET FEATURES SET TRANSFER

MODE

EFh

13

HB28A896IA1, HB28A512IA1

No.

Command set

Code

FR

SC

SN

CY

DR

HD

LBA

25

SET FEATURES ENA/DIS 8BIT PIO

TRANSFER

EFh

01h/

81h

N

Y

N

26

SET FEATURES SET 4BYTES

APPENDED

EFh

BBh

N

Y

N

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

SET MAX ADDRESS

SET MAX SET PASSWORD

SET MAX LOCK

F9h

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

F9h

01h

02h

03h

04h

N

F9h

SET MAX UNLOCK

SET MAX FREEZE LOCK

SET MULTIPLE

F9h

C6h

SLEEP

99h,E6h

N

SMART ENABLE/DISABLE AUTO SAVE B0h

D2h

D8h

D9h

DAh

N

SMART ENABLE OPERATION

SMART DISABLE OPERATION

SMART RETURN STATUS

STANDBY

B0h

96h,E2h

94h,E0h

E8h

STANDBY IMMEDIATE

WRITE BUFFER

Write DMA

N

CAh,CBh N

Write Multiple

C5h

N

Y

N

Write Long Sector

Write Same

32h,33h

E9h

Write Sector(s)

30h,31h

3Ch

Write Verify

Note: FR: Feature Register

SC: Sector Count register

SN: Sector Number register

CY: Cylinder Low/High register

DR: Device bit of Device/Head register

HD: Head No.(3 to 0) of Device/Head register

NH: No. of Heads

LBA: Logical Block Address

Y: Set up

N: Not set up

14

HB28A896IA1, HB28A512IA1

1. CFA ERASE SECTORS (code: C0h): This command pre-erases and conditions from 1 to 256 sectors as

specified in the Sector Count register.

2. CFA REQUEST EXTENDED ERROR CODE (code: 03h): This command provides an extended error

code which identifies the cause of an error condition in more detail than is available with Status and Error

register values.

3. CFA TRANSLATE SECTORS (code: 87h): This command provides information related to a specific

sector. The data indicates the erased or not erased status of the sector, and the number of erase and write

cycles performed on that sector. Devices may return zero in fields that do not apply or that are not supported

by the device.

15

HB28A896IA1, HB28A512IA1

CFA TRANSLATE SECTOR Information

Byte

00h

Description

Cylinder number MSB

Cylinder number LSB

Head number

01h

02h

03h

Sector number

04h

LBA bits ( 23:16 )

LBA bits (15:8)

05h

06h

LBA bits (7:0)

07h-12h

13h

Reserved

Sector erased flag (FFh = erased; 00h = not erased)

Reserved

Others

4. CFA WRITE MULTIPLE WITHOUT ERASE (code: CDh): This command is similar to the Write

Multiple command. Interrupts are not generated on every sector, but on the transfer of a block that contains

the number of sectors defined by the Set Multiple Mode.

5. CFA WRITE SECTORS WITHOUT ERASE (code: 38h): This command is similar to the WRITE

SECTORS command. Command execution is identical to the Write Sectors operation except that the sectors

are written without an implied erase operation. The sectors should be pre-erased by a preceding CFA ERASE

SECTORS command.

6. CHECK POWER MODE (code: E5h): This command checks the power mode.

7. EXECUTE DEVICE DIAGNOSTIC (code: 90h): This command performs the internal diagnostic tests

implemented by the device. DEV bit in Devic head register is cleared and the other bits in this register are not

cleared, after EXECUTE DEVICE DIAGNOSTIC command.

8. FLUSH CACHE (code: E7h): This command is used by the host request the device to flush the write

cache. The card returns error at the status register.

9. FORMAT TRACK (code: 50h): This command writes the desired head and cylinder of the selected

drive. But selected sector data is not exchange. This card excepts a sector buffer of data from the host to

follow the command with same protocol as the WRITE SECTOR command.

10. IDENTIFY DEVICE (code: ECh): The IDENTIFY DEVICE command enables the host to receive

parameter information from the device.

16

HB28A896IA1, HB28A512IA1

Identify Device Information

Word bit

Description

Default value F / V

0

General configuration bit-significant information

15

0 = ATA device

0040h

F

14-8

Retired

7

1 = removable media device

6

1 = not removable card and/or device

5-3

2

Retired

1 = Response incomplete

V

F

1

Retired

0

Reserved

1

Default number of logical cylinders

xxxxh

0000h

xxxxh

0000h

xxxxh

0000h

xxxxh

0000h

V

F

V

F

2

Specific configuration

3

Default number of logical heads

4-5

6

Retired

Default number of logical sectors per logical track

Reserved for assignment by CompactFlash^TMAssociation

7-8

9

Retired

10-19

20-21

22

Serial Number

Retired

Number of vendor specific bytes available on READ/WRITE LONG 0004h

commands

23-26

27-46

47

Firmware revision (8 ASCII characters)

Model Number (40 ASCII characters)

READ/WRITE Multiple support

80h

xxxxh

F

15-8

7-0

8010h

0000h

X

F

Maximum number of sectors that shall be transferred per interrupt

on READ/WRITE MULTIPLE commands

48

Reserved

R

17

HB28A896IA1, HB28A512IA1

Word bit

Description

Capabilities

Reserved

Default value F / V

49

15-14

2F00h

R

F

13

1 = Standby timer values as specified in this standard are

supported

0 = Standby timer values shall be managed by the device

12

11

10

9

Reserved

R

F

1 = device supports IORDY operation

1 = device supports the disabling IORDY

1

R

X

F

8

1

7-0

Retired

50

Capabilities

15

14

13-1

0

4000h

1

Reserved

Shall be set to one to indicate a device specific Standby timer value

minimum

51

PIO data transfer mode number

00h = PIO mode-0 is supported

01h = PIO mode-1 is supported

02h = PIO mode-2 is supported

Obsolete

15-8

7-0

0200h

F

X

R

52

53

Obsolete

0000h

0007h

Field validity

15-3

Reserved

R

F

2

1

0

1 = Word88 is valid

1 = Words 64 through 70 are valid

1 = Words 54 through 58 are valid

Number of current logical cylinders

Number of current logical heads

Number of current logical sectors per track

Current capacity in sectors

Multiple sector setting

V

54

xxxxh

55

56

57-58

59

15-9

8

Reserved

0110h

R

V

1 = Multiple sector setting is valid

7-0

xxh = Current setting for number of sectors that shall be transferred

per interrupt on Read/Write Multiple command

18

HB28A896IA1, HB28A512IA1

Word bit

Description

Default value F / V

60-61

62

Total number of user addressable sectors (LBA mode only)

obsolete

xxxxh

0000h

F

63

Multiword DMA transfer

15-11

Reserved

0007h

R

V

10

9

1 = Multiword DMA mode-2 is selected

1 = Multiword DMA mode-1 is selected

1 = Multiword DMA mode-0 is selected

Reserved

8

7-3

2

R

F

1 = Multiword DMA mode-2 and below are supported

1 = Multiword DMA mode-1 and below are supported

1 = Multiword DMA mode-0 is supported

Advanced PIO transfer modes supported

Reserved

1

0

64

15-2

0003h

0078h

R

F

1

0

1 = PIO mode-4 is supported

1 = PIO mode-3 is supported

65

Minimum Multiword DMA transfer cycle time per word

F

R

F

66

Manufacturer’s recommended Multiword DMA transfer cycle time 0078h

67

Minimum PIO transfer cycle time without flow control

0078h

0000h

0030h

0000h

68

Minimum PIO transfer cycle time with IORDY flow control

69-79

80

Reserved

Major version number

Reserved

81

19

HB28A896IA1, HB28A512IA1

Word bit

Description

Default value F / V

82

15

14

13

12

11

10

9-5

4

Command sets supported

Obsolete

7409h

F

1 = NOP command supported

1 = READ BUFFER command supported

1 = WRITE BUFFER command supported

Obsolete

1 = Host Protect Area feature set supported

Reserved

0

3

1 = Power Management feature set supported

2-1

0

Reserved

1 = SMART feature set supported

83

15

14

Command sets supported

0

4104h

F

1

13-9

Reserved

8

1 = SET MAX security extension supported

7-3

2

Reserved

1 = CFA feature set supported

1-0

15

14

13-0

Reserved

84

0

4000h

F

1

Reserved

20

HB28A896IA1, HB28A512IA1

Word bit

Description

Default value F / V

85

15

14

13

12

11

10

9-5

4

Command set/feature enabled

Obsolete

7409h

V

1 = NOP command enabled

1 = READ BUFFER command enabled

1 = WRITE BUFFER command enabled

Obsolete

1 = Host Protect Area feature set enabled

Reserved

0

3

1 = Power Management feature set enabled

Reserved

2-1

0

1 = SMART feature set enabled

Command set/feature enabled

Reserved

86

15-9

0104h

V

8

1 = SET MAX security extension enabled by SET MAX SET

PASSWORD

7-3

2

Reserved

1 = CFA feature set enabled

Reserved

1-0

87

88

Command set/feature default

0

15

4000h

101Fh

V

14

1

13-0

Reserved

Ultra DMA mode

15-13

12

11

10

9

Reserved

R

V

1 = Ultra DMA mode-4 is selected

1 = Ultra DMA mode-3 is selected

1 = Ultra DMA mode-2 is selected

1 = Ultra DMA mode-1 is selected

1 = Ultra DMA mode-0 is selected

Reserved

8

7-5

R

21

HB28A896IA1, HB28A512IA1

Word bit

Description

Default value F / V

88

Ultra DMA mode

4

1= Ultra DMA mode-4 and below are supported

1= Ultra DMA mode-3 and below are supported

1= Ultra DMA mode-2 and below are supported

1= Ultra DMA mode-1 and below are supported

1= Ultra DMA mode-0 is supported

Reserved

101Fh

F

3

2

1

0

89-91

92

93

15

14

13

0000h

R

V

Master Password Revision code

Hardware Reset result

0

xxxxh

V

1

1 = device detected -CBLID above V_IH

0 = device detected -CBLID below V_IL

12

11

Reserved

0 = Device 1 did not assert -PDIAG

1 = Device 1 asserted -PDIAG

10-9

These bit indicate how Device1 determined the device number

00 = Reserved

01 = a jumper was used

10 = -CSEL signal was used

11 = some other method was used or the method is unknown

8

7

6

1

Reserved

0 = Device 0 does not respond when Device 1 is selected

1 = Device 0 responds when Device 1 is selected

5

0 = Device 0 did not detect the assertion of -DASP

1 = Device 0 detected the assertion of -DASP

4

0 = Device 0 did not detect the assertion of -PDIAG

1 = Device 0 detected the assertion of -PDIAG

3

0 = Device 0 failed diagnostics

1 = Device 0 passed diagnostics

2-1

These bit indicate how Device 0 determined the device number.

00= Reserved

01 = a jumper was used

10 = -CSEL signal was used

11 = some other method was used or the method was unknown

0

1

94-128

Reserved

0000h

R

22

HB28A896IA1, HB28A512IA1

Word

bit

Description

Vendor Specific

Reserved

Default value F / V

129-159

160-255

0000h

X

R

Note: 1. F: the content of the word is fixed and does not change.

V: the content of the word is variable and may change depending on the state of the device or the

commands executed by the device.

X: the content of the word is Vendor Specific

R: the content of the word is reserved and set to zero

11. IDLE (code: 97h or E3h): This command allows the host to place the device in the Idle mode and also

set the Standby timer. INTRQ may be asserted even through the device may not have fully transitioned to

Idle mode. If the Sector Count register is non-zero then the Standby timer shall be enabled. The value in the

Sector Count register shall be used to determine the time programmed into the Standby timer. If the Sector

Count register is zero then the Standby timer is disabled.

12. IDLE IMMEDIATE (code: 95h or E1h): This command causes the Disk to set BSY, enter the Idle

(Read) mode, clear BSY and generate an interrupt.

13. INITIALIZE DEVICE PARAMETERS (code: 91h): This command enables the host to set the number

of sectors per track and the number of heads per cylinder.

14. NOP (code: 00h): If this command is issued, the device respond with command aborted.

15. READ BUFFER(code: E4h): This command enables the host to read the current contents of the Disk's

sector buffer.

16. READ DMA (code: C8h,C9h): This command reads from 1 to 256 sectors as specified in the Sector

Count register using the DMA data transfer protocol. A sector count of 0 requests 256 sectors. The transfer

begins at the sector specified in the Sector Number register.

17. READ MULTIPLE (code: C4h): This command performs similarly to the READ SECTORS command.

Interrupts are not generated on each sector, but on the transfer of a block which contains the number of

sectors defined by a Set Multiple command.

18. READ NATIVE MAX ADDRESS (code: F8h): This command returns the native maximum address.

23

HB28A896IA1, HB28A512IA1

19. READ LONG SECTOR (code: 22h,23h): This command is provided for compatibility purposes and

nearly performs one sector READ SECTOR command except that it transfers the data and 4 bytes appended

to the sector. These appended 4 bytes are all 0 data.

20. READ SECTOR(S) (code: 20h, or 21h): This command reads from 1 to 256 sectors as specified in the

Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in

the Sector Number register.

21. READ VERIFY SECTOR(S) (code: 40h or 41h): This command is identical to the READ SECTORS

command, except that DRQ is never set and no data is transferred to the host .

22. RECALIBRATE (code: 1Xh): This command return value is select address mode by the host request.

Return address mode status

Request Addressing

Sector Number Reg.

0x01h

CHS

LBA

0x00h

23. SEEK (code: 7Xh): This command perform a range check.

24. SET FEATURES SET TRANSFER MODE (code: EFh): This command is a host can choose the

transfer mechanism by Set Transfer Mode.

25. SET FEATURES ENA/DIS 8BIT PIO TRANSFER (code: EFh): This command allows enable or

disable PIO 8 bit transfer mode between the host and the device.

26. SET FEATURES SET 4BYTES APPENDED ( code: EFh): This command allows the host to set the 4

byte data appended to the data transfer on Read Long and Write Long commands.

27. SET MAX ADDRESS (code: F9h): This command allows the host to redefine the maximum address of

the user-accessible address space.

28. SET MAX SET PASSWORD ( code: F9h): This command requests a transfer of a single sector of data

from the host. Password data table defines the content of this sector of information. The password is retained

by the device until the next power cycle. When the device accepts this command the device is in Set Max

Unlocked state.

24

HB28A896IA1, HB28A512IA1

SET MAX SET PASSWORD content

Word

0

Content

Reserved

1-16

17-255

Password (32 bytes)

Reserved

29. SET MAX LOCK ( code: F9h): This command sets the device into Set Max Locked state. After this

command is completed any other Set Max commands except Set Max Unlock and Set Max Freeze Lock are

rejected. The device remains in this state until a power cycle or the acceptance of a Set Max Unlock or Set

Max Freeze Lock command.

30. SET MAX UNLOCK (code: F9h): This command requests a transfer of a single sector of data from the

host. Password data Table defines the content of this sector of information. The password supplied in the

sector of data transferred shall be compared with the stored SET MAX password. If the password compare

fails, then the device returns command aborted and decrements the unlock counter. On the acceptance of the

Set Max Lock command, this counter is set to a value of five and shall be decremented for each password

mismatch when Set Max Unlock is issued and the device is locked. When this counter reaches zero, then the

Set Max Unlock command shall return command aborted until a power-cycle. If the password compare

matches, then the device shall make a transition to the Set Max Unlocked state and all SET MAX commands

shall be accepted.

SET MAX SET PASSWORD content

Word

0

Content

Reserved

1-16

17-255

Password (32 bytes)

Reserved

31. SET MAX FREEZE LOCK (code: F9h): The Set Max Freeze Lock command sets the device to Set

Max Frozen state. After command completion any subsequent Set Max commands are rejected.

Commands disabled by Set Max Freeze Lock

Set Max Address

Set Max Set Password

Set Max Lock

Set Max Unlock

25

HB28A896IA1, HB28A512IA1

32. SET MULTIPLE MODE (code: C6h): This command enables the Disk to perform READ and Write

Multiple operations and establishes the block count for these commands.

33. SLEEP ( code: 99h or E6h ): This command causes the Disk to set BSY, enter the Sleep mode, clear

BSY and generate an interrupt.

34. SMART ENABLE/DISABLE AUTO SAVE (code: B0h): This command enables and disables the

optional attribute auto save feature of the device.

35. SMART ENABLE OPERATIONS (code: B0h): This command enables access to all SMART

capabilities within the device.

36. SMART DISABLE OPERATIONS (code: B0h): This command disables all SMART capabilities

within the device.

37. SMART RETURN STATUS (code: B0h): This command causes the device return the reliability status

of the device to the host.

38. STANDBY (code: 96h or E2h): This command causes the Disk to set BSY, enter the Sleep mode

(which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately.

39. STANDBY IMMEDIATE (code: 94h or E0h): This command causes the Disk to set BSY, enter the

Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt

immediately.

40. WRITE BUFFER (code: E8h): This command enables the host to overwrite contents of the Disk's

sector buffer with any data pattern desired.

41. WRITE DMA (code: CAh or CBh): This command writes from 1 to 256 sectors as specified in the

Sector Count register using the DMA data transfer protocol. A sector count of 0 requests 256 sectors. The

transfer begins at the sector specified in the Sector Number register.

42. WRITE MULTIPLE (code: C5h): This command is similar to the WRITE SECTORS command.

Interrupts are not presented on each sector, but on the transfer of a block which contains the number of sectors

defined by Set Multiple command.

43. WRITE LONG SECTOR (code: 32h or 33h): This command is provided for compatibility purposes

and nearly performs one sector WRITE SECTOR command except that it transfers the data and 4 bytes

appended to the sector. These appended 4 bytes are not written on the flash memories.

44. WRITE SAME (code: E9h): This command nearly performs one sector WRITE SECTOR command

except that only one sector of data transferred. The Sector Counter Register value means one sector data write

counts. (ex: value is 5 to nearly fifth one sector write execute.)

45. WRITE SECTOR(S) (code: 30h or 31h): This command writes from 1 to 256 sectors as specified in

the Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector

specified in the Sector Number register.

26

HB28A896IA1, HB28A512IA1

46. WRITE VERIFY (code: 3Ch): This command is similar to the WRITE SECTOR(S) command, except

that each sector is verified before the command is completed.

27

HB28A896IA1, HB28A512IA1

Absolute Maximum Ratings

Parameter

Symbol

Vin, Vout

V_CC

Value

Unit

V

Notes

All input/output voltages

V_CCvoltage

–0.3 to V_CC+ 0.3

–0.3 to +6.7

0 to +70

1

V

Operating temperature range

Storage temperature range

Topr

˚C

Tstg

–30 to +90

Notes: 1. Vin, Vout min = –2.0 V for pulse width ≤ 20 ns.

Recommended Operating Conditions

Parameter

Symbol

Ta

Min

0

Typ

25

Max

70

Unit

Operating temperature

V_CCvoltage

˚C

V

V_CC

4.5

5.0

5.5

Capacitance (Ta = 25°C, f = 1 MHz)

Parameter

Symbol

Cin

Min

—

Typ

—

Max

25

Unit

pF

Test conditions

Vin = 0 V

Note

Input capacitance

Output capacitance

1

Cout

—

25

pF

Vout = 0 V

Note: 1. This parameter is sampled and not 100% tested.

28

HB28A896IA1, HB28A512IA1

DC Characteristics-1 (Ta = 0 to +70°C, V_CC= 5 V ± 10%)

Parameter

Symbol

Min

—

Typ

—

Max

1

Unit Test conditions

Note

Output leakage current I_LO

µA

V

Vout = high impedance

1

Pull-up current

Output voltage

–I_PE

40

100

—

240

0.5

—

Vin = GND

I_OL= 4 mA

V_OL

V_OH

V_IL

—

2

2.4

—

V

I_OH= –400 µA

Input voltage

—

0.8

—

V

V_IH

2.2

—

V

Note: 1. Except pulled up input pin.

2. Output voltage is measured at static status.

29

HB28A896IA1, HB28A512IA1

DC Characteristics-2 (Ta = 0 to +70°C, V_CC= 5 V ± 10%)

Parameter

Symbol

Min

Typ

Max

Unit Test conditions

Note

Sleep current

I_SL

—

5

10

mA

CMOS level (Host control

signal = V_CC− 0.2)

Standby current

Idle current

I_SB

—

10

20

CMOS level (Host control

signal = V_CC− 0.2)

I_ID

100

150

200

TBD

150

220

300

TBD

CMOS level (Host control

signal = V_CC− 0.2)

Sector read current

I_CCR(DC)

CMOS level (Host control

signal = V_CC− 0.2)

1

2

I_CCR(Peak) —

I_CCW(DC)

I_CCW(Peak) —

CMOS level (Host control

signal = V_CC− 0.2)

Sector write current

—

CMOS level (Host control

signal = V_CC− 0.2)

CMOS level (Host control

signal = V_CC− 0.2)

Notes 1. Measured during sector read transfer.

2. Measured during sector write transfer.

30

HB28A896IA1, HB28A512IA1

AC Characteristics (Ta = 0 to +70˚C, V_CC= 5 V ± 10%)

Register Access AC Characteristics

Parameter

Symbol

(min) t₀

Mode0 Mode1 Mode2 Mode3 Mode4 Unit

Cycle time

600

70

290

—

383

50

290

—

330

30

290

—

180

30

80

70

30

10

20

5

120

25

70

25

20

10

20

5

ns

Address valid to -IORD/-IOWR setup (min) t₁

-IORD/-IOWR pulse width 8bit

-IORD/-IOWR recovery time

-IOWR data setup

(min) t₂

(min) t_2i

(min) t₃

(min) t₄

(min) t₅

(min) t₆

(max) t_6Z

(min) t₉

(min) t_RD

60

30

50

5

45

20

35

5

30

15

20

5

-IOWR data hold

-IORD data setup

-IORD data hold

-IORD data tristate

30

20

0

30

15

0

30

10

0

30

10

0

30

10

0

-IORD/-IOWR to address valid hold

Read data valid to IORDY active

(If IORDY initially low after t_A)

IORDY setup time

IORDY pulse width

(min) t_A

(max) t_B

35

ns

1250

PIO Mode Access AC Characteristics

Parameter

Symbol

(min) t₀

Mode0 Mode1 Mode2 Mode3 Mode4 Unit

Cycle time

600

70

165

—

383

50

125

—

240

30

100

—

180

30

80

70

30

10

20

5

120

25

70

25

20

10

20

5

ns

Address valid to -IORD/-IOWR setup (min) t₁

-IORD/-IOWR pulse width 16bit

-IORD/-IOWR recovery time

-IOWR data setup

(min) t₂

(min) t_2i

(min) t₃

(min) t₄

(min) t₅

(min) t₆

(max) t_6Z

(min) t₉

(min) t_RD

60

30

50

5

45

20

35

5

30

15

20

5

-IOWR data hold

-IORD data setup

-IORD data hold

-IORD data tristate

30

20

0

30

15

0

30

10

0

30

10

0

30

10

0

-IORD/-IOWR to address valid hold

Read data valid to IORDY active

(If IORDY initially low after t_A)

IORDY setup time

IORDY pulse width

(min) t_A

(max) t_B

35

ns

1250

31

HB28A896IA1, HB28A512IA1

Register Access/PIO Mode Access Timing

t₀

ADDR valid*¹

t₂

t₉

t₁

t_2i

-IORD/-IOWR

D15 to D0 (Write)

t₃

t₄

D15 to D0 (Read)

t_A

t₆

t₅

t_RD

t_6Z

IORDY

t_B

Note: 1. ADDR valid consists of signals -CS0, -CS1 and A2 to A0.

32

HB28A896IA1, HB28A512IA1

Multiword DMA Mode Access AC Characteristics

Parameter

Symbol

Mode0

480

215

150

5

Mode1

150

80

60

5

Mode2

120

70

50

5

Unit

ns

Cycle time

(min) t₀

(min) t_D

(max) t_E

(min) t_F

(min) t_G

(min) t_H

(min) t_I

(min) t_J

(min) t_KR

(min) t_KW

(max) t_LR

(max) t_LW

(min) t_M

(min) t_N

(max) t_Z

-IORD/-IOWR asserted pulse width

-IORD data access

-IORD data hold

-IORD/-IOWR data setup

-IOWR data hold

100

20

30

15

0

20

10

0

-DMACK to -IORD/-IOWR setup

-IORD/-IOWR to -DMACK hold

-IORD negated pulse width

-IOWR negated pulse width

-IORD to DMARQ delay

-IOWR to DMARQ delay

-CS0/-CS1 valid to -IORD/-IOWR

-CS0/-CS1 hold

0

20

5

50

40

30

10

25

35

25

10

25

215

120

40

50

15

-DMACK to read data released

20

33

HB28A896IA1, HB28A512IA1

Multiword DMA Mode Access Timing

-CS0/-CS1

t_M

t_N

DMARQ

-DMACK

t_LR

t_LW

t₀

t _KR

t_KW

t_J

t_I

t_D

-IORD/-IOWR

t_E

t_Z

D15 to D0 (Read)

D15 to D0 (Write)

t_G

t_F

t_G

t_H

34

HB28A896IA1, HB28A512IA1

Ultra DMA Mode Access AC Characteristics

Mode0

Mode1

Mode2

Mode3

Mode4

Parameter

Symbol Min Max Min Max Min Max Min Max Min Max Unit

Cycle time allowing for asymmetry and t_CYC

clock variations

112

230

—

73

—

54

—

39

86

—

25

57

—

ns

Two cycle time allowing for clock

variations

t_2CYC

154

115

Data setup time at recipient

Data hold time at recipient

Data valid setup at sender

Data valid hold at sender

First STROBE time*²

Limited interlock time*³

Interlock time with minimum

Unlimited interlock time

t_DS

t_DH

t_DVS

t_DVH

t_FS

t_LI

15

5

—

10

5

—

7

—

7

—

5

6

—

ns

5

70

6

48

6

30

6

20

6

0

230 0

150 0

200 0

150 0

170 0

150 0

130 0

100 0

120 ns

100 ns

0

t_MLI

t_UI

20

0

—

10

20

—

10

20

—

10

20

—

10

20

—

ns

0

Maximum time allowed for output

drivers to release

t_AZ

—

10 ns

Minimum delay time required for

output

t_ZAH

20

0

—

20

0

—

20

0

—

20

0

—

20

0

—

ns

Drivers to assert or negate

Envelope time

t_ZAD

t_ENV

t_SR

20 70 20 70 20 70 20 55 20 55 ns

STROBE–to–DMARDY time

Ready-to-final STROBE time

—

50

75

—

30

70

—

20

60

—

NA*¹—

NA*¹ns

t_RFS

t_RP

—

60

—

60 ns

Minimum time to assert STOP or

negate DMARQ

160

125

100

—

ns

Setup and hold times for DMACK

t_ACK

20

50

—

20

50

—

20

50

—

20

50

—

20

50

—

ns

Time from STROBE edge to negation t_SS

of DMARQ or assertion of STOP

Note: 1. NA = Not Available

2. When Ultra DMA data-in burst termination is occured before command completion and then the

host resumes Ultra DMA data-in burst, the Fast STROBE time may be longer than t_FS.

3. When Ultra DMA data-out burst termination is occured before command completion and then the

host resumes Ultra DMA data-out burst, the STOP–to–DMARDY time may be longer than t_LI.

4. All timing measurement switching points (low to high and high to low) is taken at 1.5 V.

35

HB28A896IA1, HB28A512IA1

Timing of Initializing an Ultra DMA data-in Burst

DMARQ

t_UI

-DMACK

t_FS

t_ACK

t_ENV

t_ZAD

STOP

t_FS

t_ACK

t_ENV

t_ZAD

-HDMARDY

DSTROBE

t_AZ

t_DVS

t_DVH

D15 to D0

t_ACK

-CS0/-CS1

A2 to A0

t_ACK

Timing of Sustained Ultra DMA data-in Burst

t_2CYC

t_CYC

t_2CYC

STROBE

D15 to D0

t_DVH

t_DVS

t_DVH

t_DVS

t_DVH

36

HB28A896IA1, HB28A512IA1

Timing of Host pausing an Ultra DMA data-in Burst

DMARQ

-DMACK

t_RP

STOP

t_SR

1

*

-HDMARDY

-DSTROBE

t_RFS

D15 to D0

Note: 1. If the t^SRtiming is not satisfied, the host may receive zero, one, or two more data words

from the device.

37

HB28A896IA1, HB28A512IA1

Timing of Device Terminating Ultra DMA data-in Burst

-DMARQ

-DMACK

t_MLI

t_LI

t_ACK

STOP

-HDMARDY

-DSTROBE

t_LI

t_ACK

t_SS

t_ZAH

t_DS

t_DH

t_AZ

D15 to D0

-CS0/-CS1

CRC

t_ACK

A2 to A0

38

HB28A896IA1, HB28A512IA1

Timing of Host terminating an Ultra DMA data-in Burst

DMARQ

t_LI

t_MLI

t_ZAH

-DMACK

STOP

t_AZ

t_ACK

t_RP

t_ACK

-HDMARDY

-DSTROBE

t_RFS

t_LI

t_MLI

t_DS

t_DH

D15 to D0

-CS0/-CS1

CRC

t_ACK

A2 to A0

39

HB28A896IA1, HB28A512IA1

Timing of Initializing an Ultra DMA data-out Burst

DMARQ

t_UI

-DMACK

t_ACK

t_ENV

STOP

DDMARDY

HSTROBE

t_LI

t_UI

t_ACK

t_DS

t_DH

D15 to D0

-CS0/-CS1

A2 to A0

t_ACK

Timing of Sustained Ultra DMA data-out Burst

t_2CYC

t_CYC

t_2CYC

HSTROBE

D15 to D0

t_DH

t_DS

40

HB28A896IA1, HB28A512IA1

Timing of Device pausing an Ultra DMA data-out Burst

t_RP

DMARQ

-DMACK

STOP

t_SR

1

*

DDMARDY

t_RFS

HSTROBE

D15 to D0

Note: 1. If the t^SRtiming is not satisfied, the device may receive zero, one,

or two more data words from the host.

41

HB28A896IA1, HB28A512IA1

Timing of Host terminating an Ultra DMA data-out Burst

t_LI

DMARQ

t_MLI

-DMACK

STOP

t_LI

t_ACK

t_SS

t_LI

DDMARDY

HSTROBE

t_ACK

t_DS

t_DH

D15 to D0

-CS0/-CS1

CRC

t_ACK

A2 to A0

42

HB28A896IA1, HB28A512IA1

Timing of Device Terminating Ultra DMA data-out Burst

DMARQ

-DMACK

t_LI

t_ACK

t_MLI

STOP

t_RP

-DDMARDY

t_RFS

t_LI

t_MLI

t_ACK

HSTROBE

t_DS

t_DH

D15 to D0

-CS0/-CS1

CRC

t_ACK

A2 to A0

43

HB28A896IA1, HB28A512IA1

Attention for Card Use

•

In the reset or power off, all register informations are cleared.

After the card hard reset, soft reset, or power on reset, the disk cannot access during BSY bit in Status

Register is set.

•

Devices shall not have a pull-up resistor on D7. The host shall have a 10 kΩ pull-down resistor and not a

pull-up resistor on D7 to allow a host to recognize the absence of a device at power-up so that a host shall

detect BSY as being cleaned when attempting to read the status register of a device that is not present.

Power off should not be done during internal operation. When power off occured during internal

operation, there is the possibility that data are lost.

•

All card status are cleared automatically when V_CCvoltage turns below about 2.5V.

Notice that the card insertion/removal should not be executed while host is active.

Before the card insertion V_CCcan not be supplied to the card.

We recommend that a circuit to detect the level of power supply voltage be added to the host.

When a read error occurs, rewriting of the sector is recommended. This may avoid the error.

44

HB28A896IA1, HB28A512IA1

Physical Outline

As of January, 2002

Surface A

Unit: mm

5.0 (max)

54.0 ± 0.1

85.6 ± 0.2

10.0 min

3.3 ± 0.1

Surface A

34 pin

1 pin

1.27 ± 0.1

68 pin

35 pin

1.27 ± 0.1

41.91

(Reference value)

Surface B

45

HB28A896IA1, HB28A512IA1

Caution for Handling Cards

•

Confirm the direction of insertion before inserting the card.

Be careful not to damage the connector.

To avoid damaging the card, never insert it in the wrong direction.

Do not bend the card; do not drop the card or expose the card to mechanical shock of any other kind.

Never modify or disassemble the card.

Do not expose the card to static electricity or electrical noise.

Make regular backups of the data in the card.

46

HB28A896IA1, HB28A512IA1

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

copyright, trademark, or other intellectual property rights for information contained in this document.

Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual

property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of

bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,

safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for

maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and

other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the

guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or

failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the

equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage

due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Tel: (03) 3270-2111 Fax: (03) 3270-5109

URL

http://www.hitachisemiconductor.com/

For further information write to:

Hitachi Semiconductor

(America) Inc.

179 East Tasman Drive Whitebrook Park

Hitachi Europe Ltd.

Electronic Components Group

Hitachi Asia Ltd.

Hitachi Tower

16 Collyer Quay #20-00

Singapore 049318

Hitachi Asia (Hong Kong) Ltd.

Group III (Electronic Components)

7/F., North Tower

San Jose,CA 95134

Lower Cookham Road

World Finance Centre,

Tel: <1> (408) 433-1990 Maidenhead

Fax: <1>(408) 433-0223 Berkshire SL6 8YA, United Kingdom

Tel: <44> (1628) 585000

Tel : <65>-538-6533/538-8577

Fax : <65>-538-6933/538-3877

URL : http://semiconductor.hitachi.com.sg

Harbour City, Canton Road

Tsim Sha Tsui, Kowloon Hong Kong

Tel : <852>-(2)-735-9218

Fax : <852>-(2)-730-0281

URL : http://semiconductor.hitachi.com.hk

Fax: <44> (1628) 585200

Hitachi Asia Ltd.

(Taipei Branch Office)

4/F, No. 167, Tun Hwa North Road

Hung-Kuo Building

Hitachi Europe GmbH

Electronic Components Group

Dornacher Straße 3

D-85622 Feldkirchen

Postfach 201,D-85619 Feldkirchen

Germany

Tel: <49> (89) 9 9180-0

Fax: <49> (89) 9 29 30 00

Taipei (105), Taiwan

Tel : <886>-(2)-2718-3666

Fax : <886>-(2)-2718-8180

Telex : 23222 HAS-TP

URL : http://www.hitachi.com.tw

Colophon 5.0

47


型号：	HB28A512IA1
厂家：	HITACHI SEMICONDUCTOR
描述：	Flash Card, 256MX16, CARD-68 内存集成电路
文件：	总47页 (文件大小：146K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HB28A512IA1 [HITACHI]

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