HB526R872ESN-10H [HITACHI]
Synchronous DRAM Module, 8MX72, 8ns, CMOS, DIMM-168;
| 型号： | HB526R872ESN-10H |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Synchronous DRAM Module, 8MX72, 8ns, CMOS, DIMM-168 时钟 动态存储器 内存集成电路 |
| 文件： | 总28页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HB526R872ESN Series
4,194,304-word × 72-bit (ECC) × 2-bank Synchronous Dynamic
RAM Module
ADE-203-799 (Z)
Preliminary
Rev. 0.1
Jul. 31, 1997
Description
The HB526R872ESN belongs to 8 byte DIMM (Dual In-line Memory Module) family, and has been
developed a as optimized main memory solution for 8 byte processor applications. The HB526R872ESN is
a 4M × 72 × 2 banks Synchronous Dynamic RAM module, mounted 36 pieces of 16-Mbit SDRAM
(HM5216405) sealed in TCP package and 1 piece of serial EEPROM (24C02) for Presence Detect (PD).
An outline of the HB526R872ESN is 168-pin socket type package (dual lead out). Therefore, the
HB526R872ESN makes high density mounting possible without surface mount technology. The
HB526R872ESN provides common data inputs and outputs. Decoupling capacitors are mounted beside
each TCP on the module board.
Features
•
168-pin socket type package (dual lead out)
Lead pitch: 1.27 mm
•
•
•
•
•
•
•
•
•
•
3.3 V ( ±0.3 V) power supply
Clock frequency: 100 MHz/ 83 MHz
JEDEC standard outline unbuffered 8-byte DIMM
LVTTL interface
Data bus width: × 72 (ECC) bit
Single pulsed RAS
2 Banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8/full page
Programmable burst sequence
Sequential/interleave
HB526R872ESN Series
•
Full page burst length capability
Sequential burst
Burst stop capability
Programmable CAS latency: 2/3
4096 refresh cycles: 64 ms
2 variations of refresh
Auto refresh
•
•
•
Self refresh
Ordering Information
Type No.
Frequency
Package
Contact pad
HB526R872ESN-10H
HB526R872ESN-10
HB526R872ESN-12
100 MHz
100 MHz
83 MHz
168-pin dual lead out socket type Gold
2
HB526R872ESN Series
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Pin No.
Pin name
VSS
Pin No.
Pin name
VSS
Pin No.
Pin name
VSS
Pin No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Pin name
VSS
1
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
2
DQ0
DQ1
DQ2
DQ3
VDD
NC
DQ32
DQ33
DQ34
DQ35
VDD
CKE0
S3
3
S2
4
DQMB2
DQMB3
NC
DQMB6
DQMB7
NC
5
6
7
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
VDD
8
NC
NC
9
NC
NC
10
11
12
13
14
15
16
17
CB2
CB6
CB3
CB7
VSS
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
DQ16
DQ17
DQ18
DQ19
VDD
DQ41
DQ42
DQ43
DQ44
DQ45
DQ48
DQ49
DQ50
DQ51
VDD
3
HB526R872ESN Series
Pin Arrangement (cont)
Pin No.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin name
VDD
Pin No.
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin name
DQ20
NC
Pin No.
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Pin name
VDD
Pin No.
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin name
DQ52
NC
DQ14
DQ15
CB0
CB1
VSS
DQ46
DQ47
CB4
CB5
VSS
NC
NC
CKE1
VSS
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ53
DQ54
DQ55
VSS
NC
NC
NC
NC
VDD
VDD
WE
DQ24
DQ25
DQ26
DQ27
VDD
CAS
DQMB4
DQMB5
S1
DQ56
DQ57
DQ58
DQ59
VDD
DQMB0
DQMB1
S0
NC
RAS
VSS
VSS
DQ28
DQ29
DQ30
DQ31
VSS
DQ60
DQ61
DQ62
DQ63
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
CK2
A9
CK3
A10 (AP)
NC
NC
A11 (BS)
NC
NC
NC
SA0
VDD
SDA
SCL
VDD
SA1
VDD
CK1
NC
SA2
CK0
VDD
VDD
4
HB526R872ESN Series
Pin Description
Pin name
Function
A0 to A11
Address input
•
•
•
Row address A0 to A10
Column address
A0 to A9
Bank select address A11
DQ0 to DQ63
Data-input/output
Check bit (Data-input/output)
Chip select
CB0 to CB7
S0 to S3 (CS0 to CS3)
RAS
Row address strobe
Column address strobe
Write enable
CAS
WE
DQMB0 to DQMB7 (DQM0 to DQM7)
Input/output mask
Clock input
CK0 to CK3 (CLK0 to CLK3)
CKE0/CKE1
SDA
Clock enable
Data-input/output for serial PD
Clock input for serial PD
Serial address input
Power supply
SCL
SA0 to SA2
VDD
VSS
Ground
NC
No connection
5
HB526R872ESN Series
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
module manufacturer
1
0
0
0
0
0
0
0
80
128
1
2
3
4
Total SPD memory size
Memory type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
1
1
0
0
1
0
08
04
0B
0A
256 byte
SDRAM
11
Number of row addresses bits 0
Number of column addresses 0
bits
10
5
6
7
Number of banks
Module data width
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
02
48
00
2
72
Module data width
(continued)
0 (+)
8
9
Module interface signal levels 0
0
0
0
0
0
0
1
01
LVTTL
CL = 3
SDRAM cycle time
(highest CE latency)
-10H, -10 (10 ns)
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
A0
C0
-12 (12 ns)
10
SDRAM access from Clock
(highest CE latency)
-10H, -10 (8 ns)
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
80
95
02
80
-12 (9.5 ns)
11
12
Module configuration type
Refresh rate/type
ECC
Normal
(15.625 µs)
Self refresh
13
14
15
SDRAM width
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
04
04
01
× 4
4
Error checking SDRAM width 0
SDRAM device attributes:
minimum clock delay for
back-to-back random column
addresses
0
1 CLK
16
17
SDRAM device attributes:
Burst lengths supported
1
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
8F
02
1, 2, 4, 8,
full page
SDRAM device attributes:
number of banks on SDRAM
device
2
18
19
SDRAM device attributes:
CE latency
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
06
01
2, 3
0
SDRAM device attributes:
CS latency
6
HB526R872ESN Series
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
0
0
0
0
0
0
0
1
01
0
WE latency
21
22
SDRAM module attributes
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
00
0E
Non buffer
SDRAM device attributes:
General
VCC ± 10%
23
SDRAM cycle time
(2nd highest CE latency)
-10H, -10 (15 ns)
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
F0
30
CL = 2
-12 (18 ns)
24
SDRAM access from Clock
(2nd highest CE latency)
-10H (9 ns)
1
1
1
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
90
95
A0
00
-10 (9.5 ns)
-12 (10 ns)
25
26
27
SDRAM cycle time
(3rd highest CE latency)
Undefined
SDRAM access from Clock
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
Minimum row precharge time
-10H, -10
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
1E
24
30 ns
36 ns
-12
28
Row active to row active min.
-10H, -10
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
0
0
1
0
0
0
14
18
1E
20 ns
24 ns
30 ns
-12
29
30
RE to CE delay min
Minimum RE pulse width
-10H, -10
0
0
0
0
1
0
1
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
3C
48
08
60 ns
-12
72 ns
31
Density of each bank on
module
32M byte
32 to 61 Superset information
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
00
01
Future use
Rev. 1
62
63
SPD data revision code
Checksum for bytes 0 to 62
-10H
0
0
1
0
0
1
1
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
1
1
0
1
0
0
1
0
53
58
EE
07
00
-10
-12
64
Manufacturer’s JEDEC DI code
HITACHI
65 to 71 Manufacturer’s JEDEC DI code
7
HB526R872ESN Series
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
72
Manufacturing location
×
×
×
×
×
×
×
×
××
ASCII-8bit
code*2
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
1
1
1
0
0
0
1
1
1
0
1
1
1
0
0
0
0
1
0
0
1
1
1
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
1
0
0
1
0
1
0
1
1
0
0
1
0
1
1
1
0
1
1
0
1
1
1
0
0
0
1
0
0
0
0
1
0
1
1
0
1
1
48
42
35
32
36
52
38
37
32
45
53
4E
5F
31
H
B
5
2
6
R
8
7
2
E
S
N
—
1
Manufacturer’s part number
-10H, -10
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
30
32
0
2
-12
88
Manufacturer’s part number
-10H
0
0
0
0
0
0
×
1
0
0
0
0
0
×
0
1
1
1
1
1
×
0
0
0
0
1
0
×
1
0
0
0
0
0
×
0
0
0
0
0
0
×
0
0
0
0
0
0
×
0
0
0
0
0
0
×
48
20
20
20
30
20
××
H
-10, -12
(Space)
(Space)
(Space)
Initial
89
90
91
92
93
Manufacturer’s part number
Manufacturer’s part number
Revision code
Revision code
(Space)
Manufacturing date
Year code
(binary) *3
94
Manufacturing date
×
×
×
×
×
×
×
×
××
Week code
(binary) *4
5
95 to 98 Assembly serial number
99 to 125 Manufacturer specific data
*
6
*
126
127
Intel specification frequency
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
66
06
66 MHz
Intel specification CE# latency 0
support
CL = 2, 3
Notes: 1. All serial PD data are not protected. 0: Serial data, “Low level”, 1: Serial data, “High level”
2. Byte72 is manufacturing location code. (ex: in case of Japan, byte72 is 4Ah. 4Ah shows “J” on
ASCII code.)
3. Byte 93 (Manufacturing date-year code) ex: 61h shows year 97, 62h shows year 98.
4. Byte 94 (Manufacturing date-week code) ex: 0Bh shows week 11, 24h shows week 36.
8
HB526R872ESN Series
5. Bytes 95 through 98 are assembly serial number.
6. All bits of 99 through 125 are not defined (“1” or “0”).
9
HB526R872ESN Series
Block Diagram
RAS, CAS, WE
S0
S1
CS
CS
CS
CS
DQMB0
DQM
DQM
DQMB4
DQM
DQM
D0
D18
D9
D27
4
4
4
4
4
R0 to R3
R4 to R7
4 R32 to R35
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
DQ0 to DQ3
DQ32 to DQ35
CS
CS
CS
CS
DQM
DQM
DQM
DQM
D1
D19
D10
D28
R36 to R39
4
4
4
4
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
DQ4 to DQ7
DQ36 to DQ39
CS
CS
CS
CS
DQM
DQM
DQM
DQM
DQMB5
DQMB1
R40 to R43
R44 to R47
R68 to R71
R8 to R11
R12 to R15
R64 to R67
D2
D20
D11
D29
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
DQ8 to DQ11
DQ40 to DQ43
CS
CS
CS
CS
DQM
DQM
DQM
DQM
D3
D21
D12
D30
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
DQ12 to DQ15
DQ44 to DQ47
CB4 to CB7
CS
CS
CS
CS
DQM
DQM
DQM
DQM
D4
D22
D13
D31
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
CB0 to CB3
S2
S3
CS
CS
CS
CS
DQMB2
DQM
DQM
DQMB6
DQM
DQM
D5
D23
D14
D32
4 R16 to R19
4 R20 to R23
4 R48 to R51
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
DQ16 to DQ19
DQ48 to DQ51
CS
CS
CS
CS
DQM
DQM
DQM
DQM
D6
D24
D15
D33
R52 to R55
4
4
4
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
DQ20 to DQ23
DQ52 to DQ55
CS
CS
CS
CS
DQM
DQM
DQM
DQM
DQMB7
DQMB3
R56 to R59
R60 to R63
4
4
R24 to R27
R28 to R31
D7
D25
D16
D34
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
DQ24 to DQ27
DQ56 to DQ59
CS
CS
CS
CS
DQM
DQM
DQM
DQM
D8
D26
D17
D35
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
I/O0
to I/O3
DQ28 to DQ31
DQ60 to DQ63
Serial PD
A0 to A11
CKE0
A0 to A11(D0 to D35)
CKE (D0 to D17)
SCL
SCL
SDA
SDA
U0
V
DD
R200
R100
A0 A1 A2
SA0 SA1 SA2
CKE1
CK0
CKE (D18 to D35)
Notes:
CLK (D0, D18)
CLK (D1, D19)
CLK (D2, D20)
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
R101
R102
R103
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
CLK (D3, D21,D4)
CLK (D5, D23, D22)
CLK (D6, D24)
CLK (D7, D25)
CK1
CK2
CK3
* D0 to D35: HM5216405
U0: 24C02
C0 to C35: 0.33 µF
R0 to R71, R100 to R107: 10 Ω
R200: 10kΩ
CLK (D8, D26)
R104
R105
CLK (D9, D27)
CLK (D10, D28)
CLK (D11, D29)
CLK (D12, D30, D13)
R106
R107
CLK (D14, D32, D31)
CLK (D15, D33)
CLK (D16, D34)
V
V
(D0 to D35)
(D0 to D35)
V
V
DD
DD
C0 to C35
SS
SS
CLK (D17, D35)
10
HB526R872ESN Series
Command Operation, Mode Resistor Configuration and Operation
Refer to the HM5216405 Series data sheet.
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to +4.6
–0.5 to +4.6
50
VDD
V
Iout
PT
mA
W
18
Operating temperature
Storage temperature
Topr
Tstg
0 to +65
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +65°C)
Parameter
Symbol
VDD
Min
3.0
0
Type
3.3
0
Max
3.6
0
Unit
V
Notes
Supply voltage
1
VSS
V
Input high voltage
VIH
2.0
–0.3
—
4.6
0.8
V
1, 2
1, 3
Input low voltage
VIL
—
V
Notes: 1. All voltage referred to VSS
2. VIH (max) = 5.5 V for pulse width ≤ 5 ns
3. VIL (min) = –1.0 V for pulse width ≤ 5 ns
11
HB526R872ESN Series
DC Characteristics (Ta = 0 to +65°C, VDD = 3.3 V ± 0.3 V, VSS = 0 V)
HB526R872ESN
-10H/-10
-12
Parameter
Symbol Min Max Min
Max Unit Test conditions
2250 mA Burst length = 1
RC = min
CKE = VIL,
CK = min
Notes
Operating current
ICC1
ICC2
—
—
—
—
2610
108
72
—
—
—
—
1, 2, 4
t
Standby current
(Bank Disable)
108
72
mA
mA
5
6
3
t
CKE = VIL
CLK = VIL or VIH Fixed
1440
1260 mA
CKE = VIH,
NOP command
t
CK = min
CKE = VIL,
CK = min, I/O = High-Z
Active standby current
(Bank active)
ICC3
—
—
252
—
—
252
mA
1, 2
t
1620
1440 mA
CKE = VIH,
1, 2, 3
NOP command
tCK = min, I/O = High-Z
Burst operating current
(CL = 2)
ICC4
ICC4
ICC5
ICC6
—
—
—
—
2610
3510
2340
72
—
—
—
—
2250 mA
2970 mA
1980 mA
tCK = min, BL = 4
1, 2, 4
(CL = 3)
Auto refresh current
Self refresh current
tRC = min
72
mA
VIH ≥ VDD – 0.2 V
0 V ≤ VIL ≤ 0.2 V
7
Input leakage current
Output leakage current
ILI
–10
–10
10
10
–10
–10
10
10
µA
µA
0 ≤ Vin ≤ VDD
ILO
0 ≤ Vout ≤ VDD
I/O = disable
Output high voltage
Output low voltage
VOH
VOL
2.4
0
VDD
0.4
2.4
0
VDD
0.4
V
V
IOH = –2 mA
IOL = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signal transition is once per two CLK cycles.
4. Input signal transition is once per one CLK cycle.
5. After power down mode, CLK operating current.
6. After power down mode, no CLK operating current.
7. After self refresh mode set, self refresh current.
12
HB526R872ESN Series
Capacitance (Ta = +25°C, VDD = 3.3 V ± 0.3 V)
Parameter
Symbol
CI1
Type
—
Max
200
200
70
Unit
pF
pF
pF
pF
pF
pF
Notes
1, 3
Input capacitance (Address)
Input capacitance (RAS, CAS, WE, CKE)
Input capacitance (CS)
CI2
—
1, 3
CI3
—
1, 3
Input capacitance (CLK)
CI4
—
65
1, 3
Input capacitance (DQM)
Input/output capacitance (DQ, CB)
CI5
—
50
1, 3
CI/O1
—
27
1, 2, 3
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. DQMB = VIH to disable Dout.
3. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to +65°C, VDD = 3.3 V ± 0.3 V, VSS = 0 V)
HB526R872ESN
-10H/-10
Symbol Min
-12
Parameter
Max
Min
Max
Unit
Notes
System clock cycle time
(CL = 2)
tCK
15
10
3
—
—
—
—
18
12
4
—
—
—
—
ns
1
(CL = 3)
tCK
CLK high pulse width
CLK low pulse width
tCKH
tCKL
ns
ns
1
1
3
4
Access time from CLK
(CL = 2) (-10H)
tAC
tAC
tAC
tOH
tLZ
—
—
—
3
9
—
—
—
3
12
12
9.5
—
—
9
1, 2
(CL = 2) (-10)
9.5
8
ns
(CL = 3)
Data-out hold time
CLK to Data-out low impedance
—
—
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2
0
0
1, 2, 3
CLK to Data-out high impedance (CL = 2, 3) tHZ
—
2
—
3
1, 4
1
Data-in setup time
Data in hold time
tDS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tDH
1
1
1
Address setup time
Address hold time
CKE setup time
tAS
2
3
1
tAH
1
1
1
tCES
tCESP
tCEH
2
3
1, 5
1
CKE setup time for power down exit
CKE hold time
2
3
1
1
1
13
HB526R872ESN Series
AC Characteristics (Ta = 0 to 65°C, VDD = 3.3 V ± 0.3 V, VSS = 0 V) (cont)
HB526R872ESN
-10H/-10
Symbol Min
-12
Min
3
Parameter
Max
—
Max
—
Unit
ns
Notes
Command setup time
tCS
2
1
1
Command hold time
tCH
1
—
1
—
ns
Ref/Active to Ref/Active command period
Active to precharge command period
Active to precharge on full page mode
tRC
90
60
—
30
—
108
—
ns
tRAS
tRASC
tRCD
120000 72
120000 —
120000 ns
120000 ns
1
1
1
Active command to column command
(same bank)
—
36
—
ns
Precharge to active command period
tRP
30
15
—
—
36
18
—
—
ns
ns
1
1
Write recovery or data-in to precharge
command
tDPL
Active (a) to Active (b) command period
Transition time (rise to fall)
Refresh period
tRRD
tT
20
1
—
5
24
1
—
5
ns
ns
ms
1
tREF
—
64
—
64
Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.40 V.
2. Access time is measured at 1.40 V. Load condition is CL = 50 pF with current source.
3. tLZ (max) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max) defines the time at which the outputs achieves the high impedance state.
5. tCES defines CKE setup time to CKE rising edge except power down exit command.
Test Conditions
•
•
Input and output timing reference levels: 1.4 V
Input waveform and output load: See following figures
input
output
DQ
2.8 V
80%
50 Ω
20%
+1.4 V
V
SS
CL
t
t
T
T
14
HB526R872ESN Series
Relationship Between Frequency and Minimum Latency
HB526R872ESN
-10H/-10
100 66
Parameter
-12
Frequency (MHz)
33
30
83
12
55
18
28
36
t
CK (ns)
Symbol 10
15
Notes
Active command to column command
(same bank)
tRCD
3
9
6
3
2
2
2
1
3
2
1
1
1
3
9
6
3
2
2
2
6
4
2
1
2
1
3
2
1
1
1
1
Active command to active command
(same bank)
tRC
6
4
2
1
2
= [tRAS + tRP]
1
Active command to precharge command tRAS
(same bank)
Precharge command to active command tRP
(same bank)
1
1
1
Write recovery or data-in to precharge tDPL
command (same bank)
Active command to active command
(different bank)
tRRD
Self refresh exit time
ISREX
IAPW
2
5
2
3
2
2
2
5
2
3
2
2
2
Last data in to active command
(Auto precharge, same bank)
= [tDPL + tRP]
Self refresh exit to command input
ISEC
9
6
3
9
6
3
= [tRC]
Precharge command to high impedance
(CAS latency = 3)
IHZP
IHZP
IAPR
3
3
2
1
3
2
1
3
3
2
1
3
2
1
(CAS latency = 2)
—
1
—
1
Last data out to active command
(auto precharge) (same bank)
Last data out to precharge
(early precharge)
(CAS latency = 3)
IEP
IEP
–2
—
1
–2
–1
1
–2
–1
1
–2
—
1
–2
–1
1
–2
–1
1
(CAS latency = 2)
Column command to column command ICCD
Write command to data in latency
DQM to data in
IWCD
IDID
IDOD
ICLE
0
0
0
0
0
0
0
0
0
0
0
0
DQM to data out
2
2
2
2
2
2
CKE to CKE disable
1
1
1
1
1
1
15
HB526R872ESN Series
Relationship Between Frequency and Minimum Latency (cont)
HB526R872ESN
Parameter
-10H/-10
100 66
-12
Frequency (MHz)
33
30
83
12
55
18
28
36
t
CK (ns)
Symbol 10
15
Notes
Register set to active command
CS to command disable
tRSA
ICDD
IPEC
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
0
Power down exit to command input
1
Burst stop to output valid data hold
(CAS latency = 3)
IBSR
IBSR
2
2
1
2
1
2
2
1
2
1
(CAS latency = 2)
—
—
Burst stop to output high impedance
(CAS latency = 3)
IBSH
IBSH
IBSW
3
3
2
0
3
2
0
3
3
2
0
3
2
0
(CAS latency = 2)
—
0
—
0
Burst stop to write data ignore
Notes: 1. tRCD to tRRD are recommended value.
2. When self refresh exit is executed, CKE should be kept “H” longer than lSREX from exit cycle.
16
HB526R872ESN Series
Timing Waveforms
Read Cycle
t
CK
t
t
CKH CKL
CLK
CKE
t
RC
V
IH
t
t
RAS
RP
t
RCD
t
t
t
t
t
t
t
t
t
CH
CH
CH
CH
t
CS
CS
CS
CS
CH
CS
CS
t
t
t
t
t
t
t
t
t
t
t
t
CH
CH
CH
CH
CH
CH
CS
CS
CS
CS
CS
CS
RAS
t
t
t
t
CH
CH
CS
CS
CAS
t
t
t
t
CH
CS
CH
CS
t
t
CH
CS
WE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AH
AH
AH
AH
AH
AH
AH
AS
AS
AS
AS
AS
AS
AS
A11
t
t
t
t
AH
AH
AS
AS
A10
Address
DQM
t
t
t
t
AH
AS
AH
AS
t
t
CH
CS
DQ(input)
t
t
t
HZ
t
AC
AC
AC
DQ(output)
t
AC
t
t
t
OH
t
OH
OH
OH
t
Burst length = 4
Bank0 Access
= VIH or VIL
LZ
Bank 0
Read
Bank 0
Active
Bank 0
Precharge
17
HB526R872ESN Series
Write Cycle
t
CK
t
t
CKH CKL
CLK
CKE
t
RC
V
IH
t
t
RAS
RP
t
RCD
t
t
t
t
t
t
CH
CH
CH
CS
CS
CS
t
t
t
t
t
t
t
t
CH
CH
CH
CH
CS
CS
CS
CS
CS
t
t
t
t
CH
CH
CS
CS
RAS
t
t
t
t
t
t
CH
CH
CH
CS
CS
CS
t
t
CH
CS
CAS
WE
t
t
CH
CS
t
t
t
t
t
t
t
t
CH
AH
CH
AH
CS
AS
CS
AS
t
t
t
t
t
t
t
t
AH
AH
AH
AH
AS
AS
AS
AS
A11
A10
t
t
t
t
t
t
AH
AH
AH
AS
AS
AS
t
t
t
t
AH
AH
AS
AS
Address
DQM
t
t
t
CH
CS
t
t
DH
t
DS
DH
t
t
t
DS
t
DH
DS
DH
DS
DQ(input)
t
DPL
DQ(output)
Bank 0
Precharge
Burst length = 4
Bank0 Access
= VIH or VIL
Bank 0
Write
Bank 0
Active
18
HB526R872ESN Series
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK
CKE
CS
V
IH
RAS
CAS
WE
A11(BS)
code
C: b’
Address
DQM
valid
C: b
R: b
b’+3
b+3
b’+1 b’+2
b’
DQ(input)
b
High-Z
DQ(output)
t
t
t
RCD
RSA
Bank 1
RP
Output mask
tRCD = 3
Precharge
If needed
Mode
Bank 1
Read
CAS Latency = 3
Burst Length = 4
= VIH or VIL
register Active
Set
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
Read cycle
V
IH
RAS-CAS delay = 3
CAS Latency = 3
Burst Length = 4
= VIH or VIL
CS
RAS
CAS
WE
A11(BS)
Address
DQM
R:a
C:a
R:b
C:b
C:b'
C:b"
DQ(output)
DQ(input)
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3
High-Z
Bank 0
Active
Bank 0
Read
Bank 1
Active
Bank 1 Bank 0
Bank 1
Read
Bank 1
Read
Bank 1
Precharge
Read
Precharge
V
IH
Write cycle
CKE
RAS-CAS delay = 3
CAS Latency = 3
Burst Length = 4
= VIH or VIL
CS
RAS
CAS
WE
A11(BS)
Address
R:a
C:a
a
R:b
C:b
C:b'
C:b"
DQM
DQ(output)
DQ(input)
High-Z
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b" b"+1b"+2 b"+3
Bank 0
Active
Bank 0
Write
Bank 1
Active
Bank 1
Write
Bank 0
Precharge
Bank 1
Write
Bank 1
Write
Bank 1
Precharge
Read/Single Write Cycle
19
HB526R872ESN Series
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
V
IH
CS
RAS
CAS
WE
A11(BS)
Address
R:a
C:a
R:b
C:a' C:a
a
DQM
DQ(input)
DQ(output)
a
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank 0
Active
Bank 0
Read
Bank 1
Active
Bank 0 Bank 0
Write Read
Bank 0
Precharge
Bank 1
Precharge
V
IH
CKE
CS
RAS
CAS
WE
A11(BS)
R:a
C:a
R:b
C:a
C:b C:c
Address
DQM
DQ(input)
DQ(output)
a
b
c
a
a+1
a+3
Bank 0
Active
Bank 0
Read
Bank 0
Write
Bank 0 Bank 0
Write Write
Bank 0
Precharge
Bank 1
Active
Read/Single write cycle
RAS-CAS delay = 3
CAS Latency = 3
Burst Length = 4
= VIH or VIL
20
HB526R872ESN Series
Read/Burst Write Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
CS
RAS
CAS
WE
A11(BS)
Address
R:a
C:a
R:b
C:a
DQM
DQ(input)
a
a+1 a+2 a+3
a
a+1 a+2 a+3
DQ(output)
Bank 0
Active
Bank 0
Read
Bank 1
Active
Clock
Suspend
Bank 0
Write
Bank 0
Precharge
Bank 1
Precharge
VIH
CKE
CS
RAS
CAS
WE
A11(BS)
Address
R:a
C:a
R:b
C:a
a
DQM
DQ(input)
a+1 a+2 a+3
a
a+1
a+3
DQ(output)
Bank 0
Active
Bank 0
Read
Bank 1
Active
Bank 0
Write
Bank 0
Precharge
Read/Burst write cycle
RAS-CAS delay = 3
CAS Latency = 4
Burst Length = 4
= VIH or VIL
21
HB526R872ESN Series
Full Page Read/Write Cycle
CLK
V
IH
CKE
Read cycle
RAS-CAS delay = 3
CAS Latency = 3
Burst Length = full page
= VIH or VIL
CS
RAS
CAS
WE
A11(BS)
R:a
C:a
R:b
Address
DQM
DQ(output)
DQ(input)
a
a+1
a+2 a+3
a-2
a-1
a
a+1 a+2
a+3
a+4
a+5
High-Z
Bank 0
Active
Bank 0
Read
Bank 1
Active
Bank 1
Precharge
Burst stop
V
CKE
IH
Write cycle
RAS-CAS delay = 3
CAS Latency = 3
Burst Length = full page
= VIH or VIL
CS
RAS
CAS
WE
A11(BS)
R:a
C:a
R:b
Address
DQM
High-Z
DQ(output)
DQ(input)
a
a+1
a+2 a+3
Bank 1
a+4
a+5 a+6
a+1 a+2
a+3 a+4
a+5
Bank 0
Active
Bank 0
Write
Burst stop
Bank 1
Precharge
Active
22
HB526R872ESN Series
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
CS
V
IH
RAS
CAS
WE
A11(BS)
Address
C:a
A10=1
R:a
DQM
DQ(input)
a+1
a
High-Z
DQ(output)
t
t
RC
t
RP
RC
Refresh cycle and
Read cycle
Active
Bank 0
Read
Bank 0
Auto Refresh
Precharge
If needed
Auto Refresh
RAS-CAS delay=2
CAS latency=2
Burst length=4
= VIH or VIL
Self Refresh Cycle
CLK
CKE
ISREX
CLK Low
CS
RAS
CAS
WE
A11 (BS)
A10x1
Address
DQM
DQ(input)
DQ(output)
High-Z
tRC
tRP
tRC
Self refresh cycle
RAS-CAS delay = 3
CAS Latency = 3
Burst Length = 4
=VIH or VIL
Precharge command Self refresh entry
If needed command
Self refresh exit
ignore command
or No operation
Next Self refresh entry
clock command
enable
Next Auto
clock refresh
enable
23
HB526R872ESN Series
Clock Suspend Mode
t
t
CES
t
CES
CEH
8
0
1
2
3
4
5
6
7
9
10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
Read cycle
RAS-CAS delay=2
CAS latency=2
Burst length=4
= VIH or VIL
CS
RAS
CAS
WE
A11(BS)
Address
DQM
R:a
C:a
R:b
C:b
DQ(output)
a
a+1 a+2
a+3
b
b+1 b+2 b+3
High-Z
DQ(input)
Bank0 Active clock
Active suspend start
Active clock Bank0
suspend end Read
Bank1 Read suspend Read suspend
Bank0
Earliest Bank1
Precharge
Bank1
Active
start
end Read Precharge
CKE
Write cycle
RAS-CAS delay=2
CAS latency=2
Burst length=4
= VIH or VIL
CS
RAS
CAS
WE
A11(BS)
R:b
a+1
Address
DQM
R:a
C:a
a
C:b
High-Z
DQ(output)
DQ(input)
a+2
a+3
b
b+1 b+2 b+3
Bank0
Active clock Bank0 Bank1 Write suspend Write suspend Bank1
Earliest Bank1
Precharge
Bank0 Active clock
Active suspend start
Precharge
end Write
supend end Write Active
start
24
HB526R872ESN Series
Power Down Mode
CLK
CKE
CS
CKE Low
RAS
CAS
WE
A11(BS)
Address
DQM
A10=1
R: a
DQ(input)
High-Z
DQ(output)
t
RP
Power down cycle
Power down entry
Power down
mode exit
Active Bank 0
Precharge command
If needed
RAS-CAS delay=3
CAS latency=3
Burst length=4
= VIH or VIL
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
10
48 49 50 51 52 53 54 55
CLK
VIH
CKE
CS
RAS
CAS
WE
Valld
code
Valld
Address
DQM
VIH
High-Z
tRC
DQ
tRP
Auto Refresh
tRC
tRSA
Mode register Bank active
Set If needed
All banks
Precharge
Auto Refresh
25
HB526R872ESN Series
Physical Outline
mm
inch
Unit:
Front side
133.35
5.250
4.80
0.189
3.00
0.118
127.35
5.014
Protective cover*1
Component area (Front)
1
84
B
A
C
11.43
0.450
8.89
0.350
36.83
1.450
54.61
2.150
1.27 ± 0.10
0.050 ±0.004
115.7
4.550
Back side
2 – φ 3.00
2 – φ 0.118
8 5
1 6 8
Component area (Back)
Note: 1. Protective cover material will be Fe-Ni or stainless steel.
Detail A
Detail B
Detail C
1.00
6.35
6.35
0.250
0.250
2.00 ± 0.10
2.00 ± 0.10
0.079 ± 0.004
0.079 ± 0.004
1.00 ± 0.05
0.039 ± 0.002
26
HB526R872ESN Series
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1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Tel: 415-589-8300
Fax: 535-1533
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Berkshire SL6 8YA
United Kingdom
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 0628-585000
Fax: 0628-778322
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
27
HB526R872ESN Series
Revision Record
Rev. Date
Contents of Modification
Drawn by
Approved by
0.0
Jul. 1, 1997
Initial issue
S. Tsukui
K. Yoshizaki
(referred to HM5216805/HM5216405 Series Rev. 3.0)
0.1
Jul. 31, 1997 (referred to HM5216805/HM5216405 Series Rev. 4.0)
Change of Serial PD matrix
AC Characteristics
tAC (CL = 3) max: 7.5/9 ns to 8/9.5 ns
28
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