HB52RF648DC-75BL [HITACHI]
Synchronous DRAM Module, 64MX64, 5.4ns, CMOS, DIMM-144;
| 型号： | HB52RF648DC-75BL |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Synchronous DRAM Module, 64MX64, 5.4ns, CMOS, DIMM-144 时钟 动态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HB52RF648DC-B, HB52RD648DC-B
512 MB Unbuffered SDRAM S.O.DIMM
64-Mword × 64-bit, 133/100 MHz Memory Bus, 2-Bank Module
(16 pcs of 64 M × 4 components)
PC133/100 SDRAM
ADE-203-1214A (Z)
Preliminary
Rev. 0.1
Oct. 20, 2000
Description
The HB52RF648DC, HB52RD648DC are a 32M × 64 × 2 banks Synchronous Dynamic RAM Small Outline
Dual In-line Memory Module (S.O.DIMM), mounted 16 pieces of 256-Mbit SDRAM
(HM5225805BTT/BLTT) sealed in TSOP package and 1 piece of serial EEPROM (2-kbit) for Presence
Detect (PD). An outline of the products is 144-pin Zig Zag Dual tabs socket type compact and thin package.
Therefore, they make high density mounting possible without surface mount technology. They provide
common data inputs and outputs. Decoupling capacitors are mounted beside TSOP on the module board.
Features
•
•
Fully compatible with: JEDEC standard outline 8-byte S.O.DIMM
144-pin Zig Zag Dual tabs socket type (dual lead out)
Outline: 67.60 mm (Length) × 31.75 mm (Height) × 3.80 mm (Thickness)
Lead pitch: 0.80 mm
•
•
•
•
•
•
•
•
3.3 V power supply
Clock frequency: 133/100 MHz (max)
LVTTL interface
Data bus width: × 64 Non parity
Single pulsed RAS
4 Banks can operates simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length : 1/2/4/8
Preliminary: The specification of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specification.
HB52RF648DC-B, HB52RD648DC-B
•
2 variations of burst sequence
Sequential
Interleave
•
•
•
•
Programmable CE latency: 2/3
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64 ms
2 variations of refresh
Auto refresh
Self refresh
•
Low self refresh current: HB52RF648DC-xxBL (L-version)
: HB52RD648DC-xxBL (L-version)
Ordering Information
Type No.
Frequency CE latency Package
Contact pad
HB52RF648DC-75B*1
HB52RF648DC-75BL*1
133 MHz
133 MHz
3
3
Small outline DIMM (144-pin) Gold
HB52RD648DC-A6B*1
HB52RD648DC-A6BL*1
HB52RD648DC-B6B*2
HB52RD648DC-B6BL*2
100 MHz
100 MHz
100 MHz
100 MHz
2/3
2/3
3
3
Notes: 1. 100 MHz operation at CE latency = 2.
2. 66 MHz operation at CE latency = 2.
2
HB52RF648DC-B, HB52RD648DC-B
Pin Arrangement
Front Side
1pin
2pin
59pin
60pin
61pin
62pin
143pin
144pin
Back Side
Front side
Back side
Signal name Pin No.
Pin No.
1
Signal name Pin No.
Signal name Pin No.
Signal name
CK1
VSS
73
NC
2
VSS
74
3
DQ0
DQ1
DQ2
DQ3
VCC
75
VSS
4
DQ32
DQ33
DQ34
DQ35
VCC
76
VSS
5
77
NC
6
78
NC
7
79
NC
8
80
NC
9
81
VCC
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
82
VCC
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
83
DQ16
DQ17
DQ18
DQ19
VSS
84
DQ48
DQ49
DQ50
DQ51
VSS
DQ4
DQ5
DQ6
DQ7
VSS
85
DQ36
DQ37
DQ38
DQ39
VSS
86
87
88
89
90
91
92
93
DQ20
DQ21
DQ22
DQ23
VCC
94
DQ52
DQ53
DQ54
DQ55
VCC
DQMB0
DQMB1
VCC
95
DQMB4
DQMB5
VCC
96
97
98
99
100
102
104
106
108
110
112
A0
101
103
105
107
109
111
A3
A1
A6
A4
A7
A2
A8
A5
BA0
VSS
VSS
VSS
VSS
DQ8
DQ9
A9
DQ40
DQ41
BA1
A10 (AP)
A11
3
HB52RF648DC-B, HB52RD648DC-B
Front side
Back side
Signal name Pin No.
Pin No.
41
Signal name Pin No.
Signal name Pin No.
Signal name
VCC
DQ10
DQ11
VCC
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
VCC
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DQ42
DQ43
VCC
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
43
DQMB2
DQMB3
VSS
DQMB6
DQMB7
VSS
45
47
DQ12
DQ13
DQ14
DQ15
VSS
DQ44
DQ45
DQ46
DQ47
VSS
49
DQ24
DQ25
DQ26
DQ27
VCC
DQ56
DQ57
DQ58
DQ59
VCC
51
53
55
57
NC
NC
59
NC
DQ28
DQ29
DQ30
DQ31
VSS
NC
DQ60
DQ61
DQ62
DQ63
VSS
61
CK0
VCC
CKE0
VCC
63
65
RE
CE
67
W
CKE1
A12
69
S0
SDA
SCL
71
S1
VCC
NC
VCC
4
HB52RF648DC-B, HB52RD648DC-B
Pin Description
Pin name
Function
Address input
Row address A0 to A12
Column address A0 to A9
Bank select address
A0 to A12
BA0/BA1
DQ0 to DQ63
Data-input/output
Chip select
S0/S1
RE
Row address asserted bank enable
Column address asserted
Write enable
CE
W
DQMB0 to DQMB7
Byte input/output mask
Clock input
CK0/CK1
CKE0/CKE1
SDA
Clock enable
Data-input/output for serial PD
Clock input for serial PD
Power supply
SCL
VCC
VSS
Ground
NC
No connection
5
HB52RF648DC-B, HB52RD648DC-B
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
module manufacturer
1
0
0
0
0
0
0
0
80
128
1
2
3
4
Total SPD memory size
Memory type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
1
0
0
0
0
1
0
0
1
0
08
04
0D
0A
256 byte
SDRAM
13
Number of row addresses bits 0
Number of column addresses
bits
0
10
5
6
7
8
9
Number of banks
Module data width
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
02
40
00
01
75
2
64
Module data width (continued) 0
0 (+)
LVTTL
CL = 3
Module interface signal levels
0
0
SDRAM cycle time
(highest CE latency)
(-75) 7.5 ns
(-A6/B6) 10 ns
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
0
A0
54
10
SDRAM access from Clock
(highest CE latency)
(-75) 5.4 ns
(-A6/B6) 6 ns
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
60
00
82
11
12
Module configuration type
Refresh rate/type
Non parity
Normal
(7.8125 µs)
Self refresh
13
14
15
SDRAM width
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
08
00
01
× 8
Error checking SDRAM width
—
SDRAM device attributes:
minimum clock delay for back-
to-back random column
addresses
1 CLK
16
17
SDRAM device attributes:
Burst lengths supported
0
0
0
0
0
0
0
0
1
0
1
1
1
0
1
0
0F
04
1, 2, 4, 8
4
SDRAM device attributes:
number of banks on SDRAM
device
18
19
SDRAM device attributes:
CE latency
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
06
01
2, 3
0
SDRAM device attributes:
S latency
6
HB52RF648DC-B, HB52RD648DC-B
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
0
0
0
0
0
0
0
1
01
0
W latency
21
22
SDRAM module attributes
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
00
0E
Non buffer
VCC ± 10%
SDRAM device attributes:
General
23
SDRAM cycle time
(2nd highest CE latency)
(-75/A6)10 ns
1
0
1
0
0
0
0
0
A0
CL = 2
(-B6) 15 ns
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
F0
60
24
SDRAM access from Clock
(2nd highest CE latency)
(-75/A6) 6 ns
(-B6) 9 ns
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
90
00
25
26
SDRAM cycle time
(3rd highest CE latency)
Undefined
SDRAM access from Clock
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
27
28
Minimum row precharge time
0
0
0
0
0
0
1
0
0
1
1
1
0
1
0
1
14
0F
20 ns
15 ns
Row active to row active min
(-75)
(-A6/B6)
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
1
14
14
2D
20 ns
20 ns
45 ns
29
30
RE to CE delay min
Minimum RE pulse width
(-75)
(-A6/B6)
0
0
0
1
1
0
1
0
0
0
0
0
1
0
0
0
32
40
50 ns
31
32
Density of each bank on
module
256M byte
Address and command signal
input setup time
(-75)
0
0
0
1
0
1
0
1
15
1.5 ns
(-A6/B6)
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
20
08
2.0 ns
0.8 ns
33
34
Address and command signal
input hold time
(-75)
(-A6/B6)
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
10
15
1.0 ns
1.5 ns
Data signal input setup time
(-75)
(-A6/B6)
0
0
1
0
0
0
0
0
20
2.0 ns
7
HB52RF648DC-B, HB52RD648DC-B
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
35
Data signal input hold time
(-75)
0
0
0
0
1
0
0
0
08
0.8 ns
(-A6/B6)
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
10
00
12
53
1.0 ns
36 to 61 Superset information
Future use
Rev. 1.2B
83
62
63
SPD data revision code
Checksum for bytes 0 to 62
(-75)
(-A6)
1
0
0
0
×
0
0
0
0
×
1
1
0
0
×
1
1
0
0
×
1
1
0
0
×
0
0
1
0
×
1
1
1
0
×
0
0
1
0
×
BA
3A
07
00
××
186
(-B6)
58
64
Manufacturer’s JEDEC ID code
HITACHI
65 to 71 Manufacturer’s JEDEC ID code
72
Manufacturing location
*2 (ASCII-
8bit code)
73
74
75
76
77
78
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
0
0
1
0
0
0
48
42
35
32
52
46
H
B
5
2
R
F
Manufacturer’s part number
(-75)
(-A6/B6)
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
1
1
1
0
0
0
1
0
0
0
1
0
0
1
0
1
1
1
0
1
0
1
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
1
1
44
36
34
38
44
42
2D
37
D
6
79
80
81
82
83
84
85
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
4
8
D
B
Manufacturer’s part number
(-75)
7
(-A6)
(-B6)
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
41
42
A
B
8
HB52RF648DC-B, HB52RD648DC-B
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
86
Manufacturer’s part number
(-75)
0
0
1
1
0
1
0
1
35
5
(-A6/B6)
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
36
42
20
6
87
88
Manufacturer’s part number
B
Manufacturer’s part number
(-xxB)
(Space)
(-xxBL)
0
0
0
0
0
×
1
0
0
0
0
×
0
1
1
1
1
×
0
0
0
1
0
×
1
0
0
0
0
×
1
0
0
0
0
×
0
0
0
0
0
×
0
0
0
0
0
×
4C
20
20
30
20
××
L
89
90
91
92
93
Manufacturer’s part number
Manufacturer’s part number
Revision code
(Space)
(Space)
Initial
Revision code
(Space)
Manufacturing date
Year code
(BCD)
94
Manufacturing date
×
×
×
×
×
×
×
×
××
Week code
(BCD)
3
95 to 98 Assembly serial number
99 to 125 Manufacturer specific data
*
4
—
0
—
1
—
1
—
0
—
0
—
1
—
0
—
0
—
*
126
127
Intel specification frequency
64
CF
100 MHz
CL = 2, 3
Intel specification CE# latency 1
1
0
0
1
1
1
1
support
(-75/A6)
(-B6)
1
1
0
0
1
1
0
1
CD
CL = 3
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”.
These SPD are based on Rev. 1.2B Specification.
2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on
ASCII code.)
3. Bytes 95 through 98 are assembly serial number.
4. All bits of 99 through 125 are not defined (“1” or “0”).
9
HB52RF648DC-B, HB52RD648DC-B
Block Diagram
W
S1
S0
CS WE
DQM
CS WE
DQM
CS WE
CS WE
DQM
DQM
DQMB0
DQMB4
D0
D8
D4
D12
N0, N1
N2, N3
N8, N9
DQ0
to DQ7
I/O0
to I/O7
I/O0
to I/O7
DQ32
to DQ39
I/O0
to I/O7
I/O0
to I/O7
WE
WE
CS WE
CS WE
CS
CS
DQM
DQM
DQM
DQM
DQMB1
DQMB5
D1
D9
D5
D13
N10, N11
DQ8
to DQ15
I/O0
to I/O7
I/O0
to I/O7
DQ40
to DQ47
I/O0
to I/O7
I/O0
to I/O7
CS
CS
CS
CS
WE
WE
WE
WE
DQM
DQM
DQM
DQM
DQMB2
DQMB6
D2
D10
D6
D14
N4, N5
N6, N7
N12, N13
N14, N15
DQ16
to DQ23
I/O0
to I/O7
I/O0
to I/O7
DQ48
to DQ55
I/O0
to I/O7
I/O0
to I/O7
WE
CS
DQM
CS
DQM
CS
DQM
CS
DQM
WE
WE
WE
DQMB3
DQMB7
D3
D11
D7
D15
DQ24
to DQ31
I/O0
to I/O7
I/O0
to I/O7
DQ56
to DQ63
I/O0
to I/O7
I/O0
to I/O7
Serial PD
SDA
SCL
RAS (D0 to D15)
CAS (D0 to D15)
Ax (D0 to D15)
BAx (D0 to D15)
CKE (D0 to D7)
CKE (D8 to D15)
RE
CE
SDA
SCL
U0
A0
A0 to A12
BA0, BA1
CKE0
A1
A2
V
SS
CKE1
CLK (D0, D4, D8, D12)
CLK (D1, D5, D9, D13)
CLK (D2, D6, D10, D14)
CLK (D3, D7, D11, D15)
CLK0
CLK1
* D0 to D15 : HM5225805
U0 : 2-kbit EEPROM
C0 to C15 : 0.1 µF
N0 to N15 : Network resistors (10 Ω)
V
V
V
(D0 to D15)
CC
CC
SS
C0 to C15
V
(D0 to D15)
SS
10
HB52RF648DC-B, HB52RD648DC-B
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to VSS
VT
–0.5 to VCC + 0.5
( 4.6 (max))
V
1
Supply voltage relative to VSS
Short circuit output current
Power dissipation
VCC
–0.5 to +4.6
50
V
1
Iout
PT
mA
W
8.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +65
–55 to +125
°C
°C
Note: 1. Respect to VSS.
DC Operating Conditions (Ta = 0 to +65°C)
Parameter
Symbol
VCC
Min
3.0
0
Max
3.6
Unit
Notes
1, 2
3
Supply voltage
V
V
V
V
VSS
0
Input high voltage
VIH
2.0
–0.3
VCC + 0.3
0.8
1, 4
1, 5
Input low voltage
VIL
Notes: 1. All voltage referred to VSS
2. The supply voltage with all VCC pins must be on the same level.
3. The supply voltage with all VSS pins must be on the same level.
4. VIH (max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC.
5. VIL (min) = VSS – 2.0 V for pulse width ≤ 3 ns at VSS.
11
HB52RF648DC-B, HB52RD648DC-B
DC Characteristics (Ta = 0 to +65˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
HB52RF648DC/HB52RD648DC
-75
-A6
-B6
Parameter
Symbol Min
Max
Min Max Min Max Unit Test conditions
Notes
Operating current
Burst length = 1
1, 2, 3
(CE latency = 2)
ICC1
ICC1
ICC2P
—
—
—
1120
1120
48
—
—
—
1000 —
1000 —
840 mA tRC = min
(CE latency = 3)
1000 mA
Standby current in
power down
48
—
48
32
mA CKE = VIL,
CK = 12 ns
6
7
t
Standby current in
power down
ICC2PS
—
32
—
32
—
mA CKE = VIL, tCK =
(input signal stable)
Standby current in non ICC2N
power down
—
—
—
320
64
—
—
—
320
64
—
—
—
320 mA CKE, S = VIH,
CK = 12 ns
4
t
Active standby current ICC3P
in power down
64
mA CKE = VIL,
CK = 12 ns
1, 2, 6
1, 2, 4
t
Active standby current ICC3N
in non power down
480
480
480 mA CKE, S = VIH,
CK = 12 ns
t
Burst operating
current
(CE latency = 2)
ICC4
—
1040
—
1040 —
840 mA tCK = min, BL = 4
1, 2, 5
(CE latency = 3)
Refresh current
ICC4
ICC5
ICC6
—
—
—
1320
2000
48
—
—
—
1040 —
2000 —
1040 mA
2000 mA tRC = min
3
8
Self refresh current
48
—
48
mA VIH V CC – 0.2 V
VIL 0.2 V
Self refresh current
(L-version)
ICC6
—
32
—
32
—
32
mA
Input leakage current ILI
–10
–10
10
10
–10 10
–10 10
–10 10
–10 10
µA
µA
0 Vin V
CC
Output leakage
current
ILO
0 Vout VCC
DQ = disable
Output high voltage
Output low voltage
VOH
VOL
2.4
—
—
2.4
—
—
2.4
—
—
V
V
IOH = –4 mA
IOL = 4 mA
0.4
0.4
0.4
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK0/CK1 operating current.
7. After power down mode, no CK0/CK1 operating current.
8. After self refresh mode set, self refresh current.
12
HB52RF648DC-B, HB52RD648DC-B
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
Max
90
Unit
pF
Notes
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 3, 4
Input capacitance (Address)
Input capacitance (RE, CE, W)
Input capacitance (S0/S1, CK0/CK1, CKE0/CKE1)
Input capacitance (DQMB)
CIN
CIN
CIN
CIN
CI/O
90
pF
60
pF
30
pF
Input/Output capacitance (DQ)
27
pF
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = VIH to disable Data-out.
4. This parameter is sampled and not 100% tested.
13
HB52RF648DC-B, HB52RD648DC-B
AC Characteristics (Ta = 0 to +65°C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
HB52RF648DC/HB52RD648DC
-75
-A6
-B6
HITACHI PC100
Symbol Symbol Min
Parameter
Max
Min Max
Min Max
Unit Notes
System clock cycle time
(CE latency = 2)
tCK
Tclk
Tclk
Tch
Tcl
10
—
—
—
—
10
10
3
—
—
—
—
15
10
3
—
—
—
—
ns
ns
ns
ns
1
(CE latency = 3)
CK high pulse width
CK low pulse width
tCK
7.5
2.5
2.5
tCKH
tCKL
1
1
3
3
Access time from CK
(CE latency = 2)
tAC
tAC
tOH
tLZ
Tac
Tac
Toh
—
—
2.7
2
6
—
—
3
6
—
—
3
8
ns
ns
ns
ns
1, 2
(CE latency = 3)
5.4
—
—
6
6
Data-out hold time
—
—
—
—
1, 2
CK to Data-out low
impedance
2
2
1, 2, 3
CK to Data-out high
impedance
tHZ
—
5.4
—
—
—
—
—
2
6
—
2
6
ns
ns
ns
ns
ns
1, 4
Input setup time
tAS, tCS, Tsi
tDS, tCES
1.5
1.5
0.8
67.5
45
—
—
—
—
—
—
—
—
1, 5, 6
CKE setup time for power
down exit
tCESP
Tpde
2
2
1
Input hold time
tAH, tCH
,
Thi
1
1
1, 6
1
t
DH, tCEH
Ref/Active to Ref/Active
command period
tRC
Trc
70
70
Active to Precharge
command period
tRAS
Tras
Trcd
Trp
120000 50
120000 50
120000 ns
1
Active command to column tRCD
command (same bank)
20
—
—
—
—
20
20
20
20
—
—
—
—
20
20
20
20
—
—
—
—
ns
ns
ns
ns
1
Precharge to active
command period
tRP
20
1
Write recovery or data-in to tDPL
precharge lead time
Tdpl
Trrd
15
1
Active (a) to Active (b)
command period
tRRD
15
1
Transition time (rise and fall) tT
Refresh period tREF
1
5
1
5
1
5
ns
—
64
—
64
—
64
ms
14
HB52RF648DC-B, HB52RD648DC-B
Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is CL = 50 pF.
3. tLZ (min) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max) defines the time at which the outputs achieves the high impedance state.
5. tCES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
•
•
Input and output timing reference levels: 1.5 V
Input waveform and output load: See following figures
2.4 V
DQ
2.0 V
input
0.8 V
0.4 V
CL
t
t
T
T
15
HB52RF648DC-B, HB52RD648DC-B
Relationship Between Frequency and Minimum Latency
HB52RF648DC/
HB52RD648DC
Parameter
-75
-A6/B6
Frequency (MHz)
133
100
HITACHI PC100
tCK (ns)
Symbol Symbol 7.5
10
Notes
Active command to column command
(same bank)
lRCD
lRC
lRAS
lRP
lDPL
lRRD
3
9
6
3
2
2
2
1
Active command to active command
(same bank)
7
5
2
2
2
= [lRAS+ lRP]
1
Active command to precharge command
(same bank)
1
1
1
1
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Tdpl
Active command to active command
(different bank)
Self refresh exit time
lSREX
lAPW
Tsrx
Tdal
1
5
1
4
2
Last data in to active command
(Auto precharge, same bank)
= [lDPL + lRP]
Self refresh exit to command input
lSEC
9
7
= [lRC]
3
Precharge command to high impedance
(CE latency = 2)
lHZP
lHZP
lAPR
Troh
Troh
2
3
1
2
3
1
(CE latency = 3)
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
(CE latency = 2)
lEP
–1
–2
1
–1
–2
1
(CE latency = 3)
lEP
Column command to column command
Write command to data in latency
DQMB to data in
lCCD
lWCD
lDID
lDOD
lCLE
lRSA
Tccd
Tdwd
Tdqm
Tdqz
Tcke
Tmrd
0
0
0
0
DQMB to data out
2
2
CKE to CK disable
1
1
Register set to active command
1
1
16
HB52RF648DC-B, HB52RD648DC-B
HB52RF648DC/
HB52RD648DC
Parameter
-75
-A6/B6
100
Frequency (MHz)
133
HITACHI PC100
Symbol Symbol 7.5
tCK (ns)
10
0
Notes
S to command disable
lCDD
lPEC
0
1
Power down exit to command input
Notes: 1. lRCD to lRRD are recommended value.
1
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
17
HB52RF648DC-B, HB52RD648DC-B
Pin Functions
CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK
rising edge.
S0/S1 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM
modules, they function in a different way. These pins define operation commands (read, write, etc.)
depending on the combination of their voltage levels. For details, refer to the command operation section.
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read
or write command cycle CK rising edge. And this column address becomes burst access start address. A10
defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged.
But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1 (BA) is
precharged.
BA0/BA1 (input pin): BA0/BA1 is a bank select signal (BA). The memory array is divided into bank0,
bank1, bank2 and bank3. If BA0 is Low and BA1 is Low, bank0 is selected. If BA0 is High and BA1 is
Low, bank1 is selected. If BA0 is Low and BA1 is High, bank2 is selected. If BA0 is High and BA1 is High,
bank3 is selected.
CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the
next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-
down mode, clock suspend mode and self refresh mode.
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If
the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks).
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low,
the data is written (The latency of DQMB during writing is 0 clock).
DQ0 to DQ63 (DQ pins): Data is input to and output from these pins.
VCC (power supply pins): 3.3 V is applied.
VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the SDRAM DIMM Operation Guide.
18
HB52RF648DC-B, HB52RD648DC-B
Physical Outline
mm
Unit:
inch
67.60
2.661
63.60
3.80 Max
2.504
24.50
0.965
0.150 Max
(Datum -A-)
2R3.00 Min
2R0.118 Min
Component area
(front)
B
A
3.30
23.20
0.913
32.80
1.00 ± 0.10
4.60
0.130
1.291
0.039 ± 0.004
2.50
0.181
0.098
2.10
4.60
0.083
0.181
3.70
0.146
23.20
0.913
32.80
1.291
2- ø1.80
2- ø0.071
Component area
(back)
2-R2.00
2.00 Min
0.079 Min
2-R0.079
(Datum -A-)
Detail B
Detail A
(DATUM -A-)
2.5
0.098
0.60 ± 0.05
0.024 ± 0.002
R0.75
R0.030
0.80
0.031
1.50 ± 0.10
0.059 ± 0.004
DD380125W
19
HB52RF648DC-B, HB52RD648DC-B
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
Asia
: http://semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
: http://www.hitachi.com.sg/grp3/sicd
: http://www.hitachi.co.jp/Sicd/indx.htm
Japan
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive, Dornacher Straße 3
Hitachi Europe GmbH
Electronic Components Group
Hitachi Asia Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7th Flr, North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
San Jose,CA 95134
D-85622 Feldkirchen, Munich
Tel: <1> (408) 433-1990 Germany
Fax: <1>(408) 433-0223 Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Fax: 535-1533
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Ltd.
Taipei Branch Office
3rd Flr, Hung Kuo Building, No.167,
Tun Hwa North Road, Taipei (105)
Taiwan
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 585160
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 23222 HAS-TP
Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
Colophon 1.0
20
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