HD4074869S [HITACHI]
Microcontroller, CMOS, PDIP64, PLASTIC, DIP-64;
| 型号： | HD4074869S |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Microcontroller, CMOS, PDIP64, PLASTIC, DIP-64 可编程只读存储器 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总200页 (文件大小：639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD404889/HD404899/HD404878/
HD404868 Series
Low-Voltage AS Microcomputers with On-Chip LCD Circuit
ADE-202-075D (O)
Rev. 5.0
Feb. 2000
Description
The HD404889, HD404899, and HD404868 Series comprise low-voltage, 4-bit single-chip
microcomputers with a variety of on-chip supporting functions that include an LCD circuit, A/D converter,
multifunctional timers, and large-current I/O pins. These devices are suitable for system and display panel
control in a wide range of applications, including pagers, remote controllers, and home appliances equipped
with an LCD display.
The HD404878 Series comprises low-voltage, 4-bit single-chip microcomputers with no on-chip A/D
converter.
Each series is equipped with a 32.768 kHz sub-resonator for realtime clock use, providing a time counting
facility, and a variety of low-power modes to reduce current drain.
The HD4074889, HD4074899, and HD4074869 are ZTAT™ microcomputers with on-chip PROM that
drastically shortens development time and ensures a smooth transition from debugging to mass production.
(The PROM programming specifications are the same as for the 27256 type.)
ZTATTM: Zero Turn-Around Time. ZTATTM is a trademark of Hitachi, Ltd.
Features
•
46 I/O pins (HD404889/HD404899/HD404878 Series)
41 I/O pins (HD404868 Series)
Large-current I/O pins (source: 10 mA max.):4
Large-current I/O pins (sink: 15 mA max.): 8 (HD404889/HD404899/HD404878 Series)
6 (HD404868 Series)
LCD segment multiplexed pins:16
Analog input multiplexed pins: 6 (HD404889 and HD404899 Series)
4 (HD404868 Series)
HD404889/HD404899/HD404878/HD404868 Series
•
Four Timer/counters
8-bit timer: 2 (HD404889/HD404899/HD404878 Series)
1 (HD404868 Series)
16-bit timer:1 (Can also be used as two 8-bit timer)
8-bit input capture circuit (HD404889/HD404899/HD404878 Series)
Two timer outputs (including PWM out-put)
Two event counter inputs (edge-programmable) (HD404889/HD404899/HD404878 Series)
One event counter input (edge-programmable) (HD404868 Series)
Clock-synchronous 8-bit serial interface
A/D converter
•
•
•
•
•
6 channels × 8-bit (HD404889 Series)
6 channels × 10-bit (HD404899 Series)
4 channels × 10-bit (HD404868 Series)
•
•
LCD controller/driver (32 segments × 4 commons) (HD404889/HD404899/HD404878 Series)
(24 segments × 4 commons) (HD404868 Series)
On-chip oscillators
Main clock (ceramic resonator, crystal resonator, or external clock operation possible)
Sub-clock (32.768 kHz crystal resonator)
Interrupts
•
External: 3 (including one edge-programmable)
Internal : 6 (HD404889 and HD404899 Series)
: 5 (HD404878 and HD404868 Series)
•
•
•
•
•
•
Subroutine stack up to 16 levels, including interrupts
Four Low-power dissipation modes
Module standby (timers, serial interface, A/D converter)
System clock division software switching (1/4 or 1/32)
Inputs for return from stop mode (wakeup): 4
Instruction execution time
Min. 0.89 µs (fOSC = 4.5 MHz)
•
Operation voltage
1.8 V to 5.5 V
Cautions about operation!
•
•
Electrical properties presented on the data sheet for the mask ROM and ZTATTM versions will surely
and sufficiently satisfy the standard values. However, real capabilities, operation margin, noise margin,
and other properties may vary depending on differences of manufacturing processes, internal wiring
patterns, etc. Therefore, it is requested for users to carry out an evaluation test for each product on an
actual system under the same conditions to see its operation.
Memory register, data area, and stack area values are unstable immediately after power is turned on.
They must be initialized before use.
2
HD404889/HD404899/HD404878/HD404868 Series
Ordering Information
HD404889 Series
Type
Product Name Model Name
ROM (Words)
RAM (Digits)
Package
Mask ROM HD404888
HD404888H
HD404888TE
HD4048812H
HD4048812TE
HD404889H
HD404889TE
8,192
1,344
80-pin plastic QFP
(FP-80A)
80-pin plastic TQFP
(TFP-80C)
HD4048812
HD404889
HCD404889
12,288
16,384
80-pin plastic QFP
(FP-80A)
80-pin plastic TQFP
(TFP-80C)
80-pin plastic QFP
(FP-80A)
80-pin plastic TQFP
(TFP-80C)
Chip*2
HCD404889
ZTATTM
HD4074889
HD4074889H
16,384
80-pin plastic QFP*1
(FP-80A)
HD4074889TE
80-pin plastic TQFP*1
(TFP-80C)
Notes: 1. ZTATTM chip shipment is not supported.
2. The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details.
3
HD404889/HD404899/HD404878/HD404868 Series
HD404899 Series
Type
Product Name Model Name
ROM (Words)
RAM (Digits)
Package
Mask ROM HD404898
HD404898H
HD404898TE
HD4048912H
HD4048912TE
HD404899H
HD404899TE
8,192
1,344
80-pin plastic QFP
(FP-80A)
80-pin plastic TQFP
(TFP-80C)
HD4048912
12,288
16,384
80-pin plastic QFP
(FP-80A)
80-pin plastic TQFP
(TFP-80C)
HD404899
80-pin plastic QFP
(FP-80A)
80-pin plastic TQFP
(TFP-80C)
HCD404899
HCD404899
Chip*2
ZTATTM
HD4074899
HD4074899H
16,384
80-pin plastic QFP*1
(FP-80A)
HD4074899TE
80-pin plastic TQFP*1
(TFP-80C)
Notes: 1. ZTATTM chip shipment is not supported.
2. The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details. In planning stage.
HD404878 Series
Type
Product Name Model Name
ROM (Words)
RAM (Digits)
Package
Mask ROM HD404874
HD404874H
HD404874TE
HD404878H
HD404878TE
HCD404878
4,096
880
80-pin plastic QFP
(FP-80A)
80-pin plastic TQFP
(TFP-80C)
HD404878
8,192
80-pin plastic QFP
(FP-80A)
80-pin plastic TQFP
(TFP-80C)
Chip*2
HCD404878
ZTATTM HD4074889 or HD4074899 is used.*1
Notes: 1. ZTATTM chip shipment is not supported.
2. The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details. In planning stage.
4
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
Type
Product Name Model Name
ROM (Words)
RAM (Digits)
Package
Mask ROM HD404864
HD404864H
HD404864S
HD404868H
HD404868S
4,096
408
64-pin plastic QFP
(FP-64A)
64-pin plastic DILP
(DP-64S)
HD404868
8,192
64-pin plastic QFP
(FP-64A)
64-pin plastic DILP
(DP-64S)
HCD404868
HCD404868
Chip*1
ZTATTM
HD4074869
HD4074869H
16,384
64-pin plastic QFP
(FP-64A)
HD4074869S
64-pin plastic DILP
(DP-64S)
Note: 1. In planning stage
5
HD404889/HD404899/HD404878/HD404868 Series
List of Functions
Product Name
ROM (words)
RAM (digit)
I/O
HD404888
HD4048812
HD404889
HCD404889
8,192
12,288
16,384
1,344
46 (max)
Large-current I/O pins
4 (source, 10 mA max), 8 (sink, 15 mA max)
LCD segment multiplexed pins
Analog input multiplexed pins
16
6
Timer/counter
16-bit timer: 1 (Can also be used as two 8-bit timer),
8-bit timer: 2
Input capture
Timer output
Event input
8 bit × 1
2 (PWM output possible)
2 (edge selection possible)
Serial interface
1 (8-bit synchronous)
A/D converter
8 bits × 6 channels
LCD circuit
Max. 32 seg × 4 com
Interrupt sources External
Internal
3 (edge selection possible for 1)
6
Low-power modes
Stop mode
4
O
Watch mode
O
Standby mode
O
Subactive mode
Module standby
System clock division software switching
O
O
O
Main oscillator
Ceramic oscillation
Crystal oscillation
Crystal oscillation
O
O
Sub-oscillator
O (32.768kHz)
0.89µs(fOSC=4.5MHz)
1.8 to 5.5
Minimum instruction execution time
Operating voltage (V)
Package
80-pin plastic QFP (FP-80A)
80-pin plastic TQFP (TFP-80C)
–20 to +75
Chip
+75
Guaranteed operation temperature(°C)
6
HD404889/HD404899/HD404878/HD404868 Series
Product Name
ROM (words)
RAM (digit)
I/O
HD4074889
HD404898
HD4048912
HD404899
16,384PROM
8,192
12,288
16,384
1,344
46 (max)
Large-current I/O pins
4 (source, 10 mA max), 8 (sink, 15 mA max)
LCD segment multiplexed pins
Analog input multiplexed pins
16
6
16-bit timer: 1 (Can also be used as two 8-bit timer),
8-bit timer: 2
Timer/counter
Input capture
Timer output
Event input
8 bit × 1
2 (PWM output possible)
2 (edge selection possible)
1 (8-bit synchronous)
Serial interface
A/D converter
8 bits × 6
channels
10 bits × 6 channels
LCD circuit
Max. 32 seg × 4 com
Interrupt sources External
Internal
3 (edge selection possible for 1)
6
Low-power modes
Stop mode
4
O
Watch mode
O
Standby mode
O
Subactive mode
Module standby
O
O
System clock division software switching
O
Main oscillator
Ceramic oscillation
Crystal oscillation
Crystal oscillation
O
O
Sub-oscillator
O (32.768kHz)
0.89µs(fOSC=4.5MHz)
1.8 to 5.5
Minimum instruction execution time
Operating voltage (V)
2.0 to 5.5
Package
80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C)
–20 to +75
Guaranteed operation temperature(°C)
7
HD404889/HD404899/HD404878/HD404868 Series
Product Name
ROM (words)
RAM (digit)
I/O
HD40C4899
HD4074899
HD404874
HD404878
16,384
16,384PROM
4,096
8,192
1,344
880
46 (max)
Large-current I/O pins
4 (source, 10 mA max), 8 (sink, 15 mA max)
16
LCD segment multiplexed pins
Analog input multiplexed pins
6
—
Timer/counter
16-bit timer: 1 (Can also be used as two 8-bit timer),
8-bit timer: 2
Input capture
Timer output
Event input
8 bit × 1
2 (PWM output possible)
2 (edge selection possible)
1 (8-bit synchronous)
Serial interface
A/D converter
10 bits × 6 channels
Max. 32 seg × 4 com
3 (edge selection possible for 1)
—
LCD circuit
Interrupt sources External
Internal
6
5
Low-power modes
Stop mode
4
O
Watch mode
O
Standby mode
O
Subactive mode
Module standby
System clock division software switching
O
O
O
Main oscillator
Ceramic oscillation
Crystal oscillation
Crystal oscillation
O
O
Sub-oscillator
O (32.768kHz)
0.89µs(fOSC=4.5MHz)
Minimum instruction execution time
Operating voltage (V)
Package
1.8 to 5.5
Chip
2.0 to 5.5
1.8 to 5.5
80-pin plastic QFP (FP-80A)
80-pin plastic TQFP (TFP-80C)
–20 to +75
Guaranteed operation temperature(°C)
+75
8
HD404889/HD404899/HD404878/HD404868 Series
Product Name
ROM (words)
RAM (digit)
I/O
HCD404878
8,192
HD404864
4,096
HD404868
HD4074869
8,192
16,384PROM
880
408
46 (max)
41 (max)
Large-current I/O pins
4 (source,
10 mA max),
8 (sink,
4 (source, 10 mA max), 6 (sink, 15 mA max)
15 mA max)
LCD segment multiplexed pins
Analog input multiplexed pins
16
—
4
Timer/counter
16-bit timer: 1
(Can also be
used as two
8-bit timer),
8-bit timer: 2
16-bit timer: 1 (Can also be used as two 8-bit
timer), 8-bit timer: 1
Input capture
Timer output
Event input
8 bit × 1
—
2 (PWM output possible)
1 (edge selection possible)
2 (edge
selection
possible)
Serial interface
1 (8-bit synchronous)
A/D converter
LCD circuit
—
10 bits × 4 channels
Max. 32 seg × Max. 24 seg × 4 com
4 com
Interrupt sources External
Internal
3 (edge selection possible for 1)
5
Low-power modes
Stop mode
4
O
Watch mode
O
Standby mode
O
Subactive mode
O
Module standby
O
System clock division software switching
O
Main oscillator
Ceramic oscillation
Crystal oscillation
Crystal oscillation
O
O
Sub-oscillator
O (32.768kHz)
0.89µs(fOSC=4.5MHz)
Minimum instruction execution time
Operating voltage (V)
Package
1.8 to 5.5
Chip
2.0 to 5.5
64-pin plastic QFP (FP-64A)
64-pin plastic DILP (DP-64S)
–20 to +75
Guaranteed operation temperature(°C)
+75
9
HD404889/HD404899/HD404878/HD404868 Series
Pin Arrangement
HD404889/HD404899 Series
AVcc
R70/AN0
R71/AN1
R72/AN2
R73/AN3
R80/AN4
R81/AN5
AVss
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG20
SEG19
SEG18
SEG17
R63/SEG16
R62/SEG15
R61/SEG14
R60/SEG13
R53/SEG12
R52/SEG11
R51/SEG10
R50/SEG9
R43/SEG8
R42/SEG7
R41/SEG6
R40/SEG5
R33/SEG4
R32/SEG3
R31/SEG2
R30/SEG1
TEST
OSC1
OCS2
GND
9
10
11
12
13
14
15
16
17
18
19
20
FP-80A
TFP-80C
(Top View)
X2
X1
RESET
Vcc
D0/INT0
D1/INT1
D2
D3
10
HD404889/HD404899/HD404878/HD404868 Series
HD404878 Series
NC
R70
R71
R72
R73
R80
R81
NC
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG20
SEG19
SEG18
SEG17
R63/SEG16
R62/SEG15
R61/SEG14
R60/SEG13
R53/SEG12
R52/SEG11
R51/SEG10
R50/SEG9
R43/SEG8
R42/SEG7
R41/SEG6
R40/SEG5
R33/SEG4
R32/SEG3
R31/SEG2
R30/SEG1
TEST
OSC1
OSC2
GND
X2
X1
RESET
Vcc
9
10
11
12
13
14
15
16
17
18
19
20
FP-80A
TFP-80C
(Top View)
D0/INT0
D1/INT1
D2
D3
11
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R62/SEG15
R61/SEG14
R60/SEG13
R53/SEG12
R52/SEG11
R51/SEG10
R50/SEG9
R43/SEG8
R42/SEG7
R41/SEG6
R40/SEG5
R33/SEG4
R32/SEG3
R31/SEG2
R30/SEG1
R23
R70/AN0
R71/AN1
R72/AN2
R73/AN3
TEST
OSC1
OSC2
GND
1
2
3
4
5
6
7
8
FP-64A
(Top View)
X2
X1
9
10
11
12
13
14
15
16
RESET
Vcc
D0/INT0
D1/INT1
D2
D3
COM1
COM2
COM3
COM4
V3
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
R63/SEG16
R62/SEG15
R61/SEG14
R60/SEG13
R53/SEG12
R52/SEG11
R51/SEG10
R50/SEG9
R43/SEG8
R42/SEG7
R41/SEG6
R40/SEG5
R33/SEG4
R32/SEG3
R31/SEG2
R30/SEG1
R23
V2
V1
R70/AN0
R71/AN1
R72/AN2
R73/AN3
TEST
OSC1
OSC2
GND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DP-64S
(Top View)
X2
X1
RESET
Vcc
D0/INT0
D1/INT1
D2
D3
D4
D5
D6
D7
D8
D9
R22/SI/SO
R21/SCK
R20/TOC
R13/TOB
R12/BUZZ
R11
R00/WU0
R01/WU1
R02/WU2
R10/EVNB
12
HD404889/HD404899/HD404878/HD404868 Series
Pad Arrangement
HCD404889, HCD404899
Model Name
1
3
5
7
2
4
6
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
9
10
12
14
16
18
20
11
13
15
17
19
Model Name: HD404889 (HCD404889)
HD404899 (HCD404899)
13
HD404889/HD404899/HD404878/HD404868 Series
Pad Coordinates
HCD404889, HCD404899
Y
Chip size (X × Y):
4.63 × 4.77 (mm)
Pad center
Coordinates:
Home point position: Chip center
Mold
Pad size (X × Y):
90 × 90 (µm)
280 (µm)
Chip thickness:
X
Chip center
(X=0,Y=0)
Coodinates
X (µm)
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–2129
–1677
–1506
–1335
–1163
–992
Coodinates
X (µm)
Pad No. Pad name
Y (µm)
Pad No. Pad name
Y (µm)
AVCC
1
1779 41
1589 42
1417 43
1246 44
1074 45
903 46
R30/SEG1
R31/SEG2
R32/SEG3
R33/SEG4
R40/SEG5
R41/SEG6
R42/SEG7
R43/SEG8
R50/SEG9
R51/SE10
R52/SEG11
R53/SEG12
R60/SEG13
R61/SEG14
R62/SEG15
R63/SEG16
SEG17
2129
2129
2129
2129
2129
2129
2129
2129
2129
2129
2129
2129
2129
2129
2129
2129
2129
2129
2129
2129
1588
1407
1236
1064
893
–1787
–1616
–1445
–1273
–1102
–973
–759
–588
–417
–245
–74
2
3
4
5
6
7
8
R70/AN0
R71/AN1
R72/AN2
R73/AN3
R80/AN4
R81/AN5
AVSS
732 47
506 48
9
TEST
OSC1
OSC2
GND
X2
X1
RESETN
VCC
103 49
–68 50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
–240 51
–434 52
–605 53
–776 54
–948 55
–1119 56
–1290 57
–1462 58
–1633 59
–1804 60
–2199 61
–2199 62
–2199 63
–2199 64
–2199 65
–2199 66
–2199 67
–2199 68
–2199 69
–2199 70
–2199 71
–2199 72
–2199 73
–2199 74
–2199 75
–2199 76
–2199 77
–2199 78
–2199 79
–2199 80
98
269
440
612
783
D0/INT0N
D1/INT1
D2
D3
D4
D5
D6
D7
D8
954
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
1126
1297
1477
2199
2199
2199
2199
2199
2199
2199
2199
2199
2199
2199
2199
2199
2199
2199
2199
2199
2199
2199
2199
D9
D10
D11
–821
–649
–478
–307
–135
36
208
379
550
722
893
1064
1236
1407
1588
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
COM1
722
550
379
208
R00/WU0N
R01/WU1N
R02/WU2N
R03/WU3N
R10/EVNB
R11/EVND
R12/BUZZ
R13/TOB
R20/TOC
R21/SCKN
R22/Si/SO
R23
36
–135
–307
–478
–649
–821
–992
–1163
–1335
–1506
–1677
COM2
COM3
COM4
V3
V2
V1
V0
14
HD404889/HD404899/HD404878/HD404868 Series
Pad Arrangement
HCD404878
Model Name
1
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Model Name: HD404878 (HCD404878)
15
HD404889/HD404899/HD404878/HD404868 Series
Pad Coordinates
HCD404878
Y
Chip size (X × Y):
4.13 × 4.26 (mm)
Pad center
Coordinates:
Home point position: Chip center
Mold
Pad size (X × Y):
90 × 90 (µm)
280 (µm)
Chip thickness:
X
Chip center
(X=0,Y=0)
Coodinates
X (µm)
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1879
–1654
–1488
–1322
–1155
–989
Coodinates
X (µm)
Pad No. Pad name
Y (µm)
Pad No. Pad name
Y (µm)
R70
1
1446 40
1280 41
1114 42
948 43
781 44
615 45
449 46
282 47
116 48
–73 49
R31/SEG2
R32/SEG3
R33/SEG4
R40/SEG5
R41/SEG6
R42/SEG7
R43/SEG8
R50/SEG9
R51/SE10
R52/SEG11
R53/SEG12
R60/SEG13
R61/SEG14
R62/SEG15
R63/SEG16
SEG17
1879
1879
1879
1879
1879
1879
1879
1879
1879
1879
1879
1879
1879
1879
1879
1879
1879
1879
1879
1509
1351
1192
1033
874
716
557
398
239
81
–78
–237
–411
–570
–728
–887
–1038
–1194
–1351
–1507
–1405
–1239
–1072
–906
–740
–573
–407
–241
–74
92
258
425
591
2
R71
3
R72
4
R73
5
R80
6
R81
7
8
9
TEST
OSC1
OSC2
GND
X2
X1
RESETN
VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
–239 50
–406 51
–572 52
–738 53
–905 54
–1071 55
–1237 56
–1404 57
–1943 58
–1943 59
–1943 60
–1943 61
–1943 62
–1943 63
–1943 64
–1943 65
–1943 66
–1943 67
–1943 68
–1943 69
–1943 70
–1943 71
–1943 72
–1943 73
–1943 74
–1943 75
–1943 76
–1943 77
–1571 78
757
D0/INT0N
D1/INT1
D2
D3
D4
D5
D6
D7
D8
924
1087
1246
1405
1564
1943
1943
1943
1943
1943
1943
1943
1943
1943
1943
1943
1943
1943
1943
1943
1943
1943
1943
1943
1943
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
D9
D10
D11
–823
–656
–490
–324
–158
9
175
341
508
674
840
1007
1173
1339
1506
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
COM1
R00/WU0N
R01/WU1N
R02/WU2N
R03/WU3N
R10/EVNB
R11/EVND
R12/BUZZ
R13/TOB
R20/TOC
R21/SCKN
R22/Si/SO
R23
COM2
COM3
COM4
V3
V2
V1
V0
R30/SEG1
1879
16
HD404889/HD404899/HD404878/HD404868 Series
Pin Description
HD404889/HD404899/HD404878 Series
Pin Number
FP-80A
Item
Symbol
VCC
TFP-80C
I/O
—
Function
Power supply
16
12
9
Apply the power supply voltage to this pin.
Connect to ground.
GND
—
Test
TEST
Input
Not for use by the user application. Connect to GND
potential.
Reset
RESET
15
10
Input
Input
Used to reset the MCU.
Oscillation
OSC1
Internal oscillator input/output pins. Connect a ceramic
resonator, crystal resonator, or external
oscillator circuit.
OSC2
X1
11
14
Output
Input
Realtime clock oscillator input/output pins. Connect a
32.768 kHz crystal. If 32.768 kHz
crystal oscillation is not used, fix the ×1 pin to VCC and
X2
13
Output
I/O
leave the ×2 pin open.
Port
D0–D11
17–28
I/O pins addressed bit by bit. D0 to D3 are large-current
source pins (max. 10 mA), and D4 to D11 are large-
current sink pins (max. 15 mA).
R00–R63
R70–R81
29–56, 2–7
I/O
I/O pins, addressed in 4-bit units.
Interrupt
Wakeup
INT0,INT1
WU0–WU3
17,18
Input
Input
External interrupt input pins
29–32
Input pins used for transition from stop mode to active
mode.
Serial interface
SCK
38
I/O
Serial interface clock I/O pin
SI
39
Input
Serial interface receive data input pin
SO
39
Output Serial interface transmit data output pin
Output Timer output pins
Timer
LCD
TOB,TOC
EVNB,EVND
V0–V3
36,37
33,34
80–77
Input
—
Event count input pins
LCD driver power supply pins. The on-chip power
supply dividing resistor can be disconnected by
software. Power supply conditions are:
VCC≥V1≥V2≥V3≥GND.
COM1–COM4
73–76
Output LCD common signal pins
Output LCD segment signal pins
SEG1–SEG32 41–72
A/D converter*1
AVCC
AVSS
1
8
—
A/D converter power supply pin. Connect as close as
possible to the VCC pin so as to be at the same potential
as VCC
.
—
Ground pin for AVCC. Connect as close as possible to
the GND pin so as to be at the same potential as GND.
AN0–AN5
BUZZ
2–7
35
Input
A/D converter analog input pins
Buzzer output
Other
Output Timer overflow toggle output or divided system clock
output pin
NC
1, 8*2
—
Connect to ground potential.
Notes: 1. Applies to HD404889 and HD404899 series.
2. Applies to HD404878 series.
17
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
Pin Number
FP-64A
DP-64S
Item
Symbol
VCC
I/O
—
Function
Power supply
12
8
19
15
12
Apply the power supply voltage to this pin.
Connect to ground.
GND
—
Test
TEST
5
Input
Not for use by the user application. Connect to
GND potential.
Reset
RESET
11
6
18
13
Input
Input
Used to reset the MCU.
Oscillation
OSC1
Internal oscillator input/output pins. Connect a
ceramic resonator, crystal resonator, or external
oscillator circuit.
OSC2
X1
7
14
17
Output
Input
10
Realtime clock oscillator input/output pins. Connect
a 32.768 kHz crystal. If 32.768 kHz
crystal oscillation is not used, fix the ×1 pin to VCC
X2
9
16
Output
I/O
and leave the ×2 pin open.
Port
D0–D9
13–22
20–29
I/O pins addressed bit by bit. D0 to D3 are large-
current source pins (max. 10 mA), and D4 to D9 are
large-current sink pins (max. 15 mA).
R00–R02
R10–R63
R70–R73
23–25
26–49
1–4
30–32
33–56
8–11
I/O
I/O pins, addressed in 4-bit units.
Interrupt
Wakeup
INT0,INT1
WU0–WU2
13,14
20, 21
30–32
Input
Input
External interrupt input pins
23–25
Input pins used for transition from stop mode to
active mode.
Serial interface
SCK
31
38
I/O
Serial interface clock I/O pin
SI
32
39
Input
Serial interface receive data input pin
SO
32
39
Output Serial interface transmit data output pin
Output Timer output pins
Timer
LCD
TOB,TOC
EVNB
V1–V3
29, 30
26
36, 37
33
Input
—
Event count input pins
64–62
7–5
LCD driver power supply pins. The on-chip power
supply dividing resistor can be disconnected by
software. Power supply conditions are:
VCC≥V1≥V2≥V3≥GND.
COM1–COM4
58–61
1–4
Output LCD common signal pins
Output LCD segment signal pins
SEG1–SEG24 34–57
41–64
8–11
35
A/D converter
Buzzer output
AN0–AN3
BUZZ
1–4
28
Input
A/D converter analog input pins
Output Timer overflow toggle output or divided system
clock output pin
18
HD404889/HD404899/HD404878/HD404868 Series
Block DiagramG
HD404889/HD404899 Series
D
D
D
D
D
D
D
D
D
D
D
D
0
HMCS400 CPU
1
P-MOS large-
current buffer
2
3
4
5
ROM
RAM
6
7
N-MOS large-
current buffer
8
9
10
11
INT
0
External interrupt
control circuit
R0
0
R0
1
R0
2
R0
3
R1
0
R1
1
R1
2
R1
3
R2
0
R2
1
R2
2
R2
3
R3
0
R3
1
R3
2
R3
3
R4
0
R4
1
R4
2
R4
3
R5
0
R5
1
R52
R53
R60
R61
R6
2
R6
3
R7
0
R7
1
R7
2
R7
3
R8
0
R8
1
INT
1
8-bit timer A
8-bit timer B
TOB
EVNB
8-bit timer C
8-bit timer D
TOC
EVND
Synchronous
serial interface
SCK
SI/SO
AVcc
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
A/D converter
8-bit × 6 channels
(HD404889 Series)
10-bit × 6 channels
(HD404899 Series)
AVss
SEG1
to
SEG32
COM1
to
COM4
LCD circuit
32-segment × 4 common
V0
V1
V2
V3
BUZZ
Buzzer output circuit
: Data bus
: Signal line
19
HD404889/HD404899/HD404878/HD404868 Series
HD404878 Series
D
D
D
D
D
D
D
D
D
D
D
D
0
HMCS400 CPU
1
P-MOS large-
current buffer
2
3
4
5
ROM
RAM
6
7
N-MOS large-
current buffer
8
9
10
11
INT
0
External interrupt
control circuit
R0
0
R0
1
R0
2
R0
3
R1
0
R1
1
R1
2
R1
3
R2
0
R2
1
R2
2
R2
3
R3
0
R3
1
R3
2
R3
3
R4
0
R4
1
R4
2
R4
3
R5
0
R5
1
R52
R53
R60
R61
R6
2
R6
3
R7
0
R7
1
R7
2
R7
3
R8
0
R8
1
INT
1
8-bit timer A
8-bit timer B
TOB
EVNB
8-bit timer C
8-bit timer D
TOC
EVND
Clock-synchronous
8-bit serial interface
SCK
SI/SO
SEG1
to
SEG32
COM1
to
COM4
LCD circuit
32-segment × 4 common
V0
V1
V2
V3
BUZZ
Buzzer output circuit
: Data bus
: Signal line
20
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
HMCS400 CPU
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
P-MOS large-
current buffer
RAM
ROM
N-MOS large-
current buffer
INT0
INT1
External interrupt control circuit
R00
R01
R02
8-bit timer A
8-bit timer B
R10
R11
R12
R13
EVNB
TOB
R20
R21
R22
R23
TOC
8-bit timer C
SCK
SI/SO
R30
R31
R32
R33
Clock-synchronous 8-bit serial interface
AN0
AN1
AN2
AN3
R40
R41
R42
R43
A/D converter
4 channels × 10-bit
R50
R51
R52
R53
SEG1
SEG24
COM1
R60
R61
R62
R63
LCD circuit
24-segment × 4 common
COM4
V1
V2
V3
R70
R71
R72
R73
BUZZ
Buzzer output circuit
21
HD404889/HD404899/HD404878/HD404868 Series
Memory Map
ROM Memory Map
The ROM memory map is shown in figure 1 and is described below.
Vector address area ($0000 to $000F): When an MCU reset or interrupt handling is performed, the
program is executed from the vector address. A JMPL instruction should be used to branch to the start
address of the reset routine or the interrupt routine.
Zero page subroutine area ($0000 to $003F):A branch can be made to a subroutine in the area $0000 to
$003F with the CAL instruction.
Pattern area ($0000 to $0FFF): ROM data in the area $0000 to $0FFF can be referenced as pattern data
with the P instruction.
Program area ($0000 to $0FFF(HD404874, HD404864)), ($0000 to $1FFF (HD404888, HD404898,
HD404878, HD404868, HCD404878)), ($0000 to $2FFF (HD4048812, HD4048912)), ($0000 to $3FFF
(HD404889, HD404899, HCD404889, HCD404899, HD4074899, HD4074889, HD4074869))
22
HD404889/HD404899/HD404878/HD404868 Series
$0000
$000F
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
JMPL instruction
(Jump to reset routine)
Vector addresses
(16 words)
JMPL instruction
(Jump to WU0 to WU3 routine)
Zero page subroutine area
(64 words)
JMPL instruction
(Jump to INT0 routine)
$003F
$0FFF
JMPL instruction
(Jump to INT1 routine)
HD404874/HD404864
pattern/program area
(4,096 words)
JMPL instruction
(Jump to timer A routine)
JMPL instruction
(Jump to timer B/timer D routine)
JMPL instruction
(Jump to timer C routine)
HD404888/HD404898/HD404878/
HD404868/HCD404878
pattern/program area
(8,192 words)
JMPL instruction
(Jump to A/D or serial interface routine)
$1FFF
HD4048812/HD4048912
pattern/program area
(12,288 words)
$2FFF
HD404889/HD4074889/
HD404899/HD4074899/HD4074869/
HCD404889/HCD404899
pattern/program area
(16,384 words)
$3FFF
Figure 1 ROM Memory Map
RAM Memory Map
The MCU has on-chip RAM comprising a memory register area, LCD data area, data area, and stack area.
In addition to these areas, an interrupt control bit area, special register area, and register flag area are
mapped onto RAM memory space as a RAM-mapped register area.The RAM memory map is shown in
figure 2 and described below.
Memory register, LCD data area, data area, and stack area values are unstable immediately after
power is turned on. They must be initialized before use.
23
HD404889/HD404899/HD404878/HD404868 Series
HD404889 Series
$000
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
Interrupt control bit area
RAM-mapped
register area
Speed Select Reg.
Miscellaneous Reg.
Edge Select Reg.
(SSR)
(MIS)
(ESR)
W
W
W
Not used
$03F
$040
Port Mode Reg.0
Port Mode Reg.1
Port Mode Reg.2
Port Mode Reg.3
(PMR0)
(PMR1)
(PMR2)
(PMR3)
(PMR4)
(MSR1)
(MSR2)
(TMA)
W
W
W
W
W
W
W
W
W
W
Memory register (MR) area
(16 digits)
$04F
$050
LCD data area
(32 digits)
Port Mode Reg.4
Module Standby Reg.1
Module Standby Reg.2
Timer Mode Reg.A
Timer Mode Reg.B1
Timer Mode Reg.B2
$06F
$070
Not used
(TMB1)
(TMB2)
$08F
$090
*
*
(TRBL/TWBL) R/W
(TRBU/TWBU) R/W
Timer-B
Timer Mode Reg.C1
Timer Mode Reg.C2
(TMC1)
(TMC2)
W
W
(TRCL/TWCL) R/W
(TRCU/TWCU) R/W
Timer-C
Timer Mode Reg.D1
Timer Mode Reg.D2
(TMD1)
(TMD2)
W
W
(TRDL/TWDL) R/W
(TRDU/TWDU) R/W
Timer-D
Data (464 digits)
V = 1 (bank = 1)
Data (464 digits)
V = 0 (bank = 0)
Not used
Register flag area
Serial Mode Reg.1
(SMR1)
(SMR2)
(SRL) R/W
(SRU) R/W
W
W
Serial Mode Reg.2
Serial Data Reg.Lower
Serial Data Reg.Upper
A/D Mode reg.
$25F
$260
(AMR)
W
Not used
A/D Data Reg.Lower
A/D Data Reg.Upper
LCD Control Reg.
LCD Mode Reg.
(ADRL)
(ADRU)
(LCR)
(LMR)
(BMR)
R
R
W
W
W
Data (304 digits)
Buzzer Mode Reg.
Not used
Port D0
Port D4
Port D8
D3 DCR
D7 DCR
D11 DCR
(DCD0)
(DCD1)
(DCD2)
W
W
W
~
~
~
$38F
$390
Not used
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
Port R8 DCR
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
W
W
W
W
W
W
W
W
W
Not used
$3BF
$3C0
Stack area
(64 digits)
Not used
Vreg.
(V) R/W
$3FF
$012 Timer Read Reg.B Lower
$013 Timer Read Reg.B Upper
(TRBL)
(TRBU)
R
R
Timer Write Reg.B Lower
Timer Write Reg.B Upper
(TWBL)
(TWBU)
W
W
Notes:
R
W
: Read
: Write
R/W : Read/Write
$016 Timer Read Reg.C Lower
$017 Timer Read Reg.C Upper
(TRCL)
(TRCU)
R
R
Timer Write Reg.C Lower
Timer Write Reg.C Upper
(TWCL)
(TWCU)
W
W
*Two registers are mapped onto the
same address ($012, $013, $016,
$017, $01A, $01B).
$01A Timer Read Reg.D Lower
$01B Timer Read Reg.D Upper
(TRDL)
(TRDU)
R
R
Timer Write Reg.D Lower
Timer Write Reg.D Upper
(TWDL)
(TWDU)
W
W
Figure 2 RAM Memory Map
24
HD404889/HD404899/HD404878/HD404868 Series
HD404899 Series
$000
$000
$001
Interrupt control bit area
$002
RAM-mapped
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
Speed Select Reg.
Miscellaneous Reg.
Edge Select Reg.
(SSR)
(MIS)
(ESR)
W
W
W
register area
Not used
$03F
$040
Port Mode Reg.0
Port Mode Reg.1
Port Mode Reg.2
Port Mode Reg.3
(PMR0)
(PMR1)
(PMR2)
(PMR3)
(PMR4)
(MSR1)
(MSR2)
(TMA)
W
W
W
W
W
W
W
W
W
W
Memory register (MR) area
(16 digits)
$04F
$050
LCD data area
(32 digits)
Port Mode Reg.4
Module Standby Reg.1
Module Standby Reg.2
Timer Mode Reg.A
Timer Mode Reg.B1
Timer Mode Reg.B2
$06F
$070
Not used
(TMB1)
(TMB2)
$08F
$090
*
(TRBL/TWBL) R/W
(TRBU/TWBU) R/W
(TMC1)
(TMC2)
(TRCL/TWCL) R/W
(TRCU/TWCU) R/W
(TMD1)
(TMD2)
(TRDL/TWDL) R/W
(TRDU/TWDU) R/W
Timer-B
Timer Mode Reg.C1
Timer Mode Reg.C2
W
W
Timer-C
Timer Mode Reg.D1
Timer Mode Reg.D2
W
W
Timer-D
Data (464 digits)
V = 1 (bank = 1)
Data (464 digits)
V = 0 (bank = 0)
Not used
Register flag area
Serial Mode Reg.1
(SMR1)
(SMR2)
(SRL) R/W
(SRU) R/W
(AMR)
(ADRL)
(ADRM)
(ADRU)
(LCR)
W
W
Serial Mode Reg.2
Serial Data Reg.Lower
Serial Data Reg.Upper
A/D Mode reg.
A/D Data Reg.Lower
A/D Data Reg.Middle
A/D Data Reg.Upper
LCD Control Reg.
LCD Mode Reg.
$25F
$260
W
R
R
R
Data (304 digits)
W
W
W
(LMR)
(BMR)
Buzzer Mode Reg.
Not used
Port D0
Port D4
Port D8
D3 DCR
D7 DCR
D11 DCR
(DCD0)
(DCD1)
(DCD2)
W
W
W
~
~
~
$38F
$390
Not used
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
Port R8 DCR
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
W
W
W
W
W
W
W
W
W
Not used
$3BF
$3C0
Stack area
(64 digits)
Not used
Vreg.
(V) R/W
$3FF
$012 Timer Read Reg.B Lower
$013 Timer Read Reg.B Upper
(TRBL)
(TRBU)
R
R
Timer Write Reg.B Lower
Timer Write Reg.B Upper
(TWBL)
(TWBU)
W
W
Notes:
R
W
: Read
: Write
R/W : Read/Write
$016 Timer Read Reg.C Lower
$017 Timer Read Reg.C Upper
(TRCL)
(TRCU)
R
R
Timer Write Reg.C Lower
Timer Write Reg.C Upper
(TWCL)
(TWCU)
W
W
*Two registers are mapped onto the
same address ($012, $013, $016,
$017, $01A, $01B).
$01A Timer Read Reg.D Lower
$01B Timer Read Reg.D Upper
(TRDL)
(TRDU)
R
R
Timer Write Reg.D Lower
Timer Write Reg.D Upper
(TWDL)
(TWDU)
W
W
Figure 2 RAM Memory Map (cont)
25
HD404889/HD404899/HD404878/HD404868 Series
HD404878 Series
$000
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
Interrupt control bit area
RAM-mapped
register area
Speed Select Reg.
Miscellaneous Reg.
Edge Select Reg.
(SSR)
(MIS)
(ESR)
W
W
W
Not used
$03F
$040
Port Mode Reg.0
Port Mode Reg.1
Port Mode Reg.2
Port Mode Reg.3
(PMR0)
(PMR1)
(PMR2)
(PMR3)
(PMR4)
(MSR1)
(MSR2)
(TMA)
W
W
W
W
W
W
W
W
W
W
Memory register (MR) area
(16 digits)
$04F
$050
LCD data area
(32 digits)
Port Mode Reg.4
Module Standby Reg.1
Module Standby Reg.2
Timer Mode Reg.A
Timer Mode Reg.B1
Timer Mode Reg.B2
$06F
$070
Not used
(TMB1)
(TMB2)
$08F
$090
*
(TRBL/TWBL) R/W
(TRBU/TWBU) R/W
Timer-B
Timer Mode Reg.C1
Timer Mode Reg.C2
(TMC1)
(TMC2)
W
W
(TRCL/TWCL) R/W
(TRCU/TWCU) R/W
Timer-C
Timer Mode Reg.D1
Timer Mode Reg.D2
(TMD1)
(TMD2)
W
W
(TRDL/TWDL) R/W
(TRDU/TWDU) R/W
Timer-D
Not used
Data (768 digits)
Register flag area
Serial Mode Reg.1
Serial Mode Reg.2
(SMR1)
(SMR2)
W
W
Serial Data Reg.Lower
Serial Data Reg.Upper
(SRL) R/W
(SRU) R/W
Not used
LCD Control Reg.
LCD Mode Reg.
Buzzer Mode Reg.
(LCR)
(LMR)
(BMR)
W
W
W
Not used
Port D0
Port D4
Port D8
D3 DCR
D7 DCR
D11 DCR
(DCD0)
(DCD1)
(DCD2)
W
W
W
~
~
~
$38F
$390
Not used
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
Port R8 DCR
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
W
W
W
W
W
W
W
W
W
Not used
$3BF
$3C0
Stack area
(64 digits)
Not used
$3FF
$012 Timer Read Reg.B Lower
$013 Timer Read Reg.B Upper
(TRBL)
(TRBU)
R
R
Timer Write Reg.B Lower
Timer Write Reg.B Upper
(TWBL)
(TWBU)
W
W
Notes:
R
W
: Read
: Write
R/W : Read/Write
$016 Timer Read Reg.C Lower
$017 Timer Read Reg.C Upper
(TRCL)
(TRCU)
R
R
Timer Write Reg.C Lower
Timer Write Reg.C Upper
(TWCL)
(TWCU)
W
W
*Two registers are mapped onto the
same address ($012, $013, $016,
$017, $01A, $01B).
$01A Timer Read Reg.D Lower
$01B Timer Read Reg.D Upper
(TRDL)
(TRDU)
R
R
Timer Write Reg.D Lower
Timer Write Reg.D Upper
(TWDL)
(TWDU)
W
W
Figure 2 RAM Memory Map (cont)
26
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
$000
$000
$001
Interrupt control bit area
$002
$003
RAM-mapped
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
Speed Select Reg.
Miscellaneous Reg.
Edge Select Reg.
(SSR)
(MIS)
(ESR)
W
W
W
register area
$03F
$040
$04F
$050
Not used
Port Mode Reg.0
Port Mode Reg.1
Port Mode Reg.2
Port Mode Reg.3
Port Mode Reg.4
(PMR0)
(PMR1)
W
W
Memory register (MR) area
(16 digits)
(PMR2)
W
LCD data area
(24 digits)
(PMR3)
W
(PMR4)
W
$067
$068
Module Standby Reg.1
Module Standby Reg.2
Timer Mode Reg.A
Timer Mode Reg.B1
Timer Mode Reg.B2
Timer B
(MSR1)
W
(MSR2)
W
(TMA)
W
Not used
(TMB1)
W
$08F
$090
(TMB2)
W
(TRBL/TWBL)
(TRBU/TWBU)
(TMC1)
R/W
R/W
W
*
Timer Mode Reg.C1
Timer Mode Reg.C2
Timer C
(TMC2)
W
(TRCL/TWCL)
(TRCU/TWCU)
R/W
R/W
Data
(304 digits)
Not used
Register flag area
(SMR1)
(SMR2)
W
W
Serial Mode Reg.1
Serial Mode Reg.2
Serial Mode Reg.Lower
Serial Mode Reg.Upper
A/D Mode reg.
(SRL) R/W
(SRU) R/W
$1BF
$1C0
(AMR)
(ADRL)
(ADRM)
(ADRU)
(LCR)
W
R
A/D Data Reg.Lower
A/D Data Reg.Middle
A/D Data Reg.Upper
LCD Control Reg.
LCD Mode Reg.
R
R
W
W
W
(LMR)
Buzzer Mode Reg.
(BMR)
Not used
Not used
Port D0–D3 DCR
Port D4–D7 DCR
Port D8–D9 DCR
W
W
W
(DCD0)
(DCD1)
(DCD2)
Not used
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
W
W
W
W
W
W
W
W
$3BF
$3C0
Stack area
(64 digits)
Not used
$3FF
Notes:
R
W
: Read
: Write
Timer Read Reg.B Lower
Timer Read Reg.B Upper
Timer Write Reg.B Lower
Timer Write Reg.B Upper
(TWBL)
$012
$013
(TRBL)
(TRBU)
R
R
W
R/W: Read/Write
(TWBU)
W
*Two registers are mapped
onto the same address
($012, $013, $016, $017).
Timer Read Reg.C Lower
Timer Read Reg.C Upper
Timer Write Reg.C Lower
Timer Write Reg.C Upper
(TWCL)
(TWCU)
$016
$017
(TRCL)
(TRCU)
R
R
W
W
Figure 2 RAM Memory Map (cont)
27
HD404889/HD404899/HD404878/HD404868 Series
RAM-mapped register area ($000 to $03F):
•
Interrupt control bit area ($000 to $003)
This area consists of bits used for interrupt control. Its configuration is shown in figure 3. Individual
bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD, REM/REMD,
TM/TMD). There are restrictions on access to certain bits. The individual bits and instruction
restrictions are shown in figure 4.
•
Special register area ($004 to $01F, $024 to $03F)
This area comprises mode registers and data registers for external interrupts, the serial interface, timers,
LCD, A/D converter, etc., and I/O pin data control registers. Its configuration is shown in figures 2 and
5. These registers are of three kinds: write-only (W), read-only (R), and read/write (R/W). The
SEM/SEMD and REM/REMD instructions can be used on the LCD control register (LCR: $02C) and
the third bit of buzzer mode register (BMR3: $02E, 3), but RAM bit manipulation instructions cannot
be used on the other registers.
•
Register flag area ($020 to $023)
This area consists of the DTON and WDON flags and interrupt control bits. Its configuration is shown
in figure 3. Individual bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD,
REM/REMD, TM/TMD). There are restrictions on access to certain bits. The individual bits and
instruction restrictions are shown in figure 4.
Memory register (MR) area ($040 to $04F):
In this data area, the 16 memory register digits (MR(0) to MR(15)) can also be accessed by the register-
register instructions LAMR and XMRA. The configuration of this area is shown in figure 6.
LCD data area: $050 to $06F (HD404889/HD404899/HD404878 Series)
$050 to $067 (HD404868 Series)
This 32-digit data area stores data to be displayed on an LCD. Data written in this area is automatically
outputed to segments as display data. "1" data indicates "on" and "0" data "off" (see the section of the LCD
circuit for details).
Data area: $090 to $38F (HD404889/HD404899/HD404878 Series)
$090 to $1BF (HD404868 Series)
For the 464 digits from $090 to $25F, the bank can be switched according to the value of the bank register
(V: $03F) (figure 7). The bank register value must always be set when accessing the area from $090 to
$25F. The data area from $260 to $38F can be addressed without a bank register setting.
Stack area ($3C0 to $3FF):
This is the stack area used to save the contents of the program counter (PC), status flag (ST), and carry flag
(CA) when a subroutine call (CAL or CALL instruction) or interrupt handling is performed. As four digits
are used for one level, the area can be used as a subroutine stack with a maximum of 16 levels. The saved
data and saved status information are shown in figure 6. The program counter is restored by the RTN and
RTNI instructions. The status and carry flags are restored by the RTNI instruction, but are not affected by
the RTN instruction. Any part of the area not used for saving can be used as a data area.
28
HD404889/HD404899/HD404878/HD404868 Series
Bit 2
RAM address
$000
Bit 3
Bit 1
RSP
Bit 0
IE
2
IFWU*
1
IMWU*
(WU0 to WU3
interrupt request flag)
IF1
(WU0 to WU3
interrupt mask)
IM1
(Stack pointer reset) (Interrupt enable flag)
IM0
(INT0 interrupt
mask)
IMTA
(Timer A interrupt
mask)
IMTC
(Timer C interrupt
mask)
IF0
$001
$002
$003
(INT1 interrupt
request flag)
IFTB
(INT
1
interrupt mask)
(INT0 interrupt
request flag)
IFTA
(Timer A interrupt
request flag)
IFTC
IMTB
(Timer B interrupt
request flag)
(Timer B interrupt
mask)
IFAD*
3
IMAD*
3
(A/D converter interrupt
request flag)
(A/D converter
interrupt mask)
(Timer C interrupt
request flag)
3
ADSF*
LSON
DTON
WDON
$020
$021
$022
$023
(DTON flag)
(A/D start flag)
(Low speed on flag)
(Watchdog on flag)
GEF
(Gear enable flag)
ICSF
(Input capture status
flag)
ICEF
(Input capture error
flag)
Not used
IMTD*
IFTD*
4
4
(Timer D interrupt mask) (Timer D interrupt
request flag)
Not used
Not used
Not used
Not used
IMS
(Serial interrupt
mask)
IFS
(Serial interrupt
request flag)
IF : Interrupt Request Flag
IM : Interrupt Mask
IE : Interrupt Enable Flag
SP : Stack Pointer
Notes: 1. WU0 to WU2 interrupt mask in the HD404868 Series
2. WU0 to WU2 interrupt request flag in the HD404868 Series
3. Applies to the HD404889, HD404899, and HD404868 Series.
4. Applies to the HD404889, HD404899, and HD404878 Series.
Figure 3 Interrupt Control Bit and Register Flag Area Configuration
29
HD404889/HD404899/HD404878/HD404868 Series
Bits in the interrupt control bit area and register flag area can be set and reset by the SEM or SEMD
instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not
affected by any other instructions.
The following restrictions apply to individual bits.
SEM/SEMD
REM/REMD
TM/TMD
IE
IM
Allowed
Allowed
Allowed
LSON
IF
ICSF
ICEF
GEF
RSP
WDON
Not executed
Allowed
Allowed
Allowed
Not executed
Allowed
Allowed
Inhibited
Inhibited
Inhibited
Allowed
Allowed
Not executed
Inhibited
*
ADSF
Allowed
Not executed in active mode
Used in subactive mode
Not executed
DTON
Allowed
Allowed
Inhibited
Not Used
Not executed
Notes :
The WDON bit is reset only by stop mode clearance by means of an MCU reset.
Do not use the REM or REMD instruction on the ADSF bit during A/D conversion.
The DTON bit is always in the reset state in active mode.
If the TM or TMD instruction is used on a bit for which its use is prohibited, or on a nonexistent
bit, the status flag value will be undetermined.
* Applies to HD404889, HD404899, and HD404868 Series.
Figure 4 Instruction Restrictions
30
HD404889/HD404899/HD404878/HD404868 Series
HD404889 Series
RAM address
Bit 3
Bit 2
Bit 1
Bit 0
$000
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01F
$020
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
Interrupt control bit area
System clock frequency
division ratio switching
32 kHz frequency division
32 kHz oscillation stop setting
Pull-up MOS control
System clock selection
SSR
MIS
ESR
ratio selection
Not used
Interrupt frame period selection
INT1 edge detection selection
Not used
Not used
Not used
D1/INT1
D0/INT0
R00/WU0
R10/EVNB
PMR0
PMR1
PMR2
PMR3
PMR4
MSR1
MSR2
TMA
TMB1
R03/WU3
R13/TOB
R22/SI/SO
R6/SEG13~16
R02/WU2
R12/BUZZ
R01/WU1
R11/EVND
R20/TOC
R21/SCK
R4/SEG5~8
R5/SEG9~12
R3/SEG1~4
Timer B lock on/off
Serial clock on/off
Not used
Timer D clock on/off
Timer C clock on/off
A/D clock on/off
Not used
TimerA/Timer base
Reload on/off
Not used
Timer A clock source selection
Timer B clock source selection
Timer B output mode setting
EVNB edge detection selection
TMB2
Timer B register (lower)
Timer B register (upper)
Timer C clock source selection
TRBL/TWBL
TRBU/TWBU
TMC1
Reload on/off
Not used
Timer C output mode selection
Not used
TMC2
Timer C register (lower)
Timer C register (upper)
TRCL/TWCL
TRCU/TWCU
TMD1
TMD2
TRDL/TWDL
TRDU/TWDU
Timer D clock source selection
EVND edge detection selection
Reload on/off
Not used
Input capture selection
Timer D register (lower)
Timer D register (upper)
Not used
Register flag area
Serial transfer clock speed selection
R22/SI/SO PMOS control
SO idle H/L setting
SMR1
SMR2
SRL
SRU
AMR
Not used
Not used
Serial data register (lower)
Serial data register (upper)
Analog channel selection
A/D conversion time
Not used
A/D data register (lower)
A/D data register (upper)
Realtime clock mode
ADRL
ADRU
LCR
LMR
BMR
Power supply dividing
resistor switch
On-chip power supply switch
Display on/off
display selection
Input clock selection
Duty selection
Clock output on/off
Buzzer/clock selection
Buzzer/clock source selection
Not used
PortD1DCR
PortD3DCR
PortD7DCR
PortD11DCR
PortD2DCR
PortD6DCR
PortD10DCR
PortD0DCR
PortD4DCR
PortD8DCR
DCD0
DCD1
DCD2
PorD5DCR
PortD9DCR
Not used
PortR03DCR
PortR13DCR
PortR23DCR
PortR33DCR
PortR43DCR
PortR53DCR
PortR63DCR
PortR73DCR
PortR02DCR
PortR12DCR
PortR22DCR
PortR32DCR
PortR42DCR
PortR52DCR
PortR62DCR
PortR72DCR
PortR01DCR
PortR11DCR
PortR21DCR
PortR31DCR
PortR41DCR
PortR51DCR
PortR61DCR
PortR71DCR
PortR81DCR
PortR00DCR
PortR10DCR
PortR20DCR
PortR30DCR
PortR40DCR
PortR50DCR
PortR60DCR
PortR70DCR
PortR80DCR
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
DCR6
DCR7
DCR8
Not used
Not used
Not used
Not used
V
Bank setting
Figure 5 Special Function Register Area
31
HD404889/HD404899/HD404878/HD404868 Series
HD404899 Series
RAM address
Bit 3
Bit 2
Bit 1
Bit 0
$000
$003
$004
SSR
Interrupt control bit area
System clock frequency
division ratio switching
32 kHz frequency division
32 kHz oscillation stop setting
Pull-up MOS control
System clock selection
ratio selection
Not used
Interrupt frame period selection
INT1 edge detection selection
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
MIS
ESR
Not used
Not used
Not used
D1/INT1
D0/INT0
R00/WU0
R10/EVNB
PMR0
PMR1
PMR2
PMR3
PMR4
R03/WU3
R13/TOB
R22/SI/SO
R6/SEG13~16
R02/WU2
R12/BUZZ
R01/WU1
R11/EVND
R20/TOC
R21/SCK
R4/SEG5~8
R5/SEG9~12
R3/SEG1~4
Timer B lock on/off
Serial clock on/off
Not used
Timer D clock on/off
Timer C clock on/off
MSR1
MSR2
A/D clock on/off
Not used
$00F TimerA/Timer base
Timer A clock source selection
Timer B clock source selection
TMA
TMB1
TMB2
Reload on/off
Not used
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01F
$020
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
Timer B output mode setting
EVNB edge detection selection
Timer B register (lower)
Timer B register (upper)
Timer C clock source selection
TRBL/TWBL
TRBU/TWBU
TMC1
Reload on/off
Not used
Timer C output mode selection
Not used
TMC2
Timer C register (lower)
Timer C register (upper)
TRCL/TWCL
TRCU/TWCU
TMD1
TMD2
TRDL/TWDL
TRDU/TWDU
Timer D clock source selection
EVND edge detection selection
Reload on/off
Not used
Input capture selection
Timer D register (lower)
Timer D register (upper)
Not used
Register flag area
Serial transfer clock speed selection
SMR1
SMR2
SRL
Not used
R22/SI/SO PMOS control
SO idle H/L setting
Not used
Serial data register (lower)
Serial data register (upper)
SRU
Analog channel selection
A/D data register (lower)
A/D data register (middle)
A/D data register (upper)
A/D conversion time
Not used
AMR
ADRL
ADRM
ADRU
LCR
Power supply dividing
resistor switch
Realtime clock mode
display selection
On-chip power supply switch
Display on/off
Input clock selection
Clock output on/off
Duty selection
LMR
BMR
Buzzer/clock selection
Buzzer/clock source selection
Not used
PortD1DCR
PortD3DCR
PortD7DCR
PortD11DCR
PortD2DCR
PortD6DCR
PortD10DCR
PortD0DCR
PortD4DCR
PortD8DCR
DCD0
DCD1
DCD2
PorD5DCR
PortD9DCR
Not used
PortR03DCR
PortR13DCR
PortR23DCR
PortR33DCR
PortR43DCR
PortR53DCR
PortR63DCR
PortR73DCR
PortR02DCR
PortR12DCR
PortR22DCR
PortR32DCR
PortR42DCR
PortR52DCR
PortR62DCR
PortR72DCR
PortR01DCR
PortR11DCR
PortR21DCR
PortR31DCR
PortR41DCR
PortR51DCR
PortR61DCR
PortR71DCR
PortR81DCR
PortR00DCR
PortR10DCR
PortR20DCR
PortR30DCR
PortR40DCR
PortR50DCR
PortR60DCR
PortR70DCR
PortR80DCR
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
DCR6
DCR7
DCR8
Not used
Not used
Not used
Not used
V
Bank setting
Figure 5 Special Function Register Area (cont)
32
HD404889/HD404899/HD404878/HD404868 Series
HD404878 Series
RAM address
Bit 3
Bit 2
Bit 1
Bit 0
$000
$003
$004
SSR
Interrupt control bit area
System clock frequency
division ratio switching
32 kHz frequency division
32 kHz oscillation stop setting
Pull-up MOS control
System clock selection
ratio selection
Not used
Interrupt frame period selection
INT1 edge detection selection
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
MIS
ESR
Not used
Not used
Not used
D1/INT1
D0/INT0
R00/WU0
R10/EVNB
PMR0
PMR1
PMR2
PMR3
PMR4
MSR1
MSR2
TMA
R03/WU3
R13/TOB
R22/SI/SO
R6/SEG13~16
R02/WU2
R12/BUZZ
R01/WU1
R11/EVND
R20/TOC
R21/SCK
R5/SEG9~12
Timer D clock on/off
Not used
R4/SEG5~8
R3/SEG1~4
Timer B lock on/off
Serial clock on/off
Not used
Timer C clock on/off
$00F TimerA/Timer base
Timer A clock source selection
Timer B clock source selection
Reload on/off
Not used
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01F
$020
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
TMB1
TMB2
Timer B output mode setting
EVNB edge detection selection
Timer B register (lower)
Timer B register (upper)
Timer C clock source selection
TRBL/TWBL
TRBU/TWBU
TMC1
Reload on/off
Not used
Timer C output mode selection
Not used
TMC2
Timer C register (lower)
Timer C register (upper)
TRCL/TWCL
TRCU/TWCU
TMD1
TMD2
TRDL/TWDL
TRDU/TWDU
Timer D clock source selection
EVND edge detection selection
Reload on/off
Not used
Input capture selection
Timer D register (lower)
Timer D register (upper)
Not used
Register flag area
Serial transfer clock speed selection
R22/SI/SO PMOS control
SO idle H/L setting
SMR1
SMR2
SRL
Not used
Not used
Serial data register (lower)
Serial data register (upper)
SRU
Not used
Power supply dividing
resistor switch
Realtime clock mode
display selection
On-chip power supply switch
Display on/off
LCR
LMR
BMR
Input clock selection
Duty selection
Clock output on/off
Buzzer/clock selection
Buzzer/clock source selection
Not used
PortD3DCR
PortD7DCR
PortD11DCR
PortD2DCR
PortD6DCR
PortD10DCR
PortD1DCR
PorD5DCR
PortD9DCR
PortD0DCR
PortD4DCR
PortD8DCR
DCD0
DCD1
DCD2
Not used
PortR03DCR
PortR13DCR
PortR23DCR
PortR33DCR
PortR43DCR
PortR53DCR
PortR63DCR
PortR73DCR
PortR02DCR
PortR12DCR
PortR22DCR
PortR32DCR
PortR42DCR
PortR52DCR
PortR62DCR
PortR72DCR
PortR01DCR
PortR11DCR
PortR21DCR
PortR31DCR
PortR41DCR
PortR51DCR
PortR61DCR
PortR71DCR
PortR81DCR
PortR00DCR
PortR10DCR
PortR20DCR
PortR30DCR
PortR40DCR
PortR50DCR
PortR60DCR
PortR70DCR
PortR80DCR
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
DCR6
DCR7
DCR8
Not used
Not used
Not used
Not used
Figure 5 Special Function Register Area (cont)
33
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
RAM address
Bit 3
Bit 2
Bit 1
Bit 0
$000
$003
$004
SSR
Interrupt control bit area
System clock frequency
division ratio switching
32 kHz frequency division
32 kHz oscillation stop setting
Pull-up MOS control
System clock selection
ratio selection
Not used
Interrupt frame period selection
INT1 edge detection selection
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
MIS
ESR
Not used
Not used
Not used
D1/INT1
D0/INT0
R00/WU0
R10/EVNB
PMR0
PMR1
PMR2
PMR3
PMR4
Not used
R13/TOB
R22/SI/SO
R6/SEG13~16
R02/WU2
R12/BUZZ
R01/WU1
Not used
R20/TOC
R21/SCK
R4/SEG5~8
R5/SEG9~12
R3/SEG1~4
Timer B lock on/off
Serial clock on/off
Not used
Not used
Timer C clock on/off
MSR1
MSR2
A/D clock on/off
$00F TimerA/Timer base
Timer A clock source selection
Timer B clock source selection
TMA
TMB1
TMB2
Reload on/off
Not used
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01F
$020
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
Timer B output mode selection
EVNB edge detection selection
Timer B register (lower)
Timer B register (upper)
Timer C clock source selection
TRBL/TWBL
TRBU/TWBU
TMC1
TMC2
TRCL/TWCL
TRCU/TWCU
Reload on/off
Not used
Timer C output mode selection
Not used
Timer C register (lower)
Timer C register (upper)
Not used
Not used
Not used
Not used
Not used
Register flag area
Serial transfer clock speed selection
SMR1
SMR2
SRL
Not used
R22/SI/SO PMOS control
SO idle H/L setting
Not used
Serial data register (lower)
Serial data register (upper)
SRU
Analog channel selection
A/D data register (lower)
A/D data register (middle)
A/D data register (upper)
A/D conversion time
Not used
AMR
ADRL
ADRM
ADRU
LCR
Power supply dividing
resistor switch
Realtime clock mode
display selection
On-chip power supply switch
Display on/off
Input clock selection
Clock output on/off
Duty selection
LMR
BMR
Buzzer/clock selection
Buzzer/clock source selection
Not used
PortD3DCR
PortD7DCR
PortD2DCR
PortD6DCR
PortD1DCR
PorD5DCR
PortD9DCR
PortD0DCR
PortD4DCR
PortD8DCR
DCD0
DCD1
DCD2
Not used
Not used
Not used
PortR02DCR
PortR12DCR
PortR22DCR
PortR32DCR
PortR42DCR
PortR52DCR
PortR62DCR
PortR72DCR
PortR01DCR
PortR11DCR
PortR21DCR
PortR31DCR
PortR41DCR
PortR51DCR
PortR61DCR
PortR71DCR
PortR00DCR
PortR10DCR
PortR20DCR
PortR30DCR
PortR40DCR
PortR50DCR
PortR60DCR
PortR70DCR
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
DCR6
DCR7
PortR13DCR
PortR23DCR
PortR33DCR
PortR43DCR
PortR53DCR
PortR63DCR
PortR73DCR
Not used
Not used
Not used
Not used
Figure 5 Special Function Register Area (cont)
34
HD404889/HD404899/HD404878/HD404868 Series
$040
$041
$042
$043
$044
$045
$046
$047
$048
$049
MR (0)
MR (1)
MR (2)
MR (3)
MR (4)
MR (5)
MR (6)
MR (7)
MR (8)
MR (9)
960
$3C0
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Bit 3
ST
Bit 2
Bit 1
Bit 0
Level
Level
Level
Level
Level
Level
Level
Level
Level
9
8
7
6
5
4
3
2
1
1020
1021
1022
1023
PC13
PC12
PC11
$3FC
$3FD
$3FE
$3FF
$04A MR (10)
$04B MR (11)
$04C MR (12)
$04D MR (13)
$04E MR (14)
PC10
CA
PC9
PC6
PC2
PC8
PC5
PC1
PC7
PC4
PC0
PC3
$04F
MR (15)
1,023
$3FF
(a) Memory registers
(b) Stack area
PC13 to PC0 : Program counter
ST
CA
: Status flag
: Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
Bank register (V: $03F)
Bit
3
2
1
0
R/W
0
Read/Write
Initial value on reset
Bit name
—
—
—
—
—
—
Not Used Not Used Not Used
V0
V0
0
1
Bank area selection
Bank 0 is selected
Bank 1 is selected
Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected.
Applies to HD404889 and HD404899 Series.
Figure 7 Bank Register (V)
35
HD404889/HD404899/HD404878/HD404868 Series
Functional Description
Registers and Flags
The MCU has nine registers and two flags for CPU operations. they are shown in figure 8 and described
below.
3
3
0
0
0
0
0
0
0
(A)
Accumulator
B register
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: 1, no R/W
(B)
1
(W)
W register
X register
3
3
3
3
(X)
(Y)
Y register
(SPX)
(SPY)
SPX register
SPY register
Carry flag
0
(CA)
0
(ST)
Status flag
13
0
Program counter
Initial value: $0000,
no R/W
(PC)
9
5
0
Stack pointer
1
1
1
1
(SP)
Initial value: $3FF, no R/W
Figure 8 Registers and Flags
Accumulator (A) and B register (B):
The accumulator and B register are 4-bit registers used to hold the result of an ALU operation, and for data
transfer to or from memory, an I/O area, or another register.
36
HD404889/HD404899/HD404878/HD404868 Series
W register (W), X register (X) and Y register (Y):
The W register is a 2-bit register, and the X and Y registers are 4-bit registers, used for RAM register
indirect addressing. The Y register is also used for D port addressing.
SPX register (SPX) and SPY register (SPY):
The SPX and SPY registers are 4-bit registers used as X register and Y register auxiliary registers,
respectively.
Carry flag (CA):
This flag holds ALU overflow when an arithmetic/logic instruction is executed. It is also affected by the
SEC, REC, ROTL, and ROTR instructions. The contents of the carry flag are saved to the stack when
interrupt handling is performed, and are restored from the stack by the RTNI instruction (but are not
affected by the RTN instruction).
Status flag (ST):
This flag holds ALU overflow when an arithmetic/logic or compare instruction is executed, and the result
of an ALU non-zero or bit test instruction. It is used as the branch condition for the BR, BRL, CAL, and
CALL instructions. The status flag is a latch-type flag, and does not change until the next arithmetic/logic,
compare, or bit test instruction is executed. After a BR, BRL, CAL, or CALL instruction, the status flag is
set to 1 regardless of whether the instruction is executed or skipped. The contents of the status flag are
saved to the stack when interrupt handling is performed, and are restored from the stack by the RTNI
instruction (but are not affected by the RTN instruction).
Program counter (PC):
This is a 14-bit binary counter that holds ROM address information.
Stack pointer (SP):
The stack pointer is a 10-bit register that holds the address of the next save space in the stack area. The
stack pointer is initialized to $3FF by an MCU reset. The stack pointer is decremented by 4 each time data
is saved, and incremented by 4 each time data is restored. The upper 4 bits of the stack pointer are fixed at
1111, so that a maximum of 16 stack levels can be used.
There are two ways in which the stack pointer is initialized to $3FF: by an MCU reset as mentioned above,
or by resetting the RSP bit with the REM or REMD instruction.
Reset
An MCU reset is performed by driving the RESET pin low. At power-on, and when subactive mode,
watch mode, or stop mode is cleared, RESET should be input for at least tRC to provide the oscillation
settling time for the oscillator.In other cases, the MCU is reset by inputting RESET for at least two
instruction cycles.
Table 1 shows the areas initialized by an MCU reset, and their initial values.
37
HD404889/HD404899/HD404878/HD404868 Series
Table 1 (1) Initial Values after MCU Reset
Initial
Item
Abbr.
(PC)
(ST)
(SP)
(IE)
value
Contents
Program counter
Status flag
Stack pointer
$0000
Program executed from ROM start address
Branching by conditional branch instruction enabled
Stack level is 0
1
$3FF
Interrupt
Interrupt enable flag
0
0
1
All interrupts disabled
flags/ mask Interrupt request flag
Interrupt mask
(IF)
No interrupt requests
(IM)
Interrupt requests masked
I/O
Port data register
(PDR)
All bits 1 "1" level output possible
Data control registers
Data control registers
(DCD0 to 2) All bits 0 Output buffer off (high impedance)
(DCR0 to 7, All bits 0
DCR80,
DCR81)
Port mode register 0
Port mode register 1
Port mode register 2
Port mode register 3
Port mode register 4
(PMR0)
(PMR1)
(PMR2)
(PMR3)
(PMR4)
(ESR)
--00
See port mode register 0 section
See port mode register 1 section
See port mode register 2 section
See port mode register 3 section
See port mode register 4 section
See edge detection select register section
0000
0000
0000
0000
--00
Edge detection select
register
Timers
Timer mode register A
Timer mode register B1
Timer mode register B2
Timer mode register C1
Timer mode register C2
Timer mode register D1
Timer mode register D2
Prescaler S
(TMA)
0000
0000
-000
0000
-0--
See timer mode register A section
See timer mode register B1 section
See timer mode register B2 section
See timer mode register C1 section
See timer mode register C2 section
See timer mode register D1 section
See timer mode register D2 section
(TMB1)
(TMB2)
(TMC1)
(TMC2)
(TMD1)
(TMD2)
(PSS)
0000
-000
$000
$00
Prescaler W
(PSW)
Timer/counter A
(TCA)
$00
Timer/counter B
(TCB)
$00
Timer/counter C
(TCC)
$00
Timer/counter D
(TCD)
$00
Timer write register B
Timer write register C
Timer write register D
(TWBU,L)
(TWCU,L)
(TWDU,L)
$X0
$X0
$X0
38
HD404889/HD404899/HD404878/HD404868 Series
Table 1 (1) (cont) Initial Values after MCU Reset
Initial
value
Item
Abbr.
Contents
Serial
Serial mode register 1
Serial mode register 2
Serial data register
Octal counter
(SMR1)
(SMR2)
(SRU,L)
0000
-0X-
$XX
000
See serial mode register 1 section
See serial mode register 2 section
interface
A/D
A/D mode register
(AMR)
0000
$7F
See A/D mode register section
See A/D data register section
converter
A/D data register
(ADRU,L)
(HD404889 Series)
A/D data register
(ADRU,M,L) $1FF
See A/D data register section
(HD404899 Series)
LCD
LCD control register
LCD mode register
Low speed on flag
Watchdog timer on flag
A/D start flag
(LCR)
0000
See LCD control register section
See LCD duty/clock control register section
See low-power mode section
See timer C section
(LMR)
(LSON)
(WDON)
(ADSF)
(DTON)
(ICSF)
(ICEF)
(GEF)
0000
Bit
0
registers
0
0
See A/D converter section
Direct transfer on flag
Input capture status flag
Input capture error flag
Gear enable flag
0
See low-power mode section
See timer D section
0
0
See timer D section
0
See system clock gear function
See low-power mode and input/output sections
See low-power mode and oscillator circuit sections
Others
Miscellaneous register
(MIS)
0-00
0000
System clock select
register
(SSR)
Module standby register 1 (MSR1)
Module standby register 2 (MSR2)
-000
--00
See timer section
See serial interface and A/D converter sections
See Buzzer mode register section
Buzzer mode register
(BMR)
0000
Notes: 1. The state of registers and flags other than those listed above after an MCU reset is shown in
table 1 (2).
2. X: Indicates invalid value, - indicates that the bit does not exist.
39
HD404889/HD404899/HD404878/HD404868 Series
Table 1 (2) Initial Values after MCU Reset
After Stop Mode Clearance by WU0 to
WU3 Input
Item
Abbr.
(CA)
(A)
After Other MCU Reset
Carry flag
Accumulator
B register
W register
Retain value immediately prior to
entering stop mode
Value immediately prior to MCU reset is not
guaranteed. Must be initialized by program.
(B)
(W)
X/SPX register (X/SPX)
Y/SPY register (Y/SPY)
RAM
Interrupts
There are a total of nine interrupt sources, comprising wakeup input (WU0 to WU3), external interrupts
(INT0, INT1), timer/counter (timer A, timer B, timer C, timer D) interrupts, a serial interface interrupt, and
an A/D converter interrupt.
Each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for
storing and controlling interrupt requests. In addition, an interrupt enable flag is provided to control
interrupts as a whole.
Of the interrupt sources, timers B and D share the same vector address, and the A/D converter and serial
interface also share the same vector address. Software must therefore determine which of the interrupt
sources is requesting an interrupt at the start of interrupt handling.
Interrupt control bits and interrupt handling:
The interrupt control bits are mapped onto RAM addresses $000 to $003 and $022 to $023, and can be
accessed by RAM bit manipulation instructions. However, the interrupt request flags (IF) cannot be set by
software. When the MCU is reset, the interrupt enable flag (IE) and interrupt request flags (IF) are
initialized to 0, and the interrupt masks (IM) are initialized to 1.
Figure 9 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector
addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of
interrupt source. When the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an
interrupt is requested. If the interrupt enable flag is set to 1 at this time, interrupt handling is started. The
vector address corresponding to the interrupt source is generated by the priority control circuit.
The interrupt handling sequence is shown in figure 10, and the interrupt handling flowchart in figure 11.
When an interrupt is accepted, execution of the previous instruction is completed in the first cycle. In the
second cycle, the interrupt enable flag (IE) is reset. In the second and third cycles, the contents of the carry
flag, status flag, and program counter are saved on the stack. In the third cycle, a jump is made to the
vector address and instruction execution is resumed from that address.
40
HD404889/HD404899/HD404878/HD404868 Series
In each vector address area, a JMPL instruction should be written that branches to the start address of the
interrupt routine. In the interrupt routine, the interrupt request flag that caused interrupt handling must be
reset by software.
Table 2
Vector Addresses and Interrupt Priorities
Interrupt Source
Priority
Vector Address
$0000
RESET
—
1
2
3
4
5
6
7
WU0 to WU3
$0002
INT0
$0004
INT1
$0006
Timer A
$0008
Timer B, D
$000A
Timer C
$000C
Serial interface, A/D converter
$000E
41
HD404889/HD404899/HD404878/HD404868 Series
$000,0
I/E
Interrupt
request
$000,2
(WU
0
to WU
3
IFWU
interrupt)
$000,3
IMWU
Priority
control circuit
Vector address
$001,0
(INT
0
interrupt)
interrupt)
IF0
$001,1
IM0
$001,2
(INT
1
IF1
$001,3
IM1
$002,0
(Timer A interrupt)
(Timer B interrupt)
(Timer C interrupt)
(A/D interrupt)
IFTA
$002,1
IMTA
$002,2
$022,2
(Timer D interrupt)
IFTB
IFTD
$002,3
$022,3
IMTB
IMTD
$003,0
IFTC
$003,1
IMTC
$003,2
$023,2
(Serial interrupt)
IFAD
IFS
$003,3
$023,3
IMAD
IMS
Figure 9 Block Diagram of Interrupt Control Circuit
42
HD404889/HD404899/HD404878/HD404868 Series
Table 3
Interrupt Processing and Activation Conditions
Interrupt Source
Timer B or
Timer A Timer D
WU0 to
A/D or
Timer C Serial
Interrupt Control Bit
IE
WU3
INT0
INT1
1
1
*
1
0
1
*
1
0
0
1
*
1
0
0
0
1
*
1
0
0
0
0
1
*
1
0
0
0
0
0
1
*
1
0
0
0
0
0
0
1
IFWU·IMWU
IF0·IM0
IF1·IM1
*
IFTA·IMTA
*
*
IFTB·IMTB+IFTD·IMTD
IFTC·IMTC
*
*
*
*
*
*
*
IFAD·IMAD+IFS·IMS
*
*
*
*
*
Note: * Operation is not affected whether the value is 0 or 1.
Instruction cycle
1
2
3
4
5
6
Instruction
execution*
Save to stack
Vector address
generated
Interrupt
acceptance
Save to stack
IE reset
Execution of JMPL instruction
at vector address
Execution of
instruction at
start address of
interrupt routine
Note: The stack is accessed and the IE reset after the instruction is executed, even if it is a 2cycle instruction.
Figure 10 Interrupt Sequence
43
HD404889/HD404899/HD404878/HD404868 Series
Power ON
No
RESET="0"?
Yes
Yes
Interrupt request?
No
IE="1"?
Yes
Execute instruction
Accept interrupt
Reset MCU
IE←"0"
Stack←(PC)
Stack←(CA)
Stack←(ST)
PC←(PC)+1
Yes
WU
0
~WU
3
PC←$0002
interrupt?
No
Yes
INT
0
PC←$0004
interrupt?
No
Yes
INT1
interrupt?
PC←$0006
No
Yes
PC←$0008
Timer A interrupt?
No
Yes
PC←$000A
Timer B, timer D
interrupt?
No
Yes
PC←$000C
Timer C interrupt?
No
PC←$000E
(A/D, serial interrupt)
Figure 11 Interrupt Handling Flowchart
44
HD404889/HD404899/HD404878/HD404868 Series
Interrupt enable flag (IE: $000,0):
The interrupt enable flag controls interrupt enabling/disabling of all interrupt requests as shown in table 4.
The interrupt enable flag is reset by interrupt handling and set by the RTNI instruction.
Table 4
Interrupt Enable Flag (IE: $000,0)
Interrupt Enable Flag(IE)
Interrupt Enabling/Disabling
Interrupts disabled
0
1
Interrupts enabled
Wakeup interrupt request flag (IFWU: $000,2):
The wakeup interrupt request flag (IFWU) is set by the detection of a falling edge in WU0 to WU3 input in
active mode, subactive mode,watch mode, or standby mode. In stop mode, when a falling edge is detected
at the wakeup pin, the MCU waits for the oscillation settling time, then switches to active mode. The
wakeup interrupt request flag (IFWU) is not set in this case.
Wakeup interrupt mask (IMWU: $000,3):
This bit masks an interrupt request by the wakeup interrupt request flag.
Edge detection select register (ESR: $006)
Bit
3
2
1
W
0
W
Read/Write
Initial value on reset
Bit name
—
—
—
—
—
—
0
0
ESR1
ESR0
ESR1
ESR0
INT
1edge detect
0
1
0
1
Not detected
Falling edge detection
Rising edge detection
Both rising and falling edge detection
0
1
Figure 12 Edge Detection Select Register (ESR)
45
HD404889/HD404899/HD404878/HD404868 Series
External interrupt request flags (IF0, IF1: $001):
IF0 is set by a falling edge in the INT0 input, and IF1 is set by a rising edge, falling edge, or both edges in
the INT1 input (table 5).
Interrupt edge selection is performed by means of the edge detection select register (ESR: $006) (figure
12).
Table 5
External Interrupt Request Flags (IF0, IF1: $001)
External Interrupt Request Flags
(IF0, IF1)
Interrupt Request
0
1
No external interrupt request
External interrupt request generated
External interrupt masks (IM0, IM1: $001):
These bits mask interrupt requests by the external interrupt request flags (table 6).
Table 6
External Interrupt Mask (IM: $001)
External Interrupt Masks
(IM0, IM1)
Interrupt Request
0
1
External interrupt request enabled
External interrupt request masked (held pending)
Timer A interrupt request flag (IFTA: $002,0):
The timer A interrupt request flag is set by timer A overflow output (table 7).
Table 7
Timer A Interrupt Request Flag (IFTA: $002,0)
Timer A Interrupt Request
Flag(IFTA)
Interrupt Request
0
1
No timer A interrupt request
Timer A interrupt request generated
Timer A interrupt mask (IMTA: $002,1):
This bit masks an interrupt request by the timer A interrupt request flag (table 8).
Table 8
Timer A Interrupt Mask (IMTA: $002,1)
Timer A Interrupt Mask (IMTA)
Interrupt Request
0
1
Timer A interrupt request enabled
Timer A interrupt request masked (held pending)
46
HD404889/HD404899/HD404878/HD404868 Series
Timer B interrupt request flag (IFTB: $002,2):
The timer B interrupt request flag is set by timer B overflow output (table 9).
Table 9
Timer B Interrupt Request Flag (IFTB: $002,2)
Timer B Interrupt Request Flag
(IFTB)
Interrupt Request
0
1
No timer B interrupt request
Timer B interrupt request generated
Timer B interrupt mask (IMTB: $002,3):
This bit masks an interrupt request by the timer B interrupt request flag (table 10).
Table 10
Timer B Interrupt Mask (IMTB: $002,3)
Timer B Interrupt Mask (IMTB)
Interrupt Request
0
1
Timer B interrupt request enabled
Timer B interrupt request masked (held pending)
Timer C interrupt request flag (IFTC: $003,0):
The timer C interrupt request flag is set by timer C overflow output (table 11).
Table 11
Timer C Interrupt Request Flag (IFTC: $003,0)
Timer C Interrupt Request Flag
(IFTC)
Interrupt Request
0
1
No timer C interrupt request
Timer C interrupt request generated (held pending)
Timer C interrupt mask (IMTC: $003,1):
This bit masks an interrupt request by the timer C interrupt request flag (table 12).
Table 12
Timer C Interrupt Mask (IMTC: $003,1)
Timer C Interrupt Mask (IMTC)
Interrupt Request
0
1
Timer C interrupt request enabled
Timer C interrupt request masked (held pending)
47
HD404889/HD404899/HD404878/HD404868 Series
Timer D interrupt request flag (IFTD: $022,2): (Applies to HD404889, HD404899, and HD404878
Series)
The timer D interrupt request flag is set by timer D overflow output, or by an EVND input edge when used
as an input capture timer (table 13).
Table 13
Timer D Interrupt Request Flag (IFTD: $022,2)
Timer D Interrupt Request Flag
(IFTD)
Interrupt Request
0
1
No timer D interrupt request
Timer D interrupt request generated
Timer D interrupt mask (IMTD: $022,3): (Applies to HD404889, HD404899, and HD404878 Series)
This bit masks an interrupt request by the timer D interrupt request flag (table 14).
Table 14
Timer D Interrupt Mask (IMTD: $022,3)
Timer D Interrupt Mask (IMTD)
Interrupt Request
0
1
Timer D interrupt request enabled
Timer D interrupt request masked (held pending)
Serial interrupt request flag (IFS: $023,2):
The serial interrupt request flag is set on completion of serial data transfer, or if data transfer is halted
midway (table 15).
Table 15
Serial Interrupt Request Flag (IFS: $023,2)
Serial Interrupt Request Flag (IFS) Interrupt Request
0
1
No serial interrupt request
Serial interrupt request generated
Serial interrupt mask (IMS: $023,3):
This bit masks an interrupt request by the serial interrupt request flag (table 16).
Table 16 Serial Interrupt Mask (IMS: $023,3)
Serial Interrupt Mask (IMS)
Interrupt Request
0
1
Serial interrupt request enabled
Serial interrupt request masked (held pending)
48
HD404889/HD404899/HD404878/HD404868 Series
A/D interrupt request flag (IFAD: $003,2): (Applies to HD404889, HD404899, and HD404868 Series)
The A/D interrupt request flag is set on completion of A/D conversion (table 17).
Table 17
A/D Interrupt Request Flag (IFAD: $003,2)
A/D Interrupt Request Flag (IFAD) Interrupt Request
0
1
No A/D interrupt request
A/D interrupt request generated
A/D interrupt mask (IMAD: $003,3): (Applies to HD404889, HD404899, and HD404868 Series)
This bit masks an interrupt request by the A/D interrupt request flag (table 18).
Table 18
A/D Interrupt Mask (IMAD: $003,3)
Serial Interrupt Mask (IMAD)
Interrupt Request
0
1
A/D interrupt request enabled
A/D interrupt request masked (held pending)
49
HD404889/HD404899/HD404878/HD404868 Series
Operating Modes
The five operating modes shown in table 19 can be used for the MCU.
The function of each mode is shown in table 20, and the state transition diagram among each mode in
figure 13.
Table 19
Operating Modes and Clock Status
Mode Name
Stop
Active
Standby
Watch
Subactive*2
Activation method
RESET
cancellation, instruction
interrupt
request, WU0
to WU3 input
in stop mode
STOP/SBY
instruction in
subactive
SBY
STOP
instruction
when
STOP
instruction
when
INT0/timer A
or WU0 to
WU3
TMA3 = 0
TMA3 = 1
interrupt
request in
watch mode
mode (when
direct
transfer is
selected)
Status
System oscillator
OP
OP
OP
Stopped
OP *1
Stopped
OP
Stopped
OP
Subsystem oscillator OP
Cancellation method
RESET
input,
RESET
input,
RESET
input,
RESET
input,
RESET
input,
STOP/SBY interrupt
instruction request
WU0 to WU3 INT0/timer A STOP/SBY
input
or WU0 to
WU3
instruction
interrupt
request
Notes:OP: implies in operation.
1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select
register (SSR: $004)
2. Subactive mode is an optional function; specify it on the fnction option list.
50
HD404889/HD404899/HD404878/HD404868 Series
Table 20
Operation in Low-Power Dissipation Modes
Function
CPU
Stop Mode
Retained
Retained
Stopped
Stopped
Stopped
Stopped
Stopped *1
Stopped
Stopped
Retained
Watch mode
Retained
Retained
OP
Standby Mode
Subactive Mode*3
Retained
Retained
OP
OP
RAM
OP
Timer A
Timer B
Timer C
Timer D *4
Serial interface
A/D *5
OP
Stopped
Stopped
Stopped
Stopped *1
Stopped
OP *2
OP
OP
OP
OP
OP
OP
OP
OP
OP
Stopped
OP
LCD
OP
I/O
Retained
Retained
OP
Notes: OP: implies in operation.
1. Transmission/Reception is activated if a clock is input in external clock mode. However,
interrupts stop.
2. When a 32 kHz clock source is used.
3. Subactive mode is an optional function specified on the function option list.
4. Applies to HD404889, HD404899, and HD404878 Series.
5. Applies to HD404889, HD404899, and HD404868 Series.
51
HD404889/HD404899/HD404878/HD404868 Series
Reset by
RESET pin
input or
Stop mode
(TMA3=0,SSR3=0,LSON=0)
fosc : Stop
watchdog timer
fx : Active
øCPU : Stop
øCLK : Stop
øPER : Stop
WU
to
WU
0
3
Reset
Active mode
Standby mode
STOP
instruction
(TMA3=0,SSR3=1,LSON=0)
osc : Stop
SBY
instruction
f
osc : Active
fosc
: Active
f
fx
fx
fx : Stop
: Active
: Stop
: fcyc
: Active
: fcyc
: fcyc
WU
0
to WU
3
ø
ø
ø
CPU
ø
ø
ø
CPU
øCPU : Stop
øCLK : Stop
øPER : Stop
CLK
PER
CLK
PER
STOP
instruction
interrupt
: fcyc
: fcyc
(TMA3=0)
*4
Subactive mode
(TMA3=1)
SBY
f
fx
ø
ø
ø
osc : Active
instruction
f
fx
ø
ø
ø
osc
: Active
: Active
: fcyc
: fw
f
fx
ø
ø
ø
osc : Stop
: Active
CPU : fSUB
CLK : fw
PER : fSUB
: Active
: Stop
: fw
*1
CPU
CPU
CLK
PER
CLK
PER
interrupt
: fcyc
: fcyc
STOP
instruction
*2
Timer A, WU
0
to WU
3
Timer A, WU
0
~WU
3
STOP
instruction
*3
or INT interrupt
0
or INT0 interrupt
Watch mode
f
osc : Stop
fosc : Stop
fx
fx
: Active
: Active
ø
ø
ø
CPU
ø
ø
ø
CPU : Stop
CLK : fw
PER : Stop
: Stop
: fw
: Stop
f
osc : Main oscillator frequency
fx : Sub-oscillator frequency
(for realtime clock)
CLK
PER
fcyc : fOSC/32 or fOSC/4 (selected by
(TMA3=1,LSON=0)
(TMA3=1,LSON=1)
software)
fw : fx/8
f
ø
ø
ø
SUB : fx/8 or fx/4 (selected by software)
CPU : System clock
CLK : Clock for realtime clock
PER : Peripheral function clock
Transition Condition
DTON
LSON
TMA3
STOP/SBY instruction
STOP/SBY instruction
1
0
0
0
1
0
1
1
1
0
*1
*2
*3
*4
LSON : Low speed on flag
DTON : Direct transfer on flag
TMA3 : Timer mode register A bit3
STOP/SBY instruction Don’t care
STOP/SBY instruction
0
Figure 13 MCU Status Transitions
52
HD404889/HD404899/HD404878/HD404868 Series
Active mode:
In active mode all functions operate. In this mode, the MCU operates on clocks generated by the OSC1 and
OSC2 oscillator circuits.
Standby mode:
In standby mode the oscillators continue to operate but clocks relating to instruction execution halt. As a
result, CPU operation stops, and registers, RAM, and the D port/R port set for output retain their state
immediately prior to entering standby mode. Interrupts, timers, the serial interface, and other peripheral
functions continue to operate.
Power consumption is lower than in active mode due to the halting of the CPU.
The MCU is switched to standby mode by executing the SBY instruction in active mode. Standby mode is
cleared by RESET input or an interrupt request. When standby mode is cleared by RESET input, an MCU
reset is performed. When standby mode is cleared by an interrupt request, the MCU enters active mode
and executes a instruction following the SBY instruction. After executing the instruction, if the interrupt
enable flag is set to 1, interrupt handling is executed; if the interrupt enable flag is cleared to 0, the interrupt
request is held pending and normal instruction execution is continued.
MCU operation flowchart is shown in figure 14.
53
HD404889/HD404899/HD404878/HD404868 Series
Watch mode
Standby mode
Stop mode
No
RESET=0?
No
RESET=0?
Yes
Yes
No
IFWU·IMWU
=1?
Yes
WU0 to WU3
No
=
?
No
IF0·IM0 =1?
Yes
Yes
No
IF1·IM1 =1?
Yes*
No
IFTA · IMTA
= 1?
Yes
IFTB · IMTB+
IFTD·IMTD = 1?
No
System clock
oscillator started
Yes*
System reset
No
IFTC· IMTC
= 1?
Yes*
IFAD·IMAD+
IFS·IMS = 1?
No
Yes*
Next Instruction
execution
System clock
oscillator started
System clock
oscillator started
NOP
IF =1,
IM =0,
IE =1?
No
Yes
Note: Only when clearing from standby mode
Next Instruction
execution
Interrupts
enabled
Figure 14 MCU Operation Flowchart
54
HD404889/HD404899/HD404878/HD404868 Series
Stop mode:
In stop mode, all MCU function stop except that states prior to entry into stop mode are retained. This
mode thus has the lowest power consumption of all operating mode.
In stop mode, the OSC1 and OSC2 oscillators stop. Bit 3 (SSR3) of the system clock select register (SSR:
$004) (figure 24) can be used to select the active (= 0) or stopped (= 1) state for the X1 and X2 oscillators.
The MCU is switched to stop mode by executing a STOP instruction while bit 3 (TMA3) of timer mode
register A (TMA: $00F) is cleared to 0 in active mode. Stop mode is cleared by RESET or WU0 to WU3
input. When stop mode is cleared by RESET, the RESET signal should be input for at least the oscillation
settling time (tRC) (see "AC Characteristics") shown in figure 15. Then, the MCU is initialized and starts
instruction execution from the start (address 0) of the program.
When the MCU detects a falling edge at WU0 to WU3 in stop mode, it automatically waits for the
oscillation settling time, then switches to active mode. After the transition to active mode, the MCU
resumes program execution from the instruction following the STOP instruction.
If stop mode is cleared by wakeup input, RAM data and registers retain their values prior to entering stop
mode.
Stop mode
Oscillator
Internal clock
RESET
tres
STOP instruction executed
(At least oscillation settling time (tRC))
Figure 15 Timing Chart for Clearing Stop Mode by RESET Input
Note: If stop mode is cleared by wakeup input when an external clock is used as the system clock
(OSC1), the subclock should not be stopped in stop mode.
Watch mode:
In watch mode, the realtime clock function (timer A) and LCD function using the X1 and X2 oscillators
operate, but other functions stop. This mode thus has the second lowest power consumption after stop
mode, and is useful for performing realtime clock display only.
In watch mode, the OSC1 and OSC2 oscillators stop but the X1 and X2 oscillators continue to operate.
The MCU is switched to watch mode by executing a STOP instruction while TMA3 = 1 in active mode, or
by executing a STOP/SBY instruction in subactive mode.
55
HD404889/HD404899/HD404878/HD404868 Series
Watch mode is cleared by RESET input or an INT0,timer A or WU0 to WU3 interrupt request. For RESET
input, refer to the section on stop mode. When watch mode is cleared by an INT0,timer A or WU0 to WU3
interrupt request, the mode transition depends on the value of the LSON bit: the MCU enters active mode if
LSON = 0, and enters subactive mode if LSON = 1. In the case of a transition to active mode, interrupt
request generation is delayed to secure the oscillation settling time: the delay is the tRC set time for the
timer A interrupt, and, for the INT0 interrupt or WU0 to WU3 interrupt, Tx (T + tRC < Tx < 2T + tRC) if bit 1
and 0 (MIS1, MIS0) of the miscellaneous register are set to 00, or Tx (tRC < Tx < T + tRC) if MIS1 and
MIS0 are set to 01 or 10 (figures 16 and 17). Other operations when the transition is made are the same as
when watch mode is cleared (figure 14).
Subactive mode:
In subactive mode, the OSC1 and OSC2 oscillator circuits stop and the MCU operates on clocks generated
by the X1 and X2 oscillator circuits. In this mode, functions other than the A/D converter operate, but
since the operating clocks are slow, power consumption is the lowest after watch mode.
A CPU instruction processing speed of 244 µs or 122 µs can be selected according to whether bit 2 (SSR2)
of the system clock select register (SSR: $004) is set to 1 or cleared to 0. The value of the SSR2 bit should
be changed (0→1 or 1→0) only in active mode. If the value is changed in subactive mode, the MCU may
operate incorrectly.
Subactive mode is cleared by executing a STOP/SBY instruction. A transition is then made to either watch
mode or active mode according to the value of the low speed on flag (LSON: $020,0) and the direct
transfer on flag (DTON: $020,3).
Subactive mode is a function option, and should be specified in the function option list.
Interrupt frame:
In watch mode and subactive mode, øCLK is supplied to the timer A, WU0 to WU3, and INT0 acceptance
circuits. Prescaler W and timer A operate as time bases, and generate interrupt frame timing. Either of two
values can be selected for the interrupt frame period, T, by means of the miscellaneous register (MIS: $005)
(figure 17).
In watch mode and subactive mode, the timing for generation of timer A,INT0 and WU0 to WU3 interrupts
is synchronized with the interrupt frame. Except for the case of an active mode transition, the interrupt
strobe timing is used for interrupt request generation. Timer A generates overflow and interrupt requests at
the interrupt strobe timing.
56
HD404889/HD404899/HD404878/HD404868 Series
Oscillation
stabilization
period
Active mode
Watch mode
Active mode
Interrupt
strobe
INT
0
Interrupt
request generation
T
T
t
RC
Only in case of
transition to active
mode
T
X
T: Interrupt frame period
RC : Oscillation stabilization period
t
Note: If the time from the fall of the INT0 or WU0 to WU3 signal until the interrupt is accepted and
active mode is entered and is designated T , then T will be in the following range :
T+tRC≤T ≤2T+tRC (MIS1, MIS0=00)
≤T+tRC (MIS1, MIS0=01 or 10)
X
X
X
tRC≤T
X
Figure 16 Interrupt Frame
Miscellaneous Register (MIS: $005)
Bit
3
W
2
1
W
0
W
Read/Write
Reset
0
0
0
Bit name
MIS3
MIS1
MIS0
Buffer control
See section 3,
Input/Output,
and Figure 33
Interrupt Frame Oscillation Settling
Oscillator Circuit
Condition
MIS1 MIS0
period T(ms)*1
Time tRC(ms)*1
0.24414
3.90625
3.90625
0.12207(0.24414)*2
7.8125
External clock input
Ceramic resonator
Crystal resonator
0
0
1
1
31.25
0
Not used
1
Notes: 1. T and tRC values are for use of a 32.768 kHz crystal oscillator at the X1-X2 pins.
2. This value applies only in case of direct transition operation.
Figure 17 Miscellaneous Register (MIS)
57
HD404889/HD404899/HD404878/HD404868 Series
Direct transition from subactive to active mode:
A direct transition can be made from subactive mode to active mode by controlling the direct transfer on
flag (DTON: $020,3) and low speed on flag (LSON: $020,0). The procedure is shown below.
(a) Set LSON = 0 and DTON = 1 in subactive mode.
(b) Execute a STOP or SBY instruction.
(c) After the lapse of the MCU internal processing time and the oscillation settling time, the MCU
automatically switches from subactive mode to active mode (figure 18).
Notes: 1. The DTON flag ($020,3) can be set in only subactive mode. It is always in the reset state in
active mode.
2. The condition for transition time TD from the subactive mode to active mode is as follows:
tRC < TD < T + tRC.
STOP/SBY
instruction execution
MCU internal
Oscillation
processing time
stabilization time
Subactive mode
Active mode
(Set LSON =0, DTON =1)
Interrupt strobe
Direct transition
completion timing
T
t
RC
T: Interrupt frame period
TD
t
RC: Oscillation settling time
TD: Direct transition time
Figure 18 Direct Transition Timing
MCU operation sequence:
The MCU operates in accordance with the flowchart shown in figure 19. RESET input is asynchronous
input, and the MCU immediately enters the reset state upon RESET input, regardless of its current state.
In the low-power mode operation sequence, if a STOP/SBY instruction is executed while the IE flag is
cleared and the interrupt flag is set, releasing the relevant interrupt mask, the STOP/SBY instruction is
canceled (regarded as NOP) and the next instruction is executed. Therefore, when executing a STOP/SBY
instruction, all interrupt flags must be cleared, or interrupts masked, beforehand.
58
HD404889/HD404899/HD404878/HD404868 Series
STOP/SBY
instruction
No
IF=1
IM=0
Yes
Stop Mode
Standby/watch mode
No
IE=0
Yes
Interrupt handling
routine
IF=1
WU
=
0~WU
3
No
No
IM=0
Yes
Yes
Clearing Standby
watch mode
Clearing Stop
mode
Hardware NOP
Execution
Hardware NOP
Execution
NOP
PC←(PC)+1
PC←(PC)+1
PC←(PC)+2
Instruction
Execution
Instruction
Execution
MCU
Operation Cycle
Note: See figure 14, MCU Operation Flowchart, for IF and IM operation.
Figure 19 MCU Operating Sequence (Low-Power Mode Operation)
59
HD404889/HD404899/HD404878/HD404868 Series
Usage notes:
In watch mode and subactive mode, an interrupt will not be detected correctly if the INT0 or WU0 to WU3
high or low-level period is shorter than the interrupt frame period.
The MCU’s edge sensing method is shown in figure 20. The MCU samples the INT0 and WU0 to WU3
signals at regular intervals, and if consecutive sampled values change from high to low, it determines that a
falling edge has been generated.
Interrupt detection errors occur since this sampling is performed at the interrupt frame period. If the high-
level period of the INT0 or WU0 to WU3 signal is within an interrupt frame, as shown in figure 21 (a), the
signal will be low at point A and point B, with the result that the falling edge will not be recognized.
Similarly, If the low-level period of the INT0 or WU0 to WU3 signal is within an interrupt frame, as shown
in figure 21 (b), the signal will be high at point A and point B, with the result that the falling edge will not
be recognized.
In watch mode and subactive mode, therefore, ensure that the high-level and low-level periods of the INT0
and WU0 to WU3 signals is at least as long as the interrupt frame period.
INT0
or
WU0 to WU3
Sampling
High
Low
Low
Figure 20 Edge Sensing Method
(a) High-level mode
(b) Low-level mode
INT
0
or
to WU
INT
0
or
to WU
WU
0
3
WU
0
3
Interrupt frame
Interrupt frame
Point A: Low
Point B: Low
Point A: High
Point B: High
Figure 21 Sampling Examples
60
HD404889/HD404899/HD404878/HD404868 Series
Internal Oscillator Circuit
Figure 22 shows the clock pulse generator circuit. As shown in table 21, a ceramic oscillator or crystal
oscillator can be connected to OSC1 and OSC2, and a 32.768 kHz crystal oscillator can be connected to X1
and X2. External clock operation is possible for the system oscillator. Set bit 1 (SSR1) of the system clock
select register (SSR: $004) according to the frequency of the oscillator connected to OSC1 and OSC2
(figure 24).
Note: If the setting of bit 1 in the system clock select register does not match the frequency of the system
oscillator, the subsystem using 32.768 kHz oscillation will not operate correctly.
LSON
OSC
2
CPU
•ROM
øCPU
fOSC
f
t
cyc
cyc
System
oscillator
1/4 or 1/32
division
circuit*
Timing
generation
circuit
•RAM
• Registers, flags
•I/O
System
clock
OSC
1
selection
circuit
Peripheral
functions
Interrupts
øPER
X2
Sub
system
clock
f
x
f
SUB
1/8 or 1/4
division
circuit*
Timing
generator
circuit
TMA3 bit
t
subcyc
oscillator
X1
Time
base
clock
selection
circuit
øCLK
Timer A
interrupts
1/8
division
circuit
Timing
generation
circuit
f
W
t
wcyc
Notes: The division ratio can be selected by setting bit 0 or bit 2 in the system clock select register
(SSR:$004).
Figure 22 Clock Pulse Generator Circuit
61
HD404889/HD404899/HD404878/HD404868 Series
System Clock Gear Function
The MCU has a built-in system clock gear function that allows the system clock divided by 4 or by 32 to be
selected by software for the instruction execution time. Efficient power consumption can be achieved by
operating at the divided-by-4 rate when high-speed processing is needed, and at the divided-by-32 rate at
the other times. Figure 23 shows the system clock conversion method.
System clock conversion from division-by-4 to division-by-32 is performed as follows. First, make the
division-by-32 setting (SSR0 write), then set the gear enable flag (GEF: $021,3). This flag is used to
distinguish between gear conversion and a transition to standby mode. Next, execute an SBY instruction.
When the gear enable flag is not set, standby mode is entered; when this flag is set, gear conversion mode
is entered. In this case a transition is made to standby mode for the duration of the gear conversion, but
after the synchronization time has elapsed, a transition is made automatically to active mode. As soon as
the transition is made to active mode, the gear enable flag is reset.
The same procedure is used for conversion from division-by-32 to division-by-4.
Clear all interrupts, then disable interrupts, before carrying out gear conversion. Incorrect operation may
result if an interrupt is generated during gear conversion.
62
HD404889/HD404899/HD404878/HD404868 Series
Division-by-32 setting (SSR0 = 1)
Set gear enable flag
Execute SBY instruction
Synchronization time
Execute next instruction
Division-by-4 setting (SSR0 = 0)
Set gear enable flag
Execute SBY instruction
Synchronization time
Execute next instruction
Figure 23 System Clock Division Ratio Conversion Flowchart
63
HD404889/HD404899/HD404878/HD404868 Series
System clock select register (SSR: $004)
Bit
3
W
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
0
0
0
0
*
SSR3
SSR2
SSR1
SSR0
System clock division ratio switch
Division-by-4 (fcyc - fOSC/4)
Division-by-32 (fcyc - fOSC/32)
0
1
System clock division ratio switch
0
1
f
osc=0.4–1.0MHz
osc=1.6–4.5MHz
f
Subsystem clock division ratio switch
0
1
f
f
SUB=fx/8
SUB=fx/4
Subsystem clock stop setting
0
1
Subsystem clock operates in stop mode
Subsystem clock stops in stop mode
Note: * If the subsystem clock is not used, this bit must be set to 1 following power-on and reset.
If it is set to 0 (the initial value), malfunctioning may occur in the stop mode.
Figure 24 System Clock Select Register
64
HD404889/HD404899/HD404878/HD404868 Series
Table 21
Oscillator Circuit Examples
Circuit Structure
Circuit Constants
External clock
operation
External
oscillator
OSC
1
Open
OSC
2
C
1
Ceramic oscillator
(OSC1, OSC2)
Ceramic oscillator: CSA4.00MG (Murata)
OSC
1
2
Ceramic
oscillator
Rf=1MΩ±20%
C1=C2=30pF±20%
Rf
OSC
C2
GND
C1
Crystal oscillator
(OSC1, OSC2)
Rf=1MΩ±20%
C1=C2=10–22pF±20%
OSC1
OSC2
Crystal
oscillator
Rf
Crystal: Equivalent circuit at left
C0=7pFmax.
RS=100Ωmax.
C2
GND
L
CS RS
OSC1
OSC2
C0
C1
Crystal oscillator
(X1, X2)
Crystal: 32.768 kHz: MX38T (Nihon Denpa
Kogyo)
C1=C2=20pF±20%
RS=14kΩ
C0=1.5pF
X1
X2
Crystal
oscillator
C2
GND
L
CS RS
X1
X2
C0
Notes: 1. With a crystal or ceramic oscillator, circuit constants will differ depending on the resonator, stray
capacitance in the interconnecting circuit, and other factors. Suitable constants should be
determined in consultation with the resonator manufacturer.
2. Make the connections between the OSC1 and OSC2 pins (X1 and X2 pins) and external
components as short as possible, and ensure that no other lines cross these lines (see layout
example in figure 25).
3. When 32.768 kHz crystal oscillation is not used, fix the X1 pin at VCC and leave the X2 pin open.
65
HD404889/HD404899/HD404878/HD404868 Series
RESET
X1
X2
GND
OSC2
OSC1
TEST
GND
Figure 25 Typical Layouts of Crystal and Ceramic Oscillator
66
HD404889/HD404899/HD404878/HD404868 Series
Input/Output
The MCU has 46 input/output pins (D0 to D11, R0 to R7, R80, and R81) in the HD404889, HD404899, and
HD404878 Series, or 41 input/output pins (D0 to D9, R00, R01, R02, and R1 to R7) in the HD404868 Series.
The features of these pins are described below.
•
•
•
The four pins D0 to D3 are source large-current (10 mA max.) I/O pins.
The eight pins D4 to D11 are sink large-current (15 mA max.) I/O pins.
I/O pins comprise pins (D0, D1, R0, R1, R20 to R22, R3 to R7, R80, and R81) that also have a peripheral
function (timer, serial interface, etc.). With these pins, the peripheral function setting has priority over
the D port or R port pin setting. When a peripheral function setting has been made for a pin, the pin
function and input/output mode will be switched automatically in accordance with that setting.
•
•
•
•
Selection of input or output for I/O pins, or selection of the port or peripheral function for pins
multiplexed as peripheral function pins, is performed by the program.
All output of the peripheral function pins are CMOS outputs. The SO pin and R22 port pin can be
designated as NMOS open-drain output by the program.
A reset clears peripheral function selection. And since the data control registers (DCD, DCR) are also
reset, input/output pins go to the high-impedance state.
Each I/O pin has a built-in pull-up MOS that can be turned on and off individually by the program.
Figure 26 shows the I/O buffer configuration, and table 22 shows I/O pin circuit configuration control by
the program.
Table 23 shows the circuit configuration of each I/O pin.
VCC
Pull-up control signal
MIS3
pull-up
MOS
VCC
Buffer control signal
PMOS
DCD, DCR
Output data
PDR
NMOS
Input data
Input control signal
Figure 26 I/O Pin Circuit Configuration
67
HD404889/HD404899/HD404878/HD404868 Series
Table 22
Programmable I/O Circuits
MIS3 (bit 3 of MIS)
DCD,DCR
PDR
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CMOS buffer
PMOS
NMOS
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
ON
—
ON
—
—
ON
—
pull-up MOS
—
ON
ON
Note: — : OFF
Table 23 Circuit Configurations of I/O Pins
Type
Circuit Configuration
Pins
I/O pins
Pull-up control signal
Buffer control signal
D0-D11
R00-R03
R10-R13
VCC
VCC
MIS3
DCD, DCR
R20, R21, R23
R30-R33
R40-R43
R50-R53
R60-R63
R70-R73
R80-R81
Output data
PDR
Input data
Input control signal
Pull-up control signal
Buffer control signal
R22
VCC
VCC
MIS3
DCR
SMR22
PDR
Output data
Input data
Input control signal
Perip- I/O pins
heral
function
pins
Pull-up control signal
SCK
VCC
VCC
MIS3
PDR
I/O control signal
Output data
SCK
Input data
SCK
Note: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state
and peripheral function selections are cleared.
68
HD404889/HD404899/HD404878/HD404868 Series
Table 23
Circuit Configurations of I/O Pins (cont)
Type
Circuit Configuration
Pins
Perip- Output
SO
Pull-up control signal
VCC
VCC
MIS3
PDR
SMR22
heral
pins
PMOS control signal
Output data
function
pins
SO
Pull-up control signal
Output data
TOB, TOC,
BUZZ
VCC
VCC
MIS3
PDR
TOB, TOC, BUZZ
Input
pins
RESET
Input data
RESET
VCC
WU0-WU3,
INT0, INT1,
EVNB,
MIS3
PDR
EVND, SI
WU0–WU3 etc.
VCC
AN0-AN5*
MIS3
PDR
A/D input
Input control signal
Notes: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state
and peripheral function selections are cleared.
* Applies to HD404889, HD404899, and HD404868 Series.
69
HD404889/HD404899/HD404878/HD404868 Series
D Port
The D port consists of 12 I/O pins (10 I/O pins in the HD404868 Series) that are addressed bit-by-bit.
Ports D0 to D3 are source large-current I/O pins, and ports D4 to D11 (ports D4 to D9 in the HD404868
Series) are sink large-current I/O pins.
The D port can be set and reset by the SED and RED instructions or the SEDD and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. The entire D port can be tested by the TD
or TDD instruction.
The D port output buffer is turned on and off by the D port data control registers (DCD0 to DCD2: $030 to
$032). The DCD registers are mapped onto memory addresses (figure 27).
Ports D0 and D1 are multiplexed as interrupt input pins INT0 and INT1, respectively. Setting as interrupt
pins is performed by bits 0 and 1 (PMR00, PMR01) of port mode register 0 (PMR0: $008) (figure 28).
70
HD404889/HD404899/HD404878/HD404868 Series
Data control registers (DCD0–2 : $030–$032)
(DCR0–8 : $034–$03C)
Register Name
Bit
3
W
0
2
W
0
1
W
0
0
W
0
Read/Write
Reset
DCD0–DCD2
Bit name
Read/Write
Reset
DCD03–DCD23 DCD02–DCD22 DCD01–DCD21 DCD00–DCD20
W
0
W
0
W
0
W
0
DCR0–DCR8
Bit name
DCR03–DCR73 DCR02–DCR72 DCR01–DCR81 DCR00–DCR80
All bits
CMOS buffer control
CMOS buffer off (high impedance)
CMOS buffer active
0
1
Correspondence between each bit of DCD and DCR and ports
Register Name
DCD0
Bit 3
Bit 2
Bit 1
Bit 0
D
3
7
D
2
6
D1
D5
D9
D0
D4
D8
DCD1
D
D
DCD2
D11*
D
10
*
2
2
2
2
2
2
2
2
DCR0
R0
R1
R2
R3
R4
R5
R6
R7
3
*
R0
R1
R2
R3
R4
R5
R6
R7
R0
R1
R2
R3
R4
R5
R6
R7
1
1
1
1
1
1
1
1
R0
R1
R2
R3
R4
R5
R6
R7
0
0
0
0
0
0
0
0
DCR1
3
DCR2
3
3
3
3
3
3
DCR3
DCR4
DCR5
DCR6
DCR7
DCR8
R81
*
R8 *
0
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 27 Data Control Registers (DCD, DCR)
71
HD404889/HD404899/HD404878/HD404868 Series
R Port
The R port consists of 34 I/O pins (31 I/O pins in the HD404868 Series) that are addressed in 4-bit units.
Input can be performed by means of the LAR and LBR instructions, and output by means of the LRA and
LRB instructions. Output data is stored in the port data register (PDR) for each pin.
The R port output buffer is turned on and off by the R port data control registers (DCR0 to DCR8: $034 to
$03C). The DCR registers are mapped onto memory addresses (figure 27).
Ports R00 to R03 are multiplexed as wakeup input pins WU0 to WU3, respectively. Setting of these pins as
peripheral function pins is performed by port mode register 1 (PMR1: $009) (figure 29).
Ports R10 and R11 are multiplexed as peripheral function pins EVNB and EVND, respectively. Setting of
these pins as peripheral function pins is performed by bits 0 and 1 (PMR20, PMR21) of port mode register
2 (PMR2: $00A) (figure 30).
Ports R12 to R13 and R20 are multiplexed as peripheral function pins BUZZ, TOB, and TOC, respectively.
Setting of these pins as peripheral function pins is performed by bits 2 and 3 (PMR22, PMR23) of port
mode register 2 (PMR2: $00A) and bit 0 (PMR30) of port mode register 3 (PMR3: $00B)(figures 30 and
31).
Ports R21 and R22 are multiplexed as peripheral function pins SCK and SI/SO, respectively. Setting of
these pins as peripheral function pins is performed by bits 1 to 3 (PMR31 to PMR33) of port mode register
3 (PMR3: $00B) (figure 31).
Ports R3 to R6 are multiplexed as peripheral function pins SEG1 to SEG16, respectively. Setting of these
pins as segment pins is performed every 4 pins in 4-bit units by port mode register 4 (PMR4: $00C) (figure
32).
Ports R70 to R73 and R80 to R8 also function as peripheral function pins AN0 to AN5 (HD404889,
1
HD404899, and HD404868 series only). Peripheral function pin setting of these pins is performed using
bits 1 to 3 (AMR1 to AMR3) of the A/D mode register (AMR :$028). (See Figure 74 in A/D Converter.)
72
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 0 (PMR0: $008)
Bit
3
2
1
W
0
W
Read/Write
Initial value on reset
Bit name
0
0
Not used
Not used
PMR01
PMR00
PMR00
D0/INT0 pin mode selection
0
1
D
0
INT
0
PMR01
D1/INT
1
pin mode selection
0
1
D
1
INT
1
Figure 28 Port Mode Register 0 (PMR0: $008)
73
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 1 (PMR1: $009)
Bit
3
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
W
0
0
0
0
PMR13*
PMR12
PMR11
PMR10
PMR10 R00/WU0 pin mode selection
0
1
R00
WU0
PMR11
R0
1
/WU pin mode selection
1
0
1
R01
WU1
PMR12
R02/WU
2
pin mode selection
0
1
R02
WU2
PMR13
R03/WU
3
pin mode selection
0
1
R03
WU3
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 29 Port Mode Register 1 (PMR1: $009)
74
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 2 (PMR2: $00A)
Bit
3
W
2
W
1
0
W
Read/Write
Initial value on reset
Bit name
W
0
0
0
0
PMR23
PMR22
PMR21*
PMR20
PMR20 R10/EVNB pin mode selection
0
1
R10
EVNB
PMR21 R11/EVND pin mode selection
0
1
R11
EVND
PMR22 R12/BUZZ pin mode selection
0
1
R12
BUZZ
PMR23
R13/TOB pin mode selection
0
1
R13
TOB
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 30 Port Mode Register 2 (PMR2: $00A)
75
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 3 (PMR3: $00B)
Bit
3
W
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
0
0
0
0
PMR33
PMR32
PMR31
PMR30
PMR30 R20/TOC pin mode selection
0
1
R20
TOC
PMR31
R21/SCK pin mode selection
0
1
R21
SCK
PMR33
PMR32 R22/SI/SO pin mode selection
0
1
R22
0
1
SI
SO
: Don't care
Figure 31 Port Mode Register 3 (PMR3: $00B)
76
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 4 (PMR4: $00C)
Bit
3
W
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
0
0
0
0
PMR43
PMR42
PMR41
PMR40
R3/SEG1 to SEG4 pin mode selection
PMR40
R3
0
SEG1–4
1*
PMR41 R4/SEG5 to SEG8 pin mode selection
0
R4
1*
SEG5–8
PMR42 R5/SEG9 to SEG12 pin mode selection
0
R5
1*
SEG9–12
PMR43 R6/SEG13 to SEG16 pin mode selection
0
R6
1*
SEG13–16
* : When use as a segment output pin, write its port data register (PDR) to '0'
Figure 32 Port Mode Register 4 (PMR4: $00C)
Pull-Up MOS Control
Program-controllable pull-ups MOS are incorporated in all I/O pins.
On/off control of all pull-ups MOS is performed by bit 3 (MIS3) of the miscellaneous register (MIS: $005)
and the port data register (PDR) for each pin, enabling the pull-up MOS to be turned on or off
independently for each pin (table 22, figure 33).
Except for analog input multiplexed pins, the pull-up MOS on/off setting can be made independent of the
setting as an on-chip supporting module pin.
77
HD404889/HD404899/HD404878/HD404868 Series
Miscellaneous register (MIS: $005)
Bit
3
W
2
1
W
0
W
Read/Write
Initial value on reset
Bit name
—
—
—
0
0
0
MIS3
MIS1
MIS0
tRC selection
(See figure 17 in the
Operating Modes section)
pull-up MOS control
All pull-ups MOS off
pull-up MOS active
MIS3
0
1
Figure 33 Miscellaneous Register (MIS:$005)
Handling of I/O Pins Not Used by User System
If I/O pins that are not used by the user system are left floating, they may generate noise that can result in
chip malfunctions. Therefore, the pin potential must be fixed.
In this case, pull the pins up to VCC with the built-in pull-up MOS or with an external resistor of
approximately 100 kΩ.
78
HD404889/HD404899/HD404878/HD404868 Series
Prescalers
The MCU has the following two prescalers, S and W.
The operating conditions for each prescaler are shown in table 24, and the output supply destinations in
figure 34.
Timer A to D input clocks other than external events, serial transfer clocks other than external clocks, and
the LCD circuit operating clock are selected from the prescaler outputs in accordance with the respective
mode register.
Prescaler Operation
Prescaler S (PSS):
Prescaler S is an 11-bit counter that has the system clock as input. When the MCU is reset, prescaler S is
reset to $000, then divides the system clock. Prescaler S operation is stopped by a reset by the MCU, and
in stop mode and watch mode. It does not stop in any other modes.
Prescaler W (PSW):
Prescaler W is a counter that has a clock divided from the X1 input (32 kHz crystal oscillation) as input.
When the MCU is reset, prescaler W is reset to $00, then divides the input clock. Prescaler W can also be
reset by software.
Table 24
Prescaler Operating Conditions
Prescaler
Input Clock
Reset Conditions
Stop Conditions
Prescaler S
System clock in active and MCU reset, Stop mode
standby modes, Subsystem clearance
clock in subactive mode
MCU reset, Stop mode,
Watch mode
Prescaler W
Clock obtained by division- MCU reset, Software*
by-8 of 32.768 kHz
MCU reset, Stop mode
oscillation by subsystem
clock oscillator
Note: If bits TMA3 to TMA1 in timer mode register A (TMA) are all set to 1, PSW is cleared to $00.
79
HD404889/HD404899/HD404878/HD404868 Series
Subsystem
Prescaler W
clock
LCD controller
driver circuit
Timer A
Timer B
Timer C
Timer D
Serial
interface
System
clock
Clock
selector
Prescaler S
Figure 34 Prescaler Output Destinations
80
HD404889/HD404899/HD404878/HD404868 Series
Timers
The MCU incorporates four timers, A to D, in the HD404889, HD404899, and HD404878 Series, or three
timers, A to C, in the HD404868 Series.
•
•
•
•
Timer A: Free-running timer
Timer B: Multifunctional timer
Timer C: Multifunctional timer
Timer D: Multifunctional timer
Timer A is an 8-bit free-running timer. Timers B, C, and D are 8-bit multifunctional timers; Each one of
their have the functions shown in table 25 and their operating mode can be set by the program.
Table 25
Timer Functions
Functios
Timer A
Timer B
Available
—
Timer C
Available
—
Timer D
Available
—
Clock source
Prescaler S
Prescaler W
External event
Available
Available
—
Available
Available
—
—
Available
Available
—
Timer functions Free-running
Time-base
Available
Available
—
Available
Event counter
—
—
—
—
—
—
Available
Available
—
—
Available
Available
—
Reload
Available
Available
—
Watchdog
Input Capture
—
Available
—
Timer outputs Toggle
PWM
Available
Available
Available
Available
—
Note: — implies not available
Timer A
Timer A Functions
Timer A has the following functions.
•
•
Free-running timer
Realtime clock time base
The block diagram of timer A is shown in figure 35.
81
HD404889/HD404899/HD404878/HD404868 Series
Timer A interrupt
request flag
(IFTA)
fW
32.768-kHz
oscillator
Prescaler W
(PSW)
1/4
1/2
tWcyc
2 fW
1/2 tWcyc
Selector
Timer
Clock
counter A
(TCA)
Overflow
Selector
øPER
System
clock
3
Prescaler S (PSS)
Timer mode
register A
(TMA)
Data bus
Clock line
Signal line
Figure 35 Timer A Block Diagram
Timer A Operation
Free-running timer operation:
The timer A input clock is selected by timer mode register A (TMA: $00F).
Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input
clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value
becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $002,0). Timer
A continues counting up after the count value returns to $00, so that an interrupt is generated regularly
every 256 input clock cycles.
Realtime clock time base operation:
Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1.
As the prescaler W output is input to timer/counter A, interrupts are generated with accurate timing using
the 32.768 kHz crystal oscillator as the basic clock.
When timer A is used as the realtime clock time base, prescaler W and timer/counter A can be reset to $00
by the program.
82
HD404889/HD404899/HD404878/HD404868 Series
Timer A Register
Timer A operation is set by means of the following register.
Timer mode register A (TMA: $00F):
Timer mode register A (TMA: $00F) is a 4-bit write-only register. Timer A operation and input clock
selection are set as shown in figure 36.
83
HD404889/HD404899/HD404878/HD404868 Series
Timer mode register A (TMA: $00F)
Bit
3
W
0
2
W
0
1
W
0
0
W
0
Read/Write
Initial value on reset
Bit name
TMA3 TMA2 TMA1 TMA0
TMA3 TMA2 TMA1 TMA0 Source prescaler Input clock period Operating mode
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
2,048 tcyc
1,024 tcyc
512 tcyc
128 tcyc
32 tcyc
PSS
PSS
PSS
PSS
PSS
PSS
PSS
PSS
PSW
PSW
PSW
PSW
PSW
0
1
0
1
Timer A
mode
0
0
1
0
8 tcyc
4 tcyc
2 tcyc
32 twcyc
16 twcyc
8 twcyc
0
1
1
Time base
mode
1
2 twcyc
1/2 twcyc
0
1
Not Used
PSW, TCA reset
* : Don't care
Notes: 1. twcyc = 244.14 µs (using 32.768 kHz crystal oscillator)
2. Timer/counter overflow output period (s) = input clock period (s) × 256.
3. If PSW and TCA reset is selected during LCD, the LCD enters the halt state
(power switch off). Therefore, to provide continuous LCD the PSW and TCA
reset interval must be minimized by the program.
4. The division ratio must not be changed while time base mode is being used, as this
will result in an error in the overflow period.
Figure 36 Timer Mode Register A (TMA)
84
HD404889/HD404899/HD404878/HD404868 Series
Timer B
Timer B Functions: Timer B has the following functions.
•
•
•
Free-running/reload timer
External event counter
Timer output operation (toggle output, PWM output)
The block diagram of timer B is shown in figure 37.
Timer B ineterrupt
request flag
(IFTB)
Timer C clock source
Timer output
TOB
control logic
1
Timer read
register BU
(TRBU)
Edge detection
logic
EVNB
Timer read
register BL
(TRBL)
2
÷2
4
÷4
÷8
Timer counter B
øPER
÷32
÷128
÷512
÷2048
System
clock
(TCBL)
(TCBU)
4
4
Timer write register B
(TWBL) (TWBU)
3
Timer mode
register B1
(TMB1)
3
Timer mode
register B2
(TMB2)
Data bus
Clock line
Signal line
Figure 37 Timer B Block Diagram
85
HD404889/HD404899/HD404878/HD404868 Series
Timer B Operation
•
Free-running/reload timer:
Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected
by means of timer mode register B1 (TMB1).
Timer B is initialized to the value written to timer write register B (TWBL, TWBU) by software, and
counts up by 1 each time the input clock is input. When the input clock is input after the timer B value
reaches $FF, overflow output is generated. Timer B is then set to the value in timer write register B if
the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts
counting up again.
Overflow output sets the timer B interrupt request flag (IFTB). This flag is reset by the program or by
an MCU reset.
For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial
Values after MCU Reset.
•
External event counter operation:
When external event input is designated for the input clock, timer B operates as an external event
counter. When external event input is used, the R10/EVNB pin is designated as the EVNB pin by port
mode register 2 (PMR2).
The external event detected edge for timer B can be designated as a falling edge, rising edge, or both
falling and rising edges in the input signal by means of timer mode register B2 (TMB2). If both falling
and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc.
Timer B counts up by 1 each time a falling edge is detected in the signal input at the EVNB pin. Other
operations are the same as for the free-running/reload timer function.
•
Timer output operation:
With timer B, the R13/TOB pin is designated as the TOB pin by the setting of bit 3 of port mode
register 2 (PMR2), and toggle waveform output or PWM waveform output can be selected by timer
mode register B2 (TMB2).
Toggle output:
With toggle output, the output level is changed upon input of the next clock pulse after the timer B
value reaches $FF. Use of this function in combination with the reload timer allows a clock signal
with any period to be output, enabling it to be used as buzzer output. The output waveform is
shown in figure 38 (1).
PWM output:
With PWM output, variable-duty pulses are output. The output waveform is as shown in figure 38
(2), according to the contents of timer mode register B1 (TMB1) and timer write register B (TWBL,
TWBU). When the waveform is output with bit 3 (TMB13) of timer mode register B1 cleared to 0,
the write to timer write register B to change the duty is effective from the next frame, whereas if the
waveform is output with the TMB13 bit set to 1 (reload setting), the next frame is output
immediately after the timer write register write.
•
Module standby:
With timer B, the supply of the system clock to the timer/counter can be halted by setting bit 0 of
module standby register 1 (MSR1: $00D) to 1. In the module standby state, the mode register value is
retained but the counter value is not guaranteed.
86
HD404889/HD404899/HD404878/HD404868 Series
(1) Toggle output waveform (timer B, timer C)
Free-running timer
256 clock periods
256 clock periods
Reload timer
(256 – N)
(256 – N)
clock periods
clock periods
(2) PWM output waveform (timer B, timer C)
×
T
(N + 1)
TMB13 = 0
(free-running timer)
×
T
256
T
TMB13 = 1
(reload timer)
T × (256 – N)
Notes: T: Counter input clock period
The clock input source and division ratio are controlled by
)
(
timer mode register B1 and timer mode register C1.
N: Value in timer write register B or timer write register C
When N = 255 (= $FF), PWM output is always fixed at the timer low level.)
Figure 38 Timer Output Waveforms
87
HD404889/HD404899/HD404878/HD404868 Series
Timer B Registers
Timer B operation setting and timer B value reading/writing is controlled by the following registers.
Timer mode register B1 (TMB1: $010)
Timer mode register B2 (TMB2: $011)
Timer write register B (TWBL: $012, TWBU: $013)
Timer read register B (TRBL: $012, TRBU: $013)
Port mode register 2 (PMR2: $00A)
Module standby register 1 (MSR1: $00D)
•
Timer mode register B1 (TMB1: $010):
Timer mode register B1 (TMB1) is a 4-bit write-only register, used to select free-running/reload timer
operation and the input clock as shown in figure 39.
Timer mode register B1 (TMB1) is reset to $0 by an MCU reset:
A modification of timer mode register B1 (TMB1) becomes effective after execution of two instructions
following the timer mode register B1 (TMB1) write instruction. The program must provide for timer B
initialization by writing to timer write register B (TWBL, TWBU) to be executed after the post-
modification mode has become effective.
88
HD404889/HD404899/HD404878/HD404868 Series
Timer mode register B1 (TMB1: $010)
Bit
3
W
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
0
0
0
0
TMB13
TMB12
TMB11
TMB10
TMB10
Input clock period and input clock source
TMB12
TMB11
0
1
0
1
0
1
0
1
2,048 tcyc
512 tcyc
128 tcyc
32 tcyc
8 tcyc
0
0
1
0
1
4 tcyc
1
2 tcyc
R10/EVNB (external event input)
TMB13
Free-running/reload timer
Free-running timer
Reload timer
0
1
Figure 39 Timer Mode Register B1 (TMB1)
•
Timer mode register B2 (TMB2: $011):
Timer mode register B2 (TMB2) is a 3-bit write-only register, used to select the timer B output mode
and EVNB pin detected edge as shown in figure 40.
Timer mode register B2 (TMB2) is reset to $0 by an MCU reset.
89
HD404889/HD404899/HD404878/HD404868 Series
Timer mode register B2 (TMB2: $011)
Bit
3
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
—
—
—
0
0
0
TMB22
TMB21
TMB20
TMB21 TMB20 EVNB pin detected edge
0
1
0
1
Not detected
0
1
Falling edge detection
Rising edge detection
Both rising and falling edge detection
TMB22 Timer B output waveform
0
1
Toggle output
PWM output
Figure 40 Timer Mode Register B2 (TMB2)
•
Timer write register B (TWBL: $012, TWBU:$013):
Timer write register B (TWBL, TWBU) is a write-only register composed of a lower digit (TWBL) and
an upper digit (TWBU) (figures 41 and 42).
The lower digit (TWBL) of timer write register B is reset to $0 by an MCU reset, while the upper digit
(TWBU) is undetermined.
Timer B can be initialized by writing to timer write register B (TWBL, TWBU). To write the data, first
write the lower digit (TWBL). The lower digit write does not change the timer B value. Next, write the
upper digit (TWBU). Timer B is then initialized to the timer write register B (TWBL, TWBU) value.
When writing to timer write register B (TWBL, TWBU) from the second time onward, if it is not
necessary to change the lower digit (TWBL) reload value, timer B initialization is completed by the
upper digit write alone.
Timer write register B (lower) (TWBL: $012)
Bit
3
W
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
0
0
0
0
TWBL3
TWBL2
TWBL1
TWBL0
Figure 41 Timer Write Register B (Lower) (TWBL)
90
HD404889/HD404899/HD404878/HD404868 Series
Timer write register B (upper) (TWBU: $013)
Bit
3
2
1
0
Read/Write
Initial value on reset
Bit name
W
W
W
W
Undetermined Undetermined Undetermined Undetermined
TWBU3
TWBU2
TWBU1
TWBU0
Figure 42 Timer Write Register B (Upper) (TWBU)
Timer read register B (TRBL: $012, TRBU: $013):
•
Timer read register B (TRBL, TRBU) is a read-only register composed of a lower digit (TRBL) and an
upper digit (TRBU) from which the value of the upper digit of timer B is read directly (figures 43 and
44).
First, read the upper digit (TRBU) of timer read register B. The current value of the timer B upper digit
is read and, at the same time, the value of the timer B lower digit is latched in the lower digit (TRBL) of
timer read register B. The timer B value is obtained when the upper digit (TRBU) of timer read register
B is read by reading the lower digit (TRBL) of timer read register B.
Timer read register B (lower) (TRBL: $012)
3
R
2
1
0
Bit
R
R
R
Read/Write
Initial value on reset
Bit name
Undetermined
TRBL3
Undetermined Undetermined Undetermined
TRBL2
TRBL1
TRBL0
Figure 43 Timer Read Register B (Lower) (TRBL)
Timer read register B (upper) (TRBU: $013)
3
2
1
0
Bit
Read/Write
Initial value on reset
Bit name
R
R
R
R
Undetermined Undetermined Undetermined Undetermined
TRBU3
TRBU2
TRBU1
TRBU0
Figure 44 Timer Read Register B (Upper) (TRBU)
91
HD404889/HD404899/HD404878/HD404868 Series
•
Port mode register 2 (PMR2: $00A):
Port mode register 2 (PMR2) is a write-only register used to set the function of the R10/EVNB and
R13/TOB pins as shown in figure 45.
Port mode register 2 (PMR2) is reset to $0 by an MCU reset.
Port mode register 2 (PMR2: $00A)
Bit
3
W
2
W
1
0
W
Read/Write
Initial value on reset
Bit name
W
0
0
0
0
PMR23
PMR22
PMR21*
PMR20
PMR20 R10/EVNB pin mode selection
0
1
R10
EVNB
PMR21 R11/EVND pin mode selection
0
1
R11
EVND
PMR22 R12/BUZZ pin mode selection
0
1
R12
BUZZ
PMR23 R13/TOB pin mode selection
0
1
R13
TOB
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 45 Port Mode Register 2 (PMR2: $00A)
Module standby register 1 (MSR1: $00D):
•
Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the
clock to timer B as shown in figure 46.
Module standby register 1 (MSR1) is reset to $0 by an MCU reset.
92
HD404889/HD404899/HD404878/HD404868 Series
Module standby register 1 (MSR1: $00D)
Bit
3
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
—
—
—
0
0
0
MSR12
MSR11
MSR10
MSR10 Timer B clock supply control
Supplied
Stopped
0
1
MSR11 Timer C clock supply control
Supplied
Stopped
0
1
MSR12 Timer D clock supply control
Supplied
Stopped
0
1
Figure 46 Module Standby Register 1 (MSR1)
93
HD404889/HD404899/HD404878/HD404868 Series
Timer C
Timer C Functions:Timer : C has the following functions.
•
•
•
Free-running/reload timer
Watchdog timer
Timer output operation (toggle output, PWM output)
The block diagram of timer C is shown in figure 47.
94
HD404889/HD404899/HD404878/HD404868 Series
System reset signal
Timer C
interrupt request
flag
Watchdog on
flag
(WDON)
Watchdog timer
control logic
(IFTC)
TOC
Timer output
control logic
Timer read
register CU
(TRCU)
System
clock
ø
PER
Timer B
overflow
Timer read
register CL
(TRCL)
÷2
4
÷ 4
Timer counter C
÷ 8
Prescaler
(PSS)
÷ 32
÷ 128
÷ 512
÷ 2048
(TCCL)
(TCCU)
Selector
4
4
Timer write register C
(TWCL) (TWCU)
3
Timer mode
register C1
(TMC1)
Timer output
control
Timer mode
register C2
(TMC2)
Data bus
Clock line
Signal line
Figure 47 Timer C Block Diagram
95
HD404889/HD404899/HD404878/HD404868 Series
Timer C Operation
•
Free-running/reload timer:
Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected
by means of timer mode register C1 (TMC1).
Timer C is initialized to the value written to timer write register C (TWCL, TWCU) by software, and
counts up by 1 each time the input clock is input. When the input clock is input after the timer C value
reaches $FF, overflow output is generated. Timer C is then set to the value in timer write register C
(TWCL, TWCU) if the reload timer function is selected, or to $00 if the free-running timer function is
selected, and starts counting up again.
Overflow output sets the timer C interrupt request flag (IFTC). This flag is reset by the program or by
an MCU reset.
For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial
Values after MCU Reset.
•
•
16-bit timer operation:
When timer B overflow flag is selected as the clock source, timer C can be used as a 16-bit timer that
counts the timer B clock source pulses. In this case, since the timer B and timer C free-running/reload
settings are independent, the settings should be made to suit the purpose.
Watchdog timer operation:
By using the timer C overflow output, timer C can be used as a watchdog timer for detecting program
runaway. The watchdog timer is enabled when the watchdog on flag (WDON) is set to 1, and generates
an MCU reset when timer C overflows. Usually, timer C initialization is performed by the program
before the timer C value reaches $FF, so controlling program runaway.
•
Timer output operation:
With timer C, the R20/TOC pin is designated as the TOC pin by setting bit 0 of port mode register 3
(PMR3) to 1, and toggle waveform output or PWM waveform output can be selected by timer mode
register C2 (TMC2).
Toggle output
The operation is similar to that for timer B toggle output.
PWM output
The operation is similar to that for timer B PWM output.
Module standby:
•
The operation is similar to that for timer B module standby.
96
HD404889/HD404899/HD404878/HD404868 Series
Timer C Registers
Timer C operation setting and timer C value reading/writing is controlled by the following registers.
Timer mode register C1 (TMC1: $014)
Timer mode register C2 (TMC2: $015)
Timer write register C (TWCL: $016, TWCU: $017)
Timer read register C (TRCL: $016, TRCU: $017)
Port mode register 3 (PMR3: $00B)
Module standby register 1 (MSR1: $00D)
•
Timer mode register C1 (TMC1: $014):
Timer mode register C1 (TMC1) is a 4-bit write-only register, used to select free-running/reload timer
operation, the input clock, and the prescaler division ratio as shown in figure 48.
Timer mode register C1 (TMC1) is reset to $0 by an MCU reset.
A modification of timer mode register C1 (TMC1) becomes effective after execution of two instructions
following the timer mode register C1 (TMC1) write instruction. The program must provide for timer C
initialization by writing to timer write register C (TWCL, TWCU) to be executed after the post-
modification mode has become effective.
97
HD404889/HD404899/HD404878/HD404868 Series
Timer mode register C1 (TMC1: $014)
Bit
3
W
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
0
0
0
0
TMC13
TMC12
TMC11
TMC10
TMC12
TMC11
TMC10
Input clock period
2,048 tcyc
512 tcyc
0
1
0
1
0
1
0
1
0
0
128 tcyc
1
0
1
32 tcyc
8 tcyc
4 tcyc
1
2 tcyc
Timer B overflow
Free-running/reload timer
Free-running timer
Reload timer
TMC13
0
1
Figure 48 Timer Mode Register C1 (TMC1)
98
HD404889/HD404899/HD404878/HD404868 Series
•
Timer mode register C2 (TMC2: $015):
Timer mode register C2 (TMC2) is a 1-bit write-only register, used to select the timer C output mode as
shown in figure 49.
Timer mode register C2 (TMC2) is reset to $0 by an MCU reset.
Timer mode register C2 (TMC2: $015)
Bit
3
2
W
1
0
Read/Write
Initial value on reset
Bit name
—
—
—
—
—
—
—
—
—
0
TMC22
Timer C output waveform
Toggle output
TMC22
0
1
PWM output
Figure 49 Timer Mode Register C2 (TMC2)
Timer write register C (TWCL: $016, TWCU: $017):
•
Timer write register C (TWCL, TWCU) is a write-only register composed of a lower digit (TWCL) and
an upper digit (TWCU) (figures 50 and 51).
Timer write register C (TWCL, TWCU) operation is similar to that for timer write register B (TWBL,
TWBU).
Timer write register C (lower) (TWCL: $016)
Bit
3
W
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
0
0
0
0
TWCL3
TWCL2
TWCL1
TWCL0
Figure 50 Timer Write Register C (Lower) (TWCL)
99
HD404889/HD404899/HD404878/HD404868 Series
Timer write register C (upper) (TWCU: $017)
Bit
3
2
1
0
Read/Write
Initial value on reset
Bit name
W
W
W
W
Undetermined Undetermined Undetermined Undetermined
TWCU3
TWCU2
TWCU1
TWCU0
Figure 51 Timer Write Register C (Upper) (TWCU)
Timer read register C (TRCL: $016, TRCU: $017):
•
Timer read register C (TRCL, TRCU) is a read-only register composed of a lower digit (TRCL) and an
upper digit (TRCU) from which the value of the upper digit of timer C is read directly (figures 52 and
53).
Timer read register C (TRCL, TRCU) operation is similar to that for timer read register B (TRBL,
TRBU).
Timer read register C (upper) (TRCL: $016)
0
R
Bit
3
2
1
Read/Write
Initial value on reset
Bit name
R
R
R
Undetermined
TRCL0
Undetermined Undetermined Undetermined
TRCL3
TRCL2
TRCL1
Figure 52 Timer Read Register C (Lower) (TRCL)
Timer read register C (upper) (TRCU: $017)
0
R
Bit
3
2
1
Read/Write
Initial value on reset
Bit name
R
R
R
Undetermined
TRCU0
Undetermined Undetermined Undetermined
TRCU3
TRCU2
TRCU1
Figure 53 Timer Read Register C (Upper) (TRCU)
100
HD404889/HD404899/HD404878/HD404868 Series
•
Port mode register 3 (PMR3: $00B):
Port mode register 3 (PMR3) is a write-only register used to set the function of the R20/TOC pin as
shown in figure 54.
Port mode register 3 (PMR3) is reset to $0 by an MCU reset.
Port mode register 3 (PMR3: $00B)
Bit
3
W
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
0
0
0
0
PMR33
PMR32
PMR31
PMR30
PMR30 R2
0
/TOC pin mode selection
R2
TOC
0
1
0
PMR31
R2
1
/SCK pin mode selection
R2
SCK
0
1
1
PMR33
PMR32
R2 /SI/SO pin mode selection
2
0
1
R2
2
0
1
SI
SO
: Don't care
Figure 54 Port Mode Register 3 (PMR3)
Module standby register 1 (MSR1: $00D):
•
Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the
clock to timer C as shown in figure 46.
Module standby register 1 (MSR1) is reset to $0 by an MCU reset.
101
HD404889/HD404899/HD404878/HD404868 Series
Timer D (HD404889/HD404899/HD404878 Series)
Timer D functions : Timer D has the following functions.
•
•
•
Free-running/reload timer
External event counter
Input capture timer
Block diagrams of timer D in different operating modes are shown in figures 55-1 and 55-2.
102
HD404889/HD404899/HD404878/HD404868 Series
Timer D interrupt
request flag
(IFTD)
EVND
Edge detection
logic
Timer read register
DU (TRDU)
øPER
System
clock
Timer read
register DL
(TRDL)
÷ 2
4
÷ 4
÷ 8
Timer counter D
(TCDL) (TCDU)
÷ 32
÷ 128
4
4
÷ 512
÷ 2048
Timer write register D
(TWDL) (TWDU)
3
Timer mode
register D1
(TMD1)
2
Edge detection
control
Timer mode
register D2
(TMD2)
Data bus
Clock line
Signal line
Figure 55-1 Timer D Block Diagram (Reload Timer and Event Counter Modes)
103
HD404889/HD404899/HD404878/HD404868 Series
Input capture
status flag
(ICSF)
Input capture
error flag
(ICEF)
Timer D interrupt
request flag
(IFTD)
EVND
Edge detection
logic
Read signal
2
øPER
System
clock
Timer read register D
(TRDL)
(TRDU)
÷2
4
4
÷4
÷8
Timer counter D
÷32
÷128
÷512
÷2048
(TCDL)
(TCDU)
Input capture
timer control
3
Timer mode
register D2
(TMD2)
3
Time mode
register D1
(TMD1)
Data bus
Clock line
Signal line
Figure 55-2 Timer D Block Diagram (Input Capture Timer Mode)
104
HD404889/HD404899/HD404878/HD404868 Series
Timer D Operation
•
Free-running/reload timer:
Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected
by means of timer mode register D1 (TMD1).
Timer D is initialized to the value written to timer write register D (TWDL, TWDU) by software, and
counts up by 1 each time the input clock is input. When the input clock is input after the timer D value
reaches $FF, overflow output is generated. Timer D is then set to the value in timer write register D
(TWDL, TWDU) if the reload timer function is selected, or to $00 if the free-running timer function is
selected, and starts counting up again.
Overflow output sets the timer D interrupt request flag (IFTD). This flag is reset by the program or by
an MCU reset. For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration,
and table 1, Initial Values after MCU Reset.
•
External event counter operation:
When external event input is designated for the input clock, timer D operates as an external event
counter. When external event input is used, the R11/EVND pin is designated as the EVND pin by port
mode register 2 (PMR2).
The external event detected edge for timer D can be designated as a falling edge, rising edge, or both
falling and rising edges in the input signal by means of timer mode register D2 (TMD2). If both falling
and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc.
Timer D counts up by 1 each time the edge selected by timer mode register D2 (TMD2) is detected.
Other operations are the same as for the free-running/reload timer function.
•
Input capture timer operation:
The input capture timer function is used to measure the time between trigger input edges input at the
EVND pin.
The trigger input edge can be designated as a falling edge, rising edge, or both falling and rising edges
by means of timer mode register D2 (TMD2).
When a trigger input edge is detected at the EVND pin, the current timer D value is stored in timer read
register D (TRDL, TRDU), and the timer D interrupt request flag (IFTD) and input capture status flag
(ICSF) are set. At the same time, timer D is reset to $00 and continues counting up.
If the next trigger input edge is input while the input capture status flag (ICSF) is set, or if timer D
overflows, the input capture error flag (ICEF) is set.
The input capture status flag (ICSF) and input capture error flag (ICEF) are reset to 0 by an MCU reset
or by writing 0 to them.
When timer D is set to operate as an input capture timer, it is reset to $00.
105
HD404889/HD404899/HD404878/HD404868 Series
Timer D Registers: Timer D operation setting and timer D value reading/writing is controlled by the
following registers.
Timer mode register D1 (TMD1: $018)
Timer mode register D2 (TMD2: $019)
Timer write register D (TWDL: $01A, TWDU: $01B)
Timer read register D (TRDL: $01A, TRDU: $01B)
Port mode register 2 (PMR2: $00A)
Module standby register 1 (MSR1: $00D)
•
Timer mode register D1 (TMD1: $018):
Timer mode register D1 (TMD1) is a 4-bit write-only register, used to select free-running/reload timer
operation, the input clock, and the prescaler division ratio as shown in figure 56.
Timer mode register D1 (TMD1) is reset to $0 by an MCU reset.
A modification of timer mode register D1 (TMD1) becomes effective after execution of two
instructions following the timer mode register D1 (TMD1) write instruction. The program must provide
for timer D initialization by writing to timer write register D (TWDL, TWDU) to be executed after the
post-modification mode has become effective.
When timer D is set to operate as an input capture timer, an internal clock should be set as the input
clock.
106
HD404889/HD404899/HD404878/HD404868 Series
Timer mode register D1 (TMD1: $018)
3
W
2
W
1
W
0
W
Bit
Read/Write
Initial value on reset
Bit name
0
0
0
0
TMD13
TMD12
TMD11
TMD10
TMD12
TMD11
TMD10
Input clock period and input clock source
2,048 tcyc
0
1
0
1
0
1
0
1
0
512 tcyc
0
128 tcyc
1
0
1
32 tcyc
8 tcyc
4 tcyc
2 tcyc
1
R11/EVND (external event input)
TMD13
Free-running/reload timer
Free-running timer
Reload timer
0
1
Figure 56 Timer Mode Register D1 (TMD1)
•
Timer mode register D2 (TMD2: $019):
Timer mode register D2 (TMD2) is a 3-bit write-only register, used to select the EVND pin detected
edge and input capture operation as shown in figure 57.
Timer mode register D2 (TMD2) is reset to $0 by an MCU reset.
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HD404889/HD404899/HD404878/HD404868 Series
Timer mode register D2 (TMD2: $019)
Bit
3
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
—
—
—
0
0
0
TMD22
TMD21
TMD20
EVND pin detected edge
Not detected
TMD21
TMD20
0
1
0
1
0
Falling edge detection
Rising edge detection
1
Both rising and falling edge detection
TMD22
Input capture setting
0
1
Free-running/reload timer
Input capture timer
Figure 57 Timer Mode Register D2 (TMD2)
•
Timer write register D (TWDL: $01A, TWDU: $01B):
Timer write register D (TWDL, TWDU) is a write-only register composed of a lower digit (TWDL) and
an upper digit (TWDU) (figures 58 and 59).
Timer write register D (TWDL, TWDU) operation is similar to that for timer write register B (TWBL,
TWBU).
Timer write register D (lower) (TWDL: $01A)
Bit
3
W
2
W
1
W
0
W
Read/Write
Initial value on reset
Bit name
0
0
0
0
TWDL3
TWDL2
TWDL1
TWDL0
Figure 58 Timer Write Register D (Lower) (TWDL)
108
HD404889/HD404899/HD404878/HD404868 Series
Timer write register D (upper) (TWDU: $01B)
Bit
3
2
1
0
Read/Write
Initial value on reset
Bit name
W
W
W
W
Undetermined Undetermined Undetermined Undetermined
TWDU3
TWDU2
TWDU1
TWDU0
Figure 59 Timer Write Register D (Upper) (TWDU)
Timer read register D (TRDL: $01A, TRDU: $01B):
•
Timer read register D (TRDL, TRDU) is a read-only register composed of a lower digit (TRDL) and an
upper digit (TRDU) (figures 60 and 61).
Timer read register D (TRDL, TRDU) operation is similar to that for timer read register B (TRBL,
TRBU).
In the input capture timer operating mode, when the timer D value is read after trigger input, it does not
matter whether the lower or upper digit is read first.
Timer read register D (lower) (TRDL: $01A)
Bit
3
2
1
0
Read/Write
Initial value on reset
Bit name
R
R
R
R
Undetermined Undetermined Undetermined Undetermined
TRDL3
TRDL2
TRDL1
TRDL0
Figure 60 Timer Read Register D (Lower) (TRDL)
Timer read register D (upper) (TRDU: $01B)
Bit
3
2
1
0
Read/Write
Initial value on reset
Bit name
R
R
R
R
Undetermined Undetermined Undetermined Undetermined
TRDU3
TRDU2
TRDU1
TRDU0
Figure 61 Timer Read Register D (Upper) (TRDU)
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HD404889/HD404899/HD404878/HD404868 Series
•
Port mode register 2 (PMR2: $00A):
Port mode register 2 (PMR2) is a write-only register used to set the R11/EVND pin function as shown in
figure 45.
Port mode register 2 (PMR2) is reset to $0 by an MCU reset.
Module standby register 1 (MSR1: $00D):
•
Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the
clock to timer D as shown in figure 46.
Module standby register 1 (MSR1) is reset to $0 by an MCU reset.
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HD404889/HD404899/HD404878/HD404868 Series
Serial Interface
The serial interface serially transfers and receives 8-bit data, and includes the following features.
•
Multiple transmit clock sources
External clock
Internal prescaler output clock
System clock
•
Output level control in idle states
Five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows.
•
•
•
•
•
•
Serial data register (SRL: $026, SRU: $027)
Serial mode register 1 (SMR1: $024)
Serial mode register 2 (SMR2: $025)
Port mode register 3 (PMR3: $00B)
Octal counter (OC)
Selector
The block diagram of the serial interface is shown in figure 62.
111
HD404889/HD404899/HD404878/HD404868 Series
Serial interrupt
request flag
(IFS)
Octal counter
(OC)
Idle control
SI/SO
logic
Clock
I/O control
Serial data
register
SCK
logic
(SRL/U)
øPER
System
clock
Transfer
control
1/2
1/2
2
÷2
÷8
4
Serial mode
register 1
(SMR1)
÷32
÷128
÷512
÷2048
Serial mode
register 2
(SMR2)
Data bus
Clock line
Signal line
Figure 62 Serial Interface Block Diagram
112
HD404889/HD404899/HD404878/HD404868 Series
Serial Interface Operation
Selecting and changing serial interface operating mode:
The operating modes that can be selected for the serial interface are shown in table 26. The combination of
port mode register 3 (PMR3) values should be selected from this table. When the serial interface operating
mode is changed, the serial interface internal state must be initialized by writing to serial mode register 1
(SMR1).
Note : The serial interface is initialized by writing to serial mode register 1 (SMR1: $024). See serial
mode register 1 for details.
Table 26
Serial Interface Operating Modes
PMR3
Bit2
Serial interface operating mode
Bit3
Bit1
1
0
*
Clock continuous output mode
Receive mode
1
0
1
1
1
1
Transmit mode
*: Don't care
Serial interface pin setting:
The R21/SCK pin and R22/SI/SO pin are set by writing data to port mode register 3 (PMR3). See serial
interface registers for details.
Serial clock source setting:
The serial clock is set by writing data to serial mode register 1 (SMR1). See serial interface registers for
details.
Serial data setting:
Transmit serial data is set by writing data to the serial data register (SRL, SRU).
Receive serial data is obtained by reading the serial data register (SRL, SRU). Serial data is shifted by
means of the serial clock to perform input/output from/to an external device.
The output level of the SO pin is undetermined until the first data is output after a reset by the MCU, or
until high/low control is performed in the idle state.
Transfer control:
Serial interface operation is started by an STS instruction. The octal counter is reset to 000 by the STS
instruction, and is incremented by 1 on each rise of the serial clock. When 8 serial clock pulses have been
input, or if data transmission/reception is suspended midway, the octal counter is reset to 000, the serial
interrupt request flag (IFS) is set, and transfer is terminated.
The serial clock is selected by means of serial mode register 1 (SMR1). See figure 66.
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HD404889/HD404899/HD404878/HD404868 Series
Serial interface operating states:
The serial interface has the operating states shown in figure 63 in external clock mode and internal clock
mode.
STS instruction wait state
Serial clock wait state
Transfer state
Clock continuous output state (internal clock mode only)
•
•
STS instruction wait state
Upon MCU reset ((00) and (10) in figure 63), the serial interface enters the STS instruction wait state.
In the STS instruction wait state, the internal state of the serial interface is initialized. Even if the serial
clock is input at this time, the serial interface will not operate. When the STS instruction is executed
((01), (11)), the serial interface enters the serial clock wait state.
Serial clock wait state
The serial clock wait state is the interval from STS instruction execution until the first serial clock
falling edge. When the serial clock is input in the serial clock wait state ((02), (12)), the octal counter
begins counting, the contents of the serial data register (SRL) begin shifting, and the serial interface
enters the transfer state. However, if clock continuous output mode is selected in internal clock mode,
the serial interface enters the clock continuous output state ((17)) instead of the transfer state.
If a write to serial mode register 1 (SMR1) is performed in the serial clock wait state, the serial interface
enters the STS instruction wait state ((04), (14)).
•
Transfer state
The transfer state is the interval from the first serial clock falling edge until the eighth serial clock rising
edge. In the transfer state, if an STS instruction is executed or if eight serial clocks have been input, the
octal counter is cleared to 000, and the serial interface makes a state transition. If an STS instruction is
executed ((05), (15)), the serial interface enters the serial clock wait state. After eight serial clocks have
been input, the serial interface enters the serial clock wait state ((03)) when in external clock mode, and
enters the STS instruction wait state ((13)) when in internal clock mode.
In internal clock mode, the serial clock stops after output of eight clocks.
If a write to serial mode register 1 (SMR1) is performed in the transfer state ((06), (16)), the serial
interface is initialized and enters the STS instruction wait state.
When the serial interface switches from the transfer state to another state, the octal counter is reset to
000 and the serial interrupt request flag (IFS) is set.
•
Clock continuous output state (internal clock mode only)
In the clock continuous output state, no receive or transmit operation is performed, and the serial clock
is only output from the SCK pin. It is therefore effective in internal clock mode.
If the serial clock is input ((17)) when bit 3 (PMR33) of port mode register 3 (PMR3) is cleared to 0 and
the serial interface is in the serial clock wait state, a transition is made to the clock continuous output
state.
If a write to serial mode register 1 (SMR1) is performed in the clock continuous output state ((18)), the
serial interface enters the STS instruction wait state.
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HD404889/HD404899/HD404878/HD404868 Series
STS instruction wait state
(octal counter ="000",
serial clock disabled)
MCU reset (00)
SMR1 write (04)
SMR1 write (06)
STS instruction (01)
Serial clock (02)
(IFS ← "1")
Serial clock wait state
Transfer state
(octal counter ="000")
(octal counter ≠"000")
8 serial clocks (03)
STS instruction (05)
(IFS ← "1")
External clock mode
STS instruction wait state
MCU reset (10)
SMR1 write (18)
(octal counter ="000",
serial clock disabled)
8 serial clocks (13)
SMR1 write (16)
(IFS←"1")
Clock continuous output state
(PMR33 ="0")
SMR1 write (14)
STS instruction (11)
Serial clock (12)
Serial clock (17)
Transfer state
Serial clock wait state
(octal counter ="000")
(octal counter ≠"000")
STS instruction (15)
(IFS←"1")
Internal clock mode
) Refer to the text for details on the circled numbers in the figure.
(
Figure 63 Serial Interface Operating States
115
HD404889/HD404899/HD404878/HD404868 Series
Idle high/low control:
When the serial interface is in the STS instruction wait state or the serial clock wait state (i.e. when idle),
the output level of the SO pin can be set arbitrarily by software. Idle high/low control is performed by
writing the output level to bit 1 (SMR21) of serial mode register 2 (SMR2).
An example of idle high/low control is shown in figure 64. Idle high/low control cannot be performed in
the transfer state.
116
HD404889/HD404899/HD404878/HD404868 Series
Serial clock
wait state
Serial clock
wait state
Transfer state
STS wait state
Port setting
STS wait state
State
MCU reset
PMR3 write
SMR1 write
SMR2 write
SRL, SRU write
External clock setting
Idle H/L setting
Transmit data write
Dummy write to
cause state transition
Idle H/L setting
STS instruction
SCK pin (input)
SO pin
IFS
LSB
Undefined
Idle
MSB
Idle
(Flag reset by transfer
completion processing)
(1) External clock mode
Serial clock
wait state
STS wait state
Transfer state
STS wait state
State
MCU reset
PMR3 write
SMR1 write
SMR2 write
SRL, SRU write
Port setting
External clock setting
Idle H/L setting
Idle H/L setting
Transmit data write
STS instruction
SCK pin (output)
SO pin
IFS
LSB
Idle
Idle
Undefined
MSB
(2) Internal clock mode
(Flag reset by transfer
completion processing)
Figure 64 Examples of Serial Interface Operation Sequence
117
HD404889/HD404899/HD404878/HD404868 Series
Serial clock error detection (external clock mode):
The serial interface will operate incorrectly in the transfer state if external noise results in unnecessary
pulses being added to the serial clock. Serial clock error detection in such cases is carried out as shown in
figure 65.
If more than eight serial clock pulses are input due to external noise while in the transfer state, at the eighth
clock pulse (including any external noise pulses), the octal counter is cleared to 000 and the serial interrupt
request flag (IFS) is set. At the same time, the serial interface exits the transfer state and enters the serial
clock wait state, but returns to the transfer state at the next regular clock pulse falling edge.
Meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial interrupt
request flag is reset, and a dummy write is performed into serial mode register 1 (SMR1). The serial
interface then returns to the STS wait state, and the serial interrupt request flag (IFS) is set again. It is
therefore possible to detect a serial clock error by testing the serial interrupt request flag after the dummy
write to serial mode register 1.
Usage notes:
•
Initialization after register modification
If a port mode register 3 (PMR3) write is performed in the serial clock wait state or transfer state, a
serial mode register 1 (SMR1) write should be performed again to initialize the serial interface.
•
Serial interrupt request flag (IFS:$023, 2) setting
If a serial mode register 1 (SMR1) write or STS instruction is executed during the first low-level
interval of the serial clock in the transfer state, the serial interrupt request flag (IFS) will not be set. To
ensure that the serial interrupt request flag (IFS) is properly set in this case, programming is required to
make sure that the SCK pin is in the 1 state (by executing an input instruction for the R2 port) before
executing a serial mode register 1 (SMR1) write or an STS instruction.
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HD404889/HD404899/HD404878/HD404868 Series
Transfer end
(IFS←"1")
Disable interrupts
IFS←"0"
SMR1 write
Yes
Serial clock
error processing
IFS=1?
No
Normal termination
(1) Serial clock error detection flowchart
Serial clock
wait state
Serial clock
wait state
Transfer state
Transfer state
State
SCK pin
(input)
Because the serial
(Noise)
interface returns to
the transfer state, a
write to SMR1
1
2
3
4
5
6
7
8
resets IFS.
SMR1
write
IFS
Flag set by octal
counter reaching
000
Flag reset by transfer
end processing
(2) Serial clock error detection sequence
Figure 65 Example of Serial Clock Error Detection
119
HD404889/HD404899/HD404878/HD404868 Series
Serial Interface Registers
Serial interface operation setting and serial data reading/writing is controlled by the following registers.
Serial mode register 1 (SMR1: $024)
Serial mode register 2 (SMR2: $025)
Serial data register (SRL: $026, SRU: $027)
Port mode register 3 (PMR3: $00B)
Module standby register 2 (MSR2: $00E)
Serial mode register 1 (SMR1: $024):
Serial mode register 1 (SMR1) has the following functions. See figure 66.
•
•
•
Serial clock selection
Prescaler division ratio selection
Serial interface initialization
The serial mode register 1 (SMR1) is a 4-bit write-only register, and is reset to $0 by an MCU reset.
A write to serial mode register 1 (SMR1) halts the supply of the serial clock to the serial data register (SRL,
SRU) and the octal counter, and resets the octal counter to 000. Therefore, if serial mode register 1
(SMR1) is written to during serial interface operation, data transmission/reception will be suspended and
the serial interrupt request flag (IFS) will be set.
A modification of serial mode register 1 (SMR1) becomes effective after execution of two instructions
following the serial mode register 1 (SMR1) write instruction. The program must therefore provide for the
STS instruction to be executed two cycles after the instruction that writes to serial mode register 1 (SMR1).
120
HD404889/HD404899/HD404878/HD404868 Series
Serial mode register 1 (SMR1: $024)
Bit
3
W
0
2
W
0
1
W
0
0
W
0
Read/Write
Initial value on reset
Bit name
SMR13 SMR12 SMR11 SMR10
Serial clock
source (PSS division ratio ÷ 2 or 4)
Serial clock
Serial clock
cycle
SMR13 SMR12 SMR11 SMR10 SCK pin
Output
Output
Output
Output
Output
Output
Output
Input
0
1
0
1
0
1
PSS
(øPER/2048)÷2
(øPER/512)÷2
(øPER/128)÷2
(øPER/32)÷2
(øPER/8)÷2
4096 tcyc
1024 tcyc
256 tcyc
64 tcyc
16 tcyc
4 tcyc
0
1
0
PSS
0
1
0
1
PSS
PSS
0
PSS
(øPER/2)÷2
PSS
ø
PER
tcyc
System clock
External clock
PSS
0
1
0
1
0
1
0
1
0
1
0
(øPER/2048)÷4
(øPER/512)÷4
(øPER/128)÷4
(øPER/32)÷4
(øPER/8)÷4
8192 tcyc
2048 tcyc
Output
Output
Output
Output
Output
Output
Output
Input
PSS
PSS
512 tcyc
128 tcyc
32 tcyc
8 tcyc
1
0
1
PSS
1
PSS
(øPER/2)÷4
PSS
ø
PER
tcyc
System clock
External clock
1
Figure 66 Serial Mode Register 1 (SMR1)
Serial mode register 2 (SMR2: $025):
Serial mode register 2 (SMR2) has the following functions. See figure 67.
•
•
R22/SI/SO pin PMOS control
Idle high/low control
Serial mode register 2 (SMR2) is a 2-bit write-only register. The register value cannot be modified in the
transfer state.
Bit 2 (SMR22) of serial mode register 2 (SMR2) controls the on/off status of the R22/SI/SO pin PMOS.
The bit 2 (SMR22) only is reset to 0 by an MCU reset.
121
HD404889/HD404899/HD404878/HD404868 Series
Bit 1 (SMR21) of serial mode register 2 (SMR2) performs SO pin high/low control in the idle state. The
SO pin changes at the same time as the high/low write.
Serial mode register 2 (SMR2: $025)
Bit
3
2
W
0
1
W
0
Read/Write
Initial value on reset
Bit name
—
—
—
—
—
undeternined
SMR22 SMR21
SMR21
Idle high/low control
0
1
SO pin set to low-level output in idle state
SO pin set to high-level output in idle state
SMR22 R22/SI/SO pin output buffer control
PMOS active
0
1
PMOS off (NMOS open-drain output)
Figure 67 Serial Mode Register 2 (SMR2)
Serial data register (SRL: $026, SRU: $027):
The serial data register (SRL, SRU) has the following functions. See figures 68 and 69.
•
•
Transmit data write and shift operations
Receive data shift and read operations
The data written to the serial data register (SRL, SRU) is output LSB-first from the SO pin in
synchronization with the falling edge of the serial clock.
External data input LSB-first from the SI pin is latched in synchronization with the rising edge of the serial
clock. Figure 70 shows the serial clock and data input/output timing chart.
Writing and reading of the serial data register (SRL, SRU) must be performed only after data
transmission/reception is completed. The data contents are not guaranteed if a read or write is performed
during data transmission or reception.
122
HD404889/HD404899/HD404878/HD404868 Series
Serial data register (lower) (SRL: $026)
Bit
3
2
1
0
Read/Write
Initial value on reset
Bit name
R/W
R/W
R/W
R/W
Undetermined Undetermined Undetermined Undetermined
SR3
SR2
SR1
SR0
Figure 68 Serial Data Register (SRL)
Serial data register (upper) (SRU: $027)
Bit
3
2
1
0
Read/Write
Initial value on reset
Bit name
R/W
R/W
R/W
R/W
Undetermined Undetermined Undetermined Undetermined
SR7 SR6 SR5 SR4
Figure 69 Serial Data Register (SRU)
Serial
clock
1
2
3
4
5
6
7
8
MSB
Serial output
data
LSB
Serial input
data latch
timing
Figure 70 Serial Interface Input/Output Timing Chart
123
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 3 (PMR3: $00B):
Port mode register 3 (PMR3) has the following functions. See figure 71.
•
•
R21/SCK pin selection
R22/SI/SO pin selection
Port mode register 3 (PMR3) is a 4-bit write-only register used to select serial interface pin settings as
shown in figure 71. It is reset to $0 by an MCU reset.
Port mode register 3 (PMR3: $00B)
Bit
3
W
0
2
W
0
1
W
0
0
W
0
Read/Write
Initial value on reset
Bit name
PMR33 PMR32 PMR31 PMR30
PMR30 R20/TOC pin mode selection
0
1
R20
TOC
PMR31 R21/SCK pin mode selection
0
1
R21
SCK
PMR33 PMR32 R22/SI/SO pin mode selection
0
*
0
1
R22
SI
1
SO
* : Don't care
Figure 71 Port Mode Register 3 (PMR3)
124
HD404889/HD404899/HD404878/HD404868 Series
Module standby register 2 (MSR2: $00E):
Module standby register 2 (MSR2) is a write-only register used to designate supply or stopping of the clock
to the serial interface as shown in figure 72.
Module standby register 2 (MSR2) is reset to $0 by an MCU reset.
Module standby register 2 (MSR2: $00E)
Bit
3
2
1
W
0
0
W
0
Read/Write
Initial value on reset
Bit name
—
—
—
—
—
—
MSR21 MSR20
MSR20 Serial clock supply control
Supplied
Stopped
0
1
A/D clock supply control
Supplied
MSR21
0
1
Stopped
Figure 72 Module Standby Register 2 (MSR2)
125
HD404889/HD404899/HD404878/HD404868 Series
A/D Converter
HD404889 Series
The MCU has a built-in successive approximation type A/D converter using a resistance ladder method,
capable of digital conversion of six analog inputs with an 8-bit resolution. The A/D converter block
diagram is shown in figure 73.
The A/D converter comprises the following four registers.
•
•
•
•
A/D mode register (AMR: $028)
A/D start flag (ADSF: $020,2)
A/D data register (ADRL: $02A, ADRU: $02B)
Module standby register 2 (MSR2: $00E)
Note : Address $029 is a reserved register, and should not be read or written to.
Interrupt flag
(IFAD)
A/D data
register
Encoder
(ADRU, ADRL)
3
R70
R71
R72
R73
R80
R81
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
A/D mode
register
(AMR)
+
–
A/D
control
logic
COMP
Conversion time control
AVCC
AVSS
A/D
start flag
(ADSF)
Reference
voltage control
Operating mode signal (set to 1 in
stop, watch, and subactive modes,
and during module standby)
D/A
Figure 73 A/D Converter Block Diagram
126
HD404889/HD404899/HD404878/HD404868 Series
A/D mode register (AMR: $028):
The A/D mode register is a 4-bit write-only register that shows the A/D converter speed setting and
information on the analog input pin specification. The A/D conversion time is selected by bit 0, and the
channel by bits 1, 2, and 3 (figure 74).
A/D start flag (ADSF: $020,2):
A/D conversion is started by writing 1 to the A/D start flag. When conversion ends, the converted data is
placed in the A/D data register and the A/D start flag is cleared at the same time. (figure 75).
A/D mode register (AMR: $028)
3
W
0
2
W
0
1
W
0
0
W
0
Bit
Read/Write
Initial value on reset
Bit name
AMR3 AMR2 AMR1 AMR0
AMR0
A/D conversion time
65 tcyc
0
1
125 tcyc
AMR3 AMR2 AMR1 Analog input channel selection
*
0
1
0
1
0
1
No selection
AN0
0
1
0
AN1
AN2
0
1
AN3
1
AN4
AN5
* : Don't care
Figure 74 A/D Mode Register (AMR)
127
HD404889/HD404899/HD404878/HD404868 Series
A/D start flag (ADSF: $020,2)
3
R/W
0
2
R/W
0
1
R/W
0
0
R/W
0
Bit
Read/Write
Initial value on reset
Bit name
DTON
ADSF
WDON
LSON
LSON (see low-power mode section)
WDON (see timer section)
A/D start flag (ADSF)
A/D conversion starts
1
0
Indicates end of A/D conversion
DTON (see low-power mode section)
Figure 75 A/D Start Flag (ADSF)
A/D data register (ADRL: $02A, ADRU: $02B):
The A/D data register is a read-only register consisting of a lower and upper 4 bits. This register is not
cleared by a reset. Also, data read during A/D conversion is not guaranteed. At the end of A/D conversion,
the resulting 8-bit data is stored in this register, and is held until the next conversion operation starts
(figures 76, 77, and 78).
ADRU : $02B
ADRL : $02A
3
2
1
0
3
2
1
0
MSB
bit7
LSB
bit0
Conversion result
Figure 76 A/D Data Register
128
HD404889/HD404899/HD404878/HD404868 Series
A/D data register-lower (ADRL: $02A)
Bit
3
2
1
0
Read/Write
Initial value on reset
Bit name
R
1
R
1
R
1
R
1
ADRL3
ADRL2
ADRL1
ADRL0
Figure 77 A/D Data Register-Lower (ADRL)
A/D data register-upper (ADRU: $02B)
Bit
3
2
1
0
Read/Write
Initial value on reset
Bit name
R
R
1
R
1
R
1
0
ADRU3
ADRU2
ADRU1
ADRU0
Figure 78 A/D Data Register-Upper (ADRU)
Module standby register 2 (MSR2: $00E):
Writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the A/D module and
cuts the current (IAD) flowing in the ladder resistor.
Usage notes:
•
•
•
•
Use the SEM or SEMD instruction to write to the A/D start flag (ADSF).
Do not write to the ADSF during A/D conversion.
Data in the A/D data register is undetermined during A/D conversion.
As the A/D converter operates on a clock from OSC, it stops in stop mode, watch mode, and subactive
mode. The current flowing in the A/D converter ladder resistor is also cut in these low-power modes to
reduce power consumption.
•
When an analog input pin is selected by the A/D mode register, the pull-up MOS for that pin is
disabled.
129
HD404889/HD404899/HD404878/HD404868 Series
A/D Converter
HD404899/HD404868 Series
The MCU has a built-in successive approximation type A/D converter using a resistance ladder method,
capable of digital conversion of six analog inputs (four analog inputs in the HD404868 Series) with a 10-bit
resolution. The A/D converter block diagram is shown in figures 79-1 and 79-2.
The A/D converter comprises the following four registers.
•
•
•
•
A/D mode register (AMR: $028)
A/D start flag (ADSF: $020,2)
A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B)
Module standby register 2 (MSR2: $00E)
Interrupt flag
(IFAD)
A/D data
register
Encoder
(ADRU, ADRM, ADRL)
3
R7
R7
R7
R7
R8
R8
0/AN
1/AN
2/AN
3/AN
0/AN
1/AN
0
1
2
3
4
5
A/D mode
register
(AMR)
+
–
A/D
control
logic
COMP
Conversion time control
AVCC
AVSS
A/D
start flag
(ADSF)
Reference
voltage control
Operating mode signal (set to 1 in
stop, watch, and subactive modes,
and during module standby)
D/A
Figure 79-1 A/D Converter Block Diagram (HD404899 Series)
130
HD404889/HD404899/HD404878/HD404868 Series
Interrupt flag
(IFAD)
A/D data
register
Encoder
(ADRU, ADRM, ADRL)
3
A/D mode
register
(AMR)
R7
R7
R7
R7
0
1
2
3
/AN
/AN
/AN
/AN
0
1
2
3
+
–
A/D
control
logic
COMP
Conversion time control
VCC
A/D
start flag
(ADSF)
Reference
voltage control
Operating mode signal (set to 1 in
stop, watch, and subactive modes,
and during module standby)
GND
D/A
Figure 79-2 A/D Converter Block Diagram (HD404868 Series)
131
HD404889/HD404899/HD404878/HD404868 Series
A/D mode register (AMR: $028):
The A/D mode register is a 4-bit write-only register that shows the A/D converter speed setting and
information on the analog input pin specification. The A/D conversion time is selected by bit 0, and the
channel by bits 1, 2, and 3 (figure 80).
A/D start flag (ADSF: $020,2):
A/D conversion is started by writing 1 to the A/D start flag. When conversion ends, the converted data is
placed in the A/D data register and the A/D start flag is cleared at the same time. (figure 81).
A/D mode register (AMR: $028)
3
W
0
2
W
0
1
W
0
0
W
0
Bit
Read/Write
Initial value on reset
Bit name
AMR3 AMR2 AMR1 AMR0
AMR0
A/D conversion time
65 tcyc
0
1
125 tcyc
AMR3 AMR2 AMR1 Analog input channel selection
No selection
AN0
0
1
0
0
1
0
1
0
1
AN1
AN2
0
1
AN3
1
AN4*
AN5
*
Note: * Applies to HD404899 Series.
Figure 80 A/D Mode Register (AMR)
132
HD404889/HD404899/HD404878/HD404868 Series
A/D start flag (ADSF: $020,2)
3
R/W
0
2
R/W
0
1
R/W
0
0
R/W
0
Bit
Read/Write
Initial value on reset
Bit name
DTON
ADSF
WDON
LSON
LSON (see low-power mode section)
WDON (see timer section)
A/D start flag (ADSF)
A/D conversion starts
1
0
Indicates end of A/D conversion
DTON (see low-power mode section)
Figure 81 A/D Start Flag (ADSF)
A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B):
The A/D data register is a read-only register consisting of a middle and upper 4 bits. This register is not
cleared by a reset. Also, data read during A/D conversion is not guaranteed. At the end of A/D conversion,
the resulting 10-bit data is stored in this register, and is held until the next conversion operation starts
(figures 82, 83, 84 and 85).
ADRU : $02B
ADRM : $02A
ADRL : $029
3
2
1
0
3
2
1
0
3
2
MSB
bit9
LSB
bit0
Conversion result
Figure 82 A/D Data Register
133
HD404889/HD404899/HD404878/HD404868 Series
A/D data register-lower (ADRL: $029)
Bit
3
2
1
—
0
—
Read/Write
Initial value on reset
Bit name
R
1
R
1
—
—
ADRL3
ADRL2
Not used
Not used
Figure 83 A/D Data Register-Lower (ADRL)
A/D data register-middle (ADRM: $02A)
Bit
3
2
1
0
Read/Write
Initial value on reset
Bit name
R
1
R
1
R
1
R
1
ADRM3
ADRM2
ADRM1
ADRM0
Figure 84 A/D Data Register-Middle (ADRM)
A/D data register-upper (ADRU: $02B)
Bit
3
2
1
0
Read/Write
Initial value on reset
Bit name
R
R
1
R
1
R
1
0
ADRU3
ADRU2
ADRU1
ADRU0
Figure 85 A/D Data Register-Upper (ADRU)
Module standby register 2 (MSR2: $00E):
Writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the A/D module and
cuts the current (IAD) flowing in the ladder resistor.
Usage notes:
•
•
•
Use the SEM or SEMD instruction to write to the A/D start flag (ADSF).
Do not write to the ADSF during A/D conversion.
Data in the A/D data register is undetermined during A/D conversion.
134
HD404889/HD404899/HD404878/HD404868 Series
•
•
As the A/D converter operates on a clock from OSC, it stops in stop mode, watch mode, and subactive
mode. The current flowing in the A/D converter ladder resistor is also cut in these low-power modes to
reduce power consumption.
When an analog input pin is selected by the A/D mode register, the pull-up MOS for that pin is
disabled.
135
HD404889/HD404899/HD404878/HD404868 Series
LCD Circuit
The MCU incorporates a controller and driver that drive four common signal pins and 32 segment pins (24
segment pins in the HD404868 Series). The controller unit consists of a RAM unit that stores the display
data, a display control register (LCR), and a duty/clock control register (LMR) (figures 86-1 and 86-2).
The LCD circuit allows four different duties and LCD clocks to be controlled by the program, and also
incorporates dual-port RAM, enabling display data to be transferred to the segment signal pins
automatically without program processing. If the 32 kHz oscillator clock is designated as the LCD clock
source, LCD display is also possible in watch mode in which the system clock stops.
136
HD404889/HD404899/HD404878/HD404868 Series
VCC
Internal LCD power supply switch
V0
V1
V2
V3
LCD display
control register
(LCR)
COM1
COM2
COM3
COM4
Common
signal
output
circuit
Port mode
register 4
(PMR4)
Pin control
4
Display
control
SEG1 to SEG4
SEG5 to SEG8
2
2
Dual-port
display RAM
(32 digits)
Display data
32
Duty selection
Segment
signal
output
circuit
SEG9 to SEG12
SEG13 to SEG16
SEG17 to SEG32
Clock
Selector
2
LCD display
mode register
(LMR)
Data bus
Clock line
Signal line
LCD input clocks
Note:
Pin function switching circuit
Figure 86-1 LCD Circuit Block Diagram (HD404889/HD404899/HD404878 Series)
137
HD404889/HD404899/HD404878/HD404868 Series
VCC
Internal LCD power supply switch
V1
V2
V3
LCD display
control register
(LCR)
COM1
Common
signal
COM2
output
COM3
circuit
Port mode
register 4
(PMR4)
COM4
Pin control
4
Display
control
SEG1 to SEG4
SEG5 to SEG8
2
2
Dual-port
display RAM
(24 digits)
Display data
24
Duty selection
Segment
signal
output
circuit
SEG9 to SEG12
SEG13 to SEG16
SEG17 to SEG24
Clock
Selector
2
LCD display
mode register
(LMR)
Data bus
Clock line
Signal line
LCD input clocks
Note:
Pin function switching circuit
Figure 86-2 LCD Circuit Block Diagram (HD404868 Series)
138
HD404889/HD404899/HD404878/HD404868 Series
LCD data area and segment data: $050 to $06F (HD404889/HD404899/HD404878 Series)
$050 to $067 (HD404868 Series)
Figures 87-1 and 87-2 show the LCD RAM area configuration. Each bit of the storage area corresponds to
one of four duties. When data is written to the area corresponding to a particular duty, it is automatically
output to the segment as display data.
bit3
bit2
bit1
bit0
bit3
bit2
bit1
bit0
$050
$051
$052
$053
$054
$055
$056
$057
$058
$059
$05A
$05B
$05C
$05D
$05E
$05F
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
$060
$061
$062
$063
$064
$065
$066
$067
$068
$069
$06A
$06B
$06C
$06D
$06E
$06F
SEG17 SEG17 SEG17 SEG17
SEG18 SEG18 SEG18 SEG18
SEG19 SEG19 SEG19 SEG19
SEG20 SEG20 SEG20 SEG20
SEG21 SEG21 SEG21 SEG21
SEG22 SEG22 SEG22 SEG22
SEG23 SEG23 SEG23 SEG23
SEG24 SEG24 SEG24 SEG24
SEG25 SEG25 SEG25 SEG25
SEG26 SEG26 SEG26 SEG26
SEG27 SEG27 SEG27 SEG27
SEG28 SEG28 SEG28 SEG28
SEG29 SEG29 SEG29 SEG29
SEG30 SEG30 SEG30 SEG30
SEG31 SEG31 SEG31 SEG31
SEG32 SEG32 SEG32 SEG32
SEG10 SEG10 SEG10 SEG10
SEG11 SEG11 SEG11 SEG11
SEG12 SEG12 SEG12 SEG12
SEG13 SEG13 SEG13 SEG13
SEG14 SEG14 SEG14 SEG14
SEG15 SEG15 SEG15 SEG15
SEG16 SEG16 SEG16 SEG16
COM4
COM3
COM2
COM1
COM4
COM3
COM2
COM1
Figure 87-1 LCD RAM Area Configuration (Using Dual-Port RAM)
(HD404889/HD404899/HD404878 Series)
bit3
bit2
bit1
bit0
bit3
bit2
bit1
bit0
$050
$051
$052
$053
$054
$055
$056
$057
$058
$059
$05A
$05B
$05C
$05D
$05E
$05F
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
$060
$061
$062
$063
$064
$065
$066
$067
SEG17 SEG17 SEG17 SEG17
SEG18 SEG18 SEG18 SEG18
SEG19 SEG19 SEG19 SEG19
SEG20 SEG20 SEG20 SEG20
SEG21 SEG21 SEG21 SEG21
SEG22 SEG22 SEG22 SEG22
SEG23 SEG23 SEG23 SEG23
SEG24 SEG24 SEG24 SEG24
COM4
COM3
COM2
COM1
SEG10 SEG10 SEG10 SEG10
SEG11 SEG11 SEG11 SEG11
SEG12 SEG12 SEG12 SEG12
SEG13 SEG13 SEG13 SEG13
SEG14 SEG14 SEG14 SEG14
SEG15 SEG15 SEG15 SEG15
SEG16 SEG16 SEG16 SEG16
COM4
COM3
COM2
COM1
Figure 87-2 LCD RAM Area Configuration (Using Dual-Port RAM) (HD404868 Series)
139
HD404889/HD404899/HD404878/HD404868 Series
LCD control register (LCR: $02C):
The LCD control register is a 4-bit write-only register that controls LCD blanking, the on/off state of the
LCD power switch, display in watch mode and subactive mode, and disconnection of the LCD power
supply dividing resistor, as shown in figure 88.
Individual bit in this register can be set and reset by bit manipulation instructions.
•
Display on/off control
Off: Segment signals are in the off state, regardless of LCD RAM data.
On: LCD RAM data is output as segment signals.
Built-in power switch on/off control
•
Off: The built-in LCD power switch is off.
On: The built-in LCD power switch is on. If V0 and V1 are shorted externally, V1 goes to the VCC
level.
•
•
LCD display in watch mode and subactive mode
Off: In watch mode and subactive mode, all common and segment pins are fixed at GND potential.
The built-in LCD power switch is off.
On: In watch mode and subactive mode, LCD RAM data is output as segment signals.
LCD power supply dividing resistor switch on/off control
Off: The built-in LCD power supply dividing resistor is disconnected.
On: The built-in LCD power supply dividing resistor is connected.
140
HD404889/HD404899/HD404878/HD404868 Series
LCD control register (LCR: $02C)
3
2
W
1
W
0
W
Bit
W
0
Read/Write
Initial value on reset
Bit name
0
0
0
LCR3
LCR2
LCR1
LCR0
LCD on/off control
LCR0
Off
On
0
1
Built-in LCD power switch on/off control
LCR1
Off
On
0
1
Watch mode/subactive mode LCD display
LCR2
Off
On
0
1
LCR3 LCD power supply dividing resistor
On
Off
0
1
Figure 88 LCD Control Register (LCR)
141
HD404889/HD404899/HD404878/HD404868 Series
LCD duty/clock control register (LMR: $02D):
The LCD duty/clock control register is a 4-bit write-only register used to set four kinds of display duty ratio
and LCD reference clock (figure 89). Table 27 shows the LCD frame frequencies for each duty setting.
LCD duty/clock control register (LMR: $02D)
Bit
3
W
0
2
W
0
1
W
0
0
W
0
Read/Write
Initial value on reset
Bit name
LMR3 LMR2 LMR1 LMR0
Duty factor
LMR1 LMR0
1/4
1/3
1/2
0
0
1
0
1
1 (static drive)
1
LCD circuit clock
CL0=32.768kHz Duty/128
LMR3 LMR2
×
0
0
CL1=32.768kHz Duty/256
×
1
CL2=øPER Duty/256
×
0
1
ø
When TMA3 = 0, CL3 = PER × Duty/2048
1
When TMA3 = 1, CL3 = 32.768 kHz × Duty/512
Figure 89 LCD Duty/Clock Control Register (LMR)
142
HD404889/HD404899/HD404878/HD404868 Series
Table 27
LCD Frame Frequencies for Each Duty Setting
Frame Period
fosc=800kHz fosc=2.0MHz
Division Division Division Division Division Division Division Division
Duty LMR3 LMR2
fosc=400kHz
fosc=4.0MHz
by 4
by 32
by 4
by 32
by 4
by 32
by 4
by 32
0
0
1
0
1
CL0 256Hz
CL1 128Hz
Static
CL2 390.6Hz 48.8Hz 781.3Hz 97.7Hz 1953Hz 244.1Hz 3906Hz 488.3Hz
1
0
CL3* 48.8Hz 6.1Hz
64Hz
97.7Hz 12.2Hz 244.1Hz 30.5Hz 488.3Hz 61.0Hz
0
1
0
1
CL0 128Hz
CL1 64Hz
1/2
CL2 195.3Hz 24.4Hz 390.6Hz 48.8Hz 976.6Hz 122.1Hz 1953Hz 244.1Hz
1
0
CL3* 24.4Hz 3.1Hz
32Hz
48.8Hz 6.1Hz
122.1Hz 15.3Hz 244.1Hz 30.5Hz
0
1
0
1
CL0 85.3Hz
CL1 42.7Hz
1/3
CL2 130.1Hz 16.3Hz 260.2Hz 32.5Hz 650Hz
81.3Hz 1301Hz 162.6Hz
1
0
CL3* 16.3Hz 2.0Hz
21.3Hz
32.5Hz 4.1Hz
81.3Hz 10.2Hz 162.6Hz 20.3Hz
0
1
0
1
CL0 64Hz
CL1 32Hz
1/4
CL2 97.7HZ 12.2Hz 195.3Hz 24.4Hz 488.3Hz 61.0Hz 976.6Hz 122.1Hz
1
CL3* 12.2Hz 1.5Hz
16Hz
24.4Hz 3.1Hz
61.0Hz 7.6Hz
122.1Hz 15.3Hz
143
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 4 (PMR4: $00C):
Port mode register 4 (PMR4) is a 4-bit write-only register that enables the R3 to R6 port pins to be
switched to SEG1 to SEG16 pin functions in 4-port units (figure 90).
Port mode register 4 (PMR4: $00C)
Bit
3
W
0
2
W
0
1
W
0
0
W
0
Read/Write
Initial value on reset
Bit name
PMR43 PMR42 PMR41 PMR40
R3/SEG1 to SEG4 pin mode selection
PMR40
0
R3
1*
SEG1–4
R4/SEG5 to SEG8 pin mode selection
PMR41
0
R4
1*
SEG5–8
R5/SEG9 to SEG12 pin mode selection
PMR42
0
R5
1*
SEG9–12
R6/SEG13 to SEG16 pin mode selection
PMR43
0
R6
1*
SEG13–16
Note: * When use as a segment output pin, write its port data resister (PDR) to "0"
Figure 90 Port Mode Register 4 (PMR4: $00C)
144
HD404889/HD404899/HD404878/HD404868 Series
LCD drive voltage (VLCD):
Example of LCD drive power supply wiring are shown in figures 91-1 and 91-2. The LCD drive voltage
(VLCD) should be within the following range.
2.2≤VLCD≤VCC (V)
If the LCD drive voltage is applied from off-chip, connect the V0 pin to VCC and turn the LCD power
switch (LCD control register) off. (HD404889/HD404899/HD404878 Series)
When the power supply voltage is used as the LCD drive voltage, the V0 and V1 pins should be shorted.
(HD404889/HD404899/HD404878 Series)
1
V
CC
4-digit LCD
COM1
V
V0
1
V
V
V
V
CC
V2
SEG1
to
SEG32
V3
GND
32
Static drive (power supply voltage used for VLCD
)
2
V
CC
8-digit LCD
COM1
COM2
V
V0
1
CC
CC
CC
V2
SEG1
to
V3
GND
SEG32
32
1/2 duty, 1/2 bias drive (power supply voltage used for VLCD
)
3
COM1
to
V
CC
10-digit signed LCD
V
V0
1
COM3
SEG1
to
V
2
V
LCD
V3
GND
SEG32
32
1/3 duty, 1/3 bias drive (external power supply used for VLCD
)
4
COM1
V
CC
16-digit LCD
to
COM4
SEG1
to
V
V0
1
V2
VLCD
V3
GND
SEG32
32
1/4 duty, 1/3 bias drive (external power supply used for VLCD
)
Figure 91-1 Examples of LCD Wiring (HD404889/HD404899/HD404878 Series)
145
HD404889/HD404899/HD404878/HD404868 Series
1
VCC
3-digit LCD
COM1
V1
V2
VCC
SEG1
to
SEG24
V3
GND
24
Static drive (power supply voltage used for VLCD)
2
VCC
6-digit LCD
COM1
COM2
V1
V2
V3
VCC
VCC
VCC
SEG1
to
GND
SEG24
24
1/2 duty, 1/2 bias drive (power supply voltage used for VLCD)
3
COM1
to
COM3
VCC
8-digit LCD
V1
V2
V3
VLCD
SEG1
to
SEG24
GND
24
1/3 duty, 1/3 bias drive (external power supply used for VLCD)
4
COM1
VCC
12-digit LCD
to
COM4
SEG1
to
V1
V2
V3
VLCD
GND
SEG24
24
1/4 duty, 1/3 bias drive (external power supply used for VLCD)
Figure 91-2 Examples of LCD Wiring (HD404868 Series)
Large LCD panel drive:
If the capacitance of the driven LCD is large, the value of the divided resistance should be reduced by
dividing the resistance in parallel with the built-in divided resistor (see figures 92-1 and 92-2).
As an LCD has a matrix structure, the path of the charge/discharge current flowing to the load capacitance
is complicated. Moreover, the current varies depending on the illumination state, so that it is not possible
to determine the resistance values simply from the LCD load capacitance. The resistance values must
therefore be determined experimentally in accordance with the power consumption requirement of the
equipment, including the LCD. (Adding capacitors C with a value of 0.1 to 0.3 µF is also effective).
A value of 1 kΩ to 10 kΩ is normally set for R.
146
HD404889/HD404899/HD404878/HD404868 Series
V0(VCC
V1
)
V0(VCC
)
V1
R
R
R
R
R
R
V2
V2
V3
C
C
V3
C
GND
GND
Figure 92-1 Large LCD Panel Drive (Using Power Supply Voltage for VLCD
)
(HD404889/HD404899/HD404878 Series)
V1
V1
R
R
R
R
R
R
V2
V2
V3
C
C
V3
C
GND
GND
Figure 92-2 Large LCD Panel Drive (Using Power Supply Voltage for VLCD) (HD404868 Series)
Usage Notes
When R30/SEG1 to R60/SEG16 pins are used as segment output pins, write their port data register (PDR) to
“0”.
147
HD404889/HD404899/HD404878/HD404868 Series
Buzzer Output Circuit
Buzzer Output Circuit Functions: The buzzer output circuit has the following functions.
•
•
Timer overflow toggle output
System clock divided clock pulse output
The block diagram of the buzzer output circuit is shown in figure 93.
Buzzer Output Circuit Operation
•
Timer overflow toggle output operation
The timer overflow toggle output operation setting is made by bits 1 and 2 of the buzzer mode register
(BMR) and bit 2 of port mode register 2 (PMR2). By clearing bit 2 of the buzzer mode register (BMR)
to 0, selecting timer B or timer C overflow by bit 1, and setting bit 2 of port mode register 2 (PMR2) to
1, a toggle waveform is output from the BUZZ pin with overflow as the trigger.
•
System clock divided clock pulse output
The system clock divided clock pulse output operation setting is made by bits 0 to 3 of the buzzer mode
register (BMR) and bit 2 of port mode register 2 (PMR2). Bit 2 of the buzzer mode register (BMR) is
set to 1, the system clock division ratio is selected by bits 0 and 1, and bit 2 of port mode register 2
(PMR2) is set to 1. Clock pulses are output by setting bit 3 of the buzzer mode register (BMR) to 1. If
bit 3 of the buzzer mode register (BMR) is cleared to 0, the BUZZ pin goes low.
The clock pulse width is fixed without regard to the timing set by bit 3 of the buzzer mode register
(BMR), and careful coordination with software is necessary with regard to the number of output pulses.
After a clock pulse modification is made, clock pulses should not be output until 4tcyc after the
modifying instruction.
Only a bit manipulation instruction can be used on bit 3 of the buzzer mode register (BMR).
Buzzer Output Circuit Registers
Buzzer output circuit operation setting is performed by the following registers.
Buzzer mode register (BMR: $02E)
Port mode register 2 (PMR2: $00A)
Buzzer mode register (BMR: $02E):
The buzzer mode register (BMR) is a 4-bit write-only register used to set toggle output by timer overflow
and system clock divided clock pulse output as shown in figure 94.
Bit 3 of the buzzer mode register (BMR) can only accessed by a bit manipulation instruction.
The buzzer mode register (BMR) is reset to $0 by an MCU reset.
148
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 2 (PMR2: $00A):
Port mode register 2 (PMR2) is a 4-bit write-only register used to switch the R12/BUZZ pin function as
shown in figure 30.
Port mode register 2 (PMR2) is reset to $0 by an MCU reset.
BUZZ
Timer B
overflow
1/2
(toggle)
Timer C
overflow
øPER
1/2
1/3
1/4
Synchro-
nization
circuit
Buzzer
mode
register
Data bus
Clock line
Signal line
Figure 93 Buzzer Output Circuit
149
HD404889/HD404899/HD404878/HD404868 Series
Buzzer mode register (BMR: $02E)
3
W
2
W
0
1
W
0
0
W
0
Bit
Read/Write
Initial value on reset
Bit name
0
BMR3
BMR2 BMR1 BMR0
BMR2 BMR1 BMR0
BUZZ pin output
Division by
0
*
2 of timer B overflow
0
1
Division by
1
0
1
*
2 of timer C overflow
0
øPER clock
1
0
øPER/2clock
øPER/3clock
øPER/4clock
1
*
: Don't care
Clock output control (enabled when BMR2 = 1, bit manipulation instruction)
0
1
Stopped (low level)
Output
Figure 94 Buzzer Mode Register (BMR)
150
HD404889/HD404899/HD404878/HD404868 Series
ZTATTM Microcomputer with Built-in Programmable ROM
1. Precautions for use of ZTATTM microcomputer with built-in programmable ROM
(1) Precautions for writing to programmable ROM built in ZTATTM microcomputer
In the ZTATTM microcomputer with built-in plastic mold one-time programmable ROM, incomplete
electrical connection between the PROM writer and socket adapter causes writing errors and, makes the
computer unoperatable. To enhance the writing efficiency, attention should be paid to the following points:
(a) Make sure that the socket adapter is firmly fixed to the PROM writer and connected electrically with
each other (neither opened nor shorted), before starting the writing process.
(b) To secure the electrical connection between the contact pin and IC lead, make sure that there is no
foreign substance on the contact pin of the socket adapter, which may cause improper electrical
connection.
(c) When inserting the IC, be careful to protect the IC lead from bending in order to secure the electrical
connection between the contact pin and IC lead. If the lead is bent, correct the bending and insert it
again.
(d) If any trouble is noticed during a blank check to be performed to prevent erroneous writing due to
improper electrical connection, carry out the writing process again according to above steps (a), (b), and
(c).
(e) During the writing process, do not touch the socket adapter and IC to prevent erroneous writing.
(f) To write continuously in the IC, follow steps (a), (b), (c), (d) and (e).
(g) If a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the PROM
writer, socket adapter, etc. for defects.
(h) If any problem is noticed in the written program or in the program after being left at a high temperature,
consult our technical staff.
(2) Precautions when new PROM writer, socket adapter or IC is used
When a new PROM writer, socket adapter or IC is employed, breakdown of the IC may occur or its writing
may become impossible because the noise, overshoot, timing or other electrical characteristics may be
inconsistent with the assured IC writing characteristics. To avoid such troubles, check the following points
before starting the writing process.
(a) To ensure stable writing operation, check that the VCC of the power supplied to the PROM writer,
power source current capacity of VPP, and current consumption at the time of writing to IC are provided
with sufficient margin.
(b) To prevent breakdown of the IC, check that the power source voltage between GND-VCC and GND-
VPP, and overshoot or undershoot of the power source at the connecting terminal of the socket adapter
are within the ratings. Particularly, if the overshoot or undershoot exceeds the maximum rating, the p-n
connection may be damaged, leading to permanent breakdown. If overshoot or undershoot occurs,
recheck the power source damping resistance of capacity.
(c) To prevent breakdown of the IC and for stable writing and reading operation, insert the IC into the
socket adapter and check the power noise between the GND-VCC and GND-VPP near the IC connecting
151
HD404889/HD404899/HD404878/HD404868 Series
terminal. If power source noise is noticed, insert an appropriate capacitor between the GND power
sources depending on the noise generated. In case of high frequency noise , insert a capacitor of low
inductance.
(d) For stable writing and reading operation, insert the IC into the socket adapter and check the input
waveform, timing and noise near the R/W, CS, address and data terminals. Particularly, since recent
ICs have increased in speed, caution should be exercised against the noise to the power source or
address due to crosstalk from the output data terminal. To avoid these problems, inserting a low
inductance capacitor between the GND and power source or inserting a damping resistance to the output
data terminal is effective.
(e) Particularly, when a multiple PROM writer is used, perform above items (a), (b), (c), and (d) assuming
all ICs inserted into the socket adapter.
(f) In the case of a multiple PROM writer, when an unacceptable result is noticed during a blank check
performed to prevent erroneous writing due to improper electrical connection of the power source, etc.,
rewriting is impossible unless every writing process can be stopped. Therefore, the potential increases
due to erroneous writing because of improper connection. Be sure to check the electrical connection
between the PROM writer and socket adapter and IC.
(g) If any abnormality is noticed while checking a written program, consult our technical staff.
2. Programming of Built-in programmable ROM
The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM.
PROM mode is set by driving the RESET, M0, and M1 pins low (or by driving the RESET and M0 pins low
in the HD4074869), and driving the TEST pin to the VPP level.
Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256.
Using a socket adapter for specific use of each product, programming is possible with a general-purpose
PROM writer.
Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the
general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits
to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to
write to a 16kword of built-in PROM writer with a general-purpose PROM, specify 32kbyte address
($0000-$7FFF). An example of PROM memory map is shown in figure 95.
Notes:
1. When programming with a PROM writer, set up each ROM size to the address given in table 30. If it is
programmed erroneously to an address given in table 30 or later, check of writing of PROM may
become impossible. Particularly, caution should be exercised in the case of a plastic package since
reprogramming is impossible with it. Set the data in unused addresses to $FF.
2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the
product may break down due to overcurrent. Be sure to check that they are properly set to the writer
before starting the writing process.
152
HD404889/HD404899/HD404878/HD404868 Series
3. Two levels of program voltages (VPP) are available for the PROM: 12.5V and 21V. Our product
employs a VPP of 12.5V. If a voltage of 21V is applied, permanent breakdown of the product will
result. The VPP of 12.5V is obtained for the PROM writer by setting it according to the Intel 27258
specifications.
Table 28
Socket Adapters
Package
FP-80A
TFP-80C
FP-64A
DP-64S
Model Name
Manufacturer
Please ask Hitachi service section.
Please ask Hitachi service section.
Please ask Hitachi service section.
Please ask Hitachi service section.
Writing/verification
Programming of the built-in program ROM employs a high speed programming method. With this method,
high speed writing is effected without voltage stress to the device or without damaging the reliability of the
written data.
A basic programming flow chart is shown in figure 96 and a timing chart in figure 97.
For precautions for PROM writing procedure, refer to Section 2, "Characteristics of ZTATTM
Microcomputer's Built-in Programmable ROM and precautions for its Applications."
Table 29
Selection of Mode
Mode
CE
OE
VPP
VPP
VPP
VPP
O0 to O4
Writing
“Low”
“High”
“High”
“Low”
“High”
Data input
Verification
Data output
High impedance
Prohibition of programming “High”
Table 30
PROM Writer Program Address
ROM size
8k
Address
$0000~$3FFF
$0000~$5FFF
$0000~$7FFF
12k
16k
153
HD404889/HD404899/HD404878/HD404868 Series
Programmable Rom (HD4074889, HD4074899, HD4074869)
The HD4074889, HD4074899, and HD4074869 are a ZTATTM microcomputers with built-in PROM that
can be programmed in PROM mode.
PROM Mode Pin Description
HD4074889, HD4074899
Pin No.
MCU Mode
Pin Name
PROM Mode
Pin Name
Pin No.
MCU Mode
Pin Name
PROM Mode
Pin Name
FP-80A
I/O
I/O
FP-80A
I/O
I/O
TFP-80C
TFP-80C
1
AVCC
—
VCC
VCC
VCC
—
—
—
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
R30/SEG1
R31/SEG2
R32/SEG3
R33/SEG4
R40/SEG5
R41/SEG6
R42/SEG7
R43/SEG8
R50/SEG9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A1
A2
A3
A4
O0
O1
O2
O3
O4
O4
O3
O2
O1
O0
I
2
R70/AN0
R71/AN1
R72/AN2
R73/AN3
R80/AN4
R81/AN5
AVSS
I/O
I/O
I/O
I/O
I/O
I/O
—
I
3
I
4
I
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
7
8
GND
VPP
—
—
—
9
TEST
OSC1
OSC2
GND
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I
VCC
R51/SEG10 I/O
R52/SEG11 I/O
R53/SEG12 I/O
R60/SEG13 I/O
R61/SEG14 I/O
R62/SEG15 I/O
R63/SEG16 I/O
O
—
GND
—
X2
O
X1
I
GND
RESET
VCC
—
I
RESET
VCC
I
—
—
I
D0/INT0
D1/INT1
D2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A0
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
COM1
COM2
COM3
COM4
V3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
—
—
A5
I
D3
A6
I
D4
A7
I
D5
A8
I
D6
A9
I
D7
A10
A11
A12
A13
A14
VCC
I
D8
I
D9
I
D10
I
D11
I
R00/WU0
R01/WU1
R02/WU2
R03/WU3
R10/EVNB
R11/EVND
R12/BUZZ
R13/TOB
R20/TOC
R21/SCK
R22/SI/SO
R23
—
M0
M1
CE
I
I
I
OE
XM0
I
V2
O
O
V1
VCC
VCC
—
—
XM1
V0
154
HD404889/HD404899/HD404878/HD404868 Series
HD4074869
Pin No.
MCU Mode
PROM Mode
Pin Name
VCC
Pin No.
MCU Mode
PROM Mode
FP-64A DP-64S Pin Name
I/O
I/O
I/O
I/O
I/O
I
I/O
—
FP-64A DP-64S Pin Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin Name
A14
A1
I/O
I
1
8
R70/AN0
R71/AN1
R72/AN2
R73/AN3
TEST
OSC1
OSC2
GND
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
R23
2
9
VCC
—
R30/SEG1
R31/SEG2
R32/SEG3
R33/SEG4
R40/SEG5
R41/SEG6
R42/SEG7
R43/SEG8
R50/SEG9
I
3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
A2
I
4
A3
I
5
VPP
VCC
—
—
A4
I
6
I
O0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
O
O1
8
—
GND
—
O2
9
X2
O
O3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
X1
I
GND
RESET
VCC
—
I
O4
RESET
VCC
I
R51/SEG10 I/O
R52/SEG11 I/O
R53/SEG12 I/O
R60/SEG13 I/O
R61/SEG14 I/O
R62/SEG15 I/O
R63/SEG16 I/O
O4
—
—
I
O3
D0/INT0
D1/INT1
D2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A0
O2
O1
A5
I
O0
D3
A6
I
D4
A7
I
D5
A8
I
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
COM1
COM2
COM3
COM4
V3
O
O
O
O
O
O
O
O
O
O
O
O
—
—
—
D6
A9
I
D7
A10
A11
A12
VCC
I
D8
I
D9
I
R00/WU0
R01/WU1
R02/WU2
R10/EVNB
R11
—
A13
I
2
R12/BUZZ
R13/TOB
R20/TOC
R21/SCKN
R22/SI/SO
M0
CE
XM1
I
3
I
4
O
I
5
OE
XM0
6
V2
O
7
V1
VCC
—
Notes: 1. I/O: I/O pin, I: Input-only pin, O: Output-only pin
2. As there are two each of pins O0 to O4, the respective pairs should be shorted.
3. Unused data pins (O5 to O7) on the PROM programmer side should be handled as shown below
on the socket.
VCC
O5, O6, O7
4. Pin A9 should be handled as shown below on the socket.
VCC
A9
Writer side
HD4074889
HD4074899
HD4074869
155
HD404889/HD404899/HD404878/HD404868 Series
2. Pin Functions in PROM Mode
VPP:
Applies the on-chip PROM programming voltage (12.5 V ±0.3 V).
CE:
Inputs a control signal to set the on-chip PROM to the write/verify enabled state.
OE:
Inputs a data output control signal during verification.
A0 to A14:
On-chip PROM address input pins.
O0 to O4:
On-chip PROM data bus I/O pins.
As there are two each of pins O0 to O4, the respective pairs should be shorted.
M0, M1, RESET, TEST:
PROM mode setting pins. PROM mode is set by driving the M0, M1, and RESET pins low (or by driving
the M0, and RESET pins low in the HD4074869), and driving the TEST pin to the VPP level.
Other pins:
VCC, AVCC, R70/AN0, R71/AN1, OSC1, V0, and V1 should be connected to VCC potential.
GND, AVSS, and X1 should be connected to GND potential.
Other pins should be left open.
156
HD404889/HD404899/HD404878/HD404868 Series
$0000
$0000
1
1
1
1
1
1
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Lower 5 bits
Bit 8 Bit 7 Bit 6 Bit 5 Upper 5 bits
JMPL instruction
(jump to RESET routine)
JMPL instruction
$0000
$0001
$0002
$0003
Bit 9
$0001
.
.
.
Vector address
(jump to WU0 to WU
3
$000F
$0010
$001F
$0020
JMPL instruction
$0004
$0005
$0006
(jump to INT
0 routine)
.
.
.
Zero-page subroutine
(64 words)
JMPL instruction
(jump to INT1 routine)
JMPL instruction
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$003F
$0040
$007F
$0080
.
.
.
(jump to timer A routine)
Pattern
(4,096 words)
JMPL instruction
(jump to timer B, timer D routine)
JMPL instruction
(jump to timer C routine)
JMPL instruction
(jump to A/D, serial routine)
$0FFF
$1000
$1FFF
$2000
Program
(16,384 words)
$3FFF
$7FFF
Upper three bits are not to be used
(fill them with 111)
Figure 95 Memory Map in PROM Mode
157
HD404889/HD404899/HD404878/HD404868 Series
Start
Set Prog./Verify Mode
VPP=12.5±0.3V, VCC=6.0±0.25V
Address=0
n=0
Yes
n+1→n
No
Program tPW = 1ms±5%
n<S
S=25
NoGo
Verify
Go
Program tOPW = 3nms
Address + 1→Address
No
Last
Address?
Yes
Set Read Mode
VCC=5.0±0.5V, VPP=VCC±0.6V
Read
NoGo
All Address
Go
Fail
End
Figure 96 Flowchart of High-Speed Programming
158
HD404889/HD404899/HD404878/HD404868 Series
Programming Electrical Characteristics
DC Characteristics (VCC = 6V ±0.25V, VPP = 12.5V ±0.3V, VSS = 0V, Ta = 25°C ±5°C, unless
otherwise specified)
Item
Symbol Test Conditions min
typ
max
Unit
Input high voltage
O0 to O4,A0 to A14, VIH
2.2
—
VCC+0.3 V
OE, CE
Input low voltage
O0 to O4,A0 to A14, VIL
–0.3
—
0.8
V
OE, CE
Output high voltage
Output low voltage
O0 to O4
O0 to O4
VOH
VOL
IOH=–200µA
IOL=1.6mA
2.4
—
—
—
—
—
0.4
2
V
V
Input leakage current O0 to O4,A0 to A14, IIL
Vin=5.25V/0.5V
—
µA
OE, CE
VCC current
VPP current
ICC
IPP
—
—
—
—
30
40
mA
mA
AC Characteristics (VCC = 6V ±0.25V, VPP = 12.5V ±0.3V, Ta = 25°C ±5°C, unless otherwise
specified)
Item
Symbol Test Conditions min
typ
—
—
—
—
—
—
—
1.0
—
—
—
max
—
Unit
µs
Address setup time
OE setup time
tAS
2
tOES
tDS
tAH
tDH
tDF
2
—
µs
Data setup time
Address hold time
Data hold time
2
—
µs
0
—
µs
2
—
µs
Data output disable time
VPP setup time
See figure 89
—
2
130
—
ns
tVPS
tPW
µs
Program pulse width
0.95
2.85
2
1.05
ms
CE pulse width during overprogramming tOPW
78.75 ms
VCC setup time
tVCS
tOE
—
µs
Data output delay time
0
500
ns
Notes: Input pulse level: 0.8 V to 2.2 V
Input rise/fall times: ≤ 20ns
Input timing reference levels: 1.0 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
159
HD404889/HD404899/HD404878/HD404868 Series
Write
Verify
Address
tAH
tAS
Data
VPP
Data In Stable
Data Out Valid
tDF
tDS
tDH
VPP
VCC
tVPS
VCC
GND
VCC
tVCS
CE
tPW
tOES
tOE
OE
tOPW
Figure 97 PROM Write/Verify Timing
160
HD404889/HD404899/HD404878/HD404868 Series
Notes on PROM Programming
Principles of Programming/Erasure: A memory cell in a ZTAT™ microcomputer is the same as an
EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot
electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an
SiO film. The change in threshold voltage of a memory cell with a charged floating gate makes the
2
corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 98).
The charge in a memory cell may decrease with time. This decrease is usually due to one of the following
causes:
•
Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure
principle.
•
•
Heat excites trapped electrons, allowing them to escape.
High voltages between the control gate and drain may erase electrons.
If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However,
electron erasure does not often occur because defective devices are detected and removed at the testing
stage.
Control gate
Control gate
SiO2
Source
SiO2
Source
Floating gate
Drain
Floating gate
Drain
+
+
+
+
N
N
N
N
Write (0)
Erasure (1)
Figure 98 Cross-Sections of a PROM Cell
PROM Programming: PROM memory cells must be programmed under specific voltage and timing
conditions. The higher the programming voltage V and the longer the programming pulse t is applied,
PP
PW
the more electrons are injected into the floating gates. However, if V exceeds specifications, the pn
PP
junctions may be permanently damaged. Pay particular attention to overshooting in the PROM
programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may
reduce breakdown voltages.
The ZTAT™ microcomputer is electrically connected to the PROM programmer by a socket adapter.
Therefore, note the following points:
•
•
Check that the socket adapter is firmly mounted on the PROM programmer.
Do not touch the socket adapter or the LSI during the programming. Touching them may affect the
quality of the contacts, which will cause programming errors.
161
HD404889/HD404899/HD404878/HD404868 Series
PROM Reliability after Programming: In general, semiconductor devices retain their reliability,
provided that some initial defects can be excluded. These initial defects can be detected and rejected by
screening. Baking devices under high-temperature conditions is one method of screening that can rapidly
eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure
section.)
ZTAT™ microcomputer devices are extremely reliable because they have been subjected to such a
screening method during the wafer fabrication process, but Hitachi recommends that each device be
exposed to 150°C at one atmosphere for at least 48 hours after it is programmed, to ensure its best
performance. The recommended screening procedure is shown in figure 99.
Note: If programming errors occur continuously during PROM programming, suspend programming and
check for problems in the PROM programmer or socket adapter. If programming verification
indicates errors in programming or after high-temperature exposure, please inform Hitachi.
Programming, verification
Exposure to high temperature, without power
+8 h
–0 h
*
150°C ± 10°C, 48 h
Program read check
VCC = 4.5 V or 5.5 V
Note: Exposure time is measured from when the temperature in the heater reaches 150°C.
Figure 99 Recommended Screening Procedure
162
HD404889/HD404899/HD404878/HD404868 Series
Addressing Modes
RAM Addressing Modes
The MCU has three RAM addressing modes, as shown in figure 100 and described below.
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from
$040 to $04F, are accessed with the LAMR and XMRA instructions.
W register
W1 W0
X register
Y register
Y
Y
Y
1
Y0
X3 X2 X1 X0
3
2
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Indirect Addressing
1st word of Instruction
Opcode
2nd word of Instruction
d3 d2 d1 d0
d 9 d8
d7 d6 d5 d4
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction
Opcode
m3 m2 m1 m0
0
0
0
1
0
0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 100 RAM Addressing Modes
163
HD404889/HD404899/HD404878/HD404868 Series
ROM Addressing Modes and the P Instruction
The MCU has four ROM addressing modes, as shown in figure 101 and described below.
Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC –PC ) with 14-bit immediate data.
13
0
Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC –PC ) with eight-bit immediate data. If the BR instruction
7
0
is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 103. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.
Note that the HMCS400-series cross assembler has an automatic paging feature for ROM pages.
Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000–
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC –PC ), and 0s are placed in the eight high-
5
0
order bits (PC –PC ).
13
6
Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.
P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 102. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If
both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.
The P instruction has no effect on the program counter.
164
HD404889/HD404899/HD404878/HD404868 Series
1st word of instruction
2nd word of instruction
d3 d2
[JMPL]
[BRL]
[CALL]
Opcode
d1 d0
p3 p2 p1 p0 d9 d8
d7 d6 d5 d4
Program counter
PC13PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Direct Addressing
Instruction
[BR]
b3 b2
b1 b0
Opcode
b7 b6 b5 b4
Program counter
PC
10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PC13PC12 PC11
Current Page Addressing
Instruction
d5 d 4
d3 d2 d1 d 0
[CAL]
Opcode
0
0
0
0
0
0
0
0
Program counter
PC2
PC1 PC0
PC13PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3
Zero Page Addressing
Instruction
Opcode
p3 p2 p1 p0
[TBR]
B register
B 3 B 2 B 1 B0
Accumulator
A3 A2 A1 A 0
0
0
Program counter PC13PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Table Data Addressing
Figure 101 ROM Addressing Modes
165
HD404889/HD404899/HD404878/HD404868 Series
Instruction
Opcode
p3 p2 p1 p0
[P]
B register
Accumulator
A3 A2 A1 A 0
B 3 B 2 B 1 B0
0
0
Referenced ROM address RA RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
13
Address Designation
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
A0
B3 B2 B1 B0 A 3 A 2 A1
Accumulator, B register
If RO8 = 1
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
R23 R22 R21 R20 R13 R12 R11 R10
Pattern Output
Output registers R1, R2
If RO9 = 1
Figure 102 P Instruction
256 (n – 1) + 255
BR
AAA
256n
AAA
NOP
BR
BR
AAA
BBB
256n + 254
256n + 255
256 (n + 1)
BBB
NOP
Figure 103 Branching when the Branch Destination is on a Page Boundary
166
HD404889/HD404899/HD404878/HD404868 Series
Instruction Set
The MCU Series has 101 instructions, classified into the following 10 groups:
•
•
•
•
•
•
•
•
•
•
Immediate instructions
Register-to-register instructions
RAM addressing instructions
RAM register instructions
Arithmetic instructions
Compare instructions
RAM bit manipulation instructions
ROM addressing instructions
Input/output instructions
Control instructions
The functions of these instructions are listed in tables 31 to 40, and an opcode map is shown in table 41.
Table 31
Immediate Instructions
Words/
Operation
Mnemonic
Operation Code
Function
i → A
Status Cycles
Load A from immediate LAI i
Load B from immediate LBI i
1
1
0
0
0
1
0
0
1
0
0
0
1
0
1
1
0
0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
1/1
1/1
2/2
i → B
Load memory from
immediate
LMID i,d
i → M
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Load memory from
LMIIY i
1
0
1
0
0
1
i3 i2 i1 i0
i → M, Y + 1 → Y NZ
1/1
immediate, increment Y
167
HD404889/HD404899/HD404878/HD404868 Series
Table 32
Register-Register Instructions
Words/
Operation
Mnemonic
LAB
Operation Code
Function
B → A
Status Cycles
Load A from B
Load B from A
Load A from W
0
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1/1
1/1
2/2*
LBA
A → B
LAW
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W → A
Load A from Y
LAY
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
Y → A
1/1
1/1
1/1
1/1
1/1
Load A from SPX
Load A from SPY
Load A from MR
Exchange MR and A
LASPX
LASPY
LAMR m
XMRA m
SPX → A
SPY → A
MR (m) → A
MR (m) ↔ A
m3 m2 m1 m0
m3 m2 m1 m0
Note:
The assembler automatically provides an operand for the second word of the LAW instruction.
Table 33
RAM Address Instructions
Words/
Status Cycles
Operation
Mnemonic
Operation Code
Function
i → W
Load W from immediate LWI i
Load X from immediate LXI i
Load Y from immediate LYI i
0
1
1
0
0
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
1/1
1/1
1/1
2/2*
i → X
i → Y
Load W from A
LWA
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
A → W
Load X from A
Load Y from A
Increment Y
LXA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
1
0
1
A → X
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
LYA
A → Y
IY
Y + 1 → Y
Y – 1 → Y
Y + A → Y
Y – A → Y
X ↔ SPX
Y ↔ SPY
X ↔ SPX,Y ↔ SPY
NZ
Decrement Y
DY
NB
Add A to Y
AYY
SYY
XSPX
XSPY
XSPXY
OVF
NB
Subtract A from Y
Exchange X and SPX
Exchange Y and SPY
Exchange X and SPX,
Y and SPY
Note: The assembler automatically provides an operand for the second word of the LWA instruction.
168
HD404889/HD404899/HD404878/HD404868 Series
Table 34
RAM Register Instructions
Words/
Operation
Mnemonic Operation Code
Function
Status Cycles
Load A from memory
LAM
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
M → A
1/1
LAMX
M → A
X ↔ SPX
LAMY
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
1
0
M → A
Y ↔ SPY
LAMXY
LAMD d
M → A
X ↔ SPX, Y ↔ SPY
Load A from memory
Load B from memory
M → A
2/2
1/1
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
LBM
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
M → B
LBMX
M → B
X ↔ SPX
LBMY
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
M → B
Y ↔ SPY
LBMXY
M → B
X ↔ SPX, Y ↔ SPY
Load memory from A
LMA
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
A → M
1/1
LMAX
A → M
X ↔ SPX
LMAY
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
0
1
0
A → M
Y ↔ SPY
LMAXY
LMAD d
A → M
X ↔ SPX, Y ↔ SPY
Load memory from A
A → M
2/2
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Load memory from A, LMAIY
increment Y
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
A → M, Y + 1 → Y
NZ
NB
1/1
LMAIYX
A → M, Y + 1 → Y
X ↔ SPX
Load memory from A, LMADY
decrement Y
A → M, Y – 1 → Y
1/1
LMADYX
A → M, Y – 1 → Y
X ↔ SPX
169
HD404889/HD404899/HD404878/HD404868 Series
Table 34
RAM Register Instructions (cont)
Words/
Operation
Mnemonic Operation Code
Function
Status Cycles
Exchange memory
and A
XMA
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
M ↔ A
1/1
XMAX
XMAY
XMAXY
XMAD d
XMB
M ↔ A
X ↔ SPX
M ↔ A
Y ↔ SPY
M ↔ A
X ↔ SPX, Y ↔ SPY
Exchange memory
and A
M ↔ A
2/2
1/1
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Exchange memory
and B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
M ↔ B
XMBX
XMBY
XMBXY
M ↔ B
X ↔ SPX
M ↔ B
Y ↔ SPY
M ↔ B
X ↔ SPX, Y ↔ SPY
170
HD404889/HD404899/HD404878/HD404868 Series
Table 35
Arithmetic Instructions
Words/
Operation
Mnemonic Operation Code
Function
A + i → A
B + 1 → B
B – 1 → B
Status Cycles
Add immediate to A
Increment B
AI i
IB
1
0
0
0
0
0
0
0
1
0
1
1
0
1
1
0
0
0
0
1
0
0
0
0
i3 i2 i1 i0
OVF
NZ
1/1
1/1
1/1
1/1
1
1
0
1
1
1
0
1
1
0
1
0
Decrement B
DB
DAA
NB
Decimal adjust for
addition
Decimal adjust for
subtraction
DAS
0
0
1
0
1
0
1
0
1
0
1/1
Negate A
NEGA
COMB
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
1
0
0
A + 1 → A
B → B
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
2/2
Complement B
Rotate right A with carry ROTR
Rotate left A with carry
Set carry
ROTL
SEC
REC
TC
1 → CA
0 → CA
Reset carry
Test carry
CA
Add A to memory
Add A to memory
AM
M + A → A
M + A → A
OVF
OVF
AMD d
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Add A to memory with
carry
AMC
0
0
0
0
0
1
1
0
0
0
M + A + CA → A
OVF → CA
OVF
OVF
NB
1/1
2/2
1/1
2/2
Add A to memory with
carry
AMCD d
0
1
0
0
0
1
1
0
0
0
M + A + CA → A
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 OVF → CA
Subtract A from memory SMC
with carry
0
0
1
0
0
1
1
0
0
0
M – A – CA → A
NB → CA
Subtract A from memory SMCD d
with carry
0
1
1
0
0
1
1
0
0
0
M – A – CA → A
NB
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 NB → CA
OR A and B
OR
0
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
0
0
0
0
0
A
B → A
1/1
1/1
2/2
AND memory with A
AND memory with A
ANM
A ∩ M → A
A ∩ M → A
NZ
NZ
ANMD d
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
OR memory with A
OR memory with A
ORM
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
A
A
M → A
M → A
NZ
NZ
1/1
2/2
ORMD d
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
EOR memory with A
EOR memory with A
EORM
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
A
A
M → A
M → A
NZ
NZ
1/1
2/2
EORMD d
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
171
HD404889/HD404899/HD404878/HD404868 Series
Table 36
Compare Instructions
Words/
Cycles
Operation
Mnemonic
Operation Code
Function
Status
Immediate not equal to
memory
INEM i
0
0
0
0
1
0
i3 i2 i1 i0
i ≠ M
NZ
1/1
Immediate not equal to
memory
INEMD i,d
0
1
0
0
1
0
i3 i2 i1 i0
i ≠ M
NZ
2/2
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
A not equal to memory
A not equal to memory
ANEM
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
A ≠ M
A ≠ M
NZ
NZ
1/1
2/2
ANEMD d
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
B not equal to memory
Y not equal to immediate
BNEM
YNEI i
ILEM i
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
1
0
1
0
0
B ≠ M
Y ≠ i
NZ
NZ
NB
1/1
1/1
1/1
i3 i2 i1 i0
i3 i2 i1 i0
Immediate less than or
equal to memory
i ≤ M
Immediate less than or
equal to memory
ILEMD i,d
ALEM
0
1
0
0
1
1
i3 i2 i1 i0
i ≤ M
NB
NB
NB
NB
NB
2/2
1/1
2/2
1/1
1/1
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
A less than or equal to
memory
0
0
0
0
0
1
0
1
0
0
A ≤ M
A ≤ M
B ≤ M
A ≤ i
A less than or equal to
memory
ALEMD d
BLEM
0
1
0
0
0
1
0
1
0
0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
B less than or equal to
memory
0
0
1
1
0
0
0 1 0 0
A less than or equal to
immediate
ALEI i
1
0
1
0
1
1
i3 i2 i1 i0
Table 37
RAM Bit Manipulation Instructions
Words/
Operation
Mnemonic Operation Code
Function
Status Cycles
Set memory bit
Set memory bit
SEM n
0
0
0
1
1
1
0
0
0
0
0
0
0
1
n1 n0 i → M (n)
1/1
2/2
SEMD n,d
0 1 n1 n0 i → M (n)
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Reset memory bit
Reset memory bit
REM n
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
n1 n0 0 → M (n)
n1 n0 0 → M (n)
1/1
2/2
REMD n,d
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Test memory bit
Test memory bit
TM n
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
n1 n0
n1 n0
M (n)
M (n)
1/1
2/2
TM n,d
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
172
HD404889/HD404899/HD404878/HD404868 Series
Table 38
ROM Address Instructions
Words/
Operation
Mnemonic Operation Code
Function
Status Cycles
Branch on status 1
BR b
1
0
1
1
b7 b6 b5 b4 b3 b2 b1 b0
0 1 1 1 p3 p2 p1 p0
1
1
1/1
2/2
Long branch on status 1 BRL u
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
p3 p2 p1 p0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Long jump
JMPL u
CAL a
0
1
0
1
0
1
2/2
1/2
2/2
unconditionally
Subroutine jump on
status 1
0
1
1
1
a5 a4 a3 a2 a1 a0
1
1
1
Long subroutine jump
on status 1
CALL u
0
1
0
1
1 0 p3 p2 p1 p0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Table branch
TBR p
RTN
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
1
1
p3 p2 p1 p0
1/1
1/3
1/1
Return from subroutine
Return from interrupt
0
0
0
0
0
0
0
1
RTNI
1 → IE,
ST
carry restored
Table 39
Input/Output Instructions
Words/
Operation
Mnemonic Operation Code
Function
1 → D (Y)
1 → D (m)
Status Cycles
Set discrete I/O latch
SED
0
1
0
0
1
1
1
1
1
1
0
0
0
1
0
0
1/1
1/1
Set discrete I/O latch
direct
SEDD m
m3 m2 m1 m0
Reset discrete I/O latch
RED
0
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0 → D (Y)
0 → D (m)
1/1
1/1
Reset discrete I/O latch
direct
REDD m
m3 m2 m1 m0
Test discrete I/O latch
TD
0
1
0
0
1
1
1
0
1
1
0
0
0
0
0
0
D (Y)
D (m)
1/1
1/1
Test discrete I/O latch
direct
TDD m
m3 m2 m1 m0
m3 m2 m1 m0
m3 m2 m1 m0
m3 m2 m1 m0
m3 m2 m1 m0
p3 p2 p1 p0
Load A from R-port
register
LAR m
LBR m
LRA m
LRB m
P p
1
1
1
1
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
1
R (m) → A
R (m) → B
A → R (m)
B → R (m)
1/1
1/1
1/1
1/1
1/2
Load B from R-port
register
Load R-port register
from A
Load R-port register
from B
Pattern generation
173
HD404889/HD404899/HD404878/HD404868 Series
Table 40
Control Instructions
Words/
Cycles
Operation
No operation
Start serial
Mnemonic
NOP
Operation Code
Function
Status
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
1
1/1
1/1
1/1
1/1
STS
Standby mode/watch mode* SBY
Stop mode/watch mode STOP
Note: Only after a transition from subactive mode.
174
HD404889/HD404899/HD404878/HD404868 Series
Table 41
Opcode Map
0
R8
L
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
R9
H
0
NOP XSPX XSPY XSPXY ANEM
AM
ORM
RTN RTNI
ALEM
AMC
EORM
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
INEM i(4)
ILEM i(4)
LAB
LBM(XY)
LMAIY(X)
NEGA
BNEM
AYY
IB
IY
LASPY
RED
LASPX
TC
0
YNEI i(4)
XMA(XY)
LAM(XY)
ROTR ROTL
SEM n(2)
LMA(XY)
DAA
REM n(2)
DAS
TM n(2)
SMC
ANM
LAY
TBR p(4)
LBA
XMB(XY)
BLEM
SYY
DB
DY
LMADY(X)
TD
LYA
SED
LXA
REC
SEC
LWI i(2)
LBI i(4)
LYI i(4)
LXI i(4)
LAI i(4)
LBR m(4)
LAR m(4)
REDD m(4)
LAMR m(4)
AI i(4)
1
LMIIY i(4)
TDD m(4)
ALEI i(4)
LRB m(4)
LRA m(4)
SEDD m(4)
XMRA m(4)
C
D
E
F
1-word/2-cycle
instruction
1-word/3-cycle
instruction
RAM direct address
instruction
2-word/2-cycle
instruction
(2-word/2-cycle)
175
HD404889/HD404899/HD404878/HD404868 Series
Table 41
Opcode Map (cont)
1
R8
L
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
R9
H
LAW
ANEMD
AMD
ORMD
0
LWA
ALEMD
AMCD
EORMD
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
INEMD i(4)
ILEMD i(4)
STS
COMB
OR
SBY STOP
JMPL p(4)
CALL p(4)
BRL p(4)
0
XMAD
LAMD
SEMD n(2)
REMD n(2)
TMD n(2)
LMAD
SMCD
ANMD
LMID i(4)
P
p(4)
CAL a(6)
BR b(8)
1
C
D
E
F
1-word/2-cycle
instruction
1-word/3-cycle
instruction
RAM direct address
instruction
2-word/2-cycle
instruction
(2-word/2-cycle)
176
HD404889/HD404899/HD404878/HD404868 Series
Absolute Maximum Ratings
Item
Symbol
VCC
Value
Unit
V
Notes
Power supply voltage
Programming voltage
Pin voltage
–0.3 to +7.0
VPP
–0.3 to +14.0
V
1
VT
–0.3 to VCC+0.3
V
Allowable input current (total)
Allowable output current (total)
Allowable input current (per pin)
∑l0
100
mA
mA
mA
mA
mA
mA
°C
2
–∑ l0
l0
50
3
4
4,5
4,6
7,8
7,9
10
11
30
Allowable output current (per pin)
–l0
4
20
Operating temperature
Storage temperature
Topr
Tstg
–20 to +75
–55 to +125
°C
Notes: Permanent damage may occur if these maximum ratings are exceeded. Normal operation must be
under the conditions stated in the electrical characteristics tables. If these conditions are exceeded,
the LSI may malfunction or its reliability may be affected.
1. Applies to the HD4074889, HD4074899, and HD4074869 TEST (VPP) pin.
2. The allowable input current (total) is the sum of all currents flowing from I/O pins to ground at the
same time.
3. The allowable output current (total) is the sum of all currents flowing from VCC to I/O pins.
4. The allowable input current (per pin) is the maximum current allowed to flow from any one I/O pin
to ground.
5. Applies to pins D0 to D3 and R0 to R8.
6. Applies to pins D4 to D11.
7. The allowable output current (per pin) is the maximum current allowed to flow from VCC to any
one I/O pin.
8. Applies to pins D4 to D11 and R0 to R8.
9. Applies to pins D0 to D3.
10. The operating temperature indicates the temperature range in which power can be supplied to
the LSI (voltage Vcc shown in the electrical characteristics tables can be applied).
11. In the case of chips, the storage specification differs from that of the package products. Please
consult your Hitachi sales representative for details.
177
HD404889/HD404899/HD404878/HD404868 Series
Electrical Characteristics
DC Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912, HD404899,
HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=–20°C to +75°C;
HCD404889, HCD404899, HCD404878: VCC=1.8V to 5.5V, GND=0V, Ta=+75°C; HD4074889,
HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless otherwise
specified)
Item
Symbol Pins
VIH
min.
typ. max.
Unit Test conditions
Notes
Input high
voltage
RESET,SCK, SI,
0.90VCC — VCC+0.3 V
INT0,INT1, WU0 to WU3,
EVNB, EVND
OSC1
VCC–0.3 — VCC+0.3 V
External clock
operation
Input low
voltage
VIL
RESET,SCK, SI,
INT0,INT1, WU0 to WU3,
EVNB, EVND
–0.3
–0.3
—
—
0.10VCC
V
OSC1
0.3
—
0.4
1
V
V
V
External clock
operation
Output high
voltage
VOH
VOL
| IIL|
SCK,SO, BUZZ, TOB,
TOC
VCC–0.5 —
–IOH=0.3mA
Output low
voltage
SCK,SO, BUZZ, TOB,
TOC
—
—
—
—
IOL=0.4mA
I/O leakage
current
RESET,SCK, SI,INT0,
INT1 , WU0 to WU3, EVNB,
EVND, OSC1, TOB, TOC,
SO, BUZZ
µA Vin=0V to VCC
1
Active mode
current
dissipation
lCC1
lCC2
VCC
—
—
3.0 5.0
0.4 1.0
mA VCC=5V, fOSC=4MHz 2
mA VCC=3V,
2
f
OSC=800kHz
Standby mode lSBY1
current
dissipation
VCC
—
—
—
1.0 2.0
0.3 0.6
35 60
mA VCC=5V,
3
f
OSC=4MHz,
LCD on
lSBY2
mA VCC=3V,
3
f
OSC=800kHz LCD
on
Subactive
lSUB
VCC
µA
µA
VCC = 3V, LCD on, 4,5
32 kHz oscillator
used
mode current
dissipation
(HD404888, HD4048812,
HD404889, HCD404889,
HD404898, HD4048912,
HD404899, HCD404899,
HD404874, HD404878,
HCD404878, HD404864,
HD404868)
VCC (HD4074889,
—
70 120
4,5
HD4074899, HD4074869)
178
HD404889/HD404899/HD404878/HD404868 Series
Item
Symbol Pins
min.
typ. max.
Unit Test Conditions
Notes
Watch mode
current dissipation
lWTC1 VCC
—
15 30
µA
µA
µA
V
VCC = 3 V, LCD on,
32 kHz oscillator used
4,5
lWTC2 VCC
—
5
8
VCC = 3 V, LCD off,
32 kHz oscillator used
5
5
6
Stop mode current lSTOP VCC
dissipation
—
—
—
5
VCC = 3 V, no 32 kHz
oscillator
Stop mode
VSTOP VCC
1.5
—
no 32 kHz oscillator
retention voltage
Notes: 1. Excludes output buffer current.
2. Power supply current when the MCU is in the reset state and there are no I/O currents.
Test Conditions MCU State
Pin States
•
•
Reset state
RESET, TEST: At ground
3. Power supply current when the on-chip timers are operating and there are no I/O currents.
Test Conditions MCU State
•
•
•
I/O: Same as reset state
Standby mode
fcyc = fOSC/4
Pin States
•
•
•
RESET: At VCC
TEST: At ground
D0 to D11, R0 to R8: At VCC
4. Applies when the LCD power supply dividing resistor is connected.
5. Power supply current when there are no I/O currents.
Test Conditions Pin States
•
•
•
RESET: At VCC
TEST: At ground
D0 to D11, R0 to R8: At VCC
6. Voltage needed to retain RAM data.
179
HD404889/HD404899/HD404878/HD404868 Series
I/O Characteristics for Standard Pins (HD404888, HD4048812, HD404889, HD404898, HD4048912,
HD404899, HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=–20°C to
+75°C; HCD404889, HCD404899, HCD404878: VC C =1.8V to 5.5V, GND=0V, Ta=+75°C;
HD4074889, HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless
otherwise specified)
Item
Symbol
Pins
min.
typ. max.
Unit
Test conditions
Notes
Input high voltage
VIH
R0 to R8
R0 to R7
R0 to R8
R0 to R7
R0 to R8
R0 to R7
R0 to R8
R0 to R7
R0 to R8
R0 to R7
R0 to R8
R0 to R7
0.7VCC
—
—
—
—
—
50
VCC+0.3
V
1
2
Input low voltage
VIL
–0.3
VCC–0.5
—
0.3VCC
—
V
1
2
Output high voltage
Output low voltage
I/O leakage current
MOS pull-up current
VOH
V
–IOH=0.3mA
IOL=0.4mA
1
2
VOL
0.4
1
V
1
2
| IIL
|
—
µA
µA
VIN=0V to VCC
VCC=3V, VIN=0V
1, 3
2, 3
1
–IPU
10
150
2
Notes: 1. Applies to the HD404889, HD404899, and HD404878 Series.
2. Applies to the HD404868 Series.
3. Excludes the current flowing in the output buffer.
180
HD404889/HD404899/HD404878/HD404868 Series
I/O Characteristics for High-Current Pins (HD404888, HD4048812, HD404889, HD404898,
HD4048912, HD404899, HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V,
Ta=–20°C to +75°C; HCD404889, HCD404899, HCD404878: VCC =1.8V to 5.5V, GND=0V,
Ta=+75°C; HD4074889, HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C,
unless otherwise specified)
Item
Symbol
Pins
min.
typ. max.
Unit
Test conditions
Notes
Input high voltage
VIH
D0 to D11
D0 to D9
D0 to D11
D0 to D9
D4 to D11
D4 to D9
D0 to D3
0.7VCC
—
—
—
—
VCC+0.3
V
1
2
1
2
1
2
Input low voltage
VIL
–0.3
0.3VCC
—
V
V
V
Output high voltage
VOH
VCC–0.5
VCC–2.0
–IOH=0.3mA
—
–IOH=10mA,
VCC=4.5 to 5.5V
Output low voltage
VOL
D0 to D3
D4 to D11
D4 to D9
D0 to D11
D0 to D9
D0 to D11
D0 to D9
—
—
—
—
0.4
2.0
V
V
IOL=0.4mA
IOL=15mA
1
VCC=4.5V to 5.5V
VIN =0V to VCC
2
I/O leakage current
MOS pull-up current
| IIL
|
—
—
1
µA
µA
1, 3
2, 3
1
–IPU
10
50
150
VCC=3V, VIN=0V
2
Notes: 1. Applies to the HD404889, HD404899, and HD404878 Series.
2. Applies to the HD404868 Series.
3. Excludes the current flowing in the output buffer.
181
HD404889/HD404899/HD404878/HD404868 Series
LCD Circuit Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912,
HD404899, HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta= –20°C to
+75°C; HCD404889, HCD404899, HCD404878: VCC =1.8V to 5.5V, GND=0V, Ta=+75°C;
HD4074889, HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless
otherwise specified)
Item
Symbol
Pins
min.
typ. max.
Unit
Test conditions
Notes
Segment driver voltage VDS
drop
SEG1 to
SEG32
—
—
0.6
V
Id=3 µA
1, 2
V1=2.7 to 5.5V
SEG1 to
SEG24
1, 3
1
Common driver voltage VDC
drop
COM1 to
COM4
—
—
0.3
V
Id=3 µA
V1=2.7 to 5.5V
LCD power supply
dividing resistance
RW
50
2.2
300 900
kΩ
V
V1-GND
LCD voltage
VLCD
V1
—
VCC
4, 5
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and GND to each segment pin or each
common pin.
2. Applies to the HD404889, HD404899, and HD404878 Series.
3. Applies to the HD404868 Series.
4. In the HD404889, HD404899, and HD404878 Series, when VLCD is supplied by the internal power
supply, V0 and V1 should be shorted. When VLCD is supplied by an external power supply, the
relationship VCC ≥ VLCD ≥ 2.2 V should be maintained. In this case, the V0 pin should be fixed at
VCC.
5. In the HD404868 Series, when VLCD is supplied by an external power supply, the relationship VCC
≥ VLCD ≥ 2.2 V should be maintained.
182
HD404889/HD404899/HD404878/HD404868 Series
A/D Converter Characteristics (HD404888, HD4048812, HD404889: VCC=1.8V to 5.5V, GND=0V,
Ta=–20°C to +75°C; HCD404889: VCC =1.8V to 5.5V, GND=0V, Ta=+75°C; HD4074889: VCC=2.0V to
5.5V, GND=0V, Ta=–20°C to +75°C, unless otherwise specified)
Item
Symbol
Pins
min.
typ. max.
Unit
Test conditions
Notes
Analog power supply
voltage
AVCC
AVCC
VCC–0.3
VCC VCC+0.3
V
1
Analog input voltage
AVCC-AVSS current
AVin
IAD
AN0 to AN5
AN0 to AN5
AVSS
—
—
—
15
AVCC
500
—
V
µA
pF
VCC=AVCC=5.0V
Analog input
capacitance
CAin
—
Resolution
—
0
8
—
bit
Number of inputs
Absolute accuracy
—
—
6
channel
LSB
—
±2.0
VCC=AVCC=2.7V to
5.5V
—
—
±3.0
LSB
VCC=AVCC=1.8V to
2.7V
2
Conversion time
Input impedance
65
1
—
—
125
—
tcyc
AN0 to AN5
MΩ
Notes: 1. Connect to the VCC pin when the A/D converter is not used. The AVCC setting ranges are 1.8
V≤AVCC≤5.5V (HD404888, HD4048812, HD404889, HCD404889) and 2.0V≤AVCC≤5.5V
(HD4074889)
2. The conversion time is 125tcyc.
183
HD404889/HD404899/HD404878/HD404868 Series
(HD404898, HD4048912, HD404899: VCC=1.8V to 5.5V, GND=0V, Ta=–20°C to +75°C;
HCD404899: VCC =1.8V to 5.5V, GND=0V, Ta=+75°C;
HD4074899: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless otherwise specified)
Item
Symbol
Pins
min.
typ. max.
Unit
Test conditions
Notes
Analog power supply
voltage
AVCC
AVCC
VCC–0.3
VCC VCC+0.3
V
1
Analog input voltage
AVCC-AVSS current
AVin
IAD
AN0 to AN5
AN0 to AN5
AVSS
—
—
—
15
AVCC
500
—
V
µA
pF
VCC=AVCC=5.0V
Analog input
capacitance
CAin
—
Resolution
—
0
10
—
—
—
6
bit
Number of inputs
Conversion time
channel
tcyc
125
—
VCC = AVCC = 1.8 V to
less than 2.0 V
2
65
—
125
tcyc
VCC=AVCC=2.0 V to
5.5V
Absolute accuracy
Input impedance
—
1
—
—
±4.0
LSB
AN0 to AN5
—
MΩ
Notes: 1. Connect to the VCC pin when the A/D converter is not used. The AVCC setting ranges are 1.8
V≤AVCC≤5.5V (HD404898, HD4048912, HD404899, HCD404899) and 2.0V≤AVCC≤5.5V
(HD4074899)
2. Applies to HD404898, HD4048912, HD404899, and HCD404899.
(HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, T =–20°C to +75°C; HD4074869: VCC =2.0V to
a
5.5V, GND=0V, Ta=–20°C to +75°C)
Item
Symbol
AVin
Pins
min.
GND
—
typ. max.
Unit
V
Test conditions
Notes
Analog input voltage
AN0 to AN3
AN0 to AN3
—
VCC
—
Analog input
capacitance
CAin
15
pF
Resolution
—
0
10
—
—
—
—
bit
Number of inputs
Absolute accuracy
Conversion time
4
channel
LSB
tcyc
—
125
±4.0
—
VCC = 1.8 V to less
than 2.0 V
1
65
1
—
—
125
—
tcyc
VCC= 2.0 V to 5.5V
Input impedance
AN0 to AN3
MΩ
Note: 1. Applies to HD404864 and HD404868.
184
HD404889/HD404899/HD404878/HD404868 Series
AC Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912, HD404899,
HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=–20°C to +75°C;,
HCD404889, HCD404899, HCD404878: VCC =1.8V to 5.5V, GND=0V, Ta=+75°C; HD4074889,
HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless otherwise
specified)
Item
Symbol Pins
min. typ.
max. Unit
Test conditions
Notes
Clock oscillation
frequency
fOSC
OSC1, OSC2
0.4
—
—
4.5
32.768 —
10
MHz
kHz
µs
Division by 4
1
X1,X2
Instruction cycle time
tcyc
0.89
—
—
Division by 4
tsubcyc
244.14 —
µs
32 kHz oscillator used,
division by 8
—
—
122.07 —
µs
32 kHz oscillator used,
division by 4
Oscillation settling
time(external clock and
ceramic oscillator)
tRC
OSC1, OSC2
—
7.5
ms
2
Oscillation settling
tRC
OSC1, OSC2
X1,X2
—
—
—
—
30
2
ms
s
VCC=2.0 to 5.5V
Ta=–10 to +60°C
fOSC=4MHZ
2
2
3
time(crystal oscillator)
—
External clock high-
level width
tCPH
OSC1
105
—
ns
External clock low-
level width
tCPL
OSC1
105
—
—
ns
fOSC=4MHZ
3
External clock rise time tCPr
External clock fall time tCPf
OSC1
OSC1
—
—
2
—
—
—
20
20
—
ns
fOSC=4MHZ
fOSC=4MHZ
3
3
4
ns
INT0 to INT1,
tIH
INT0 to INT1,
EVNB,EVND, WU0 to
WU3
tcyc/tsubcyc
EVNB,EVND, WU0 to
WU3 high-level width
INT0 to INT1,
EVNB,EVND, WU0 to
WU3 low-level width
tIL
INT0 to INT1,
EVNB,EVND, WU0 to
WU3
2
—
—
tcyc/tsubcyc
4
RESET low-level width tRSTL
RESET
RESET
2
—
—
—
—
20
15
tcyc
ms
pF
5
5
RESET rise time
tRSTr
Cin
—
—
Input capacitance
All input pins except
TEST
f=1MHz,Vin=0V
TEST
—
—
15
pF
(HD404888, HD4048812,
HD404889, HCD404889,
HD404899, HD404898,
HD4048912,
HCD404899, HD404874,
HD404878, HCD404878,
HD404864, HD404868)
TEST
—
—
40
pF
(HD4074889,
HD4074899,
HD4074869)
185
HD404889/HD404899/HD404878/HD404868 Series
Notes: 1. When the subsystem oscillator (32.768 kHz crystal oscillation) is used, use within the range
0.4 MHz≤fOSC≤1.0 MHz or 1.6 MHz≤fOSC≤4.5 MHz. The SSR1 bit of the system clock select
register (SSR) should be set to 0 and 1, respectively.
2. The oscillation settling time is defined as follows:
(1)
(2)
The time required for the oscillation to settle after VCC has reached min. at power-on.
The time required for the oscillation to settle after RESET input has gone low when stop
mode is cleared.
To ensure enough time for the oscillation to settle at power-on hold the RESET input low for at
least time tRC. The oscillation settling time will depend on the circuit constants and stray
capacitance. The resonator should be determined in consultation with the resonator
manufacturer. With regard to the system clock (OSC1, OSC2), bits MIS1 and MIS0 in the
miscellaneous register (MIS) should be set according to the oscillation settling time of the
resonator used.
3. See figure 104.
4. See figure 105.
5. See figure 106.
Serial Interface Timing Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912,
HD404899, HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=–20°C to
+75°C;, HCD404889, HCD404899, HCD404878: VCC =1.8V to 5.5V, GND=0V, Ta=+75°C;
HD4074889, HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless
otherwise specified)
Item
Symbol
Pins
SCK
SCK
min.
1
typ. max.
Unit
tcyc
Test conditions
Notes
Serial clock cycle time tScyc
—
—
—
—
See load in figure 108
See load in figure 108
1
1
Serial clock high-level tSCKH
width
0.4
tScyc
Serial clock low-level
width
tSCKL
SCK
0.4
—
—
tScyc
See load in figure 108
1
Serial clock rise time
Serial clock fall time
tSC Kr
tSCKf
tDSO
SCK
SCK
SO
—
—
—
—
—
—
100
100
300
ns
ns
ns
See load in figure 108
See load in figure 108
See load in figure 108
1
1
1
Serial output data
delay time
Serial input data setup tSSI
time
SI
SI
200
200
—
—
—
—
ns
ns
1
1
Serial input data hold tHSI
time
186
HD404889/HD404899/HD404878/HD404868 Series
During Serial Clock Input
Item
Symbol
Pins
SCK
SCK
min.
1
typ. max.
Unit
tcyc
Test conditions
Notes
Serial clock cycle time tScyc
—
—
—
—
1
1
Serial clock high-level tSCKH
width
0.4
tScyc
Serial clock low-level
width
tSCKL
SCK
0.4
—
—
tScyc
1
Serial clock rise time
Serial clock fall time
tSC Kr
tSCKf
tDSO
SCK
SCK
SO
—
—
—
—
—
—
100
100
300
ns
ns
ns
1
1
1
Serial output data
delay time
See load in figure 108
Serial input data setup tSSI
time
SI
SI
200
200
—
—
—
—
ns
ns
1
1
Serial input data hold tHSI
time
Note: 1. See figure 107.
OSC1
1/fCP
VCC-0.3V
0.3V
tCPL
tCPH
tCPr
tCPf
Figure 104 External Clock Input Waveform
INT0 , INT1, EVNB, EVND, WU0 to WU3
0.9VCC
tIH
tIL
0.1VCC
Figure 105 Interrupt Timing
187
HD404889/HD404899/HD404878/HD404868 Series
RESET
0.9VCC
tRSTL
0.1VCC
tRSTr
Figure 106 Reset Timing
tScyc
tSCKr
tSCKf
tSCKL
SCK
VCC–0.5V(0.9VCC)*
tSCKH
0.4V(0.1VCC)*
tDOS
VCC–0.5V
0.4V
SO
tSSI
tHSI
0.9VCC
0.1VCC
SI
Note : VCC–0.5V and 0.4V are the voltages during serial clock output.
0.9 VCC and 0.1 VCC are the voltages during serial clock input.
Figure 107 Serial Interface Timing
188
HD404889/HD404899/HD404878/HD404868 Series
VCC
R1=2.6kΩ
Test point
R=12kΩ
C=30pF
1S2074(H)
or equivalent
Figure 108 Timing Load Circuit
189
HD404889/HD404899/HD404878/HD404868 Series
Package Dimensions
17.2 ± 0.3
Unit: mm
14
60
41
61
40
21
80
1
20
*0.32 ± 0.08
0.30 ± 0.06
M
0.12
0.83
1.6
0° – 8°
0.8 ± 0.3
0.10
Hitachi Code
JEDEC
FP-80A
—
EIAJ
Conforms
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 1.2 g
14.0 ± 0.2
Unit: mm
12
60
41
61
80
40
21
1
20
*0.22 ± 0.05
0.20 ± 0.04
M
0.10
1.25
1.0
0° – 8°
0.5 ± 0.1
0.10
Hitachi Code
JEDEC
TFP-80C
—
EIAJ
Conforms
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.4 g
190
HD404889/HD404899/HD404878/HD404868 Series
Unit: mm
17.2 ± 0.3
14
33
48
32
17
49
64
1
16
M
*0.37 ± 0.08
0.35 ± 0.06
0.15
1.6
1.0
0° – 8°
0.8 ± 0.3
0.10
Hitachi Code
JEDEC
FP-64A
—
EIAJ
Conforms
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 1.2 g
Unit: mm
57.6
58.5 Max
64
33
32
1
1.0
19.05
1.46 Max
+ 0.11
– 0.05
0.25
1.78 ± 0.25
0.48 ± 0.10
0° – 15°
Hitachi Code
JEDEC
DP-64S
—
EIAJ
Conforms
Weight (reference value) 8.8 g
191
HD404889/HD404899/HD404878/HD404868 Series
Note on ROM Ordering
Please note the following when ordering HD404888, HD4048812, HD404898 or HD4048912 ROM.
When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of
data as for the 16-kwords version (HD404889, HD404899). The program that converts ROM data to mask
drawing data is the same as that used for the 16-kwords version, and therefore the same amount of data is
necessary. This applies both to orders using EPROM and orders using data transmission.
12-kword ROM version:
HD4048812, HD4048912
Write all-1 data to addresses
$3000 to $3FFF.
8-kword ROM
version: HD404888, HD404898
Write all-1 data to addresses
$2000 to $3FFF.
$0000
$0000
Vector addresses
Vector addresses
$000F
$0010
$000F
$0010
Zero page
subroutine area
(64 words)
Zero page
subroutine area
(64 words)
$003F
$0040
$003F
$0040
Program and pattern
area (8,192 words)
Program and pattern
area (12,288 words)
$1FFF
$2000
$2FFF
$3000
Not used
Not used
$3FFF
$3FFF
Note : Write all-1 data in shaded areas.
192
HD404889/HD404899/HD404878/HD404868 Series
Note on ROM Ordering
Please note the following when ordering HD404874 or HD404864 ROM.
When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of
data as for the 8-kwords version (HD404878, HD404868). The program that converts ROM data to mask
drawing data is the same as that used for the 8-kwords version, and therefore the same amount of data is
necessary. This applies both to orders using EPROM and orders using data transmission.
4-kword ROM
version: HD404874, HD404864
Write all-1 data to addresses
$1000 to $1FFF.
$0000
Vector addresses
$000F
$0010
Zero page
subroutine area
(64 words)
$003F
$0040
Program and pattern
area (4,096 words)
$0FFF
$1000
Not used
$1FFF
Note : Write all-1 data in shaded areas.
193
HD404889/HD404899/HD404878/HD404868 Series
Option List HD404888, HD4048812, HD404889, HCD404889
Please check off the appropriate applications and enter the necessary information.
Date of order
Customer
Year
Month
Day
Department
Name
ROM code name
LSI number (Hitachi entry)
1. ROM Size
❑ HD404888
❑ HD4048812
❑ HD404889
❑ HCD404889
8 kwords
12 kwords
16 kwords
16 kwords
2. Function Options
*
*
❑
❑
❑
32 kHz CPU operation, realtime clock time base
No 32 kHz CPU operation, realtime clock time base
No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1
X2).
3. ROM Code Data Organization
For a microcomputer with EPROM mounted (including a ZTAT™ microcomputer), specify the combined upper/lower
type.
❑
•
Combined lower/upper type
Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU...
Separate lower/upper type
❑
•
The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
4. System Oscillator (OSC1-OSC2)
❑
❑
❑
Ceramic oscillator
Crystal oscillator
External clock
f =
f =
f =
MHz
MHz
MHz
194
HD404889/HD404899/HD404878/HD404868 Series
5. Subsystem Oscillator (X1 X2)
6. Stop Mode
7. Package
❑ FP-80A
❑ TFP-80C
❑ Chip
❑
❑
Not used
—
❑
❑
Yes (used)
Crystal resonator
f = 32.768 kHz
No (not used)
Note: The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details.
195
HD404889/HD404899/HD404878/HD404868 Series
Option List HD404898, HD4048912, HD404899, HCD404899
Please check off the appropriate applications and enter the necessary information.
Date of order
Customer
Year
Month
Day
Department
Name
ROM code name
LSI number (Hitachi entry)
1. ROM Size
❑ HD404898
❑ HD4048912
❑ HD404899
❑ HCD404899
8 kwords
12 kwords
16 kwords
16 kwords
2. Function Options
*
*
❑
❑
❑
32 kHz CPU operation, realtime clock time base
No 32 kHz CPU operation, realtime clock time base
No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1
X2).
3. ROM Code Data Organization
For a microcomputer with EPROM mounted (including a ZTAT™ microcomputer), specify the combined upper/lower
type.
❑
•
Combined lower/upper type
Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU...
Separate lower/upper type
❑
•
The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
4. System Oscillator (OSC1-OSC2)
❑
❑
❑
Ceramic oscillator
Crystal oscillator
External clock
f =
f =
f =
MHz
MHz
MHz
196
HD404889/HD404899/HD404878/HD404868 Series
5. Subsystem Oscillator (X1 X2)
6. Stop Mode
7. Package
❑ FP-80A
❑ TFP-80C
❑ Chip
❑
❑
Not used
—
❑
❑
Yes (used)
Crystal resonator
f = 32.768 kHz
No (not used)
Note: The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details.
197
HD404889/HD404899/HD404878/HD404868 Series
Option List HD404874, HD404878, HCD404878
Please check off the appropriate applications and enter the necessary information.
Date of order
Customer
Year
Month
Day
Department
Name
ROM code name
LSI number (Hitachi entry)
1. ROM Size
❑ HD404874
❑ HD404878
❑ HCD404878
4 kwords
8 kwords
8 kwords
2. Function Options
*
*
❑
❑
❑
32 kHz CPU operation, realtime clock time base
No 32 kHz CPU operation, realtime clock time base
No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1 X2).
3. ROM Code Data Organization
For a microcomputer with EPROM mounted (including a ZTAT™ microcomputer), specify the combined upper/lower
type.
❑
•
Combined lower/upper type
Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU...
Separate lower/upper type
❑
•
The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
4. System Oscillator (OSC1-OSC2)
❑
❑
❑
Ceramic oscillator
Crystal oscillator
External clock
f =
f =
f =
MHz
MHz
MHz
5. Subsystem Oscillator (X1 X2)
6. Stop Mode
7. Package
❑ FP-80A
❑ TFP-80C
❑ Chip
❑
❑
Not used
—
❑
Yes (used)
Crystal resonator
f = 32.768 kHz
❑
No (not used)
Note: The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details.
198
HD404889/HD404899/HD404878/HD404868 Series
Option List HD404864, HD404868
Please check off the appropriate applications and enter the necessary information.
Date of order
Customer
Year
Month
Day
Department
Name
ROM code name
LSI number (Hitachi entry)
1. ROM Size
❑ HD404864
❑ HD404868
4 kwords
8 kwords
2. Function Options
*
*
❑
❑
❑
32 kHz CPU operation, realtime clock time base
No 32 kHz CPU operation, realtime clock time base
No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1
X2).
3. ROM Code Data Organization
For a microcomputer with EPROM mounted (including a ZTAT™ microcomputer), specify the combined upper/lower
type.
❑
•
Combined lower/upper type
Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU...
Separate lower/upper type
❑
•
The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
4. System Oscillator (OSC1-OSC2)
❑
❑
❑
Ceramic oscillator
Crystal oscillator
External clock
f =
f =
f =
MHz
MHz
MHz
5. Subsystem Oscillator (X1 X2)
6. Stop Mode
7. Package
❑ FP-64A
❑ DP-64S
❑
❑
Not used
—
❑
Yes (used)
Crystal resonator
f = 32.768 kHz
❑
No (not used)
199
HD404889/HD404899/HD404878/HD404868 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
: http:semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
Asia (Taiwan)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/index.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe GmbH
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
200
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SI9137LG
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SI9122E
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