HD6413308CP10 [HITACHI]
Microcontroller, 8-Bit, H8/300 CPU, 20MHz, CMOS, PQCC84, PLASTIC, LCC-84;
| 型号： | HD6413308CP10 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Microcontroller, 8-Bit, H8/300 CPU, 20MHz, CMOS, PQCC84, PLASTIC, LCC-84 微控制器 |
| 文件： | 总348页 (文件大小：1425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HITACHI SINGLE-CHIP MICROCOMPUTER
H8/330
HD6473308, HD6433308, HD6413308
HARDWARE MANUAL
Preface
The H8/330 is a high-performance single-chip microcomputer ideally suited for embedded control
of industrial equipment. Its core is the H8/300 CPU: a high-speed processor. On-chip supporting
modules provide memory, I/O, and timer functions, including:
•
•
•
•
•
•
•
16K bytes of on-chip ROM
512 bytes of on-chip RAM
15 bytes of dual-port RAM for a master-slave interface
Serial I/O
General-purpose I/O ports
A/D converter
Timers
Compact, high-performance control systems can be built using the H8/330.
The H8/330 is available with either electrically programmable or mask programmable ROM.
Manufacturers can use the electrically programmable ZTAT™* (Zero Turn-Around Time) version
to get production off to a fast start and make software changes quickly, then switch over to the
masked version for full-scale production runs.
This manual describes the H8/330 hardware. Refer to the H8/300 Series Programming Manual for
a detailed description of the instruction set.
* ZTAT is a registered trademark of Hitachi, Ltd.
CONTENTS
Section 1. Overview...............................................................................................................
1.1 Block Diagram......................................................................................................................
1.2 Descriptions of Blocks..........................................................................................................
1.3 Pin Assignments and Functions............................................................................................
1.3.1 Pin Arrangement......................................................................................................
1.3.2 Pin Functions...........................................................................................................
1
2
3
6
6
9
Section 2. MCU Operating Modes and Address Space................................................ 17
2.1 Overview............................................................................................................................... 17
2.2 Mode Descriptions................................................................................................................ 18
2.3 Address Space Map .............................................................................................................. 19
2.3.1 Access Speed........................................................................................................... 19
2.3.2 IOS........................................................................................................................... 19
2.4 Mode and System Control Registers (MDCR and SYSCR)................................................. 21
2.4.1 Mode Control Register (MDCR) – H'FFC5 ............................................................ 21
2.4.2 System Control Register (SYSCR) – H'FFC4......................................................... 22
Section 3. CPU........................................................................................................................ 25
3.1 Overview............................................................................................................................... 25
3.1.1 Features.................................................................................................................... 25
3.2 Register Configuration.......................................................................................................... 26
3.2.1 General Registers..................................................................................................... 26
3.2.2 Control Registers..................................................................................................... 27
3.2.3 Initial Register Values.............................................................................................. 28
3.3 Addressing Modes ................................................................................................................ 29
3.4 Data Formats......................................................................................................................... 31
3.4.1 Data Formats in General Registers.......................................................................... 32
3.4.2 Memory Data Formats............................................................................................. 33
3.5 Instruction Set....................................................................................................................... 34
3.5.1 Data Transfer Instructions ....................................................................................... 36
3.5.2 Arithmetic Operations ............................................................................................. 38
3.5.3 Logic Operations ..................................................................................................... 39
3.5.4 Shift Operations....................................................................................................... 39
3.5.5 Bit Manipulations .................................................................................................... 41
3.5.6 Branching Instructions............................................................................................. 47
3.5.7 System Control Instructions .................................................................................... 49
i
3.5.8 Block Data Transfer Instruction .............................................................................. 50
3.6 CPU States............................................................................................................................ 51
3.6.1 Program Execution State ......................................................................................... 52
3.6.2 Exception-Handling State........................................................................................ 52
3.6.3 Power-Down State................................................................................................... 53
3.7 Access Timing and Bus Cycle.............................................................................................. 53
3.7.1 Access to On-Chip Memory (RAM and ROM) ...................................................... 53
3.7.2 Access to On-Chip Register Field and External Devices........................................ 55
Section 4. Exception Handling............................................................................................ 59
4.1 Reset ..................................................................................................................................... 60
4.2 Interrupts............................................................................................................................... 63
4.2.1 Interrupt-Related Registers...................................................................................... 69
4.2.2 External Interrupts................................................................................................... 70
4.2.3 Internal Interrupts .................................................................................................... 71
4.2.4 Interrupt Response Time.......................................................................................... 72
4.2.5 Note on Stack Handling........................................................................................... 73
4.2.6 Deferring of Interrupts............................................................................................. 75
Section 5. I/O Ports................................................................................................................ 77
5.1 Overview............................................................................................................................... 77
5.2 Port 1..................................................................................................................................... 78
5.3 Port 2..................................................................................................................................... 81
5.4 Port 3..................................................................................................................................... 84
5.5 Port 4..................................................................................................................................... 88
5.6 Port 5..................................................................................................................................... 91
5.7 Port 6..................................................................................................................................... 96
5.8 Port 7.....................................................................................................................................102
5.9 Port 8.....................................................................................................................................104
5.10 Port 9..................................................................................................................................... 114
Section 6. 16-Bit Free-Running Timer..............................................................................123
6.1 Overview...............................................................................................................................123
6.1.1 Features....................................................................................................................123
6.1.2 Block Diagram.........................................................................................................123
6.1.3 Input and Output Pins..............................................................................................125
6.1.4 Register Configuration ............................................................................................125
6.2 Register Descriptions............................................................................................................126
ii
6.2.1 Free-Running Counter (FRC) – H'FF92..................................................................126
6.2.2 Output Compare Registers A and B (OCRA and OCRB) – H'FF94.......................127
6.2.3 Input Capture Registers A to D (ICRA to ICRD) –
H'FF98, H'FF9A, H'FF9C, H'FF9E.........................................................................127
6.2.4 Timer Interrupt Enable Register (TIER) – H'FF90 .................................................129
6.2.5 Timer Control/Status Register (TCSR) – H'FF91 ...................................................131
6.2.6 Timer Control Register (TCR) – H'FF96 ................................................................134
6.2.7 Timer Output Compare Control Register (TOCR) – H'FF97..................................136
6.3 CPU Interface .......................................................................................................................137
6.4 Operation ..............................................................................................................................139
6.4.1 FRC Incrementation Timing....................................................................................139
6.4.2 Output Compare Timing..........................................................................................141
6.4.3 Input Capture Timing ..............................................................................................142
6.4.4 Setting of FRC Overflow Flag (OVF).....................................................................145
6.5 Interrupts...............................................................................................................................146
6.6 Sample Application...............................................................................................................146
6.7 Application Notes .................................................................................................................147
Section 7. 8-Bit Timers .........................................................................................................153
7.1 Overview...............................................................................................................................153
7.1.1 Features....................................................................................................................153
7.1.2 Block Diagram.........................................................................................................153
7.1.3 Input and Output Pins..............................................................................................154
7.1.4 Register Configuration ............................................................................................155
7.2 Register Descriptions............................................................................................................155
7.2.1 Timer Counter (TCNT) – H'FFC8 (TMR0), H'FFD0 (TMR1) ...............................155
7.2.2 Time Constant Registers A and B (TCORA and TCORB) –
H'FFCA and H'FFCB (TMR0), H'FFD2 and H'FFD3 (TMR1)..............................156
7.2.3 Timer Control Register (TCR) – H'FFC8 (TMR0), H'FFD0 (TMR1) ....................156
7.2.4 Timer Control/Status Register (TCSR) – H'FFC9 (TMR0), H'FFD1 (TMR1).......158
7.3 Operation ..............................................................................................................................160
7.3.1 TCNT Incrementation Timing.................................................................................160
7.3.2 Compare Match Timing...........................................................................................161
7.3.3 External Reset of TCNT..........................................................................................163
7.3.4 Setting of TCSR Overflow Flag..............................................................................164
7.4 Interrupts...............................................................................................................................165
7.5 Sample Application...............................................................................................................165
7.6 Application Notes .................................................................................................................166
iii
Section 8. PWM Timers........................................................................................................171
8.1 Overview...............................................................................................................................171
8.1.1 Features....................................................................................................................171
8.1.2 Block Diagram.........................................................................................................171
8.1.3 Input and Output Pins..............................................................................................172
8.1.4 Register Configuration ............................................................................................172
8.2 Register Descriptions............................................................................................................172
8.2.1 Timer Counter (TCNT) – H'FFA2 (PWM0), H'FFA6 (PWM1)..............................172
8.2.2 Duty Register (DTR) – H'FFA1 (PWM0), H'FFA5 (PWM1) .................................173
8.2.3 Timer Control Register (TCR) – H'FFA0 (PWM0), H'FFA4 (PWM1)...................173
8.3 Operation ..............................................................................................................................175
8.3.1 Timer Incrementation ..............................................................................................175
8.3.2 PWM Operation.......................................................................................................176
8.4 Application Notes .................................................................................................................177
Section 9. Serial Communication Interface .....................................................................179
9.1 Overview...............................................................................................................................179
9.1.1 Features....................................................................................................................179
9.1.2 Block Diagram.........................................................................................................180
9.1.3 Input and Output Pins..............................................................................................180
9.1.4 Register Configuration ............................................................................................181
9.2 Register Descriptions............................................................................................................181
9.2.1 Receive Shift Register (RSR)..................................................................................181
9.2.2 Receive Data Register (RDR) – H'FFDD................................................................182
9.2.3 Transmit Shift Register (TSR).................................................................................182
9.2.4 Transmit Data Register (TDR) – H'FFDB...............................................................182
9.2.5 Serial Mode Register (SMR) – H'FFD8 ..................................................................183
9.2.6 Serial Control Register (SCR) – H'FFDA ...............................................................185
9.2.7 Serial Status Register (SSR) – H'FFDC ..................................................................187
9.2.8 Bit Rate Register (BRR) – H'FFD9.........................................................................189
9.3 Operation ..............................................................................................................................193
9.3.1 Overview .................................................................................................................193
9.3.2 Asynchronous Mode................................................................................................194
9.3.3 Synchronous Mode..................................................................................................198
9.4 Interrupts...............................................................................................................................202
9.5 Application Notes .................................................................................................................203
iv
Section 10. A/D Converter .....................................................................................................207
10.1 Overview...............................................................................................................................207
10.1.1 Features....................................................................................................................207
10.1.2 Block Diagram.........................................................................................................208
10.1.3 Input Pins.................................................................................................................209
10.1.4 Register Configuration ............................................................................................209
10.2 Register Descriptions............................................................................................................210
10.2.1 A/D Data Registers (ADDR) – H'FFE0 to H'FFE6.................................................210
10.2.2 A/D Control/Status Register (ADCSR) – H'FFE8 ..................................................210
10.2.3 A/D Control Register (ADCR) – H'FFEA...............................................................213
10.3 Operation ..............................................................................................................................213
10.3.1 Single Mode (SCAN = 0)........................................................................................214
10.3.2 Scan Mode (SCAN = 1) ..........................................................................................217
10.3.3 Input Sampling Time and A/D Conversion Time....................................................220
10.3.4 External Trigger Input Timing.................................................................................222
10.4 Interrupts...............................................................................................................................223
Section 11. Dual-Port RAM (Parallel Communication Interface) ...............................225
11.1 Overview...............................................................................................................................225
11.1.1 Features....................................................................................................................225
11.1.2 Block Diagram.........................................................................................................226
11.1.3 Input and Output Pins..............................................................................................227
11.1.4 Register Configuration ............................................................................................227
11.2 Register Descriptions............................................................................................................228
11.2.1 Dual Port RAM Enable Bit (DPME).......................................................................228
11.2.2 Parallel Communication Data Register 0 (PCDR0) – H'FFF1................................230
11.2.3 Parallel Communication Data Registers 1 to 14 –
H'FFF2 (PCDR1) to H'FFFF (PCDR1-14)..............................................................231
11.2.4 Parallel Communication Control/Status Register (PCCSR) – H'FFF0 ...................231
11.3 Usage ....................................................................................................................................234
11.3.1 Data Transfer from Master CPU to H8/300 CPU....................................................234
11.3.2 Data Transfer from H8/300 CPU to Master CPU....................................................235
11.4 Master-Slave Interconnections .............................................................................................237
Section 12. RAM.......................................................................................................................239
12.1 Overview...............................................................................................................................239
12.2 Block Diagram......................................................................................................................239
12.3 RAM Enable Bit (RAME)....................................................................................................239
v
12.4 Operation ..............................................................................................................................240
12.4.1 Expanded Modes (Modes 1 and 2)..........................................................................240
12.4.2 Single-Chip Mode (Mode 3) ...................................................................................240
Section 13. ROM.......................................................................................................................241
13.1 Overview...............................................................................................................................241
13.1.1 Block Diagram.........................................................................................................242
13.2 PROM Mode.........................................................................................................................242
13.2.1 PROM Mode Setup .................................................................................................242
13.2.2 Socket Adapter Pin Assignments and Memory Map...............................................243
13.3 Programming ........................................................................................................................245
13.3.1 Writing and Verifying..............................................................................................245
13.3.2 Notes on Writing......................................................................................................249
13.3.3 Reliability of Written Data ......................................................................................249
13.3.4 Erasing of Data........................................................................................................250
13.4 Handling of Windowed Packages.........................................................................................250
Section 14. Power-Down State..............................................................................................253
14.1 Overview...............................................................................................................................253
14.2 System Control Register: Power-Down Control Bits...........................................................254
14.3 Sleep Mode ...........................................................................................................................255
14.3.1 Transition to Sleep Mode.........................................................................................256
14.3.2 Exit from Sleep Mode .............................................................................................256
14.4 Software Standby Mode........................................................................................................256
14.4.1 Transition to Software Standby Mode.....................................................................257
14.4.2 Exit from Software Standby Mode..........................................................................257
14.4.3 Sample Application of Software Standby Mode.....................................................257
14.4.4 Application Notes....................................................................................................258
14.5 Hardware Standby Mode ......................................................................................................259
14.5.1 Transition to Hardware Standby Mode....................................................................259
14.5.2 Recovery from Hardware Standby Mode................................................................259
14.5.3 Timing Relationships...............................................................................................260
Section 15. E-Clock Interface................................................................................................261
15.1 Overview...............................................................................................................................261
Section 16. Clock Pulse Generator.......................................................................................265
16.1 Overview...............................................................................................................................265
vi
16.1.1 Block Diagram.........................................................................................................265
16.2 Oscillator Circuit...................................................................................................................265
16.3 System Clock Divider...........................................................................................................268
Section 17. Electrical Specifications....................................................................................269
17.1 Absolute Maximum Ratings.................................................................................................269
17.2 Electrical Characteristics ......................................................................................................269
17.2.1 DC Characteristics...................................................................................................269
17.2.2 AC Characteristics...................................................................................................273
17.2.3 A/D Converter Characteristics.................................................................................277
17.3 MCU Operational Timing.....................................................................................................278
17.3.1 Bus Timing ..............................................................................................................278
17.3.2 Control Signal Timing.............................................................................................280
17.3.3 16-Bit Free-Running Timer Timing ........................................................................283
17.3.4 8-Bit Timer Timing..................................................................................................284
17.3.5 Pulse Width Modulation Timer Timing...................................................................285
17.3.6 Serial Communication Interface Timing .................................................................285
17.3.7 I/O Port Timing........................................................................................................286
17.3.8 Dual-Port RAM Timing...........................................................................................287
Appendices
Appendix A. CPU Instruction Set......................................................................................289
A.1 Instruction Set List................................................................................................................289
A.2 Operation Code Map.............................................................................................................296
A.3 Number of States Required for Execution............................................................................298
Appendix B. Register Field.................................................................................................304
B.1 Register Addresses and Bit Names.......................................................................................304
B.2 Register Descriptions............................................................................................................308
Appendix C. Pin States.........................................................................................................337
C.1 Pin States in Each Mode.......................................................................................................337
Appendix D. Timing of Transition to and Recovery From Hardware
Standby Mode................................................................................................339
Appendix E. Package Dimensions ....................................................................................340
vii
Table
Table 1-1
Table 1-2
Table 1-3
Product Lineup......................................................................................................
Pin Assignments in Each Operating Mode (1)......................................................
5
9
Pin Functions (1)................................................................................................... 12
Table 2-1
Table 2-2
Operating Modes................................................................................................... 17
Mode and System Control Registers..................................................................... 21
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 3-9
Instruction Classification....................................................................................... 34
Data Transfer Instructions..................................................................................... 36
Arithmetic Instructions.......................................................................................... 38
Logic Operation Instructions................................................................................. 39
Shift Instructions ................................................................................................... 39
Bit-Manipulation Instruction (1)........................................................................... 41
Branching Instructions .......................................................................................... 47
System Control Instructions.................................................................................. 49
Block Data Transfer Instruction/EEPROM Write Operation................................ 50
Table 4-1
Table 4-2
Table 4-3
Table 4-4
Reset and Interrupt Exceptions ............................................................................. 59
Interrupts ............................................................................................................... 64
Registers Read by Interrupt Controller ................................................................. 69
Number of States before Interrupt Service............................................................ 73
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 5-6
Table 5-7
Table 5-8
Table 5-9
Table 5-10
Table 5-11
Table 5-12
Table 5-13
Table 5-14
Auxiliary Functions of Input/Output Ports............................................................ 78
Functions of Port 1................................................................................................ 78
Port 1 Registers ..................................................................................................... 79
Functions of Port 2................................................................................................ 81
Port 2 Registers ..................................................................................................... 82
Functions of Port 3................................................................................................ 84
Port 3 Registers ..................................................................................................... 85
Port 4 Pin Functions (Mode 1 to 3)....................................................................... 88
Port 4 Registers ..................................................................................................... 88
Port 5 Pin Functions (Mode 1 to 3)....................................................................... 91
Port 5 Registers ..................................................................................................... 92
Port 6 Pin Functions.............................................................................................. 96
Port 6 Registers ..................................................................................................... 97
Port 7 Pin Functions (Mode 1 to 3).......................................................................103
viii
Table 5-15
Table 5-16
Table 5-17
Table 5-18
Table 5-19
Port 7 Registers .....................................................................................................103
Port 8 Pin Functions..............................................................................................104
Port 8 Registers .....................................................................................................104
Port 9 Pin Functions.............................................................................................. 114
Port 9 Registers ..................................................................................................... 114
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Input and Output Pins of Free-Running Timer Module........................................125
Register Configuration..........................................................................................125
Free-Running Timer Interrupts .............................................................................146
Effect of Changing Internal Clock Sources...........................................................150
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Input and Output Pins of 8-Bit Timer ...................................................................154
8-Bit Timer Registers............................................................................................155
8-Bit Timer Interrupts ...........................................................................................165
Priority of Timer Output........................................................................................168
Effect of Changing Internal Clock Sources...........................................................169
Table 8-1
Table 8-2
Table 8-3
Output Pins of PWM Timer Module.....................................................................172
PWM Timer Registers...........................................................................................172
PWM Timer Parameters for 10MHz System Clock..............................................175
Table 9-1
Table 9-2
Table 9-3
Table 9-4
Table 9-5
Table 9-6
Table 9-7
Table 9-8
Table 9-9
Table 9-10
SCI Input/Output Pins...........................................................................................180
SCI Registers.........................................................................................................181
Examples of BRR Settings in Asynchronous Mode (1)........................................189
Examples of BRR Settings in Synchronous Mode................................................192
Communication Formats Used by SCI..................................................................193
SCI Clock Source Selection..................................................................................193
Data Formats in Asynchronous Mode...................................................................195
Receive Errors.......................................................................................................198
SCI Interrupts........................................................................................................203
SSR Bit States and Data Transfer When Multiple Receive Errors Occur.............204
Table 10-1
Table 10-2
Table 10-3
A/D Input Pins.......................................................................................................209
A/D Registers........................................................................................................209
Assignment of Data Registers to Analog Input Channels.....................................210
Table 10-4 (a) A/D Conversion Time (Single Mode)...................................................................222
Table 10-4 (b) A/D Conversion Time (Scan Mode) .....................................................................222
ix
Table 11-1
Table 11-2
Dual-Port RAM Input and Output Pins.................................................................227
Dual-Port RAM Register Configuration ...............................................................227
Table 12-1
System Control Register........................................................................................240
Table 13-1
Table 13-2
Table 13-3
Table 13-4
Table 13-5
On-Chip ROM Usage in Each MCU Mode ..........................................................241
Selection of PROM Mode.....................................................................................242
Recommended Socket Adapters............................................................................243
Selection of Sub-Modes in PROM Mode .............................................................245
DC Characteristics (When VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V,
VSS = 0V, Ta=25˚C ±5˚C) .....................................................................................247
AC Characteristics (When VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V,
Table 13-6
Ta=25˚C ±5˚C) ......................................................................................................247
Erasing Conditions................................................................................................250
Recommended Socket for Mounting 84-Pin LCC Package..................................251
Table 13-7
Table 13-8
Table 14-1
Table 14-2
Table 14-3
Power-Down State.................................................................................................253
System Control Register........................................................................................254
Times Set by Standby Timer Select Bits (Unit: ms) .............................................255
Table 16-1
External Crystal Parameters..................................................................................266
Table 17-1
Table 17-2
Table 17-3
Table 17-4
Table 17-5
Table 17-6
Table 17-7
Absolute Maximum Ratings..................................................................................269
DC Characteristics.................................................................................................270
Allowable Output Current Sink Values.................................................................272
Bus Timing............................................................................................................273
Control Signal Timing...........................................................................................274
Timing Conditions of On-Chip Supporting Modules............................................274
A/D Converter Characteristics ..............................................................................277
Table A-1
Table A-2
Table A-3
Table A-4
Instruction Set .......................................................................................................290
Operation Code Map.............................................................................................297
Number of States Taken by Each Cycle in Instruction Execution ........................298
Number of Cycles in Each Instruction..................................................................299
Table C-1
Pin States...............................................................................................................337
x
Figure
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Block Diagram ......................................................................................................
Pin Arrangement (FP-80A, Top View) .................................................................
Pin Arrangement (CP-84, Top View)....................................................................
Pin Arrangement (CG-84, Top View) ...................................................................
2
6
7
8
Figure 2-1
Address Space Map............................................................................................... 20
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 3-11
Figure 3-12
Figure 3-13
Figure 3-14
Figure 3-15
Figure 3-16
CPU Registers ....................................................................................................... 26
Stack Pointer ......................................................................................................... 27
Register Data Formats........................................................................................... 32
Memory Data Formats .......................................................................................... 33
Data Transfer Instruction Codes............................................................................ 37
Arithmetic, Logic, and Shift Instruction Codes .................................................... 40
Bit Manipulation Instruction Codes...................................................................... 46
Branching Instruction Codes................................................................................. 48
System Control Instruction Codes......................................................................... 50
Block Data Transfer Instruction/EEPROM Write Operation Code ...................... 51
Operating States .................................................................................................... 51
State Transitions.................................................................................................... 52
On-Chip Memory Access Cycle ........................................................................... 54
Pin States during On-Chip Memory Access Cycle............................................... 54
On-Chip Register Field Access Cycle................................................................... 55
Pin States during On-Chip Register Field Access Cycle ...................................... 56
Figure 3-17(a) External Device Access Timing (read) ................................................................. 56
Figure 3-17(b) External Device Access Timing (write) ................................................................ 57
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Reset Sequence (Mode 2 or 3, Reset Routine in On-Chip ROM)......................... 61
Reset Sequence (Mode 1)...................................................................................... 62
Block Diagram of Interrupt Controller.................................................................. 66
Hardware Interrupt-Handling Sequence................................................................ 67
Timing of Interrupt Sequence................................................................................ 68
Usage of Stack in Interrupt Handling.................................................................... 74
Example of Damage Caused by Setting an Odd Address in R7 ........................... 75
Example of Deferred Interrupt.............................................................................. 76
Figure 5-1
Port 1 Schematic Diagram..................................................................................... 81
xi
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
Figure 5-10
Figure 5-11
Figure 5-12
Figure 5-13
Figure 5-14
Figure 5-15
Figure 5-16
Figure 5-17
Figure 5-18
Figure 5-19
Figure 5-20
Figure 5-21
Figure 5-22
Figure 5-23
Figure 5-24
Figure 5-25
Port 2 Schematic Diagram..................................................................................... 84
Port 3 Schematic Diagram..................................................................................... 87
Port 4 Schematic Diagram (Pins P40, P42, P43, and P45) ..................................... 90
Port 4 Schematic Diagram (Pins P41, P44, P46, and P47) ..................................... 91
Port 5 Schematic Diagram (Pin P50)..................................................................... 94
Port 5 Schematic Diagram (Pin P51)..................................................................... 95
Port 5 Schematic Diagram (Pin P52)..................................................................... 96
Port 6 Schematic Diagram (Pins P60, P62, P63, P64, and P65).............................. 99
Port 6 Schematic Diagram (Pin P61).....................................................................100
Port 6 Schematic Diagram (Pin P66).....................................................................101
Port 6 Schematic Diagram (Pin P67).....................................................................102
Port 7 Schematic Diagram.....................................................................................103
Port 8 Schematic Diagram (Pin P80).....................................................................108
Port 8 Schematic Diagram (Pin P81).....................................................................109
Port 8 Schematic Diagram (Pins P82 and P83)...................................................... 110
Port 8 Schematic Diagram (Pin P84)..................................................................... 111
Port 8 Schematic Diagram (Pin P85)..................................................................... 112
Port 8 Schematic Diagram (Pin P86)..................................................................... 113
Port 9 Schematic Diagram (Pin P90)..................................................................... 117
Port 9 Schematic Diagram (Pins P91 to P92) ........................................................ 118
Port 9 Schematic Diagram (Pins P93 and P94)...................................................... 119
Port 9 Schematic Diagram (Pin P95).....................................................................120
Port 9 Schematic Diagram (Pin P96).....................................................................121
Port 9 Schematic Diagram (Pin P97).....................................................................122
Figure 6-1
Figure 6-2
Figure 6-3
Block Diagram of 16-Bit Free-Running Timer.....................................................124
Input Capture Buffering ........................................................................................128
Minimum Input Capture Pulse Width ...................................................................128
Figure 6-4 (a) Write Access to FRC (When CPU Writes H'AA55).............................................138
Figure 6-4 (b) Read Access to FRC (When FRC Contains H'AA55) ..........................................139
Figure 6-5
Figure 6-6
Figure 6-7
Figure 6-8
Figure 6-9
Figure 6-10
Figure 6-11
Figure 6-12
Increment Timing for Internal Clock Source ........................................................140
Increment Timing for External Clock Source .......................................................140
Minimum External Clock Pulse Width .................................................................140
Setting of Output Compare Flags..........................................................................141
Clearing of Output Compare Flag.........................................................................141
Timing of Output Compare A ...............................................................................142
Clearing of FRC by Compare-Match A................................................................142
Input Capture Timing (Usual Case) ......................................................................143
xii
Figure 6-13
Figure 6-14
Figure 6-15
Figure 6-16
Figure 6-17
Figure 6-18
Figure 6-19
Figure 6-20
Figure 6-21
Figure 6-22
Figure 6-23
Input Capture Timing (1-State Delay)...................................................................143
Input Capture Timing (1-State Delay, Buffer Mode) ............................................143
Buffered Input Capture with Both Edges Selected ...............................................144
Setting of Input Capture Flag................................................................................144
Clearing of Input Capture Flag..............................................................................145
Setting of Overflow Flag (OVF)...........................................................................145
Clearing of Overflow Flag ....................................................................................145
Square-Wave Output (Example) ...........................................................................146
FRC Write-Clear Contention.................................................................................147
FRC Write-Increment Contention.........................................................................148
Contention between OCR Write and Compare-Match..........................................149
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10
Figure 7-11
Figure 7-12
Figure 7-13
Figure 7-14
Figure 7-15
Block Diagram of 8-Bit Timer..............................................................................154
Count Timing for Internal Clock Input .................................................................160
Count Timing for External Clock Input ................................................................161
Minimum External Clock Pulse Widths................................................................161
Setting of Compare-Match Flags ..........................................................................162
Clearing of Compare-Match Flags........................................................................162
Timing of Timer Output ........................................................................................163
Timing of Compare-Match Clear..........................................................................163
Timing of External Reset ......................................................................................164
Setting of Overflow Flag (OVF)...........................................................................164
Clearing of Overflow Flag ....................................................................................165
Example of Pulse Output.......................................................................................166
TCNT Write-Clear Contention..............................................................................166
TCNT Write-Increment Contention ......................................................................167
Contention between TCOR Write and Compare-Match .......................................168
Figure 8-1
Figure 8-2
Figure 8-3
Block Diagram of PWM Timer.............................................................................171
TCNT Increment Timing.......................................................................................175
PWM Timing.........................................................................................................176
Figure 9-1
Figure 9-2
Figure 9-3
Figure 9-4
Figure 9-5
Figure 9-6
Block Diagram of Serial Communication Interface..............................................180
Data Format in Asynchronous Mode ....................................................................194
Phase Relationship Between Clock Output and Transmit Data............................195
Data Format in Synchronous Mode ......................................................................199
Timing of Interrupt Signal.....................................................................................203
Sampling Timing (Asynchronous Mode)..............................................................205
xiii
Figure 10-1
Figure 10-2
Figure 10-3
Figure 10-4
Figure 10-5
Figure 10-6
Block Diagram of A/D Converter.........................................................................208
The Response of the A/D Converter .....................................................................214
A/D Operation in Single Mode (When Channel 1 is Selected).............................216
A/D Operation in Scan Mode (When Channel 0 to 2 are Selected)......................219
A/D Conversion Timing........................................................................................221
External Trigger Input Timing ..............................................................................222
Figure 11-1
Figure 11-2
Figure 11-3
Figure 11-4
Block Diagram of Dual-Port RAM.......................................................................226
Parallel Communication Data Register 0..............................................................230
Dual-Port RAM Timing Chart ..............................................................................236
Interconnection to H8/532 (Example)...................................................................237
Figure 12-1
Block Diagram of On-Chip RAM.........................................................................239
Figure 13-1
Figure 13-2
Figure 13-3
Figure 13-4
Figure 13-5
Figure 13-6
Block Diagram of On-Chip ROM.........................................................................242
Socket Adapter Pin Assignments..........................................................................244
Memory Map in PROM Mode..............................................................................245
High-Speed Programming Flowchart....................................................................246
PROM Write/Verify Timing..................................................................................248
Recommended Screening Procedure.....................................................................249
Figure 14-1
Figure 14-2
Software Standby Mode (when) NMI Timing ......................................................258
Hardware Standby Mode Timing..........................................................................260
Figure 15-1
Figure 15-2
Execution Cycle of Instruction Synchronized with E Clock in
Expanded Modes (Maximum Synchronization Delay).........................................262
Execution Cycle of Instruction Synchronized with E Clock in
Expanded Modes (Minimum Synchronization Delay)..........................................263
Figure 16-1
Figure 16-2
Figure 16-3
Figure 16-4
Figure 16-5
Figure 16-6
Block Diagram of Clock Pulse Generator.............................................................265
Connection of Crystal Oscillator (Example).........................................................266
Equivalent Circuit of External Crystal..................................................................266
Notes on Board Design around External Crystal ..................................................267
External Clock Input (Example) ...........................................................................267
Phase Relationship of System Clock and E Clock................................................268
Figure 17-1
Figure 17-2
Example of Circuit for Driving a Darlington Pair.................................................272
Example of Circuit for Driving a LED..................................................................272
xiv
Figure 17-3
Figure 17-4
Figure 17-5
Figure 17-6
Figure 17-7
Figure 17-8
Figure 17-9
Output Load Circuit ..............................................................................................277
Basic Bus Cycle (Without Wait States) in Expanded Modes................................278
Basic Bus Cycle (Without 1 Wait States) in Expanded Modes.............................279
E Clock Bus Cycle ................................................................................................280
Reset Input Timing................................................................................................280
Interrupt Input Timing...........................................................................................281
Clock Settling Timing ...........................................................................................282
Figure 17-10 Clock Settling Timing for Recovery from Software Standby Mode.....................283
Figure 17-11 Free-Running Timer Input/Output Timing............................................................283
Figure 17-12 External Clock Input Timing for Free-Running Timer .........................................284
Figure 17-13 8-Bit Timer Output Timing ...................................................................................284
Figure 17-14 8-Bit Timer Clock Input Timing ...........................................................................284
Figure 17-15 8-Bit Timer Reset Input Timing............................................................................285
Figure 17-16 PWM Timer Output Timing..................................................................................285
Figure 17-17 SCI Input/Output Timing (Synchronous Mode) ...................................................285
Figure 17-18 SCI Input Clock Timing........................................................................................286
Figure 17-19 I/O Port Input/Output Timing................................................................................286
Figure 17-20 Dual-Port RAM Read Timing...............................................................................287
Figure 17-21 Dual-Port RAM Write Timing ..............................................................................288
Appendix E-1 Package Dimensions (CG-84)...............................................................................340
Appendix E-2 Package Dimensions (CP-84)................................................................................340
Appendix E-3 Package Dimensions (FP-80A).............................................................................341
xv
Section 1. Overview
The H8/330 is a single-chip microcomputer with an H8/300 CPU core and a complement of on-
chip supporting modules. A variety of system functions are integrated onto the H8/330 chip.
The H8/300 CPU is a high-speed Hitachi-original processor with an architecture featuring powerful
bit-manipulation instructions, ideally suited for realtime control applications. The on-chip
supporting modules include 16K bytes of ROM, 512 bytes of RAM, a 16-bit free-running timer,
two 8-bit timers, two PWM timers, a serial communication interface, an A/D converter, dual-port
RAM, and I/O ports.
The H8/330 can operate in single-chip mode or in two expanded modes, depending on the memory
requirements of the application. The operating mode is referred to in this manual as the MCU
mode (MCU: MicroComputer Unit).
The H8/330 is available in a masked ROM version, in an electrically programmable ROM version
that can be programmed at the user site, or in a version with no ROM. The no-ROM version can be
used only in mode 1.
Section 1.1 shows a block diagram of the H8/330. Section 1.2 describes the main features of the
blocks. Section 1.3 shows the pin layout and describes the pin functions.
1
1.1 Block Diagram
Figure 1-1 shows a block diagram of the H8/330 chip.
*
P1
P1
P1
P1
P1
P1
P1
P1
0
/A
/A
/A
/A
/A
/A
/A
/A
0
P9
P9
P9
P9
P9
P95
P96
P97
0
/IRQ
/IRQ
/IRQ
/CS/RD
2
/ADTRG
Clock
pulse
gener-
ator
1
1
1
1
CPU
H8/300
2
2
2
0
3
3
3
4
4
4/OE/WR
5
5
/RDY/AS
/Ø
/WE/WAIT
Data bus (Low)
RAM
6
6
7
7
PROM (or
masked
ROM) 16K
bytes
P2
P2
P2
P2
0
/A
/A
8
P3
P3
P3
P3
P3
P3
P3
P3
0
/DDB
/DDB
/DDB
/DDB
/DDB
/DDB
/DDB
/DDB
0
/D
/D
/D
/D
/D
/D
/D
/D
0
512 bytes
1
9
1
1
1
2/A10
2
2
2
3/A11
Dual-port
RAM
3
3
3
P24/A12
4
4
4
P25/A13
5
5
5
P26/A14
6
6
6
Serial
communication
(8 channels)
16-Bit
free-running
timer
P27/A15
7
7
7
P6
P6 /FTOA
P6 /FTIA
P6
0/FTCI
P8
P8
P8
P8
P8
P8
P8
0
/RS
/RS
/RS
/RS
/CTxD/IRQ
/CRxD/IRQ
/CSCK/IRQ
0/E
1
1
1/IOS
8-Bit timer
(2channels)
2
2
2
8-Bit A/D
converter
(8 channels)
3/FTIB
3
3
P64/FTIC
4
3
PWM timer
(2channels)
P65/FTID
5
4
P66
/FTOB/IRQ
6
6
5
P6 /IRQ
7
7
Port 5
Port 4
Port 7
* CP-84, CG-84
Figure 1-1. Block Diagram
2
1.2 Descriptions of Blocks
CPU: The CPU has a high-speed-oriented architecture in which operands are located in general registers.
•
Two-way general register configuration
-
-
Eight 16-bit registers, or
Sixteen 8-bit registers
•
Streamlined instruction set
-
-
Instruction length: 2 or 4 bytes
Register-register arithmetic, logic, and shift operations, including:
-
-
8 × 8-bit multiply
16 ÷ 8-bit divide
-
-
Extensive bit-manipulation instructions, featuring:
-
-
Bit accumulator
Register-indirect specification of bit positions
Maximum clock rate: 10MHz
-
-
Register-register add or subtract: 0.2µs
Register-register multiply or divide: 1.4µs
ROM: The 16K-byte on-chip ROM is accessed in two states via a 16-bit bus. Three versions are
available:
•
•
•
Masked ROM
Electrically programmable ROM, programmable with a standard PROM writer
No ROM
RAM: The 512-byte on-chip RAM is accessed in two states via a 16-bit bus. RAM contents are
held in the power-down state.
Dual-Port RAM: In single-chip mode, the 15 bytes of dual-port memory can be accessed by both
the on-chip CPU and an external CPU for convenient parallel data transfer in master-slave systems.
Serial Communication Interface: The single serial I/O channel offers:
•
•
•
•
Synchronous or asynchronous communication
Separate input/output pins for the synchronous and asynchronous modes
An on-chip baud rate generator supporting up to megabit-per-second speeds
Serial clock input or output
3
A/D Converter: A/D conversion can be performed in single or scan mode.
•
•
•
•
Eight-bit resolution
Eight input channels; selection of single mode or scan mode
Conversion can be started by an external trigger signal
Sample-and-hold
I/O Ports: Pins not used for other functions are available for general-purpose input and output.
I/O is memory-mapped, with the CPU reading and writing the port registers in three states via an 8-
bit internal bus.
•
•
58 Input/output pins (including 16 pins with LED driving capability)
8 Input-only pins
Interrupts: With a 10MHz clock rate, interrupt response times are on the order of 2 or 3µs (when
the vector table and stack are located in on-chip memory).
•
•
9 External interrupts: NMI and IRQ0 to IRQ7
19 Internal interrupts
Free-Running Timer: The time base is a 16-bit free-running counter that can be internally or
externally clocked. Applications range from programmable pulse output to counting or timing of
external events.
•
•
•
Two independent, comparator-controlled outputs
Four input capture channels
Input capture buffering
8-Bit Timers: Two independent 8-bit timers support applications such as programmable pulse
output and external event counting.
•
•
Internal or external clocking
Output controlled by values in two compare registers
PWM Timers: Two independent timers are provided for pulse-width modulated output. Duty
cycles from 0 to 100% can be selected with 1/250 resolution.
Power-Down State: In the three power-down modes some or all chip functions are halted but
memory contents are retained.
•
•
•
Sleep mode: CPU halts to save power while waiting for an interrupt
Software standby mode: entire chip halts to save power while waiting for an external interrupt
Hardware standby mode: totally shut down, but on-chip RAM contents are held
4
Clock Pulse Generator: The H8/330 can generate its system clock from a crystal oscillator, or can
input an external clock signal.
E-Clock Interface: An E clock can be output for interfacing to peripheral devices.
MCU Modes: The H8/330 has three operating modes:
•
•
•
Mode 1: Expanded mode, on-chip ROM disabled
Mode 2: Expanded mode, on-chip ROM enabled
Mode 3: Single-chip mode
Product Lineup: A selection is offered of 80- or 84-pin packages with PROM or masked ROM.
See table 1-1. The windowed PROM version is UV-erasable.
Table 1-1. Product Lineup
Product code
HD6473308F
HD6473308CP
HD6473308CG
HD6433308F
HD6433308CP
HD6413308CP
HD6413308F
Package
On-chip ROM
PROM
80-Pin QFP (FP-80A)
84-Pin PLCC (CP-84)
84-Pin windowed LCC (CG-84)
80-Pin QFP (FP-80A)
84-Pin PLCC (CP-84)
84-Pin PLCC (CP-84)
80-Pin QFP (FP-80A)
Masked ROM
No ROM
5
1.3 Pin Assignments and Functions
1.3.1 Pin Arrangement
Figure 1-2 shows the pin arrangement of the FP-80A package. Figure 1-3 shows the pin
arrangement of the CP-84 package. Figure 1-4 shows the pin arrangement of the CG-84 package.
RES
XTAL
1
2
3
4
5
6
7
P14/A4
60
59
58
57
56
55
54
P15/A5
EXTAL
P16/A6
MD1
P17/A7
MD0
VSS
NMI
P20/A8
STBY
P21/A9
VCC
8
9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
VCC
53
52
P52/ASCK
P51/ARxD
P50/ATxD
VSS
10
11
12
13
14
15
16
17
18
51
50
49
48
47
46
45
44
43
P97/WE/WAIT
P96/Ø
P95/RDY/AS
P94/OE/WR
P93/CS/RD
P92/IRQ0
P91/IRQ1
P90/IRQ2/ADTRG
P47/PW1
P46/PW0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI1
19
20
42
41
Figure 1-2. Pin Arrangement (FP-80A, Top View)
6
RES
XTAL
74
73
72
71
70
69
68
P14/A4
12
13
14
15
16
17
18
P15/A5
EXTAL
P16/A6
MD1
P17/A7
MD0
VSS
NMI
P20/A8
STBY
P21/A9
VCC
67
66
P22/A10
P23/A11
P24/A12
VSS
19
20
P52/ASCK
P51/ARxD
P50/ATxD
VSS
65
64
63
62
61
60
59
58
57
21
22
23
24
25
26
27
28
29
P25/A13
P26/A14
P27/A15
VCC
VSS
P97/WE/WAIT
P96/Ø
P95/RDY/AS
P94/OE/WR
P93/CS/RD
P92/IRQ0
P91/IRQ1
P90/IRQ2/ADTRG
P47/PW1
P46/PW0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0
56
55
54
30
31
32
Figure 1-3. Pin Arrangement (CP-84, Top View)
7
RES
XTAL
74
73
72
71
70
69
68
P14/A4
12
13
14
15
16
17
18
P15/A5
EXTAL
P16/A6
MD1
P17/A7
MD0
VSS
NMI
P20/A8
STBY
P21/A9
VCC
67
66
P22/A10
P23/A11
P24/A12
VSS
19
20
P52/ASCK
P51/ARxD
P50/ATxD
VSS
65
64
63
62
61
60
59
58
57
21
22
23
24
25
26
27
28
29
P25/A13
P26/A14
P27/A15
VCC
VSS
P97/WE/WAIT
P96/Ø
P95/RDY/AS
P94/OE/WR
P93/CS/RD
P92/IRQ0
P91/IRQ1
P90/IRQ2/ADTRG
P47/PW1
P46/PW0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0
56
55
54
30
31
32
Figure 1-4. Pin Arrangement (CG-84, Top View)
8
1.3.2 Pin Functions
(1) Pin Assignments in Each Operating Mode: Table 1-2 lists the assignments of the pins of the
FP-80A, CP-84, and CG-84 packages in each operating mode.
The PROM mode is a non-operating mode used for programming the on-chip ROM. See section
13, “ROM” for details.
Table 1-2. Pin Assignments in Each Operating Mode (1)
Pin No.
Single-chip mode (mode 3)
Expanded modes
(modes 1 and 2)
CP-84 FP
DPRAM
DPRAM
enabled
DDB6
PROM
mode
EO6
VSS
EO7
VSS
VCC
VCC
NC
CG-84 -80A disabled
1
2
71
—
72
73
74
75
76
77
78
79
80
1
P36
D6
VSS
VSS
VSS
3
P37
DDB7
D7
4
VSS
VSS
VSS
5
P80
RS0
P80* / E
P81* /IOS
P82
6
P81
RS1
7
P82
RS2
8
P83
RS3
P83
NC
9
P84 / CTxD /IRQ3
P85 / CRxD /IRQ4
P86 / CSCK /IRQ5
RES
P84 / CTxD /IRQ3
P85 / CRxD /IRQ4
P86 / CSCK /IRQ5
RES
P84 / CTxD /IRQ3
P85 / CRxD /IRQ4
P86 / CSCK /IRQ5
RES
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
VPP
NC
2
XTAL
XTAL
XTAL
3
EXTAL
MD1
EXTAL
MD1
EXTAL
MD1
NC
4
VSS
VSS
EA9
VSS
VCC
NC
5
MD0
MD0
MD0
6
NMI
NMI
NMI
7
STBY
STBY
STBY
8
VCC
VCC
VCC
9
P52 / ASCK
P51 / ARxD
P50 / ATxD
P52 / ASCK
P51 / ARxD
P50 / ATxD
P52 / ASCK
P51 / ARxD
P50 / ATxD
10
11
NC
NC
Note: Pins marked NC should be left unconnected.
*Input port only
9
Table 1-2. Pin Assignments in Each Operating Mode (2)
Pin No.
Single-chip mode (mode 3)
Expanded modes
(modes 1 and 2)
CP-84 FP
DPRAM
DPRAM
enabled
VSS
PROM
mode
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VCC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
NC
NC
CG-84 -80A disabled
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
12
—
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
—
29
30
31
32
33
34
35
36
37
38
39
40
VSS
VSS
VSS
VSS
VSS
P97
WE
WAIT
Ø
P96 * / Ø
P95
P96 * / Ø
RDY
AS
P94
OE
WR
P93
CS
RD
P92 / IRQ0
P91 / IRQ1
P92 / IRQ0
P91 / IRQ1
P92 / IRQ0
P91 / IRQ1
P90 / ADTRG / IRQ2 P90 / ADTRG / IRQ2 P90 / ADTRG / IRQ2
P60 / FTCI
P61 / FTOA
P62 / FTIA
P63 / FTIB
P64 / FTIC
P65 / FTID
P66 / FTOB /IRQ6
P67 /IRQ7
VSS
P60 / FTCI
P61 / FTOA
P62 / FTIA
P63 / FTIB
P64 / FTIC
P65 / FTID
P66 / FTOB /IRQ6
P67 /IRQ7
VSS
P60 / FTCI
P61 / FTOA
P62 / FTIA
P63 / FTIB
P64 / FTIC
P65 / FTID
P66 / FTOB /IRQ6
P67 /IRQ7
VSS
AVCC
AVCC
AVCC
P70 / AN0
P71 / AN1
P72 / AN2
P73 / AN3
P74 / AN4
P75 / AN5
P76 / AN6
P77 / AN7
AVSS
P70 / AN0
P71 / AN1
P72 / AN2
P73 / AN3
P74 / AN4
P75 / AN5
P76 / AN6
P77 / AN7
AVSS
P70 / AN0
P71 / AN1
P72 / AN2
P73 / AN3
P74 / AN4
P75 / AN5
P76 / AN6
P77 / AN7
AVSS
P40 / TMCI0
P41 / TMO0
P40 / TMCI0
P41 / TMO0
P40 / TMCI0
P41 / TMO0
Note: Pins marked NC should be left unconnected.
*Input port only
10
Table 1-2. Pin Assignments in Each Operating Mode (3)
Pin No.
Single-chip mode (mode 3)
Expanded modes
(modes 1 and 2)
CP-84 FP
DPRAM
DPRAM
enabled
P42 / TMRI0
P43 / TMCI1
P44 / TMO1
P45 / TMRI1
P46 / PW0
P47 / PW1
VCC
PROM
mode
NC
CG-84 -80A disabled
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
41
42
43
44
45
46
47
48
49
50
—
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
P42 / TMRI0
P43 / TMCI1
P44 / TMO1
P45 / TMRI1
P46 / PW0
P47 / PW1
VCC
P42 / TMRI0
P43 / TMCI1
P44 / TMO1
P45 / TMRI1
P46 / PW0
NC
NC
NC
NC
P47 / PW1
NC
VCC
VCC
CE
P27
P27
A15 P27* / A15
A14 P26* / A14
A13 P25* / A13
VSS VSS
P26
P26
EA14
EA13
VSS
P25
P25
VSS
VSS
P24
P24
A12 P24* / A12
A11 P23* / A11
A10 P22* / A10
EA12
EA11
EA10
OE
P23
P23
P22
P22
P21
P21
A9
A8
P21* / A9
P20* / A8
P20
P20
EA8
VSS
VSS
VSS
VSS VSS
P17
P17
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D4
D5
P17* / A7
EA7
EA6
EA5
EA4
EA3
EA2
EA1
EA0
EO0
EO1
EO2
EO3
EO4
EO5
P16
P16
P16* / A6
P15* / A5
P14* / A4
P13* / A3
P12* / A2
P11* / A1
P10* / A0
D0
P15
P15
P14
P14
P13
P13
P12
P12
P11
P11
P10
P10
P30
DDB0
DDB1
DDB2
DDB3
DDB4
DDB5
P31
D1
P32
D2
P33
D3
P34
D4
P35
D5
Note: Pins marked NC should be left unconnected.
*Input port only
11
(2) Pin Functions: Table 1-3 gives a concise description of the function of each pin.
Table 1-3. Pin Functions (1)
Type
Symbol
I/O
Name and function
Power
VCC
I
Power: Connected to the power supply (+5V). Connect both VCC
pins to the system power supply (+5V).
VSS
I
I
Ground: Connected to ground (0V). Connect all VSS pins to the
system power supply (0V).
Clock
XTAL
Crystal: Connected to a crystal oscillator. The crystal frequency
should be double the desired system clock frequency. If an
external clock is input at the EXTAL pin, a reverse-phase clock
should be input at the XTAL pin.
EXTAL
I
External crystal: Connected to a crystal oscillator or external
clock. The frequency of the external clock should be double the
desired system clock frequency. See Section 16.2, “Oscillator
Circuit” for examples of connections to a crystal and external
clock.
Ø
E
O
O
System clock: Supplies the system clock to peripheral devices.
Enable clock: Supplies an E clock to E clock based peripheral
devices.
System
control
RES
I
I
Reset: A Low input causes the H8/330 chip to reset.
Standby: A transition to the hardware standby mode
(a power-down state) occurs when a Low input is received at the
STBY pin.
STBY
Address
bus
A15 to A0 O
Address bus: Address output pins.
12
Table 1-3. Pin Functions (2)
Type
Symbol
I/O
Name and function
Data bus D7 to D0 I/O
Data bus: 8-Bit bidirectional data bus.
Bus
WAIT
RD
I
Wait: Requests the CPU to insert TW states into the bus cycle
when an off-chip address is accessed.
control
O
O
O
O
Read: Goes Low to indicate that the CPU is reading an external
address.
WR
AS
Write: Goes Low to indicate that the CPU is writing to an
external address.
Address Strobe: Goes Low to indicate that there is a valid
address on the address bus.
IOS
I/O Select: Goes Low when the CPU accesses addresses H’FF00
to H’FFFF. Can be used as a chip select signal replacing the upper
8 bits of the address bus when external devices are mapped onto
addresses H’FF80 to H’FF8F and H’FFA8 to H’FFAF.
NonMaskable Interrupt: Highest-priority interrupt request.
The NMIEG bit in the system control register determines whether
the interrupt is requested on the rising or falling edge of the NMI
input.
Interrupt NMI
signals
I
IRQ0 to
I
I
Interrupt Request 0 to 7: Maskable interrupt request pins.
IRQ7
Operating MD1,
Mode: Input pins for setting the MCU operating mode
mode
MD0
according to the table below.
control
MD1
MD0
Mode
Description
0
1
Mode 1
Expanded mode with
on-chip ROM disabled
Expanded mode with
on-chip ROM enabled
Single-chip mode
1
1
0
1
Mode 2
Mode 3
The inputs at these pins are latched in mode select bits 1 to 0
(MDS1 and MDS0) of the mode register (MDCR) on the rising
edge of the RES signal.
13
Table 1-3. Pin Functions (3)
Type Symbol I/O Name and function
Serial com- ATxD
munication
O
Asynchronous Transmit Data: Asynchronous data output
pin for the serial communication interface.
interface
ARxD
ASCK
CTxD
CRxD
CSCK
I
Asynchronous Receive Data: Asynchronous data input pin for
the serial communication interface.
I/O Asynchronous Serial ClocK: Input/output pin for the
asynchronous serial clock.
O
I
Clock-synchronized Transmit Data: Synchronous data output
pin for the serial communication interface.
Clock-synchronized Receive Data: Synchronous data input pin
for the serial communication interface.
I/O Clock-synchronized Serial ClocK: Input/output pin for the
synchronous serial clock.
16-Bit free- FTOA,
O
FRT Output compare A and B: Output pins controlled by
running
timer
FTOB
comparators A and B of the free-running timer.
FTCI
I
FRT counter Clock Input: Input pin for an external clock
signal for the free-running timer.
FTIA to
FTID
I
FRT Input capture A to D: Input capture pins for the
free-running timer.
8-Bit
timer
TMO0,
TMO1
TMCI0,
TMCI1
TMRI0,
TMRI1
PW0,
O
I
8-bit TiMer Output: Compare-match output pins for the
8-bit timers.
8-bit TiMer counter Clock Input: External clock input pins
for the 8-bit timer counters.
I
8-bit TiMer counter Reset Input: A High input at these
pins resets the 8-bit timer counters.
PWM
timer
O
PWM timer output (channels 0 and 1): Pulse-width
modulation timer output pins.
PW1
A/D
AN7 to AN0 I
ANalog input: Analog signal input pins.
A/D Trigger: External trigger input for starting the A/D
converter.
converter
ADTRG
I
I
I
AVCC
Analog reference Voltage: Reference voltage pin for the A/D
converter.
AVSS
Analog ground: Ground pin for the A/D converter.
14
Table 1-3. Pin Functions (4)
Type
Dual-port DDB7
RAM to DDB0
Symbol
I/O Name and function
I/O Dual-port RAM Data Bus: Bidirectional 8-bit bus by which
an external CPU can access the dual-port RAM.
CS
I
Chip Select: Input pin for selecting the dual-port RAM.
Register Select: Input pins for addressing the dual-port RAM.
Output Enable: Enables output on DDB7 to DDB0.
Write Enable: Enables writing to the dual-port RAM.
ReaDY: For sending an interrupt request signal to an external
CPU. NMOS open-drain output.
RS3 to RS0
OE
I
I
WE
I
RDY
O
General- P17 to P10 I/O Port 1: An 8-bit input/output port with programmable MOS input
purpose
I/O
pull-ups and LED driving capability. The direction of each bit can
be selected in the port 1 data direction register (P1DDR).
P27 to P20 I/O Port 2: An 8-bit input/output port with programmable MOS input
pull-ups and LED driving capability. The direction of each bit can
be selected in the port 2 data direction register (P2DDR).
P37 to P30 I/O Port 3: An 8-bit input/output port with programmable MOS input
pull-ups. The direction of each bit can be selected in the port 3
data direction register (P3DDR).
P47 to P40 I/O Port 4: An 8-bit input/output port with programmable MOS input
pull-ups. The direction of each bit can be selected in the port 4
data direction register (P4DDR).
P52 to P50 I/O Port 5: A 3-bit input/output port with programmable MOS input
pull-ups. The direction of each bit can be selected in the port 5
data direction register (P5DDR).
P67 to P60 I/O Port 6: An 8-bit input/output port with programmable MOS input
pull-ups. The direction of each bit can be selected in the port 6
data direction register (P6DDR).
P77 to P70
I
Port 7: An 8-bit input port.
P86 to P80 I/O Port 8: A 7-bit input/output port with programmable MOS input
pull-ups. The direction of each bit can be selected in the port 8
data direction register (P8DDR).
P97 to P90 I/O Port 9: An 8-bit input/output port with programmable MOS input
pull-ups. The direction of each bit can be selected in the port 9
data direction register (P9DDR).
15
Section 2. MCU Operating Modes and Address Space
2.1 Overview
The H8/330 operates in three modes numbered 1, 2, and 3. An additional non-operating mode
(mode 0) is used for programming the PROM version of the chip. The mode is selected by the
inputs at the mode pins (MD1 and MD0) at the instant when the chip comes out of a reset. As
indicated in table 2-1, the mode determines the size of the address space and the usage of on-chip
ROM and on-chip RAM.
The no-ROM version (HD6413308) can operate only in mode 1 (expanded mode with on-chip
ROM disabled).
Table 2-1. Operating Modes
MD1
Low
Low
High
High
MD0
Low
High
Low
High
Mode
Address space
—
On-chip ROM
—
On-chip RAM
—
Mode 0
Mode 1
Mode 2
Mode 3
Expanded: 64KB
Expanded: 64KB
Single-chip: about 17KB
Disabled
Enabled
Enabled
Enabled*
Enabled*
Enabled
* In modes 1 and 2, external memory can be accessed instead of on-chip RAM by clearing the
RAME bit in the system control register (SYSCR) to "0."
Modes 1 and 2 are referred to as “expanded” because they permit access to off-chip memory
addresses.
17
2.2 Mode Descriptions
Mode 1 (Expanded Mode without On-Chip ROM): Mode 1 supports a 64K-byte address space
most of which is off-chip. In particular, the interrupt vector table is located in off-chip memory.
The on-chip ROM and dual-port RAM are not used. Software can select whether to use the on-chip
RAM. Ports 1 to 3, 8, and 9 are used for the address and data bus lines and control signals as
follows:
Ports 1 and 2:
Address bus
Data bus
Port 3:
Port 8 (pin 1), port 9 (pins 7, 5, 4, 3):
Bus control signals
Mode 2 (Expanded Mode with On-Chip ROM): Mode 2 supports a 64K-byte address space of
which the first 16K bytes are in on-chip ROM. Software can select whether or not to use the on-
chip RAM, and can select the usage of pins in ports 1 and 2.
Ports 1 and 2:
Address bus (see note)
Data bus
Port 3:
Port 8 (pin 1), port 9 (pins 7, 5, 4, 3):
Bus control signals
Note: In mode 2, ports 1 and 2 are initially general-purpose input ports. Software must change the
desired pins to output before using them for the address bus. See section 5, “I/O Ports” for
details.
Mode 3 (Single-Chip Mode): In this mode all memory is on-chip, in 16K bytes of ROM, 512
bytes of RAM, and internal I/O registers. If enabled by software, the dual-port RAM can be
accessed by an external CPU.
Since no off-chip memory is accessed, there is no address bus; ports 1 and 2 are available for
general-purpose input and output. When the dual-port RAM is enabled, ports 3, 8, and 9 are used
as follows:
Port 3:
Dual-port RAM data bus
Port 8 (pins 0 to 3):
Port 9 (pins 7, 5, 4, 3):
Dual-port RAM register select
Dual-port RAM interface signals
The mode in which the dual-port RAM is enabled is also called the slave mode.
18
2.3 Address Space Map
Figure 2-1 shows a memory map in each of the three operating modes. The on-chip register field
consists of control, status, and data registers for the on-chip supporting modules, I/O ports, and
dual-port RAM.
Off-chip addresses can be accessed only in the expanded modes. Access to an off-chip address in
the single-chip mode does not cause an address error, but all “1” data are returned.
2.3.1 Access Speed
On-chip ROM and RAM are accessed a word (16 bits) at a time in two states. (A “state” is one
system clock period.) The on-chip register field is accessed a byte at a time in three states.
External memory is accessed a byte at a time in three or more states. The basic bus cycle is three
states, but additional wait states can be inserted on request.
2.3.2 IOS
There are two small gaps in the on-chip address space above the on-chip RAM. Addresses H’FF80
to H’FF8F, situated between the on-chip RAM and register field, are off-chip. Addresses H’FFA8
to H’FFAF are also off-chip. These 24 addresses can be conveniently assigned to external I/O
devices.
To simplify the addressing of devices at these addresses, an IOS signal is provided that goes Low
when the CPU accesses addresses H’FF00 to H’FFFF. The IOS signal can be used in place of the
upper 8 bits of the address bus.
19
Mode 1 (on-chip ROM disabled)
H'0000
Mode 2 (on-chip ROM enabled)
H'0000
Mode 3 (single-chip mode)
H'0000
Vector table
Vector table
Vector table
H'003D
H'003E
H'003D
H'003E
H'003D
H'003E
On-chip ROM,
16K bytes
On-chip ROM,
16K bytes
H'3FFF
H'4000
H'3FFF
External address space
External address space
H'FD7F
H'FD80
H'FD7F
H'FD80
H'FD80
H'FF7F
On-chip RAM,
512 bytes*
On-chip RAM,
512 bytes*
On-chip RAM,
512 bytes
H'FF7F
H'FF7F
H'FF80
H'FF80
External address space
External address space
H'FF8F
H'FF8F
H'FF90
H'FF90
H'FF90
H'FFA7
On-chip register field
H'FFA7
On-chip register field
H'FFA7
On-chip register field
On-chip register field
H'FFA8
H'FFA8
External address space
H'FFAF
External address space
H'FFAF
H'FFB0
H'FFB0
H'FFB0
H'FFFF
On-chip register field
H'FFFF
On-chip register field
H'FFFF
Figure 2-1. Address Space Map
* External memory can be accessed at these addresses when the RAME bit in the system control
register (SYSCR) is cleared to "0".
20
2.4 Mode and System Control Registers (MDCR and SYSCR)
Two of the control registers in the register field are the mode control register (MDCR) and system
control register (SYSCR). The mode control register controls the MCU mode: the operating mode
of the H8/330 chip. The system control register has bits that enable or disable the on-chip RAM
and dual-port RAM. Table 2-2 lists the attributes of these registers.
Table 2-2. Mode and System Control Registers
Name
Abbreviation
MDCR
Read/Write
Address
H’FFC5
H’FFC4
Mode control register
System control register
R
SYSCR
R/W
2.4.1 Mode Control Register (MDCR) – H’FFC5
Bit
7
—
1
6
—
1
5
—
1
4
—
0
3
—
0
2
—
1
1
0
MDS1 MDS0
Initial value
Read/Write
*
*
—
—
—
—
—
—
R
R
*
Initialized according to MD1 and MD0 inputs.
Bits 7 to 5 and 2—Reserved: These bits cannot be modified and are always read as “1.”
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as “0.”
Bits 1 and 0—Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the
mode pins (MD1 and MD0) latched on the rising edge of the RES signal. These bits can be read but
not written.
Coding example: To test whether the MCU is operating in mode 1:
MOV.B @H’FFC5, R0L
CMP.B #H’E5, R0L
The comparison is with H’E5 instead of H’01 because bits 7, 6, 5, and 2 are always read as “1.”
21
2.4.2 System Control Register (SYSCR) – H’FFC4
By setting or clearing the lower two bits of the system control register, software can enable or
disable the on-chip RAM and dual-port RAM.
The other bits in the system control register concern the software standby mode and the valid edge
of the NMI signal. These bits will be described in section 4, “Exception Handling” and section 14,
“Power-Down State.”
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
—
1
2
1
0
NMIEG DPME RAME
Initial value
Read/Write
0
0
1
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
Bit 1—Dual-Port RAM Enable (DPME): In the single-chip mode, this bit enables or disables the
dual-port RAM. When enabled, the dual-port RAM can be accessed by both an external (master)
CPU and the on-chip (slave) CPU. When disabled, the dual-port RAM can be accessed only by the
on-chip CPU.
This bit affects the usage of ports 3, 8, and 9.
Bit 1
DPME
Description
0
1
The dual-port RAM is disabled. (Initial state)
Single-chip mode: The dual-port RAM is enabled (slave mode).
Expanded modes: The dual-port RAM is disabled (but can be accessed by the on-chip
CPU).
Bit 0—RAM Enable (RAME): This bit enables or disables the 512-byte on-chip RAM. When
enabled, the on-chip RAM occupies addresses H’FD80 to H’FF7F of the address space. When the
on-chip RAM is disabled, accesses to these addresses are directed off-chip.
The RAME bit is initialized to "1" by a reset, enabling the on-chip RAM. The setting of the
RAME bit is not altered in the sleep mode or software standby mode. It should be cleared to "0"
before entering the hardware standby mode. See section 14, "Power-Down State."
Bit 0
RAME
Description
0
1
The on-chip RAM is disabled.
The on-chip RAM is enabled.
(Initial state)
22
Coding Examples: To disable the on-chip RAM (in expanded modes):
BCLR #0, @H’FFC4
To enable the dual-port RAM (in single-chip mode):
BSET #1, @H’FFC4
23
Section 3. CPU
3.1 Overview
The H8/330 chip has the generic H8/300 CPU: an 8-bit central processing unit with a speed-
oriented architecture featuring sixteen general registers. This section describes the CPU features
and functions, including a concise description of the addressing modes and instruction set. For
further details on the instructions, see the H8/300 Series Programming Manual.
3.1.1 Features
The main features of the H8/300 CPU are listed below.
• Two-way register configuration
— Sixteen 8-bit general registers, or
— Eight 16-bit general registers
• Instruction set with 57 basic instructions, including:
— Multiply and divide instructions
— Powerful bit-manipulation instructions
• Eight addressing modes
— Register direct (Rn)
— Register indirect (@Rn)
— Register indirect with displacement (@(d:16, Rn))
— Register indirect with post-increment or pre-decrement (@Rn+ or @–Rn)
— Absolute address (@aa:8 or @aa:16)
— Immediate (#xx:8 or #xx:16)
— PC-relative (@(d:8, PC))
— Memory indirect (@@aa:8)
• Maximum 64K-byte address space
• High-speed operation
— All frequently-used instructions are executed two to four states
— The maximum clock rate is 10MHz
—
—
—
8- or 16-bit register-register add or subtract: 0.2µs
8 × 8-bit multiply:
1.4µs
1.4µs
16 ÷ 8-bit divide:
• Power-down mode
— SLEEP instruction
25
3.2 Register Configuration
Figure 3-1 shows the register structure of the CPU. There are two groups of registers: the general
registers and control registers.
7
07
0
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
(SP)
SP: Stack Pointer
15
0
PC
PC: Program Counter
7
5
3 2 1 0
I U H U N Z V C
CCR: Condition Code Register
Carryflag
CCR
Overflow flag
Zero flag
Negative flag
Half-carryflag
Interrupt mask bit
User bit
User bit
Figure 3-1. CPU Registers
3.2.1 General Registers
All the general registers can be used as both data registers and address registers. When used as
address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as
data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed
separately as 8-bit registers.
R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and
subroutine calls. In assembly-language coding, R7 can also be denoted by the letters SP. As
indicated in figure 3-2, R7 (SP) points to the top of the stack.
26
Unused area
Stack area
SP
(R7)
Figure 3-2. Stack Pointer
3.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
(1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the
CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit of the
PC is ignored (always regarded as 0).
(2) Condition Code Register (CCR): This 8-bit register contains internal status information,
including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the interrupt
mask bit (I).
Bit 7—Interrupt Mask Bit (I): When this bit is set to “1,” all interrupts except NMI are masked.
This bit is set to “1” automatically by a reset and at the start of interrupt handling.
Bit 6—User Bit (U): This bit can be written and read by software for its own purposes.
Bit 5—Half-Carry (H): This bit is set to “1” when the ADD.B, ADDX.B, SUB.B, SUBX.B,
NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to “0” otherwise.
Similarly, it is set to “1” when the ADD.W, SUB.W, or CMP.W instruction causes a carry or borrow
out of bit 11, and cleared to “0” otherwise. It is used implicitly in the DAA and DAS instructions.
Bit 4—User Bit (U): This bit can be written and read by software for its own purposes.
Bit 3—Negative (N): This bit indicates the most significant bit (sign bit) of the result of an
instruction.
27
Bit 2—Zero (Z): This bit is set to “1” to indicate a zero result and cleared to “0” to indicate a
nonzero result.
Bit 1—Overflow (V): This bit is set to “1” when an arithmetic overflow occurs, and cleared to
“0” at other times.
Bit 0—Carry (C): This bit is used by:
• Add and subtract instructions, to indicate a carry or borrow at the most significant bit of the
result
• Shift and rotate instructions, to store the value shifted out of the most significant or least
significant bit
• Bit manipulation and bit load instructions, as a bit accumulator
The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR,
and to set or clear selected bits by logic operations.
Some instructions leave some or all of the flag bits unchanged. The action of each instruction on
the flag bits is shown in Appendix A-1, “Instruction Set List.” See the H8/300 Series
Programming Manual for further details.
3.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt
mask bit (I) in the CCR is set to “1.” The other CCR bits and the general registers are not
initialized.
In particular, the stack pointer (R7) is not initialized. To prevent program crashes the stack pointer
should be initialized by software, by the first instruction executed after a reset.
28
3.3 Addressing Modes
The H8/330 supports eight addressing modes. Each instruction uses a subset of these addressing
modes.
(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand. In most cases the general register is accessed as an 8-bit register.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
(2) Register indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in MOV
instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4)
which is added to the contents of the specified general register to obtain the operand address. For
the MOV.W instruction, the resulting address must be even.
(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
•
Register indirect with Post-Increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is incremented after the operand is accessed. The size of the increment is
1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the
original contents of the 16-bit general register must be even.
•
Register Indirect with Pre-Decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is decremented before the operand is accessed. The size of the
decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For
MOV.W, the original contents of the 16-bit general register must be even.
(5) Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H’FFxx.
The upper 8 bits are assumed to be 1, so the possible address range is H’FF00 to H’FFFF (65280 to
65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses.
29
(6) Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or
a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit
immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit
manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the
instruction, specifying a bit number.
(7) PC-Relative—@(d:8, PC): This mode is used to generate branch addresses in the Bcc and
BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a sign-extended value
to the program counter contents. The result must be an even number. The possible branching
range is –126 to +128 bytes (–63 to +64 words) from the current address.
(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address from H’0000 to H’00FF (0 to
255). The word located at this address contains the branch address. Note that addresses H’0000 to
H’003D (0 to 61) are located in the vector table.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as “0,” causing word access to be performed at the
address preceding the specified address. See section 3.4.2, “Memory Data Formats” for further
information.
30
3.4 Data Formats
The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte
operand.
• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
• The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed
BCD form. Each nibble of the byte is treated as a decimal digit.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU
(16 bits ÷ 8 bits) instructions operate on word data.
31
3.4.1 Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 3-3.
Data type
Register No.
Data format
7
0
RnH
7 6 5 4 3 2 1 0
Don't-care
1-Bit data
7
0
Don't-care
1-Bit data
Byte data
Byte data
RnL
RnH
7 6 5 4 3 2 1 0
7
0
M
S
B
L
S
B
Don't-care
7
M
S
0
L
S
RnL
Rn
Don't-care
B
B
15
0
M
S
B
L
S
B
Word data
7
0
4 3
Upper digit Lower digit
RnH
RnL
Don't-care
4 3
4-Bit BCD data
4-Bit BCD data
7
0
Upper digit Lower digit
Don't-care
Figure 3-3. Register Data Formats
Note:
RnH: Upper digit of general register
RnL: Lower digit of general register
MSB: Most significant Bit
LSB: Least significant Bit
32
3.4.2 Memory Data Formats
Figure 3-4 indicates the data formats in memory.
Word data stored in memory must always begin at an even address. In word access the least
significant bit of the address is regarded as “0.” If an odd address is specified, no address error
occurs but the access is performed at the preceding even address. This rule affects MOV.W
instructions and branching instructions, and implies that only even addresses should be stored in the
vector table.
Data type
Address
Data format
7
0
7 6 5 4 3 2 1 0
Address n
Address n
1-Bit data
Byte data
M
S
B
L
S
B
M
S
B
Upper 8 bits
Lower 8 bits
Even address
Odd address
L
S
B
Word data
M
S
B
M
S
B
L
S
B
L
S
B
CCR
Even address
Odd address
Byte data (CCR) on stack
CCR*
M
S
B
Even address
Odd address
L
S
B
Word data on stack
CCR: Condition Code Register
*: Ignored when return
Figure 3-4. Memory Data Formats
The stack must always be accessed a word at a time. When the CCR is pushed on the stack, two
identical copies of the CCR are pushed to make a complete word. When they are returned, the
lower byte is ignored.
33
3.5 Instruction Set
Table 3-1 lists the H8/330 instruction set.
Table 3-1. Instruction Classification
Function
Instructions
Types
Data transfer
MOV, MOVTPE, MOVFPE, PUSH*1, POP*1
3
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, 14
DAA, DAS, MULXU, DIVXU, CMP, NEG
Logic operations
Shift
AND, OR, XOR, NOT
4
8
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
Bit manipulation
BSET, BCLR, BNOT, BTST,BAND, BIAND, BOR,
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST
Bcc*2, JMP, BSR, JSR, RTS
14
Branch
5
8
1
System control
Block data transfer
RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
EEPMOV
Total 57
*1
PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn.
*2
Bcc is a conditional branch instruction in which cc represents a condition code.
The following sections give a concise summary of the instructions in each category, and indicate
the bit patterns of their object code. The notation used is defined next.
34
Operation Notation
Rd
Rs
General register (destination)
General register (source)
#xx:16 16-Bit immediate data
op
disp
abs
B
Operation field
Displacement
Absolute address
Byte
Rn, Rm General register
General register field
rn, rm
<EAs> Effective address: general
register or memory location
W
+
Word
(EAd)
(EAs)
SP
Destination operand
Source operand
Addition
–
Subtraction
Multiplication
Division
Stack pointer
×
PC
Program counter
÷
CCR
N
Condition code register
N (negative) bit of CCR
Z (zero) bit of CCR
V (overflow) bit of CCR
C (carry) bit of CCR
Immediate data
AND logical
OR logical
Exclusive OR logical
Move
Z
V
→
↔
¬
C
Exchange
#imm
#xx:3
#xx:8
Not
3-Bit immediate data
8-Bit immediate data
cc
Condition field
35
3.5.1 Data Transfer Instructions
Table 3-2 describes the data transfer instructions. Figure 3-5 shows their object code formats.
Table 3-2. Data Transfer Instructions
Instruction
Size* Function
MOV
B/W (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @–Rn, and
@Rn+ addressing modes are available for byte or word data. The
@aa:8 addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not specify
byte size for these two modes.
MOVTPE
MOVFPE
PUSH
B
Rs → (EAd)
Transfers data from a general register to memory in synchronization
with the E clock.
B
(EAs) → Rd
Transfers data from memory to a general register in synchronization
with the E clock.
W
W
Rn → @–SP
Pushes a 16-bit general register onto the stack. Equivalent to MOV.W
Rn, @–SP.
POP
@SP+ → Rn
Pops a 16-bit general register from the stack. Equivalent to MOV.W
@SP+, Rn.
* Size: operand size
B: Byte
W: Word
36
15
8
7
0
MOV
r
r
→
Rn
Op
Op
Rm
m
n
r
r
→
→
Rn
@Rm, or @Rm
Rn
m
n
r
r
→
@(d:16, Rm)
Op
Rn, or
m
n
disp.
→
Rn
@(d:16, Rm)
r
r
→
→
@–Rm
Op
@Rm+
@aa:8
Rn, or Rn
→
Rn, or Rn @aa:8
m
n
r
→
Op
Op
abs.
n
r
→
Op
@aa:16
Rn, or
n
abs.
→
Rn
@aa:16
r
→
Rn
#imm.
#xx:8
n
r
→
Rn
Op
#xx:16
n
#imm.
r
Op
Op
MOVFPE, MOVTPE
MOVFPE: d = 0
MOVTPE: d = 1
n
abs.
r
n
PUSH, POP
Notation
Op:
Operation field
d:
Direction field (0–load from; 1–store to)
Register field
Displacement
r , r :
m n
disp.:
abs.:
Absolute address
#imm.:
Immediate data
Figure 3-5. Data Transfer Instruction Codes
37
3.5.2 Arithmetic Operations
Table 3-3 describes the arithmetic instructions. See figure 3-6 in section 3.5.4, “Shift Operations”
for their object codes.
Table 3-3. Arithmetic Instructions
Instruction
ADD
Size* Function
B/W Rd ± Rs → Rd, Rd + #imm → Rd
SUB
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data can
be added or subtracted only when both words are in general registers.
Rd ± Rs ± C → Rd, Rd ± #imm ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data and
data in a general register.
ADDX
SUBX
B
INC
B
Rd ± #1 → Rd
DEC
ADDS
SUBS
Increments or decrements a general register.
Rd ± #imm → Rd
Adds or subtracts immediate data to or from data in a general register.
The immediate data must be 1 or 2.
W
DAA
DAS
B
Rd decimal adjust → Rd
Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR.
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result.
MULXU
DIVXU
CMP
B
B
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.
Rd – Rs, Rd – #imm
B/W
Compares data in a general register with data in another general register
or with immediate data. Word data can be compared only between two
general registers.
NEG
B
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register.
* Size: operand size
B: Byte
W: Word
38
3.5.3 Logic Operations
Table 3-4 describes the four instructions that perform logic operations. See figure 3-6 in section
3.5.4, “Shift Operations” for their object codes.
Table 3-4. Logic Operation Instructions
Instruction
Size* Function
AND
B
B
B
B
Rd
Rs → Rd,
Rd
#imm → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
Rd
Rs → Rd,
Rd
#imm → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
NOT
Rd
Rs → Rd,
Rd #imm → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
¬ (Rd) → (Rd)
Obtains the one’s complement (logical complement) of general register
contents.
3.5.4 Shift Operations
Table 3-5 describes the eight shift instructions. Figure 3-6 shows the object code formats of the
arithmetic, logic, and shift instructions.
Table 3-5. Shift Instructions
Instruction
SHAL
Size* Function
B
B
B
B
Rd shift → Rd
SHAR
Performs an arithmetic shift operation on general register contents.
Rd shift → Rd
SHLL
SHLR
Performs a logical shift operation on general register contents.
Rd rotate → Rd
ROTL
ROTR
Rotates general register contents.
ROTXL
ROTXR
Rd rotate through carry → Rd
Rotates general register contents through the C (carry) bit.
* Size: operand size
B: Byte
39
15
8
7
0
Op
r
r
ADD, SUB, CMP
m
n
ADDX, SUBX, MULXU, DIVXU
Op
r
ADDS, SUBS, INC, DEC, DAA,
DAS, NEG, NOT
n
r
Op
#imm.
#imm.
ADD, ADDX, SUBX, CMP
(#xx:8)
n
r
r
Op
AND, OR, XOR (Rm)
m
n
Op
r
AND, OR, XOR (#xx:8)
n
r
Op
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
n
Notation
Op:
Operation field
Register field
Immediate data
r , r :
m n
#imm.:
Figure 3-6. Arithmetic, Logic, and Shift Instruction Codes
40
3.5.5 Bit Manipulations
Table 3-6 describes the bit-manipulation instructions. Figure 3-7 shows their object code formats.
Table 3-6. Bit-Manipulation Instructions (1)
Instruction
Size* Function
BSET
B
B
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to “1.” The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register.
BCLR
BNOT
BTST
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to “0.” The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register.
¬(<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register
B
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or clears
the Z flag accordingly. The bit is specified by a bit number, given in
3-bit immediate data or the lower three bits of a general register.
BAND
C
(<bit-No.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or memory.
[¬ (<bit-No.> of <EAd>)] → C
BIAND
C
ANDs the C flag with the inverse of a specified bit in a general register
or memory.
The bit number is specified by 3-bit immediate data.
BOR
B
B
C
(<bit-No.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory.
[¬ (<bit-No.> of <EAd>)] → C
BIOR
C
ORs the C flag with the inverse of a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
BXOR
C
(<bit-No.> of <EAd>) → C
XORs the C flag with a specified bit in a general register or memory.
* Size: operand size
B: Byte
41
Table 3-6. Bit-Manipulation Instructions (2)
Instruction
Size* Function
BIXOR
B
C
¬ [(<bit-No.> of <EAd>)] → C
XORs the C flag with the inverse of a specified bit in a general register
or memory.
The bit number is specified by 3-bit immediate data.
(<bit-No.> of <EAd>) → C
BLD
B
Copies a specified bit in a general register or memory to the C flag.
¬ (<bit-No.> of <EAd>) → C
BILD
Copies the inverse of a specified bit in a general register or memory to
the C flag.
The bit number is specified by 3-bit immediate data.
C → (<bit-No.> of <EAd>)
BST
B
Copies the C flag to a specified bit in a general register or memory.
¬ C → (<bit-No.> of <EAd>)
BIST
Copies the inverse of the C flag to a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
* Size: operand size
B: Byte
Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-modify-
write instructions. They read a byte of data, modify one bit in the byte, then write the byte back.
Care is required when these instructions are applied to registers with write-only bits and to the I/O
port registers.
Read
Read one data byte at the specified address
Modify one bit in the data byte
Modify
Write
Write the modified data byte back to the specified address
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under
the following conditions.
P47:
Input pin, Low, MOS pull-up transistor on
Input pin, High, MOS pull-up transistor off
Output pins, Low
P46:
P45 – P40:
The intended purpose of this BCLR instruction is to switch P40 from output to input.
42
Before Execution of BCLR Instruction
P47
Input
Low
0
P46
P45
P44
P43
P42
P41
P40
Input/output
Pin state
DDR
Input Output Output Output Output Output Output
High
0
Low
1
Low
1
Low
1
Low
1
Low
1
Low
1
DR
1
0
0
0
0
0
0
0
Pull-up Mos
On
Off
Off
Off
Off
Off
Off
Off
Execution of BCLR Instruction
;clear bit 0 in data direction register
After Execution of BCLR Instruction
BCLR.B #0, @P4DDR
P47
P46
P45
P44
P43
P42
P41
P40
Input/output
Pin state
DDR
Output Output Output Output Output Output Output Input
Low
1
High
1
Low
1
Low
1
Low
1
Low
1
Low
1
High
0
DR
1
0
0
0
0
0
0
0
Pull-up Mos
Off
Off
Off
Off
Off
Off
Off
Off
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to "0," making P40 an input pin. In addition, P47DDR and P46DDR
are set to "1," making P47 and P46 output pins.
Example 2: BSET is executed to set bit 0 in the port 4 data register (P4DR) under the following
conditions.
P47:
Input pin, Low, MOS pull-up transistor on
Input pin, High, MOS pull-up transistor off
Output pins, Low
P46:
P45 – P40:
The intended purpose of this BSET instruction is to switch the output level at P40 from Low to
High.
43
Before Execution of BSET Instruction
P47
Input
Low
0
P46
P45
P44
P43
P42
P41
P40
Input/output
Pin state
DDR
Input Output Output Output Output Output Output
High
0
Low
1
Low
1
Low
1
Low
1
Low
1
Low
1
DR
1
0
0
0
0
0
0
0
Pull-up Mos
On
Off
Off
Off
Off
Off
Off
Off
Execution of BSET Instruction
;set bit 0 in data register
After Execution of BSET Instruction
BSET.B #0, @PORT4
P47
Input
Low
0
P46
P45
P44
P43
P42
P41
P40
Input/output
Pin state
DDR
Input Output Output Output Output Output Output
High
0
Low
1
Low
1
Low
1
Low
1
Low
1
High
1
DR
0
1
0
0
0
0
0
1
Pull-up
Off
On
Off
Off
Off
Off
Off
Off
Explanation: To execute the BSET instruction, the CPU begins by reading port 4. Since P47 and
P46 are input pins, the CPU reads the level of these pins directly, not the value in the data register.
It reads P47 as Low ("0") and P46 as High ("1").
Since P45 to P40 are output pins, for these pins the CPU reads the value in the data register ("0").
The CPU therefore reads the value of port 4 as H'40, although the actual value in P4DR is H'80.
Next the CPU sets bit 0 of the read data to "1," changing the value to H'41.
Finally, the CPU writes this value (H'41) back to P4DR to complete the BSET instruction.
As a result, bit P40 is set to "1," switching pin P40 to High output. In addition, bits P47 and P46 are
both modified, changing the on/off settings of the MOS pull-up transistors of pins P47 and P46.
Programming Solution: The switching of the pull-ups for P47 and P46 in example 2 can be
avoided by reserving a byte in RAM as a temporary register for P4DR and using it as follows.
RAM0 is a symbol for the user-selected address of the temporary register.
44
Before Execution of BSET Instruction
MOV.B #80, R0L
;write data (H'80) for data register
MOV.B R0L, @RAM0
MOV.B R0L, @PORT4
;write to DR temporary register (RAM0)
;write to DR
P47
P46
P45
P44
P43
P42
P41
P40
Input/output
Pin state
DDR
Input
Low
0
Input Output Output Output Output Output Output
High
0
Low
1
Low
1
Low
1
Low
1
Low
1
Low
1
DR
1
0
0
0
0
0
0
0
Pull-up Mos
RAM0
On
1
Off
0
Off
0
Off
0
Off
0
Off
0
Off
0
Off
0
Execution of BSET Instruction
;set bit 0 in DR temporary register (RAM0)
After Execution of BSET Instruction
BSET.B #0, @RAM0
MOV.B @RAM0, R0L
;obtain value of temporary register RAM0
;write value to DR
MOV.B R0L, @PORT4
P47
P46
P45
P44
P43
P42
P41
P40
Input/output
Pin state
DDR
Input
Low
0
Input Output Output Output Output Output Output
High
0
Low
1
Low
1
Low
1
Low
1
Low
1
High
1
DR
1
0
0
0
0
0
0
1
Pull-up Mos
RAM0
On
1
Off
0
Off
0
Off
0
Off
0
Off
0
Off
0
Off
1
45
0
15
8
7
BSET, BCLR, BNOT, BTST
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
r
r
Op
#imm.
n
n
r
Op
Operand: register direct (Rn)
Bit No.: register direct (Rm)
m
Op
r
0
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
n
Op
#imm.
Op
Op
r
r
0
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: register direct (Rm)
n
m
Op
Op
abs.
0
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
#imm.
0
0
0
0
0
0
Op
Op
abs.
0
Operand: absolute (@aa:8)
Bit No.: register direct (Rm)
r
m
BAND, BOR, BXOR, BLD, BST
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
Op
r
n
#imm.
r
0
0
0
0
0 0
Op
Op
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
n
#imm.
0
0
Op
Op
abs.
0
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
#imm.
#imm.
0
0
0
BIAND, BIOR, BIXOR, BILD, BIST
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
Op
r
n
Op
Op
r
0
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
n
#imm.
Op
Op
abs.
0
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
0
0
0
#imm.
Notation
Op:
Operation field
Register field
Absolute address
Immediate data
r , r :
m
n
abs.:
#imm.:
Figure 3-7. Bit Manipulation Instruction Codes
46
3.5.6 Branching Instructions
Table 3-7 describes the branching instructions. Figure 3-8 shows their object code formats.
Table 3-7. Branching Instructions
Instruction
Size
Function
Bcc
—
Branches if condition cc is true.
Mnemonic
BRA (BT)
BRN (BF)
BHI
cc Field
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
Description
Always (True)
Never (False)
High
Condition
Always
Never
C
C
Z = 0
Z = 1
BLS
Low or Same
Carry Clear
(High or Same)
Carry Set (Low)
Not Equal
BCC (BHS)
C = 0
BCS (BLO)
BNE
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
BEQ
Equal
BVC
Overflow Clear
Overflow Set
Plus
BVS
BPL
BMI
Minus
BGE
Greater or Equal
Less Than
N
N
Z
Z
V = 0
BLT
V = 1
BGT
Greater Than
Less or Equal
(N V) = 0
(N V) = 1
BLE
JMP
JSR
BSR
—
—
—
Branches unconditionally to a specified address.
Branches to a subroutine at a specified address.
Branches to a subroutine at a specified displacement from the current
address.
RTS
—
Returns from a subroutine
47
15
8
7
0
0
Op
cc
disp.
Bcc
r
Op
m
0
0
0
JMP(@Rm)
JMP (@aa:16)
Op
abs.
Op
Op
Op
abs.
JMP (@@aa:8)
BSR
disp.
r
0
0
0
0
JSR(@Rm)
JSR (@aa:16)
m
Op
abs.
Op
abs.
JSR (@@aa:8)
RTS
Op
Notation
Op:
cc:
Operation field
Condition field
Register field
Displacement
Absolute address
r :
m
disp.:
abs.:
Figure 3-8. Branching Instruction Codes
48
3.5.7 System Control Instructions
Table 3-8 describes the system control instructions. Figure 3-9 shows their object code formats.
Table 3-8. System Control Instructions
Instruction
RTE
Size
—
—
B
Function
Returns from an exception-handling routine.
Causes a transition to the power-down state.
Rs → CCR, #imm → CCR
SLEEP
LDC
Moves immediate data or general register contents to the condition code
register.
STC
B
B
B
B
CCR → Rd
Copies the condition code register to a specified general register.
CCR #imm → CCR
ANDC
ORC
Logically ANDs the condition code register with immediate data.
CCR #imm → CCR
Logically ORs the condition code register with immediate data.
CCR #imm → CCR
XORC
Logically exclusive-ORs the condition code register with immediate
data.
NOP
—
PC + 2 → PC
Only increments the program counter.
* Size: operand size
B: Byte
49
15
8
7
0
Op
RTE, SLEEP, NOP
LDC, STC (Rn)
r
Op
n
Op
#imm.
ANDC, ORC, XORC, LDC
(#xx:8)
Notation
Op:
Operation field
Register field
Immediate data
r :
n
#imm.:
Figure 3-9. System Control Instruction Codes
3.5.8 Block Data Transfer Instruction
In the H8/330 the EEPMOV instruction is a block data transfer instruction. It does not have the
EEPROM write function it has in some other chips.
Table 3-9 describes the EEPMOV instruction. Figure 3-10 shows its object code format.
Table 3-9. Block Data Transfer Instruction/EEPROM Write Operation
Instruction
Size
Function
EEPMOV
—
if R4L ≠ 0 then
repeat @R5+ → @R6+
R4L – 1 → R4L
until
R4L = 0
else next;
Moves a data block according to parameters set in general registers R4L,
R5, and R6.
R4L: size of block (bytes)
R5:
R6:
starting source address
starting destination address
Execution of the next instruction starts as soon as the block transfer is
completed.
50
15
8
7
0
Op
Op
EEPROM
Notation
O : Operation field
P
Figure 3-10. Block Data Transfer Instruction/EEPROM Write Operation Code
Notes on EEPMOV Instruction
1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
→
R5
←
←
R6
R5 + R4L →
R6 + R4L
2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
R5 →
←
R6
→
R5 + R4L
H'FFFF
Not allowed
← R6 + R4L
3.6 CPU States
The CPU has three states: the program execution state, exception-handling state, and power-down
state. The power-down state is further divided into three modes: the sleep mode, software standby
mode, and hardware standby mode. Figure 3-11 summarizes these states, and figure 3-12 shows a
map of the state transitions.
State
Program execution state
The CPU executes successive program instructions.
Exception-handling state
A transient state triggered by a reset or interrupt. The CPU executes a hardware
sequence that includes loading the program counter from the vector table.
Power-down state
Sleep mode
A state in which some or all of the chip
functions are stopped to conserve power.
Software standby mode
Hardware standby mode
Figure 3-11. Operating States
51
SLEEP instruction
with SSBY bit set
Program
execution state
Exception
SLEEP
handling
instruction
request
Exception
handing
Exception -
handling state
Sleep mode
Interrupt request
NMI or IRQ0
to IRQ7
Software
standby mode
RES = 1
STBY=1 or RES=0
Hardware
standby mode
Reset state
Power-down state
Notes:
1. A transition to the reset state occurs when RES goes Low, except when the chip is in the hardware standby mode.
2. A transition from any state to the hardware standby mode occurs when STBY goes Low.
Figure 3-12. State Transitions
3.6.1 Program Execution State
In this state the CPU executes program instructions in sequence. The main program, subroutines,
and interrupt-handling routines are all executed in this state.
3.6.2 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or accepts an
interrupt. In this state the CPU carries out a hardware-controlled sequence that prepares it to
execute a user-coded exception-handling routine.
In the hardware exception-handling sequence the CPU does the following:
(1) Saves the program counter and condition code register to the stack (except in the case of a
reset).
(2) Sets the interrupt mask (I) bit in the condition code register to “1.”
(3) Fetches the start address of the exception-handling routine from the vector table.
(4) Branches to that address, returning to the program execution state.
See section 4, “Exception Handling,” for further information on the exception-handling state.
52
3.6.3 Power-Down State
The power-down state includes three modes: the sleep mode, the software standby mode, and the
hardware standby mode.
(1) Sleep Mode: The sleep mode is entered when a SLEEP instruction is executed. The CPU
halts, but CPU register contents remain unchanged and the on-chip supporting modules continue to
function.
When an interrupt or reset signal is received, the CPU returns through the exception-handling state
to the program execution state.
(2) Software Standby Mode: The software standby mode is entered if the SLEEP instruction is
executed while the SSBY (Software Standby) bit in the system control register (SYSCR) is set.
The CPU and all on-chip supporting modules halt. The on-chip supporting modules are initialized,
but the contents of the on-chip RAM and CPU registers remain unchanged. I/O port outputs also
remain unchanged.
(3) Hardware Standby Mode: The hardware standby mode is entered when the input at the
STBY pin goes Low. All chip functions halt, including I/O port output. The on-chip supporting
modules are initialized, but on-chip RAM contents are held.
See section 14, “Power-Down State” for further information.
3.7 Access Timing and Bus Cycle
The CPU is driven by the system clock (Ø). The period from one rising edge of the system clock to
the next is referred to as a “state.”
Memory access is performed in a two-or three-state bus cycle as described below. For more
detailed timing diagrams of the bus cycles, see section 17, “Electrical Specifications.”
3.7.1 Access to On-Chip Memory (RAM and ROM)
On-chip ROM and RAM are accessed in a cycle of two states designated T1 and T2. Either byte or
word data can be accessed, via a 16-bit data bus. Figure 3-13 shows the on-chip memory access
cycle. Figure 3-14 shows the associated pin states.
53
Bus cycle
T2 state
T1 state
Ø
Internal address bus
Internal Read signal
Internal data bus (read)
Address
Read data
Write data
Internal Write signal
Internal data bus (write)
Figure 3-13. On-Chip Memory Access Cycle
Bus cycle
T1 state
T2 state
Ø
Address bus
Address
AS: High
RD: High
WR: High
Data bus: high impedance state
Figure 3-14. Pin States during On-Chip Memory Access Cycle
54
3.7.2 Access to On-Chip Register Field and External Devices
The on-chip register field (I/O ports, dual-port RAM, on-chip supporting module registers, etc.) and
external devices are accessed in a cycle consisting of three states: T1, T2, and T3. Only one byte of
data can be accessed per cycle, via an 8-bit data bus. Access to word data or instruction codes
requires two consecutive cycles (six states).
Wait States: If requested, additional wait states (TW) are inserted between T2 and T3. The WAIT
pin is sampled at the center of state T2. If it is Low, a wait state is inserted after T2. The WAIT pin
is also sampled at the center of each wait state and if it is still Low, another wait state is inserted.
An external device can have any number of wait states inserted by holding WAIT Low for the
necessary duration.
The bus cycle for the MOVTPE and MOVFPE instructions will be described in section 15,
"E-Clock Interface."
Figure 3-15 shows the access cycle for the on-chip register field. Figure 3-16 shows the associated
pin states. Figures 3-17 (a) and (b) show the read and write access timing for external devices.
Bus cycle
T1 state
T2 state
T3 state
Ø
Internal address bus
Internal Read signal
Internal data bus (read)
Address
Read data
Internal Write signal
Write data
Internal data bus (write)
Figure 3-15. On-Chip Register Field Access Cycle
55
Bus cycle
T2 state
T1 state
T3 state
Ø
Address bus
AS: High
Address
RD: High
WR: High
Data bus: high impedance state
Figure 3-16. Pin States during On-Chip Register Field Access Cycle
Read cycle
T1 state
T2 state
T3 state
Ø
Address bus
Address
AS
RD
WR: High
Data bus
Read data
Figure 3-17 (a). External Device Access Timing (read)
56
Write cycle
T2 state
T1 state
T3 state
Ø
Address bus
AS
Address
RD: High
WR
Data bus
Write data
Figure 3-17 (b). External Device Access Timing (write)
57
Section 4. Exception Handling
As indicated in table 4-1, the H8/330 recognizes only two kinds of exceptions: interrupts (28
sources) and the reset. There are no error or trap exceptions.
When an exception occurs the CPU enters the exception-handling state and performs a hardware
exception-handling sequence. There are two exception-handling sequences: one for the reset and
one for interrupts. In both sequences the CPU:
• Sets the interrupt mask (I) bit in the CCR to “1,” and
• Loads the program counter (PC) from the vector table.
After the program counter is loaded, the CPU returns to the program execution state and program
execution starts from the new PC address.
The vector table occupies addresses H’0000 to H’003D in memory. It consists of word entries
giving the addresses of software interrupt-handling routines and the reset routine. The entries are
indexed by a vector number associated with the particular exception.
For an interrupt, before the PC and CCR are altered as described above, the old PC and CCR
contents are pushed on the stack, so that they can be restored when an RTE (Return from
Exception ) instruction is executed.
If a reset and interrupt occur simultaneously, the reset has priority. There is also a priority order
among different types of interrupts. Table 4-1 compares the reset and interrupt exceptions.
Table 4-1. Reset and Interrupt Exceptions
Item
Reset
Interrupt
Priority
Highest
Lower
Cause
Low RES input
Any clock period
Internal or external interrupt signal
At end of current instruction, unless current
instruction is ANDC, ORC, XORC, or LDC, or at
end of hardware interrupt-handling sequence.
At end of current instruction.
3 to 30
When detected
When handled
Vector numbers
Vector table
Immediately
0
H’0000 – H’0001
H’0006 – H’003D
59
4.1 Reset
A reset has the highest exception-handling priority. When the RES pin goes Low, all current
processing by the CPU and on-chip supporting modules halts. When RES returns from Low to
High, the following hardware reset sequence is executed.
(1) The value at the mode pins (MD1 and MD0) is latched in bits MDS1 and MDS0 of the mode
register (MDCR).
(2) In the condition code register (CCR), the I bit is set to “1” to mask interrupts.
(3) The registers of the I/O ports and on-chip supporting modules are initialized.
(4) The CPU loads the program counter with the first word in the vector table (stored at
addresses H’0000 and H’0001) and starts program execution.
A reset does not initialize the general registers or on-chip RAM.
All interrupts, including NMI, are disabled immediately after a reset. The first program instruction,
located at the address specified at the top of the vector table, is therefore always executed. This
instruction should be a MOV.W instruction initializing the stack pointer (R7). After execution of
this instruction, the NMI interrupt is enabled. Other interrupts remain disabled until their enable
bits are set to “1” and the interrupt mask is cleared.
To ensure correct resetting, at power-on the RES pin should be held Low for at least 20ms. In a
reset during operation, the RES pin should be held Low for at least 10 system clock periods. The
RES pin should also be held Low when power is switched off.
Figure 4-1 indicates the timing of the reset sequence when the vector table and reset routine are
located in on-chip ROM. Figure 4-2 indicates the timing when they are in off-chip memory.
60
Vector
fetch
Internal
processing prefetch
Instruction
RES
Ø
Internal address
bus
(1)
(2)
Internal Read
signal
Internal Write
signal
Internal data bus
(16 bits)
(2)
(3)
(1) Reset vector address (H'0000)
(2) Starting address of reset routine (contents of H'0000–H'0001)
(3) First instruction of reset routine
Figure 4-1. Reset Sequence (Mode 2 or 3, Reset Routine in On-Chip ROM)
61
Internal
process-
ing
Instruction prefetch
Vector fetch
RES
Ø
A15 to A0
RD
(5)
(1)
(3)
(7)
WR
D7 to D0
(8 bits)
(8)
(2)
(4)
(6)
(1),(3) Reset vector address: (1)=H'0000, (3)=H'0001
(2),(4) Starting address of reset routine (contents of reset vector): (2)=upper byte, (4)=lower byte
(5),(7) Starting address of reset routine: (5)=(2)(4), (7)=(2)(4)+1
(6),(8) First instruction of reset routine: (6)=first byte, (8)=second byte
Figure 4-2. Reset Sequence (Mode 1)
4.2 Interrupts
There are nine input pins for external interrupts (NMI, IRQ0 to IRQ7). There are also 19 internal
interrupts originating in the 16-bit free-running timer (FRT), 8-bit timers (TMR0 and TMR1), serial
communication interface (SCI), and A/D converter. The features of these interrupts are:
• All internal and external interrupts except NMI can be masked by the I bit in the CCR.
• IRQ0 to IRQ7 can be edge-sensed or level-sensed. (The falling edge or Low level is active.)
The type of sensing can be selected for each interrupt individually. NMI is edge-sensed, and
either the rising or falling edge can be selected.
• Interrupts are individually vectored. The software interrupt-handling routine does not have to
determine what type of interrupt has occurred.
Table 4-2 lists all the interrupts in their order of priority and gives their vector numbers and the
addresses of their entries in the vector table.
63
Table 4-2. Interrupts
Priority Source
Vector
No.
3
Address
of vector
H’0006
H’0008
H’000A
H’000C
H’000E
H’0010
H’0012
H’0014
H’0016
H’0018
H’001A
H’001C
H’001E
H’0020
H’0022
H’0024
H’0026
H’0028
H’002A
H’002C
H’002E
H’0030
H’0032
H’0034
H’0036
H’0038
H’003A
H’003C
Interrupt
High
External
NMI
interrupts
IRQ0
4
IRQ1
5
IRQ2
6
IRQ3
7
IRQ4
8
IRQ5
9
IRQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
IRQ7
Free-running
timer
ICIA (Input capture A)
ICIB (Input capture B)
ICIC (Input capture C)
ICID (Input capture D)
OCIA (Output compare A)
OCIB (Output compare B)
FOVI (Overflow)
CMI0A (Compare-match A)
CMI0B (Compare-match B)
OVI0 (Overflow)
CMI1A (Compare-match A)
CMI1B (Compare-match B)
OVI1 (Overflow)
MREI (Master read end)
MWEI (Master write end)
ERI (Receive error)
8-Bit timer 0
8-Bit timer 1
Dual-port
RAM
Serial
communication RXI (Receive end)
interface TXI (Transmit end)
A/D converter ADI (Conversion end)
Low
Notes:
1. H’0000 and H'0001 contain the reset vector.
2. H’0002 to H’0005 are reserved by the H8/330 and are not available to the user.
64
Figure 4-3 shows a block diagram of the interrupt controller. Figure 4-4 is a flowchart showing the
operation of the interrupt controller and the sequence by which an interrupt is accepted. This
sequence is outlined below.
(1) The interrupt controller receives an interrupt request signal. Interrupt request signals can be
generated by:
—
—
—
A High-to-Low (or Low-to-High) transition of the NMI signal
A Low input (or High-to-Low transition) of one of the IRQ0 to IRQ7 signals
An on-chip supporting module
All interrupts except NMI have enable bits. The interrupt can be requested only when its
enable bit is set to "1."
(2) When notified of an interrupt, the interrupt controller scans the interrupt signals in priority
order and selects the one with the highest priority. (See table 4-2 for the priority order.) Other
requested interrupts remain pending.
(3) The interrupt controller accepts the interrupt if it is an NMI, or if it is another interrupt and the
I bit in the CCR is cleared to “0.” If the interrupt is not an NMI and the I bit is set to “1,” the
interrupt is held pending.
(4) When an interrupt is accepted, after completion of the current instruction, the CPU pushes first
the PC then the CCR onto the stack. The stacked PC indicates the address of the first
instruction that will be executed after the return. The stack pointer (R7) must indicate an even
address. See section 4.2.5, “Note on Stack Handling” for details.
(5) The CPU sets the I bit in the CCR to “1,” masking all further interrupts except NMI during the
interrupt-handling routine.
(6) The CPU generates the vector address of the interrupt and loads the word at this address into
the program counter.
(7) Execution of the software interrupt-handling routine starts from the address now in the pro-
gram counter.
(8) On the return from the interrupt-handling routine (RTE instruction), the CCR and PC are
popped from the stack and execution of the interrupted program resumes.
The timing of this sequence is shown in Figure 4-5 for the case in which the program and vector
table are in on-chip ROM and the stack is in on-chip RAM.
65
Interrupt controller
NMI
NMI request
External (IRQ0 to
IRQ7) or internal
interrupt
Interrupt request
External (IRQ0 to
IRQ7) or internal
interrupt enable
signal
I
CCRinCPU
Figure 4-3. Block Diagram of Interrupt Controller
66
Program execution
Interrupt
request
present?
N
Y
N
NMI?
Y
N
IRQ0?
Y
N
IRQ1?
Y
ADI?
Y
N
I=0 in
CCR?
Pending
Y
Save PC
Save CCR
PC: Program Counter
CCR: Condition Code Register
I: Interrupt mask bit
←
I
1, masking all
interrupts except NMI
To software
interrupt-handling routine
Figure 4-4. Hardware Interrupt-Handling Sequence
67
Interrupt
accepted
Instruction fetch
(first instruction of
Internal interrupt-handling
process- routine)
ing
Interrupt priority
decision. Wait for Instruction Internal
end of instruction. fetch
Vector
table
fetch
process-
ing
Stack
Interrupt request
signal
Ø
Internal address
bus
(5)
(1)
(3)
(6)
(8)
(9)
Internal Read
signal
Internal Write
signal
Internal 16-bit
data bus
(2)
(4)
(1)
(7)
(9)
(10)
(1)
Instruction prefetch address (Pushed on stack. Instruction is executed on return from
interrupt-handling routine.)
(2) (4) Instruction code (Not executed)
(3)
Instruction prefetch address (Not executed)
(5)
SP–2
(6)
SP–4
CCR
(7)
(8) Addressofvectortable entry
(9) Vector table entry (address of first instruction interrupt-handling routine)
(10) First instruction of interrupt-handling routine
Figure 4-5. Timing of Interrupt Sequence
68
4.2.1 Interrupt-Related Registers
The interrupt controller refers to three registers in addition to the CCR. The names and attributes of
these registers are listed in Table 4-3.
Table 4-3. Registers Read by Interrupt Controller
Name
Abbreviation
SYSCR
ISCR
Read/write
R/W
Address
H’FFC4
H’FFC6
H’FFC7
System control register
IRQ sense control register
IRQ enable register
R/W
IER
R/W
(1) System Control Register (SYSCR)—H’FFC4
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
—
1
2
1
0
NMIEG DPME RAME
Initial value
Read/Write
0
0
1
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
The first four bits of the system control register concern the software standby mode, and the last
two bits enable the on-chip RAM and dual-port RAM. Bit 2 is the only bit read by the interrupt
controller.
Bit 2—Nonmaskable Interrupt Edge (NMIEG): This bit determines whether a nonmaskable
interrupt is generated on the falling or rising edge of the NMI input signal.
Bit 2
NMIEG Description
0
1
An interrupt is generated on the falling edge of NMI.
An interrupt is generated on the rising edge of NMI.
(Initial state)
(2) IRQ Sense Control Register (ISCR)—H’FFC6
Bit
7
6
5
4
3
2
1
0
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
69
Bits 0 to 7 – IRQ0 to IRQ7 Sense Control (IRQ0SC to IRQ7SC): These bits determine whether
the IRQ0 to IRQ7 inputs are edge-sensed or level-sensed.
Bit i
IRQiSC Description
0
1
IRQi is level-sensed.
(Initial state)
IRQi is sensed on the falling edge.
Edge-sensed interrupt signals are latched (if enabled) until the interrupt is serviced. They are
latched even if the interrupt mask bit (I) is set in the CCR, and remain latched even if the enable bit
(IRQ0E to IRQ7E) is later cleared to 0.
(3) IRQ Enable Register (IER)—H’FFC7
Bit
7
6
5
4
3
2
1
0
IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 0 to 7 – IRQ0 to IRQ7 Enable (IRQ0E to IRQ7E): These bits enable or disable the IRQi
signals individually.
After a reset, all IRQi interrupts are disabled (as well as masked).
Bit i
IRQiE
Description
0
1
IRQi is disabled.
IRQi is enabled.
(Initial state)
4.2.2 External Interrupts
The external interrupts are NMI and IRQ0 to IRQ7.
(1) NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input
signal regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected
by the NMIEG bit in the system control register.
An NMI has highest priority and is always accepted as soon as the current instruction ends, unless
the current instruction is an ANDC, ORC, XORC, or LDC instruction. When an NMI interrupt is
70
accepted the interrupt mask (I bit) is set, so the NMI handling routine cannot be interrupted except
by another NMI.
The NMI vector number is 3. Its entry is located at address H’0006 in the vector table.
(2) IRQ0 to IRQ7: These interrupt signals are level-sensed or sensed on the falling edge of the
input, as selected by the bits in the ISCR. These interrupts can be masked collectively by the I bit
in the CCR, and can be enabled and disabled individually by setting and clearing the bits in the
IER. When one of these interrupts is accepted, the I bit is set to "1" to mask further interrupts
(except NMI).
The interrupt controller reads level-sensed signals directly from the input pin, so the signal must be
held Low until the interrupt is accepted.
Edge-sensed signals are latched in a flip-flop in the interrupt controller. The signal is latched only
if the interrupt is enabled in the IRQ enable register. However, the signal is latched even if the
interrupt is masked (I bit set to “1” in the CCR).
These interrupts are second in priority to NMI. Among them, IRQ0 has the highest priority and
IRQ7 the lowest priority.
Interrupts IRQ0 to IRQ7 occur regardless of whether the IRQ0 to IRQ7 lines are used for input or
output. When IRQ0 to IRQ7 are requested by external signals, clear the corresponding bits in the
port data direction register (DDR) to 0, and do not use the same pins for timer or serial
communication interface input or output.
4.2.3 Internal Interrupts
Nineteen internal interrupts can be requested by the on-chip supporting modules. All of them are
masked when the I bit in the CCR is set. In addition, they can all be enabled or disabled by bits in
the control registers of the on-chip supporting modules. When one of these interrupts is accepted,
the I bit is set to "1" to mask further interrupts (except NMI).
Power can be conserved by waiting for an internal interrupt in the sleep mode, in which the CPU
halts but the on-chip supporting modules continue to run. When the interrupt arrives, the CPU
returns to the program-execution state, services the interrupt, then resumes execution of the main
program. See section 14, “Power-Down State” for further information on the sleep mode.
The internal interrupt signals received by the interrupt controller are generated from flag bits in the
71
registers of the on-chip supporting modules. The interrupt controller does not reset these flag bits
when accepting the interrupt. The flag bit must be reset by the software interrupt-handling routine.
To reset an interrupt flag, software must read the relevant bit or register, then clear the flag bit to
“0.” The flag bit cannot be cleared unless it is first read. The following is a coding example that
clears the A/D interrupt flag (ADF bit) in the A/D control/status register.
BCLR #7, @H’FFE8
Note: When disabling internal interrupts, note the following points.
1. Set the interrupt mask (I) to "1" before disabling an internal interrupt (an interrupt from an on-
chip supporting module) or clearing an interrupt flag.
2. If an instruction that disables an internal interrupt is executed while the interrupt mask (I) is
cleared to "0", and the interrupt is requested during execution of the instruction, the CPU
resolves this conflict as follows:
➀ If one or more other interrupts are also requested, the other interrupt with the highest priority
is serviced.
➁ If no other interrupt is requested, the CPU branches to the reset address.
Example: The following coding disables the output compare A interrupt from the free-running
timer module in the H8/330 by clearing the OCIAE bit. The I bit is first set to "1."
ORC
#80, CCR
#3, @TIER
#7F, CCR
; Set I bit
BCLR
ANDC
; Disable output compare A interrupt
; Clear I bit
Note: Interrupt requests are not detected immediately after the ANDC, ORC, XORC, and LDC
instructions.
For the priority order of these interrupts, see table 4-2.
4.2.4 Interrupt Response Time
Table 4-4 indicates the time that elapses from an interrupt request signal until the first instruction of
the software interrupt-handling routine is executed. Since the H8/330 accesses its on-chip memory
16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines
in on-chip ROM and the stack in on-chip RAM.
72
Table 4-4. Number of States before Interrupt Service
Number of states
On-chip memory External memory
No. Reason for wait
1
2
Interrupt priority decision
Wait for completion of
current instruction (note 1)
Save PC and CCR
Fetch vector
2 (note 3)
1 to 13
2 (note 3)
5 to 17 (note 2)
3
4
5
6
4
12 (note 2)
6 (note 2)
12 (note 2)
4
2
Fetch instruction
Internal processing
Total
4
4
17 to 29
41 to 53 (note 2)
Notes:
1. These values do not apply if the current instruction is an EEPMOV, MOVFPE, or
MOVTPE instruction.
2. If wait states are inserted in external memory access, these values may be longer.
3. 1 for internal interrupts.
4.2.5 Note on Stack Handling
When the H8/330 performs word access, the least significant bit of the address is always assumed
to be “0.” If an odd address is specified, no address error occurs, but the intended address is not
accessed.
The stack is always accessed by word access. Care should be taken to keep an even value in the
stack pointer (general register R7). The PUSH and POP (or MOV.W Rn, @–SP and MOV.W
@SP+, Rn) instructions should be used for pushing and popping registers on the stack. The
MOV.B Rn, @–SP and MOV.B @SP+, Rn instructions should never be used; they can easily cause
programs to crash.
Figure 4-6 shows how the PC and CCR are pushed on the stack during the hardware interrupt-
handling sequence. The CCR is saved as a word consisting of two identical bytes, both containing
the CCR value. On return from the interrupt-handling routine, the CCR is popped from the upper
of these two bytes. The lower byte is ignored.
73
Figure 4-7 shows an example of damage caused when the stack pointer contains an odd address.
SP-4
SP-3
SP-2
SP(R7)
SP+1
SP+2
CCR
CCR *
PC (upper byte)
SP-1
SP+3
SP+4
PC (lower byte)
SP(R7)
Even address
Stack area
Before interrupt
is accepted
After interrupt
is accepted
Pushed onto stack
PC : Program counter
CCR : Condition code register
SP : Stack pointer
: Ignored on return.
*
Notes: 1. The PC contains the address of the first instruction
executed after return.
2. Registers must be saved and restored by word
access at an even address.
Figure 4-6. Usage of Stack in Interrupt Handling
74
SP
H'FFCC
H'FFCD
PC
PC
R1
PC
L
L
H
L
SP
H'FFCF
SP
BSR instruction
MOV.B R1L, @–R7
PC is improperly stored
beyond top of stack
PC is lost
H
H'FFCF set in SP
PC : Upper byte of program counter
H
PC : Lower byte of program counter
L
R1 : General register
L
SP : Stack pointer
Figure 4-7. Example of Damage Caused by Setting an Odd Address in R7
4.2.6 Deferring of Interrupts
As noted previously, no interrupt is accepted immediately after a reset. System control instructions
that rewrite the CCR have a similar effect. Interrupts requests received during one of these
instructions are deferred until at least one more instruction has been executed.
The instructions that defer interrupts in this way are XORC, ORC, ANDC, and LDC. At the
completion of these instructions the interrupt controller does not check the interrupt signals. The
CPU therefore always proceeds to the next instruction. (And if the next instruction is one of these
four, the CPU also proceeds to the next instruction after that.) The interrupt-handling sequence
starts after the next instruction that is not one of these four has been executed. Figure 4-8 shows an
example.
75
NMI and other edge-sensed interrupt request signals that arrive during the execution of an ANDC,
ORC, XORC, or LDC instruction are not lost. The request is latched in the interrupt controller and
detected after another instruction has been executed.
Program flow
LDC.B #H’00
← Interrupt request: ignored by interrupt controller
MOV.W #H’FF80,SP
← CPU executes next instruction: interrupt controller now
detects interrupt request
PUSH R1
← To interrupt-handling sequence
Figure 4-8. Example of Deferred Interrupt
76
Section 5. I/O Ports
5.1 Overview
The H8/330 has nine parallel I/O ports, including:
• Six 8-bit input/output ports—ports 1, 2, 3, 4, 6, and 9
• One 8-bit input port—port 7
• One 7-bit input/output port—port 8
• One 3-bit input/output port—port 5
All ports except port 7 have programmable MOS input pull-ups. Ports 1 and 2 can drive LEDs.
Input and output are memory-mapped. The CPU views each port as a data register (DR) located in
the register field at the high end of the address space. Each port (except port 7) also has a data
direction register (DDR) which determines which pins are used for input and which for output.
Output: To send data to an output port, the CPU selects output in the data direction register and
writes the desired data in the data register, causing the data to be held in a latch. The latch output
drives the pin through a buffer amplifier. If the CPU reads the data register of an output port, it
obtains the data held in the latch rather than the actual level of the pin.
Input: To read data from an I/O port, the CPU selects input in the data direction register and reads
the data register. This causes the input logic level at the pin to be placed directly on the internal
data bus. There is no intervening input latch.
MOS Pull-Up: The MOS pull-ups for input pins are controlled as follows. To turn on the pull-up
transistor for a pin, software must first clear its data direction bit to “0” to make the pin an input
pin, then write a “1” in the data bit for that pin. The pull-up can be turned off by writing a “0” in
the data bit, or a “1” in the data direction bit. The pull-ups are also turned off by a reset and by
entry to the hardware standby mode.
The data direction registers are write-only registers; their contents are invisible to the CPU. If the
CPU reads a data direction register all bits are read as “1,” regardless of their true values. Care is
required if bit manipulation instructions are used to set and clear the data direction bits. See the
note on bit manipulation instructions in Section 3.5.5, "Bit Manipulations."
Auxiliary Functions: In addition to their general-purpose input/output functions, all of the I/O
ports have auxiliary functions. Most of the auxiliary functions are software-selectable and must be
enabled by setting bits in control registers. When selected, an auxiliary function usually replaces
77
the general-purpose input/output function, but in some cases both functions can operate
simultaneously. Table 5-1 summarizes the auxiliary functions of the ports.
Table 5-1. Auxiliary Functions of Input/Output Ports
I/O port Expanded modes
Single-chip mode
1
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Address bus (Low)*
—
1
Address bus (High)*
—
2
Data bus*
Dual-port RAM data bus
8-Bit and PWM timer input and output
Serial communication (asynchronous mode)
Free-running timer input/output, IRQ6 and IRQ7
Analog input
Serial communication (synchronous
mode)
Serial communication (synchronous
mode)
E clock and IOS output
Dual-port RAM address select input
IRQ3 to IRQ5
IRQ3 to IRQ5
2
Port 9
Bus control and Ø output*
Dual-port RAM interface control,
Ø output
IRQ0 to IRQ2 and ADTRG
IRQ0 to IRQ2 and ADTRG
Notes:
*1 Selected automatically in mode 1; software-selectable in mode 2
*2 Selected automatically in modes 1 and 2
5.2 Port 1
Port 1 is an 8-bit input/output port that also provides the low bits of the address bus. The function
of port 1 depends on the MCU mode as indicated in table 5-2.
Table 5-2. Functions of Port 1
Mode 1
Mode 2
Mode 3
Address bus (Low)
(A7 to A0)
Input port or
Address bus (Low)
(A7 to A0)*
Input/output port
* Depending on the bit settings in the data direction register: 0—input pin; 1—address pin
Pins of port 1 can drive a single TTL load and a 90pF capacitive load when they are used as
output pins. They can also drive light-emitting diodes and a Darlington pair. When they are
used as input pins, they have programmable MOS pull-ups.
78
Table 5-3 details the port 1 registers.
Table 5-3. Port 1 Registers
Name
Abbreviation Read/Write Initial value
Address
Port 1 data direction register P1DDR
W
H’FF (mode 1)
H’00 (modes 2 and 3)
H’00 H’FFB2
H’FFB0
Port 1 data register
P1DR
R/W
Port 1 Data Direction Register (P1DDR)—H’FFB0
Bit
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P1DDR is an 8-bit register that selects the direction of each pin in port 1. A pin functions as an
output pin if the corresponding bit in P1DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Port 1 Data Register (P1DR)—H’FFB2
Bit
7
P17
0
6
P16
0
5
P15
0
4
P14
0
3
P13
0
2
P12
0
1
P11
0
0
P10
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1DR is an 8-bit register containing the data for pins P17 to P10. When the CPU reads P1DR, for
output pins it reads the value in the P1DR latch, but for input pins, it obtains the logic level directly
from the pin, bypassing the P1DR latch.
MOS Pull-Ups: Are available for input pins in modes 2 and 3. Software can turn on the MOS
pull-up by writing a “1” in P1DR, and turn it off by writing a “0.” The pull-ups are automatically
turned off for output pins in modes 2 and 3, and for all pins in mode 1.
79
Mode 1: In mode 1 (expanded mode without on-chip ROM), port 1 is automatically used for
address output. The port 1 data direction register is unwritable. All bits in P1DDR are
automatically set to "1" and cannot be cleared to "0."
Mode 2: In mode 2 (expanded mode with on-chip ROM), the usage of port 1 can be selected on a
pin-by-pin basis. A pin is used for general-purpose input if its data direction bit is cleared to "0,"
or for address output if its data direction bit is set to “1.”
Mode 3: In the single-chip mode port 1 is a general-purpose input/output port.
Reset: A reset clears P1DDR and P1DR to all “0,” placing all pins in the input state with the MOS
pull-ups off. In mode 1, when the chip comes out of reset, P1DDR is set to all "1."
Hardware Standby Mode: All pins are placed in the high-impedance state with the MOS pull-ups
off.
Software Standby Mode: In the software standby mode, both P1DDR and P1DR remain in their
previous state. Address output pins are Low. General-purpose output pins continue to output the
data in P1DR.
Figure 5-1 shows a schematic diagram of port 1.
80
Mode 1 Reset
S*
Hardware standby
R
D
Q
•
•
P1n DDR
C
*
WP1D
Mode 3
Reset
R
D
Q
•
P1
n
•
P1n DR
C
Mode 1 or 2
WP1
•
•
RP1
•
WP1D: Write Port 1 DDR
WP1: Write Port 1
RP1:
Read Port 1
n =0 to7
* Set-priority
Figure 5-1. Port 1 Schematic Diagram
5.3 Port 2
Port 2 is an 8-bit input/output port that also provides the high bits of the address bus. The function
of port 2 depends on the MCU mode as indicated in Table 5-4.
Table 5-4. Functions of Port 2
Mode 1
Mode 2
Mode 3
Address bus (High)
(A15 to A8)
Input port or
Address bus (High)
(A15 to A8)*
Input/output port
* Depending on the bit settings in the data direction register: 0—input pin; 1—address pin
81
Pins of port 2 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive light-emitting diodes and a Darlington pair. When they are used as input
pins, they have programmable MOS pull-ups.
Table 5-5 details the port 2 registers.
Table 5-5. Port 2 Registers
Name
Abbreviation Read/Write
Initial value
H’FF (mode 1)
H'00 (modes 2 and 3)
H’00
Address
Port 2 data direction
register
P2DDR
W
H’FFB1
Port 2 data register
P2DR
R/W
H’FFB3
Port 2 Data Direction Register (P2DDR)—H’FFB1
Bit
7
6
5
4
3
2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P2DDR is an 8-bit register that selects the direction of each pin in port 2. A pin functions as an
output pin if the corresponding bit in P2DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Port 2 Data Register (P2DR)—H’FFB3
Bit
7
P27
0
6
P26
0
5
P25
0
4
P24
0
3
P23
0
2
P22
0
1
P21
0
0
P20
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P2DR is an 8-bit register containing the data for pins P27 to P20. When the CPU reads P2DR, for
output pins it reads the value in the P2DR latch, but for input pins, it obtains the logic level directly
from the pin, bypassing the P2DR latch.
82
MOS Pull-Ups: Are available for input pins in modes 2 and 3. Software can turn on the MOS
pull-up by writing a “1” in P2DR, and turn it off by writing a “0.” The pull-ups are automatically
turned off for output pins in modes 2 and 3, and for all pins in mode 1.
Mode 1: In mode 1 (expanded mode without on-chip ROM), port 2 is automatically used for
address output. The port 2 data direction register is unwritable. All bits in P2DDR are
automatically set to "1" and cannot be cleared to "0."
Mode 2: In mode 2 (expanded mode with on-chip ROM), the usage of port 2 can be selected on a
pin-by-pin basis. A pin is used for general-purpose input if its data direction bit is cleared to "0,"
or for address output if its data direction bit is set to “1.”
Mode 3: In the single-chip mode port 2 is a general-purpose input/output port.
Reset: A reset clears P2DDR and P2DR to all “0,” placing all pins in the input state with the MOS
pull-ups off. In mode 1, when the chip comes out of reset, P2DDR is set to all "1."
Hardware Standby Mode: All pins are placed in the high-impedance state with the MOS pull-ups
off.
Software Standby Mode: In the software standby mode, both P2DDR and P2DR remain in their
previous state. Address output pins are Low. General-purpose output pins continue to output the
data in P2DR.
Figure 5-2 shows a schematic diagram of port 2.
83
Mode 1 Reset
S*
Hardware standby
R
Q
D
P2n DDR
C
*
WP2D
Mode 3
Reset
R
Q
D
P2
n
P2n DR
C
Mode 1 or 2
WP2
RP2
WP2D: Write Port 2 DDR
WP2: Write Port 2
RP2:
Read Port 2
n = 0 to7
* Set-priority
Figure 5-2. Port 2 Schematic Diagram
5.4 Port 3
Port 3 is an 8-bit input/output port that also provides the external data bus and dual-port RAM
(master-slave) data bus. The function of port 3 depends on the MCU mode as indicated in table
5-6.
Table 5-6. Functions of Port 3
Mode 3
DPME = "0" DPME = "1"
Input/output port Dual-port RAM data bus
Mode 1
Mode 2
Data bus
Data bus
Pins of port 3 can drive a single TTL load and a 90pF capacitive load when they are used as output
84
pins. They can also drive a Darlington pair. When they are used as input pins, they have
programmable MOS pull-ups.
Table 5-7 details the port 3 registers.
Table 5-7. Port 3 Registers
Name
Port 3 data direction register P3DDR
Port 3 data register P3DR
Abbreviation
Read/Write Initial value
Address
H’FFB4
H’FFB6
W
H’00
H’00
R/W
Port 3 Data Direction Register (P3DDR)—H’FFB4
Bit
7
6
5
4
3
2
1
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P3DDR is an 8-bit register that selects the direction of each pin in port 3. A pin functions as an
output pin if the corresponding bit in P3DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Port 3 Data Register (P3DR)—H’FFB6
Bit
7
P37
0
6
P36
0
5
P35
0
4
P34
0
3
P33
0
2
P32
0
1
P31
0
0
P30
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3DR is an 8-bit register containing the data for pins P37 to P30. When the CPU reads P3DR, for
output pins it reads the value in the P3DR latch, but for input pins, it obtains the logic level directly
from the pin, bypassing the P3DR latch.
MOS Pull-Ups: Are available for input pins in mode 3 when the dual-port RAM is disabled.
Software can turn on the MOS pull-up on by writing a “1” in P3DR, and turn it off by writing a
“0.”
85
The MOS pull-ups cannot be used in slave mode (when the dual-port RAM is enabled). P3DR
should be cleared to H'00 (its initial value) in slave mode.
Modes 1 and 2: In the expanded modes, port 3 is automatically used as the data bus. The values
in P3DDR and P3DR are ignored.
Mode 3: In the single-chip mode, when the dual-port RAM enable (DPME) bit in the system
control register is cleared to “0,” port 3 can be used as a general-purpose input/output port.
When DPME is set to “1,” entering the slave mode, port 3 is used as the dual-port RAM data bus
(DDB7 to DDB0). P3DR should also be cleared to H'00 in slave mode.
See section 12, “Dual-Port RAM” for further information.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P3DDR and P3DR to all “0,” and clears the DPME bit to "0." In modes 1 and 2, all pins are placed
in the data input (high-impedance) state. In mode 3 (single-chip mode), all pins are in the input
state with the MOS pull-ups off.
Software Standby Mode: In the software standby mode, P3DDR, P3DR, and the DPME bit
remain in their previous state. In modes 1 and 2 and slave mode, all pins are placed in the data
input (high-impedance) state. In mode 3 with the dual-port RAM disabled, all pins remain in their
previous input or output state.
Figure 5-3 shows a schematic diagram of port 3.
86
DPME Mode 3
Mode 3
Reset
CS
OE
R
D
Q
P3nDDR
External
address
write
C
WP3D
Reset
R
P3
n
D
Q
P3nDR
C
WP3
Mode 1 or 2
CS
WE
RP3
External address read
WP3D: Write Port 3 DDR
WP3:
Write Port 3
RP3: Read Port 3
n = 0 to 3
Figure 5-3. Port 3 Schematic Diagram
87
5.5 Port 4
Port 4 is an 8-bit input/output port that also provides the input and output pins for the 8-bit timers
and the output pins for the PWM timers. The pin functions depend on control bits in the control
registers of the timers. Pins not used by the timers are available for general-purpose input/output.
Table 5-8 lists the pin functions, which are the same in both the expanded and single-chip modes.
Table 5-8. Port 4 Pin Functions (Modes 1 to 3)
Usage
I/O port
Timer
Pin functions
P40
P41
P42
P43
P44
P45
P46
P47
TMCI0 TMO0 TMRI0 TMCI1 TMO1 TMRI1 PW0
PW1
See section 7, “8-Bit Timer Module” and section 8, “PWM Timer Module” for details of the timer
control bits.
Pins of port 4 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive a Darlington pair. When used as input pins, they have programmable
MOS pull-ups.
Table 5-9 details the port 4 registers.
Table 5-9. Port 4 Registers
Name
Port 4 data direction register P4DDR
Port 4 data register P4DR
Abbreviation Read/Write Initial value
Address
H’FFB5
H’FFB7
W
H’00
H’00
R/W
Port 4 Data Direction Register (P4DDR)—H’FFB5
Bit
7
6
5
4
3
2
1
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P4DDR is an 8-bit register that selects the direction of each pin in port 4. A pin functions as an
output pin if the corresponding bit in P4DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
88
Port 4 Data Register (P4DR)—H’FFB7
Bit
7
P47
0
6
P46
0
5
P45
0
4
P44
0
3
P43
0
2
P42
0
1
P41
0
0
P40
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P4DR is an 8-bit register containing the data for pins P47 to P40. When the CPU reads P4DR, for
output pins (P4DDR = "1") it reads the value in the P4DR latch, but for input pins (P4DDR = "0"),
it obtains the logic level directly from the pin, bypassing the P4DR latch. This also applies to pins
used for timer input or output.
MOS Pull-Ups: Are available for input pins, including timer input pins, in all modes. Software
can turn the MOS pull-up on by writing a “1” in P4DR, and turn it off by writing a “0.”
Pins P40, P42, P43, and P45: As indicated in Table 5-8, these pins can be used for general-purpose
input or output, or input of 8-bit timer clock and reset signals. When a pin is used for timer signal
input, its P4DDR bit should normally be cleared to "0;" otherwise the timer will receive the value
in P4DR. If input pull-up is not desired, the P4DR bit should also be cleared to "0."
Pins P41, P44, P46, and P47: As indicated in Table 5-8, these pins can be used for general-purpose
input or output, or for 8-bit timer output (P41 and P44) or PWM timer output (P46 and P47). Pins
used for timer output are unaffected by the values in P4DDR and P4DR, and their MOS pull-ups
are automatically turned off.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P4DDR and P4DR to all “0” and makes all pins into input port pins with the MOS pull-ups off.
Software Standby Mode: In the software standby mode, the control registers of the 8-bit and
PWM timers are initialized but P4DDR and P4DR remain in their previous states. All pins become
input or output port pins depending on the setting of P4DDR. Output pins output the values in
P4DR. The MOS pull-ups of input pins are on or off depending on the values in P4DR.
Figures 5-4 and 5-5 show schematic diagrams of port 4.
89
Reset
R
Q
D
P4n DDR
C
WP4D
Reset
R
Q
D
P4
n
P4n DR
C
WP4
RP4
8-bit timer module
Counter clock
input
Counter reset
input
WP4D: Write Port 4 DDR
WP4: Write Port 4
RP4:
Read Port 4
n = 0, 2, 3, 5
Figure 5-4. Port 4 Schematic Diagram (Pins P40, P42, P43, and P45)
90
Reset
R
Q
D
P4n DDR
C
WP4D
Reset
R
D
Q
P4
n
P4n DR
8-Bit timer module,
PWM timer module
C
WP4
Output enable
8-Bit timer output
or PWM timer output
RP4
WP4D: Write Port 4 DDR
WP4: Write Port 4
RP4:
Read Port 4
n = 1, 4, 6, 7
Figure 5-5. Port 4 Schematic Diagram (Pins P41, P44, P46, and P47)
5.6 Port 5
Port 5 is a 3-bit input/output port that also provides the input and output pins for asynchronous
serial communication. The pin functions depend on control bits in the serial control register (SCR).
Pins not used for serial communication are available for general-purpose input/output. Table 5-10
lists the pin functions, which are the same in both the expanded and single-chip modes.
Table 5-10. Port 5 Pin Functions (Modes 1 to 3)
Usage
I/O port
Timer
Pin functions
P50
P51
P52
ATxD
ARxD
ASCK
91
See section 9, “Serial Communication Interface” for details of the serial control bits. Pins used by
the serial communication interface are switched between input and output without regard to the
values in the data direction register.
Pins of port 5 can drive a single TTL load and a 30pF capacitive load when they are used as output
pins. They can also drive a Darlington pair. When used as input pins, they have programmable
MOS pull-ups.
Table 5-11 details the port 5 registers.
Table 5-11. Port 5 Registers
Name
Abbreviation
P5DDR
Read/Write
Initial value
H’F8
Address
H’FFB8
H’FFBA
Port 5 data direction register
Port 5 data register
W
P5DR
R/W
H’F8
Port 5 Data Direction Register (P5DDR)—H’FFB8
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
P52DDR P51DDR P50DDR
Initial value
Read/Write
0
0
0
—
—
—
—
—
W
W
W
P5DDR is an 8-bit register that selects the direction of each pin in port 5. A pin functions as an
output pin if the corresponding bit in P5DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Port 5 Data Register (P5DR)—H’FFBA
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
P52
0
1
P51
0
0
P50
0
Initial value
Read/Write
—
—
—
—
—
R/W
R/W
R/W
P5DR is an 8-bit register containing the data for pins P52 to P50. When the CPU reads P5DR, for
output pins (P5DDR = "1") it reads the value in the P5DR latch, but for input pins (P5DDR = "0"),
it obtains the logic level directly from the pin, bypassing the P5DR latch. This also applies to pins
92
used for serial communication.
MOS Pull-Ups: Are available for input pins, including serial communication input pins. Software
can turn the MOS pull-up on by writing a “1” in P5DR, and turn it off by writing a “0.”
Pin P50: This pin can be used for general-purpose input or output, or for output of asynchronous
serial transmit data (ATxD). When used for ATxD output, this pin is unaffected by the values in
P5DDR and P5DR, and its MOS pull-up is automatically turned off.
Pin P51: This pin can be used for general-purpose input or output, or for input of asynchronous
serial receive data (ARxD). When used for ARxD input, this pin is unaffected by P5DDR and
P5DR, except that software can turn on its MOS pull-up by clearing its data direction bit to "0" and
setting its data bit to "1."
Pin P52: This pin can be used for general-purpose input or output, or for asynchronous serial clock
input or output (ASCK). When used for ASCK input or output, this pin is unaffected by P5DDR
and P5DR, except that software can turn on its MOS pull-up by clearing its data direction bit to "0"
and setting its data bit to "1." For ASCK usage, the MOS pull-up should be turned off.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode makes all
pins of port 5 into input port pins with the MOS pull-ups off.
Software Standby Mode: In the software standby mode, the serial control register is initialized
but P5DDR and P5DR remain in their previous states. All pins become input or output port pins
depending on the setting of P5DDR. Output pins output the values in P5DR. The MOS pull-ups of
input pins are on or off depending on the values in P5DR.
Figures 5-6 to 5-8 show schematic diagrams of port 5.
93
Reset
R
D
Q
P50 DDR
C
WP5D
Reset
R
D
Q
P5
0
P50 DR
SCI module
C
WP5
Asynchronous serial
transmit enable
Asynchronous serial
transmit data
RP5
WP5D: Write Port 5 DDR
WP5: Write Port 5
RP5:
Read Port 5
Figure 5-6. Port 5 Schematic Diagram (Pin P50)
94
Reset
R
Q
D
P51 DDR
SCI module
C
WP5D
Asynchronous
serial receive
enable
Reset
R
Q
D
P5
1
P51 DR
C
WP5
RP5
Asynchronous
serial receive
data
WP5D: Write Port 5 DDR
WP5
RP5:
Write Port 5
Read Port 5
Figure 5-7. Port 5 Schematic Diagram (Pin P51)
95
Reset
R
D
Q
P52DDR
SCI module
WP5D
Asynchronous
serial clock
input enable
Reset
R
D
Q
P5
2
P52 DR
C
Asynchronous
serial clock
WP5
output enable
Asynchronous
serial clock
output
RP5
Asynchronous
serial clock
input
WP5D: Write Port 5 DDR
WP5
RP5:
Write Port 5
Read Port 5
Figure 5-8. Port 5 Schematic Diagram (Pin P52)
5.7 Port 6
Port 6 is an 8-bit input/output port that also provides the input and output pins for the free-running
timer and the IRQ6 and IRQ7 input/output pins. The pin functions depend on control bits in the
free-running timer control registers, and on bit 6 or 7 of the interrupt enable register. Pins not used
for timer or interrupt functions are available for general-purpose input/output. Table 5-12 lists the
pin functions, which are the same in both the expanded and single-chip modes.
Table 5-12. Port 6 Pin Functions
Usage Pin functions (Modes 1 to 3)
I/O port
P60
P61
P62
P63
P64
P65
P66
P67
Timer/interrupt FTCI FTOA FTIA
FTIB FTIC
FTID FTOB/IRQ6
IRQ7
96
See section 4 “Exception Handling” and section 6, “Free-Running Timer Module” for details of the
free-running timer and interrupts.
Pins of port 6 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive a Darlington pair. When they are used as input pins, they have
programmable MOS pull-ups.
Table 5-13 details the port 6 registers.
Table 5-13. Port 6 Registers
Name
Port 6 data direction register P6DDR
Port 6 data register P6DR
Abbreviation
Read/Write Initial value
Address
H’FFB9
H’FFBB
W
H’00
H’00
R/W
Port 6 Data Direction Register (P6DDR)—H’FFB9
Bit
7
6
5
4
3
2
1
0
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P6DDR is an 8-bit register that selects the direction of each pin in port 6. A pin functions as an
output pin if the corresponding bit in P6DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Port 6 Data Register (P6DR)—H’FFBB
Bit
7
P67
0
6
P66
0
5
P65
0
4
P64
0
3
P63
0
2
P62
0
1
P61
0
0
P60
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P6DR is an 8-bit register containing the data for pins P67 to P60. When the CPU reads P6DR, for
output pins (P6DDR = "1") it reads the value in the P6DR latch, but for input pins (P6DDR = "0"),
it obtains the logic level directly from the pin, bypassing the P6DR latch. This also applies to pins
used for input and output of timer and interrupt signals.
97
MOS Pull-Ups: Are available for input pins, including pins used for input of timer or interrupt
signals. Software can turn the MOS pull-up on by writing a “1” in P6DR, and turn it off by writing
a “0.”
Pins P60, P62, P63, P64 and P65: As indicated in Table 5-12, these pins can be used for general-
purpose input or output, or for input of free-running timer clock and input capture signals. When a
pin is used for free-running timer input, its P6DDR bit should be cleared to "0;" otherwise the free-
running timer will receive the value in P6DR. If input pull-up is not desired, the P6DR bit should
also be cleared to "0."
Pin P61: This pin can be used for general-purpose input or output, or for the output compare A
signal (FTOA) of the free-running timer. When used for FTOA output, this pin is unaffected by the
values in P6DDR and P6DR, and its MOS pull-up is automatically turned off.
Pin P66: This pin can be used for general-purpose input or output, for the output compare B signal
(FTOB) of the free-running timer, or for IRQ6 input. When used for FTOB output, this pin is
unaffected by the values in P6DDR and P6DR, and its MOS pull-up is automatically turned off.
When this pin is used for IRQ6 input, P66DDR should normally be cleared to "0," so that the value
in P6DR will not generate interrupts.
Pin P67: This pin can be used for general-purpose input or output, or IRQ7 input. When it is used
for IRQ7 input, P67DDR should normally be cleared to "0," so that the value in P6DR will not
generate interrupts.
Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears
P6DDR and P6DR to all “0” and makes all pins into input port pins with the MOS pull-ups off.
Software Standby Mode: In the software standby mode, the free-running timer control registers
are initialized but P6DDR and P6DR remain in their previous states. All pins become input or
output port pins depending on the setting of P6DDR. Output pins output the values in P6DR. The
MOS pull-ups of input pins are on or off depending on the values in P6DR.
Figures 5-9 to 5-11 shows schematic diagrams of port 6.
98
Reset
R
D
Q
P6n DDR
C
WP6D
Reset
R
D
Q
P6
n
P6n DR
C
WP6
RP6
Free-running
timer module
Input capture
input,
WP6D: Write Port 6 DDR
WP6: Write Port 6
counter clock
input
RP6:
Read Port 6
n = 0. 2 – 5
Figure 5-9. Port 6 Schematic Diagram (Pins P60, P62, P63, P64, and P65)
99
Reset
R
Q
D
P61 DDR
C
WP6D
Reset
R
D
Q
P6
1
P61 DR
Free-running
timer module
C
WP6
Output enable
Output-compare
output
RP6
WP6D: Write Port 6 DDR
WP6: Write Port 6
RP6:
Read Port 6
Figure 5-10. Port 6 Schematic Diagram (Pin P61)
100
Reset
R
D
Q
P66 DDR
C
WP6D
Reset
R
D
Q
P6
6
P66 DR
Free-running
timer module
C
WP6
Output enable
Output-compare
output
RP6
IRQ6 input
IRQ enable
register
WP6D: Write Port 6 DDR
WP6: Write Port 6
IRQ6 enable
RP6:
Read Port 6
Figure 5-11. Port 6 Schematic Diagram (Pin P66)
101
Reset
R
Q
D
P67 DDR
C
WP6D
Reset
R
Q
P6
D
7
P67 DR
C
WP6
RP6
IRQ7 input
IRQ enable
register
WP6D: Write Port 6 DDR
WP6: Write Port 6
IRQ7 enable
RP6:
Read Port 6
Figure 5-12. Port 6 Schematic Diagram (Pin P67)
5.8 Port 7
Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter module.
The pin functions are the same in both the expanded and single-chip modes.
Table 5-14 lists the pin functions. Table 5-15 describes the port 7 data register, which simply
consists of connections of the port 7 pins to the internal data bus. Figure 5-13 shows a schematic
diagram of port 7.
102
Table 5-14. Port 7 Pin Functions (Modes 1 to 3)
Usage
Pin functions
I/O port
P70
P71
P72
P73
P74
P75
P76
P77
Analog input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Table 5-15. Port 7 Register
Name
Abbreviation
Read/Write
Initial value
Address
Port 7 data register
P7DR
R
Undetermined
H’FFBE
Port 7 Data Register (P7DR)—H’FFBE
Bit
7
P77
*
6
P76
*
5
P75
*
4
P74
*
3
P73
*
2
P72
*
1
P71
*
0
P70
*
Initial value
Read/Write
R
R
R
R
R
R
R
R
* Depends on the levels of pins P77 to P70.
RP7
A/D converter
module
P7
n
Analog input
RP7: Read port 7
n = 0 to 7
Figure 5-13. Port 7 Schematic Diagram
103
5.9 Port 8
Port 8 is a 7-bit input/output port that also provides pins for E clock output, dual-port RAM register
select input, interrupt input, and clock-synchronized serial communication. Table 5-16 lists the pin
functions.
Table 5-16. Port 8 Pin Functions
Auxiliary functions
I/O port
Expanded modes
E clock output
Single-chip mode
RS0 input
P80 input/output
P81 input/output
P82 input/output
P83 input/output
P84 input/output
P85 input/output
P86 input/output
IOS output
RS1 input
—
RS2 input
—
RS3 input
CTxD output /IRQ3 input
CRxD input /IRQ4 input
CSCK input/output /IRQ5 input
Pins of port 8 can drive a single TTL load and a 30pF capacitive load when they are used as output
pins. They can also drive a Darlington pair. When used as input pins, they have programmable
MOS pull-ups.
Table 5-17 details the port 8 registers.
Table 5-17. Port 8 Registers
Name
Abbreviation Read/Write Initial value
Address
H’81 (modes 1 and 2) H’FFBD
H’80 (mode 3)
Port 8 data direction register P8DDR
W
Port 8 data register
P8DR
R/W
H'80
H’FFBF
104
Port 8 Data Direction Register (P8DDR)—H’FFBD
Bit
7
6
5
4
3
2
1
0
—
P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR
Modes 1 and 2
Initial value
Read/Write
Mode 3
1
0
0
0
0
0
0
1
—
W
W
W
W
W
W
W
Initial value
Read/Write
1
0
0
0
0
0
0
0
—
W
W
W
W
W
W
W
P8DDR is an 8-bit register that selects the direction of each pin in port 8. A pin functions as an
output pin if the corresponding bit in P8DDR is set to “1,” and as in input pin if the bit is cleared to
“0.”
Bit 7 is reserved. It cannot be modified, and is always read as "1."
Port 8 Data Register (P8DR)—H’FFBF
Bit
7
—
1
6
P86
0
5
P85
0
4
P84
0
3
P83
0
2
P82
0
1
P81
0
0
P80
0
Initial value
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P8DR is an 8-bit register containing the data for pins P86 to P80. When the CPU reads P8DR, for
output pins (P8DDR = "1") it reads the value in the P8DR latch, but for input pins (P8DDR = "0"),
it obtains the logic level directly from the pin, bypassing the P8DR latch. This also applies to pins
used for dual-port RAM register select input, interrupt input, serial communication, and E clock or
IOS output.
Bit 7 is reserved. It cannot be modified, and is always read as "1."
MOS Pull-Ups: Are available for input pins in all modes, including pins used for dual-port RAM
register select input, interrupt input, or serial communication input. Software can turn the MOS
pull-up on by writing a “1” in P8DR, and turn it off by writing a “0.”
105
Pin P80: In modes 1 and 2 (expanded modes), pin P80 is used for E clock output if P80DDR is set
to "1," and for general-purpose input if P80DDR is cleared “0.” It cannot be used for general-
purpose output.
In mode 3 (single-chip mode), when the dual-port RAM is disabled (DPME = "0"), pin P80 can be
used for general-purpose input or output. In the slave mode (DPME = "1"), this pin is used for
register select input (RS0). In slave mode this pin is unaffected by the values in P8DDR and
P8DR, except that software can turn on its MOS pull-up by clearing its data direction bit to "0" and
setting its data bit to "1."
Pin P81: In modes 1 and 2 (expanded modes), pin P81 is used for IOS output if P81DDR is set to
"1," and for general-purpose input if P81DDR is cleared “0.” It cannot be used for general-purpose
output.
In mode 3, when the dual-port RAM is disabled (DPME = "0"), pin P81 can be used for general-
purpose input or output. In the slave mode (DPME = "1"), this pin is used for register select input
(RS1). In slave mode this pin is unaffected by the values in P8DDR and P8DR, except that
software can turn on its MOS pull-up by clearing its data direction bit to "0" and setting its data bit
to "1."
Pins P82 and P83: These pins are available for general-purpose input or output in modes 1 and 2,
and in mode 3 if the dual-port RAM is disabled (DPME = "0").
In the slave mode (mode 3 with DPME = "1"), these pins are used for register select input (RS2 and
RS3). They are unaffected by the bits in P8DDR and P8DR, except that software can turn on their
MOS pull-ups by clearing the P8DDR bit to "0" and setting the P8DR bit to "1."
Pin P84: This pin has the same functions in all modes. It can be used for general-purpose input or
output, for output of clock-synchronized serial transmit data (CTxD), or for IRQ3 input. When
used for CTxD output, this pin is unaffected by the values in P8DDR and P8DR, and its MOS pull-
up is automatically turned off. When this pin is used for IRQ3 input, P84DDR should normally be
cleared to "0," so that the value in P8DR will not generate interrupts.
Pin P85: This pin has the same functions in all modes. It can be used for general-purpose input or
output, for input of clock-synchronized serial receive data (CRxD), or for IRQ4 input. When used
for CRxD input, this pin is unaffected by the values in P8DDR and P8DR, except that software can
turn on its MOS pull-up by clearing its data direction bit to "0" and setting its data bit to "1." When
this pin is used for IRQ4 input, P85DDR should normally be cleared to "0," so that the value in
P8DR will not generate interrupts.
106
Pin P86: This pin has the same functions in all modes. It can be used for general-purpose input or
output, for serial clock input or output (CSCK), or for IRQ5 input. When this pin is used for IRQ5
input, P86DDR should normally be cleared to "0," so that the value in P8DR will not generate
interrupts.
When used for CSCK input or output, this pin is unaffected by the values in P8DDR and P8DR,
except that software can turn on its MOS pull-up by clearing its data direction bit to "0" and setting
its data bit to "1." For CSCK usage, the MOS pull-up should be turned off.
Reset: A reset clears bits P86DDR to P81DDR to “0” and clears the DPME bit, serial control bits,
and interrupt enable bits to “0,” making P86 to P81 into input port pins with the MOS pull-ups off.
In the expanded modes (modes 1 and 2), P80DDR is initialized to “1” and the P80 pin is used for E
clock output. In the single-chip mode (mode 3), P80DDR is initialized to “0” and the P80 pin is
used for port input.
Hardware Standby Mode: All pins are placed in the high-impedance state with the MOS pull-ups
off.
Software Standby Mode: In the software standby mode, the serial control register is initialized,
but the DPME bit, the interrupt enable register, P8DDR, and P8DR remain in their previous states.
Pins that were being used for serial communication revert to general-purpose input or output,
depending on the value in P8DDR. Other pins remain in their previous state. Output pins output
the values in P8DR. E clock output is Low.
Figures 5-14 to 5-19 show schematic diagrams of port 8.
107
Mode Mode3
1 or 2 Reset
Mode 3
DPME
Hardware standby
S
R
D
Q
P8 DDR
0
C
WP8D
Reset
Mode 3
R
D
Q
P8
0
P8 DR
0
C
Mode 1 or 2
WP8
E
RP8
Dual-port RAM
module
Register select
input
WP8D: Write Port 8 DDR
WP8: Write Port 8
RP8:
Read Port 8
Figure 5-14. Port 8 Schematic Diagram (Pin P80)
108
Mode 3
DPME
Reset
R
D
Q
P81 DDR
C
WP8D
Mode 3
Reset
R
D
Q
P8
1
P81 DR
C
Mode 1 or 2
WP8
IOS output
RP8
Dual-port RAM
module
Register select
input
WP8D: Write Port 8 DDR
WP8: Write Port 8
RP8:
Read Port 8
Figure 5-15. Port 8 Schematic Diagram (Pin P81)
109
Mode 3
DPME
Reset
R
D
Q
P8n DDR
C
WP8D
Reset
R
D
P8
Q
n
P8n DR
C
WP8
RP8
Dual-port RAM
module
Register select
input
WP8D: Write Port 8 DDR
WP8: Write Port 8
RP8:
Read Port 8
n = 2, 3
Figure 5-16. Port 8 Schematic Diagram (Pins P82 and P83)
110
Reset
R
D
Q
P84 DDR
C
WP8D
Reset
R
D
Q
P8
4
P84 DR
SCI module
C
WP8
Synchronous serial
transmit enable
Synchronous serial
transmit data
RP8
IRQ3 input
IRQ enable
register
WP8D: Write Port 8 DDR
WP8: Write Port 8
IRQ3 enable
RP8:
Read Port 8
Figure 5-17. Port 8 Schematic Diagram (Pin P84)
111
Reset
R
Q
D
P85 DDR
C
SCI module
WP8D
Synchronous
serial input
enable
Reset
R
D
P8
Q
5
P85 DR
C
WP8
RP8
Synchronous
receive data
IRQ4 input
IRQ enable
register
WP8D: Write Port 8 DDR
WP8: Write Port 8
IRQ4 enable
RP8:
Read Port 8
Figure 5-18. Port 8 Schematic Diagram (Pin P85)
112
Reset
R
Q
D
P86DDR
C
SCI module
WP8D
Synchronous
serial clock
input enable
Reset
R
Q
D
P8
6
P86 DR
C
Synchronous
serial clock
WP8
output enable
Synchronous
serial clock
output
RP8
Synchronous
serial clock
input
IRQ5 input
IRQ enable
register
WP8D: Write Port 8 DDR
WP8: Write Port 8
RP8:
Read Port 8
IRQ5 enable
Figure 5-19. Port 8 Schematic Diagram (Pin P86)
113
5.10 Port 9
Port 9 is an 8-bit input/output port that also provides pins for interrupt input (IRQ0 to IRQ2), A/D
trigger input, system clock (Ø) output, bus control signals (in the expanded modes), and dual-port
RAM interface control signals (in the single-chip mode).
Pins P97 to P93 have different functions in different modes. Pins P92 to P90 have the same
functions in all modes. Table 5-18 lists the pin functions.
Table 5-18. Port 9 Pin Functions
Single-chip mode
DPME = 0 DPME = 1
Pin
P90
P91
P92
P93
P94
P95
P96
P97
Expanded modes
P90 input/output , IRQ2 input, and ADTRG input (simultaneously)
P91 input/output and IRQ1 input (simultaneously)
P92 input/output and IRQ0 input (simultaneously)
RD output
WR output
AS output
Ø output
P93 input/output
P94 input/output
P95 input/output
P96 input or Ø output
P97 input/output
CS input
OE input
RDY output
P96 input or Ø output
WE input
WAIT input
Pins of port 9 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. When used as input pins, they have programmable MOS pull-ups.
Table 5-19 details the port 9 registers.
Table 5-19. Port 9 Registers
Name
Abbreviation
Read/Write
Initial value
H’40 (modes 1 and 2)
H'00 (mode 3
H’00 H’FFC1
Address
Port 9 data direction register P9DDR
W
H’FFC0
Port 9 data register
P9DR
R/W
114
Port 9 Data Direction Register (P9DDR)—H’FFC0
Bit
7
6
5
4
3
2
1
0
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
Modes 1 and 2
Initial value
Read/Write
Mode 3
0
1
0
0
0
0
0
0
W
—
W
W
W
W
W
W
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P9DDR is an 8-bit register that selects the direction of each pin in port 9. A pin functions as an
output pin if the corresponding bit in P9DDR is set to “1,” and as in input pin if the bit is cleared to
“0.”
Port 9 Data Register (P9DR)—H’FFC1
Bit
7
P97
0
6
P96
0
5
P95
0
4
P94
0
3
P93
0
2
P92
0
1
P91
0
0
P90
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P9DR is an 8-bit register containing the data for pins P97 to P90. When the CPU reads P9DR, for
output pins (P9DDR = "1") it reads the value in the P9DR latch, but for input pins (P9DDR = "0"),
it obtains the logic level directly from the pin, bypassing the P9DR latch. This also applies to pins
used for interrupt input, A/D trigger input, clock output, and control signal input or output.
MOS Pull-Ups: Are available for input pins, including pins used for input of interrupt request
signals, the A/D trigger signal, and control signals. Software can turn the MOS pull-up on by
writing a “1” in P9DR, and turn it off by writing a “0.”
Pins P90, P91, and P92: Can be used for general-purpose input or output, interrupt request input,
or A/D trigger input. See Table 5-18. If a pin is used for interrupt or A/D trigger input, its data
direction bit should be cleared to "0," so that the output from P9DR will not generate an interrupt
request or A/D trigger signal.
Pins P93 and P94: In modes 1 and 2 (the expanded modes), these pins are used for output of the
RD and WR bus control signals. They are unaffected by the values in P9DDR and P9DR, and their
115
MOS pull-ups are automatically turned off.
In mode 3 (single-chip mode) with the dual-port RAM disabled (DPME = "0"), these pins can be
used for general-purpose input or output.
In slave mode (mode 3 with DPME = "1"), these pins are used for input of the CS and OE dual-port
RAM interface control signals. They are unaffected by the values in P9DDR and P9DR, except
that software can turn on their MOS pull-ups by clearing their data direction bits to "0" and setting
their data bits to "1."
Pin P95: In modes 1 and 2 and slave mode, this pin is used for output of the AS bus control signal
or RDY dual-port RAM interface control signal. It is unaffected by the values in P9DDR and
P9DR, and its MOS pull-up is automatically turned off.
In mode 3 with the dual-port RAM disabled (DPME = "0"), this pin can be used for general-
purpose input or output.
Pin P96: In modes 1 and 2, this pin is used for system clock (Ø) output. Its MOS pull-up is
automatically turned off.
In mode 3, this pin is used for general-purpose input if P96DDR is cleared to "0," or system clock
output if P96DDR is set to "1."
Pin P97: In modes 1 and 2 and slave mode, this pin is used for input of the WAIT bus control
signal or WE dual-port RAM interface control signal. It is unaffected by the values in P9DDR and
P9DR, except that software can turn on its MOS pull-up by clearing its data direction bit to "0" and
setting its data bit to "1."
In mode 3 (single-chip mode) with the dual-port RAM disabled (DPME = "0"), this pin can be used
for general-purpose input or output.
Reset: In the single-chip mode (mode 3), a reset initializes all pins of port 9 to the general-purpose
input function with the MOS pull-ups off. In the expanded modes (modes 1 and 2), P90 to P92 are
initialized as input port pins, and P93 to P97 are initialized to their bus control and system clock
output functions.
Hardware Standby Mode: All pins are placed in the high-impedance state with their MOS pull-
ups off.
116
Software Standby Mode: All pins remain in their previous state. For RD, WR, AS, and Ø this
means the High output state.
Figures 5-20 to 5-25 show schematic diagrams of port 9.
Reset
R
Q
D
P90 DDR
C
WP9D
Reset
R
P9
Q
0
D
P90 DR
C
WP9
RP9
A/D converter
module
ADTRG
IRQ2 input
IRQ enable
register
WP8D: Write Port 8 DDR
WP8: Write Port 8
RP8:
Read Port 8
IRQ2 enable
Figure 5-20. Port 9 Schematic Diagram (Pin P90)
117
Reset
R
Q
D
P9n DDR
C
WP9D
Reset
R
Q
P9
D
n
P9n DR
C
WP9
RP9
IRQ0 input
IRQ1 input
IRQ enable
register
WP9D: Write Port 9 DDR
WP9: Write Port 9
RP9:
n = 1, 2
Read Port 9
IRQ0 enable
IRQ1 enable
Figure 5-21. Port 9 Schematic Diagram (Pins P91 to P92)
118
Mode 3
DPME
Hardware standby
Reset
Mode 1 or 2
R
D
Q
P9n DDR
C
WP9D
Reset
Mode 3
R
D
Q
P9
n
P9n DR
C
Mode 1 or 2
WP9
RD output
WR output
RP9
Dual-port RAM
module
CS input
OE input
WP9D: Write Port 9 DDR
WP9: Write Port 9
RP9:
n:
Read Port 9
3, 4
Figure 5-22. Port 9 Schematic Diagram (Pins P93 and P94)
119
Mode 3
DPME
Mode
1 or 2
Reset
Hardware standby
R
D
Q
P95 DDR
Dual-port RAM
module
C
WP9D
RDY
output
Reset
R
D
P9
5
Q
*
P95 DR
C
Mode 1 or 2
WP9
AS output
RP9
WP9D: Write Port 9 DDR
WP9: Write Port 9
RP9:
*
Read Port 9
NMOS open drain if DPME="1" (Slave mode)
Figure 5-23. Port 9 Schematic Diagram (Pin P95)
120
Mode1,2 Reset
Hardware standby
S
Q
R
D
P96 DDR
C
*
WP9D
Reset
R
D
Q
P96 DR
C
WP9
ø
P9
6
RP9
WP9D: Write Port 9 DDR
WP9: Write Port 9
RP9:
*
Read Port 9
Set-priority
Figure 5-24. Port 9 Schematic Diagram (Pin P96)
121
DPME Mode 3
Mode 1 or 2
Reset
R
D
Q
P97 DDR
C
WP9D
Reset
R
D
P9
Q
7
P97 DR
C
WP9
RP9
WAIT input
Dual-port RAM
module
WE input
WP9D: Write Port 9 DDR
WP9: Write Port 9
RP9:
Read Port 9
Figure 5-25. Port 9 Schematic Diagram (Pin P97)
122
Section 6. 16-Bit Free-Running Timer
6.1 Overview
The H8/330 has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free-running
counter as a time base. Applications of the FRT module include rectangular-wave output (up to
two independent waveforms), input pulse width measurement, and measurement of external clock
periods.
6.1.1 Features
The features of the free-running timer module are listed below.
• Selection of four clock sources
The free-running counter can be driven by an internal clock source (Ø/2, Ø/8, or Ø/32), or an
external clock input (enabling use as an external event counter).
• Two independent comparators
Each comparator can generate an independent waveform.
• Four input capture channels
The current count can be captured on the rising or falling edge (selectable) of an input signal.
The four input capture registers can be used separately, or in a buffer mode.
• Counter can be cleared under program control
The free-running counters can be cleared on compare-match A.
• Seven independent interrupts
Compare-match A and B, input capture A to D, and overflow interrupts are requested
independently.
6.1.2 Block Diagram
Figure 6-1 shows a block diagram of the free-running timer.
123
Internal
clock sources
Ø/2
External
clock source
FTCI
Ø/8
Ø/32
Clock
OCRA (H/L)
Comparator A
FRC(H/L)
Clock select
Compare-
match A
FTOA
FTOB
Overflow
Clear
Internal
data bus
Comparator B
OCRB (H/L)
Compare-
match B
Control
logic
Capture
ICRA (H/L)
ICRB (H/L)
FTIA
FTIB
ICRC (H/L)
ICRD (H/L)
FTIC
FTID
TCSR
TIER
TCR
TOCR
ICIA
ICIB
ICIC
ICID
Interrupt signals
OCIA
OCIB
FOVI
FRC:
OCRA, B:
Free-Running Counter (16 bits)
Output Compare Register A, B (16 bits)
TIER: Timer Interrupt Enable Register (8 bits)
TCR: Timer Control Register (8 bits)
TOCR: Timer Output Compare Control
Register (8 bits)
ICRA, B, C, D: Input Capture Register A, B, C, D (16 bits)
TCSR: Timer Control/Status Register (8 bits)
Figure 6-1. Block Diagram of 16-Bit Free-Running Timer
124
6.1.3 Input and Output Pins
Table 6-1 lists the input and output pins of the free-running timer module.
Table 6-1. Input and Output Pins of Free-Running Timer Module
Name
Abbreviation
I/O
Function
Counter clock input FTCI
Input
Input of external free-running counter clock
signal
Output compare A
Output compare B
Input capture A
FTOA
FTOB
FTIA
Output
Output
Input
Output controlled by comparator A
Output controlled by comparator B
Trigger for capturing current count into input
capture register A
Input capture B
Input capture C
Input capture D
FTIB
FTIC
FTID
Input
Input
Input
Trigger for capturing current count into input
capture register B
Trigger for capturing current count into input
capture register C
Trigger for capturing current count into input
capture register D
6.1.4 Register Configuration
Table 6-2 lists the registers of the free-running timer module.
Table 6-2. Register Configuration
Initial
Name
Abbreviation R/W
value
H’01
H’00
H’00
H’00
H’FF
H’FF
H’00
H’E0
H’00
H’00
Address
H’FF90
H’FF91
H’FF92
H’FF93
H’FF94
H’FF95
H’FF96
H’FF97
H’FF98
H’FF99
Timer interrupt enable register
Timer control/status register
Free-running counter (High)
Free-running counter (Low)
Output compare register A/B (High)*
TIER
R/W
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R
1
TCSR
FRC (H)
FRC (L)
OCRA/B (H)
OCRA/B (L)
TCR
2
2
Output compare register A/B (Low)*
Timer control register
Timer output compare control register
Input capture register A (High)
Input capture register A (Low)
TOCR
ICRA (H)
ICRA (L)
R
Notes:
1
* Software can write a “0” to clear bits 7 to 1, but cannot write a “1” in these bits.
2
* OCRA and OCRB share the same addresses. Access is controlled by the OCRS bit in TOCR.
125
Table 6-2. Register Configuration (cont.)
Initial
Name
Abbreviation R/W
value
H’00
H’00
H’00
H’00
H’00
H’00
Address
H’FF9A
H’FF9B
H’FF9C
H’FF9D
H’FF9E
H’FF9F
Input capture register B (High)
Input capture register B (Low)
Input capture register C (High)
Input capture register C (Low)
Input capture register D (High)
Input capture register D (Low)
ICRB (H)
ICRB (L)
ICRC (H)
ICRC (L)
ICRD (H)
ICRD (L)
R
R
R
R
R
R
6.2 Register Descriptions
6.2.1 Free-Running Counter (FRC) – H’FF92
Bit
15 14 13
12 11 10
9
0
8
0
7
0
6
5
0
4
0
3
0
2
0
1
0
0
0
Initial 0
value
0
0
0
0
0
0
Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Write
The FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated
from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and
CKS0) of the timer control register (TCR).
When the FRC overflows from H’FFFF to H’0000, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to “1.”
Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is written
or read. See section 6.3, “CPU Interface” for details.
The FRC is initialized to H’0000 at a reset and in the standby modes. It can also be cleared by
compare-match A.
126
6.2.2 Output Compare Registers A and B (OCRA and OCRB) – H’FF94
Bit
15 14 13
12 11 10
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Initial 1
value
1
1
1
1
1
Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Write
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually
compared with the value in the FRC. When a match is detected, the corresponding output compare
flag (OCFA or OCFB) is set in the timer control/status register (TCSR).
In addition, if the output enable bit (OEA or OEB) in the timer output compare control register
(TOCR) is set to “1,” when the output compare register and FRC values match, the logic level
selected by the output level bit (OLVLA or OLVLB) in the TOCR is output at the output compare
pin (FTOA or FTOB).
OCRA and OCRB share the same address. They are differentiated by the OCRS bit in the TOCR.
A temporary register (TEMP) is used for write access, as explained in section 6.3, "CPU Interface."
OCRA and OCRB are initialized to H’FFFF at a reset and in the standby modes.
6.2.3 Input Capture Registers A to D (ICRA to ICRD) – H’FF98, H’FF9A, H’FF9C, H’FF9E
Bit
15 14 13
12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Initial 0
value
0
0
0
0
0
Read/ R
Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Each input capture register is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected, the
current value of the FRC is copied to the corresponding input capture register (ICRA to ICRD). At
the same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status
register (TCSR) is set to “1.” The input capture edge is selected by the input edge select bits
(IEDGA to IEDGD) in the timer interrupt enable register (TIER).
127
Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in
the timer control register (TCR) is set to “1,” ICRC is used as a buffer register for ICRA as shown
in Figure 6-2. When an FTIA input is received, the old ICRA contents are moved into ICRC, and
the new FRC count is copied into ICRA.
BUFEA
IEDGA IEDGC
Edge detect and
capture signal
FTIA
generating circuit
FRC
ICRC
ICRA
BUFEA: Buffer Enable A
IEDGA: Input Edge Select A
IEDGC: Input Edge Select C
ICRC:
ICRA:
FRC:
Input Capture Register C
Input Capture Register A
Free-Running Counter
Figure 6-2. Input Capture Buffering
Similarly, when the BUFEB bit in TIER is set to “1,” ICRD is used as a buffer register for ICRB.
When input capture is buffered, if the two input edge bits are set to different values (IEDGA ≠
IEDGC or IEDGB ≠ IEDGD), then input capture is triggered on both the rising and falling edges of
the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA =
IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge.
Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when
they are read. See Section 6.3, “CPU Interface” for details.
To ensure input capture, the width of the input capture pulse (FTIA, FTIB, FTIC, FTID) should be
at least 1.5 system clock periods (1.5·Ø). When triggering is enabled on both edges, the input
capture pulse width should be at least 2.5 system clock periods.
Ø
FTIA, FTIB,
FTIC, orFTID
Figure 6-3. Minimum Input Capture Pulse Width
128
The input capture registers are initialized to H’0000 at a reset and in the standby modes.
Note: When input capture is detected, the FRC value is transferred to the input capture register
even if the input capture flag is already set.
6.2.4 Timer Interrupt Enable Register (TIER) – H’FF90
Bit
7
6
5
4
3
2
1
0
—
1
ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE
Initial value
Read/Write
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
The TIER is an 8-bit readable/writable register that enables and disables interrupts.
The TIER is initialized to H’01 (all interrupts disabled) at a reset and in the standby modes.
Bit 7 – Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input
capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register
(TCSR) is set to “1.”
Bit 7
ICIAE
Description
0
1
Input capture interrupt request A (ICIA) is disabled.
Input capture interrupt request A (ICIA) is enabled.
(Initial value)
Bit 6 – Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input
capture interrupt B (ICIB) when input capture flag B (ICFB) in the timer status/control register
(TCSR) is set to “1.”
Bit 6
ICIBE
Description
0
1
Input capture interrupt request B (ICIB) is disabled.
Input capture interrupt request B (ICIB) is enabled.
(Initial value)
Bit 5 – Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input
capture interrupt C (ICIC) when input capture flag C (ICFC) in the timer status/control register
(TCSR) is set to “1.”
129
Bit 5
ICICE
Description
0
1
Input capture interrupt request C (ICIC) is disabled.
Input capture interrupt request C (ICIC) is enabled.
(Initial value)
Bit 4 – Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input
capture interrupt D (ICID) when input capture flag D (ICFD) in the timer status/control register
(TCSR) is set to “1.”
Bit 4
ICIDE
Description
0
1
Input capture interrupt request D (ICID) is disabled.
Input capture interrupt request D (ICID) is enabled.
(Initial value)
Bit 3 – Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request
output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer status/control
register (TCSR) is set to “1.”
Bit 3
OCIAE Description
0
1
Output compare interrupt request A (OCIA) is disabled.
Output compare interrupt request A (OCIA) is enabled.
(Initial value)
Bit 2 – Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request
output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer status/control
register (TCSR) is set to “1.”
Bit 2
OCIBE Description
0
1
Output compare interrupt request B (OCIB) is disabled.
Output compare interrupt request B (OCIB) is enabled.
(Initial value)
Bit 1 – Timer overflow Interrupt Enable (OVIE): This bit selects whether to request a free-
running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer
status/control register (TCSR) is set to “1.”
130
Bit 1
OVIE
Description
0
1
Timer overflow interrupt request (FOVI) is disabled.
Timer overflow interrupt request (FOVI) is enabled.
(Initial value)
Bit 0 – Reserved: This bit cannot be modified and is always read as “1.”
6.2.5 Timer Control/Status Register (TCSR) – H’FF91
Bit
7
ICFA
0
6
ICFB
0
5
ICFC
0
4
ICFD
0
3
2
1
0
OCFA OCFB
OVF CCLRA
Initial value
Read/Write
0
0
0
0
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
R/W
The TCSR is an 8-bit readable and partially writable* register contains the seven interrupt flags and
specifies whether to clear the counter on compare-match A (when the FRC and OCRA values
match).
* Software can write a “0” in bits 7 to 1 to clear the flags, but cannot write a “1” in these bits.
The TCSR is initialized to H’00 at a reset and in the standby modes.
Bit 7 – Input Capture Flag A (ICFA): This status bit is set to “1” to flag an input capture A
event. If BUFEA = “0,” ICFA indicates that the FRC value has been copied to ICRA. If BUFEA =
“1,” ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value
has been copied to ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 7
ICFA
Description
0
To clear ICFA, the CPU must read ICFA after it
has been set to "1," then write a “0” in this bit.
This bit is set to 1 when an FTIA input signal causes the FRC
value to be copied to ICRA.
(Initial value)
1
131
Bit 6 – Input Capture Flag B (ICFB): This status bit is set to “1” to flag an input capture B
event. If BUFEB = “0,” ICFB indicates that the FRC value has been copied to ICRB. If BUFEB =
“1,” ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value
has been copied to ICRB.
ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6
ICFB
Description
0
To clear ICFB, the CPU must read ICFB after it
has been set to "1," then write a “0” in this bit.
This bit is set to 1 when an FTIB input signal causes the FRC value
to be copied to ICRB.
(Initial value)
1
Bit 5 – Input Capture Flag C (ICFC): This status bit is set to “1” to flag input of a rising or
falling edge of FTIC as selected by the IEDGC bit. When BUFEA = “0,” this indicates capture of
the FRC count in ICRC. When BUFEA = “1,” however, the FRC count is not captured, so ICFC
becomes simply an external interrupt flag. In other words, the buffer mode frees FTIC for use as a
general-purpose interrupt signal (which can be enabled or disabled by the ICICE bit).
ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 5
ICFC
Description
0
To clear ICFC, the CPU must read ICFC after it
has been set to "1," then write a “0” in this bit.
This bit is set to 1 when an FTIC input signal is received.
(Initial value)
1
Bit 4 – Input Capture Flag D (ICFD): This status bit is set to “1” to flag input of a rising or
falling edge of FTID as selected by the IEDGD bit. When BUFEB = “0,” this indicates capture of
the FRC count in ICRD. When BUFEB = “1,” however, the FRC count is not captured, so ICFD
becomes simply an external interrupt flag. In other words, the buffer mode frees FTID for use as a
general-purpose interrupt signal (which can be enabled or disabled by the ICIDE bit).
ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software.
132
Bit 4
ICFD
0
Description
To clear ICFD, the CPU must read ICFD after it
has been set to "1," then write a “0” in this bit.
This bit is set to 1 when an FTID input signal is received.
(Initial value)
1
Bit 3 – Output Compare Flag A (OCFA): This status flag is set to “1” when the FRC value
matches the OCRA value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 3
OCFA
Description
0
To clear OCFA, the CPU must read OCFA after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when FRC = OCRA.
(Initial value)
1
Bit 2 – Output Compare Flag B (OCFB): This status flag is set to “1” when the FRC value
matches the OCRB value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 2
OCFB
Description
0
To clear OCFB, the CPU must read OCFB after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when FRC = OCRB.
(Initial value)
1
Bit 1 – Timer Overflow Flag (OVF): This status flag is set to “1” when the FRC overflows
(changes from H’FFFF to H’0000). This flag must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 1
OVF
Description
0
To clear OVF, the CPU must read OVF after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when FRC changes from H’FFFF to H’0000.
(Initial value)
1
133
Bit 0 – Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match
A (when the FRC and OCRA values match).
Bit 0
CCLRA Description
0
1
The FRC is not cleared.
(Initial value)
The FRC is cleared at compare-match A.
6.2.6 Timer Control Register (TCR) – H’FF96
Bit
7
6
5
4
3
2
1
0
IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1
CKS0
0
Initial value
Read/Write
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input
capture signals, enables the input capture buffer mode, and selects the FRC clock source.
The TCR is initialized to H’00 at a reset and in the standby modes.
Bit 7 – Input Edge Select A (IEDGA): This bit causes input capture A events to be recognized on
the selected edge of the input capture A signal (FTIA).
Bit 7
IEDGA Description
0
1
Input capture A events are recognized on the falling edge of FTIA.
Input capture A events are recognized on the rising edge of FTIA.
(Initial value)
Bit 6 – Input Edge Select B (IEDGB): This bit causes input capture B events to be recognized on
the selected edge of the input capture B signal (FTIB).
Bit 6
IEDGB Description
0
1
Input capture B events are recognized on the falling edge of FTIB.
Input capture B events are recognized on the rising edge of FTIB.
(Initial value)
134
Bit 5 – Input Edge Select C (IEDGC): This bit causes input capture C events to be recognized on
the selected edge of the input capture C signal (FTIC). In buffer mode (when BUFEA = “1”),
it also causes input capture A events to be recognized on the selected edge of FTIA.
Bit 5
IEDGC Description
0
1
Input capture C events are recognized on the falling edge of FTIC.
Input capture C events are recognized on the rising edge of FTIC.
(Initial value)
Bit 4 – Input Edge Select D (IEDGD): This bit causes input capture D events to be recognized on
the selected edge of the input capture D signal (FTID). In the buffer mode (when BUFEB = “1”),
it also causes input capture B events to be recognized on the selected edge of FTIB.
Bit 4
IEDGD Description
0
1
Input capture D events are recognized on the falling edge of FTID.
Input capture D events are recognized on the rising edge of FTID.
(Initial value)
Bit 3 – Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for
ICRA.
Bit 3
BUFEA Description
0
1
ICRC is used for input capture C.
(Initial value)
ICRC is used as a buffer register for input capture A. Input C is not captured.
Bit 2 – Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for
ICRB.
Bit 2
BUFEB Description
0
1
ICRD is used for input capture D.
(Initial value)
ICRD is used as a buffer register for input capture B. Input D is not captured.
Bits 1 and 0 – Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
135
Bit 1
Bit 0
CKS1
CKS0
Description
0
0
1
1
0
1
0
1
Ø/2 Internal clock source
Ø/8 Internal clock source
Ø/32 Internal clock source
External clock source (rising edge)
(Initial value)
6.2.7 Timer Output Compare Control Register (TOCR) – H’FF97
Bit
7
—
1
6
—
1
5
—
1
4
OCRS
0
3
2
1
0
OEA
0
OEB OLVLA OLVLB
Initial value
Read/Write
0
0
0
—
—
—
R/W
R/W
R/W
R/W
R/W
The TOCR is an 8-bit readable/writable register that controls the output compare function.
The TOCR is initialized to H’E0 at a reset and in the standby modes.
Bits 7 to 5 – Reserved: These bits cannot be modified and are always read as “1.”
Bit 4 – Output Compare Register Select (OCRS): When the CPU accesses addresses H’FF94
and H’FF95, this bit directs the access to either OCRA or OCRB. These two registers share the
same addresses as follows:
Upper byte of OCRA and upper byte of OCRB: H’FF94
Lower byte of OCRA and lower byte of OCRB: H’FF95
Bit 4
OCRS
Description
0
1
The CPU can access OCRA.
The CPU can access OCRB.
(Initial value)
Bit 3 – Output Enable A (OEA): This bit enables or disables output of the output compare A
signal (FTOA). When output compare A is disabled, the corresponding pin is used as a general-
purpose input/output port.
Bit 3
OEA
Description
0
1
Output compare A output is disabled.
Output compare A output is enabled.
(Initial value)
136
Bit 2 – Output Enable B (OEB): This bit enables or disables output of the output compare B
signal (FTOB). When output compare B is disabled, the corresponding pin is used as a general-
purpose input/output or interrupt port.
Bit 2
OEB Description
0
1
Output compare B output is disabled.
Output compare B output is enabled.
(Initial value)
Bit 1 – Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin
when the FRC and OCRA values match.
Bit 1
OLVLA Description
0
1
A “0” logic level (Low) is output for compare-match A.
A “1” logic level (High) is output for compare-match A.
(Initial value)
Bit 0 – Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin
when the FRC and OCRB values match.
Bit 0
OLVLB Description
0
1
A “0” logic level (Low) is output for compare-match B.
A “1” logic level (High) is output for compare-match B.
(Initial value)
6.3 CPU Interface
The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture
registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When
the CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the
access is performed using an 8-bit temporary register (TEMP).
These registers are written and read as follows:
• Register Write
When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when
the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16
bits are written in the register simultaneously.
137
• Register Read
When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte
is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP.
(As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower bytes
directly, without using TEMP.)
Programs that access these registers should normally use word access. Equivalently, they may
access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not be
transferred correctly if the bytes are accessed in reverse order, if only one byte is accessed, or if the
upper and lower bytes are accessed separately and another register is accessed in between, altering
the value in TEMP.
Coding Examples
To write the contents of general register R0 to OCRA:
To transfer the contents of ICRA to general register R0:
MOV.W R0, @OCRA
MOV.W @ICRA, R0
Figure 6-4 shows the data flow when the FRC is accessed. The other registers are accessed in the
same way.
(1) Upper byte write
Module data bus
CPU writes
data H’AA
Bus interface
TEMP
[H’AA]
FRCL
[
FRCH
[
]
]
(2) Lower byte write
Module data bus
CPU writes
data H’55
Bus interface
TEMP
[H’AA]
FRCH
[H’AA]
FRCL
[H’55]
Figure 6-4 (a). Write Access to FRC (When CPU Writes H’AA55)
138
(1) Upper byte read
Module data bus
CPU writes
data H’AA
Bus interface
TEMP
[H’55]
FRCH
[H’AA]
FRCL
[H’55]
(2) Lower byte read
Module data bus
CPU writes
data H’55
Bus interface
TEMP
[H’55]
FRCH
FRCL
[
]
[
]
Figure 6-4 (b). Read Access to FRC (When FRC Contains H’AA55)
6.4 Operation
6.4.1 FRC Incrementation Timing
The FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source.
The internal clock sources are created from the system clock (Ø) by a prescaler. The FRC
increments on a pulse generated from the falling edge of the prescaler output. See Figure 6-5.
139
Ø
Prescaler
output
FRC clock
pulse
FRC
N – 1
N
N + 1
Figure 6-5. Increment Timing for Internal Clock Source
If external clock input is selected, the FRC increments on the rising edge of the FTCI clock signal.
Figure 6-6 shows the increment timing.
The pulse width of the external clock signal must be at least 1.5 system clock (Ø) periods. The
counter will not increment correctly if the pulse width is shorter than one Ø period.
Ø
FTCI
FRC clock pulse
FRC
N
N + 1
Figure 6-6. Increment Timing for External Clock Source
Ø
FTCI
Figure 6-7. Minimum External Clock Pulse Width
140
6.4.2 Output Compare Timing
(1) Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags
are set to “1” by an internal compare-match signal generated when the FRC value matches the
OCRA or OCRB value. This compare-match signal is generated at the last state in which the two
values match, just before the FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 6-8 shows the timing of the setting of the output
compare flags.
Ø
N
N
N + 1
FRC
OCRA or OCRB
Internal compare-
match signal
OCFAorOCFB
Figure 6-8. Setting of Output Compare Flags
(2) Timing of Output Compare Flag (OCFA or OCFB) Clearing: The output compare flag
OCFA or OCFB is cleared when the CPU writes a “0” in this bit.
Write cycle: CPU writes "0" in OCFA or OCFB
T1
T2
T 3
Ø
OCFA or OCFB
Figure 6-9. Clearing of Output Compare Flag
141
(3) Output Timing: When a compare-match occurs, the logic level selected by the output level
bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 6-
10 shows the timing of this operation for compare-match A.
Ø
FRC
N
N
N + 1
N
N
N + 1
OCRA
Internal compare-
match A signal
Clear *
OLVLA
FTOA
* Cleared by software
Figure 6-10. Timing of Output Compare A
(4) FRC Clear Timing: If the CCLRA bit in the TCSR is set to “1,” the FRC is cleared when
compare-match A occurs. Figure 6-11 shows the timing of this operation.
Ø
Internal compare-
match A signal
FRC
N
H'0000
Figure 6-11. Clearing of FRC by Compare-Match A
6.4.3 Input Capture Timing
(1) Input Capture Timing: An internal input capture signal is generated from the rising or falling
edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the corresponding
IEDGx bit in TCR. Figure 6-12 shows the usual input capture timing when the rising edge is
selected (IEDGx = “1”).
142
Ø
Input at FTI pin
Internal input
capture signal
Figure 6-12. Input Capture Timing (Usual Case)
If the upper byte of ICRx is being read when the input capture signal arrives, the internal input
capture signal is delayed by one state. Figure 6-13 shows the timing for this case.
Read cycle: CPU reads upper byte of ICR
T 1
T 2
T 3
Ø
Input at FTI pin
Internal input
capture signal
Figure 6-13. Input Capture Timing (1-State Delay)
In buffer mode, this delay occurs if the CPU is reading either of the two registers concerned. When
ICRA and ICRC are used in buffer mode, for example, if the upper byte of either ICRA or ICRC is
being read when the FTIA input arrives, the internal input capture signal is delayed by one state.
Figure 6-14 shows the timing for this case. The case of ICRB and ICRD is similar.
Read cycle: CPU reads upper byte of ICRA or ICRC
T 1
T 2
T 3
Ø
Input at
FTIA pin
Internal input
capture signal
Figure 6-14. Input Capture Timing (1-State Delay, Buffer Mode)
143
Figure 6-15 shows how input capture operates when ICRA and ICRC are used in buffer mode and
IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and
IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
Ø
FTIA
Internal input
capture signal
n
n + 1
N
N + 1
FRC
ICRA
α
β
n
n
N
n
α
α
ICRC
Figure 6-15. Buffered Input Capture with Both Edges Selected
In this mode, FTIC does not cause the FRC contents to be copied to ICRC. However, input capture
flag C still sets on the edge of FTIC selected by IEDGC, and if the interrupt enable bit (ICICE) is
set, a CPU interrupt is requested.
The situation when ICRB and ICRD are used in buffer mode is similar.
(2) Timing of Input Capture Flag (ICF) Setting: The input capture flag ICFx (x = A, B, C, D) is
set to “1” by the internal input capture signal. Figure 6-16 shows the timing of this operation.
Ø
Internal input
capture signal
ICF
FRC
ICR
N
N
Figure 6-16. Setting of Input Capture Flag
144
(3) Timing of Input Capture Flag (ICF) Clearing: The input capture flag ICFx (x = A, B, C, D)
is cleared when the CPU writes a “0” in this bit.
Write cycle: CPU writes "0" in ICFx
T1
T2
T3
Ø
ICFx
Figure 6-17. Clearing of Input Capture Flag
6.4.4 Setting of FRC Overflow Flag (OVF)
The FRC overflow flag (OVF) is set to “1” when the FRC overflows (changes from H’FFFF to
H’0000). Figure 6-18 shows the timing of this operation.
Ø
FRC
H'FFFF
H'0000
Internal overflow
signal
OVF
Figure 6-18. Setting of Overflow Flag (OVF)
(2) Timing of Overflow Flag (OVF) Clearing: The overflow flag is cleared when the CPU
writes a “0” in this bit.
Write cycle: CPU writes "0" in OVF
T1
T2
T3
Ø
OVF
Figure 6-19. Clearing of Overflow Flag
145
6.5 Interrupts
The free-running timer channel can request seven types of interrupts: input capture A to D (ICIA,
ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each
interrupt is requested when the corresponding enable and flag bits are set. Independent signals are
sent to the interrupt controller for each type of interrupt. Table 6-3 lists information about these
interrupts.
Table 6-3. Free-Running Timer Interrupts
Interrupt
ICIA
Description
Priority
Requested when ICFA and ICIAE are set
Requested when ICFB and ICIBE are set
Requested when ICFC and ICICE are set
Requested when ICFD and ICIDE are set
Requested when OCFA and OCIAE are set
Requested when OCFB and OCIBE are set
Requested when OVF and OVIE are set
High
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
Low
6.6 Sample Application
In the example below, the free-running timer channel is used to generate two square-wave outputs
with a 50% duty factor and arbitrary phase relationship. The programming is as follows:
(1) The CCLRA bit in the TCSR is set to “1.”
(2) Each time a compare-match interrupt occurs, software inverts the corresponding output level
bit in TOCR (OLVLA or OLVLB).
FRC
H’FFFF
Clear counter
OCRA
OCRB
H’0000
FTOA
FTOB
Figure 6-20. Square-Wave Output (Example)
146
6.7 Application Notes
Application programmers should note that the following types of contention can occur in the free-
running timers.
(1) Contention between FRC Write and Clear: If an internal counter clear signal is generated
during the T3 state of a write cycle to the lower byte of the free-running counter, the clear signal
takes priority and the write is not performed.
Figure 6-21 shows this type of contention.
Write cycle: CPU write to lower byte of FRC
T1
T2
T3
Ø
Internal address bus
FRC address
Internal write signal
FRC clear signal
FRC
N
H'0000
Figure 6-21. FRC Write-Clear Contention
(2) Contention between FRC Write and Increment: If an FRC increment pulse is generated
during the T3 state of a write cycle to the lower byte of the free-running counter, the write takes
priority and the FRC is not incremented.
Figure 6-22 shows this type of contention.
147
Write cycle: CPU write to lower byte of FRC
T 1
T 2
T 3
Ø
Internal address bus
FRC address
Internal write signal
FRC clock pulse
FRC
N
M
Write data
Figure 6-22. FRC Write-Increment Contention
(3) Contention between OCR Write and Compare-Match: If a compare-match occurs during
the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes precedence and
the compare-match signal is inhibited.
Figure 6-23 shows this type of contention.
148
Write cycle: CPU write to lower byte of OCRA or OCRB
T1
T2
T3
Ø
Internal address bus
OCR address
Internal write signal
FRC
N
N
N + 1
M
OCRAorOCRB
Write data
Compare-match
A or B signal
Inhibited
Figure 6-23. Contention between OCR Write and Compare-Match
(4) Incrementation Caused by Changing of Internal Clock Source: When an internal clock
source is changed, the changeover may cause the FRC to increment. This depends on the time at
which the clock select bits (CKS1 and CKS0) are rewritten, as shown in Table 6-4.
The pulse that increments the FRC is generated at the falling edge of the internal clock source. If
clock sources are changed when the old source is High and the new source is Low, as in case No. 3
in Table 6-5, the changeover generates a falling edge that triggers the FRC increment clock pulse.
Switching between an internal and external clock source can also cause the FRC to increment.
149
Table 6-4. Effect of Changing Internal Clock Sources
No.
Description
Timing chart
Low → Low:
Old clock
source
CKS1 and CKS0 are
rewritten while both
clock sources are Low.
1
New clock
source
FRC clock
pulse
N
N + 1
FRC
CKS rewrite
Low → High:
Old clock
source
CKS1 and CKS0 are
rewritten while old
clock source is Low and
new clock source is High.
2
New clock
source
FRC clock
pulse
N
N + 1
N + 2
FRC
CKS rewrite
High → Low:
Old clock
source
CKS1 and CKS0 are
rewritten while old
clock source is High and
new clock source is Low.
3
New clock
source
*
FRC clock
pulse
N
N + 1
N + 2
FRC
CKS rewrite
* The switching of clock sources is regarded as a falling edge that increments the FRC.
150
Table 6-4. Effect of Changing Internal Clock Sources (cont.)
No.
Description
Timing chart
High → High:
Old clock
source
CKS1 and CKS0 are
rewritten while both
clock sources are High.
4
New clock
source
FRC clock
pulse
N
N + 1
N + 2
FRC
CKS rewrite
151
Section 7. 8-Bit Timers
7.1 Overview
The H8/330 chip includes an 8-bit timer module with two channels (TMR0 and TMR1). Each
channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that
are constantly compared with the TCNT value to detect compare-match events. One application of
the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty factor.
7.1.1 Features
The features of the 8-bit timer module are listed below.
• Selection of four clock sources
The counters can be driven by an internal clock signal (Ø/8, Ø/64, or Ø/1024) or an external
clock input (enabling use as an external event counter).
• Selection of three ways to clear the counters
The counters can be cleared on compare-match A or B, or by an external reset signal.
• Timer output controlled by two time constants
The timer output signal in each channel is controlled by two independent time constants,
enabling the timer to generate output waveforms with an arbitrary duty factor.
• Three independent interrupts
Compare-match A and B and overflow interrupts can be requested independently.
7.1.2 Block Diagram
Figure 7-1 shows a block diagram of one channel in the 8-bit timer module. The other channel is
identical.
153
Internal
clock sources
Ø/8
External
clock source
TMCI
Ø/64
Ø/1024
Clock
Clock select
TCORA
Comparator A
TCNT
Compare-
match A
TMO
TMRI
Overflow
Clear
Internal
data bus
Comparator B
TCORB
Compare-
match B
Control
logic
TCSR
TCR
CMIA
CMIB
OVI
Interrupt signals
TCR:
Timer Control Register (8 bits)
TCSR: Timer Control Status Register (8 bits)
TCORA: Time Constant Register A (8 bits)
TCORB: Time Constant Register B (8 bits)
TCNT: Timer Counter
Figure 7-1. Block Diagram of 8-Bit Timer
7.1.3 Input and Output Pins
Table 7-1 lists the input and output pins of the 8-bit timer.
Table 7-1. Input and Output Pins of 8-Bit Timer
Abbreviation
Name
TMR0
TMR1
TMO1
TMCI1
TMRI1
I/O
Function
Timer output
TMO0
Output
Input
Input
Output controlled by compare-match
External clock source for the counter
External reset signal for the counter
Timer clock input TMCI0
Timer reset input TMRI0
154
7.1.4 Register Configuration
Table 7-2 lists the registers of the 8-bit timer module. Each channel has an independent set of
registers.
Table 7-2. 8-Bit Timer Registers
Address
Name
Abbreviation R/W
Initial value TMR0
TMR1
Timer control register
Timer control/status register
Timer constant register A
Timer constant register B
Timer counter
TCR
R/W
H’00
H’10
H’FF
H’FF
H’00
H’FFC8 H’FFD0
H’FFC9 H’FFD1
H’FFCA H’FFD2
H’FFCB H’FFD3
H’FFCC H’FFD4
TCSR
R/(W)*
R/W
TCORA
TCORB
TCNT
R/W
R/W
* Software can write a “0” to clear bits 7 to 5, but cannot write a “1” in these bits.
7.2 Register Descriptions
7.2.1 Timer Counter (TCNT) – H’FFC8 (TMR0), H’FFD0 (TMR1)
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from one of
four clock sources. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) of the
timer control register (TCR). The CPU can always read or write the timer counter.
The timer counter can be cleared by an external reset input or by an internal compare-match signal
generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer
control register select the method of clearing.
When a timer counter overflows from H’FF to H’00, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to “1.”
The timer counters are initialized to H’00 at a reset and in the standby modes.
155
7.2.2 Time Constant Registers A and B (TCORA and TCORB) – H’FFCA and H’FFCB
(TMR0), H’FFD2 and H’FFD3 (TMR1)
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually
compared with the constants written in these registers. When a match is detected, the
corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register
(TCSR).
The timer output signal (TMO0 or TMO1) is controlled by these compare-match signals as
specified by output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR).
TCORA and TCORB are initialized to H’FF at a reset and in the standby modes.
Compare-match is not detected during the T3 state of a write cycle to TCORA or TCORB. See
item (3) in section 7.6, "Application Notes."
7.2.3 Timer Control Register (TCR) – H’FFC8 (TMR0), H’FFD0 (TMR1)
Bit
7
6
5
4
3
2
1
CKS1
0
0
CKS0
0
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each TCR is an 8-bit readable/writable register that selects the clock source and the time at which
the timer counter is cleared, and enables interrupts.
The TCRs are initialized to H’00 at a reset and in the standby modes.
Bit 7 – Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request
compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer
control/status register (TCSR) is set to “1.”
156
Bit 7
CMIEB Description
0
1
Compare-match interrupt request B (CMIB) is disabled.
Compare-match interrupt request B (CMIB) is enabled.
(Initial value)
Bit 6 – Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request
compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer
control/status register (TCSR) is set to “1.”
Bit 6
CMIEA Description
0
1
Compare-match interrupt request A (CMIA) is disabled.
Compare-match interrupt request A (CMIA) is enabled.
(Initial value)
Bit 5 – Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer
overflow interrupt (OVI) when the overflow flag (OVF) in the timer control/status register (TCSR)
is set to “1.”
Bit 5
OVIE
Description
0
1
The timer overflow interrupt request (OVI) is disabled.
The timer overflow interrupt request (OVI) is enabled.
(Initial value)
Bits 4 and 3 – Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer
counter is cleared: by compare-match A or B or by an external reset input.
Bit 4
Bit 3
CCLR1 CCLR0 Description
0
0
1
1
0
1
0
1
Not cleared.
(Initial value)
Cleared on compare-match A.
Cleared on compare-match B.
Cleared on rising edge of external reset input signal.
Bits 2, 1, and 0 – Clock Select (CKS2, CKS1, and CKS0): These bits select the internal or
external clock source for the timer counter. For the external clock source they select whether to
increment the count on the rising or falling edge of the clock input, or on both edges. For the
internal clock sources the count is incremented on the falling edge of the clock input.
157
Bit 2
Bit 1
Bit 0
CKS2
CKS1
CKS0
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No clock source (timer stopped)
(Initial value)
Ø/8 Internal clock source, counted on the falling edge
Ø/64 Internal clock source, counted on the falling edge
Ø/1024 Internal clock source, counted on the falling edge
No clock source (timer stopped)
External clock source, counted on the rising edge
External clock source, counted on the falling edge
External clock source, counted on both the rising
and falling edges
7.2.4 Timer Control/Status Register (TCSR) – H’FFC9 (TMR0), H’FFD1 (TMR1)
Bit
7
6
5
OVF
0
4
—
1
3
2
1
0
CMFB CMFA
OS3
0
OS2
0
OS1
0
OS0
0
Initial value
Read/Write
0
0
R/(W)* R/(W)* R/(W)*
—
R/W
R/W
R/W
R/W
* Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits.
The TCSR is an 8-bit readable and partially writable register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal.
The TCSR is initialized to H’10 at a reset and in the standby modes.
Bit 7 – Compare-Match Flag B (CMFB): This status flag is set to “1” when the timer count
matches the time constant set in TCORB. CMFB must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 7
CMFB
Description
0
To clear CMFB, the CPU must read CMFB after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when TCNT = TCORB.
(Initial value)
1
Bit 6 – Compare-Match Flag A (CMFA): This status flag is set to “1” when the timer count
matches the time constant set in TCORA. CMFA must be cleared by software. It is set by
hardware, however, and cannot be set by software.
158
Bit 6
CMFA
0
Description
To clear CMFA, the CPU must read CMFA after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when TCNT = TCORA.
(Initial value)
1
Bit 5 – Timer Overflow Flag (OVF): This status flag is set to “1” when the timer count overflows
(changes from H’FF to H’00). OVF must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 5
OVF
Description
0
To clear OVF, the CPU must read OVF after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when TCNT changes from H’FF to H’00.
(Initial value)
1
Bit 4 – Reserved: This bit is always read as “1.” It cannot be written.
Bits 3 to 0 – Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of compare-match
events on the timer output signal (TCOR or TCNT). Bits OS3 and OS2 control the effect of
compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on
the output level.
If compare-match A and B occur simultaneously, any conflict is resolved as explained in item (4) in
section 7.6, "Application Notes."
After a reset, the timer output is "0" until the first compare-match event.
When all four output select bits are cleared to “0” the timer output signal is disabled.
Bit 3
Bit 2
OS3
OS2
Description
0
0
1
1
0
1
0
1
No change when compare-match B occurs.
Output changes to “0” when compare-match B occurs.
Output changes to “1” when compare-match B occurs.
Output inverts (toggles) when compare-match B occurs.
(Initial value)
159
Bit 1
Bit 0
OS1
OS0
Description
0
0
1
1
0
1
0
1
No change when compare-match A occurs.
Output changes to “0” when compare-match A occurs.
Output changes to “1” when compare-match A occurs.
Output inverts (toggles) when compare-match A occurs.
(Initial value)
7.3 Operation
7.3.1 TCNT Incrementation Timing
The timer counter increments on a pulse generated once for each period of the clock source selected
by bits CKS2 to CKS0 of the TCR.
Internal Clock: Internal clock sources are created from the system clock by a prescaler. The
counter increments on an internal TCNT clock pulse generated from the falling edge of the
prescaler output, as shown in figure 7-2. Bits CKS2 to CKS0 of the TCR can select one of the
three internal clocks (Ø/8, Ø/64, or Ø/1024).
Ø
Prescaler
output
TCNT clock
pulse
TCNT
N–1
N
N+1
Figure 7-2. Count Timing for Internal Clock Input
External Clock: If external clock input (TMCI) is selected, the timer counter can increment on the
rising edge, the falling edge, or both edges of the external clock signal. Figure 7-3 shows
incrementation on both edges of the external clock signal.
The external clock pulse width must be at least 1.5 system clock periods for incrementation on a
single edge, and at least 2.5 system clock periods for incrementation on both edges. See figure 7.4.
The counter will not increment correctly if the pulse width is shorter than these values.
160
Ø
External clock
source
TCNT clock
pulse
TCNT
N – 1
N
N + 1
Figure 7-3. Count Timing for External Clock Input
Ø
TMCI
Minimum TMCI Pulse Width
(Single-Edge Incrementation)
Ø
TMCI
Minimum TMCI Pulse Width
(Double-Edge Incrementation)
Figure 7-4. Minimum External Clock Pulse Widths (Example)
7.3.2 Compare Match Timing
(1) Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags
are set to “1” by an internal compare-match signal generated when the timer count matches the time
constant in TCNT or TCOR. The compare-match signal is generated at the last state in which the
match is true, just before the timer counter increments to a new value.
161
Accordingly, when the timer count matches one of the time constants, the compare-match signal is
not generated until the next period of the clock source. Figure 7-5 shows the timing of the setting
of the compare-match flags.
Ø
TCNT
TCOR
N
N
N + 1
Internal
compare-match
signal
CMF
Figure 7-5. Setting of Compare-Match Flags
(2) Timing of Compare-Match Flag (CMFA or CMFB) Clearing: The compare-match flag
CMFA or CMFB is cleared when the CPU writes a “0” in this bit.
Write cycle: CPU writes "0" in CMFA or CMFB
T 1
T 2
T 3
Ø
CMFA
or CMFB
Figure 7-6. Clearing of Compare-Match Flags
(3) Output Timing: When a compare-match event occurs, the timer output (TMO0 or TMO1)
changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits,
the output can remain the same, change to “0,” change to “1,” or toggle. If compare-match A and
B occur simultaneously, the higher priority compare-match determines the output level. See item
(4) in section 7.6, “Application Notes” for details.
162
Figure 7-7 shows the timing when the output is set to toggle on compare-match A.
Ø
Internal
compare-match
A signal
Timer output
(TMO)
Figure 7-7. Timing of Timer Output
(4) Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR,
the timer counter can be cleared when compare-match A or B occurs. Figure 7-8 shows the timing
of this operation.
Ø
Internal
compare-match
signal
TCNT
N
H’00
Figure 7-8. Timing of Compare-Match Clear
7.3.3 External Reset of TCNT
When the CCLR1 and CCLR0 bits in the TCR are both set to “1,” the timer counter is cleared on
the rising edge of an external reset input. Figure 7-9 shows the timing of this operation. The timer
reset pulse width must be at least 1.5 system clock periods.
163
Ø
External reset
input (TMRI)
Internal clear
pulse
N – 1
N
H’00
TCNT
Figure 7-9. Timing of External Reset
7.3.4 Setting of TCSR Overflow Flag
(1) Setting of TCSR Overflow Flag (OVF): The overflow flag (OVF) is set to “1” when the
timer count overflows (changes from H’FF to H’00). Figure 7-10 shows the timing of this
operation.
Ø
TCNT
H’FF
H’00
Internal overflow
signal
OVF
Figure 7-10. Setting of Overflow Flag (OVF)
(2) Timing of TCSR Overflow Flag (OVF) Clearing: The overflow flag (OVF) is cleared when
the CPU writes a “0” in this bit.
164
When cycle: CPU writes "0" in OVF
T1
T2
T3
Ø
OVF
Figure 7-11. Clearing of Overflow Flag
7.4 Interrupts
Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B
(CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding
enable bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller
for each interrupt. Table 7-3 lists information about these interrupts.
Table 7-3. 8-Bit Timer Interrupts
Interrupt
CMIA
CMIB
OVI
Description
Priority
Requested when CMFA and CMIEA are set
Requested when CMFB and CMIEB are set
Requested when OVF and OVIE are set
High
Low
7.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor.
The control bits are set as follows:
(1) In the TCR, CCLR1 is cleared to “0” and CCLR0 is set to “1” so that the timer counter is
cleared when its value matches the constant in TCORA.
(2) In the TCSR, bits OS3 to OS0 are set to “0110,” causing the output to change to “1” on
compare-match A and to “0” on compare-match B.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a
pulse width determined by TCORB. No software intervention is required.
165
TCNT
H’FF
Clear counter
TCORA
TCORB
H’00
TMO pin
Figure 7-12. Example of Pulse Output
7.6 Application Notes
Application programmers should note that the following types of contention can occur in the 8-bit
timer.
(1) Contention between TCNT Write and Clear: If an internal counter clear signal is generated
during the T3 state of a write cycle to the timer counter, the clear signal takes priority and the write
is not performed.
Figure 7-13 shows this type of contention.
Write cycle: CPU writes to TCNT
T1
T2
T3
Ø
Internal Address
bus
TCNT address
Internal write
signal
Counter clear
signal
TCNT
N
H’00
Figure 7-13. TCNT Write-Clear Contention
166
(2) Contention between TCNT Write and Increment: If a timer counter increment pulse is
generated during the T3 state of a write cycle to the timer counter, the write takes priority and the
timer counter is not incremented.
Figure 7-14 shows this type of contention.
Write cycle: CPU writes to TCNT
T1
T2
T3
Ø
Internal Address
bus
TCNT address
Internal write
signal
TCNT clock
pulse
TCNT
N
M
Write data
Figure 7-14. TCNT Write-Increment Contention
(3) Contention between TCOR Write and Compare-Match: If a compare-match occurs during
the T3 state of a write cycle to TCORA or TCORB, the write takes precedence and the compare-
match signal is inhibited.
Figure 7-15 shows this type of contention.
167
Write cycle: CPU writes to TCORA or TCORB
T1
T2
T3
Ø
Internal address
bus
TCOR address
Internal write
signal
N + 1
TCNT
N
TCORAor
TCORB
N
M
TCOR write data
Compare-match
A or B signal
Inhibited
Figure 7-15. Contention between TCOR Write and Compare-Match
(4) Contention between Compare-Match A and Compare-Match B: If identical time constants
are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any
conflict between the output selections for compare-match A and B is resolved by following the
priority order in Table 7-4.
Table 7-4. Priority of Timer Output
Output selection
Toggle
Priority
High
“1” Output
“0” Output
No change
Low
(5) Incrementation Caused by Changing of Internal Clock Source: When an internal clock
source is changed, the changeover may cause the timer counter to increment. This depends on the
time at which the clock select bits (CKS2 to CKS0) are rewritten, as shown in Table 7-5.
168
The pulse that increments the timer counter is generated at the falling edge of the internal clock
source signal. If clock sources are changed when the old source is High and the new source is Low,
as in case No. 3 in Table 7-5, the changeover generates a falling edge that triggers the TCNT clock
pulse and increments the timer counter.
Switching between an internal and external clock source can also cause the timer counter to
increment. This type of switching should be avoided at external clock edges.
Table 7-5. Effect of Changing Internal Clock Sources
No.
Description
Timing chart
1
Low → Low* :
Old clock
source
CKS1 and CKS0 are
rewritten while both
clock sources are Low.
1
New clock
source
TCNT clock
pulse
N + 1
TCNT
N
CKS rewrite
2
Old clock
source
Low → High* :
CKS1 and CKS0 are
rewritten while old
2
New clock
source
clock source is Low and
new clock source is High.
TCNT clock
pulse
TCNT
N
N + 1
N + 2
CKS rewrite
1
* Including a transition from Low to the stopped state (CKS1 = 0, CKS0 = 0), or a transition from
the stopped state to Low.
2
* Including a transition from the stopped state to High.
169
Table 7-5. Effect of Changing Internal Clock Sources (cont.)
No.
Description
Timing chart
1
High → Low* :
Old clock
source
CKS1 and CKS0 are
rewritten while old
3
New clock
source
clock source is High and
new clock source is Low.
2
*
3
*
TCNT clock
pulse
TCNT
N
N + 1
N + 2
CKS rewrite
High → High:
Old clock
source
CKS1 and CKS0 are
rewritten while both
clock sources are High.
4
New clock
source
TCNT clock
pulse
TCNT
N
N + 1
N + 2
CKS rewrite
1
* Including a transition from High to the stopped state.
2
* The switching of clock sources is regarded as a falling edge that increments the TCNT.
170
Section 8. PWM Timers
8.1 Overview
The H8/330 has an on-chip pulse-width modulation (PWM) timer module with two independent
channels (PWM0 and PWM1). Both channels are functionally identical. Each PWM channel
generates a rectangular output pulse with a duty factor of 0 to 100%. The duty factor is specified in
an 8-bit duty register (DTR).
8.1.1 Features
The PWM timer module has the following features:
• Selection of eight clock sources
• Duty factors from 0 to 100% with 1/250 resolution
• Output with positive or negative logic and software enable/disable control
8.1.2 Block Diagram
Figure 8-1 shows a block diagram of one PWM timer channel.
DTR
Compare-match
Internal
data bus
Output
control
Pulse
Comparator
TCNT
TCR
Ø/2
Ø/8
Ø/32
Ø/128
Ø/256
Clock
Clock
select
Ø/1024
Ø/2048
Ø/4096
Internal clock sources
TCR:
DTR:
Timer Control Register (8 bits)
Duty Register (8 bits)
TCNT: Timer Counter (8 bits)
Figure 8-1. Block Diagram of PWM Timer
171
8.1.3 Input and Output Pins
Table 8-1 lists the output pins of the PWM timer module. There are no input pins.
Table 8-1. Output Pins of PWM Timer Module
Name
Abbreviation I/O
Function
PWM0 output
PWM1 output
PW0
PW1
Output
Output
Pulse output from PWM timer channel 0.
Pulse output from PWM timer channel 1.
8.1.4 Register Configuration
The PWM timer module has three registers for each channel as listed in Table 8-2.
Table 8-2. PWM Timer Registers
Initial
value
H’38
H’FF
H’00
Address
PWM0
Name
Abbreviation R/W
PWM1
Timer control register
Duty register
Timer counter
TCR
R/W
H’FFA0 H’FFA4
H’FFA1 H’FFA5
H’FFA2 H’FFA6
DTR
TCNT
R/W
R/(W)*
* The timer counters are read/write registers, but the write function is for test purposes only.
Application programs should never write to these registers.
8.2 Register Descriptions
8.2.1 Timer Counter (TCNT) – H’FFA2 (PWM0), H’FFA6 (PWM1)
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The PWM timer counters (TCNT) are 8-bit up-counters. When the output enable bit (OE) in the
timer control register (TCR) is set to “1,” the timer counter starts counting pulses of an internal
clock source selected by clock select bits 2 to 0 (CKS2 to CKS0). After counting from H’00 to
H’F9, the timer counter repeats from H’00.
172
The PWM timer counters can be read and written, but the write function is for test purposes only.
Application software should never write to a PWM timer counter, because this may have
unpredictable effects.
The PWM timer counters are initialized to H’00 at a reset and in the standby modes, and when the
OE bit is cleared to “0.”
8.2.2 Duty Register (DTR) – H’FFA1 (PWM0), H’FFA5 (PWM1)
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The duty registers (DTR) are 8-bit readable/writable registers that specify the duty factor of the
output pulse. Any duty factor from 0 to 100% can be selected, with a resolution of 1/250. Writing
0 (H’00) in a DTR gives a 0% duty factor; writing 125 (H’7D) gives a 50% duty factor; writing 250
(H’FA) gives a 100% duty factor.
The timer count is continually compared with the DTR contents. If the DTR value is not 0, when
the count increments from H’00 to H’01 the PWM output signal is set to “1.” When the count
increments past the DTR value, the PWM output returns to “0.” If the DTR value is 0 (duty factor
0%), the PWM output remains constant at “0.”
The DTRs are double-buffered. A new value written in a DTR while the timer counter is running
does not become valid until after the count changes from H’F9 to H’00. When the timer counter is
stopped (while the OE bit is “0”), new values become valid as soon as written. When a DTR is
read, the value read is the currently valid value.
The DTRs are initialized to H’FF at a reset and in the standby modes.
8.2.3 Timer Control Register (TCR) – H’FFA0 (PWM0), H’FFA4 (PWM1)
Bit
7
OE
0
6
OS
0
5
—
1
4
—
1
3
—
1
2
CKS2
0
1
CKS1
0
0
CKS0
0
Initial value
Read/Write
R/W
R/W
—
—
—
R/W
R/W
R/W
173
The TCRs are 8-bit readable/writable registers that select the clock source and control the PWM
outputs.
The TCRs are initialized to H’38 at a reset and in the standby modes.
Bit 7 – Output Enable (OE): This bit enables the timer counter and the PWM output.
Bit 7
OE
0
Description
PWM output is disabled. TCNT is cleared to H’00 and stopped.
PWM output is enabled. TCNT runs.
(Initial value)
1
Bit 6 – Output Select (OS): This bit selects positive or negative logic for the PWM output.
Bit 6
OS
0
Description
Positive logic; positive-going PWM pulse, “1” = High
Negative logic; negative-going PWM pulse, “1” = Low
(Initial value)
1
Bits 5 to 3 – Reserved: These bits cannot be modified and are always read as “1.”
Bits 2, 1, and 0 – Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight internal
clock sources obtained by dividing the system clock (Ø).
Bit 2
Bit 1
Bit 0
CKS2
CKS1
CKS0
Description
Ø/2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(Initial value)
Ø/8
Ø/32
Ø/128
Ø/256
Ø/1024
Ø/2048
Ø/4096
From the clock source frequency, the resolution, period, and frequency of the PWM output can be
calculated as follows.
174
Resolution =
PWM period
1/clock source frequency
=
=
resolution × 250
PWM frequency
1/PWM period
If the system clock frequency is 10MHz, then the resolution, period, and frequency of the PWM
output for each clock source are given in Table 8-3.
Table 8-3. PWM Timer Parameters for 10MHz System Clock
Internal clock frequency
Resolution
200ns
PWM period
50µs
PWM frequency
20kHz
Ø/2
Ø/8
800ns
200µs
5kHz
Ø/32
3.2µs
800µs
1.25kHz
312.5Hz
156.3Hz
39.1Hz
Ø/128
Ø/256
Ø/1024
Ø/2048
Ø/4096
12.8µs
25.6µs
102.4µs
204.8µs
409.6µs
3.2ms
6.4ms
25.6ms
51.2ms
102.4ms
19.5Hz
9.8Hz
8.3 Operation
8.3.1 Timer Incrementation
The PWM clock source is created from the system clock (Ø) by a prescaler. The timer counter
increments on a TCNT clock pulse generated from the falling edge of the prescaler output as shown
in Figure 8-2.
Ø
Prescaler
output
TCNT clock
pulse
TCNT
N–1
N
N+1
Figure 8-2. TCNT Increment Timing
175
8.3.2 PWM Operation
Figure 8-3 is a timing chart of the PWM operation.
176
(1) Positive Logic (OS = “0”)
➀ When (OE = “0”) – (a) in Figure 8-3: The timer count is held at H’00 and PWM output is
inhibited. (Pin 46 (for PW0) or pin 47 (for PW1)is used for port 4 input/output, and its state
depends on the corresponding port 4 data register and data direction register.) Any value (such as
N in Figure 8-3) written in the DTR becomes valid immediately.
② When (OE = “1”)
i) The timer counter begins incrementing. The PWM output goes High when TCNT changes
from H’00 to H’01, unless DTR = H’00. [(b) in Figure 8-3]
ii) When the count passes the DTR value, the PWM output goes Low. [(c) in Figure 8-3]
iii) If the DTR value is changed (by writing the data “M” in Figure 8-3), the new value
becomes valid after the timer count changes from H’F9 to H’00. [(d) in Figure 8-3]
(2) Negative Logic (OS = “1”) – (e) in Figure 8-3: The operation is the same except that High
and Low are reversed in the PWM output . [(e) in Figure 8-3]
8.4 Application Notes
Some notes on the use of the PWM timer module are given below.
(1) Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS)
should be made before the output enable bit (OE) is set to “1.”
(2) If the DTR value is H’00, the duty factor is 0% and PWM output remains constant at “0.” If
the DTR value is H’FA to H’FF, the duty factor is 100% and PWM output remains constant at
“1.”
(For positive logic, “0” is Low and “1” is High. For negative logic, “0” is High and “1” is
Low.)
(3) When the DTR is read, the currently valid value is obtained. Due to the double buffering, this
may not be the value most recently written.
(4) Software should never write to a PWM timer counter. The write function is for test purposes
only and may have unintended effects in normal operation.
177
Section 9. Serial Communication Interface
9.1 Overview
The H8/330 chip includes a single-channel serial communication interface (SCI) for transferring
serial data to and from other chips. Either the synchronous or asynchronous communication mode
can be selected. Communication control functions are provided by internal registers.
9.1.1 Features
The features of the on-chip serial communication interface are:
• Separate pins for asynchronous and synchronous modes
– Asynchronous mode
The SCI can communicate with a UART (Universal Asynchronous Receiver/Transmitter),
ACIA (Asynchronous Communication Interface Adapter), or other chip that employs standard
asynchronous serial communication. Eight data formats are available.
– Data length: 7 or 8 bits
– Stop bit length: 1 or 2 bits
– Parity: Even, odd, or none
– Error detection: Parity, overrun, and framing errors
– Synchronous mode
The SCI can communicate with chips able to perform clocked serial data transfer.
– Data length: 8 bits
– Error detection: Overrun errors
• Full duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. Both the transmit and receive sections use double buffering, so continuous data
transfer is possible in either direction.
• Built-in baud rate generator
Any specified baud rate can be generated.
• Internal or external clock source
The baud rate generator can operate on an internal clock source, or an external clock signal input
at the ASCK or CSCK pin.
• Three interrupts
Transmit-end, receive-end, and receive-error interrupts are requested independently.
179
9.1.2 Block Diagram
Internal
data bus
Module data bus
RDR
RSR
TDR
TSR
SSR
BRR
SCR
SMR
ARxD/
CRxD
Internal
clock
Ø
Communi-
cation
control
Ø/4
Ø/16
Ø/64
Baud rate
generator
ATxD/
CTxD
Parity
generate
Clock
Parity check
External clock source
ASCK/
CSCK
TXI
RXI
RSR: Receive Shift Register (8 bits)
RDR: Receive Data Register (8 bits)
ERI
TSR:
TDR:
Transmit Shift Register (8 bits)
Transmit Data Register (8 bits)
Interrupt signals
SMR: Serial Mode Register (8 bits)
SCR: Serial Control Register (8 bits)
SSR: Serial Status Register (8 bits)
BRR: Bit Rate Register (8 bits)
Figure 9-1. Block Diagram of Serial Communication Interface
9.1.3 Input and Output Pins
Table 9-1 lists the input and output pins used by the SCI module.
Table 9-1. SCI Input/Output Pins
Name
Abbreviation
ASCK
I/O
Function
Asynchronous serial clock
Asynchronous receive data
Asynchronous transmit data
Synchronous serial clock
Synchronous receive data
Synchronous transmit data
Input/output
Input
Serial clock input and output.
Receive data input.
ARxD
ATxD
Output
Input/output
Input
Transmit data output.
Serial clock input and output.
Receive data input.
CSCK
CRxD
CTxD
Output
Transmit data output.
180
9.1.4 Register Configuration
Table 9-2 lists the SCI registers.
Table 9-2. SCI Registers
Name
Abbreviation R/W
Initial value
—
Address
—
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
RSR
RDR
TSR
TDR
SMR
SCR
SSR
BRR
—
R
H’00
—
H’FFDD
—
—
R/W
R/W
R/W
R/(W)*
R/W
H’FF
H’04
H’0C
H’87
H’FF
H’FFDB
H’FFD8
H’FFDA
H’FFDC
H’FFD9
Notes:
* Software can write a “0” to clear the status flag bits, but cannot write a “1.”
9.2 Register Descriptions
9.2.1 Receive Shift Register (RSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
The RSR receives incoming data bits. When one data character (1 byte) has been received, it is
transferred to the receive data register (RDR).
The CPU cannot read or write the RSR directly.
181
9.2.2 Receive Data Register (RDR) – H’FFDD
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
The RDR stores received data. As each character is received, it is transferred from the RSR to the
RDR, enabling the RSR to receive the next character. This double-buffering allows the SCI to
receive data continuously.
The CPU can read but not write the RDR. The RDR is initialized to H’00 at a reset and in the
standby modes.
9.2.3 Transmit Shift Register (TSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
The TSR holds the character currently being transmitted. When transmission of this character is
completed, the next character is moved from the transmit data register (TDR) to the TSR and
transmission of that character begins. If the CPU has not written the next character in the TDR, no
data are transmitted.
The CPU cannot read or write the TSR directly.
9.2.4 Transmit Data Register (TDR) – H’FFDB
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The TDR is an 8-bit readable/writable register that holds the next character to be transmitted.
When the TSR becomes empty, the character written in the TDR is transferred to the TSR.
Continuous data transmission is possible by writing the next byte in the TDR while the current byte
is being transmitted from the TSR.
182
The TDR is initialized to H’FF at a reset and in the standby modes.
9.2.5 Serial Mode Register (SMR) – H’FFD8
Bit
7
C/A
0
6
5
PE
0
4
O/E
0
3
STOP
0
2
—
1
1
CKS1
0
0
CKS0
0
CHR
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
The SMR is an 8-bit readable/writable register that controls the communication format and selects
the clock rate for the internal clock source. It is initialized to H’04 at a reset and in the standby
modes.
Bit 7 – Communication Mode (C/A): This bit selects the asynchronous or synchronous
communication mode.
Bit 7
C/A
0
Description
Asynchronous communication.
Clock-synchronized communication.
(Initial value)
1
Bit 6 – Character Length (CHR): This bit selects the character length in asynchronous mode. It
is ignored in synchronous mode.
Bit 6
CHR Description
0
1
8 Bits per character.
7 Bits per character.
(Initial value)
Bit 5 – Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It
is ignored in synchronous mode.
Bit 5
PE
Description
0
Transmit: No parity bit is added.
Receive: Parity is not checked.
Transmit: A parity bit is added.
Receive: Parity is checked.
(Initial value)
1
183
Bit 4 – Parity Mode (O/E ): In asynchronous mode, when parity is enabled (PE = “1”), this bit
selects even or odd parity.
Even parity means that a parity bit is added to the data bits for each character to make the total
number of 1’s even. Odd parity means that the total number of 1’s is made odd.
This bit is ignored when PE = “0,” and in the synchronous mode.
Bit 4
O/E Description
0
1
Even parity.
Odd parity.
(Initial value)
Bit 3 – Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in the
synchronous mode.
Bit 3
STOP
Description
1 Stop bit.
2 Stop bits.
0
1
(Initial value)
Bit 2 – Reserved: This bit cannot be modified and is always read as “1.”
Bits 1 and 0 – Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source when the baud rate generator is clocked from within the H8/330 chip.
Bit 1
Bit 0
CKS1
CKS0
Description
Ø clock
0
0
1
1
0
1
0
1
(Initial value)
Ø/4 clock
Ø/16 clock
Ø/64 clock
For further information about SMR settings, see Tables 9-5 to 9-7 in Section 9.3, "Operation."
184
9.2.6 Serial Control Register (SCR) – H’FFDA
Bit
7
TIE
0
6
RIE
0
5
TE
0
4
RE
0
3
—
1
2
—
1
1
CKE1
0
0
CKE0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
—
—
R/W
R/W
The SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is
initialized to H’0C at a reset and in the standby modes.
Bit 7 – Transmit Interrupt Enable (TIE): This bit enables or disables the transmit-end interrupt
(TxI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR)
is set to “1.”
Bit 7
TIE
0
Description
The transmit-end interrupt request (TxI) is disabled.
The transmit-end interrupt request (TxI) is enabled.
(Initial value)
1
Bit 6 – Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt
(RxI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is
set to “1.”
Bit 6
RIE
Description
0
1
The receive-end interrupt (RxI) request is disabled.
The receive-end interrupt (RxI) request is enabled.
(Initial value)
Bit 5 – Transmit Enable (TE): This bit enables or disables the transmit function. When the
transmit function is enabled, the ATxD or CTxD pin is automatically used for output. When the
transmit function is disabled, the ATxD or CTxD pin can be used as a general-purpose I/O port.
Bit 5
TE Description
0
The transmit function is disabled.
(Initial value)
The ATxD and CTxD pins can be used for general-purpose I/O.
The transmit function is enabled. When C/A = 0, the ATxD pin is used
for output. When C/A = 1, the CTxD pin is used for output.
1
185
Bit 4 – Receive Enable (RE): This bit enables or disables the receive function. When the receive
function is enabled, the ARxD or CRxD pin is automatically used for input. When the receive
function is disabled, the ARxD or CRxD pin is available as a general-purpose I/O port.
Bit 4
RE Description
0
The receive function is disabled. The ARxD and CRxD pins can be
used for general-purpose I/O.
(Initial value)
1
The receive function is enabled. When C/A = 0, the ARxD pin is used
for input. When C/A = 1, the CRxD pin is used for input.
Bits 3 and 2 – Reserved: These bits cannot be modified and are always read as “1.”
Bit 1 – Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud
rate generator. When the external clock source is selected, the ASCK or CSCK pin is automatically
used for input of the external clock signal.
Bit 1
CKE1
Description
0
Internal clock source. (When C/A = 1, the CSCK pin is used
for output.)
(Initial value)
1
External clock source. (When C/A = 1, the CSCK pin is used
for input. When C/A = 0, the ASCK pin is used for input.)
Bit 0 – Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode,
this bit enables or disables serial clock output at the ASCK pin.
This bit is ignored when the external clock is selected, or when the synchronous mode is selected.
Bit 0
CKE0
Description
0
The ASCK pin is not used by the SCI (and is available as
a general-purpose I/O port).
(Initial value)
1
The ASCK pin is used for serial clock output.
For further information on clock source selection, see Table 9-6 in Section 9.3, “Operation.”
186
9.2.7 Serial Status Register (SSR) – H’FFDC
Bit
7
6
5
4
FER
0
3
PER
0
2
—
1
1
—
1
0
—
1
TDRE RDRF ORER
Initial value
Read/Write
1
0
0
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
—
—
—
* Software can write a “0” to clear the flags, but cannot write a “1” in these bits.
The SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H’87 at a
reset and in the standby modes.
Bit 7 – Transmit Data Register Empty (TDRE): This bit indicates when the TDR contents have
been transferred to the TSR and the next character can safely be written in the TDR.
Bit 7
TDRE
Description
0
To clear TDRE, the CPU must read TDRE after it has been set to "1," then write a “0”
in this bit.
1
This bit is set to 1 at the following times:
(Initial value)
(1) When TDR contents are transferred to the TSR.
(2) When the TE bit in the SCR is cleared to "0."
Bit 6 – Receive Data Register Full (RDRF): This bit indicates when one character has been
received and transferred to the RDR.
Bit 6
RDRF
Description
0
To clear RDRF, the CPU must read RDRF after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when one character is received without error and
transferred from the RSR to the RDR.
(Initial value)
1
187
Bit 5 – Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5
ORER
Description
0
To clear ORER, the CPU must read ORER after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 if reception of the next character ends while
the receive data register is still full (RDRF = “1”).
(Initial value)
1
Bit 4 – Framing Error (FER): This bit indicates a framing error during data reception in the
asynchronous mode. It has no meaning in the synchronous mode.
Bit 4
FER
Description
0
To clear FER, the CPU must read FER after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 if a framing error occurs (stop bit = “0”).
(Initial value)
1
Bit 3 – Parity Error (PER): This bit indicates a parity error during data reception in the
asynchronous mode, when a communication format with parity bits is used.
This bit has no meaning in the synchronous mode, or when a communication format without parity
bits is used.
Bit 3
PER
Description
0
To clear PER, the CPU must read PER after
it has been set to "1," then write a “0” in this bit.
This bit is set to 1 when a parity error occurs (the parity of the
received data does not match the parity selected by the O/E bit
in the SMR).
(Initial value)
1
Bits 2 to 0 – Reserved: These bits cannot be modified and are always read as “1.”
188
9.2.8 Bit Rate Register (BRR) – H’FFD9
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines
the baud rate output by the baud rate generator.
The BRR is initialized to H’FF (the slowest rate) at a reset and in the standby modes.
Tables 9-3 and 9-4 show examples of BRR (N) and CKS (n) settings for commonly used bit rates.
Table 9-3. Examples of BRR Settings in Asynchronous Mode (1)
XTAL Frequency (MHz)
2
2.4576
Error
(%)
4
4.194304
Error
N (%)
Bit
Error
(%)
Error
(%)
rate
110
n
N
n
1
0
0
0
0
0
0
0
0
—
0
N
n
N
n
1
70 +0.03
207 +0.16
103 +0.16
51 +0.16
25 +0.16
12 +0.16
86 +0.31
255 0
1
141
103
207
103
51
+0.03
+0.16
+0.16
+0.16
+0.16
+0.16
+0.16
—
1
148 –0.04
108 +0.21
217 +0.21
108 +0.21
150
0
1
1
300
0
127 0
0
0
600
0
63
31
15
7
0
0
0
1200
2400
4800
9600
0
0
0
0
54
26
13
—
—
—
—
–0.70
+1.14
–2.48
—
0
0
0
25
0
—
—
—
—
—
—
—
—
—
—
—
—
0
0
12
0
3
0
—
—
0
—
—
—
—
—
19200 —
31250 —
38400 —
1
0
—
—
—
—
0
—
0
1
0
—
—
—
—
—
189
Table 9-3. Examples of BRR Settings in Asynchronous Mode (2)
XTAL Frequency (MHz)
4.9152
Error
6
7.3728
8
Bit
Error
(%)
Error
Error
(%)
rate
110
n
1
1
0
0
0
0
0
0
N
(%)
n
N
n
2
1
1
0
0
0
0
0
0
—
0
N
(%)
n
2
N
174 –0.26
127 0
255 0
127 0
2
52 +0.50
155 +0.16
77 +0.16
155 +0.16
77 +0.16
38 +0.16
19 –2.34
64
191
95
191
95
47
23
11
5
+0.70
70
+0.03
150
1
0
0
0
0
0
0
0
0
—
0
1
207 +0.16
103 +0.16
207 +0.16
103 +0.16
300
1
1
600
0
0
1200
2400
4800
9600
63
31
15
7
0
0
0
0
0
0
51
25
12
—
3
+0.16
+0.16
+0.16
—
0
0
0
0
—
—
0
—
—
2
—
—
0
0
19200 0
31250 —
38400 0
3
0
—
0
—
1
—
0
—
2
0
—
—
—
—
—
—
Table 9-3. Examples of BRR Settings in Asynchronous Mode (3)
XTAL Frequency (MHz)
9.8304
Error
(%)
10
12
12.288
N
Bit
Error
(%)
Error
(%)
–0.44
0
Error
(%)
rate
110
n
2
1
1
0
0
0
0
0
N
n
2
2
1
1
0
0
0
0
0
0
0
N
n
2
N
n
2
2
1
1
0
0
0
0
0
0
—
86 +0.31
255 0
88 –0.25
64 +0.16
129 +0.16
64 +0.16
129 +0.16
64 +0.16
32 –1.36
15 +1.73
106
77
155
77
155
77
38
19
—
5
108 +0.08
150
2
79
159
79
159
79
39
19
4
0
300
127 0
1
0
0
600
255 0
1
0
0
1200
2400
4800
9600
127 0
0
+0.16
+0.16
+0.16
–2.34
—
0
63
31
15
7
0
0
0
0
0
0
0
0
0
19200 0
31250 0
38400 0
0
7
4
3
+1.73
0
—
0
0
4
–1.70
0
0
5
+2.40
—
3
+1.73
—
—
—
—
190
Table 9-3. Examples of BRR Settings in Asynchronous Mode (4)
XTAL Frequency (MHz)
14.7456
Error
(%)
130 –0.07
95
191 0
95
191 0
16
19.6608
20
Bit
Error
(%)
Error
Error
(%)
rate
110
n
2
2
1
1
0
0
0
0
N
n
2
2
1
1
0
0
0
0
0
0
—
N
n
2
2
1
1
0
0
0
0
0
0
0
N
(%)
n
3
2
2
1
1
0
0
0
0
0
0
N
141 +0.03
103 +0.16
207 +0.16
103 +0.16
207 +0.16
103 +0.16
51 +0.16
25 +0.16
12 +0.16
174
127
255
127
255
127
63
–0.26
43
+0.88
150
0
0
129 +0.16
64 +0.16
129 +0.16
64 +0.16
129 +0.16
300
0
600
0
0
1200
2400
4800
9600
0
95
47
23
11
—
5
0
0
0
0
64
32
15
9
+0.16
–1.36
+1.73
0
0
31
0
19200 0
31250 —
38400 0
0
15
0
—
0
7
0
9
–1.70
0
—
—
7
7
+1.73
Note: If possible, the error should be within 1%.
6
2n
B = OSC × 10 /[64 × 2
× (N + 1)]
N: BRR value (0 ≤ N ≤ 255)
OSC: Crystal oscillator frequency in MHz
B: Bit rate (bits/second)
n: Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n
0
1
2
3
CKS1
CKS0
Clock
Ø
0
0
1
1
0
1
0
1
Ø/4
Ø/16
Ø/64
191
Table 9-4. Examples of BRR Settings in Synchronous Mode
XTAL Frequency (MHz)
Bit
2
4
n
—
2
1
1
0
0
0
0
0
0
0
0
8
n
—
2
2
1
1
0
0
0
0
0
0
0
0
10
n
16
n
—
3
20
n
rate
100
250
500
1k
n
—
1
N
N
N
N
N
N
—
249
124
249
99
49
24
9
—
124
249
124
199
99
49
19
9
—
249
124
249
99
199
99
39
19
9
—
—
—
—
1
—
—
—
—
124
249
124
49
24
—
4
—
124
249
124
199
99
199
79
39
19
7
—
—
—
—
1
—
—
—
—
249
124
249
99
49
24
9
1
2
0
2
2.5k
5k
0
1
0
0
1
1
10k
25k
50k
100k
250k
500k
1M
0
0
0
0
0
0
0
0
0
4
0
0
0
—
0
—
0*
4
—
0
0
0
1
3
0
0
0*
1
—
—
—
—
0
3
0
4
0*
0
1
—
0
—
0*
2.5M
Notes:
Blank: No setting is available.
—: A setting is available, but the bit rate is inaccurate.
*: Continuous transfer is not possible.
6
2n
B = OSC × 10 /[8 × 2
× (N + 1)]
N: BRR value (0 ≤ N ≤ 255)
OSC: Crystal oscillator frequency in MHz
B: Bit rate (bits per second)
n: Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n
0
1
2
3
CKS1
CKS0
Clock
Ø
0
0
1
1
0
1
0
1
Ø/4
Ø/16
Ø/64
192
9.3 Operation
9.3.1 Overview
The SCI supports serial data transfer in both asynchronous and synchronous modes.
The communication format depends on settings in the SMR as indicated in Table 9-5. The clock
source and usage of the ASCK and CSCK pins depend on settings in the SMR and SCR as
indicated in Table 9-6.
Table 9-5. Communication Formats Used by SCI
SMR
Stop bit
C/A
CHR PE
STOP Mode
Format
Parity
length
0
0
0
0
1
0
None
1
8-Bit data
2
1
Yes
None
Yes
—
1
1
Asynchronous
2
1
0
0
1
1
7-Bit data
8-Bit data
2
1
0
1
1
2
1
—
—
—
Synchronous
—
Table 9-6. SCI Clock Source Selection
SMR
C/A
SCR
CKE1
0
Clock
CKE0
source ASCK pin
CSCK pin
0
0
1
Internal Input/output port*
Serial clock output
Input/output port*
Input/output port*
(Async
mode)
at bit rate
1
0
1
0
1
0
1
0
1
External Serial clock input
at 16 × bit rate
Input/output port*
Serial clock output
Serial clock input
1
Internal Input/output port*
(Sync
mode)
External Input/output port*
* Not used by the SCI.
193
Transmitting and receiving operations in the two modes are described next.
9.3.2 Asynchronous Mode
In asynchronous mode, each character is individually synchronized by framing it with a start bit
and stop bit.
Full duplex data transfer is possible because the SCI has independent transmit and receive sections.
Double buffering in both sections enables the SCI to be programmed for continuous data transfer.
Figure 9-2 shows the general format of one character sent or received in the asynchronous mode.
The communication channel is normally held in the mark state (High). Character transmission or
reception starts with a transition to the space state (Low).
The first bit transmitted or received is the start bit (Low). It is followed by the data bits, in which
the least significant bit (LSB) comes first. The data bits are followed by the parity bit, if present,
then the stop bit or bits (High) confirming the end of the frame.
In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the
center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate).
Idle state
Start bit
1 bit
D0
D1
Dn
Parity bit
0 or 1 bit
Stop bit
1 or 2 bits
7 or 8 bits
One character
Figure 9-2. Data Format in Asynchronous Mode
(1) Data Format: Table 9-7 lists the data formats that can be sent and received in asynchronous
mode. Eight formats can be selected by bits in the SMR.
194
Table 9-7. Data Formats in Asynchronous Mode
SMR bits
CHR PE
STOP
Data format
START
START
START
START
START
START
START
START
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8-Bit data
8-Bit data
8-Bit data
8-Bit data
7-Bit data
7-Bit data
7-Bit data
7-Bit data
STOP
STOP STOP
P
P
STOP
STOP STOP
STOP
STOP STOP
P
P
STOP
STOP STOP
Note
START: Start bit
STOP: Stop bit
P: Parity bit
(2) Clock: In the asynchronous mode it is possible to select either an internal clock created by the
on-chip baud rate generator, or an external clock input at the ASCK pin. Refer to Table 9-6.
If an external clock is input at the ASCK pin, its frequency should be 16 times the desired baud
rate.
If the internal clock provided by the on-chip baud rate generator is selected and the ASCK pin is
used for clock output, the output clock frequency is equal to the baud rate, and the clock pulse rises
at the center of the transmit data bits. Figure 9-3 shows the phase relationship between the output
clock and transmit data.
Output clock
Start bit
Transmit data
D1
D2
D3
Figure 9-3. Phase Relationship Between Clock Output and Transmit Data
195
(3) Data Transmission and Reception
• SCI Initialization: Before data can be transmitted or received, the SCI must be initialized by
software. To initialize the SCI, software must clear the TE and RE bits to “0,” then execute the
following procedure.
➀ Write the value corresponding to the desired bit rate in the BRR. (This step is not necessary if
an external clock is used.)
➁ Select the desired communication parameters in the SCR. Leave bit 0 (CKE0) cleared to zero.
➂ Select clocked synchronous mode in the SMR.
➃ Set the TE and/or RE bit in the SCR to “1.”
The TE and RE bits must both be cleared to “0” whenever the operating mode or data format is
changed.
After changing the operating mode or data format, before setting the TE and RE bits to “1”
software must wait for at least the transfer time for 1 bit at the selected baud rate, to make sure the
SCI is initialized. If an external clock is used, the clock must not be stopped.
When clearing the TDRE bit during data transmission, to assure transfer of the correct data, do not
clear the TDRE bit until after writing data in the TDR. Similarly, in receiving data, do not clear the
RDRF bit until after reading data from the RDR.
• Data Transmission: The procedure for transmitting data is as follows.
➀ Set up the desired transmitting conditions in the SMR, SCR, and BRR.
➁ Set the TE bit in the SCR to “1.”
The ATxD pin will automatically be switched to output and one frame* of all 1’s will be
transmitted, after which the SCI is ready to transmit data.
➂ Check that the TDRE bit is set to “1,” then write the first byte of transmit data in the TDR.
Next clear the TDRE bit to “0.”
196
➃ The first byte of transmit data is transferred from the TDR to the TSR and sent in the designated
format as follows.
i) Start bit (one “0” bit).
ii) Transmit data (seven or eight bits, starting from bit 0)
iii) Parity bit (odd or even parity bit, or no parity bit)
iv) Stop bit (one or two consecutive “1” bits)
➄ Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the TDRE bit
is set to “1.”
If the TIE bit is set to “1,” a transmit-end interrupt (TxI) is requested.
When the transmit function is enabled but the TDR is empty (TDRE = “1”), the output at the
ATxD pin is held at “1” until the TDRE bit is cleared to “0.”
* A frame is the data for one character, including the start bit and stop bit(s).
• Data Reception: The procedure for receiving data is as follows.
➀ Set up the desired receiving conditions in the SMR, SCR, and BRR.
➁ Set the RE bit in the SCR to “1.”
The ARxD pin is automatically be switched to input and the SCI is ready to receive data.
➂ The SCI synchronizes with the incoming data by detecting the start bit, and places the received
bits in the RSR. At the end of the data, the SCI checks that the stop bit is “1.”
➃ When a complete frame has been received, the SCI transfers the received data from the RSR to
the RDR so that it can be read. If the character length is 7 bits, the most significant bit of the
RDR is cleared to “0.”
At the same time, the SCI sets the RDRF bit in the SSR to “1.” If the RIE bit is set to “1,” a
receive-end interrupt (RxI) is requested.
➄ The RDRF bit is cleared to “0” when software reads the SSR, then writes a “0” in the RDRF bit.
The RDR is then ready to receive the next character from the RSR.
When a frame is not received correctly, a receive error occurs. There are three types of receive
errors, listed in Table 9-8.
197
If a receive error occurs, the RDRF bit in the SSR is not set to “1.” (For an overrun error, RDRF is
already set to "1.") The corresponding error flag is set to “1” instead. If the RIE bit in the SCR is
set to “1,” a receive-error interrupt (ERI) is requested.
When a framing or parity error occurs, the RSR contents are transferred to the RDR. If an overrun
error occurs, however, the RSR contents are not transferred to the RDR.
If multiple receive errors occur simultaneously, all the corresponding error flags are set to “1.”
To clear a receive-error flag (ORER, FER, or PER), software must read the SSR and then write a
“0” in the flag bit.
Table 9-8. Receive Errors
Name
Abbreviation
Description
Overrun error
ORER
Reception of the next frame ends while the
RDRF bit is still set to “1.”
The RSR contents are not transferred to the
RDR.
Framing error
Parity error
FER
PER
A stop bit is “0.”
The RSR contents are transferred to the RDR.
The parity of a frame does not match the value
selected by the O/E bit in the SMR.
The RSR contents are transferred to the RDR.
9.3.3 Synchronous Mode
The synchronous mode is suited for high-speed, continuous data transfer. Each bit of data is
synchronized with a serial clock pulse at the CSCK pin.
Continuous data transfer is enabled by the double buffering employed in both the transmit and
receive sections of the SCI. Full duplex communication is possible because the transmit and
receive sections are independent.
(1) Data Format: Figure 9-4 shows the communication format used in the synchronous mode.
The data length is 8 bits for both the transmit and receive directions. The least significant bit (LSB)
is sent and received first. Each bit of transmit data is output from the falling edge of the serial
clock pulse to the next falling edge. Received bits are latched on the rising edge of the serial clock
pulse.
198
Transmission direction
Serial clock
Data
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t-care
Don’t-care
Serial
clock
8-Bit data
8-Bit data
Data
Figure 9-4. Data Format in Synchronous Mode
(2) Clock: Either the internal serial clock created by the on-chip baud rate generator or an external
clock input at the CSCK pin can be selected in the synchronous mode. See Table 9-6 for details.
(3) Data Transmission and Reception
• SCI Initialization: Before data can be transmitted or received, the SCI must be initialized by
software. To initialize the SCI, software must clear the TE and RE bits to “0” to disable both the
transmit and receive functions, then execute the following procedure.
➀ Write the value corresponding to the desired bit rate in the BRR. (This step is not necessary if
an external clock is used.)
➁ Select the clock and enable desired interrupts in the SCR. Leave bit 0 (CKE0) cleared to "0."
➂ Select the synchronous mode in the SMR.
➃ Set the TE and/or RE bit in the SCR to “1.”
The TE and RE bits must both be cleared to “0” whenever the operating mode or data format is
changed. After changing the operating mode or data format, before setting the TE and RE bits to
“1” software must wait for at least 1 bit transfer time at the selected communication speed, to make
sure the SCI is initialized.
199
When clearing the TDRE bit during data transmission, to assure correct data transfer, do not clear
the TDRE bit until after writing data in the TDR. Similarly, in receiving data, do not clear the
RDRF bit until after reading data from the RDR.
• Data Transmission: The procedure for transmitting data is as follows.
➀ Set up the desired transmitting conditions in the SMR, BRR, and SCR.
➁ Set the TE bit in the SCR to “1.”
The CTxD pin will automatically be switched to output, after which the SCI is ready to transmit
data.
➂ Check that the TDRE bit is set to “1,” then write the first byte of transmit data in the TDR.
Next clear the TDRE bit to “0.”
➃ The first byte of transmit data is transferred from the TDR to the TSR and sent, each bit
synchronized with a clock pulse. Bit 0 is sent first.
Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the TDRE bit
is set to “1.” If the TIE bit is set to “1,” a transmit-end interrupt (TxI) is requested.
The TDR and TSR function as a double buffer. Continuous data transmission can be achieved by
writing the next transmit data in the TDR and clearing the TDRE bit to “0” while the SCI is
transmitting the current data from the TSR.
If an internal clock source is selected, after transferring the transmit data from the TDR to the TSR,
while transmitting the data from the TSR the SCI also outputs a serial clock signal at the CSCK
pin. When all data bits in the TSR have been transmitted, if the TDR is empty (TDRE = “1”),
serial clock output is suspended until the next data byte is written in the TDR and the TDRE bit is
cleared to “0.” During this interval the CTxD pin continues to output the value of the last bit of the
previous data.
If the external clock source is selected, data transmission is synchronized with the clock signal
input at the CSCK pin. When all data bits in the TSR have been transmitted, if the TDR is empty
(TDRE = “1”) but external clock pulses continue to arrive, the CTxD pin outputs the value of last
bit of the previous data.
• Data Reception: The procedure for receiving data is as follows.
200
➀ Set up the desired receiving conditions in the SMR, BRR, and SCR.
➁ Set the RE bit in the SCR to “1.”
The CRxD pin is automatically be switched to input and the SCI is ready to receive data.
➂ Incoming data bits are latched in the RSR on eight clock pulses.
When 8 bits of data have been received, the SCI sets the RDRF bit in the SSR to “1.” If the
RIE bit is set to “1,” a receive-end interrupt (RxI) is requested.
➃ The SCI transfers the received data byte from the RSR to the RDR so that it can be read.
The RDRF bit is cleared when software reads the RDRF bit in the SSR, then writes a “0” in the
RDRF bit.
The RDR and RSR function as a double buffer. Data can be received continuously by reading each
byte of data from the RDR and clearing the RDRF bit to “0” before the last bit of the next byte is
received.
In general, an external clock source should be used for receiving data.
If an internal clock source is selected, the SCI starts receiving data as soon as the RE bit is set to
“1.” The serial clock is also output at the CSCK pin. The SCI continues receiving until the RE bit
is cleared to “0.”
If the last bit of the next data byte is received while the RDRF bit is still set to “1,” an overrun error
occurs and the ORER bit is set to “1.” If the RIE bit is set to “1,” a receive-error interrupt (ERI) is
requested. The data received in the RSR are not transferred to the RDR when an overrun error
occurs.
After an overrun error, reception of the next data is enabled when the ORER bit is cleared to “0.”
• Simultaneous Transmit and Receive: The procedure for transmitting and receiving
simultaneously is as follows:
➀ Set up the desired communication conditions in the SMR, BRR, and SCR.
➁ Set the TE and RE bits in the SCR to “1.”
The CTxD and CRxD pins are automatically switched to output and input, respectively, and the
SCI is ready to transmit and receive data.
201
➂ Data transmitting and receiving start when the TDRE bit in the SSR is cleared to “0.”
➃ Data are sent and received in synchronization with eight clock pulses.
➄ First, the transmit data are transferred from the TDR to the TSR. This makes the TDR empty,
so the TDRE bit is set to “1.” If the TIE bit is set to “1,” a transmit-end interrupt (TxI) is
requested.
If continuous data transmission is desired, software must read the TDRE bit in the SSR, write
the next transmit data in the TDR, then clear the TDRE bit to “0.”
If the TDRE bit is not cleared to “0” by the time the SCI finishes sending the current byte from
the TSR, the CTxD pin continues to output the value of last bit of the previous data.
➅ In the receiving section, when 8 bits of data have been received they are transferred from the
RSR to the RDR and the RDRF bit in the SSR is set to “1.” If the RIE bit is set to “1,” a
receive-end interrupt (RxI) is requested.
➆ To clear the RDRF bit software should read the RDRF bit in the SSR, read the data in the RDR,
then write a “0” in the RDRF bit.
For continuous data reception, software should read the RDRF bit in the SSR, read the data in
the RDR, then clear the RDRF bit to “0.”
If the last bit of the next byte is received while the RDRF bit is still set to “1,” an overrun error
occurs. The error is handled as described under “Data Reception” above. The overrun error does
not affect the transmit section of the SCI, which continues to transmit normally.
9.4 Interrupts
The SCI can request three types of interrupts: transmit-end (TxI), receive-end (RxI), and receive-
error (ERI). Interrupt requests are enabled or disabled by the TIE and RIE bits in the SCR.
Independent signals are sent to the interrupt controller for each type of interrupt. The transmit-end
and receive-end interrupt request signals are obtained from the TDRE and RDRF flags. The
receive-error interrupt request signal is the logical OR of the three error flags: overrun error
(ORER), framing error (FER), and parity error (PER). Table 9-9 lists information about these
interrupts.
202
Table 9-9. SCI Interrupts
Interrupt
Description
Priority
ERI
Receive-error interrupt, requested when ORER, FER, or PER
is set. RIE must also be set.
High
RxI
TxI
Receive-end interrupt, requested when RDRF and RIE are set.
Transmit-end interrupt, requested when TDRE and TIE are set.
Low
Figure 9-5 shows the timing of the RxI interrupt signal. The timing of TxI and ERI is similar.
Ø
Internal
Receive-
End
signal
RDRF
RxI
Figure 9-5. Timing of Interrupt Signal
9.5 Application Notes
Application programmers should note the following features of the SCI.
(1) TDR Write: The TDRE bit in the SSR is simply a flag that indicates that the TDR contents
have been transferred to the TSR. The TDR contents can be rewritten regardless of the TDRE
value. If a new byte is written in the TDR while the TDRE bit is “0,” before the old TDR contents
have been moved into the TSR, the old byte will be lost. Normally, software should check that the
TDRE bit is set to “1” before writing to the TDR.
(2) Multiple Receive Errors: Table 9-10 lists the values of flag bits in the SSR when multiple
receive errors occur, and indicates whether the RSR contents are transferred to the RDR.
203
Table 9-10. SSR Bit States and Data Transfer When Multiple Receive Errors Occur
SSR Bits
2
Receive error
RDRF
ORER
FER
PER
RSR → RDR*
1
Overrun error
1*
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
1
No
Yes
Yes
No
No
Yes
No
Framing error
0
0
Parity error
1
Overrun + framing errors
Overrun + parity errors
Framing + parity errors
Overrun + framing + parity errors
1*
1
1*
0
1
1*
1
* Set to “1” before the overrun error occurs.
2
* Yes: The RSR contents are transferred to the RDR.
No: The RSR contents are not transferred to the RDR.
(3) Line Break Detection: When the ARxD pin receives a continuous stream of 0’s in the
asynchronous mode (line-break state), a framing error occurs because the SCI detects a “0” stop bit.
The value H’00 is transferred from the RSR to the RDR. Software can detect the line-break state as
a framing error accompanied by H’00 data in the RDR.
The SCI continues to receive data, so if the FER bit is cleared to “0” another framing error will
occur.
(4) Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by
the SCI in asynchronous mode runs at 16 times the baud rate. The falling edge of the start bit is
detected by sampling the ARxD input on the falling edge of this clock. After the start bit is
detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits)
is sampled on the rising edge of the serial clock pulse at the center of the bit. See Figure 9-6.
It follows that the receive margin can be calculated as in equation (1).
When the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5, data
can theoretically be received with distortion up to the margin given by equation (2). This is a
theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%.
204
0 1 2 3 4 5 6 7 89 10111213141516 1 2 3 4 5 6 7 8 9101112131415161 2 3 4 5
Basic clock
–7.5 pulses
+7.5 pulses
Receive data
D0
D1
Start bit
Sync sampling
Data sampling
Figure 9-6. Sampling Timing (Asynchronous Mode)
M = {(0.5 – 1/2N) – (D – 0.5)/N – (L – 0.5)F} × 100 [%]
(1)
M: Receive margin
N: Ratio of basic clock to baud rate (N=16)
D: Duty factor of clock—ratio of High pulse width to Low width (0.5 to 1.0)
L: Frame length (9 to 12)
F: Absolute clock frequency deviation
When D = 0.5 and F= 0
M=(0.5 –1/2 × 16) × 100 [%] = 46.875%
(2)
205
Section 10. A/D Converter
10.1 Overview
The H8/330 chip includes an analog-to-digital converter module with eight input channels. A/D
conversion is performed by the successive approximations method with 8-bit resolution.
10.1.1 Features
The features of the on-chip A/D module are:
• Eight analog input channels
• 8-bit resolution
• Rapid conversion
Conversion time is 12.2µs per channel (minimum) with a 10MHz system clock
• External triggering can be selected
• Single and scan modes
– Single mode: A/D conversion is performed once.
– Scan mode: A/D conversion is performed in a repeated cycle on one to four channels.
• Four 8-bit data registers
These registers store A/D conversion results for up to four channels.
• A CPU interrupt (ADI) can be requested at the completion of each A/D conversion cycle.
207
10.1.2 Block Diagram
Internal
data bus
Module data bus
AVCC
A
D
D
R
A
A
D
D
R
B
A
D
D
R
C
A
D
D
R
D
A
D
C
S
R
A
D
C
R
8 Bit
D/A
AVSS
AN0
Ø/8
Ø/16
AN1
AN2
+
–
Analog
multi-
plexer
AN3
AN4
AN5
Control circuit
Comparator
AN6
AN7
Sample and
hold circuit
ADI
Interrupt signal
ADTRG
ADCR: A/D Control Register (8 bits)
ADCSR: A/D Control/Status Register (8 bits)
ADDRA: A/D Data Register A (8 bits)
ADDRB: A/D Data Register B (8 bits)
ADDRC: A/D Data Register C (8 bits)
ADDRD: A/D Data Register D (8 bits)
Figure 10-1. Block Diagram of A/D Converter
208
10.1.3 Input Pins
Table 10-1 lists the input pins used by the A/D converter module.
The eight analog input pins are divided into two groups, consisting of analog inputs 0 to 3 (AN0 to
AN3) and analog inputs 4 to 7 (AN4 to AN7), respectively.
Table 10-1. A/D Input Pins
Name
Abbreviation I/O
Function
Analog supply voltage
AVCC
Input
Power supply and reference voltage for the
analog circuits.
Analog ground
AVSS
Input
Ground and reference voltage for the
analog circuits.
Analog input 0
Analog input 1
Analog input 2
Analog input 3
Analog input 4
Analog input 5
Analog input 6
Analog input 7
A/D external trigger
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADTRG
Input
Input
Input
Input
Input
Input
Input
Input
Input
Analog input pins, group 0
Analog input pins, group 1
External trigger for starting A/D conversion
10.1.4 Register Configuration
Table 10-2 lists the registers of the A/D converter module.
Table 10-2. A/D Registers
Name
Abbreviation R/W
Initial value Address
A/D data register A
A/D data register B
A/D data register C
A/D data register D
A/D control/status register
A/D control register
ADDRA
ADDRB
ADDRC
ADDRD
ADCSR
ADCR
R
R
R
R
H’00
H’00
H’00
H’00
H’FFE0
H’FFE2
H’FFE4
H’FFE6
H’FFE8
H’FFEA
R/(W)* H’00
R/W H’7F
* Software can write a "0" to clear bit 7, but cannot write a "1" in this bit.
209
10.2 Register Descriptions
10.2.1 A/D Data Registers (ADDR) – H’FFE0 to H'FFE6
Bit
7
6
5
4
3
2
1
0
ADDRn
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 8-bit read-only registers that store the results
of A/D conversion. Each data register is assigned to two analog input channels as indicated in
Table 10-3.
The A/D data registers are always readable by the CPU.
The A/D data registers are initialized to H’00 at a reset and in the standby modes.
Table 10-3. Assignment of Data Registers to Analog Input Channels
Analog input channel
Group 0 Group 1 A/D data register
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADDRA
ADDRB
ADDRC
ADDRD
10.2.2 A/D Control/Status Register (ADCSR) – H’FFE8
Bit
7
ADF
0
6
ADIE
0
5
4
3
2
1
0
ADST SCAN
CKS
0
CH2
0
CH1
0
CH0
0
Initial value
Read/Write
0
0
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
* Software can write a “0” in bit 7 to clear the flag, but cannot write a “1” in this bit.
The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the
operation of the A/D converter module.
210
The ADCSR is initialized to H’00 at a reset and in the standby modes.
Bit 7 – A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion.
Bit 7
ADF
Description
0
To clear ADF, the CPU must read ADF after
it has been set to "1," then write a "0" in this bit.
This bit is set to 1 at the following times:
(1) Single mode: when one A/D conversion is completed.
(2) Scan mode: when inputs on all selected channels have
been converted.
(Initial value)
1
Bit 6 – A/D Interrupt Enable (ADIE): This bit selects whether to request an A/D interrupt (ADI)
when A/D conversion is completed.
Bit 6
ADIE
Description
0
1
The A/D interrupt request (ADI) is disabled.
The A/D interrupt request (ADI) is enabled.
(Initial value)
Bit 5 – A/D Start (ADST): The A/D converter operates while this bit is set to “1.” In the single
mode, this bit is automatically cleared to “0” at the end of each A/D conversion.
Bit 5
ADST
Description
0
1
A/D conversion is halted.
(Initial value)
(1) Single mode: One A/D conversion is performed. The ADST
bit is automatically cleared to “0” at the end of the conversion.
(2) Scan mode: A/D conversion starts and continues cyclically on the selected
channels until the ADST bit is cleared to “0” by software (or a reset, or by entry to
a standby mode).
211
Bit 4 – Scan Mode (SCAN): This bit selects the scan mode or single mode of operation.
See Section 10.3, “Operation” for descriptions of these modes.
The mode should be changed only when the ADST bit is cleared to “0.”
Bit 4
SCAN
Description
Single mode
Scan mode
0
1
(Initial value)
Bit 3 – Clock Select (CKS): This bit controls the A/D conversion time.
The conversion time should be changed only when the ADST bit is cleared to “0.”
Bit 3
CKS
Description
0
1
Conversion time = 242 states (max.)
Conversion time = 122 states (max.)
(Initial value)
Bits 2 to 0 – Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit combine to select
one or more analog input channels.
The channel selection should be changed only when the ADST bit is cleared to “0.”
Group select
Channel select
Selected channels
CH2
CH1
CH0
Single mode
Scan mode
AN0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AN0 (Initial value)
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN0, AN1
AN0 to AN2
AN0 to AN3
AN4
1
AN4, AN5
AN4 to AN6
AN4 to AN7
212
10.2.3 A/D Control Register (ADCR) – H’FFEA
Bit
7
TRGE
0
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
R/W
—
—
—
—
—
—
—
The A/D control register (ADCR) is an 8-bit readable/writable register that enables or disables the
A/D external trigger signal.
The ADCR is initialized to H’7F at a reset and in the standby modes.
Bit 7 – Trigger Enable (TRGE): This bit enables the ADTRG (A/D external trigger) signal to set
the ADST bit and start A/D conversion.
Bit 7
TRGE
Description
0
A/D external trigger is disabled. ADTRG does not set
the ADST bit.
(Initial value)
1
A/D external trigger is enabled. ADTRG sets the ADST bit.
(The ADST bit can also be set by software.)
Bits 6 to 0 – Reserved: These bits cannot be modified and are always read as “1.”
10.3 Operation
The A/D converter performs 8 successive approximations to obtain a result ranging from H’00
(corresponding to AVSS) to H’FF (corresponding to AVCC). Figure 10-2 shows the response of the
A/D converter.
213
H'FF
H'00
AVss
AVcc
Figure 10-2. The Response of the A/D Converter
The A/D converter module can be programmed to operate in single mode or scan mode as
explained below.
10.3.1 Single Mode (SCAN = 0)
The single mode is suitable for obtaining a single data value from a single channel. A/D
conversion starts when the ADST bit is set to “1,” either by software or by a High-to-Low
transition of the ADTRG signal (if enabled). During the conversion process the ADST bit remains
set to “1.” When conversion is completed, the ADST bit is automatically cleared to “0.”
When the conversion is completed, the ADF bit is set to “1.” If the interrupt enable bit (ADIE) is
also set to “1,” an A/D conversion end interrupt (ADI) is requested, so that the converted data can
be processed by an interrupt-handling routine. The ADF bit is cleared when software reads the
A/D control/status register (ADCSR), then writes a “0” in this bit.
Before selecting the single mode, clock, and analog input channel, software should clear the ADST
bit to “0” to make sure the A/D converter is stopped. Changing the mode, clock, or channel
selection while A/D conversion is in progress can lead to conversion errors. A/D conversion begins
when the ADST bit is set to "1" again. The same instruction can be used to alter the mode and
channel selection and set ADST to "1."
214
The following example explains the A/D conversion process in single mode when channel 1 (AN1)
is selected and the external trigger is disabled. Figure 10-3 shows the corresponding timing chart.
(1) Software clears the ADST bit to “0,” then selects the single mode (SCAN = “0”) and channel 1
(CH2 to CH0 = “001”), enables the A/D interrupt request (ADIE = “1”), and sets the ADST bit
to “1” to start A/D conversion.
Coding Example: (when using the slow clock, CKS = “0”)
BCLR #5, @H’FFE8
MOV.B #H’7F, ROL
MOV.B ROL, @H’FFEA
MOV.B #H’61, ROL
MOV.B ROL, @H’FFE8
Value set in ADCSR:
;Clear ADST
;Disable external trigger
;Select mode and channel and set ADST to "1"
ADF
0
ADIE
ADST SCAN
CKS
0
CH2
0
CH1
0
CH0
1
1
1
0
(2) The A/D converter converts the voltage level at the the AN1 input pin to a digital value. At the
end of the conversion process the A/D converter transfers the result to register ADDRB, sets
the ADF bit is set to “1,” clears the ADST bit to “0,” and halts.
(3) ADF = “1” and ADIE = “1,” so an A/D interrupt is requested.
(4) The user-coded A/D interrupt-handling routine is started.
(5) The interrupt-handling routine reads the ADCSR value, then writes a “0” in the ADF bit to
clear this bit to “0.”
(6) The interrupt-handling routine reads and processes the A/D conversion result.
(7) The routine ends.
Steps (2) to (7) can now be repeated by setting the ADST bit to “1” again.
215
Interrupt (ADI)
ADIE
Set*
Set*
Set*
A/D conversion starts
ADST
ADF
Clear*
Clear*
Channel 0 (AN 0)
Waiting
Waiting
Waiting
Waiting
Channel 1 (AN 1)
A/D conver-
sion
Waiting
Waiting
A/D conver-
sion ➁
➀
Channel 2 (AN 2)
Channel 3 (AN 3)
ADDRA
ADDRB
ADDRC
ADDRD
Read result
Read result
A/D conversion result
A/D conversion result
➀
➁
indicates execution of a software instruction
*
Figure 10-3. A/D Operation in Single Mode (When Channel 1 is Selected)
10.3.2 Scan Mode (SCAN = 1)
The scan mode can be used to monitor analog inputs on one or more channels. When the ADST bit
is set to “1,” either by software or by a High-to-Low transition of the ADTRG signal (if enabled),
A/D conversion starts from the first channel selected by the CH bits. When CH2 = “0” the first
channel is AN0. When CH2 = “1” the first channel is AN4.
If the scan group includes more than one channel (i.e. if bit CH1 or CH0 is set), conversion of the
next channel begins as soon as conversion of the first channel ends.
Conversion of the selected channels continues cyclically until the ADST bit is cleared to “0.” The
conversion results are placed in the data registers corresponding to the selected channels. The A/D
data registers are readable by the CPU.
Before selecting the scan mode, clock, and analog input channels, software should clear the ADST
bit to “0” to make sure the A/D converter is stopped. Changing the mode, clock, or channel
selection while A/D conversion is in progress can lead to conversion errors. A/D conversion begins
when the ADST bit is set to "1" again. The same instruction can be used to alter the mode and
channel selection and set ADST to "1."
The following example explains the A/D conversion process when three channels in group 0 are
selected (AN0, AN1, and AN2) and the external trigger is disabled. Figure 10-4 shows the
corresponding timing chart.
(1) Software clears the ADST bit to “0,” then selects the scan mode (SCAN = “1”), scan group 0
(CH2 = “0”), and analog input channels AN0 to AN2 (CH1 and CH0 = “0”) and sets the
ADST bit to “1” to start A/D conversion.
Coding Example: (with slow clock and ADI interrupt enabled)
BCLR #5, @H’FFE8
MOV.B #H’7F, ROL
MOV.B ROL, @H’FFEA
MOV.B #H’72, ROL
MOV.B ROL, @H’FFE8
Value set in ADCSR
;Clear ADST
;Disable external trigger
;Select mode and channels and set ADST to "1"
ADF
0
ADIE
ADST SCAN
CKS
0
CH2
0
CH1
1
CH0
0
1
1
1
217
(2) The A/D converter converts the voltage level at the AN0 input pin to a digital value, and
transfers the result to register ADDRA.
(3) Next the A/D converter converts AN1 and transfers the result to ADDRB. Then it converts
AN2 and transfers the result to ADDRC.
(4) After all selected channels (AN0 to AN2) have been converted, the AD converter sets the ADF
bit to “1.” If the ADIE bit is set to “1,” an A/D interrupt (ADI) is requested. Then the A/D
converter begins converting AN0 again.
(5) Steps (2) to (4) are repeated cyclically as long as the ADST bit remains set to “1.”
To stop the A/D converter, software must clear the ADST bit to “0.”
Regardless of which channel is being converted when the ADST bit is cleared to “0,” when the
ADST bit is set to “1” again, conversion begins from the the first selected channel (AN0 or AN4).
218
Continuous A/D conversion
Clear *1
1
*
Set
ADST
Clear*1
ADF
A/D conversion
time
Channel 0 (AN 0)
A/D conver-
A/D conver-
Waiting
Waiting
Waiting
Waiting
Waiting
sion
sion
➀
➃
Channel 1 (AN 1)
2
A/D conver-
sion ➁
Waiting
Waiting
A/D conver-
sion ➄
*
Channel 2 (AN 2)
Channel 3 (AN 3)
ADDRA
Waiting
A/D conver-
➂
sion
Waiting
Transfer
A/D conversion result
A/D conver-
➃
➀
sion result
ADDRB
ADDRC
A/D conversion result
➁
A/D conversion result
➂
ADDRD
1
indicates execution of a software instruction
Data undergoing conversion when ADST bit is cleared are ignored.
*
2
*
Figure 10-4. A/D Operation in Scan Mode (When Channels 0 to 2 are Selected)
Note: If the ADST bit is cleared to "0" when two or more channels are selected in the scan mode,
incorrect values may be left in the A/D data registers.
For this reason, in the scan mode the A/D data registers should be read while the ADST bit is still
set to "1."
Example: The following coding example sets up a four-channel A/D scan, and shows the first part
of an ADI interrupt handler for reading the converted data. Note that the data are read before the
ADST bit is cleared.
MOV.B
MOV.B
BSET
#5B
R0L
#5
, R0L
, @ADCSR ; Four-channel scan mode
, @ADCSR ; Start conversion (set ADST)
(Conversion of four channels)
ADI: MOV.B
MOV.B
@ADDRA , R1
@ADDRB , R2
@ADDRC , R3
@ADDRD , R4
; Read ADDRA
; Read ADDRB
; Read ADDRC
; Read ADDRD
MOV.B
MOV.B
BCLR
#5
#7
, @ADCSR ; Clear ADST
, @ADCSR ; Clear ADF
BCLR
(It is not necessary to clear the ADST bit in order to read ADDRA to ADDRD.)
10.3.3 Input Sampling Time and A/D Conversion Time
The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a
time tD after the ADST bit is set to "1." The sampling process lasts for a time tSPL. The actual A/D
conversion begins after sampling is completed. Figure 10-5 shows the timing of these steps. Table
10-4 (a) lists the conversion times for the single mode. Table 10-4 (b) lists the conversion times for
the scan mode.
The total conversion time (tCONV) includes tD and tSPL. The purpose of tD is to synchronize the
ADCSR write time with the A/D conversion process, so the length of tD is variable. The total
conversion time therefore varies within the minimum to maximum ranges indicated in table 10-4
(a) and (b).
220
In the scan mode, the ranges given in table 10-4 (b) apply to the first conversion. The length of the
second and subsequent conversion processes is fixed at 256 states (when CKS = "0") or 128 states
(when CKS = "1").
(1)
Ø
Internal address bus
(2)
Write signal
Input sampling timing
ADF
tD
tSPL
tCONV
(Notation)
(1)
ADCSR write cycle
ADCSR address
(2)
tD
Synchronization delay
Input sampling time
tSPL
tCONV
Total A/D conversion time
Figure 10-5. A/D Conversion Timing
221
Table 10-4 (a). A/D Conversion Time (Single Mode)
CKS = "0"
CKS = "1"
Item
Symbol min
typ
—
63
—
max
33
min
10
typ
—
31
—
max
17
Synchronization delay
Input sampling time
tD
18
tSPL
—
—
—
—
Total A/D conversion time tCONV
227
242
115
122
Table 10-4 (b). A/D Conversion Time (Scan Mode)
CKS = "0"
typ
CKS = "1"
Item
Symbol min
max
33
min
10
typ
—
31
—
max
17
Synchronization delay
Input sampling time
tD
18
—
63
—
tSPL
—
—
—
—
Total A/D conversion time tCONV
259
274
131
138
Note: Values in the tables above are numbers of states.
10.3.4 External Trigger Input Timing
A/D conversion can be started by external trigger input at the ADTRG pin. This input is enabled or
disabled by the TRGE bit in the A/D control register (ADCR). If the TRGE bit is set to "1," when
a falling edge of ADTRG is detected the ADST bit is set to "1" and A/D conversion begins.
Subsequent operation is the same as when the ADST bit is set to "1" by software.
Figure 10-6 shows the trigger timing.
Ø
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 10-6. External Trigger Input Timing
222
10.4 Interrupts
The A/D conversion module generates an A/D-end interrupt request (ADI) at the end of A/D
conversion.
The ADI interrupt request can be enabled or disabled by the ADIE bit in the A/D control/status
register (ADCSR).
223
Section 11. Dual-Port RAM (Parallel Communication
Interface)
11.1 Overview
The H8/330 has an on-chip dual-port RAM (DPRAM) that can be accessed by both the CPU on the
H8/330 chip and a master CPU on another chip. The dual-port RAM can be used only in the
single-chip mode (mode 3), and only when the DPME bit in the system control register (SYSCR) is
set to "1." The dual-port-RAM-enabled mode is called slave mode because it is designed for a
master-slave system in which the dual-port RAM provides a parallel communication interface with
a master CPU.
In this section the CPU on the H8/330 chip will be referred to as the H8/300 CPU.
11.1.1 Features
• 15-Byte capacity
Fifteen 8-bit parallel communication data registers
• Standard external memory interface
The master CPU can be connected to the dual-port RAM in the same way as to a memory chip.
• Simple data-transfer protocol
• Can generate master CPU interrupts
225
11.1.2 Block Diagram
Figure 11-1 shows a block diagram of the dual-port RAM.
Internal
data bus
Bus interface
Module data bus
P
C
D
R
0
P
C
D
R
0
CS
MREI
P
C
C
S
R
P
C
D
R
1
P
C
D
R
14
OE
to
WE
RDY
MWEI
A
B
Bus interface
DDB7 to DDB0
RS3 to RS0
PCCSR: Parallel Communication Control/Status Register
PCDR0: Parallel Communication Data Register 0
PCDR1 to 14 : Paralle Communication Data Register 1 to 14
Figure 11-1. Block Diagram of Dual-Port RAM
226
11.1.3 Input and Output Pins
Table 11-1 lists the input and output pins of the dual-port RAM.
Table 11-1. Dual-Port RAM Input and Output Pins
Name
Abbreviation
I/O
Function
DPRAM data bus
DDB7 to DDB0
Input/output An 8-bit parallel data bus by which the
master CPU can access the dual-port
RAM.
Chip select
CS
Input
Chip select input pin for selecting the
dual-port RAM.
Register select
Output enable
Write enable
RS3 to RS0
OE
Input
Input
Input
Dual-port RAM address input.
Enables output on the DPRAM data bus.
Enables data to be written in the dual-port
RAM via the DPRAM data bus.
Indicates that the dual-port RAM is ready
to be written or read by the master CPU.
(NMOS open-drain output)
WE
Ready
RDY
Output *
* NMOS open drain output.
11.1.4 Register Configuration
Table 11-2 lists the registers of the dual-port RAM.
Table 11-2. Dual-Port RAM Register Configuration
Read/write
H8/300 Master Initial On-chip
External address
Name
Abbr.
CPU
CPU
value
address RS3 RS2 RS1 RS0
Parallel communication PCCSR R/(W)* R/(W)* H’00
control/status register
H’FFF0 0
0
0
0
Parallel communication PCDR0A R
data register 0 PCDR0B W
W
Undeter- H’FFF1
0
0
0
0
0
0
0
0
1
1
1
0
R
mined H’FFF1
Undeter- H’FFF2
mined
Parallel communication PCDR1 R/W
data register 1
R/W
Parallel communication PCDR2 R/W
data register 2
R/W
R/W
Undeter- H’FFF3
mined
0
0
0
1
1
0
1
0
Parallel communication PCDR3 R/W
data register 3
Undeter- H’FFF4
mined
227
Table 11-2. Dual-Port RAM Register Configuration (cont.)
Read/write
H8/300 Master Initial On-chip
External address
Name
Abbr.
CPU
CPU
value
address RS3 RS2 RS1 RS0
Parallel communication PCDR4 R/W
data register 4
R/W
Undeter- H’FFF5
mined
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
Parallel communication PCDR5 R/W
data register 5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Undeter- H’FFF6
mined
Parallel communication PCDR6 R/W
data register 6
Undeter- H’FFF7
mined
Parallel communication PCDR7 R/W
data register 7
Undeter- H’FFF8
mined
Parallel communication PCDR8 R/W
data register 8
Undeter- H’FFF9
mined
Parallel communication PCDR9 R/W
data register 9
Undeter- H’FFFA
mined
Parallel communication PCDR10 R/W
data register 10
Undeter- H’FFFB
mined
Parallel communication PCDR11 R/W
data register 11
Undeter- H’FFFC
mined
Parallel communication PCDR12 R/W
data register 12
Undeter- H’FFFD
mined
Parallel communication PCDR13 R/W
data register 13
Undeter- H’FFFE
mined
Parallel communication PCDR14 R/W
data register 14
Undeter- H’FFFF
mined
Note: The H8/300 CPU can write only bits 6, 4, and 2 of the PCCSR. The master CPU can write
only bit 4.
11.2 Register Descriptions
11.2.1 Dual Port RAM Enable Bit (DPME)
The dual-port RAM is enabled or disabled by the DPRAM Enable (DPME) bit in the system
control register (SYSCR). In the extended modes the dual-port RAM is always disabled. In the
single-chip mode, the dual-port RAM is initially disabled but can be enabled by setting the DPME
bit to "1."
228
System Control Register (SYSCR)—H’FFC4
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
—
1
2
1
0
NMIEG DPME RAME
Initial value
Read/Write
0
0
1
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
The only bit in the system control register that concerns the dual-port RAM is the DPME bit. See
section 2.4.2, "System Control Register" for the other bits.
Bit 1 – Dual-Port RAM Enable (DPME): This bit enables or disables the dual-port RAM. The
dual-port RAM can be enabled only in the single-chip mode (mode 3).
Bit 1
DPME
Description
0
1
The dual-port RAM is disabled.
The dual-port RAM is enabled (in single-chip mode only).
(Initial value)
If the DPME bit is set to “1” while the H8/330 is operating in the single-chip mode, the following
pins are automatically assigned to dual-port RAM functions, regardless of their data direction
register settings:
Port 3 (P37 to P30) →DDB7 to DDB0 (parallel communication data bus; input/output)
Port 8 (P83 to P80) →RS3 to RS0 (dual-port RAM register select; input)
In port 9,
P97 → WE (Write Enable; input)
P95 →RDY (Ready; output)
P94 → OE (Output Enable; input)
P93 → CS (Chip Select; input)
The DPME bit is initialized to “0” by a reset and in the hardware standby mode.
Setting the DPME bit to "1" in the expanded modes (modes 1 and 2) has no effect.
229
11.2.2 Parallel Communication Data Register 0 (PCDR0) – H’FFF1
(a) Parallel Communication Data Register 0A (PCDR0A)
Bit
7
6
5
4
3
2
1
0
Initial value
R/W H8/300 CPU
Master CPU
—
R
—
R
—
R
—
R
—
R
—
R
—
R
—
R
W
W
W
W
W
W
W
W
(b) Parallel Communication Data Register 0B (PCDR0B)
Bit
7
6
5
4
3
2
1
0
Initial value
R/W H8/300 CPU
Master CPU
—
W
R
—
W
R
—
W
R
—
W
R
—
W
R
—
W
R
—
W
R
—
W
R
Parallel communication data register 0 consists of two separate 8-bit registers with the same
address. As shown in Figure 11-2, PCDR0A is written by the H8/300 CPU and read by the master
CPU; PCDR0B is written by the master CPU and read by the H8/300 CPU. This arrangement
prevents contention even if both CPUs write to PCDR0 at the same time. When either CPU reads
PCDR0, it is assured of reading data written by the other CPU.
Internal data bus
Read
H8/300 CPU
Write
PCDR0A
PCDR0B
Read
PCDR 0
Write
External data bus
Master CPU
Figure 11-2. Parallel Communication Data Register 0
230
The value in PCDR0 after a reset is undetermined. In non-slave modes, the value obtained by
reading PCDR0 is unpredictable.
11.2.3 Parallel Communication Data Registers 1 to 14 – H’FFF2 (PCDR1) to H’FFFF
(PCDR1-14)
Bit
7
6
5
4
3
2
1
0
Initial value
—
—
—
—
—
—
—
—
R/W H8/300 CPU R/W
Master CPU R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Parallel communication data registers 1 to 14 are 8-bit registers which can be written and read by
either the H8/300 CPU or the master CPU. The H8/300 CPU can read and write these registers
regardless of the operating mode of the H8/330 chip. The master CPU can read and write them
only when the H8/330 chip is operating in slave mode.
In non-slave modes, these registers can be used as 14 bytes of data memory. Note that access
requires three states per byte, which is slower than the on-chip RAM.
The values in PCDR1 to PCDR14 after a reset are undetermined.
11.2.4 Parallel Communication Control/Status Register (PCCSR) – H’FFF0
Bit
7
6
5
4
3
2
1
0
MWEF EMWI SWEF EAKAR MREF EMRI MWMF SWMF
Initial value
R/W H8/300 CPU
Master CPU
0
R
R
0
R/W
R
0
R
R
0
0
R
R
0
R/W
R
0
R
R
0
R
R
R/W
R/W
The PCCSR is an 8-bit readable and partly writable register that provides protocol and interrupt
control functions. Either CPU can read and write bit 4, which enables the RDY signal. The
H8/300 CPU can read and write bits 6, 4 and 2, which enable interrupts. The other bits are read-
only bits.
The PCCSR is initialized to H’00 at a reset and in the standby modes.
231
In the bit names that follow, the H8/300 is referred to as the slave and the master CPU as the
master.
Bit 7 – Master Write End Flag (MWEF): This flag bit is used to indicate that the master CPU
has finished writing data in the parallel communication data registers. It is set when the master
CPU writes to PCDR14 and cleared when the H8/300 CPU reads PCDR14.
Bit 7
MWEF
Description
0
The H8/300 CPU has read PCDR14 while the dual-port
RAM was in the master write mode (MWMF = "1").
The master CPU has written data in PCDR14.
(Initial state)
1
Bit 6 – Enable Master Write Interrupt (EMWI): This bit enables or disables the master write
end interrupt (MWEI).
Bit 6
EMWI
Description
0
1
The master write end interrupt request (MWEI) is disabled.
The master write end interrupt request (MWEI) is enabled.
(Initial state)
Bit 5 – Slave Write End Flag (SWEF): This flag bit is used to indicate that the H8/300 CPU has
finished writing data in the parallel communication data registers. It is set when the H8/300 CPU
writes to PCDR14 and cleared when the master CPU reads PCDR14.
Bit 5
SWEF
Description
0
1
The master CPU has read PCDR14.
The H8/300 CPU has written data in PCDR14.
(Initial state)
Bit 4 – Enable Acknowledge and Request (EAKAR): This bit enables or disables the RDY
signal output by the H8/330 chip. If enabled:
• The RDY signal goes Low when the H8/300 CPU reads PCDR0 while the dual-port RAM is in
the master write mode (MWMF = "1"), or when the H8/300 CPU writes to PCDR14.
• The RDY signal goes High when the master CPU reads PCDR14 or the PCCSR, or when either
the master or H8/300 CPU writes to PCDR0.
In the non-slave modes this bit has no effect.
232
Bit 4
EAKAR Description
0
1
RDY output is disabled. RDY remains in the high-impedance state. (Initial state)
RDY output is enabled.
Bit 3 – Master Read End Flag (MREF): This flag indicates whether the master CPU has finished
reading data set in the parallel communication data registers.
Bit 3
MREF
Description
0
This bit is cleared to “0” when:
(Initial state)
• The H8/300 CPU reads or writes PCDR0.
• The master CPU writes to PCDR0.
This bit is set to “1” when the master CPU reads PCDR0.
1
Bit 2 – Enable Master Read Interrupt (EMRI): This bit enables or disables the master read end
interrupt (MREI).
Bit 2
EMRI
Description
0
1
The master read end interrupt request (MREI) is disabled.
The master read end interrupt request (MREI) is enabled.
(Initial state)
Bit 1 – Master Write Mode Flag (MWMF): This bit indicates when the dual-port RAM is in the
master write mode. The master CPU should check that this bit is set to “1” before writing to
parallel communication data registers 1 to 14. The H8/300 CPU cannot write in those registers
while this bit is set to “1.”
Bit 1
MWMF Description
0
This bit is cleared to “0” when the H8/300 CPU reads PCDR0.
The dual-port RAM is not in the master write mode. The master
CPU should avoid writing in PCDR1 to PCDR14.
(Initial state)
1
This bit is set to “1” if the master CPU writes to PCDR0 while the
SWMF flag is cleared to “0.” The dual-port RAM is in the master
write mode. Only the master CPU can write in PCDR1 to PCDR14.
233
Bit 0 – Slave Write Mode Flag (SWMF): This bit indicates when the dual-port RAM is in the
slave write mode. The H8/300 CPU should check that this bit is set to “1” before writing to parallel
communication data registers 1 to 14. The master CPU cannot write in those registers while this bit
is set to “1.”
Bit 0
SWMF
Description
0
This bit is cleared to “0” when the master CPU reads PCDR0.
The dual-port RAM is not in the slave write mode. The H8/300
CPU should avoid writing in PCDR1 to PCDR14.
(Initial state)
1
This bit is set to “1” if the H8/300 CPU writes to PCDR0 while the
MWMF flag is cleared to “0.” The dual-port RAM is in the slave
write mode. Only the H8/300 CPU can write in PCDR1 to PCDR14.
11.3 Usage
The dual-port RAM has a simple protocol for controlling the use of the data registers and parallel
communication data bus. The basic rule is that when either CPU writes to the dual-port RAM, it
should write to PCDR0 first and PCDR14 last. Conversely, in reading the dual-port RAM, the
CPU should read PCDR14 first and PCDR0 last.
Procedures for data transfer in both directions are given below. Figure 11-3 shows a timing chart.
11.3.1 Data Transfer from Master CPU to H8/300 CPU
The following procedure should be used when the master CPU sends data to the H8/300 CPU via
the dual-port RAM:
(1) The master CPU writes the first byte of data in PCDR0. If the dual-port RAM is not currently
in the slave write mode, MWMF is set to "1," placing it in the master write mode and
preventing the H8/300 CPU from writing in PCDR1 to PCDR14.
(2) The master CPU reads the PCCSR and checks MWMF. If MWMF is set to “1,” the master
CPU may continue writing in PCDR1 to PCDR14. If MWMF is cleared to "0," the dual-port
RAM is presumably in the slave write mode.
(3) The master CPU writes data in PCDR1 to PCDR13 as required, then writes the last byte in
PCDR14. This sets the master write end flag (MWEF) to “1,” notifying the H8/300 CPU that
the master CPU has finished writing. If EMWI is set to “1,” a master write end interrupt is
requested.
234
(4) After the master CPU has finished writing data, the H8/300 CPU first reads PCDR14. This
clears the master write end flag. Then the H8/300 CPU reads data from PCDR1 to PCDR13 as
required. Finally, the H8/300 CPU reads PCDR0. This clears MWMF, so the dual-port RAM
is no longer in the master write mode. If the EAKAR bit is set to “1,” the RDY signal goes
Low to acknowledge the received data.
(5) If the master CPU has more data to send, it should check that MWMF is cleared to "0," then
repeat the above procedure from step (1). If MWMF is still set to "1," that indicates that the
H8/300 CPU has not read all the data sent previously.
11.3.2 Data Transfer from H8/300 CPU to Master CPU
The following procedure should be used when the H8/300 CPU sends data to the master CPU via
the dual-port RAM:
(1) The H8/300 CPU writes the first byte of data in PCDR0. If the dual-port RAM is not
currently in the master write mode, SWMF is set to "1," placing it in the slave write mode and
preventing the master CPU from writing in PCDR1 to PCDR14.
(2) The H8/300 CPU reads the PCCSR and checks SWMF. If SWMF is set to “1,” the H8/300
CPU may continue writing in PCDR1 to PCDR14. If SWMF is cleared to "0," the dual-port
RAM is presumably in the master write mode.
(3) The H8/300 CPU writes data in PCDR1 to PCDR13 as required, then writes the last byte in
PCDR14. This sets the slave write end flag (SWEF) to “1.” If the EAKAR bit is set to “1,”
the RDY signal goes Low to notify the master CPU that the H8/300 CPU has finished writing.
(4) After the H8/300 CPU has finished writing data, the master CPU first reads PCDR14. This
clears the slave write end flag. Then the master CPU reads data from PCDR1 to PCDR13 as
required. Finally, the master CPU reads PCDR0. This clears the SWMF bit, so the dual-port
RAM is no longer in the slave write mode. It also sets the master read end flag (MREF). If
EMRI is set to “1,” a master read end interrupt is requested to notify the H8/300 CPU that the
master CPU has finished reading the data.
(5) If the H8/300 CPU has more data to send, it should check that SWMF is cleared to "0," then
repeat the above procedure from step (1). If SWMF is still set to "1," that indicates that the
master CPU has not read all the data sent previously.
235
Slave receive mode
H8/300 CPU
Read
PCCSR
Read
PCDR0
Read
PCDR14
Read
PCDR14
Read
PCDR0
Write
PCDR14
Write
PCDR0 PCCSR
Read
Write
PCDR14
Write
PCDR0
Master CPU
SWMF
MWMF
MREF
MWEF
SWEF
(RDY)
Slave transmit mode
Write
H8/300 CPU
Read
PCCSR
Read
PCCSR PCDR14
Write
Write
PCDR14
Write
PCDR0
PCDR0
Read
PCDR14
Read
PCDR0
Read
Read
PCDR14
Master CPU
SWMF
PCDR0
MWMF
MREF
MWEF
SWEF
(RDY)
Figure 11-3. Dual-Port RAM Timing Chart
11.4 Master-Slave Interconnections
Figure 11-4 shows an example of the master-slave interconnections when the master chip is an
H8/532.
A15 – A4
A3 – A0
D7 – D0
Decoder
CS
Address bus
RS3 – RS0
DDB7 –DDB0
Data bus
WR
RD
WE
OE
IRQ
RDY
H8/532
H8/330
Note:An external pull-up resistor should be connected to the RDY output pin.
Figure 11-4. Interconnection to H8/532 (Example)
237
Section 12. RAM
12.1 Overview
The H8/330 includes 512 bytes of on-chip static RAM, connected to the CPU by a 16-bit data bus.
Both byte and word access to the on-chip RAM are performed in two states, enabling rapid data
transfer and instruction execution.
The on-chip RAM is assigned to addresses H’FD80 to H’FF7F in the chip’s address space. The
RAME bit in the system control register (SYSCR) can enable or disable the on-chip RAM,
permitting these addresses to be allocated to external memory instead, if so desired.
12.2 Block Diagram
Figure 12-1 is a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Address
H'FD80
H'FD82
H'FD80
H'FD82
H'FD81
H'FD83
On-chip RAM
H'FF7E
H'FF7E
H'FF7F
Even address
Odd address
Figure 12-1. Block Diagram of On-Chip RAM
12.3 RAM Enable Bit (RAME)
The on-chip RAM is enabled or disabled by the RAME (RAM Enable) bit in the system control
register (SYSCR). Table 12-1 lists information about the system control register.
239
Table 12-1. System Control Register
Name
Abbreviation R/W
Initial value Address
System control register
SYSCR
R/W
H’09
H’FFC4
Bit
7
SSBY
0
6
5
STS1
0
4
STS0
0
3
—
1
2
1
0
STS2
NMIEG DPME RAME
Initial value
Read/Write
0
0
0
1
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
The only bit in the system control register that concerns the on-chip RAM is the RAME bit. See
section 2.4.2, "System Control Register" for the other bits.
Bit 0 – RAM Enable (RAME): This bit enables or disables the on-chip RAM.
The RAME bit is initialized to “1” on the rising edge of the RES signal, so a reset enables the on-
chip RAM. The RAME bit is not initialized in the software standby mode.
Bit 7
RAME
Description
0
1
On-chip RAM is disabled.
On-chip RAM is enabled.
(Initial value)
12.4 Operation
12.4.1 Expanded Modes (Modes 1 and 2)
If the RAME bit is set to “1,” accesses to addresses H’FD80 to H’FF7F are directed to the on-chip
RAM. If the RAME bit is cleared to “0,” accesses to addresses H’FD80 to H’FF7F are directed to
the external data bus.
12.4.2 Single-Chip Mode (Mode 3)
If the RAME bit is set to “1,” accesses to addresses H’FD80 to H’FF7F are directed to the on-chip
RAM.
If the RAME bit is cleared to “0,” the on-chip RAM data cannot be accessed. Attempted write
access has no effect. Attempted read access always results in H’FF data being read.
240
Section 13. ROM
13.1 Overview
The H8/330 includes 16K bytes of high-speed, on-chip ROM. The on-chip ROM is connected to
the CPU via a 16-bit data bus. Both byte data and word data are accessed in two states, enabling
rapid data transfer and instruction fetching.
The H8/330 is available in two versions: one with electrically programmable ROM (PROM); the
other with masked ROM. The PROM version has a PROM mode in which the chip can be
programmed with a standard PROM writer.
The on-chip ROM is enabled or disabled depending on the MCU operating mode, which is
determined by the inputs at the mode pins (MD1 and MD0) when the chip comes out of the reset
state. See table 13-1.
Table 13-1. On-Chip ROM Usage in Each MCU Mode
Mode pins
Mode
MD1
MD0
On-chip ROM
Disabled (external addresses)
Enabled
Mode 1 (expanded mode)
Mode 2 (expanded mode)
Mode 3 (single-chip mode)
0
1
1
1
0
1
Enabled
241
13.1.1 Block Diagram
Figure 13-1 is a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000
H'0002
H'0001
H'0003
On-chip ROM
H'3FFE
H'3FFF
Even addresses Odd addresses
Figure 13-1. Block Diagram of On-Chip ROM
13.2 PROM Mode
13.2.1 PROM Mode Setup
In the PROM mode of the PROM version of the H8/330, the usual microcomputer functions are
halted to allow the on-chip PROM to be programmed. The programming method is the same as for
the HN27C256.
To select the PROM mode, apply the signal inputs listed in Table 13-2.
Table 13-2. Selection of PROM Mode
Pin
Input
Low
Low
Low
High
Mode pin MD1
Mode pin MD0
STBY pin
Pins P80 and P81
242
13.2.2 Socket Adapter Pin Assignments and Memory Map
The H8/330 can be programmed with a general-purpose PROM writer. Since the H8/330 package
has 80 or 84 pins instead of 28, a socket adapter is necessary. Table 13-3 lists recommended socket
adapters. Figure 13-2 shows the socket adapter pin assignments by giving the correspondence
between H8/330 pins and HN27C256 pin functions.
Figure 13-3 shows a memory map in the PROM mode. Since the H8/330 has only 16K bytes of
on-chip PROM, the address range should be specified as H’0000 to H’3FFF. H’FF data should be
specified for unused address areas.
It is important to limit the program address range to H'0000 to H'3FFF and specify H'FF data for
H'4000 and higher addresses. If data (other than H’FF) are written by mistake in addresses equal to
or greater than H’4000, it may become impossible to program or verify the PROM data. With a
windowed package, it is possible to erase the data and reprogram, but this cannot be done with a
plastic package, so particular care is required.
Table 13-3. Recommended Socket Adapters
Package
Recommended Socket Adapter
HS338ESC01H
84-Pin PLCC
84-Pin windowed LCC
80-Pin QFP
HS338ESG01H
HS338ESH01H
243
H8/330
CG-84,
EPROM Socket
Pin HN27C256H
FP-80A
1
Pin
CP-84
12
RES
VPP
1
6
17
79
80
81
82
83
84
1
NMI
P30
P31
P32
P33
P34
P35
P36
P37
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P80
P81
AVCC
VCC
VCC
MD0
MD1
STBY
AVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
EA9
EO0
EO1
EO2
EO3
EO4
EO5
EO6
EO7
EA0
EA1
EA2
EA3
EA4
EA5
EA6
EA7
EA8
OE
24
11
12
13
15
16
17
18
19
10
9
65
66
67
68
69
70
71
72
64
63
62
61
60
59
58
57
55
54
53
52
51
50
49
48
74
75
29
8
3
78
77
76
75
74
73
72
71
69
68
67
66
65
63
62
61
5
8
7
6
5
4
3
25
22
21
23
2
EA10
EA11
EA12
EA13
EA14
CE
26
27
20
28
VCC
6
42
19
60
16
15
18
51
2
47
5
VSS
14
4
7
38
12
56
73
–
4
Notation
23
24
41
64
70
VPP:
Programming voltage (12.5 V)
EO7 to EO0: Data input/output
EA14 to EA0: Address input
–
–
OE:
CE:
Output enable
Chip enable
–
Note: All pins not listed in this figure should be left open.
Figure 13-2. Socket Adapter Pin Assignments
244
Address in MCU mode
H'0000
Address in PROM mode
H'0000
On-chip
PROM
H'3FFF
H'3FFF
If this area is read in PROM mode,
the output data are H'FF.
"1" output *
*
H'7FFF
Figure 13-3. Memory Map in PROM Mode
13.3 Programming
The write, verify, inhibited, and read sub-modes of the PROM mode are selected as shown in Table
13-4.
Table 13-4. Selection of Sub-Modes in PROM Mode
Pins
Sub-mode
Write
CE
OE
VPP
VPP
VPP
VPP
VCC
VCC
VCC
VCC
EO7 – EO0
Data input
Data output
EA14 – EA0
Address input
Address input
Low
High
High
Low
High
Verify
Programming inhibited High
High-impedance Address input
Note: The VPP and VCC pins must be held at the VPP and VCC voltage levels.
The H8/330 PROM uses the same, standard read/write specifications as the HN27C256 and
HN27256.
13.3.1 Writing and Verifying
An efficient, high-speed programming procedure can be used to write and verify PROM data. This
procedure writes data quickly without subjecting the chip to voltage stress and without sacrificing
data reliability. It leaves the data H’FF written in unused addresses.
245
Figure 13-4 shows the basic high-speed programming flowchart.
Tables 13-5 and 13-6 list the electrical characteristics of the chip in the PROM mode. Figure 13-5
shows a write/verify timing chart.
START
Set program/verify mode
Vcc = 6.0V ±0.25V, Vpp = 12.5V ±0.5V
Address = 0
n = 0
n + 1 → n
Write time t
= 1 ms ±5%
PW
Y
N
N
n < 25
Verify OK?
Y
Write t
= 3n ms
OPW
→
Address + 1
Address
N
Last address?
Y
Set read mode
Vcc = 5.0V ±0.5V, Vpp = Vcc
N
Error
All addresses read?
Y
END
Figure 13-4. High-Speed Programming Flowchart
246
Table 13-5. DC Characteristics (When VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, VSS = 0V,
Ta = 25˚C ±5˚C)
Measurement
Item
Symbol min
typ max
Unit conditions
Input High voltage EO7 – EO0, VIH
2.4
— VCC + 0.3 V
EA14 – EA10,
EA8 – EA0,
OE, CE
EA9
VCC × 0.7 — VCC + 0.3 V
Input Low voltage
EO7 – EO0,
EA14 – EA0,
OE, CE
VIL
– 0.3
—
0.8
V
Output High voltage EO7 – EO0
Output Low voltage EO7 – EO0
VOH
VOL
2.4
—
—
—
—
—
—
0.45
2
V
IOH = –200µA
IOL = 1.6mA
Vin = 5.25V/
0.5V
V
Input leakage
current
EO7 – EO0, |ILI|
EA14 – EA0,
OE, CE
µA
Vcc current
Vpp current
ICC
—
—
—
—
40
40
mA
mA
Ipp
Table 13-6. AC Characteristics
(When VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, Ta = 25˚C ±5˚C)
Measurement
Item
Symbol min
typ
—
—
—
—
—
—
—
1.0
max
—
Unit
µs
conditions
Address setup time
OE setup time
tAS
2
See Figure 13-5*
tOES
tDS
2
—
µs
Data setup time
Address hold time
Data hold time
2
—
µs
tAH
tDH
tDF
tVPS
tPW
0
—
µs
2
—
µs
Data output disable time
Vpp setup time
Program pulse width
—
2
130
—
ns
µs
0.95
1.05
ms
* Input pulse level: 0.8V to 2.2V
<
Input rise/fall time 20ns
=
Timing reference levels: input—1.0V, 2.0V; output—0.8V, 2.0V
247
Table 13-6. AC Characteristics (cont.)
(When VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V, Ta = 25˚C ±5˚C)
Measurement
Item
Symbol min
typ
max
Unit
conditions
OE pulse width for
overwrite-programming
Vcc setup time
tOPW
2.85
—
78.75 ms
See Figure 13-5*
tVCS
tOE
2
0
—
—
—
µs
ns
Data output delay time
500
* Input pulse level: 0.8V to 2.2V
<
Input rise/fall time 20ns
=
Timing reference levels: input—1.0V, 2.0V; output—0.8V, 2.0V
Write
Verify
Address
tAS
tAH
tDF
Data
Input data
Output data
tDS
tDH
VPP
VCC
VPP
tVPS
VCC
VCC
tVCS
GND
CE
tPW
tOES
tOE
OE
tOPW
Figure 13-5. PROM Write/Verify Timing
248
13.3.2 Notes on Writing
(1) Write with the specified voltages and timing. The programming voltage (Vpp) is 12.5V.
Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be
particularly careful about the PROM writer’s overshoot characteristics.
If the PROM writer is set to Intel specifications or Hitachi HN27256 or HN27C256 specifications,
VPP will be 12.5V.
(2) Before writing data, check that the socket adapter and chip are correctly mounted in the
PROM writer. Overcurrent damage to the chip can result if the index marks on the PROM writer,
socket adapter, and chip are not correctly aligned.
(3) Don’t touch the socket adapter or chip while writing. Touching either of these can cause
contact faults and write errors.
13.3.3 Reliability of Written Data
An effective way to assure the data holding characteristics of the programmed chips is to bake them
at 150˚C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 13-6 shows the recommended screening procedure.
Write program
Bake with power off
+ 8 Hr *
– 0 Hr
150°± 10°C, 48 Hr
Read and check program
Vcc = 4.5V and 5.5V
Install
Note: Baking time should be measured from the point when the baking oven reaches 150°C.
Figure 13-6. Recommended Screening Procedure
249
If a series of write errors occurs while the same PROM writer is in use, stop programming and
check the PROM writer and socket adapter for defects, using a microcomputer chip with a
windowed package and on-chip EPROM.
Please inform Hitachi of any abnormal conditions noted during programming or in screening of
program data after high-temperature baking.
13.3.4 Erasing of Data
The windowed package enables data to be erased by illuminating the window with ultraviolet light.
Table 13-7 lists the erasing conditions.
Table 13-7. Erasing Conditions
Item
Value
Ultraviolet wavelength
Minimum illumination
253.7 nm
15W·s/cm2
The conditions in Table 13-7 can be satisfied by placing a 12000µW/cm2 ultraviolet lamp 2 or 3
centimeters directly above the chip and leaving it on for about 20 minutes.
13.4 Handling of Windowed Packages
(1) Glass Erasing Window: Rubbing the glass erasing window of a windowed package with a
plastic material or touching it with an electrically charged object can create a static charge on the
window surface which may cause the chip to malfunction.
If the erasing window becomes charged, the charge can be neutralized by a short exposure to
ultraviolet light. This returns the chip to its normal condition, but it also reduces the charge stored
in the floating gates of the PROM, so it is recommended that the chip be reprogrammed afterward.
Accumulation of static charge on the window surface can be prevented by the following
precautions:
① When handling the package, ground yourself. Don’t wear gloves. Avoid other possible sources
of static charge.
② Avoid friction between the glass window and plastic or other materials that tend to accumulate
static charge.
250
➂ Be careful when using cooling sprays, since they may have a slight ion content.
④ Cover the window with an ultraviolet-shield label, preferably a label including a conductive
material. Besides protecting the PROM contents from ultraviolet light, the label protects the
chip by distributing static charge uniformly.
(2) Handling after Programming: Fluorescent light and sunlight contain small amounts of
ultraviolet, so prolonged exposure to these types of light can cause programmed data to invert. In
addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip
malfunction. It is recommended that after programming the chip, you cover the erasing window
with a light-proof label (such as an ultraviolet-shield label).
(3) Note on 84-Pin LCC Package: A socket should always be used when the 84-pin LCC
package is mounted on a printed-circuit board. Table 13.8 lists the recommended socket.
Table 13-8. Recommended Socket for Mounting 84-Pin LCC Package
Manufacturer
Code
Sumitomo 3-M
284-1273-00-1102J
251
Section 14. Power-Down State
14.1 Overview
The H8/330 has a power-down state that greatly reduces power consumption by stopping some or
all of the chip functions. The power-down state includes three modes:
(1) Sleep mode – a software-triggered mode in which the CPU halts but the rest of the chip
remains active
(2) Software standby mode – a software-triggered mode in which the entire chip is inactive
(3) Hardware standby mode – a hardware-triggered mode in which the entire chip is inactive
Table 14-1 lists the conditions for entering and leaving the power-down modes. It also indicates the
status of the CPU, on-chip supporting modules, etc. in each power-down mode.
Table 14-1. Power-Down State
Entering
procedure
Execute
CPU Sup.
I/O
Exiting
Mode
Sleep
mode
Clock CPU Reg’s. Mod.* RAM ports methods
Run
Halt
Halt
Halt
Held
Held
Run
Held
Held
Held
Held
• Interrupt
• RES
SLEEP
instruction
Set SSBY bit
in SYSCR to
“1,” then
• STBY
• NMI
Soft-
Halt
and
ware
• IRQ0 – IRQ2
• STBY
• RES
standby
mode
initial-
ized
execute SLEEP
instruction
Set STBY
pin to Low
level
Hard-
ware
Halt
Halt
Not
Halt
and
Held
High
impe-
dance
state
• STBY High,
then RES
held
standby
mode
initialized
Low → High
Notes
1. SYSCR: System control register
2. SSBY: Software standby bit
3. On-chip supporting modules, including the dual-port RAM.
253
14.2 System Control Register: Power-Down Control Bits
Bits 7 to 4 of the system control register (SYSCR) concern the power-down state. Specifically,
they concern the software standby mode.
Table 14-2 lists the attributes of the system control register.
Table 14-2. System Control Register
Name
Abbreviation R/W
Initial value Address
System control register
SYSCR
R/W
H’09
H’FFC4
Bit
7
SSBY
0
6
5
STS1
0
4
STS0
0
3
—
1
2
1
0
STS2
NMIEG DPME RAME
Initial value
Read/Write
0
0
0
1
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
Bit 7 – Software Standby (SSBY): This bit enables or disables the transition to the software
standby mode.
On recovery from the software standby mode by an external interrupt, SSBY remains set to "1." To
clear this bit, software must write a "0."
Bit 7
SSBY
Description
0
1
The SLEEP instruction causes a transition to the sleep mode.
The SLEEP instruction causes a transition to the software
standby mode.
(Initial value)
Bits 6 to 4 – Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from the software standby mode by an external interrupt. During the
selected time, the clock oscillator runs but clock pulses are not supplied to the CPU or the on-chip
supporting modules.
254
Bit 6
Bit 5
Bit 4
STS2
STS1
STS0
Description
0
0
0
0
1
0
0
Settling time = 8192 states
Settling time = 16384 states
Settling time = 32768 states
Settling time = 65536 states
Settling time = 131072 states
(Initial value)
0
1
1
0
1
1
—
—
When the H8/330's on-chip clock generator is used, the STS bits should be set to allow a settling
time of at least 10ms. Table 14-3 lists the settling times selected by these bits at several clock
frequencies and indicates the recommended settings.
When the H8/330 is externally clocked, the STS bits can be set to any value. The minimum value
(STS2 = STS1 = STS0 = "0") is recommended.
Table 14-3. Times Set by Standby Timer Select Bits (Unit: ms)
Settling
time
System clock frequency (MHz)
STS2 STS1 STS0
(states) 10
8
6
4
2
1
0.5
0
0
0
0
1
0
0
8192
0.8
1.0
2.0
4.1
8.2
16.4
1.3
2.7
5.5
10.9
21.8
2.0
4.1
8.2
16.4
32.8
4.1
8.2
16.4
32.8
65.5
8.2
16.4
32.8
65.5
131.1
0
1
16384 1.6
32768 3.3
65536 6.6
131072 13.1
16.4
32.8
65.5
1
0
1
1
—
—
131.1 262.1
Notes:
1. All times are in milliseconds.
2. Recommended values are printed in boldface.
14.3 Sleep Mode
The sleep mode provides an effective way to conserve power while the CPU is waiting for an
external interrupt or an interrupt from an on-chip supporting module.
255
14.3.1 Transition to Sleep Mode
When the SSBY bit in the system control register is cleared to “0,” execution of the SLEEP
instruction causes a transition from the program execution state to the sleep mode. After executing
the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged.
The on-chip supporting modules continue to operate normally.
14.3.2 Exit from Sleep Mode
The chip wakes up from the sleep mode when it receives an internal or external interrupt request, or
a Low input at the RES or STBY pin.
(1) Wake-Up by Interrupt: An interrupt releases the sleep mode and starts the CPU’s interrupt-
handling sequence.
If an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable
bit in the module’s control register, the interrupt cannot be requested, so it cannot wake the chip up.
Similarly, the CPU cannot be awoken by an interrupt other than NMI if the I (interrupt mask) bit in
the CCR (condition code register) is set when the SLEEP instruction is executed.
(2) Wake-Up by RES pin: When the RES pin goes Low, the chip exits from the sleep mode to
the reset state.
(3) Wake-Up by STBY pin: When the STBY pin goes Low, the chip exits from the sleep mode to
the hardware standby mode.
14.4 Software Standby Mode
In the software standby mode, the system clock stops and chip functions halt, including both CPU
functions and the functions of the on-chip supporting modules. Power consumption is reduced to
an extremely low level. The on-chip supporting modules and their registers are reset to their initial
states, but as long as a minimum necessary voltage supply is maintained (at least 2V), the contents
of the CPU registers and on-chip RAM remain unchanged.
256
14.4.1 Transition to Software Standby Mode
To enter the software standby mode, set the standby bit (SSBY) in the system control register
(SYSCR) to “1,” then execute the SLEEP instruction.
14.4.2 Exit from Software Standby Mode
The chip can be brought out of the software standby mode by an input at one of six pins: NMI,
IRQ0, IRQ1, IRQ2, RES, or STBY.
(1) Recovery by External Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 request signal is
received, the clock oscillator begins operating. After the waiting time set in the system control
register (bits STS2 to STS0), clock pulses are supplied to the CPU and on-chip supporting modules.
The CPU executes the interrupt-handling sequence for the requested interrupt, then returns to the
instruction after the SLEEP instruction. The SSBY bit is not cleared.
See Section 14.2, “System Control Register: Power-Down Control Bits” for information about the
STS bits.
Interrupts IRQ3 to IRQ7 should be disabled before entry to the software standby mode. Clear
IRQ3E to IRQ7E to "0" in the interrupt enable register (IER).
(2) Recovery by RES Pin: When the RES pin goes Low, the clock oscillator starts. Next, when
the RES pin goes High, the CPU begins executing the reset sequence. The SSBY bit is cleared to
“0.”
The RES pin must be held Low long enough for the clock to stabilize.
(3) Recovery by STBY Pin: When the STBY pin goes Low, the chip exits from the software
standby mode to the hardware standby mode.
14.4.3 Sample Application of Software Standby Mode
In this example the H8/330 enters the software standby mode when NMI goes Low and exits when
NMI goes High, as shown in Figure 14-1.
257
The NMI edge bit (NMIEG) in the system control register is originally cleared to "0," selecting the
falling edge. When NMI goes Low, the NMI interrupt handling routine sets NMIEG to "1," sets
SSBY to "1" (selecting the rising edge), then executes the SLEEP instruction. The H8/330 enters
the software standby mode. It recovers from the software standby mode on the next rising edge of
NMI.
Clock
generator
Ø
NMI
NMIEG
SSBY
Settling time
Software standby mode
(power-down state)
NMI interrupt handler
NMI interrupt handler
NMIEG = "1"
SSBY = "1"
SLEEP
Figure 14-1. Software Standby Mode (when) NMI Timing
14.4.4 Application Notes
(1) The I/O ports retain their current states in the software standby mode. If a port is in the High
output state, the current dissipation caused by the High output current is not reduced.
(2) If the software standby mode is entered under either condition ①or condition ➁ below, current
dissipation is greater than in normal standby mode.
① In single-chip mode (mode 3): if software standby mode is entered by executing an
instruction stored in on-chip ROM, after even one instruction not stored in on-chip ROM
has been fetched (e.g. from on-chip RAM).
➁ In expanded mode with on-chip ROM enabled (mode 2): if software standby mode is
entered by executing an instruction stored in on-chip ROM, after even one instruction not
stored in on-chip ROM has been fetched (e.g. from external memory or on-chip RAM).
258
Note that the H8/300 CPU pre-fetches instructions. If an instruction stored in the last two bytes
of on-chip ROM is executed (at addresses H'3FFE and H'3FFF in the H8/330), the contents of
the next two bytes (H'4000 and H'4001), which are not in on-chip ROM, will be fetched as the
next instruction.
This problem does not occur in expanded mode when on-chip ROM is disabled (mode 1). In
hardware standby mode there is no such additional current dissipation, regardless of the
conditions when hardware standby mode is entered.
14.5 Hardware Standby Mode
14.5.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters the hardware standby mode whenever the STBY pin
goes Low.
The hardware standby mode reduces power consumption drastically by halting the CPU, stopping
all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance
state. The registers of the on-chip supporting modules are reset to their initial values. Only the on-
chip RAM is held unchanged, provided the minimum necessary voltage supply is maintained (at
least 2V).
Notes:
1. The RAME bit in the system control register should be cleared to “0” before the STBY pin
goes Low, to disable the on-chip RAM during the hardware standby mode.
2. Do not change the inputs at the mode pins (MD1, MD0) during hardware standby mode. Be
particularly careful not to let both mode pins go Low in hardware standby mode, since that
places the chip in PROM mode and increases current dissipation.
14.5.2 Recovery from Hardware Standby Mode
Recovery from the hardware standby mode requires inputs at both the STBY and RES pins.
When the STBY pin goes High, the clock oscillator begins running. The RES pin should be Low at
this time and should be held Low long enough for the clock to stabilize. When the RES pin
changes from Low to High, the reset sequence is executed and the chip returns to the program
execution state.
259
14.5.3 Timing Relationships
Figure 14-2 shows the timing relationships in the hardware standby mode.
In the sequence shown, first RES goes Low, then STBY goes Low, at which point the H8/330
enters the hardware standby mode. To recover, first STBY goes High, then after the clock settling
time, RES goes High.
Clock pulse
generator
RES
STBY
Clock settling
time
Result
Figure 14-2. Hardware Standby Mode Timing
260
Section 15. E-Clock Interface
15.1 Overview
For interfacing to peripheral devices that require it, the H8/330 can generate an E clock output.
Special instructions (MOVTPE, MOVFPE) perform data transfers synchronized with the E clock.
The E clock is created by dividing the system clock (Ø) by 8. The E clock is output at the P80 pin
when the P80DDR bit in the port 8 data direction register (P8DDR) is set to “1.” It is output only in
the expanded modes (mode 1 and mode 2); it is not output in the single-chip mode. Output begins
immediately after a reset.
When the CPU executes an instruction that synchronizes with the E clock, the address strobe (AS),
the address on the address bus, and the IOS signal are output as usual, but the RD and WR signal
lines and the data bus do not become active until the falling edge of the E clock is detected. The
length of the access cycle for an instruction synchronized with the E clock accordingly varies from
9 to 16 states. Figures 15-1 and 15-2 show the timing in the cases of maximum and minimum
synchronization delay.
It is not possible to insert wait states (Tw) during the execution of an instruction synchronized with
the E clock by input at the WAIT pin.
261
Figure 15-1. Execution Cycle of Instruction Synchronized with E Clock in
Expanded Modes (Maximum Synchronization Delay)
Figure 15-2. Execution Cycle of Instruction Synchronized with E Clock in Expanded
Modes (Minimum Synchronization Delay)
263
Section 16. Clock Pulse Generator
16.1 Overview
The H8/330 chip has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a
system (Ø) clock divider, an E clock divider, and a prescaler. The prescaler generates clock signals
for the on-chip supporting modules.
16.1.1 Block Diagram
CPG
Prescaler
XTAL
EXTAL
Oscillator
circuit
Divider
÷ 2
Divider
÷ 8
Ø
E
Ø/2 to Ø/4096
Figure 16-1. Block Diagram of Clock Pulse Generator
16.2 Oscillator Circuit
If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit
generates a clock signal for the system clock divider. Alternatively, an external clock signal can be
applied to the EXTAL pin.
(1) Connecting an External Crystal
① Circuit Configuration: An external crystal can be connected as in the example in Figure 16-2.
An AT-cut parallel resonating crystal should be used.
265
CL1
CL2
EXTAL
XTAL
CL1 = CL2 = 10 to 22pF
Figure 16-2. Connection of Crystal Oscillator (Example)
② Crystal Oscillator: The external crystal should have the characteristics listed in Table 16-1.
Table 16-1. External Crystal Parameters
Frequency (MHz)
Rs max (Ω)
C0 (pF)
2
4
8
12
40
16
30
20
20
500
120
60
7 pF max
CL
L
RS
XTAL
EXTAL
C0
AT-cut parallel resonating crystal
Figure 16-3. Equivalent Circuit of External Crystal
➂ Note on Board Design: When an external crystal is connected, other signal lines should be
kept away from the crystal circuit to prevent induction from interfering with correct oscillation.
See Figure 16-4. The crystal and its load capacitors should be placed as close as possible to the
XTAL and EXTAL pins.
266
Not allowed
Signal A
Signal B
H8/330
CL2
XTAL
EXTAL
CL1
Figure 16-4. Notes on Board Design around External Crystal
(2) Input of External Clock Signal
① Circuit Configuration: An external clock signal can be input at the EXTAL pin. The reverse-
phase clock signal should be input at the XTAL pin, as shown in the example in Figure 16-5.
EXTAL
External clock input
74HC04
XTAL
Figure 16-5. External Clock Input (Example)
② External Clock Input
Frequency
Duty factor
Double the system clock (Ø) frequency
45% to 55%
267
16.3 System Clock Divider
The system clock divider divides the crystal oscillator or external clock frequency by 2 to create the
system clock (Ø).
An E clock signal is created by dividing the system clock by 8.
Figure 16-6 shows the phase relationship of the E clock to the system clock.
Ø
E
Figure 16-6. Phase Relationship of System Clock and E Clock
268
Section 17. Electrical Specifications
17.1 Absolute Maximum Ratings
Table 17-1 lists the absolute maximum ratings.
Table 17-1. Absolute Maximum Ratings
Item
Symbol
VCC
Rating
Unit
V
Supply voltage
Programming voltage
Input voltage
–0.3 to +7.0
–0.3 to +13.5
VPP
V
Ports 1 – 6, 8, 9
Port 7
Vin
–0.3 to VCC + 0.3
V
V
V
V
˚C
Vin
–0.3 to AVCC + 0.3
–0.3 to +7.0
Analog supply voltage
Analog input voltage
Operating temperature
AVCC
VAN
Topr
–0.3 to AVCC + 0.3
Regular specifications: –20 to +75
Wide-range specifications: – 40 to +85 ˚C
–55 to +125 ˚C
Storage temperature
Tstg
Note: The input pins have protection circuits that guard against high static voltages and electric
fields, but these high input-impedance circuits should never receive overvoltages exceeding
the absolute maximum ratings shown in table 17-1.
17.2 Electrical Characteristics
17.2.1 DC Characteristics
Table 17-2 lists the DC characteristics of the H8/330.
269
Table 17-2. DC Characteristics
Conditions: VCC = 5.0V ±10%*, AVCC = 5.0V ±10%, VSS = AVSS = 0V,
Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications)
Measurement
Item
Symbol min
typ max
Unit conditions
-
Schmitt trigger
input voltage
(1)
P67 – P62, P60, VT
1.0
–
–
–
V
V
V
+
P86 – P80,
VT
–
–
3.5
–
-
+
P97, P94 – P90 VT –VT 0.4
Input High voltage RES, STBY,
VIH
VCC – 0.7 –
VCC + 0.3 V
(2)
MD1, MD0
EXTAL, NMI
P77 – P70
VCC × 0.7 –
VCC + 0.3 V
AVCC + 0.3 V
VCC + 0.3 V
2.2
2.2
–
–
Input High voltage Input pins
other than (1)
VIH
and (2)
Input Low voltage RES, STBY
VIL
VIL
–0.3
–0.3
–
–
0.5
0.8
V
V
(3)
Input Low voltage Input pins
other than (1)
and (3)
MD1, MD0
Output High
voltage
All output pins VOH
VCC – 0.5 –
–
V
IOH = –200µA
IOH = –1.0mA
IOL = 1.6mA
IOL = 10.0mA
Vin = 0.5V to
VCC – 0.5V
3.5
–
–
–
–
–
–
–
V
Output Low
voltage
All output pins VOL
Ports 1 and 2
0.4
1.0
10.0
1.0
V
–
V
Input leakage
current
RES
|Iin|
–
µA
µA
STBY, NMI,
MD1, MD0
P77 – P70
–
–
–
–
–
1.0
1.0
250
µA
µA
µA
Vin = 0.5V to
AVCC – 0.5V
Vin = 0.5V to
VCC – 0.5V
Vin = 0V
Leakage current
Ports 1, 2, 3
|ITSI|
–
in 3-state (off state) 4, 5, 6, 8, 9
Input pull-up
MOS current
Ports 1, 2, 3
4, 5, 6, 8, 9
-Ip
30
* Connect AVCC to the power supply (+5V) even when the A/D converter is not used.
270
Table 17-2. DC Characteristics (cont.)
Conditions: VCC = AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ta = –20 to 75˚C (regular specifications)
Ta = –40 to 85˚C (wide-range specifications)
Measurement
Item
Symbol min
typ max
Unit conditions
Input capacitance RES (VPP)
NMI
Cin
–
–
–
–
–
–
60
30
15
pF
pF
pF
Vin = 0V
All input pins
except RES
f = 1MHz
Ta = 25˚C
and NMI
Current
Normal
ICC
–
–
–
–
–
–
–
–
12 25
16 30
20 40
mA
mA
mA
mA
mA
mA
µA
mA
f = 6MHz
f = 8MHz
f = 10MHz
f = 6MHz
f = 8MHz
f = 10MHz
*1
dissipation
operation
Sleep mode
8
15
10 20
12 25
0.01 5.0
0.6 1.5
*2
Standby modes
During A/D
conversion
Waiting
Analog supply
current
AICC
–
0.01 5.0
µA
V
RAM standby
voltage
VRAM
2.0
–
–
*1 Current dissipation values assume that VIH min. = VCC – 0.5V, VIL max. = 0.5V, all output pins
are in the no-load state, and all MOS input pull-ups are off.
*2 For these values it is assumed that VRAM ≤ VCC < 4.5V and VIH min. = VCC × 0.9, VIL max. =
0.3V.
271
Table 17-3. Allowable Output Current Sink Values
Conditions: VCC = AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ta = –20 to 75˚C (regular specifications)
Ta = –40 to 85˚C (wide-range specifications)
Item
Symbol
min
–
typ
–
max
10
Unit
mA
mA
mA
mA
mA
Allowable output Low
current sink (per pin)
Allowable output Low
current sink (total)
Ports 1 and 2
IOL
Other output pins
Ports 1 and 2, total
All output pins
–
–
2.0
80
ΣIOL
–IOH
–
–
–
–
120
2.0
Allowable output High All output pins
current sink (per pin)
–
–
Allowable output High Total of all output
current sink (total)
Σ–IOH
–
–
40
mA
Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current
sink values in table 17-3. In particular, when driving a Darlington transistor pair or LED directly,
be sure to insert a current-limiting resistor in the output path. See figures 17-1 and 17-2.
H8/330
2 kΩ
Port
Darlington
pair
Figure 17-1. Example of Circuit for Driving a Darlington Pair
H8/330
Vcc
600 Ω
Port 1 or 2
LED
Figure 17-2. Example of Circuit for Driving a LED
272
17.2.2 AC Characteristics
The AC characteristics of the H8/330 chip are listed in three tables. Bus timing parameters are
given in table 17-4, control signal timing parameters in table 17-5, and timing parameters of the on-
chip supporting modules in table 17-6.
Table 17-4. Bus Timing
Conditions: VCC = 5.0V ±10%, Ø = 0.5 to 10MHz, VSS = 0V,
Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications)
Measurement
Measurement 6MHz
8MHz
10MHz
Item
Symbol conditions
min max min max min max Unit
Clock cycle time
Clock pulse width Low
Clock pulse width High
Clock rise time
tcyc
tCL
tCH
tCr
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-4
Fig. 17-5
Fig. 17-5
Fig. 17-6
Fig. 17-6
Fig. 17-6
Fig. 17-6
166.7 2000 125 2000 100 2000 ns
65
65
–
–
45
45
–
–
35
35
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
15
15
70
–
15
15
60
–
15
15
55
–
Clock fall time
tCf
–
–
–
Address delay time
Address hold time
tAD
tAH
–
–
–
30
–
25
–
20
–
Address strobe delay time tASD
70
70
70
–
60
60
60
–
50
50
50
–
Write strobe delay time
Strobe delay time
tWSD
tSD
–
–
–
–
–
–
Write strobe pulse width tWSW
200
25
105
70
0
150
20
80
55
0
120
15
65
50
0
Address setup time 1
Address setup time 2
Read data setup time
Read data hold time
Write data delay time
Read data access time
Write data setup time
Write data hold time
Wait setup time
tAS1
tAS2
tRDS
tRDH
tWDD
tACC
tWDS
tWDH
tWTS
tWTH
tED
–
–
–
–
–
–
–
–
–
–
–
–
–
70
270
–
–
60
190
–
–
60
–
–
–
160 ns
30
30
40
10
–
15
25
40
10
–
10
20
40
10
–
–
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
Wait hold time
–
–
–
E clock delay time
E clock rise time
20
15
15
–
20
15
15
–
20
15
15
–
tEr
–
–
–
E clock fall time
tEf
–
–
–
Read data hold time
(for E clock)
tRDHE
0
0
0
Write data hold time
(for E clock)
tWDHE
Fig. 17-6
50
–
40
–
30
–
ns
273
Table 17-5. Control Signal Timing
Conditions: VCC = 5.0V ±10%, Ø = 0.5 to 10MHz, VSS = 0V,
Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications)
Measurement
Measurement 6MHz
8MHz
10MHz
Item
Symbol conditions min max min max min max Unit
RES setup time
tRESS
tRESW
tMDS
Fig. 17-7
Fig. 17-7
Fig. 17-7
200
10
4
–
–
–
200
10
4
–
–
–
200
10
4
–
–
–
ns
RES pulse width
Mode programming
setup time
tcyc
tcyc
NMI setup time
(NMI, IRQ0 to IRQ7)
NMI hold time
tNMIS
tNMIH
tNMIW
Fig. 17-8
Fig. 17-8
Fig. 17-8
110
10
–
–
–
110
10
–
–
–
110
10
–
–
–
ns
ns
ns
(NMI, IRQ0 to IRQ7)
Interrupt pulse width
for recovery from soft-
ware standby mode
(NMI, IRQ0 to IRQ2)
200
200
200
Crystal oscillator settling tOSC1
time (reset)
Fig. 17-9
20
10
–
–
20
10
–
–
20
10
–
–
ms
ms
Crystal oscillator settling tOSC2
time (software standby)
Fig. 17-10
Table 17-6. Timing Conditions of On-Chip Supporting Modules
Conditions: VCC = 5.0V ±10%, Ø = 0.5 to 10MHz, VSS = 0V,
Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications)
Measurement 6MHz 8MHz 10MHz
Symbol conditions min max min max min max Unit
Item
FRT
Timer output
delay time
Timer input
setup time
tFTOD
Fig. 17-11
Fig. 17-11
Fig. 17-12
–
100
–
100
–
100 ns
tFTIS
50
50
1.5
–
50
50
1.5
–
50
50
1.5
–
–
–
ns
Timer clock
input setup time
Timer clock
pulse width
tFTCS
–
–
ns
tFTCWH Fig. 17-12
–
–
tcyc
tFTCWL
274
Table 17-6. Timing Conditions of On-Chip Supporting Modules (cont.)
Conditions: VCC = 5.0V ±10%, Ø = 0.5 to 10MHz, VSS = 0V,
Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications)
Measurement 6MHz
8MHz
10MHz
Item
TMR Timer output
delay time
Symbol conditions min max min max min max Unit
tTMOD
tTMRS
tTMCS
Fig. 17-13
Fig. 17-15
Fig. 17-14
–
100
–
–
100
–
–
100 ns
Timer reset
50
50
1.5
50
50
1.5
50
50
1.5
–
–
–
ns
input setup time
Timer clock
–
–
ns
input setup time
Timer clock
tTMCWH Fig. 17-14
tTMCWL Fig. 17-14
–
–
tcyc
pulse width
(single edge)
Timer clock
2.5
–
–
2.5
–
–
2.5
–
–
tcyc
pulse width
(both edges)
PWM Timer output
delay time
tPWOD
Fig. 17-16
100
100
100 ns
SCI
Input (Async) tscyc
Fig. 17-17
Fig. 17-17
2
4
–
–
2
4
–
–
2
4
–
–
tcyc
tcyc
clock (Sync)
cycle
tscyc
Transmit data
delay time (Sync)
Receive data
setup time (Sync)
Receive data
hold time (Sync)
Input clock
tTXD
tRXS
tRXH
tSCKW
tPWD
Fig. 17-17
Fig. 17-17
Fig. 17-17
Fig. 17-18
Fig. 17-19
Fig. 17-19
Fig. 17-19
–
100
–
–
100
–
–
100 ns
100
100
100
100
0.4
–
100
100
–
–
ns
–
–
ns
0.4 0.6
0.6
100
–
0.4 0.6
tscyc
pulse width
Ports
Output data
–
100
–
–
100 ns
delay time
Input data setup tPRS
50
50
50
50
50
50
–
–
ns
ns
time
Input data hold tPRH
time
–
–
275
Table 17-6. Timing Conditions of On-Chip Supporting Modules (cont.)
Conditions: VCC = 5.0V ±10%, Ø = 0.5 to 10MHz, VSS = 0V,
Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications)
Measurement 6MHz
8MHz
10MHz
Item
Symbol conditions min max min max min max Unit
Dual- Address
tDAA
tDACS
tDOE
Fig. 17-20
Fig. 17-20
Fig. 17-20
–
–
–
–
–
0
150
130
70
50
50
–
–
–
–
–
–
0
150
130
70
50
50
–
–
–
–
–
–
0
150 ns
130 ns
port
access time
RAM CS access
read
time
cycle OE output
delay time
70
50
50
–
ns
ns
ns
ns
CS output
tDCHZ Fig. 17-20
tDOHZ Fig. 17-20
floating time
OE output
floating time
Output data
hold time
tDOH
Fig. 17-20
Dual- Chip select time tDCW
Fig. 17-21
Fig. 17-21
100
100
–
–
100
100
–
–
100
100
–
–
ns
ns
port
Address valid
tDAW
RAM time
write
Address setup
tDAS
Fig. 17-21
Fig. 17-21
Fig. 17-21
Fig. 17-21
Fig. 17-21
20
90
20
60
15
–
–
–
–
–
20
90
20
60
15
–
–
–
–
–
20
90
20
60
15
–
–
–
–
–
ns
ns
ns
ns
ns
cycle time
Write pulse
tDWP
tDWR
tDDW
tDDH
width
Address hold
time
Input data
setup time
Input data
hold time
276
• Measurement Conditions for AC Characteristics
5 V
RL
LSI
output pin
C = 90 pF: Ports 1 – 4, 6, 9
30 pF: Ports 5, 8
RL = 2.4 kΩ
RH
C
RH = 12 kΩ
Input/output timing reference levels
Low: 0.8 V
High: 2.0 V
Figure 17-3. Output Load Circuit
17.2.3 A/D Converter Characteristics
Table 17-7 lists the characteristics of the on-chip A/D converter.
Table 17-7. A/D Converter Characteristics
Conditions: VCC = AVCC = 5.0V ±10%, VSS = AVSS = 0V, Ta = –20 to 75˚C (regular specifications)
Ta = –40 to 85˚C (wide-range specifications)
6MHz
8MHz
10MHz
Item
min typ
max min typ
max min typ
max Unit
Bits
12.2 µs
Resolution
Conversion time
(single mode)
8
8
8
8
8
8
8
8
8
—
—
20.4
—
—
15.25 —
—
Analog input capacitance —
—
—
20
10
—
—
—
—
20
10
—
—
—
—
20
10
pF
Allowable signal
source impedance
Nonlinearity error
Offset error
—
kΩ
—
—
—
—
—
—
—
—
—
—
±1
—
—
—
—
—
—
—
—
—
—
±1
—
—
—
—
—
—
—
—
—
—
±1
±1
±1
LSB
LSB
LSB
±1
±1
Full-scale error
Quantizing error
Absolute accuracy
±1
±1
±0.5
±1.5
±0.5
±1.5
±0.5 LSB
±1.5 LSB
277
17.3 MCU Operational Timing
This section provides the following timing charts:
17.3.1 Bus Timing
Figures 17-4 to 17-6
17.3.2 Control Signal Timing
17.3.3 16-Bit Free-Running Timer Timing
17.3.4 8-Bit Timer Timing
17.3.5 PWM Timer Timing
17.3.6 SCI Timing
Figures 17-7 to 17-10
Figures 17-11 to 17-12
Figures 17-13 to 17-15
Figure 17-16
Figures 17-17 to 17-18
Figure 17-19
17.3.7 I/O Port Timing
17.3.8 Dual-port RAM Timing
Figures 17-20 to 17-21
17.3.1 Bus Timing
(1) Basic Bus Cycle (Without Wait States) in Expanded Modes
T
1
T
2
T
3
tcyc
tCH
tCL
Ø
tCr
tCf
tAD
A15 to A0
IOS
tASD
tSD
tAH
tASI
AS, RD
(Read)
tRDH
tRDS
tACC
D7 to D0
(Read)
tWSD
tSD
tAS2
tWSW
tAH
WR
tWDH
tWDD
tWDS
D7 to D0
(Write)
Figure 17-4. Basic Bus Cycle (Without Wait States) in Expanded Modes
278
(2) Basic Bus Cycle (With 1 Wait State) in Expanded Modes
T
T
T
T
3
2
1
W
Ø
A15 to A0
IOS
AS, RD
D7 to D0
(Read)
WR
D7 to D0
(Write)
tWTS tWTH
tWTS tWTH
WAIT
Figure 17-5. Basic Bus Cycle (With 1 Wait State) in Expanded Modes
279
(3) E Clock Bus Cycle
Ø
E
tED
tED
tEf
tEr
tAD
A15 – A0, IOS
tAS1
tSD
tAH
AS
tAD
tAD
RD,WR
tRDS
tRDH
tRDHE
D7 to D0
(Read)
tWDHE
D7 to D0
(Write)
Figure 17-6. E Clock Bus Cycle
17.3.2 Control Signal Timing
(1) Reset Input Timing
Ø
tRESS
tRESS
RES
tMDS
tRESW
MD1 and
MD0
Figure 17-7. Reset Input Timing
280
(2) Interrupt Input Timing
Ø
tNMIS tNMIH
NMI
IRQi (Edge)
tNMIS
IRQi (Level)
tNMIW
NMI
IRQi
Note: i = 0 to 7
Figure 17-8. Interrupt Input Timing
281
Ø
VCC
STBY
RES
tOSC1
tOSC1
Figure 17-9. Clock Settling Timing
(4) Clock Settling Timing for Recovery from Software Standby Mode
Ø
NMI
IRQi
tOSC2
(i = 0, 1, 2)
Figure 17-10. Clock Settling Timing for Recovery from Software Standby Mode
17.3.3 16-Bit Free-Running Timer Timing
(1) Free-Running Timer Input/Output Timing
Ø
Free-running
Compare-match
timer counter
tFTOD
FTOA , FTOB
tFTIS
FTIA, FTIB,
FTIC, FTID
Figure 17-11. Free-Running Timer Input/Output Timing
283
(2) External Clock Input Timing for Free-Running Timer
Ø
t
FTCS
FTCI
t
FTCWL
tFTCWH
Figure 17-12. External Clock Input Timing for Free-Running Timer
17.3.4 8-Bit Timer Timing
(1) 8-Bit Timer Output Timing
Ø
Timer
Compare- match
counter
tTMOD
TMCI1,
TMCI0
Figure 17-13. 8-Bit Timer Output Timing
(2) 8-Bit Timer Clock Input Timing
Ø
tTMCS
tTMCS
TMCI0,
TMCI1
tTMCWL
tTMCWH
Figure 17-14. 8-Bit Timer Clock Input Timing
284
(3) 8-Bit Timer Reset Input Timing
Ø
tTMRS
TMRI0,
TMRI1
Timer
counter
n
H'00
Figure 17-15. 8-Bit Timer Reset Input Timing
17.3.5 Pulse Width Modulation Timer Timing
Ø
Timer
Compare- match
counter
tPWOD
PW0, PW1
Figure 17-16. PWM Timer Output Timing
17.3.6 Serial Communication Interface Timing
(1) SCI Input/Output Timing
tScyc
Serial clock
(CSCK)
tTXD
Transmit
data
(CTxD)
tRXS tRXH
Receive
data
(CRxD)
Figure 17-17. SCI Input/Output Timing (Synchronous Mode)
285
(2) SCI Input Clock Timing
tSCKW
ASCK, CSCK
tScyc
Figure 17-18. SCI Input Clock Timing
17.3.7 I/O Port Timing
Port read/write cycle
T1
T2
T3
Ø
tPRS
tPRH
Port 1
to (Input)
Port 9
tPWD
Port 1*
to (Output)
Port 9
* Except P96 and P77 to P70
Figure 17-19. I/O Port Input/Output Timing
286
17.3.8 Dual-Port RAM Timing
(1) Read Cycle 1
RS3 to RS0
OE
tDAA
tDOH
tDOE
CS
tDOHZ
tDCHZ
tDACS
DDB7 to DDB0
Note: WE should be High during a read cycle.
(2) Read Cycle 2
RS3 to RS0
tDAA
tDOH
tDOH
DDB7 to DDB0
Notes: 1. WE should be High during a read cycle.
2. CS = VIL
3. OE = VIL
(3) Read Cycle 3
CS
tDCHZ
tDACS
DDB7 to DDB0
Notes:1. WE should be High during a read cycle.
2. The address on the register select lines should be set up by the time CS goes Low, or before that time.
3. OE = VIL
Figure 17-20. Dual-Port RAM Read Timing
287
(4) Write Cycle
RS3 to RS0
2*
tDWR
OE
CS
3*
tDCW
tDAW
tDAS
WE
1*
tDWP
tDDH
tDDW
DDB7 to DDB0
Notes: 1. Data are written while CS and WE are both low (tDWP).
2. tDWR is measured from the rise of CS or WE, whichever rises first.
3. If CS goes Low at the same time as WE goes Low or after WE goes Low, the output remains in the high-
impedance state.
Figure 17-21. Dual-Port RAM Write Timing
288
Appendix A. CPU Instruction Set
A.1 Instruction Set List
Operation Notation
Rd8/16
General register (destination) (8 or 16 bits)
Rs8/16
General register (source) (8 or 16 bits)
General register (8 or 16 bits)
Destination operand
Source operand
Rn8/16
(EAd)
(EAs)
CCR
Condition code register
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Program counter
N
Z
V
C
PC
SP
Stack pointer
#xx:3/8/16
Immediate data (3, 8, or 16 bits)
Displacement (8 or 16 bits)
Absolute address (8 or 16 bits)
Addition
d:8/16
@aa:8/16
+
–
×
÷
Subtraction
Multiplication
Division
AND logical
OR logical
Exclusive OR logical
Move
→
Not
Condition Code Notation
↕
*
Modified according to the instruction result
Undetermined (unpredictable)
Always cleared to "0"
0
—
Not affected by the instruction result
289
Appendix B. Instruction Set List
Addressing mode/
instruction length
Mnemonic
Operation
Condition code
I
H
–
–
–
–
–
N Z
V
0
0
0
0
0
C
–
–
–
–
–
MOV.B #xx:8,Rd
MOV.B Rs,Rd
B
B
B
B
B
#xx:8 → Rd8
2
–
–
–
–
–
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
2
2
4
6
6
Rs8 → Rd8
2
MOV.B @Rs,Rd
MOV.B @(d:16,Rs),Rd
MOV.B @Rs+,Rd
@Rs16 → Rd8
@(d:16,Rs16)→ Rd8
@Rs16 → Rd8
Rs16+1 → Rs16
@aa:8 → Rd8
2
4
2
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B Rs,@Rd
B
B
B
B
B
2
4
–
–
–
–
–
–
–
–
–
–
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
0
0
0
0
0
–
–
–
–
–
4
6
4
6
6
@aa:16 → Rd8
Rs8 → @Rd16
Rs8 → @(d:16,Rd16)
Rd16–1 → Rd16
Rs8 → @Rd16
Rs8 → @aa:8
2
MOV.B Rs,@(d:16,Rd)
MOV.B Rs,@–Rd
4
2
MOV.B Rs,@aa:8
MOV.B Rs,@aa:16
MOV.W #xx:16,Rd
MOV.W Rs,Rd
B
2
4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
0
0
0
0
0
0
0
–
–
–
–
–
–
–
4
6
4
2
4
6
6
B
Rs8 → @aa:16
#xx:16 → Rd
W
W
W
W
W
4
Rs16 → Rd16
2
MOV.W @Rs,Rd
MOV.W @(d:16,Rs),Rd
MOV.W @Rs+,Rd
@Rs16 → Rd16
@(d:16,Rs16) → Rd16
@Rs16 → Rd16
Rs16+2 → Rs16
@aa:16 → Rd16
Rs16 → @Rd16
Rs16 → @(d:16,Rd16)
Rd16–2 → Rd16
Rs16 → @Rd16
Rs16 → @aa:16
@SP → Rd16
2
2
4
4
2
2
MOV.W @aa:16,Rd
MOV.W Rs,@Rd
W
W
W
W
4
4
–
–
–
–
–
–
–
–
◊
◊
◊
◊
◊
◊
◊
◊
0
0
0
0
–
–
–
–
6
4
6
6
MOV.W Rs,@(d:16,Rd)
MOV.W Rs,@–Rd
MOV.W Rs, @aa:16
POP Rd
W
W
–
–
–
–
◊
◊
◊
◊
0
0
–
–
6
6
2
2
SP+2 → SP
PUSH Rs
W
SP–2 → SP
–
–
◊
◊
0
–
6
Rs16 → @SP
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
EEPMOV
B
B
–
Not supported
Not supported
if R4L≠0 then
4
–
–
–
–
–
–
√
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next
290
Appendix B. Instruction Set List (cont.)
Addressing mode/
instruction length
Mnemonic
Operation
Condition code
I
H N Z V C
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W Rs,Rd
ADDX.B #xx:8,Rd
ADDX.B Rs,Rd
ADDS.W #1,Rd
ADDS.W #2,Rd
INC.B Rd
B
Rd8+#xx:8 → Rd8
Rd8+Rs8 → Rd8
Rd16+Rs16 → Rd16
Rd8+#xx:8 +C → Rd8
Rd8+Rs8 +C → Rd8
Rd16+1 → Rd16
Rd16+2 → Rd16
Rd8+1 → Rd8
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
–
–
◊
*
◊
◊
◊
◊
–
–
◊
*
◊
◊
◊
◊
–
–
◊
◊
◊
◊
◊
–
–
–
2
2
2
2
2
2
2
2
B
2
2
◊
W
B
➀ ◊
◊
◊
◊
–
–
–
*
◊
◊
◊
–
–
◊
◊
◊
➁
➁
–
B
2
2
2
2
2
2
2
W
W
B
–
◊
DAA.B Rd
B
Rd8 decimal adjust → Rd8
Rd8–Rs8 → Rd8
Rd16–Rs16 → Rd16
Rd8–#xx:8 –C → Rd8
Rd8–Rs8 –C → Rd8
Rd16–1 → Rd16
Rd16–2 → Rd16
Rd8–1 → Rd8
◊
➂ 2
SUB.B Rs,Rd
SUB.W Rs,Rd
SUBX.B #xx:8,Rd
SUBX.B Rs,Rd
SUBS.W #1,Rd
SUBS.W #2,Rd
DEC.B Rd
B
◊
◊
◊
◊
◊
–
–
–
–
◊
◊
◊
◊
–
–
2
2
W
B
➀ ◊
◊
2
◊
◊
–
–
–
*
◊
◊
◊
◊
◊
–
–
◊
◊
◊
◊
◊
➁
➁
–
2
B
2
2
2
2
2
2
2
W
W
B
2
–
2
◊
2
DAS.B Rd
B
Rd8 decimal adjust → Rd8
0–Rd → Rd
◊
2
NEG.B Rd
B
◊
2
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W Rs,Rd
MULXU.B Rs,Rd
DIVXU.B Rs,Rd
B
Rd8–#xx:8
2
◊
2
B
Rd8–Rs8
2
2
2
2
◊
2
W
B
Rd16–Rs16
➀ ◊
◊
2
Rd8×Rs8 → Rd16
Rd16÷Rs8 → Rd16
(RdH:remainder, RdL:quotient)
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
Rd → Rd
–
–
–
–
14
14
B
≈
∆
AND.B #xx:8,Rd
AND.B Rs,Rd
OR.B #xx:8,Rd
OR.B Rs,Rd
B
B
B
B
B
B
B
2
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
0
0
0
0
0
0
0
–
–
–
–
–
–
–
2
2
2
2
2
2
2
2
2
XOR.B #xx:8,Rd
XOR.B Rs,Rd
NOT.B Rd
2
2
291
Appendix B. Instruction Set List (cont.)
Addressing mode/
instruction length
Mnemonic
Operation
Condition code
H N Z V C
I
C
0
SHAL.B Rd
B
B
B
B
B
B
B
B
2
2
2
2
2
2
2
2
–
–
–
–
–
–
–
–
–
◊ ◊
◊ ◊
◊ ◊
0 ◊
◊ ◊
◊ ◊
◊ ◊
◊ ◊
◊
0
0
0
0
0
0
0
◊
◊
◊
◊
◊
◊
◊
◊
2
2
2
2
2
2
2
2
b7
b0
SHAR.B Rd
SHLL.B Rd
SHLR.B Rd
ROTXL.B Rd
ROTXR.B Rd
ROTL.B Rd
ROTR.B Rd
–
–
–
–
–
–
–
C
b7
b7
b0
b0
C
0
0
C
b7
b7
b0
b0
C
C
b7
b7
b0
b0
C
C
b7
b0
BSET #xx:3,Rd
BSET #xx:3,@Rd
BSET #xx:3,@aa:8
BSET Rn,Rd
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
(#xx:3 of Rd8) ← 1
(#xx:3 of @Rd16) ← 1
(#xx:3 of @aa:8) ← 1
(Rn8 of Rd8) ← 1
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
8
8
2
8
8
2
8
8
2
8
8
2
8
8
BSET Rn,@Rd
(Rn8 of @Rd16) ← 1
(Rn8 of @aa:8) ← 1
(#xx:3 of Rd8) ← 0
(#xx:3 of @Rd16) ← 0
(#xx:3 of @aa:8) ← 0
(Rn8 of Rd8) ← 0
BSET Rn,@aa:8
BCLR #xx:3,Rd
BCLR #xx:3,@Rd
BCLR #xx:3,@aa:8
BCLR Rn,Rd
BCLR Rn,@Rd
BCLR Rn,@aa:8
BNOT #xx:3,Rd
BNOT #xx:3,@Rd
BNOT #xx:3,@aa:8
(Rn8 of @Rd16) ← 0
(Rn8 of @aa:8) ← 0
(#xx:3 of Rd8) ← (#xx:3 of Rd8)
(#xx:3 of @Rd16) ←(#xx:3 of @Rd16)
(#xx:3 of @aa:8) ← (#xx:3 of @aa:8)
292
Appendix B. Instruction Set List (cont.)
Addressing mode/
instruction length
Mnemonic
Operation
Condition code
H N Z V C
I
BNOT Rn,Rd
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
(Rn8 of Rd8) ← (Rn8 of Rd8)
(Rn8 of @Rd16) ← (Rn8 of @Rd16)
(Rn8 of @aa:8) ← (Rn8 of @aa:8)
(#xx:3 of Rd8) → Z
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
–
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
–
–
–
◊
◊
◊
◊
◊
◊
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
◊
◊
◊
◊
◊
◊
–
–
–
–
–
–
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
2
8
8
2
6
6
2
6
6
2
6
6
2
6
6
2
8
8
2
8
8
2
6
6
2
6
6
2
6
6
2
BNOT Rn,@Rd
BNOT Rn,@aa:8
BTST #xx:3,Rd
BTST #xx:3,@Rd
BTST #xx:3,@aa:8
BTST Rn,Rd
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(#xx:3 of @Rd16) → Z
(#xx:3 of @aa:8) → Z
(Rn8 of Rd8) → Z
BTST Rn,@Rd
(Rn8 of @Rd16) → Z
(Rn8 of @aa:8) → Z
BTST Rn,@aa:8
BLD #xx:3,Rd
(#xx:3 of Rd8) → C
BLD #xx:3,@Rd
BLD #xx:3,@aa:8
BILD #xx:3,Rd
(#xx:3 of @Rd16) → C
(#xx:3 of @aa:8) → C
(#xx:3 of Rd8) → C
BILD #xx:3,@Rd
BILD #xx:3,@aa:8
BST #xx:3,Rd
(#xx:3 of @Rd16) → C
(#xx:3 of @aa:8) → C
C → (#xx:3 of Rd8)
BST #xx:3,@Rd
BST #xx:3,@aa:8
BIST #xx:3,Rd
C → (#xx:3 of @Rd16)
C → (#xx:3 of @aa:8)
C → (#xx:3 of Rd8)
BIST #xx:3,@Rd
BIST #xx:3,@aa:8
BAND #xx:3,Rd
BAND #xx:3,@Rd
BAND #xx:3,@aa:8
BIAND #xx:3,Rd
BIAND #xx:3,@Rd
BIAND #xx:3, @aa:8
BOR #xx:3,Rd
C → (#xx:3 of @Rd16)
C → (#xx:3 of @aa:8)
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
BOR #xx:3,@Rd
BOR #xx:3, @aa:8
BIOR #xx:3, Rd
293
Appendix B. Instruction Set List (cont.)
Addressing mode/
instruction length
Mnemonic
Operation
Condition code
H N Z V
Branching
condition
I
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
C
◊
◊
◊
◊
◊
◊
◊
◊
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BIOR #xx:3,@Rd
BIOR #xx:3, @aa:8
BXOR #xx:3,Rd
BXOR #xx:3,@Rd
BXOR #xx:3, @aa:8
BIXOR #xx:3,Rd
BIXOR #xx:3,@Rd
BIXOR #xx:3, @aa:8
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
B
B
B
B
B
B
B
B
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
C (#xx:3 of @Rd16) → C
4
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6
6
2
6
6
2
6
6
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
6
8
6
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
PC ← PC+d:8
4
2
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PC ← PC+2
if condition
is true then
C
C
Z = 0
Z = 1
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
PC ← PC+d:8 C = 0
else next;
C = 1
Z = 0
BEQ d:8
Z = 1
BVC d:8
V = 0
BVS d:8
V = 1
BPL d:8
N = 0
BMI d:8
N = 1
BGE d:8
N V = 0
N V = 1
BLT d:8
BGT d:8
Z
Z
(N V) = 0
BLE d:8
(N V) = 1
JMP @Rn
PC ← Rn16
PC ← aa:16
PC ← @aa:8
SP–2 → SP
PC → @SP
PC ← PC+d:8
2
JMP @aa:16
JMP @@aa:8
BSR d:8
4
2
2
294
Appendix B. Instruction Set List (cont.)
Addressing mode/
instruction length
Mnemonic
Operation
Condition code
H N Z V C
I
JSR @Rn
–
–
SP–2 → SP
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6
8
8
PC → @SP
PC ← Rn16
JSR @aa:16
JSR @@aa:8
SP–2 → SP
4
–
–
PC → @SP
PC ← aa:16
SP–2 → SP
2
PC → @SP
PC ← @aa:8
PC ← @SP
RTS
RTE
–
–
2
2
–
–
–
–
–
–
8
SP+2 → SP
CCR ← @SP
SP+2 → SP
◊
◊
◊
◊
◊
◊
10
PC ← @SP
SP+2 → SP
SLEEP
–
Transit to sleep mode.
#xx:8 → CCR
Rs8 → CCR
2
–
◊
◊
–
◊
◊
◊
–
–
◊
◊
–
◊
◊
◊
–
–
◊
◊
–
◊
◊
◊
–
–
◊
◊
–
◊
◊
◊
–
–
◊
◊
–
◊
◊
◊
–
–
◊
◊
–
◊
◊
◊
–
2
2
2
2
2
2
2
2
LDC #xx:8,CCR
LDC Rs,CCR
STC CCR,Rd
ANDC #xx:8,CCR
ORC #xx:8,CCR
XORC #xx:8,CCR
NOP
B
B
B
B
B
B
–
2
2
2
CCR → Rd8
CCR #xx:8 → CCR
CCR #xx:8 → CCR
CCR #xx:8 → CCR
PC ← PC+2
2
2
2
2
Notes: The number of states is the number of states required for execution when the instruction and its
operands are located in on-chip memory.
①
≠
Set to “1” when there is a carry or borrow from bit 11; otherwise cleared to “0.”
If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to “0.”
Set to “1” if decimal adjustment produces a carry; otherwise cleared to “0.”
The number of states required for execution is 4n+8 (n = value of R4L)
These instructions are not supported by the H8/338 Series.
③
④
∞
±
Set to “1” if the divisor is negative; otherwise cleared to “0.”
≤
Cleared to “0” if the divisor is not zero; undetermined when the divisor is zero.
295
A.2 Operation Code Map
Table A-2 is a map of the operation codes contained in the first byte of the instruction code (bits 15
to 8 of the first instruction word).
Some pairs of instructions have identical first bytes. These instructions are differentiated by the
first bit of the second byte (bit 7 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is "0."
Instruction when first bit of byte 2 (bit 7 of first instruction word) is "1."
296
Table A-2. Operation Code Map
LO
0
1
2
3
4
5
6
8
9
A
B
C
E
7
D
F
HI
ADDS
0
NOP
SLEEP
STC
LDC
ORC
OR
XORC
XOR
ANDC
AND
ADD
SUB
INC
DEC
MOV
CMP
ADDX
SUBX
DAA
DAS
LDC
SHLL
SHLR
SHAR
ROTXL
ROTL
ROTXR
ROTR
NOT
SUBS
1
2
3
4
5
6
SHAL
NEG
MOV
BRA*2
MULXU DIVXU
BRN *2
BHI
BLS
BCC*2
RTS
BCS*2
BSR
BVS
BMI
BNE
RTE
BEQ
BVC
BPL
JMP
BGE
BLT
BGT
JSR
BLE
BST
BLD
MOV *1
BIST
BNOT
BTST
BSET
BCLR
BOR
BXOR
BIXOR
BAND
BIAND
EEPMOV
Bit manipulation instruction
7
MOV
BIOR
BILD
ADD
8
ADDX
9
CMP
SUBX
OR
A
B
C
D
E
F
XOR
AND
MOV
1
2
*
The MOVFPE and MOVTPE instructions are identical to MOV instructions in the first byte and first bit of the second byte (bits 15 to 7 of the instruction word). The PUSH and POP
instructions are identical in machine language to MOV instructions.
The BT, BF, BHS, and BLO instructions are identical in machine language to BRA, BRN, BCC, and BCS, respectively.
*
A.3 Number of States Required for Execution
The tables below can be used to calculate the number of states required for instruction execution.
Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates
the number of cycles of each type occurring in each instruction. The total number of states required
for execution of an instruction can be calculated from these two tables as follows:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state
inserted in external memory access.
1. BSET #0, @FFC7
From table A-4: I = L = 2, J = K = M = N= 0
From table A-3: SI = 8, SL = 3
Number of states required for execution: 2 × 8 + 2 × 3 =22
2. JSR @@30
From table A-4: I = 2, J = K = 1, L = M = N = 0
From table A-3: SI = SJ = SK = 8
Number of states required for execution: 2 × 8 + 1 × 8 + 1 × 8 = 32
Table A-3. Number of States Taken by Each Cycle in Instruction Execution
Execution Status
(instruction cycle)
Instruction fetch
Access Location
On-Chip Memory On-Chip Reg. Field External Memory
SI
Branch address read SJ
6
6 + 2m
Stack operation
Byte data access
Word data access
Internal operation
SK
SL
SM
SN
2
3
6
2
3 + m
6 + 2m
Notes: 1. m: Number of wait states inserted in access to external device.
2. The byte data access cycle to an external device by the MOVFPE and MOVTPE
instructions requires 9 to 16 states since it is synchronized with the E clock. See
section 15, "E-Clock Interface" for timing details.
298
Table A-4. Number of Cycles in Each Instruction
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
ADD
ADD.B #xx:8, Rd
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
2
2
ADD.B Rs, Rd
ADD.W Rs, Rd
ADDS.W #1/2, Rd
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
AND.B #xx:8, Rd
AND.B Rs, Rd
ANDC#xx:8, CCR
BAND#xx:3, Rd
BAND#xx:3, @Rd
BAND#xx:3, @aa:8
BRAd:8 (BT d:8)
BRNd:8 (BF d:8)
BHId:8
ADDS
ADDX
AND
ANDC
BAND
1
1
Bcc
BLSd:8
BCCd:8 (BHS d:8)
BCSd:8 (BLO d:8)
BNEd:8
BEQd:8
BVCd:8
BVSd:8
BPLd:8
BMId:8
BGEd:8
BLTd:8
BGTd:8
BLEd:8
BCLR
BCLR#xx:3, Rd
BCLR#xx:3, @Rd
BCLR#xx:3, @aa:8
BCLRRn, Rd
BCLRRn, @Rd
BCLRRn, @aa:8
2
2
2
2
299
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
BIAND#xx:3, Rd
J
K
L
BIAND
BILD
BIOR
BIST
BIXOR
BLD
1
BIAND#xx:3, @Rd
BIAND#xx:3, @aa:8
BILD#xx:3, Rd
2
1
1
2
1
BILD#xx:3, @Rd
BILD#xx:3, @aa:8
BIOR#xx:3 Rd
2
1
1
2
1
BIOR#xx:3 @Rd
BIOR#xx:3 @aa:8
BIST#xx:3, Rd
2
1
1
2
1
BIST#xx:3, @Rd
BIST#xx:3, @aa:8
BIXOR#xx:3, Rd
BIXOR#xx:3, @Rd
BIXOR#xx:3, @aa:8
BLD #xx:3, Rd
2
2
2
2
1
2
1
1
2
1
BLD #xx:3, @Rd
BLD #xx:3, @aa:8
BNOT #xx:3, Rd
BNOT #xx:3, @Rd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
2
1
1
2
BNOT
1
2
2
2
2
1
BNOT Rn, @Rd
BNOT Rn, @aa:8
BOR #xx:3, Rd
2
2
2
2
BOR
1
BOR #xx:3, @Rd
BOR #xx:3, @aa:8
BSET #xx:3, Rd
BSET #xx:3, @Rd
BSET #xx:3, @aa:8
BSET Rn, Rd
2
1
1
2
BSET
1
2
2
2
2
1
BSET Rn, @Rd
BSET Rn, @aa:8
2
2
2
2
300
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
BSR
BST
BSR d:8
2
1
2
2
1
2
2
1
2
2
1
2
2
1
1
1
1
1
1
1
2
1
2
2
2
2
2
2
1
1
1
1
1
2
1
BST #xx:3, Rd
BST #xx:3, @Rd
BST #xx:3, @aa:8
BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
2
2
BTST
1
1
BTST Rn, @Rd
BTST Rn, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W Rs, Rd
DAA.B Rd
1
1
BXOR
CMP
1
1
DAA
DAS
DAS.B Rd
DEC
DEC.B Rd
DIVXU
DIVXU.B Rs, Rd
6
*1
EEPMOV EEPMOV
2n+2
INC
JMP
INC.B Rd
JMP @Rn
JMP @aa:16
1
1
JMP @@aa:8
JSR @Rn
1
1
JSR
1
1
1
JSR @aa:16
1
JSR @@aa:8
LDC #xx:8, CCR
LDC Rs, CCR
MOV.B#xx:8, Rd
MOV.BRs, Rd
MOV.B@Rs, Rd
MOV.B@(d:16,Rs), Rd
LDC
MOV
1
1
301
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
Instruction Mnemonic
MOV MOV.B @Rs+, Rd
J
K
L
1
1
1
1
1
1
1
1
N
1
1
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
1
2
1
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @–Rd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
2
1
1
1
2
2
1
MOV.W @Rs, Rd
1
1
1
1
1
1
1
1
1
MOV.W @(d:16, Rs), Rd
MOV.W @Rs+, Rd
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
2
1
1
1
6
2
1
MOV.W Rs, @(d:16, Rd)
MOV.W Rs, @–Rd
MOV.W Rs, @aa:16
2
1
2
*2
MOVFPE MOVFPE @aa:16, Rd
MOVTPE MOVTPE.Rs, @aa:16
2
1
*2
2
1
MULXU
NEG
NOP
NOT
OR
MULXU.Rs, Rd
NEG.B Rd
NOP
1
1
1
NOT.B Rd
OR.B #xx:8, Rd
OR.B Rs, Rd
ORC #xx:8, CCR
ROTL.B Rd
ROTR.B Rd
ROTXL.B Rd
ROTXR.B Rd
RTE
1
1
1
ORC
1
ROTL
ROTR
ROTXL
ROTXR
RTE
1
1
1
1
2
2
1
1
1
RTS
RTS
2
302
Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
I
J
K
L
SHAL
SHAR
SHLL
SHLR
SLEEP
STC
SHAL.B Rd
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SHAR.B Rd
SHLL.B Rd
SHLR.B Rd
SLEEP
STC CCR, Rd
SUB.B Rs, Rd
SUB.W Rs, Rd
SUBS.W#1/2, Rd
SUBX.B#xx:8, Rd
SUBX.BRs, Rd
XOR.B#xx:8, Rd
XOR.B Rs, Rd
XORC#xx:8, CCR
SUB
SUBS
SUBX
XOR
XORC
Notes:
*1 n: Initial value in R4L. Source and destination are accessed n + 1 times each.
*2 Data access requires 9 to 16 states.
303
Appendix B. Register Field
B.1 Register Addresses and Bit Names
Addr.
(last Register
Bit names
byte) name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
Module
External
addresses
(in
H'80
H'81
H'82
H'83
H'84
H'85
H'86
H'87
H'88
H'89
H'8A
H'8B
H'8C
H'8D
H'8E
H'8F
expanded
modes)
H’90
H’91
H’92
H’93
H’94
TIER
ICIAE
ICFA
ICIBE
ICFB
ICICE
ICFC
ICIDE
ICFD
OCIAE OCIBE OVIE
—
FRT
TCSR
OCFA
OCFB OVF
CCLRA
FRC (H)
FRC (L)
OCRA (H)
OCRB (H)
OCRA (L)
OCRB (L)
TCR
H’95
H’96
H’97
H’98
H’99
IEDGA IEDGB IEDGC IEDGD
OCRS
BUFEA BUFEB CKS1
CKS0
TOCR
—
—
—
OEA OEB OLVLA OLVLB
ICRA (H)
ICRA (L)
H’9A ICRB (H)
H’9B ICRB (L)
H’9C ICRC (H)
H’9D ICRC (L)
H’9E ICRD (H)
H’9F
ICRD (L)
Notes: FRT: Free-Running Timer
(Continued on next page)
304
(Continued from previous page)
Addr.
(last Register
Bit names
byte) name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
Module
H’A0 TCR
H’A1 DTR
H’A2 TCNT
OE
OS
—
—
—
CKS2 CKS1
CKS0
PWM0
H’A3
—
—
—
—
—
—
—
—
—
—
—
—
H’A4 TCR
H’A5 DTR
H’A6 TCNT
OE
OS
CKS2 CKS1
CKS0
PWM1
H’A7
H'A8
H'A9
H'AA
H'AB
H'AC
H'AD
H'AE
H'AF
—
—
—
—
—
—
—
—
—
External
addresses
(in
expanded
modes)
H’B0 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDRP11DDR P10DDR
H’B1 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDRP21DDR P20DDR
Port 1
Port 2
Port 1
Port 2
Port 3
Port 4
Port 3
Port 4
Port 5
Port 6
Port 5
Port 6
—
H’B2 P1DR
H’B3 P2DR
P17
P27
P16
P26
P15
P25
P14
P24
P13
P23
P12
P22
P11
P21
P10
P20
H’B4 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDRP31DDR P30DDR
H’B5 P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDRP41DDR P40DDR
H’B6 P3DR
H’B7 P4DR
H’B8 P5DDR
P37
P47
—
P36
P46
—
P35
P45
—
P34
P44
—
P33
P43
—
P32
P42
P31
P41
P30
P40
P52DDRP51DDR P50DDR
H’B9 P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDRP61DDR P60DDR
H’BA P5DR
H’BB P6DR
—
—
—
—
—
P52
P62
—
P51
P61
—
P50
P60
—
P67
—
P66
—
P65
—
P64
—
P63
—
H’BC
—
H’BD P8DDR
H’BE P7DR
H’BF P8DR
—
P86DDR P85DDR P84DDR P83DDR P82DDRP81DDR P80DDR
Port 8
Port 7
Port 8
P77
—
P76
P86
P75
P85
P74
P84
P73
P83
P72
P82
P71
P81
P70
P80
(Continued on next page)
Notes: PWM0: Pulse-Width Modulation timer channel 0
PWM1: Pulse-Width Modulation timer channel 1
305
(Continued from preceding page)
Addr.
(last Register
Bit names
Bit 4 Bit 3
byte) name Bit 7
Bit 6
Bit 5
Bit 2 Bit 1
Bit 0
Module
H’C0 P9DDR P97DDR P96DDR P95DDR P94DDR P93DDR P92DDRP91DDR P90DDR
Port 9
H’C1 P9DR
P97
—
P96
—
P95
—
P94
—
P93
—
—
—
—
P92
—
P91
—
P90
—
H’C2
H’C3
—
—
—
—
—
—
—
—
—
H’C4 SYSCR SSBY
STS2
—
STS1
—
STS0
—
NMIEG DPME RAME
MDS1 MDS0
System
control
H’C5 MDCR
H’C6 ISCR
H’C7 IER
—
—
IRQ7SC IRQ6SC IRQ5SC IRQ4SC
IRQ3SC IRQ2SC IRQ1SC IRQ0SC
IRQ7E
IRQ6E
IRQ5E
IRQ4E
CCLR1
—
IRQ3E
IRQ2E IRQ1E
IRQ0E
CKS0
OS0
H’C8 TCR
CMIEB CMIEA OVIE
CCLR0 CKS2 CKS1
TMR0
TMR1
SCI
H’C9 TCSR
H’CA TCORA
H’CB TCORB
H’CC TCNT
CMFB
CMFA OVF
OS3
OS2
OS1
H’CD
H’CE
H’CF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H’D0 TCR
CMIEB CMIEA OVIE
CCLR1
—
CCLR0 CKS2 CKS1
CKS0
OS0
H’D1 TCSR
H’D2 TCORA
H’D3 TCORB
H’D4 TCNT
CMFB
CMFA OVF
OS3
OS2
OS1
H’D5
H’D6
H’D7
—
—
—
—
—
—
—
—
PE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H’D8 SMR
H’D9 BRR
H’DA SCR
H’DB TDR
H’DC SSR
H’DD RDR
C/A
CHR
O/E
STOP
CKS1
CKS0
TIE
RIE
TE
RE
—
—
—
CKE1
—
CKE0
—
TDRE
RDRF
ORER
FER
PER
H’DE
H’DF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Continued on next page)
Notes: TMR0: 8-Bit Timer channel 0
TMR1: 8-Bit Timer channel 1
SCI: Serial Communication Interface
306
(Continued from preceding page)
Addr.
(last Register
Bit names
byte) name Bit 7
Bit 6
—
Bit 5
—
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
—
Module
H’E0
H’E1
ADDRA
—
A/D
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H’E2 ADDRB
H’E3
H’E4 ADDRC
—
—
—
—
—
H’E5
H’E6
H’E7
—
—
—
—
—
ADDRD
—
—
—
—
—
CKS
—
—
CH2
—
—
CH1
—
—
CH0
—
H’E8 ADCSR ADF
H’E9
H’EA ADCR TRGE
ADIE
—
ADST
—
SCAN
—
—
—
—
—
—
—
—
—
—
H’EB
H’EC
H’ED
H’EE
H’EF
H’F0
H’F1
H’F2
H’F3
H’F4
H’F5
H’F6
H’F7
H’F8
H’F9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PCCSR MWEF
PCDR0
EMWI SWEF
EAKAR MREF
EMRI MWMF SWMF
DPRAM
PCDR1
PCDR2
PCDR3
PCDR4
PCDR5
PCDR6
PCDR7
PCDR8
H’FA PCDR9
H’FB PCDR10
H’FC PCDR11
H’FD PCDR12
H’FE PCDR13
H’FF
PCDR14
Note: A/D: Analog-to-Digital converter
DPRAM: Dual-port RAM
307
308
TIER—Timer Interrupt Enable Register
H’FF90
FRT
Bit
7
6
5
ICICE
0
4
3
2
1
0
—
1
ICIAE ICIBE
ICIDE OCIAE OCIBE OVIE
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Overflow Interrupt Enable
0 Overflow interrupt request is disabled.
1 Overflow interrupt request is enabled.
Output Compare Interrupt B Enable
0 Output compare interrupt request B is disabled.
1 Output compare interrupt request B is enabled.
Output Compare Interrupt A Enable
0 Output compare interrupt request A is disabled.
1 Output compare interrupt request A is enabled.
Input Capture Interrupt D Enable
0 Input capture interrupt request D is disabled.
1 Input capture interrupt request D is enabled.
Input Capture Interrupt C Enable
0 Input capture interrupt request C is disabled.
1 Input capture interrupt request C is enabled.
Input Capture Interrupt B Enable
0 Input capture interrupt request B is disabled.
1 Input capture interrupt request B is enabled.
Input Capture Interrupt A Enable
0 Input capture interrupt request A is disabled.
1 Input capture interrupt request A is enabled.
309
TCSR—Timer Control/Status Register
H’FF91
FRT
Bit
7
6
5
ICFC
0
4
3
2
1
0
ICFA ICFB
ICFD OCFA OCFB
OVF CCLRA
Initial value
0
0
0
0
0
0
0
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W
Counter Clear A
0 FRC count is not cleared.
1 FRC count is cleared by compare-match A.
Timer Overflow Flag
0 Cleared when CPU reads OVF = “1,” then writes “0” in OVF.
1 Set when FRC changes from H’FFFF to H’0000.
Output Compare Flag B
0 Cleared when CPU reads OCFB = “1”, then writes “0” in OCFB.
1 Set when FRC = OCRB.
Output Compare Flag A
0 Cleared when CPU reads OCFA = “1”, then writes “0” in OCFA.
1 Set when FRC = OCRA.
Input Capture Flag D
0 Cleared when CPU reads ICFD = “1”, then writes “0” in ICFD.
1 Set by FTID input.
Input Capture Flag C
0 Cleared when CPU reads ICFC = “1”, then writes “0” in ICFC.
1 Set by FTIC input.
Input Capture Flag B
0 Cleared when CPU reads ICFB = “1”, then writes “0” in ICFB.
1 Set when FTIB input causes FRC to be copied to ICRB.
Input Capture Flag A
0 Cleared when CPU reads ICFA = “1”, then writes “0” in ICFA.
1 Set when FTIA input causes FRC to be copied to ICRA.
* Software can write a "0" in bits 7 to 1 to clear the flags, but cannot write a "1" in these bits
310
FRC (H and L)—Free-Running Counter
H’FF92, H’FF93
FRT
Bit
7
6
5
4
3
2
1
0
0
Initial value
Read/Write
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
OCRA (H and L)—Output Compare Register A
H’FF94, H’FF95
FRT
Bit
7
6
5
4
3
2
1
0
1
Initial value
Read/Write
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Continually compared with FRC. OCFA is set to “1” when OCRA = FRC.
OCRB (H and L)—Output Compare Register B
H’FF94, H’FF95
FRT
Bit
7
6
5
4
3
2
1
0
1
Initial value
Read/Write
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Continually compared with FRC. OCFB is set to “1” when OCRB = FRC.
311
TCR—Timer Control Register
H’FF96
FRT
Bit
7
6
5
4
3
2
1
0
IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select
0 0 Internal clock source: Ø/2
0 1 Internal clock source: Ø/8
1 0 Internal clock source: Ø/32
1 1 External clock source: counted on rising edge
Buffer Enable B
0 ICRD is used for input capture D.
1 ICRD is buffer register for input capture B.
Buffer Enable A
0 ICRC is used for input capture C.
1 ICRC is buffer register for input capture A.
Input Edge Select D
0 Falling edge of FTID is valid.
1 Rising edge of FTID is valid.
Input Edge Select C
0 Falling edge of FTIC is valid.
1 Rising edge of FTIC is valid.
Input Edge Select B
0 Falling edge of FTIB is valid.
1 Rising edge of FTIB is valid.
Input Edge Select A
0 Falling edge of FTIA is valid.
1 Rising edge of FTIA is valid.
312
TOCR—Timer Output Control Register
H’FF97
FRT
Bit
7
—
1
6
—
1
5
—
1
4
OCRS
0
3
2
1
0
OEA
0
OEB OLVLA OLVLB
Initial value
Read/Write
0
0
0
—
—
—
R/W
R/W
R/W
R/W
R/W
Output Level B
0 Compare-match B causes “0” output.
1 Compare-match B causes “1” output.
Output Level A
0 Compare-match A causes “0” output.
1 Compare-match A causes “1” output.
Output Enable B
0 Output compare B output is disabled.
1 Output compare B output is enabled.
Output Enable A
0 Output compare A output is disabled.
1 Output compare A output is enabled.
Output Compare Register Select
0 The CPU can access OCRA at addresses H’FF94 – H’FF95.
1 The CPU can access OCRB at addresses H’FF94 – H’FF95.
ICRA (H and L)—Input Capture Register
H’FF98, H’FF99
FRT
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Contains FRC count captured on FTIA input.
313
ICRB (H and L)—Input Capture Register
H’FF9A, H’FF9B
FRT
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Contains FRC count captured on FTIB input.
ICRC (H and L)—Input Capture Register
H’FF9C, H’FF9D
FRT
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Contains FRC count captured on FTIC input, or old ICRA value in buffer mode.
ICRD (H and L)—Input Capture Register
H’FF9E, H’FF9F
FRT
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Contains FRC count captured on FTID input, or old ICRB value in buffer mode.
314
TCR—Timer Control Register
H’FFA0
PWM0
Bit
7
OE
0
6
OS
0
5
—
1
4
—
1
3
—
1
2
1
0
CKS2 CKS1 CKS0
Initial value
Read/Write
0
0
0
R/W
R/W
—
—
—
R/W
R/W
R/W
Clock Select
(Values When Ø = 10MHz)
Internal
Reso-
PWM
period
PWM
clock Freq. lution
frequency
0 0 0
0 0 1
0 1 0
Ø/2
Ø/8
200ns
50µs 20kHz
200µs 5kHz
800ns
3.2µs
Ø/32
800µs 1.25kHz
3.2ms 312.5Hz
6.4ms 156.3Hz
0 1 1 Ø/128 12.8µs
1 0 0 Ø/256 25.6µs
1 0 1 Ø/1024 102.4µs 25.6ms 39.1Hz
1 1 0 Ø/2048 204.8µs 51.2ms 19.5Hz
1 1 1 Ø/4096 409.6µs 102.4ms
9.8Hz
Output Select
0 Positive logic
1 Negative logic
Output Enable
0 PWM output disabled; TCNT cleared to H’00 and stops.
1 PWM output enabled; TCNT runs.
DTR—Duty Register
H’FFA1
PWM0
Bit
7
6
5
4
3
1
2
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Pulse duty factor
315
TCNT—Timer Counter
H’FFA2
PWM0
Bit
7
6
5
4
3
0
2
0
1
0
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value (runs from H’00 to H’F9, then repeats from H’00)
TCR—Timer Control Register
H’FFA4
PWM1
Bit
7
OE
0
6
OS
0
5
—
1
4
—
1
3
—
1
2
1
0
CKS2 CKS1 CKS0
Initial value
Read/Write
0
0
0
R/W
R/W
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for PWM0.
DTR—Duty Register
H’FFA5
PWM1
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for PWM0.
316
TCNT—Timer Counter
H’FFA6
PWM1
Bit
7
6
5
4
3
0
2
0
1
0
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for PWM0.
P1DDR—Port 1 Data Direction Register
H’FFB0
2
Port 1
Bit
7
6
5
4
3
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 1 Input/Output Control
0 Input port
1 Output port
P1DR—Port 1 Data Register
H’FFB2
Port 1
Bit
7
P17
0
6
P16
0
5
P15
0
4
P14
0
3
P13
0
2
P12
0
1
P11
0
0
P10
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
317
P2DDR—Port 2 Data Direction Register
H’FFB1
Port 2
Bit
7
6
5
4
3
2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 2 Input/Output Control
0 Input port
1 Output port
P2DR—Port 2 Data Register
H’FFB3
Port 2
Bit
7
P27
0
6
P26
0
5
P25
0
4
P24
0
3
P23
0
2
P22
0
1
P21
0
0
P20
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3DDR—Port 3 Data Direction Register
H’FFB4
Port 3
Bit
7
6
5
4
3
2
1
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 3 Input/Output Control
0 Input port
1 Output port
318
P3DR—Port 3 Data Register
H’FFB6
Port 3
Bit
7
P37
0
6
P36
0
5
P35
0
4
P34
0
3
P33
0
2
1
P31
0
0
P30
0
P32
Initial value
Read/Write
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P4DDR—Port 4 Data Direction Register
H’FFB5
Port 4
Bit
7
6
5
4
3
2
1
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 4 Input/Output Control
0 Input port
1 Output port
P4DR—Port 4 Data Register
H’FFB7
Port 4
Bit
7
P47
0
6
P46
0
5
P45
0
4
P44
0
3
P43
0
2
P42
0
1
P41
0
0
P40
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P5DDR—Port 5 Data Direction Register
H’FFB8
Port 5
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
P52DDR P51DDR P50DDR
Initial value
Read/Write
0
0
0
—
—
—
—
—
W
W
W
Port 5 Input/Output Control
0 Input port
1 Output port
319
P5DR—Port 5 Data Register
H’FFBA
Port 5
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
P52
0
1
P51
0
0
P50
0
Initial value
Read/Write
—
—
—
—
—
R/W
R/W
R/W
P6DDR—Port 6 Data Direction Register
H’FFB9
Port 6
Bit
7
6
5
4
3
2
1
0
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 6 Input/Output Control
0 Input port
1 Output port
P6DR—Port 6 Data Register
H’FFBB
Port 6
Bit
7
P67
0
6
P66
0
5
P65
0
4
P64
0
3
P63
0
2
P62
0
1
P61
0
0
P60
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P7DR—Port 7 Data Register
H’FFBE
Port 7
Bit
7
P77
*
6
P76
*
5
P75
*
4
P74
*
3
P73
*
2
P72
*
1
P71
*
0
P70
*
Initial value
Read/Write
R
R
R
R
R
R
R
R
* Depends on the levels of pins P77 to P70.
320
P8DDR—Port 8 Data Direction Register
H’FFBD
Port 8
Bit
7
6
5
4
3
2
1
0
—
P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR
Initial value
Modes 1 and 2 1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Mode 3
1
Read/Write
—
W
W
W
W
W
W
W
Port 8 Input/Output Control
0 Input port
1 Output port
P8DR—Port 8 Data Register
H’FFBF
Port 8
Bit
7
—
1
6
P86
0
5
P85
0
4
P84
0
3
P83
0
2
P82
0
1
P81
0
0
P80
0
Initial value
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P9DDR—Port 9 Data Direction Register
Bit
H’FFC0
Port 9
7
6
5
4
3
2
1
0
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
Modes 1 and 2
Initial value
Read/Write
Mode 3
0
1
0
0
0
0
0
0
W
—
W
W
W
W
W
W
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 9 Input/Output Control
0 Input port
1 Output port
321
P9DR—Port 9 Data Register
H’FFC1
Port 9
Bit
7
P97
0
6
P96
0
5
P95
0
4
P94
0
3
P93
0
2
1
P91
0
0
P90
0
P92
Initial value
Read/Write
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SYSCR—System Control Register
H’FFC4
System Control
Bit
7
6
5
STS1
0
4
STS0
0
3
—
1
2
1
0
SSBY STS2
NMIEG DPME RAME
Initial value
Read/Write
0
0
0
0
1
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
RAM Enable
0 On-chip RAM is disabled.
1 On-chip RAM is enabled.
Dual-Port RAM Enable
0 Dual-port RAM is disabled.
1 (1) Single-chip mode: dual-port RAM is enabled.
(2) Expanded modes: no effect
NMI Edge
0 Falling edge of NMI is detected.
1 Rising edge of NMI is detected.
Standby Timer Select
0 0 0 Clock settling time = 8192 states
0 0 1 Clock settling time = 16384 states
0 1 0 Clock settling time = 32768 states
0 1 1 Clock settling time = 65536 states
1 – – Clock settling time = 131072 states
Software Standby
0 SLEEP instruction causes transition to sleep mode.
1 SLEEP instruction causes transition to software standby mode.
322
MDCR—Mode Control Register
H’FFC5
System Control
Bit
7
—
1
6
—
1
5
—
1
4
—
0
3
—
0
2
—
1
1
0
MDS1 MDS0
Initial value
Read/Write
*
*
—
—
—
—
—
—
R
R
Mode Select Bits
Value at mode pins.
* Determined by inputs at pins MD1 and MD0.
ISCR—IRQ Sense Control Register
H’FFC6
System Control
Bit
7
6
5
4
3
2
1
0
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ0 to IRQ7 Sense Control
0 IRQi is level-sensed (active Low).
1 IRQi is edge-sensed (falling edge).
IER—IRQ Enable Register
H’FFC7
System Control
Bit
7
6
5
IRQ5E
0
4
3
2
1
0
IRQ7E IRQ6E
IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Initial value
Read/Write
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ0 to IRQ7 Enable
0 IRQi is disabled.
1 IRQi is enabled.
323
TCR—Timer Control Register
H’FFC8
TMR0
Bit
7
6
5
4
3
2
1
0
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select
0 0 0 No clock source; timer stops.
0 0 1 Internal clock source: Ø/8, counted on falling edge.
0 1 0 Internal clock source: Ø/64, counted on falling edge.
0 1 1 Internal clock source: Ø/1024, counted on falling edge.
1 0 0 No clock source; timer stops.
1 0 1 External clock source, counted on rising edge.
1 1 0 External clock source, counted on falling edge.
1 1 1 External clock source, counted on both rising and falling edges.
Counter Clear
0 0 Counter is not cleared.
0 1 Cleared by compare-match A.
1 0 Cleared by compare-match B.
1 1 Cleared on rising edge of external reset input.
Timer Overflow Interrupt Enable
0 Overflow interrupt request is disabled.
1 Overflow interrupt request is enabled.
Compare-Match Interrupt Enable A
0 Compare-match A interrupt request is disabled.
1 Compare-match A interrupt request is enabled.
Compare-Match Interrupt Enable B
0 Compare-match B interrupt request is disabled.
1 Compare-match B interrupt request is enabled.
324
TCSR—Timer Control/Status Register
H’FFC9
TMR0
Bit
7
6
5
OVF
0
4
—
1
3
2
1
0
2
2
2
2
CMFB CMFA
OS3*
0
OS2*
0
OS1*
0
OS0*
Initial value
0
0
0
1
1
1
Read/Write R/(W)* R/(W)* R/(W)*
—
R/W
R/W
R/W
R/W
Output Select
0 0 No change on compare-match A.
0 1 Output “0” on compare-match A.
1 0 Output “1” on compare-match A.
1 1 Invert (toggle) output on compare-match A.
Output Select
0 0 No change on compare-match B.
0 1 Output “0” on compare-match B.
1 0 Output “1” on compare-match B.
1 1 Invert (toggle) output on compare-match B.
Timer Overflow Flag
0 Cleared when CPU reads OVF = “1,” then writes “0” in OVF.
1 Set when TCNT changes from H’FF to H’00.
Compare-Match Flag A
0 Cleared when CPU reads CMFA = “1,” then writes “0” in CMFA.
1 Set when TCNT = TCORA.
Compare-Match Flag B
0 Cleared from when CPU reads CMFB = “1,” then writes “0” in CMFB.
1 Set when TCNT = TCORB.
1
* Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits.
2
* When all four bits (OS3 to OS0) are cleared to “0,” output is disabled.
325
TCORA—Time Constant Register A
H’FFCA
TMR0
Bit
7
6
5
4
3
1
2
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The CMFA bit is set to “1” when TCORA = TCNT.
TCORB—Time Constant Register B
H’FFCB
TMR0
Bit
7
6
5
4
3
1
2
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The CMFB bit is set to “1” when TCORB = TCNT.
TCNT—Timer Counter
H’FFCC
TMR0
Bit
7
6
5
4
3
0
2
0
1
0
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
TCR—Timer Control Register
H’FFD0
TMR1
Bit
7
6
5
4
3
2
1
0
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for TMR0.
326
TCSR—Timer Control/Status Register
H’FFD1
TMR1
Bit
7
6
5
OVF
0
4
—
1
3
2
1
0
2
2
2
2
CMFB CMFA
OS3*
0
OS2*
0
OS1*
0
OS0*
Initial value
0
0
0
1
1
1
Read/Write R/(W)* R/(W)* R/(W)*
—
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for TMR0.
1
* Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits.
2
* When all four bits (OS3 to OS0) are cleared to “0,” output is disabled.
TCORA—Time Constant Register A
H’FFD2
TMR1
Bit
7
6
5
4
3
1
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for TMR0.
TCORB—Time Constant Register B
H’FFD3
2
TMR1
Bit
7
6
5
4
3
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for TMR0.
TCNT—Timer Counter
H’FFD4
TMR1
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for TMR0.
327
SMR—Serial Mode Register
H’FFD8
SCI
Bit
7
C/A
0
6
5
PE
0
4
O/E
0
3
2
1
0
CHR
0
STOP
0
—
1
CKS1 CKS0
Initial value
Read/Write
0
0
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
Clock Select
0 0 Ø clock
0 1 Ø/4 clock
1 0 Ø/16 clock
1 1 Ø/64 clock
Stop Bit Length
0 One stop bit
1 Two stop bits
Parity Mode
0 Even parity
1 Odd parity
Parity Enable
0 Transmit: No parity bit added.
Receive: Parity bit not checked.
1 Transmit: Parity bit added.
Receive: Parity bit checked.
Character Length
0 8-Bit data length
1 7-Bit data length
Communication Mode
0 Asynchronous
1 Synchronous
328
BRR—Bit Rate Register
H’FFD9
SCI
Bit
7
6
5
4
3
1
2
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Constant that determines the bit rate
SCR—Serial Control Register
H’FFDA
SCI
Bit
7
TIE
0
6
RIE
0
5
TE
0
4
RE
0
3
—
1
2
—
1
1
0
CKE1 CKE0
Initial value
Read/Write
0
0
R/W
R/W
R/W
R/W
—
—
R/W
R/W
Clock Enable 0
0 Asynchronous serial clock not output
1 Asynchronous serial clock output at ASCK pin
Clock Enable 1
0 Internal clock
1 External clock, input at ASCK or CSCK pin
Receive Enable
0 Receive disabled
1 Receive enabled
Transmit Enable
0 Transmit disabled
1 Transmit enabled
Receive Interrupt Enable
0 Receive interrupt request (RxI) is disabled.
1 Receive interrupt request (RxI) is enabled.
Transmit Interrupt Enable
0 Transmit interrupt request (TxI) is disabled.
1 Transmit interrupt request (TxI) is enabled.
329
TDR—Transmit Data Register
H’FFDB
SCI
Bit
7
6
5
4
3
1
2
1
1
0
Initial value
Read/Write
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Transmit data
330
SSR—Serial Status Register
H’FFDC
SCI
Bit
7
6
5
ORER
0
4
FER
0
3
2
1
—
1
0
TDRE RDRF
PER
0
—
1
—
1
Initial value
1
0
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
—
—
—
Parity Error
0 Cleared when CPU reads PER = “1,” then
writes “0” in PER.
1 Set when a parity error occurs (parity of receive
data does not match parity selected by O/E bit).
Framing Error
0 Cleared when CPU reads FER = “1,” then writes “0” in FER.
1 Set when a framing error occurs (stop bit is “0”).
Overrun Error
0 Cleared when CPU reads ORER = “1,” then writes “0” in ORER.
1 Set when an overrun error occurs (next data is completely
received while RDRF bit is set to “1”).
Receive Data Register Full
0 Cleared when CPU reads RDRF = “1,” then writes “0” in RDRF.
1 Set when one character is received normally and transferred from
RSR to RDR.
Transmit Data Register Empty
0 Cleared when CPU reads TDRE = “1,” then writes “0” in TDRE
1 Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = "0."
* Software can write a “0” in bits 7 to 3 to clear the flags, but cannot write a “1” in these bits.
RDR—Receive Data Register
H’FFDD
SCI
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Receive data
331
ADDRn—A/D Data Register n (n = A, B, C, D)
H’FFE0, H’FFE2, H’FFE4, H’FFE6
A/D
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
A/D conversion result
Note: The least significant bit of the register address is ignored.
332
ADCSR—A/D Control/Status Register
H’FFE8
A/D
Bit
7
ADF
0
6
ADIE
0
5
ADST
0
4
SCAN
0
3
2
1
0
CKS
0
CH2
0
CH1
0
CH0
0
Initial value
Read/Write R/(W)* R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel Select
CH2 CH1 CH0 Single mode Scan mode
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN0
AN0, AN1
AN0 to AN2
AN0 to AN3
AN4
AN4, AN5
AN4 to AN6
AN4 to AN7
1
Clock Select
0 Conversion time = 242 states (max)
1 Conversion time = 122 states (max)
Scan Mode
0 Single mode
1 Scan mode
A/D Start
0 A/D conversion is halted.
1 1. Single mode: One A/D conversion is performed, then this bit is automatically cleared to “0.”
2. Scan mode: A/D conversion starts and continues cyclically on all selected channels until “0”
is written in this bit.
A/D Interrupt Enable
0 The A/D interrupt request (ADI) is disabled.
1 The A/D interrupt request (ADI) is enabled.
A/D End Flag
0 Cleared from “1” to “0” when CPU reads ADF = “1,” then writes “0” in ADF.
1 Set to “1” at the following times:
1. Single mode: at the completion of A/D conversion
2. Scan mode: when all selected channels have been converted.
* Software can write a “0” in bit 7 to clear the flag, but cannot write a “1” in this bit.
333
ADCR—A/D Control Register
H’FFEA or H’FFEB
A/D
Bit
7
TRGE
0
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
R/W
—
—
—
—
—
—
—
Trigger Enable
0 ADTRG is disabled.
1 ADTRG is enabled. A/D conversion can be started by external trigger, or
by software.
334
PCCSR—Parallel Communication Control/Status Register
H’FFF0
DPRAM
Bit
7
6
5
4
3
2
1
0
MWEF EMWI SWEF EAKAR MREF EMRI MWMF SWMF
Initial value
Read/Write
0
0
0
0
0
0
0
0
H8/300 CPU: R
Master CPU: R
R/W
R
R
R
R/W
R/W
R
R
R/W
R
R
R
R
R
Master Write End Flag
0 H8/300 CPU has read PCDR14 while MWMF = "1."
1 Master CPU has written data in PCDR14.
Enable Master Write Interrupt
0 Master write end interrupt (MWEI) is disabled.
1 Master write end interrupt (MWEI) is enabled.
Slave Write End Flag
0 Master CPU has read PCDR14.
1 H8/300 CPU has written data in PCDR14.
Enable Acknowledge and Request
0 RDY output is disabled. Remains in high-impedance state.
1 RDY output is enabled.
Master Read End Flag
0 Cleared when H8/300 CPU reads or writes
PCDR0, or master CPU writes to PCDR0.
1 Set when master CPU reads PCDR0.
Enable Master Read Interrupt
0 Master read end interrupt (MREI) is disabled.
1 Master read end interrupt (MREI) is enabled.
Master Write Mode Flag
0 Not master write mode. Cleared when H8/300 CPU reads PCDR0.
1 Master write mode. Set if the master CPU writes to PCDR0 while
SWMF = “0.”
Slave Write Mode Flag
0 Not slave write mode. Cleared when master CPU reads
PCDR0.
1 Slave write mode. Set if H8/300 CPU writes to PCDR0
while MWMF = “0.”
335
PCDR0A—Parallel Communication Data Register 0A
H’FFF1
DPRAM
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
—
—
—
—
—
—
—
—
H8/300 CPU: R
Master CPU: W
R
R
R
R
R
R
R
W
W
W
W
W
W
W
PCDR0B—Parallel Communication Data Register 0B
H’FFF1
DPRAM
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
—
—
—
—
—
—
—
—
H8/300 CPU: W
Master CPU: R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
PCDR1 to PCDR14—Parallel Communication Data
Registers 1 to 14
H’FFF2 – H’FFFF
DPRAM
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
—
—
—
—
—
—
—
—
H8/300 CPU:R/W
Master CPU: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
336
Appendix C. Pin States
C.1 Pin States in Each Mode
Table C-1. Pin States
Pin
MCU
mode Reset
Hardware
standby
3-State
Software Sleep
Normal
name
standby
Low
mode
operation
Addr. output
Addr. output
P17 – P10
A7 – A0
1
2
Low
Prev. state
(Addr.
3-State
Low if
DDR = 1, output pins: or input port
Prev. state last address
if DDR = 0 accessed)
3
1
2
Prev. state
Low
I/O port
P27 – P20
A15 – A8
Low
3-State
Prev. state
(Addr.
Addr. output
Addr. output
3-State
Low if
DDR = 1, output pins: or input port
Prev. state last address
if DDR = 0 accessed)
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
Prev. state
3-state
I/O port
D7 – D0
P37 – P30
D7 – D0
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
Prev. state Prev. state
Prev. state Prev. state
(note 3)
I/O port
I/O port
P47 – P40,
P52 – P50,
P67 – P60,
P77 – P70,
P86 – P81,
Prev. state Prev. state
(note 3)
I/O port
I/O port
Input port
I/O port
Prev. state Prev. state
(note 3)
3-State
3-State
Prev. state Prev. state
(note 3)
337
Table C-1. Pin States (cont.)
Pin
MCU
Hardware
standby
3-State
Software Sleep
Normal
operation
E clock if
DDR = 1,
3-state if
DDR = 0
I/O port
WAIT
name
P80/E
mode Reset
standby
mode
1
2
E clock
output
Low if
E clock if
DDR = 1, DDR = 1,
3-state if 3-state if
DDR = 0 DDR = 0
Prev. state Prev. state
3
1
2
3
1
2
3
3-State
3-State
P97/WAIT
P96/Ø
3-State
3-state
3-State
3-State
Prev. state Prev. state
I/O port
Clock
Clock
output
3-State
High
Clock
output
output
High if
Clock output Clock output
DDR = 1, if DDR = 1, if DDR = 1,
3-state if
DDR = 0 DDR = 0
High High
3-state if
input port if
DDR = 0
AS, WR,
RD
P95 – P93,
1
2
3
1
2
3
High
3-State
3-State
AS, WR, RD
3-State
3-State
Prev. state Prev. state
Prev. state Prev. state
I/O port
I/O port
P92 – P90,
Notes:
1. 3-state: High-impedance state
2. Prev. state: Previous state. Input ports are in the high-impedance state (with the MOS pull-up
on if DDR = 0 and DR = 1). Output ports hold their previous output level.
3. On-chip supporting modules are initialized, so these pins revert to I/O ports according to the
DDR and DR bits.
4. I/O port: Direction depends on the data direction (DDR) bit. Note that these pins may also be
used by the on-chip supporting modules.
See section 5, “I/O Ports” for further information.
338
Appendix D. Timing of Transition to and Recovery From
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1). To retain RAM contents, drive the RES signal low 10 system clock cycles before the STBY
signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay
from STBY low to RES high: 0 ns).
STBY
t1 ≥ 10 tcyc
t2 ≥ 0 ns
RES
(2). When it is not necessary to retain RAM contents, RES does not have to be driven low as in
(1).
Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately
100 ns before STBY goes high.
STBY
tOSC
t = 100 ns
RES
339
Appendix E. Package Dimensions
Figure E-1 shows the dimensions of the CG-84 package. Figure E-2 shows the dimensions of the
CP-84 package. Figure E-3 shows the dimensions of the FP-80A package.
Unit: mm
29.21 ± 0.38
12
32
33
53
11
1
84
75
54
74
1.27
2.16
1.27
Figure E-1. Package Dimensions (CG-84)
Unit: mm
30.23 ± 0.12
29.28
74
54
75
53
84
1
11
33
32
12
0.75
0.42 ± 0.10
28.20 ± 0.50
1.27
28.20 ± 0.50
0.10
Unit: mm
17.2 ± 0.3
14.0
60
41
40
21
61
80
1
20
0.30 ±0.10
M
0.12
1.60
0 – 5 °
0.10
0.80 ± 0.30
Figure E-3. Package Dimensions (FP-80A)
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