HD66710A01TF_技术文档

HD66710 (LCD-II/F8)

(Dot Matrix Liquid

Crystal Display Controller/Driver)

Description

Features

The LCD-II/F8 (HD66710) dot-matrix liquid crys-

tal display controller and driver LSI displays

alphanumerics, numbers, and symbols. It can be

configured to drive a dot-matrix liquid crystal

display under the control of a 4- or 8-bit micro-

processor. Since all the functions such as display

RAM, character generator, and liquid crystal

driver, required for driving a dot-matrix liquid

crystal display are internally provided on one chip,

a minimum system can be interfaced with this

controller/driver.

• 5 × 8 dot matrix possible

• Low power operation support:

— 2.7 V to 5.5 V (low voltage)

• Booster for liquid crystal voltage

— Two/three times (13 V max.)

• Wide range of liquid crystal display driver voltage

— 3.0 V to 13 V

• Extension driver interface

• High-speed MPU bus interface

(2 MHz at 5-V operation)

• 4-bit or 8-bit MPU interface capability

• 80 × 8-bit display RAM (80 characters max.)

• 9,600-bit character generator ROM

— 240 characters (5 × 8 dot)

• 64 × 8-bit character generator RAM

— 8 characters (5 × 8 dot)

A single LCD-II/F8 is capable of displaying a

single16-character line, two 16-character lines, or

up to four 8-character lines.

The LCD-II/F8 software is upwardly compatible

with the LCDII (HD44780) which allows the user

to easily replace an LCD-II with an HD66710. In

addition, the HD66710 is equipped with functions

such as segment displays for icon marks, a 4-line

display mode, and a horizontal smooth scroll, and

thus supports various display forms. This achieves

various display forms. The HD66710 character

generator ROM is extended to generate 240 5 × 8

dot characters.

• 8 × 8-bit segment RAM

— 40-segment icon mark

• 33-common × 40-segment liquid crystal display

driver

• Programmable duty cycle

(See list 1)

• Wide range of instruction functions:

— Functions compatible with LCD-II: Display

clear, cursor home, display on/off, cursor

on/off, display character blink, cursor shift,

display shift

— Additional functions: Icon mark control,

4-line display, horizontal smooth scroll,

6-dot character width control, white-black

inverting blinking cursor

The low voltage version (2.7 V) of the HD66710,

combined with a low power mode, is suitable for

any portable battery-driven product requiring low

power dissipation.

• Software upwardly compatible with HD44780

• Automatic reset circuit that initializes the con-

troller/driver after power on

• Internal oscillator with an external resistor

• Low power consumption

• QFP1420-100 pin, TQFP1414-100 pin bare-chip

HD66710

List 1 Programmable Duty Cycles

Maximum Number of Displayed Characters

Number of

Lines

Displayed

Character

Duty Ratio

Single-chip Operation

With Extention Driver

1

2

4

1/17

5 × 8-dot

One 16-character

line + 40 segments

One 50-character

line + 40 segments

1/33

5 × 8-dot

Two 16-character

lines + 40 segments

Two 30-character

lines + 40 segments

Four 8-character

Four 20-character

lines + 40 segments

Ordering Information

Type No.

Package

CGROM

HD66710A00FS

HD66710A00TF

HCD66710A00

HD66710A01TF*

HD66710A02TF*

HD66710BxxFS

HD66710BxxTF

HCD66710Bxx

QFP1420-100 (FP-100A)

TQFP1414-100 (TFP-100B)

Chip

Japanese standard

TQFP1414-100 (TFP-100B)

QFP1420-100 (FP-100A)

TQFP1414-100 (TFP-100B)

Chip

Communication

European font

Custom font

Note: * Under development

Bxx = ROM code No.

333

HD66710

LCD-II Family Comparison

LCD-II

(HD44780U)

LCD-II/E20

(HD66702R)

LCD-II/F8

(HD66710)

LCD-II/F12

HD66712

Item

Power supply voltage

2.7 V to 5.5 V

5 V ±10%

2.7 V to 5.5 V

(standard)

2.7 V to 5.5 V

(low voltage)

Liquid crystal drive

voltage

3.0 V to 11 V

3.0 V to 8.3 V

3.0 V to 13.0 V

Maximum display

digits per chip

8 characters

× 2 lines

20 characters

× 2 lines

16 characters ×

2 lines/

24 characters ×

2 lines/

8 characters ×

4 lines

12 characters ×

4 lines

Segment display

Display duty cycle

None

40 segments

1/17 and 1/33

60 segments

1/17 and 1/33

1/8, 1/11, and

1/16

1/8, 1/11, and

1/16

CGROM

9,920 bits

7,200 bits

9,600 bits

(208 5 × 8 dot

characters and

32 5 × 10 dot

characters)

(160 5 × 7 dot

characters and

32 5 × 10 dot

characters)

(240 5 × 8 dot

characters)

(240 5 × 8 dot

characters)

CGRAM

64 bytes

80 bytes

None

40

64 bytes

80 bytes

None

100

64 bytes

80 bytes

8 bytes

40

64 bytes

80 bytes

16 bytes

60

DDRAM

SEGRAM

Segment signals

Common signals

16

33

34

Liquid crystal drive

waveform

A

B

Bleeder resistor for LCD External

External

power supply

(adjustable)

Clock source

Extenal resistor

or external clock

External resistor

or external clock

External resistor

or external clock

External resistor

or external clock

R_foscillation frequency

(frame frequency)

270 kHz ±30%

(59 to 110 Hz for

320 kHz ±30%

(70 to 130 Hz for (56 to 103 Hz for (56 to 103 Hz for

270 kHz ±30%

1/8 and 1/16 duty 1/8 and 1/16 duty 1/17 duty cycle;

1/17 duty cycle;

57 to 106 Hz for

1/33 duty cycle)

cycle; 43 to

80 Hz for 1/11

duty cycle)

cycle; 51 to

95 Hz for 1/11

duty cycle)

57 to 106 Hz for

1/33 duty cycle)

R_fresistance

91 kΩ: 5-V

operation;

75 kΩ: 3-V

operation

68 kΩ: 5-V

operation;

56 kΩ: (3-V

operation)

91 kΩ: 5-V

operation;

75 kΩ: 3-V

operation)

91 kΩ: 5-V

operation;

75 kΩ: 3-V

operation

Liquid crystal voltage

booster circuit

None

2–3 times step-

up circuit

2–3 times step-

up circuit

334

HD66710

LCD-II

(HD44780U)

LCD-II/E20

(HD66702R)

LCD-II/F8

(HD66710)

LCD-II/F12

HD66712

Item

Extension driver control

signal

Independent

control signal

Independent

control signal

Used in common Independent

with a driver

output pin

control signal

Reset function

Instructions

Power on

automatic

reset

Power on

automatic

reset

Power on

automatic

reset

Power on

automatic reset

or reset input

LCD-II

(HD44780)

Fully compatible

with the LCD-II

Upper

compatible with

the LCD-II

Upper compatible

with the LCD-II

Number of displayed

lines

1 or 2

1, 2, or 4

Low power mode

Horizontal scroll

Bus interface

None

Available

Dot unit

Available

Dot unit

Character unit

4 bits/8 bits

Character unit

4 bits/8 bits

Serial;

4 bits/8 bits

CPU bus timing

2 MHz: 5-V

operation;

1 MHz: 3-V

operation

1 MHz

2 MHz: 5-V

operation;

1 MHz: 3-V

operation

2 MHz: 5-V

operation;

1 MHz: 3-V

operation

Package

QFP-1420-80

LQFP-2020-144

QFP-1420-100

QFP-1420-128

80-pin bare chip

144-pin bare chip 100-pin bare chip TCP-128

TQFP1414-100 128-pin bare chip

335

HD66710

HD66710 Block Diagram

OSC1

OSC2

EXT

CPG

Reset circuit

ACL

Timing generator

7

Instruction register

(I R)

Instruction

decoder

COM1–

COM33

Display data RAM

(DD RAM)

80 × 8 bits

Common

signal

33-bit

shift

8

driver

register

Address counter

7

RS

R/W

E

MPU

interface

7

8

SEG1–

SEG36

40-bit

shift

register

40-bit

latch

circuit

8

Data

register

(DR)

Segment

signal

driver

DB4–DB7

DB3–DB0

SEG37/CL1

SEG38/CL2

SEG39/D

Input/

output

buffer

8

SEG40/M

3

7

Busy

flag

LCD drive

voltage

selector

Cursor and

bling

controller

Segment

RAM

(SGRAM)

8 bytes

Character

generator RAM

(CGRAM)

Character

generator ROM

(CGROM)

64 bytes

9,600 bytes

Vci

C1

C2

Booster

5

5/6

V5OUT2

V5OUT3

Parallel/serial

converter

and attribute circuit

V_CC

GND

V1

V2

V3

V4

V5

336

HD66710

HD66710 Pin Arrangement

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SEG27

SEG28

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

2

SEG29

3

SEG30

4

SEG31

5

SEG32

6

SEG33

7

V

CC

SEG34

8

TEST

EXT

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

E

SEG35

9

SEG36

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

SEG37/CL1

SEG38/CL2

SEG39/D

SEG40/M

COM9

LCD-II/F8

(FP-100A)

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

R/W

RS

OSC2

OSC1

Vci

C2

C1

GND

V5OUT2

V5OUT3

V5

V4

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

(Top view)

337

HD66710

HD66710 Pin Arrangement (TQFP1414-100 Pin)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

80 79 78 77 76

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SEG29

SEG30

SEG3

SEG2

SEG1

V_CC

2

SEG31

3

SEG32

4

SEG33

5

TEST

EXT

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

E

SEG34

6

SEG35

7

SEG36

8

SEG37/CL1

SEG38/CL2

SEG39/D

SEG40/M

COM9

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

LCD-II/F8

(TFP-100B)

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

R/W

RS

OSC2

OSC1

Vci

C2

C1

GND

V5OUT2

V5OUT3

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

26 27 28 29 30

(Top view)

338

HD66710

HD66710 Pad Arrangement

Chip size (X ×Y): 5.63 mm × 6.06 mm

Coordinate

Origin

: Pad center

: Chip center

Pad size (X×Y) : 100 µm × 100 µm

1

100

81 80

2

79

HD66710

Type code

Y

29

52

50 51

30 31

X

339

HD66710

HD66710 Pad Location Coordinates

Pin No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Pad Name

V4

X

Y

Pin No.

1

Pad Name

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

COM9

X

Y

2458

2660

2640

2650

2675

2695

2495

2049

1699

1499

1300

1100

901

–2910

–2731

–2500

–2300

–2090

–1887

–1702

–1502

–1303

–1103

–900

–701

–501

–302

–99

–2495

–2695

–2495

–2051

–1701

–1498

–1302

–1102

–899

2910

V5

2

2730

V5OUT3

V5OUT2

GND

3

2499

4

2300

5

2100

C1

6

1901

C2

7

1698

Vci

8

1498

OSC1

OSC2

RS

9

1295

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

1099

900

R/W

E

700

501

DB0

301

DB1

98

DB2

98

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM24

COM23

COM22

COM21

COM20

COM19

COM18

COM17

COM8

–113

DB3

301

–302

DB4

501

–501

DB5

700

–701

DB6

900

–900

DB7

1099

1299

1502

1698

1901

2104

2300

2503

2730

2910

–1100

–1303

–1502

–1702

–1901

–2101

–2300

–2500

–2731

–2910

EXT

TEST

V_CC

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

701

–700

502

–500

299

–301

99

COM7

–101

–301

–500

–700

–899

–1099

–1302

–1501

–1701

–2051

COM6

99

COM5

302

COM4

502

COM3

698

COM2

887

COM1

1077

COM33

V1

1266

1488

V2

1710

V3

2063

340

HD66710

Pin Functions

Table 1

Pin Functional Description

Device

Signal

I/O

Interfaced with

Function

RS

I

MPU

Selects registers

0: Instruction register (for write)

Busy flag: address counter (for read)

1: Data register (for write and read)

R/W

I

MPU

Selects read or write

0: Write

1: Read

E

I

MPU

Starts data read/write

DB4 to DB7

I/O

Four high order bidirectional tristate data bus pins. Used

for data transfer between the MPU and the HD66710.

DB7 can be used as a busy flag.

DB0 to DB3

I/O

O

MPU

LCD

Four low order bidirectional tristate data bus pins. Used

for data transfer between the MPU and the HD66710.

These pins are not used during 4-bit operation.

COM1 to COM33

Common signals; those are not used become non-

selected waveforms. At 1/17 duty rate, COM1 to COM16

are used for character display, COM17 for icon display,

and COM18 to COM33 become non-selected waveforms.

At 1/33 duty rate, COM1 to COM32 are used for

character display, and COM33 for icon display.

SEG1 to SEG35

SEG36

O

LCD

Segment signals

Segment signal. When EXT = high, the same data as

that of the first dot of the extension driver is output.

SEG37/CL1

SEG38/CL2

SEG39/D

O

LCD/

Extension driver

Segment signal when EXT = low. When EXT = high,

outputs the extension driver latch pulse.

LCD/

Extension driver

Segment signal when EXT = low. When EXT = high,

outputs the extension driver shift clock.

LCD/

Extension driver

Segment signal at EXT = low. At EXT = high, the

extension driver data. Data on and after the 36th

dot is output.

SEG40/M

EXT

O

I

LCD/

Extension driver

Segment signal when EXT = low. When EXT = high,

outputs the extension driver AC signal.

—

Extension driver enable signal. When EXT = high,

SEG37 to SEG40 become extension driver interface

signals. At this time, make sure that V5 level is lower

than GND level (0 V). V5 (low) ≤ GND (high).

V1 to V5

—

Power supply

Power supply for LCD drive

V_CC– V5 = 13 V (max)

341

HD66710

Table 1

Pin Functional Description (cont)

Device

Signal

I/O

—

Interfaced with

Function

V_CC, GND

OSC1, OSC2

Power supply

V_CC: +2.7 V to 5.5 V, GND: 0 V

—

Oscillation

resistor

clock

When CR oscillation is performed, a resistor must

be connected externally. When the pin input is an

external clock, it must be input to OSC1.

Vci

I

—

Input voltage to the booster, from which the liquid crystal

display drive voltage is generated.

Vci is reference voltage and power supply for the booster.

Vci = 2.0 V to 5.0 V ≤ Vci

V5OUT2

O

V5 pin/

Booster

capacitance

Voltage input to the Vci pin is boosted twice and output

When the voltage is boosted three times, the same

capacity as that of C1–C2 should be connected.

V5OUT3

C1/C2

TEST

O

—

I

V5 pin

Voltage input to the Vci pin is boosted three times and

output.

Booster

capacitance

External capacitance should be connected when using

the booster.

—

Test pin. Should be wired to ground.

342

HD66710

Function Description

By the register selector (RS) signal, these two

registers can be selected (table 2).

Registers

The HD66710 has two 8-bit registers, an instruc-

tion register (IR) and a data register (DR).

Busy Flag (BF)

When the busy flag is 1, the HD66710 is in the

internal operation mode, and the next instruction

will not be accepted. When RS = 0 and R/W = 1

The IR stores instruction codes, such as display

clear and cursor shift, and address information for

the display data RAM (DD RAM), the character

generator RAM (CG RAM), and the segment

RAM (SEG RAM). The MPU can only write to IR,

and cannot be read from.

(table 2), the busy flag is output from DB . The

7

next instruction must be written after ensuring that

the busy flag is 0.

Address Counter (AC)

The DR temporarily stores data to be written into

DD RAM, CG RAM, or SEG RAM. Data written

into the DR from the MPU is automatically written

into DD RAM, CG RAM, or SEG RAM by an

internal operation. The DR is also used for data

storage when reading data from DD RAM,

CG RAM, or SEG RAM. When address infor-

mation is written into the IR, data is read and then

stored into the DR from DD RAM, CG RAM, or

SEG RAM by an internal operation. Data transfer

between the MPU is then completed when the

MPU reads the DR. After the read, data in DD

RAM, CG RAM, or SEGRAM at the next address

is sent to the DR for the next read from the MPU.

The address counter (AC) assigns addresses to DD

RAM, CG RAM, or SEG RAM. When an address

of an instruction is written into the IR, the address

information is sent from the IR to the AC.

Selection of DD RAM, CG RAM, and SEG RAM

is also determined concurrently by the instruction.

After writing into (reading from) DD RAM, CG

RAM, or SEG RAM, the AC is automatically

incremented by 1 (decremented by 1). The AC

contents are then output to DB to DB when RS =

0 and R/W = 1 (table 2).

0

6

Table 2

Register Selection

RS

0

R/W

Operation

0

1

0

1

IR write as an internal operation (display clear, etc.)

Read busy flag (DB₇) and address counter (DB₀to DB₆)

0

1

DR write as an internal operation (DR to DD RAM, CG RAM, or SEGRAM)

DR read as an internal operation (DD RAM, CG RAM, or SEGRAM to DR)

1

343

HD66710

Display Data RAM (DD RAM)

When the display shift operation is per-

formed, the DD RAM address shifts. See

figure 3.

Display data RAM (DD RAM) stores display data

represented in 8-bit character codes. Its capacity is

80 × 8 bits, or 80 characters. The area in display

data RAM (DD RAM) that is not used for display

can be used as general data RAM. See figure 1 for

the relationships between DD RAM addresses and

positions on the liquid crystal display.

— Case 2: Figure 4 shows the case where the

EXT pin is fixed high, and the HD66710

and the 40-output extension driver are used

to extend the number of display characters.

In this case, the start address from COM9 to

COM16 of the LCD-II/F8 is 0AH. To

display 24 characters, addresses starting at

SEG11 should be used.

The DD RAM address (A_DD) is set in the address

counter (AC) as hexadecimal.

• 1-line display (N = 0) (figure 2)

When a display shift operation is performed,

the DD RAM address shifts. See figure 4.

— Case 1: When there are fewer than 80

display characters, the display begins at the

head position. For example, if using only the

HD66710, 16 characters are displayed. See

figure 3.

High order

bits

Low order

bits

Example: DD RAM address 4E

AC

1

0

1

0

AC6AC5 AC4 AC3AC2 AC1AC0

(hexadecimal)

Figure 1 DD RAM Address

Display position

(digit)

1

2

3

4

5

79

80

DD RAM

address

. . . . . . . . . . . . . . . . . .

00 01 02 03 04

4E 4F

(hexadecimal)

Figure 2 1-Line Display

344

HD66710

1 2 3 4 5 6 7 8 9 10111213141516

Display position

COM9 to 16

DRAM address

00 01 02 03 04 05 06 07

08 09 0A 0B 0C 0D 0E 0F

COM1 to 8

1 2 3 4 5 6 7 8 9 10111213141516

01 02 03 04 05 06 07 08

09 0A 0B 0C 0D 0E 0F 10

COM1 to 8

COM9 to 16 (Left shift display)

COM9 to 16 (Right shift display)

4F 00 01 02 03 04 05 06

07 08 09 0A 0B 0C 0D 0E

Figure 3 1-line by 16-Character Display Example

1 2 3 4 5 6 7 8 9 101112 1314151617 18192021222324

Display position

COM9 to 16

00 01 02 03 04 05 06

07 08 09 0A 0B

0C 0D 0E 0F 10

11 12 13 14 15 16 17

COM1 to 8

DDRAM address

LCD-II/F8

SEG1 to 35

Extension

driver (1)

LCD-II/F8

SEG11 to 35

Extension

driver (1)

Seg1 to 25

(SEG1 to 10: skip) Seg1 to 35

1 2 3 4 5 6 7 8 9 101112 1314151617 18192021222324

01 02 03 04 05 06 07

08 09 0A 0B 0C

0D 0E 0F 10 11

12 13 14 15 16 17 18

COM1 to 8

COM9 to 16 (Left shift display)

COM9 to 16 (Right shift display)

4F 00 01 02 03 04 05

06 07 08 09 0A

0B 0C 0D 0E 0F

10 11 12 13 14 15 16

Figure 4 1-line by 24-Character Display Example

345

HD66710

• 2-line display (N = 1, and NW = 0)

are not consecutive. For example, the case is

shown in figure 6 where 16 × 2-line display

is performed using the HD66710. When a

display shift operation is performed, the DD

RAM address shifts. See figure 5.

— Case 1: The first line is displayed from

COM1 to COM16, and the second line is

displayed from COM17 to COM32. Care is

required because the end address of the first

line and the start address of the second line

1 2 3 4 5 6 7 8 9 10111213141516

Display position

COM9 to 16

00 01 02 03 04 05 06 07

08 09 0A 0B 0C 0D 0E 0F

COM1 to 8

40 41 42 43 44 45 46 47

48 49 4A 4B 4C 4D 4E 4F

COM17 to 24

COM25 to 32

DDRAM address

01 02 03 04 05 06 07 08

09 0A 0B 0C 0D 0E 0F 10

49 4A 4B 4C 4D 4E 4F 50

COM1 to 8

COM9 to 16

(Left shift display)

(Right shift display)

42 43 44 45 46 47 48

COM17 to 24

41

COM25 to 32

27 00 01 02 03 04 05 06

07 08 09 0A 0B 0C 0D 0E

47 48 49 4A 4B 4C 4D 4E

COM1 to 8

COM9 to 16

COM17 to 24

67

40 41 42 43 44 45 46

COM25 to 32

Figure 5 2-line by 16-Character Display Example

346

HD66710

— Case 2: Figure 6 shows the case where the

EXT pin is fixed to high, the HD66710 and

the 40-output extension driver are used to

extend the number of display characters.

from COM25 to COM32 of the HD66710 is

4AH. To display 24 characters, the addresses

starting at SEG11 should be used.

When a display shift operation is performed,

the DD RAM address shifts. See figure 6.

In this case, the start address from COM9 to

COM16 of the HD66710 is 0AH, and that

Display position

COM9 to COM16

DDRAM address

1 2 3 4 5 6 7 8 9 101112 1314151617 18192021222324

COM1 to

COM8

00 01 02 03 04 05 06

07 08 09 0A 0B

0C 0D 0E 0F 10

11 12 13 14 15 16 17

LCD-II/F8

Extension

LCD-II/F8

Extension

SEG1 to SEG35 driver (1)

SEG11 to SEG35 driver (1)

Seg1 to Seg25 (SEG1 to SEG10: Seg1 to Seg35

skip)

1 2 3 4 5 6 7 8 9 101112 131415 1617 18192021222324

COM1 to

COM8

COM17 to

COM9 to

COM16

COM25 to

01 02 03 04 05 06 07

08 09 0A 0B 0C

0D 0E 0F 10 11

12 13 14 15 16 17 18

(Left shift display)

(Right shift display)

41 42 43 44 45 46 47

48 49 4A 4B 4C

4D 4E 4F 50 51

52 53 54 55 56 57 58

COM24

COM32

COM1 to

COM8

COM17 to

COM9 to

COM16

COM25 to

27 00 01 02 03 04 05

67 40 41 42 43 44 45

06 07 08 09 0A

46 47 48 49 4A

0B 0C 0D 0E 0F

4B 4C 4D 4E 4F

10 11 12 13 14 15 16

50 51 52 53 54 55 56

COM32

COM24

Figure 6 2-Line by 24 Character Display Example

347

HD66710

• 4-line display (NW = 1)

because the DD RAM addresses of each line

are not consecutive. For example, the case is

shown in figure 7 where 8 × 4-line display is

performed using the HD66710.

— Case 1: The first line is displayed from

COM1 to COM8, the second line is

displayed from COM9 to COM16, the third

line is displayed from COM17 to COM24,

and the fourth line is displayed from

COM25 to COM32. Care is required

When a display shift operation is performed,

the DD RAM address shifts. See figure 7.

1 2 3 4 5 6 7 8

Display position

DDRAM address

00 01 02 03 04 05 06 07

COM1 to 8

COM9 to 16

COM17 to 24

20 21 22 23 24 25 26 27

40 41 42 43 44 45 46 47

60 61 62 63 64 65 66 67

COM25 to 32

1 2 3 4 5 6 7 8

01 02 03 04 05 06 07 08

13 00 01 02 03 04 05 06

COM1 to 8

COM9 to 16

COM17 to 24

21 22 23 24 25 26 27 28

41 42 43 44 45 46 47 48

61 62 63 64 65 66 67 68

33

20 21 22 23 24 25 26

(Left shift display)

(Right shift display)

53 40 41 42 43 44 45 46

73 60 61 62 63 64 65 66

COM25 to 32

Figure 7 4-Line Display

348

HD66710

— Case 2: The case is shown in figure where

the EXT pin is fixed high, and the HD66710

and the 40-output extension driver are used

to extend the number of display characters.

When a display shift operation is performed,

the DD RAM address shifts. See figure 8.

1 2 3 4 5 6 7 8 9 10 111213141516 17 1819 20

Display position

DDRAM address

COM1 to 8

COM9 to 16

COM17 to 24

COM25 to 32

00 01 02 03 04 05 06

07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13

20 21 22 23 24 25 26

27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33

40 41 42 43 44 45 46

60 61 62 63 64 65 66

47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53

67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73

LCD-II/F8

Extension driver (1)

Extension driver (2)

1 2 3 4 5 6 7 8 9 1011 12131415 1617181920

1 2 3 4 5 6 7 8 9 1011121314151617181920

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 00

13 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12

21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 20

41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 40

33 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32

53 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52

73 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72

(Display shift right)

61 62 63 64 65

67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 60

66

(Display shift left)

Figure 8 4-Line by 20-Character Display Example

349

HD66710

Character Generator ROM (CG ROM)

SEG RAM data is stored in eight bits. The lower

six bits control the display of each segment, and

the upper two bits control segment blinking.

The character generator ROM generates 5 × 8 dot

character patterns from 8-bit character codes

(table 3). It can generate 240 5 × 8 dot character

patterns. User-defined character patterns are also

available using a mask-programmed ROM.

Modifying Character Patterns

• Character pattern development procedure

The following operations correspond to the

numbers listed in figure 9:

Character Generator RAM (CG RAM)

The character generator RAM allows the user to

redefine the character patterns. In the case of 5 × 8

characters, up to eight may be redefined.

1. Determine the correspondence between char-

acter codes and character patterns.

2. Create a listing indicating the correspondence

between EPROM addresses and data.

Write the character codes at the addresses shown

as the left column of table 3 to show the character

patterns stored in CG RAM.

3. Program the character patterns into an

EPROM.

See table 5 for the relationship between CG RAM

addresses and data and display patterns.

4. Send the EPROM to Hitachi.

Segment RAM (SEG RAM)

5. Computer processing of the EPROM is per-

formed at Hitachi to create a character pattern

listing, which is sent to the user.

The segment RAM (SEG RAM) is used to enable

control of segments such as an icon and a mark by

the user program.

6. If there are no problems within the character

pattern listing, a trial LSI is created at Hitachi

and samples are sent to the user for evaluation.

When it is confirmed by the user that the

character patterns are correctly written, mass

production of the LSI will proceed at Hitachi.

For a 1-line display, SEG RAM is read from the

COM17 output, and as for 2- or 4-line displays,

it is from the COM33 output, to performs

40-segment display.

As shown in table 6, bits in SEG RAM corre-

sponding to segments to be displayed are directly

set by the MPU, regardless of the contents of DD

RAM and CG RAM.

350

HD66710

Hitachi

User

Start

Computer

processing

Determine

character patterns

1

2

3

4

Create character

pattern listing

Create EPROM

address data listing

5

Evaluate

character

patterns

Write EPROM

EPROM → Hitachi

No

OK?

Yes

Art work

M/T

Masking

Trial

Sample

evaluation

6

No

OK?

Yes

Mass

production

Note: For a description of the numbers used in this figure, refer to the preceding page.

Figure 9 Character Pattern Development Procedure

351

HD66710

Table 3

Correspondence between Character Codes and Character Patterns (Hitachi Standard

HD66710)

Upper 4

Bits

Lower

4 Bits

0001

0000

0010 0011 0100 0101 0110 0111 1000 1001

1010 1011 1100 1101 1110 1111

CG

RAM

(1)

xxxx0000

xxxx0001

xxxx0010

xxxx0011

xxxx0100

xxxx0101

xxxx0110

xxxx0111

xxxx1000

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(1)

xxxx1001 (2)

(3)

xxxx1010

xxxx1011

xxxx1100

xxxx1101

xxxx1110

(4)

(5)

(6)

(7)

xxxx1111 (8)

Note: The user can specify any pattern in the character-generator RAM.

352

HD66710

Table 4

Relationship between Character Codes and Character Pattern (ROM Code: A01)

Upper 4

Bits

Lower

4 Bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

CG

RAM

(1)

xxxx0000

xxxx0001

xxxx0010

xxxx0011

xxxx0100

xxxx0101

xxxx0110

xxxx0111

xxxx1000

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(1)

xxxx1001 (2)

(3)

xxxx1010

xxxx1011

xxxx1100

xxxx1101

xxxx1110

(4)

(5)

(6)

(7)

xxxx1111 (8)

353

HD66710

Table 5

Relationship between Character Codes and Character Patterns (ROM Code: A02)

Upper 4

Bits

Lower

4 Bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

CG

RAM

(1)

xxxx0000

xxxx0001

xxxx0010

xxxx0011

xxxx0100

xxxx0101

xxxx0110

xxxx0111

xxxx1000

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(1)

xxxx1001 (2)

(3)

xxxx1010

xxxx1011

xxxx1100

xxxx1101

xxxx1110

(4)

(5)

(6)

(7)

xxxx1111 (8)

Note: The character codes of the characters enclosed in the bold frame are the same as those of the first

edition of the ISO8859 and the character code compatible.

354

HD66710

• Programming character patterns

— Character patterns

This section explains the correspondence be-

tween addresses and data used to program

character patterns in EPROM. The HD66710

character generator ROM can generate 240 5 × 8

dot character patterns.

EPROM address data and character pattern

data correspond with each other to form a

5 × 8 dot character pattern (table 4).

Table 6

Example of Correspondence between EPROM Address Data and Character Pattern

(5 × 8 Dots)

EPROM Address

Data

MSB

LSB

A10 A9 A8 A7 A6 A5 A4 A3

A2 A1 A0

O4 O3 O2 O1 O0

A11

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Character code

Line position

“0”

Notes: 1. EPROM addresses A₁₁to A₄correspond to a character code.

2. EPROM addresses A₂to A₀specify a line position of the character pattern. EPROM address A3

should be set to 0.

3. EPROM data O₄to O₀correspond to character pattern data.

4. Area which are lit (indicated by shading) are stored as 1, and unlit are as 0.

5. The eighth line is also stored in the CGROM, and should also be programmed. If the eighth line

is used for a cursor, this data should all be set to zero.

6. EPROM data bits O₇to O₅are invalid. 0 should be written in all bits.

355

HD66710

— Handling unused character patterns

a. When unused character patterns are

not programmed: If an unused character

code is written into DD RAM, all its dots

are lit, because the EPROM is filled with

1s after it is erased.

1. EPROM data outside the character pattern

area: This is ignored by the character gener-

ator ROM for display operation so any data is

acceptable.

b. When unused character patterns are

programmed as 0s: Nothing is displayed

even if unused character codes are written

into DD RAM. (This is equivalent to a

space.)

2. EPROM data in CG RAM area: Always fill

with zeros. (EPROM addresses 00H to FFH.)

3. Treatment of unused user patterns in the

HD66710 EPROM: According to the user

application, these are handled in either of two

ways:

Table 7

Example of Correspondence between Character Code and Character Pattern

(5 × 8 Dots) in CGRAM

a) When Character Pattern in 5 × 8 Dots

Character code (DDRAM data)

CGRAM address

A5 A4 A3 A2 A1 A0

CGRAM data

O7 O6 O5 O4 O3 O2 O1 O0

MSB

LSB

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 * 0 0 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

1

0

1

0

1

0

1

0

1

0

Character

pattern

(1)

0

*

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

1

0

1

0

1

0

1

0

1

0

Character

pattern

(8)

356

HD66710

Table 7

Example of Correspondence between Character Code and Character Pattern

(5 × 8 Dots) in CGRAM (cont)

b) When Character Pattern is 6 × 8 Dots

Character code (DDRAM data)

D7 D6 D5 D4 D3 D2 D1 D0

CGRAM address

A5 A4 A3 A2 A1 A0

CGRAM data

O7 O6 O5 O4 O3 O2 O1 O0

MSB

LSB

*

0

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Character

pattern

(1)

0

*

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

0

1

0

1

0

1

0

1

0

1

0

Character

pattern

(8)

Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).

2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the

cursor position and its display is formed by a logical OR with the cursor.

3. The character data is stored with the rightmost character element in bit 0, as shown in table 5.

Characters with 5 dots in width (FW = 0) are stored in bits 0 to 4, and characters with 6 dots in

width (FW = 1) are stored in bits 0 to 5.

4. When the upper four bits (bits 7 to 4) of the character code are 0, CGRAM is selected.

Bit 3 of the character code is invalid (*). Therefore, for example, the character codes 00

(hexadecimal) and 08 (hexadecimal) correspond to the same CGRAM address.

5. A set bit in the CGRAM data corresponds to display selection, and 0 to non-selection.

6. When the BE bit of the function set register is 1, pattern blinking control of the lower six bits is

controlled using the upper two bits (bits 7 and 6) in CGRAM.

When bit 7 is 1, of the lower six bits, only those which are set are blinked on the display.

When bit 6 is 1, a bit 4 pattern can be blinked as for a 5-dot font width, and a bit 5 pattern can

be blinked as for a 6-dot font width.

* Indicates no effect.

357

HD66710

Table 8

Relationships between SEGRAM Addresses and Display Patterns

SEGRAM data

SEGRAM

address

a) 5-dot font width

b) 6-dot font width

A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

B1 B0 S1 S2 S3 S4 S5 S6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0 * S1 S2 S3 S4 S5

B1 B0 * S6 S7 S8 S9 S10 B1 B0 S7 S8 S9 S10S11S12

B1 B0 * S11S12S13S14S15 B1 B0 S13S14S15S16S17S18

B1 B0 * S16S17S18S19S20 B1 B0 S19S20S21S22S23S24

B1 B0 * S21S22S23S24S25 B1 B0 S25S26S27S28S29S30

B1 B0 * S26S27S28S29S30 B1 B0 S31S32S33S34S35S36

B1 B0 * S31S32S33S34S35 B1 B0 S37S38S39S40S41S42

B1 B0 * S36S37S38S39S40 B1 B0 S43S44S45S46S47S48

Pattern on/off

Blinking control

Notes: 1. Data set to SEGRAM is output when COM17 is selected, as for a 1-line display, and output

when COM33 is selected, as for a 2-line or a 4-line display.

2. S1 to S48 are pin numbers of the segment output driver.

S1 is positioned to the left of the monitor.

S37 to S48 are extension driver outputs for a 6-dot character width.

3. After S40 output at 5-dot font and S48 output at 6-dot font, S1 output is repeated again.

4. As for a 5-dot font width, lower five bits (D4 to D0) are display on.off information of each

segment. For a 6-dot character width, the lower six bits (D5 to D0) are the display information

for each segment.

5. When the BE bit of the function set register is 1, pattern blinking of the lower six bits is

controlled using the upper two bits (bits 7 and 6) in SEGRAM.

When bit 7 is 1, only a bit set to “1” of the lower six bits is blinked on the display.

When bit 6 is 1, only a bit 4 pattern can be blinked as for a 5-dot font width, and only a bit 5

pattern can be blinked as for 6-dot font width.

6. Bit 5 (D5) is invalid for a 5-dot font width.

7. Set bits in the CGRAM data correspond to display selection, and zeros to non-selection.

358

HD66710

i) 5-dot font width (FW = 0)

S40

S10

S5

S1

S2

S3

S6

S7

S8

S36 S37 S38

S1

S2

S3

S9

S4

S39

ii) 6-dot font width (FW = 1)

S47

S5

S11

S5

S1

S2

S3

S6

S7

S8

S9

S12

S43 S44 S45

S48 S1

S2

S3

S6

S4

S10

S46

S4

<< Extension driver >>

Figure 10 Relationships between SEGRAM Data and Display

359

HD66710

Timing Generation Circuit

data has arrived. The latched data then enables the

driver to generate drive waveform outputs.

The timing generation circuit generates timing

signals for the operation of internal circuits such as

DD RAM, CG ROM, CG RAM, and SEGRAM.

RAM read timing for display and internal opera-

tion timing by MPU access are generated sepa-

rately to avoid interfering with each other.

Therefore, when writing data to DD RAM, for

example, there will be no undesirable inter-

ferences, such as flickering, in areas other than the

display area.

Sending serial data always starts at the display data

character pattern corresponding to the last address

of the display data RAM (DD RAM).

Since serial data is latched when the display data

character pattern corresponding to the starting

address enters the internal shift register, the

HD66710 drives from the head display.

Cursor/Blink Control Circuit

Liquid Crystal Display Driver Circuit

The cursor/blink (or white-black inversion) control

is used to produce a cursor or a flashing area on the

display at a position corresponding to the location

in stored in the address counter (AC).

The liquid crystal display driver circuit consists of

33 common signal drivers and 40 segment signal

drivers. When the character font and number of

lines are selected by a program, the required

common signal drivers automatically output drive

waveforms, while the other common signal drivers

continue to output non-selection waveforms.

For example (figure 11), when the address counter

is 08H, a cursor is displayed at a position

corresponding to DDRAM address 08H.

Character pattern data is sent serially through a

40-bit shift register and latched when all needed

360

HD66710

AC6 AC5 AC4 AC3 AC2 AC1 AC0

AC

0

1

0

For a 1-line display

Display position

1

2

3

4

5

6

7

8

9

10

09

11

DD RAM address

(hexadecimal)

00

01

02

03

04

05

06

07

08

0A

Cursor position

For a 2-line display

Display position

1

2

3

4

5

6

7

8

9

10

09

49

11

0A

4A

00

40

01

41

02

42

03

43

04

44

05

45

06

46

07

47

08

48

DD RAM address

(hexadecimal)

Cursor position

Note: Even if the address counter (AC) points to an address in the character generator RAM (CGRAM) or

segment RAM (SEGRAM), cursor/blink black-white inversion will still occur, although it will produce

meaningless results.

Figure 11 Cursor/Blink Display Example

361

HD66710

Interfacing to the MPU

before the four low order bits (for 8-bit opera-

tion, DB to DB ).

The HD66710 can send data in either two 4-bit

operations or one 8-bit operation, thus allowing

interfacing with 4- or 8-bit MPUs.

0

3

The busy flag must be checked (one instruction)

after the 4-bit data has been transferred twice.

Two more 4-bit operations then transfer the busy

flag and address counter data.

• For 4-bit interface data, only four bus lines (DB

4

to DB ) are used for transfer. Bus lines DB to

7

0

DB are disabled. The data transfer between the

3

HD66710 and the MPU is completed after the

4-bit data has been transferred twice. As for the

order of data transfer, the four high order bits

• For 8-bit interface data, all eight bus lines (DB

0

to DB ) are used.

7

(for 8-bit operation, DB to DB ) are transfered

4

7

RS

R/W

E

DB₇

DB₆

DB₅

DB₄

IR₇

IR₃

IR₂

IR₁

IR₀

BF

AC₃

AC₂

AC₁

AC₀

DR₇

DR₆

DR₅

DR₄

DR₃

DR₂

DR₁

DR₀

IR₆

IR₅

IR₄

AC₆

AC₅

AC₄

Instruction register (IR)

write

Busy flag (BF) and

address counter (AC)

read

Data register (DR)

read

Figure 12 4-Bit Transfer Example

362

HD66710

Reset Function

4. Entry mode set:

I/D = 1; Increment by 1

S = 0; No shift

Initializing by Internal Reset Circuit

An internal reset circuit automatically initializes

the HD66710 when the power is turned on. The

following instructions are executed during the

initialization. The busy flag (BF) is kept in the

busy state until the initialization ends (BF = 1).

5. Extension function set:

FW = 0; 5-dot character width

B/W = 0; Normal cursor (eighth line)

NW = 0; 1- or 2-line display (depending on N)

6. SEGRAM address set:

The busy state lasts for 15 ms after V rises to

CC

4.5 V or 40 ms after the V rises to 2.7 V.

CC

1. Display clear

HDS = 000; No scroll

2. Function set:

Note: If the electrical characteristics conditions

listed under the table Power Supply

Conditions Using Internal Reset Circuit are

not met, the internal reset circuit will not

operate normally and will fail to initialize

the HD66710. For such a case, initial-

ization must be performed by the MPU as

explained in the section, Initializing by

Instruction.

DL = 1; 8-bit interface data

N = 0; 1-line display

RE = 0; Extension register write disable

3. Display on/off control:

D = 0; Display off

C = 0; Cursor off

B = 0; Blinking off

BE = 0; CGRAM/SEGRAM blinking off

LP = 0; Not in low power mode

363

HD66710

Instructions

Outline

auto-incrementation by 1 (or auto-decrementation

by 1) of internal HD66710 RAM addresses after

each data write can lighten the program load of the

MPU. Since the display shift instruction (table 7)

can perform concurrently with display data write,

the user can minimize system development time

with maximum programming efficiency.

Only the instruction register (IR) and the data

register (DR) of the HD66710 can be controlled by

the MPU. Before starting internal operation of the

HD66710, control information is temporarily

stored in these registers to allow interfacing with

various MPUs, which operate at different speeds,

or various peripheral control devices. The internal

operation of the HD66710 is determined by signals

sent from the MPU. These signals, which include

register selection (RS), read/write (R/W), and the

data bus (DB0 to DB7), make up the HD66710

instructions (table 7). There are four categories of

instructions that:

When an instruction is being executed for internal

operation, no instruction other than the busy

flag/address read instruction can be executed.

Because the busy flag is set to 1 while an

instruction is being executed, check it to make sure

it is 0 before sending another instruction from the

MPU.

• Designate HD66710 functions, such as display

format, data length, etc.

Note: Be sure the HD66710 is not in the busy

state (BF = 1) before sending an instruction

from the MPU to the HD66710. If an

instruction is sent without checking the

busy flag, the time between the first

instruction and next instruction will take

much longer than the instruction time itself.

Refer to table 7 for the list of each instruc-

tion execution time.

• Set internal RAM addresses

• Perform data transfer with internal RAM

• Perform miscellaneous functions

Normally, instructions that perform data transfer

with internal RAM are used the most. However,

364

HD66710

Table 9

Instructions

Execution Time

(Max) (when f_cpor

f_OSCis 270 kHz)

Code

Instruction RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀Description

Clear

display

0

1

Clears entire display and

sets DD RAM address 0

in address counter.

1.52 ms

Return

home

0

1

—

Sets DD RAM address 0

in address counter. Also

returns display from being

shifted to original position.

DD RAM contents remain

unchanged.

1.52 ms

Entry

mode set

0

1

I/D

C

S

B

Sets cursor move direction 37 µs

and specifies display shift.

These operations are

performed during data

write and read.

Display

on/off

control

(RE = 0)

0

1

D

Sets entire display (D)

on/off, cursor on/off (C),

and blinking of cursor

position character (B).

37 µs

Extension

function

FW B/W NW Sets a font width, a black- 37 µs

white inverting cursor (B/W),

set (RE = 1)

a 6-dot font width (FW), and

a 4-line display (NW).

Cursor or

display

shift

0

1

S/C R/L

—

Moves cursor and shifts

display without changing

DD RAM contents.

37 µs

Function

set

(RE = 0)

DL

N

RE

Sets interface data length 37 µs

(DL), number of display

lines (N), and extension

register write enable (RE).

(RE = 1)

0

1

DL

RE BE LP

Sets CGRAM/SEGRAM

blinking enable (BE), and

low power mode (LP).

LP is available when the

EXT pin is low.

37 µs

Set

A_CGA_CGA_CGA_CGA_CGA_CGSets CG RAM address.

CG RAM data is sent and

CGRAM

address

(RE = 0)

received after this setting.

Set DDRAM

address

(RE = 0)

0

1

A_DDA_DDA_DDA_DDA_DDA_DDA_DDSets DD RAM address.

DD RAM data is sent and

37 µs

received after this setting.

Set

HDS HDS HDS *— ASG ASG ASG Sets SEGRAM address.

DDRAM data is sent and

SEGRAM

address

(RE = 1)

received after this setting.

Also sets a horizontal dot

scroll quantity (HDS).

365

HD66710

Table 9

Instructions (cont)

Execution Time

(Max) (when f_cpor

f_OSCis 270 kHz)

Code

Instruction RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀Description

Read busy

flag &

address

0

1

BF AC AC AC AC AC AC AC

Reads busy flag (BF)

indicating internal

operation is being

performed and reads

address counter contents.

0 µs

Write data

to RAM

(RE = 0/1)

0

Write data

Writes data into DD RAM, 37 µs

CG RAM, or SEGRAM.

To write data to DD RAM

CG RAM, clear RE to 0;

or to write data to SEG

RAM, set RE to 1.

t_ADD= 5.5 µs*

Read data

from RAM

(RE = 0/1)

1

Read data

Reads data from DD RAM, 37 µs

CG RAM, or SEGRAM.

To read data from DD

RAM or CG RAM, clear

RE to 0; to read data from

SEG RAM, set RE to 1.

t_ADD= 5.5 µs*

I/D = 1: Increment

I/D = 0: Decrement

DD RAM: Display data

RAM

S

D

C

B

= 1: Accompanies display shift

CG RAM: Character

generator RAM

SEGRAM: Segment RAM

= 1: Display on

= 1: Cursor on

= 1: Blink on

FW = 1: 6-dot font width

B/W = 1: Black-white inverting cursor on

NW = 1: Four lines

NW = 0: One or two lines

S/C = 1: Display shift

S/C = 0: Cursor move

R/L = 1: Shift to the right

R/L = 0: Shift to the left

DL = 1: 8 bits, DL = 0: 4 bits

A_CG

A_DD

:

CG RAM address

:

DD RAM address

(corresponds to

cursor address)

N

= 1: 2 lines, N = 0: 1 line

ASEG: Segment RAM

address

HDS: Horizontal dot scroll

quantity

RE = 1: Extension register access enable

BE = 1: CGRAM/SEGRAM blinking enable

LP = 1: Low power mode

BF = 1: Internally operating

BF = 0: Instructions acceptable

AC:

Address counter

used for both DD, CG,

and SEG RAM

addresses.

Notes: 1. — indicates no effect.

* After execution of the CG RAM/DD RAM/SEGRAM data write or read instruction, the RAM

address counter is incremented or decremented by 1. The RAM address counter is updated

after the busy flag turns off.

In figure 13, t_ADDis the time elapsed after the busy flag turns off until the address counter is

updated.

2. Extension time changes as frequency changes. For example, when f is 300 kHz, the execution

time is: 37 µs × 270/300 = 33 µs.

3. Execution time in a low power mode (LP = 1 & EXT = low) becomes four times as long as for a

1-line mode, and twice as long as for a 2- or 4-line mode.

366

HD66710

Busy state

(DB₇pin)

Busy state

Address counter

(DB₀to DB₆pins)

A

A + 1

t_ADD

Note: t _ADDdepends on the operation frequency

t _ADD= 1.5/(f_cpor f_OSC) seconds

Figure 13 Address Counter Update

367

HD66710

Instruction Description

Clear Display

Display On/Off Control

When extension register enable bit (RE) is 0, bits

D, C, and B are accessed.

Clear display writes space code (20)H (character

pattern for character code (20)H must be a blank

pattern) into all DD RAM addresses. It then sets

DD RAM address 0 into the address counter, and

returns the display to its original status if it was

shifted. In other words, the display disappears and

the cursor or blinking goes to the left edge of the

display (in the first line if 2 lines are displayed). It

also sets I/D to 1 (increment mode) in entry mode.

S of entry mode does not change. It resets the ex-

tended register enable bit (RE) to 0 in function set.

D: The display is on when D is 1 and off when D

is 0. When off, the display data remains in

DD RAM, but can be displayed instantly by setting

D to 1.

C: The cursor is displayed when C is 1 and not

displayed when C is 0. Even if the cursor dis-

appears, the function of I/D or other specifications

will not change during display data write. The

cursor is displayed using 5 dots in the 8th line for 5

× 8 dot character font.

Return Home

Return home sets DD RAM address 0 into the

address counter, and returns the display to its

original status if it was shifted. The DD RAM

contents do not change.

B: The character indicated by the cursor blinks

when B is 1 (figure 14). The blinking is displayed

as switching between all blank dots and displayed

characters at a speed of 370-ms intervals when f

cp

or f

is 270 kHz. The cursor and blinking can be

The cursor or blinking go to the left edge of the

display (in the first line if 2 lines are displayed). It

resets the extended register enable bit (RE) to 0 in

function set.

OSC

set to display simultaneously. (The blinking fre-

quency changes according to f or the reciprocal

of f . For example, when f is 300 kHz, 370 ×

OSC

cp

270/300 = 333 ms.)

Entry Mode Set

Extended Function Set

I/D: Increments (I/D = 1) or decrements (I/D = 0)

the DD RAM address by 1 when a character code

is written into or read from DD RAM.

When the extended register enable bit (RE) is 1,

FW, B/W, and NW bit shown below are accessed.

Once these registers are accessed, the set values

are held even if the RE bit is set to zero.

The cursor or blinking moves to the right when

incremented by 1 and to the left when decremented

by 1. The same applies to writing and reading of

CG RAM and SEG RAM.

FW: When FW is 1, each displayed character is

controlled with a 6-dot width. The user font in

CG RAM is displayed with a 6-bit character width

from bits 5 to 0. As for fonts stored in CG ROM,

no display area is assigned to the leftmost bit, and

the font is displayed with a 5-bit character width. If

the FW bit is changed, data in DD RAM and CG

RAM SEG RAM is destroyed. Therefore, set FW

before data is written to RAM. When font width is

set to 6 dots, the frame frequency decreases to 5/6

compared to 5-dot time. See “Oscillator Circuit”

for details.

S: Shifts the entire display either to the right (I/D =

0) or to the left (I/D = 1) when S is 1 during DD

RAM write. The display does not shift if S is 0.

If S is 1, it will seem as if the cursor does not move

but the display does. The display does not shift

when reading from DD RAM. Also, writing into or

reading out from CG RAM and SEG RAM does

not shift the display. In a low power mode (LP =

1), do not set S = 1 because the whole display does

not normally shift.

368

HD66710

B/W: When B/W is 1, the character at the cursor

position is cyclically displayed with black-white

invertion. At this time, bits C and B in display

on/off control register are “Don’t care”. When f_CP

or f_OSCis 270 kHz, display is changed by

switching every 370 ms.

NW: When NW is 1, 4-line display is performed.

At this time, bit N in the function set register is

“Don’t care”.

Note: After changing the N or NW or LP bit,

please issue the return home or clear display

instructions to cancel to shift display.

Alternating

display

i) Cursor display example

ii) Blink display example

Alternating

display

iii) White-black inverting

display example

Figure 14 Cursor Blink Width Control

i) 5-dot character width

ii) 6-dot character width

Figure 15 Character Width Control

369

HD66710

Cursor or Display Shift

In low power mode (LP = 1), whole-display shift

cannot be normally performed.

Cursor or display shift shifts the cursor position or

display to the right or left without writing or

reading display data (table 8). This function is used

to correct or search the display. In a 2-line display,

the cursor moves to the second line when it passes

the 40th digit of the first line. In a 4-line display,

the cursor moves to the second line when it passes

the 20th character of the line. Note that, all line

displays will shift at the same time. When the

displayed data is shifted repeatedly each line

moves only horizontally. The second line display

does not shift into the first line position.

Function Set

Only when the extended register enable bit (RE) is

1, the BE bit shown below can be accessed. Bits

DL and N can be accessed regardless of RE.

DL: Sets the interface data length. Data is sent or

received in 8-bit lengths (DB to DB ) when

DL is 1, and in 4-bit lengths (DB to DB ) when

DL is 0.

7

0

7

4

When 4-bit length is selected, data must be sent or

received twice.

These instruction reset the extended register enable

bit (RE) to 0 in function set.

The address counter (AC) contents will not change

if the only action performed is a display shift.

Table 10

Shift Function

S/C

0

R/L

0

Shifts the cursor position to the left. (AC is decremented by one.)

Shifts the cursor position to the right. (AC is incremented by one.)

Shifts the entire display to the left. The cursor follows the display shift.

Shifts the entire display to the right. The cursor follows the display shift.

0

1

0

1

370

HD66710

N: When bit NW in the extended function set is 0,

a 1- or a 2-line display is set. When N is 0, 1-line

display is selected; when N is 1, 2-line display is

selected. When NW is 1, a 4-line display is set. At

this time, N is “Don’t care”.

clock, and in a 2-line or a 4-line display mode, the

HD66710 operates on a 2-division clock. Accord-

ing to these operations, instruction execution takes

four times or twice as long. Notice that in a low

power mode, display shift cannot be performed.

RE: When the RE bit is 1, bit BE and LP in the

extended function set registe, the SEGRAM

address set register, and the extended function set

register can be accessed. When bit RE is 0, the

registers described above cannot be accessed, and

the data in these registers is held.

Note: Perform the DL, N, NW, FW functions at

the head of the program before executing

any instructions (except for the read busy

flag and address instruction). From this

point, if bit N, NW, or FW is changed after

other instructions are executed, RAM con-

tents may be lost.

To maintain compatibility with the HD44780, the

RE bit should be fixed to 0.

After changing the N or NW or LP bit,

please issue the return home or clear display

instruction cancel to shift display.

Clear display, return home and cursor or display

shift instruction a reset the RE bit to 0.

Set CG RAM Address

BE: When the RE bit is 1, this bit can be rewritten.

When this bit is 1, the user font in CGRAM and

the segment in SEGRAM can be blinked according

to the upper two bits of CGRAM and SEGRAM.

A CG RAM address can be set while the RE bit is

cleared to 0. Set CG RAM address sets the

CG RAM address binary AAAAAA into the

address counter.

LP: When the RE bit is 1, this bit can be rewritten.

When LP is set to 1 and the EXT pin is low

(without an extended driver), the HD66710

operates in low power mode. In 1-line display

mode, the HD66710 operates on a 4-division

Data is then written to or read from the MPU for

CG RAM.

Table 11 Display Line Set

No. of

Display

Lines

Character

Font

Duty

Factor

Maximum Number of Characters/

1 Line with Extended Drivers

N

0

1

*

NW

0

1

2

4

5 × 8 dots

1/17

1/33

50 characters

30 characters

20 characters

0

1

Note: * Indicates don’t care.

371

HD66710

Set DD RAM Address

Note: When performing a horizontal scroll is

described above by connecting an extended

driver, the maximum number of characters

per line decreases by one. In other words,

49 characters, 29 characters, and 19 char-

acters are displayed in 1-line, 2-line, and

4-line modes, respectively. Notice that in

low power mode (LP = 1), the display shift

and scroll cannot be performed.

Set DD RAM address sets the DD RAM address

binary AAAAAAA into the address counter while

the RE bit is cleared to 0.

Data is then written to or read from the MPU for

DD RAM.

However, when N and NW is 0 (1-line display),

AAAAAAA can be 00H to 4FH. When N is 1 and

NW is 0 (2-line display), AAAAAAA is (00)H to

(27)H for the first line, and (40)H to (67)H for the

second line. When NW is 1 (4-line display),

AAAAAAA is (00)H to (13)H for the first line,

(20)H to (33)H for the second line, (40)H to (53)H

for the third line, and (60)H to (73)H for the fourth

line.

Read Busy Flag and Address

Read busy flag and address reads the busy flag

(BF) indicating that the system is now internally

operating on a previously received instruction. If

BF is 1, the internal operation is in progress. The

next instruction will not be accepted until BF is

reset to 0. Check the BF status before the next

write operation. At the same time, the value of the

address counter in binary AAAAAAA is read out.

This address counter is used by all CG, DD, and

SEGRAM addresses, and its value is determined

by the previous instruction. The address contents

are the same as for CG RAM, DD RAM, and

SEGRAM address set instructions.

Set SEGRAM Address

Only when the extended register enable bit (RE) is

1, HS2 to HS0 and the SEGRAM address can be

set.

The SEGRAM address in the binary form AAA is

set to the address counter. SEGRAM can then be

written to or read from by the MPU.

Table 12

HS2 to HS0 Settings

HS2

0

HS1

HS0

Description

No shift.

0

1

0

1

0

1

Shift the display position to the left by one dot.

Shift the display position to the left by two dots.

Shift the display position to the left by three dots.

Shift the display position to the left by four dots.

Shift the display position to the left by five dots.

No shift.

0

1

0

1

0 or 1

372

HD66710

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

Clear

display

Code

0

1

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

Return

home

Note: * Don’t care.

0

1

*

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

I/D

Entry

mode set

0

1

S

RS R/W DB₇DB₆DB₅DB₄DB DB₂DB₁DB₀

3

Display

on/off control

0

1

D

C

B

DB₄

0

DB₃

1

DB₂DB₁DB₀

FW B/W NW

RS R/W DB₇DB₆DB₅

RE = 1

Code

Extended

function set

0

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

Cursor or

display shift

Code

0

1

S/C R/L

*

Note: * Don’t care.

Note: * BE and LP

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂

DB₀

DB₁

*

Function set

0

1

DL

N

RE

LP

BE

can be rewritten

while RE = 1.

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

Set CG

RAM address

RE = 0

Code

0

1

A

Highest

order bit

Lowest

order bit

Figure 16 Character Width Control

373

HD66710

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

0

1

A

Set DDRAM

address

RE = 0

Highest

order bit

Lowest

order bit

DB₆DB

DB₃

DB₂DB₁DB₀

RS R/W DB₇

DB₄

HS₀

5

RE = 1

Code

Set SEGRAM

address

0

1

A

HS₂HS₁

*

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

Read busy flag

and address

0

1

BF

A

Highest

order bit

Lowest

order bit

Figure 16 Character Width Control (cont)

374

HD66710

Write Data to CG, DD, or SEG RAM

set instruction need not be executed just before this

read instruction when shifting the cursor by a

cursor shift instruction (when reading from DD

RAM). A cursor shift instruction is the same as a

set DD RAM address instruction.

This instruction writes 8-bit binary data

DDDDDDDD to CG, DD or SEGRAM. If the

RE bit is cleared, CG or DD RAM is selected, as

determined by the previous specification of the

address set instruction; if the RE bit is set, SEG

RAM is selected. After a write, the address is

automatically incremented or decremented by 1

according to the entry mode. The entry mode also

determines the display shift direction.

After a read, the entry mode automatically in-

creases or decreases the address by 1. However, a

display shift is not executed regardless of the entry

mode.

Note: The address counter (AC) is automatically

incremented or decremented after write in-

structions to CG, DD or SEG RAM. The

RAM data selected by the AC cannot be

read out at this time even if read instruc-

tions are executed. Therefore, to read data

correctly, execute either an address set in-

struction or a cursor shift instruction (only

with DD RAM), or alternatively, execute a

preliminary read instruction to ensure the

address is correctly set up before accessing

the data.

Read Data from CG, DD, or SEG RAM

This instruction reads 8-bit binary data

DDDDDDDD from CG, DD, or SEG RAM. If the

RE bit is cleared, CG or DD RAM is selected, as

determined by the previous specification of the

address set instruction; if the RE bit is set, SEG

RAM is selected. If no address is specified, the

first data read will be invalid. When executing

serial read instructions, the next address is

normally read from the next address. An address

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

Write data to

CG, DD, or SEG RAM

1

0

D

RE = 0/1

Code

Higher

Lower

order bits

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

RE = 0/1

Code

Read data from

CG, DD, or SEG RAM

1

D

Higher

Lower

order bits

Figure 16 Character Width Control (cont)

375

HD66710

Interfacing the HD66710

1) Interface to 8-Bit MPUs

port. When number of I/O port in MCU, or

interfacing bus width, 4-bit interface function

is useful.

HD66710 can interface to 8-bit MPU directly

with E clock, or to 8-bit MCU through I/O

RS

R/W

E

Internal

signal

Internal operation

Busy

Not

Busy

DB7

Data

Busy

Instruction

write

Instruction

write

Busy flag check Busy flag check Busy flag check

Figure 17 Example of 8-Bit Data Transfer Timing Sequence

376

HD66710

i) Connection to 8-bit MPU bus line

VMA

ø2

E

HD6800

A15

HD66710

A0

R/W

RS

R/W

DB0–DB7

D0–D7

8

ii) Connection to H8/325 with port (when single chip mode)

C0

C1

C2

E

H8/325

HD66710

RS

R/W

8

A0–A7

DB0–DB7

iii) Connection to HD6301 with port

P34

RS

HD6301

HD66710

P35

P36

R/W

E

8

P10–P17

DB0–DB7

Figure 18 8-Bit MPU Interface

377

HD66710

2) Interface to 4-Bit MPUs

must be transferred twice continuously. The

DL bit in function set selects the interface data

length.

HD66710 can interface to 4-bit MCU through

I/O port. 4-bit data for high and low order

RS

R/W

E

Internal

signal

Internal operation

Not

Busy

Busy AC3

AC3

D7

D3

DB7

IR7 IR3

Instruction

write

Instruction

write

Busy flag check

Figure 19 Example of 4-Bit Data Transfer Timing Sequence

HMCS4019R

HD66710

COM1–

16

40

D15

D14

D13

RS

R/W

E

COM16

Connected to

the LCD

SEG1–

SEG40

4

R10–R13

DB4 –DB7

Figure 20 Interface to HMCS4019R

378

HD66710

Oscillator Circuit

The liquid crystal display frame frequencies of

figure 22 apply only when the oscillation

frequency is 270 kHz (one clock period: 3.7 µs).

• Relationship between Oscillation frequency and

Liquid Crystal Display Frame Frequency

1) When an external clock is used

2) When an internal oscillator is used

The oscillator frequency can be

adjusted by oscillator resistance

(Rf). If Rf is increased or power

supply voltage is decreased, the

oscillator frequency decreases.

The recommended oscillator

resistor is as follows.

Clock

OSC1

OSC2

Rf

HD66710

• Rf = 91 kΩ ± 2% (Vcc = 5 V)

• Rf = 75 kΩ ± 2% (Vcc = 3 V)

Figure 21 Oscillator Circuit

(1) 1 /17 duty cycle

200 clocks (6-dot font width: 240 clocks)

1

2

3

4

16 17

1

2

3

16 17

Vcc

V1

COM1

V4

V5

1 frame

Normal Display Mode (LP = 0)

5-Dot Font Width 6-Dot Font Width

Low Power Mode (LP = 1)

5-Dot Font Width 6-Dot Font Width

Item

Line selection period 200 clocks

Frame frequency

240 clocks

66.2 Hz

50 clocks

79.4 Hz

60 clocks

66.2 Hz

79.4 Hz

(2) 1 /33 duty cycle

100 clocks (6-dot font width: 120 clocks)

1

2

3

4

32 33

1

2

3

32 33

Vcc

V1

COM1

V4

V5

1 frame

Normal Display Mode (LP = 0)

5-Dot Font Width 6-Dot Font Width

Low Power Mode (LP = 1)

5-Dot Font Width 6-Dot Font Width

Item

Line selection period 100 clocks

Frame frequency

120 clocks

68.2 Hz

50 clocks

81.8 Hz

60 clocks

68.2 Hz

81.8 Hz

Figure 22 Frame Frequency

379

HD66710

Power Supply for Liquid Crystal

Display Drive

1) When an external power supply is used

Vcc

V1

V2

V3

V4

V5

R

R0

R

VR

V_EE

2) When an internal booster is used

(Boosting twice)

(Boosting three times)

V_CC

V1

V2

V3

V4

V5

V_CC

Vci

NTC-type

thermistor

Vci

NTC-type

thermistor

R

V1

GND

V2

GND

R0

R

GND

R0

R

C1

C2

C1

V3

C2

1µF

+

V4

V5OUT2

V5OUT3

V5OUT2

R

V5

1µF

V5OUT3

1µF

+

GND

Notes: 1. Boosting output voltage should not exceed the power supply voltage (2) (15 V max.)

in the absolute maximum ratings. Especially, voltage of over 5 V should not be input

to the reference voltage (Vci) when boosting three times.

2. Vci input terminal is used for reference voltage and power supply for the internal booster.

Input current into the Vci pin needs three times or more of load current through the

bleeder resistor for LCD. So, when it adjusts LCD driving voltage (Vlcd), input voltage

should be controlled with transistor to supply LCD load current.

3. Please notice connection (+/–) when it uses capacitors with poler.

380

HD66710

Table 13

Duty Factor and Power Supply for Liquid Crystal Display Drive

Item

Data

Number of Lines

Duty factor

1

2/4

1/17

1/5

R

1/33

1/6.7

R

Bias

Divided resistance

R

R0

R

2.7R

Note: R changes depending on the size of liquid crystal penel. Normally, R must be 4.7 kΩ to 20 kΩ.

381

HD66710

Extension Driver LSI Interface

the character baundary, the Seg1 output is used for

the 5-dot font width. For the 6-dot font width, the

SEG36 output is used, and the Seg1 output of the

extension driver must not be used. When the

extension driver LSI interface is used, ground level

(GND) must be higher than the V5 level.

By bringing the EXT pin high, segment driver pins

(SEG37 to SEG40) functions as the extended driver

interface outputs. From these pins, a latch pulse

(CL1), a shift clock (CL2), data (D), and an AC

signal (M) are output. The same data is output

from the SEG36 pin of the HD66710 and the start

segment pin (Seg1) of the extension driver. Due to

Table 14

Required Number of 40-Output Extension Driver

Controller

Display Line

16 × 2 lines

20 × 2 lines

24 × 2 lines

40 × 2 lines

12 × 4 lines

16 × 4 lines

20 × 4 lines

HD66710*

6-Dot Width

HD44780

HD66702

5-Dot Width

Not required

1

5-Dot Width

Not required

1

2

1

2

Disabled

4

3

1

2

1

2

3

Disabled

Note: * The number of display lines can be extended to 30 × 2 lines or 20 × 4 lines.

1) 1-chip operation

2) When using the extension driver

(EXT = High, 5-dot font width)

(EXT = Low, 5-dot font width)

Vcc

EXT

HD66710

GND

EXT

COM1–

COM33

24 × 2-line display

SEG1–

SEG35

COM1–

COM33

HD66710

16 × 2-line display

SEG1–

SEG40

M

D

Seg1–

Seg35

SEG1–SEG40

CL2

CL1

Extension driver

Figure 23 HD66710 and the Extension Driver Connection

382

HD66710

When using one HD66710, the start address of

COM9–COM16/COM25–COM33 is calculated by

adding 8 to the start address of COM9–COM16

COM25–COM32. When extending the address, the

start address is calculated by adding A(10) to

COM9–COM16/COM25 to COM32. The relation-

ship betweenmodes and display start addresses is

shown below.

Table 15

Display Start Address in Each Mode

Number of Lines

1-Line Mode

2-Line Mode

EXT Low EXT High

4-Line Mode

EXT Low/High

D00±1

Output

EXT Low

D00±1

D08±1

—

EXT High

D00±1

D0A±1

—

COM1–COM8

COM9–COM16

COM17–COM24

COM25–COM32

COM17

D00±1

D08±1

D40±1

D48±1

—

D00±1

D0A±1

D40±1

D4A±1

—

D20±1

D40±1

—

D60±1

S00

—

COM33

—

S00

Notes: 1. When an EXT pin is low, the extension driver is not used; otherwise, the extension driver is

used.

2. D— is the start address of display data RAM (DDRAM) for each display line.

3. S— is the start address of segment RAM (SEGRAM).

4. ±1 following D— indicates increment or decrement at display shift.

383

HD66710

a) 5-dot font width: 20 × 2-line display

1 2

3

4

5

6

7

8 9 10 11 121314 151617 1819 20

00 01 02 03 04 05 06

07 08 09

0A 0B 0C 0D 0E 0F 10

11 12 13

COM1–COM8

COM9–COM16

COM25–COM32

45

47

4A 4B

4D 4E 4F 50

51

40 41 42 43 44

46

48 49

4C

52

53

COM17–COM24

HD66710

SEG1–SEG35

Extension

driver (1)

Seg1–Seg15

HD66710

SEG1–SEG35 driver (1)

Seg1–Seg15

Extension

b) 6-dot font width: 20 × 2-line display

2 3

1

4

5

6

7 8 9 10 1112131415 16 171819 20

00 01 02 03 04 05

06 07 08 09

0A 0B 0C 0D 0E 0F

10 11 12 13

COM1–COM8

COM9–COM16

COM25–COM32

40 41 42 43 44 45

46 47 48 49

4A 4B 4C 4D 4E 4F

50 51 52 53

COM17–COM24

HD66710

Extension

HD66710

Extension

SEG1–SEG36 driver (1)

Seg2–Seg25

SEG1–SEG36 driver (1)

Seg2–Seg25

(Seg1 is

skipped)

(Seg1 is skipped)

c) 5-dot font width: 24 × 2-line display

1

2

3

4

5

6

7

13141516 17 1819 202122 2324

8 9 101112

00 01 02 03 04 05 06

07 08 09 0A 0B

0C 0D 0E 0F 10

11 12 13 14 15 16 17

COM1–COM8

COM9–COM16

COM25–COM32

40 41 42 43 44 45 46

47 48 49 4A 4B

4C 4D 4E 4F 50

51 52 53 54 55 56 57

COM17–COM24

HD66710

SEG1–SEG35

Extension

driver (1)

HD66710

SEG11–SEG35

Extension

driver (1)

Seg1–Seg15 (SEG1–SEG10

are skipped)

Seg1–Seg35

d) 6-dot font width: 24 × 2-line display

1

2

3

4

5

6

7

13141516 171819 202122 2324

8 9 101112

00 01 02 03 04 05

06 07 08 09 0A 0B

0C 0D 0E 0F

10 11 12 13 14 15 16 17

COM1–COM8

COM9–COM16

COM25–COM32

40 41 42 43 44 45

46 47 48 49 4A 4B

4C 4D 4E 4F

50 51 52 53 54 55 56 57

COM17–COM24

HD66710

SEG1–SEG36

Extension

driver (1)

HD66710

SEG13–SEG36 driver (1)

Extension

driver (2)

Seg2–Seg37 (SEG1–SEG12 Seg2–Seg40 Seg1–Seg9

(SEG1 is

skipped)

are skipped)

(SEG1 is

skipped)

Figure 24 Correspondence between the Display Position at Extension Display and

the DDRAM Address

384

HD66710

e) 5-dot font width: 20 × 4-line display

2 3 4 5 6

1

7

8 9 10111213141516171819 20

00 01 02 03 04 05 06

20 21 22 23 24 25 26

40 41 42 43 44 45 46

07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13

COM1–COM8

COM9–COM16

COM17–COM24

27 28 29

2A

2B

2C 2D

2E

2F 61 62 63

60

47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53

60

62

66

67 68

61

63 64 65

69 6A

6B 6C 6D 6E 6F 70 71 72 73

COM25–COM32

HD66710

SEG1–SEG35

Extension

driver (1)

Extension

driver (2)

Seg1–Seg40

Seg1–Seg25

f) 6-dot font width: 20 × 4-line display

00 01 02 03 04 05

06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13

COM1–COM8

COM9–COM16

COM17–COM24

COM25–COM32

27 28 29

2A

2B

2C 2D

2E

2F 61 62 63

60

20 21 22 23 24 25

40 41 42 43 44 45

26

46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53

60

62

66 67

61

63 64 65

68 69 6A 6B 6C 6D 6E 6F 70 72 73

71

HD66710

SEG1–SEG36

Extension

driver (1)

Extension

driver (2)

Extension

driver (3)

Seg2–Seg40

(Seg1 is skipped)

Seg1–Seg40 Seg1–Seg5

Figure 24 Correspondence between the Display Position at Extension Display and

the DDRAM Address (cont)

385

HD66710

Interface to Liquid Crystal Display

respectively. The relationship between the EXT

pin, register set value, and the display lines are

given below.

Set the extended driver interface, the number of

display lines, and the font width with the EXT pin,

an extended register NW, and the FW bit,

Table 16

Relationship between EXT, Register Setting, and Display Lines

5-Dot Font

6-Dot Font

No. of No. of

EXT Extended

Lines Charactrers Pin Driver

N

0

1

*

RE NW FW Pin Driver

N

0

1

*

RE NW FW Duty

1

2

4

16

20

24

16

20

24

16

20

24

L

—

1

0

1

0

1

0

H

1

2

1

2

1

2

3

1

0

1

1/17

1/33

H

L

1

—

1

H

1

2

*

2

*

Note: — means not required.

386

HD66710

• Example of 5-dot font width connection

1

8

9

16

HD66710

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

±

+ – x ÷ = ≠

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG40

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

EXT

a) 16 × 1-line + 40-segment display (5-dot font, 1/17 duty)

1

8

9

16

HD66710

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM33

± + – x ÷ = ≠

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG40

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

EXT

b) 16 × 2-line + 40-segment display (5-dot font, 1/33 duty)

Figure 25 Liquid Crystal Display and HD66710 Connections (Single-Chip Operation)

387

HD66710

1

7

8

10

11

17

18

20

HD66710

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

±

+ – x ÷ = ≠

COM33

SEG1

SEG2

SEG3

SEG4

SEG5

SEG31

SEG32

SEG33

SEG34

SEG35

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

Vcc

EXT

Extension

driver

SEG1

SEG2

SEG3

SEG4

SEG5

SEG11

SEG12

SEG13

SEG14

SEG15

a) 20 × 2-line + 40-segment display (5-dot font, 1/33 duty)

3

8

1

7

12

13

17

18

20

24

HD66710

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

±

+

– x ÷ = ≠

COM33

SEG1

SEG2

SEG3

SEG4

SEG5

SEG11

SEG12

SEG13

SEG14

SEG15

SEG31

SEG32

SEG33

SEG34

SEG35

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

Vcc

COM30

COM31

COM32

EXT

Extension

driver

SEG1

SEG2

SEG3

SEG4

SEG5

SEG11

SEG12

SEG13

SEG14

SEG15

SEG31

SEG32

SEG33

SEG34

SEG35

b) 24 × 2-line + 40-segment display (5-dot font, 1/33 duty)

Figure 26 Liquid Crystal Display and HD66710 Connections (with the Extended Driver)

388

HD66710

1

7

8

15

16

20

HD66710

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM23

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

± + – x ÷ = ≠

SEG1

SEG2

SEG3

SEG4

SEG5

SEG31

SEG32

SEG33

SEG34

SEG35

Vcc

EXT

SEG1

SEG2

SEG3

SEG4

SEG5

Extension

driver

(1)

SEG36

SEG37

SEG38

SEG39

SEG40

SEG1

SEG2

SEG3

SEG4

SEG5

Extension

driver

(2)

SEG21

SEG22

SEG23

SEG24

SEG25

c) 20 × 4-line + 40-segment display (5-dot font, 1/33 duty)

Figure 26 Liquid Crystal Display and HD66710 Connections (with the Extended Driver) (cont)

389

HD66710

• Example of 6-dot font width connection

1

2

6

7

8

12

HD66710

Note: The DDRAM address between

6th and 7th digits is not contiguous.

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

±

+

– x ÷ = ≠

COM33

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG36

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

EXT

a) 12 × 2-line + 36-segment display (6-dot font, 1/33 duty)

1

6

10

11

16

17

20

7

HD66710

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

±

+ – x ÷ = ≠

COM33

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

Vcc

EXT

Extension _SEG2

SEG3

driver

SEG4

SEG5

SEG6

SEG7

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

b) 20 × 2-line + 36-segment display (6-dot font, 1/33 duty)

Figure 27 Liquid Crystal Display and HD66710 Connections (6-Dot Font Width)

390

HD66710

Instruction and Display Correspondence

40th digit of the first line has been written. Thus,

if there are only 16 characters in the first line,

the DD RAM address must be again set after the

16th character is completed. (See table 17.)

• 8-bit operation, 16-digit × 1-line display with

internal reset

Refer to table 16 for an example of an 16-digit ×

1-line display in 8-bit operation. The HD66710

functions must be set by the function set

instruction prior to the display. Since the display

data RAM can store data for 80 characters, a

character unit scroll can be performed by a

display shift instruction. A dot unit smooth

scroll can also be performed by a horizontal

scroll instruction. Since data of display RAM

(DDRAM) is not changed by a display shift

instruction, the display can be returned to the

first set display when the return home operation

is performed.

The display shift is performed for the first and

second lines. If the shift is repeated, the display

of the second line will not move to the first line.

The same display will only shift within its own

line for the number of times the shift is repeated.

• 8-bit operation, 8-digit × 4-line display with

internal reset

The RE bit must be set by the function set

instruction and then the NW bit must be set by

an extension function set instruction. In this

case, 4-line display is always performed regard-

less of the N bit setting (table 18).

• 4-bit operation, 16-digit × 1-line display with

internal reset

In a 4-line display, the cursor automatically

moves from the first to the second line after the

20th digit of the first line has been written. Thus,

if there are only 8 characters in the first line, the

DD RAM address must be set again after the 8th

character is completed. Display shifts are per-

formed on all lines simultaneously.

The program must set all functions prior to the

4-bit operation (table 16). When the power is

turned on, 8-bit operation is automatically

selected and the first write is performed as an

8-bit operation. Since DB to DB are not con-

0

3

nected, a rewrite is then required. However,

since one operation is completed in two accesses

for 4-bit operation, a rewrite is needed to set the

Note: When using the internal reset, the electrical

characteristics in the Power Supply Condi-

tions Using Internal Reset Circuit table

must be satisfied. If not, the HD66710 must

be initialized by instructions. See the sec-

tion, Initializing by Instruction.

functions (see table 16). Thus, DB to DB of

4

7

the function set instruction is written twice.

• 8-bit operation, 16-digit × 2-line display with

internal reset

For a 2-line display, the cursor automatically

moves from the first to the second line after the

391

HD66710

Table 17

8-Bit Operation, 16-Digit × 1-Line Display Example with Internal Reset

Instruction

Step

No. RS R/W D₇D₆D₅D₄D₃D₂D₁D₀

Display

Operation

1

Power supply on (the HD66710 is initialized by

the internal reset circuit)

Initialized. No display.

2

Function set

Sets to 8-bit operation and

selects 1-line display.

Bit 2 must always be cleared.

0

1

0

1

0

1

*

1

*

0

3

4

Display on/off control

Turns on display and cursor.

Entire display is in space mode

because of initialization.

_

0

Entry mode set

Sets mode to increment the

address by one and to shift the

cursor to the right at the time of

write to the RAM.

0

Display is not shifted.

5

Write data to CG RAM/DD RAM

Writes H. DD RAM has

already been selected by

initialization when the power

was turned on.

H_

1

0

1

0

1

0

1

6

7

Write data to CG RAM/DD RAM

Writes I.

HI_

1

0

1

0

1

·

8

Write data to CG RAM/DD RAM

HITACHI_

1

0

1

0

1

0

1

0

1

0

1

0

9

Entry mode set

Sets mode to shift display at

the time of write.

HITACHI_

0

10

Write data to CG RAM/DD RAM

Writes a space.

ITACHI

_

1

0

1

0

392

HD66710

Table 17

8-Bit Operation, 16-Digit × 1-Line Display Example with Internal Reset (cont)

Instruction

Step

No. RS R/W D₇D₆D₅D₄D₃D₂D₁D₀

Display

Operation

11

Write data to CG RAM/DD RAM

Writes M.

TACHI M_

1

0

1

0

1

0

1

12

·

13

14

15

16

17

18

19

20

Write data to CG RAM/DD RAM

Writes O.

MICROKO_

MICROK_O

ICROCO_

1

0

1

0

1

0

1

0

1

*

1

*

0

1

*

1

*

1

Cursor or display shift

0

Shifts only the cursor position

to the left.

0

Cursor or display shift

0

Shifts only the cursor position

to the left.

0

Write data to CG RAM/DD RAM

Writes C over K.

The display moves to the left.

1

0

1

0

1

0

1

0

Cursor or display shift

0

Shifts the display and cursor

position to the right.

MICROCO_

ICROCOM_

0

Cursor or display shift

0

Shifts the display and cursor

position to the right.

0

Write data to CG RAM/DD RAM

Writes M.

1

0

1

0

1

·

21

Return home

0

Returns both display and cursor

to the original position

(address 0).

H_ITACHI

0

1

0

393

HD66710

Table 18

4-Bit Operation, 16-Digit × 1-Line Display Example with Internal Reset

Instruction

Step

No. RS R/W D₇D₆D₅D₄D₃D₂D₁D₀

Display

Operation

1

Power supply on (the HD66710 is initialized by

the internal reset circuit)

Initialized. No display.

2

Function set

Sets to 4-bit operation.

Clear bit 2. In this case,

operation is handled as 8 bits

by initialization. *

0

—

1

—

0

—

3

Function set

Sets 4-bit operation and selects

1-line display. Clear BE, LP bits.

4-bit operation starts from

this step.

0

1

0

—

4

5

6

7

Function set

Sets 4-bit operation and selects

1-line display. Clear RE bit.

0

1

*

0

*

—

Return home

Returns both display and cursor

to the original position

(address 0).

0

1

0

—

Display on/off control

Turns on display and cursor.

Entire display is in space mode

because of initialization.

_

0

1

0

1

0

1

0

—

Entry mode set

Sets mode to increment the

address by one and to shift the

cursor to the right at the time of

write to the DD/CG RAM.

Display is not shifted.

0

1

0

1

0

—

8

Write data to CG RAM/DD RAM

Writes H.

DDRAM has already been

selected by initialization.

H_

1

0

1

0

—

Note: 1. The control is the same as for 8-bit operation beyond step #8.

2. When DB3 to DB0 pins are open in 4-bit mode, the RE, BE, LP bits are set to “1” at step #2.

So, these bits are clear to “0” at step #3.

394

HD66710

Table 19

8-Bit Operation, 16-Digit × 2-Line Display Example with Internal Reset

Instruction

Step

No. RS R/W D₇D₆D₅D₄D₃D₂D₁D₀

Display

Operation

1

2

3

4

Power supply on (the HD66710 is initialized by

the internal reset circuit)

Initialized. No display.

Function set

Sets to 8-bit operation and

selects 1-line display.

Clear bit 2.

0

1

0

1

0

1

*

1

*

0

Display on/off control

0

Turns on display and cursor.

All display is in space mode

because of initialization.

_

0

Entry mode set

0

Sets mode to increment the

address by one and to shift the

cursor to the right at the time of

write to the RAM.

0

Display is not shifted.

5

6

Write data to CG RAM/DD RAM

Writes H. DD RAM has

already been selected by

initialization when the power

was turned on.

H_

1

0

1

0

1

0

·

7

8

Write data to CG RAM/DD RAM

Writes I.

HITACHI_

1

0

1

0

1

0

1

0

Set DD RAM address

Sets RAM address so that the

cursor is positioned at the head

of the second line.

HITACHI

_

0

1

0

395

HD66710

Table 19

8-Bit Operation, 16-Digit × 2-Line Display Example with Internal Reset (cont)

Instruction

Step

No. RS R/W D₇D₆D₅D₄D₃D₂D₁D₀

Display

Operation

9

Write data to CG RAM/DD RAM

Writes a space.

HITACHI

M_

1

0

1

0

1

0

1

10

·

11

12

13

14

Write data to CG RAM/DD RAM

Writes O.

HITACHI

1

0

1

0

1

0

1

MICROCO_

Entry mode set

Sets mode to shift display at

the time of write.

HITACHI

0

MICROCO_

Write data to CG RAM/DD RAM

Writes M.

ITACHI

1

0

1

0

1

ICROCOM_

·

15

Return home

Returns both display and cursor

to the original position

(address 0).

H_ITACHI

0

1

0

MICROCOM

396

HD66710

Table 20

8-Bit Operation, 8-Digit × 4-Line Display Example with Internal Reset

Instruction

Step

No. RS R/W D₇D₆D₅D₄D₃D₂D₁D₀

Display

Operation

1

2

3

4

5

6

7

8

Power supply on (the HD66710 is initialized by

the internal reset circuit)

Initialized. No display.

Function set

Sets to 8 bit operation and the

extended register enable bit.

0

1

0

1

0

1

0

*

4-line mode set

0

Sets 4-line display.

0

1

Function set

Clear extended register enable bit

Clears the extended register

enable bit. Setting the N bit is

“don’t care”.

0

1

0

1

*

Display on/off control

0

Turns on display and cursor.

Entire display is in space mode

because of initialization.

_

0

1

0

Entry mode set

Sets mode to increment the

address by one and to shift the

cursor to the right at the time of

write to the RAM. Display is not

shifted.

_

0

1

0

1

0

Write data to CGRAM/DDRAM

1

Writes H. DDRAM has already

been selected by initialization

when the power was turned on.

H_

0

1

0

1

—

397

HD66710

Table 20

8-Bit Operation, 8-Digit × 4-Line Display Example with Internal Reset (cont)

Instruction

Step

No. RS R/W D₇D₆D₅D₄D₃D₂D₁D₀

Display

Operation

9

Write data to CGRAM/DDRAM

Writes I.

HITACHI_

1

0

1

0

1

0

1

0

10

11

Set DDRAM address

Sets RAM address so that the

cursor is positioned at the head

of the second line.

HITACHI

_

0

1

0

1

0

Write data to CGRAM/DDRAM

Writes 0.

HITACHI

0_

1

0

1

0

398

HD66710

Initializing by Instruction

tion by instructions becomes necessary.

If the power supply conditions for correctly operat-

ing the internal reset circuit are not met, initializa-

Power on

• Wait for more than 15 ms

after V_CCrises to 4.5 V

(V_CC= 5 V)

• Wait for more than 40 ms

after V_CCrises to 2.7 V

(V_CC= 3 V)

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

0

1

*

Wait for more than 4.1 ms

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

0

1

*

Wait for more than 100 µs

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

0

1

*

BF can be checked after the following instructions.

When BF is not checked, the waiting time between

instructions is longer than the execution instuction

time. (See table 7.)

RS R/W DB₇DB₆DB₅DB₄DB₃DB₂DB₁DB₀

Function set

0

1

N

0

*

0

*

0

1

S

Display off

0

1

0

1

0

Display clear

Entry mode set

I/D

Initialization ends

Figure 28 8-Bit Interface

399

HD66710

Power on

Important Notice

Notes: 1. When DB3 to DB0 pins are open in 4-bit mode,

the N, RE, BE, LP bits are set to “1”. In this case,

instruction time becomes four times in a low

power mode (LP = “1”).

• Wait for more than 15 ms

after V_CCrises to 4.5 V

(V_CC= 5 V)

• Wait for more than 40 ms

after V_CCrises to 2.7 V

(V_CC= 3 V)

2. The low power mode is available in this step, so

instruction time takes four times.

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

RS R/W DB₇DB₆DB₅DB₄

0

1

Wait for more than 4.1 ms

RS R/W DB₇DB₆DB₅DB₄

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

0

1

Wait for more than 100 µs

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

RS R/W DB₇DB₆DB₅DB₄

*1

0

1

BF can be checked after the following instructions.

When BF is not checked, the waiting time between

instructions is longer than the execution instuction

time. (See table 7.)

RS R/W DB₇DB₆DB₅DB₄

*1

*2

0

1

0

Function set (4-bit mode).

0

N

0

N

0

1

0

1

0

1

0

*

Function set (4-bit mode, N specification).

BE, LE are clear to “0”

1

Function set (4-bit mode, N specification).

*

0

1

0

S

Display off

0

Display clear

0

Entry mode set (I/D, S specification)

I/D

Initialization ends

Figure 29 4-Bit Interface

400

HD66710

Horizontal Dot Scroll

with character unit display shift instructions,

smooth horizontal scrolling can be performed on a

6-dot font width display as shown below.

Dot unit shifts are performed by setting the hori-

zontal dot scroll bit (HDS) when the extension

register is enabled (RE = 1). By combining this

6-dot font width (FW = 1)

No shift performed

5-dot font width (FW = 0)

No shift performed

Shift to the left by one dot

Shift to the left by two dots

Shift to the left by three dots

Shift to the left by four dots

Shift to the left by five dots

Shift to the left by three dots

Shift to the left by four dots

Figure 30 Shift in 5- and 6-Dot Font Width

(1) Method of smooth scroll to the left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Enable the extension register

1

2

0

1

DL

N

1

*

0

1

0

1

Shift the whole display to the left by one dot

*

CPU Wait

Shift the whole display to the left by two dots

Shift the whole display to the left by three dots

Shift the whole display to the left by four dots

Shift the whole display to the left by five dots^*1

3

4

5

6

0

1

0

1

0

*

CPU Wait

1

CPU Wait

0

CPU Wait

0

1

CPU Wait

7

8

0

1

0

Perform no shift

*

Shift the whole display to the left by one character^*2

0

1

0

CPU Wait

Notes: 1. When the font width is five (FW = 0), this step is skipped.

2. The extended register enable bit (RE) is cleared.

Figure 31 Smooth Scroll to the Left

401

HD66710

(2) Method of smooth scroll to the right

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Shift the whole display to the right by one

character ^*2

1

2

0

1

*

0

1

DL

N

1

Enable the extension register

*

CPU Wait

Shift the whole display to the left by five dots^*1

Shift the whole display to the left by four dots

3

4

5

6

7

8

0

1

0

1

*

CPU Wait

0

CPU Wait

1

Shift the whole display to the left by three dots

Shift the whole display to the left by two dots

CPU Wait

1

0

CPU Wait

0

1

Shift the whole display to the left by one dot

Perform no shift

CPU Wait

0

Notes: 1.

2.

When the font width is five (FW = 0), this step is skipped.

The extended register enable bit (RE) is cleared.

Figure 31 Smooth Scroll to the Left (cont)

402

HD66710

Low Power Mode

When LP bit is 1 and the EXT pin is low (without

an extended driver), the HD66710 operates in low

power mode. In 1-line display mode, the HD66710

operates on a 4-division clock, and in 2-line or 4-line

display mode, it operates on 2-division clock. So,

instruction execution takes four times or twice as

long. Notice that in this mode, display shift and

scroll cannot be performed. Clear display shift with

the return home instruction, and the horizontal

scroll quantity.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DL BE

Extended register enable

0

1

N

0

1

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AS2 AS1 AS0

Clear horizontal scroll quantity

HDS = “000”

0

1

0

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DL BE

Set a low power mode

Return home

0

1

N

1

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

Note: In this operation, instruction execution time

takes four times or twice as long.

Low power operation

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Reset a power mode

Return home

0

1

DL

N

BE

1

0

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

Figure 32 Low Power Mode Operation

403

HD66710

Absolute Maximum Ratings

Item

Symbol

Value

Unit

V

Notes*

Power supply voltage (1)

Power supply voltage (2)

Input voltage

V_CC

V_CC–V₅

V_t

–0.3 to +7.0

–0.3 to +15.0

–0.3 to V_CC+0.3

–20 to +75

–55 to +125

1

V

1, 2

1

V

Operating temperature

Storage temperature

T_opr

T_stg

°C

3

4

Notes: If the LSI is used above these absolute maximum ratings, it may become permanently damaged.

Using the LSI within the following electrical characteristic limits is strongly recommended for normal

operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction

and cause poor reliability.

* Refer to the Electrical Characteristics Notes section following these tables.

404

HD66710

DC Characteristics (V = 2.7 V to 5.5 V, T = –20°C to +75°C^*3)

CC

a

Item

Symbol Min

Typ

Max

Unit Test Condition

Notes*

Input high voltage (1)

(except OSC₁)

V_IH1

0.7V_CC

—

V_CC

V

6

Input low voltage (1)

(except OSC₁)

V_IL1

–0.3

—

0.2V_CC

0.6

V

6

–0.3

Input high voltage (2)

(OSC₁)

V_IH2

V_IL2

0.7V_CC

V_CC

V

15

7

Input low voltage (2)

(OSC₁)

—

0.2V_CC

—

Output high voltage (1) V_OH1

(D₀–D₇)

0.75V_CC

—

V

–I_OH= 0.1 mA

I_OL= 0.1 mA

Output low voltage (1) V_OL1

(D₀–D₇)

0.2V_CC

—

V

7

Output high voltage (2) V_OH2

(except D₀–D₇)

0.8V_CC

—

V

–I_OH= 0.04 mA

I_OL= 0.04 mA

8

Output low voltage (2) V_OL2

(except D₀–D₇)

0.2V_CC

20

V

8

Driver on resistance

(COM)

R_COM

—

kΩ

±Id = 0.05 mA (COM)

V_LCD= 4 V

13

9

Driver on resistance

(SEG)

R_SEG

—

30

±Id = 0.05 mA (SEG)

V_LCD= 4 V

I/O leakage current

I_LI

–1

5

—

1

µA

V_IN= 0 to V_CC

Pull-up MOS current

(D₀–D₇, RS, R/W)

–Ip

50

120

V_CC= 3 V

V_IN= 0 V

Power supply current

I_CC

—

0.15

0.30

mA

R_foscillation,

external clock

10, 14

V_CC= 3V, f_OSC= 270 kHz

LCD voltage

V_LCD1

V_LCD2

3.0

—

13.0

V

V_CC–V₅, 1/5 bias

16

V_CC–V₅, 1/6.7 bias

Note: * Refer to the Electrical Characteristics Notes section following these tables.

Booster Characteristics

Item

Symbol Min

Typ

Max

Unit Test Condition

Notes*

Output voltage

(V5OUT2 pin)

V_UP2

V_UP3

V_Ci

7.5

7.0

2.0

8.7

—

V

V_ci= 4.5 V, I₀= 0.25 mA, 18, 19

C = 1 µF, f_OSC= 270 kHz,

T_a= 25°C

Output voltage

(V5OUT3 pin)

7.7

—

V_ci= 2.7 V, I₀= 0.25 mA, 18, 19

C = 1 µF, f_OSC= 270 kHz,

T_a= 25°C

Input voltage

5.0

18, 19,

20

Note: * Refer to the Electrical Characteristics Notes section following these tables.

405

HD66710

AC Characteristics (V = 2.7 V to 5.5 V, T = –20°C to +75°C^*3)

CC

a

Clock Characteristics

Item

Symbol Min

Typ

270

50

Max Unit Test Condition Notes*

External

clock

operation

External clock frequency

External clock duty

f_cp

125

45

350

55

kHz

%

11

Duty

t_rcp

t_fcp

External clock rise time

External clock fall time

—

0.2

350

µs

—

µs

R_f

Clock oscillation frequency f_OSC

190

270

kHz R_f= 91 kΩ,

12

oscillation

V_CC= 5 V

Note: * Refer to the Electrical Characteristics Notes section following these tables.

Bus Timing Characteristics (1) (V = 2.7 V to 4.5 V, T = –20°C to +75°C^*3)

CC

a

Write Operation

Item

Symbol

Min

1000

450

—

Typ

—

Max

—

Unit

Test Condition

Enable cycle time

Enable pulse width (high level)

Enable rise/fall time

t_cycE

ns

Figure 33

PW_EH

t_Er, t_Ef

—

25

—

Address set-up time (RS, R/W to E) t_AS

60

Address hold time

Data set-up time

Data hold time

t_AH

t_DSW

t_H

20

—

195

10

—

Read Operation

Item

Symbol

t_cycE

Min

1000

450

—

Typ

—

Max

—

Unit

Test Condition

Enable cycle time

Enable pulse width (high level)

Enable rise/fall time

ns

Figure 34

PW_EH

t_Er, t_Ef

—

25

—

Address set-up time (RS, R/W to E) t_AS

60

Address hold time

Data delay time

Data hold time

t_AH

20

—

t_DDR

t_DHR

—

360

—

5

406

HD66710

Bus Timing Characteristics (2) (V = 4.5 V to 5.5 V, T = –20°C to +75°C^*3)

CC

a

Write Operation

Item

Symbol

Min

500

230

—

Typ

—

Max

—

Unit

Test Condition

Enable cycle time

Enable pulse width (high level)

Enable rise/fall time

t_cycE

ns

Figure 33

PW_EH

t_Er, t_Ef

—

20

—

Address set-up time (RS, R/W to E) t_AS

40

Address hold time

Data set-up time

Data hold time

t_AH

t_DSW

t_H

10

—

80

—

10

—

Read Operation

Item

Symbol

t_cycE

Min

500

230

—

Typ

—

Max

—

Unit

Test Condition

Enable cycle time

Enable pulse width (high level)

Enable rise/fall time

ns

Figure 34

PW_EH

t_Er, t_Ef

—

20

—

Address set-up time (RS, R/W to E) t_AS

40

Address hold time

Data delay time

Data hold time

t_AH

10

—

t_DDR

t_DHR

—

160

—

5

Segment Extension Signal Timing (V = 2.7 V to 5.5 V, T = –20°C to +75°C^*3)

CC

a

Item

Symbol

t_CWH

t_CWL

t_CSU

t_SU

Min

500

300

–1000

—

Typ

—

Max

—

Unit

Test Condition

Clock pulse width

High level

Low level

ns

Figure 35

—

Clock set-up time

Data set-up time

Data hold time

M delay time

—

t_DH

—

t_DM

1000

600

Clock rise/fall time

t_ct

407

HD66710

Power Supply Conditions Using Internal Reset Circuit

Item

Symbol

t_rCC

Min

0.1

1

Typ

—

Max

10

Unit

Test Condition

Power supply rise time

Power supply off time

ms

Figure 36

t_OFF

—

Electrical Characteristics Notes

1. All voltage values are referred to GND = 0 V. If the LSI is used above these absolute maximum ratings,

it may become permanently damaged. Using the LSI within the following electrical characteristic limits is

strongly recommended for normal operation. If these electrical characteristic conditions are also

exceeded, the LSI will malfunction and cause poor reliability.

2.

V_CC≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must be maintained. In addition, if the SEG37/CL1, SEG38/CL2,

SEG39/D, and SEG40/M are used as extension driver interface signals (EXT = high), GND ≥ V5 must

be maintained.

3. For die products, specified up to 75°C.

4. For die products, specified by the die shipment specification.

5. The following four circuits are I/O pin configurations except for liquid crystal display output.

Input pin

Pin: E (MOS without pull-up)

Pins: RS, R/W (MOS with pull-up)

V_CCV_CC

V_CC

PMOS

NMOS

PMOS

(pull up MOS)

NMOS

I/O pin

Pins: DB₀–DB₇

V_CC

(MOS with pull-up)

(input circuit)

PMOS

(pull-up MOS)

PMOS

Input enable

NMOS

V_CC

NMOS

PMOS

Output enable

data

NMOS

(output circuit)

(tristate)

408

HD66710

6. Applies to input pins and I/O pins, excluding the OSC₁pin.

7. Applies to I/O pins.

8. Applies to output pins.

9. Current flowing through pull-up MOSs, excluding output drive MOSs.

10. Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive

current flows through the input circuit to the power supply. To avoid this from happening, the input level

must be fixed high or low.

11. Applies only to external clock operation.

Th

Tl

Oscillator

Open

OSC1

OSC2

0.7 V_CC

0.5 V_CC

0.3 V_CC

t_rcp

× 100%

t_fcp

Th

Th + Tl

Duty =

12. Applies only to the internal oscillator operation using oscillation resistor R_f.

R_f: 75 kΩ ± 2% (when V_CC= 3 V to 4 V)

OSC1

R_f: 91 kΩ ± 2% (when V_CC= 4 V to 5 V)

R_f

Since the oscillation frequency varies depending on the OSC1 and

OSC2 pin capacitance, the wiring length to these pins should be minimized.

OSC2

V_CC= 5 V

V_CC= 3 V

500

400

300

500

400

300

max.

typ.

(270)

max.

200

100

200

100

typ.

min.

150

min.

150

(75)

(91)

100

50

R_f(kΩ)

409

HD66710

13. R_COMis the resistance between the power supply pins (V_CC, V1, V4, V5) and each common

signal pin (COM1 to COM33).

R_SEGis the resistance between the power supply pins (V_CC, V2, V3, V5) and each segment signal pin

(SEG1 to SEG40).

14. The following graphs show the relationship between operation frequency and current consumption.

V

_CC= 5 V

V

_CC= 3 V

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

max.

typ.

max.

typ.

typ. (LP mode)

0

100 200 300 400 500

f_OSCor f_cp(kHz)

0

100 200 300 400 500

f_OSCor f_cp(kHz)

15. Applies to the OSC1 pin.

16. Each COM and SEG output voltage is within ±0.15 V of the LCD voltage (V_CC, V1, V2, V3, V4, V5)

when there is no load.

17. The TEST pin must be fixed to the ground, and the EXT or V_CCpin must also be connected to the

ground.

18. Booster characteristics test circuits are shown below.

Boosting twice

V_CC

Boosting three times

V_CC

Vci

C1

C2

Rload

I_O

Vci

C1

C2

Rload

I_O

1 µF

+

V5OUT2

1 µF

+

V5OUT3

GND

410

HD66710

19. Reference data

The following graphs show the liquid crystal voltage booster characteristics.

VUP2 = V_CC–V5OUT2

VUP3 = V_CC–V5OUT3

(1) VUP2, VUP3 vs V_ci

Boosting twice

Boosting three times

11

10

9

15

14

13

12

11

10

9

typ.

8

7

6

8

7

5

4

6

2.0

3.0

4.0

V_ci(V)

5.0

2.0

3.0

4.0

V_ci(V)

5.0

Test condition: V_ci= V_CC, f_cp= 270 kHz

T_a= 25°C, Rload = 25 kΩ

Ta = 25°C, Rload = 25 kΩ

(2) VUP2, VUP3 vs I_o

Boosting twice

9.0

Boosting three times

8.0

8.5

7.5

7.0

6.5

typ.

min.

8.0

7.5

7.0

6.5

6.0

typ.

min.

6.0

5.5

5.0

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

I_o(mA)

Test condition: V_ci= V_CC= 4.5 V

R_f= 91 kΩ, T_a= 25°C

Test condition: V_ci= V_CC= 2.7 V

R_f= 75 kΩ, T_a= 25°C

(3) VUP2, VUP3 vs T_a

Boosting twice

Boosting three times

8.0

9.0

8.5

8.0

7.5

7.0

typ.

min.

7.5

7.0

6.5

6.0

–60 –20 0 20

T_a(°C)

60

100

–60 –20 0 20

T_a(°C)

60 100

Test condition: V_ci= V_CC= 4.5 V

R_f= 91 kΩ, I_o= 0.25 mA

Test condition: V_ci= V_CC= 2.7 V

R_f= 75 kΩ, I_o= 0.25 mA

411

HD66710

(4) VUP2, VUP3 vs Capacitance

Boosting twice

Boosting three times

9.0

8.5

8.0

7.5

7.0

typ.

min.

8.0

7.5

7.0

6.5

6.0

typ.

min.

0.5

1.0

1.5

0.5

1.0

1.5

C (µF)

Test condition: V_ci= V_CC= 4.5 V

R_f= 91 kΩ, I_o= 0.25 mA

Test condition: V_ci= V_CC= 2.7 V

R_f= 75 kΩ, I_o= 0.25 mA

20. V_ci≤ V_CCmust be maintained.

412

HD66710

Load Circuits

AC Characteristics Test Load Circuits

Data bus: DB0–DB7

Segment extension signals: CL1, CL2, D, M

Test

point

Test

point

30 pF

50 pF

413

HD66710

Timing Characteristics

V_IH1

V_IL1

V_IH1

V_IL1

RS

t_AS

t_AH

R/W

V_IL1

PW_EH

t_AH

t_Ef

V_IH1

V_IL1

V_IH1

V_IL1

E

V_IL1

t_Er

t_DSW

t_H

V_IH1

V_IL1

V_IH1

V_IL1

Valid data

t_cycE

DB₀to DB₇

Figure 33 Write Operation

V_IH1

V_IL1

V_IH1

V_IL1

RS

t_AS

t_AH

V_IH1

R/W

PW_EH

t_AH

t_Ef

V_IH1

V_IL1

V_IH1

V_IL1

E

V_IL1

t_Er

t_DDR

t_DHR

V_OH1

*

V_OL1

Valid data

t_cycE

DB₀to DB₇

*

V_OL1

Note: V_OL1is assumed to be 0.8 V at 2 MHz operation.

Figure 34 Read Operation

414

HD66710

t_ct

V_OH2

t_CWH

CL₁

CL₂

D

V_OL2

t_CWH

V_OH2

V_OL2

t_CSU

t_CWL

t_ct

V

OH2

OL2

t_DH

t_SU

M

V_OL2

t_DM

Figure 35 Interface Timing with External Driver

2.7 V/4.5 V^*2

0.2 V

V_CC

0.2 V

t_rcc

t_OFF*1

0.1 ms ≤ t_rcc≤ 10 ms

t_OFF≥1 ms

Notes: 1. t_OFFcompensates for the power oscillation period caused by momentary power

supply oscillations.

2. Specified at 4.5 V for standard voltage operation, and at 2.7 V for low voltage operation.

3. If the above electrical conditions are not satisfied, the internal reset circuit will not

operate normally. In this case, the LSI must be initialized by software. (Refer to the

Initializing by Instruction section.)

Figure 36 Power Supply Sequemce

415


型号：	HD66710A01TF
厂家：	HITACHI SEMICONDUCTOR
描述：	Dot Matrix LCD Driver, CMOS, PQFP100, 14 X 14 MM, TQFP-100 驱动 CD 外围集成电路
文件：	总84页 (文件大小：478K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HD66710A01TF [HITACHI]

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