HD66710BXXFS_技术文档

HD66710

(Dot Matrix Liquid Crystal Display Controller/Driver)

Description

The HD66710 dot-matrix liquid crystal display controller and driver LSI displays alphanumerics,

numbers, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control

of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and

liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one

chip, a minimum system can be interfaced with this controller/driver.

A single HD66710 is capable of displaying a single16-character line, two 16-character lines, or up to four

8-character lines.

The HD66710 software is upwardly compatible with the LCD-II (HD44780) which allows the user to

easily replace an LCD-II with an HD66710. In addition, the HD66710 is equipped with functions such as

segment displays for icon marks, a 4-line display mode, and a horizontal smooth scroll, and thus supports

various display forms. This achieves various display forms. The HD66710 character generator ROM is

extended to generate 240 5 × 8 dot characters.

The low voltage version (2.7V) of the HD66710, combined with a low power mode, is suitable for any

portable battery-driven product requiring low power dissipation.

Features

•

5 × 8 dot matrix possible

Low power operation support:

2.7V to 5.5V (low voltage)

•

Booster for liquid crystal voltage

Two/three times (13V max.)

Wide range of liquid crystal display driver voltage

3.0V to 13V

•

Extension driver interface

High-speed MPU bus interface (2 MHz at 5-V operation)

4-bit or 8-bit MPU interface capability

80 × 8-bit display RAM (80 characters max.)

291

HD66710

•

9,600-bit character generator ROM

240 characters (5 × 8 dot)

64 × 8-bit character generator RAM

8 characters (5 × 8 dot)

8 × 8-bit segment RAM

40-segment icon mark

•

33-common × 40-segment liquid crystal display driver

Programmable duty cycle (See List 1)

Wide range of instruction functions:

Functions compatible with LCD-II: Display clear, cursor home, display on/off, cursor on/off,

display character blink, cursor shift, display shift

Additional functions: Icon mark control, 4-line display, horizontal smooth scroll, 6-dot character

width control, white-black inverting blinking cursor

•

Software upwardly compatible with HD44780

Automatic reset circuit that initializes the controller/driver after power on

Internal oscillator with an external resistor

Low power consumption

QFP1420-100 pin, TQFP1414-100 pin bare-chip

List 1 Programmable Duty Cycles

Maximum Number of Displayed Characters

Single-Chip Operation

Number of

Lines

Displayed

Duty Ratio

1/17

Character

5 × 8-dot

1

2

4

One 16-character line + 40 segments

Two 16-character lines + 40 segments

Four 8-character lines + 40 segments

1/33

Ordering Information

Type No.

Package

QFP1420-100 (FP-100A)

CGROM

HD66710A00FS

HD66710A00TF

HCD66710A00

Japanese standard

TQFP1414-100 (TFP-100B)

Chip

292

HD66710

LCD-II Family Comparison

LCD-II

Item

(HD44780U)

HD66702R

HD66710

HD66712U

Power supply voltage 2.7V to 5.5V

5V ±10%

2.7V to 5.5V

(standard)

2.7V to 5.5V

(low voltage)

Liquid crystal drive

voltage

3.0V to 11V

3.0V to 8.3V

3.0V to 13.0V

2.7V to 11.0V

Maximum display

digits per chip

8 characters

× 2 lines

20 characters

× 2 lines

16 characters ×

2 lines/

24 characters ×

2 lines/

8 characters ×

4 lines

12 characters ×

4 lines

Segment display

Display duty cycle

CGROM

None

40 segments

60 segments

1/17 and 1/33

1/8, 1/11, and 1/16 1/8, 1/11, and 1/16 1/17 and 1/33

9,920 bits

7,200 bits

9,600 bits

(208 5 × 8 dot

characters and

32 5 × 10 dot

characters)

(160 5 × 7 dot

characters and

32 5 × 10 dot

characters)

(240 5 × 8 dot

characters)

(240 5 × 8 dot

characters)

CGRAM

64 bytes

80 bytes

None

40

64 bytes

80 bytes

None

100

64 bytes

80 bytes

8 bytes

40

64 bytes

80 bytes

16 bytes

60

DDRAM

SEGRAM

Segment signals

Common signals

16

33

34

Liquid crystal drive

waveform

A

B

Bleeder resistor for

LCD power supply

External

(adjustable)

External

(adjustable)

External

(adjustable)

External

(adjustable)

Clock source

Extenal resistor or External resistor or External resistor or External resistor or

external clock

R_foscillation

frequency (frame

frequency)

270 kHz ±30%

(59 to 110 Hz for

1/8 and 1/16 duty

320 kHz ±30%

(70 to 130 Hz for

1/8 and 1/16 duty

270 kHz ±30%

(56 to 103 Hz for

1/17 duty cycle; 57 1/17 duty cycle; 57

270 kHz ±30%

(56 to 103 Hz for

cycle; 43 to 80 Hz cycle; 51 to 95 Hz to 106 Hz for 1/33 to 106 Hz for 1/33

for 1/11 duty cycle) for 1/11 duty cycle) duty cycle)

duty cycle)

R_fresistance

91 kΩ: 5-V

operation;

75 kΩ: 3-V

operation

68 kΩ: 5-V

operation;

56 kΩ: (3-V

operation)

91 kΩ: 5-V

operation;

75 kΩ: 3-V

operation)

130 kΩ: 5-V

operation;

110 kΩ: 3-V

operation

Liquid crystal voltage None

booster circuit

None

2-3 times step-

up circuit

2-3 times step-

up circuit

293

HD66710

LCD-II

Item

(HD44780U)

HD66702R

HD66710

HD66712U

Extension driver

control signal

Independent

control signal

Independent

control signal

Used in common

with a driver

output pin

Independent

control signal

Reset function

Instructions

Power on

automatic reset

Power on

automatic reset

Power on

automatic reset

Power on

automatic reset

or reset input

LCD-II

(HD44780)

Fully compatible

with the LCD-II

Upper compatible

with the LCD-II

Upper compatible

with the LCD-II

Number of displayed 1 or 2

lines

1 or 2

1, 2, or 4

Low power mode

Horizontal scroll

Bus interface

None

Available

Dot unit

Available

Dot unit

Character unit

4 bits/8 bits

Character unit

4 bits/8 bits

Serial;

4 bits/8 bits

CPU bus timing

2 MHz: 5-V

operation;

1 MHz: 3-V

operation

1 MHz

2 MHz: 5-V

operation;

1 MHz: 3-V

operation

2 MHz: 5-V

operation;

1 MHz: 3-V

operation

Package

QFP-1420-80

80-pin bare chip

LQFP-2020-144

144-pin bare chip

QFP-1420-100

100-pin bare chip

TQFP1414-100

TCP-128

128-pin bare chip

294

HD66710

HD66710 Block Diagram

OSC1

OSC2

EXT

CPG

Reset circuit

ACL

Timing generator

7

Instruction register

(I R)

Instruction

decoder

COM1–

COM33

Display data RAM

(DDRAM)

80 × 8 bits

Common

signal

33-bit

shift

8

driver

register

Address counter

7

RS

R/W

E

MPU

interface

7

8

SEG1–

SEG36

40-bit

shift

register

40-bit

latch

circuit

8

Data

register

(DR)

Segment

signal

driver

DB4–DB7

DB3–DB0

SEG37/CL1

SEG38/CL2

SEG39/D

Input/

output

buffer

8

SEG40/M

3

7

Busy

flag

LCD drive

voltage

selector

Cursor and

bling

controller

Segment

RAM

(SGRAM)

8 bytes

Character

generator RAM

(CGRAM)

Character

generator ROM

(CGROM)

64 bytes

9,600 bytes

Vci

C1

C2

Booster

5

5/6

V5OUT2

V5OUT3

Parallel/serial

converter

and attribute circuit

V_CC

GND

V1

V2

V3

V4

V5

295

HD66710

HD66710 Pin Arrangement

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

SEG27

SEG28

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

V_CC

2

SEG29

3

SEG30

4

SEG31

5

SEG32

6

SEG33

7

SEG34

8

TEST

EXT

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

E

SEG35

9

SEG36

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

SEG37/CL1

SEG38/CL2

SEG39/D

SEG40/M

COM9

HD66710

(FP-100A)

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

R/W

RS

OSC2

OSC1

Vci

C2

C1

GND

V5OUT2

V5OUT3

V5

V4

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

(Top view)

296

HD66710

HD66710 Pin Arrangement (TQFP1414-100 Pin)

80 79 78 77 76

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

SEG29

SEG30

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SEG3

SEG2

SEG1

V_CC

2

SEG31

3

SEG32

4

SEG33

5

TEST

EXT

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

E

SEG34

6

SEG35

7

SEG36

8

SEG37/CL1

SEG38/CL2

SEG39/D

SEG40/M

COM9

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

HD66710

(TFP-100B)

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

R/W

RS

OSC2

OSC1

Vci

C2

C1

GND

V5OUT2

V5OUT3

26 27 28 29 30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

(Top view)

297

HD66710

HD66710 Pad Arrangement

Chip size (X ×Y): 5.36 mm × 6.06 mm

Coordinate

Origin

: Pad center

: Chip center

Pad size (X×Y) : 100 µm × 100 µm

1

100

81 80

2

79

HD66710

Type code

Y

29

52

50 51

30 31

X

298

HD66710

HD66710 Pad Location Coordinates

Pin No.

1

2

3

4

5

6

7

8

Pad Name

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM24

COM23

COM22

COM21

COM20

COM19

COM18

COM17

COM8

COM7

COM6

COM5

COM4

COM3

COM2

COM1

X

Y

2910

2730

2499

2300

2100

1901

1698

1498

Pin No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Pad Name

V4

V5

V5OUT3

V5OUT2

GND

C1

C2

Vci

OSC1

OSC2

RS

R/

E

DB0

DB1

DB2

DB3

X

2458

Y

–2495

–2695

–2495

–2051

–1701

–1498

–1302

–1102

–899

–2910

–2731

–2500

–2300

–2090

–1887

–1702

–1502

–1303

–1103

–900

–701

–501

–302

–99

2660

2640

2650

2675

2695

2495

2049

1699

1499

1300

1100

901

9

1295

1099

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

900

700

501

301

98

–113

–302

–501

–701

98

301

501

700

DB4

DB5

DB6

DB7

EXT

TEST

V_CC

–900

900

–1100

–1303

–1502

–1702

–1901

–2101

–2300

–2500

–2731

–2910

1099

1299

1502

1698

1901

2104

2300

2503

2730

2910

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

–700

–500

–301

–101

701

502

299

99

302

502

698

–101

–301

–500

–700

–899

–1099

–1302

–1501

–1701

–2051

887

1077

1266

1488

1710

COM33

V1

V2

V3

2063

299

HD66710

Pin Functions

Table 1

Pin Functional Description

Device

Signal

I/O

Interfaced with Function

RS

I

MPU

Selects registers

0: Instruction register (for write)

Busy flag: address counter (for read)

1: Data register (for write and read)

R/

I

Selects read or write

0: Write

1: Read

E

I

MPU

Starts data read/write

DB4 to DB7

I/O

Four high order bidirectional tristate data bus pins. Used for

data transfer between the MPU and the HD66710. DB7 can

be used as a busy flag.

DB0 to DB3

I/O

O

MPU

LCD

Four low order bidirectional tristate data bus pins. Used for

data transfer between the MPU and the HD66710. These

pins are not used during 4-bit operation.

COM1 to COM33

Common signals; those are not used become non-selected

waveforms. At 1/17 duty rate, COM1 to COM16 are used for

character display, COM17 for icon display, and COM18 to

COM33 become non-selected waveforms. At 1/33 duty rate,

COM1 to COM32 are used for character display, and

COM33 for icon display.

SEG1 to SEG35

SEG36

O

LCD

Segment signals

Segment signal. When EXT = high, the same data as that of

the first dot of the extension driver is output.

SEG37/CL1

SEG38/CL2

SEG39/D

SEG40/M

EXT

O

I

LCD/

Segment signal when EXT = low. When EXT = high, outputs

Extension driver the extension driver latch pulse.

LCD/

Segment signal when EXT = low. When EXT = high, outputs

Extension driver the extension driver shift clock.

LCD/

Segment signal at EXT = low. At EXT = high, the extension

Extension driver driver data. Data on and after the 36th dot is output.

LCD/

Segment signal when EXT = low. When EXT = high, outputs

Extension driver the extension driver AC signal.

—

Extension driver enable signal. When EXT = high, SEG37 to

SEG40 become extension driver interface signals. At this

time, make sure that V5 level is lower than GND level (0 V).

V5 (low) ≤ GND (high).

V1 to V5

—

Power supply

Power supply for LCD drive

V_CC– V5 = 13V (max)

300

HD66710

Table 1

Pin Functional Description (cont)

Device

Signal

I/O

—

Interfaced with Function

V_CC, GND

OSC1, OSC2

Power supply

V_CC: +2.7V to 5.5V, GND: 0V

—

Oscillation

When CR oscillation is performed, a resistor must be

resistor clock

connected externally. When the pin input is an external

clock, it must be input to OSC1.

Vci

I

—

Input voltage to the booster, from which the liquid crystal

display drive voltage is generated.

Vci is reference voltage and power supply for the booster.

Vci = 1.0V to 5.0V ≤ V_CC

V5OUT2

O

V5 pin/

Booster

capacitance

Voltage input to the Vci pin is boosted twice and output

When the voltage is boosted three times, the same capacity

as that of C1–C2 should be connected.

V5OUT3

C1/C2

TEST

O

—

I

V5 pin

Voltage input to the Vci pin is boosted three times and

output.

Booster

capacitance

External capacitance should be connected when using the

booster.

—

Test pin. Should be wired to ground.

301

HD66710

Function Description

Registers

The HD66710 has two 8-bit registers, an instruction register (IR) and a data register (DR).

The IR stores instruction codes, such as display clear and cursor shift, and address information for the

display data RAM (DDRAM), the character generator RAM (CGRAM), and the segment RAM

(SEGRAM). The MPU can only write to IR, and cannot be read from.

The DR temporarily stores data to be written into DDRAM, CGRAM, or SEGRAM. Data written into the

DR from the MPU is automatically written into DDRAM, CGRAM, or SEGRAM by an internal

operation. The DR is also used for data storage when reading data from DDRAM, CGRAM, or

SEGRAM. When address infor-mation is written into the IR, data is read and then stored into the DR

from DDRAM, CGRAM, or SEGRAM by an internal operation. Data transfer between the MPU is then

completed when the MPU reads the DR. After the read, data in DDRAM, CGRAM, or SEGRAM at the

next address is sent to the DR for the next read from the MPU. By the register selector (RS) signal, these

two registers can be selected (Table 2).

Busy Flag (BF)

When the busy flag is 1, the HD66710 is in the internal operation mode, and the next instruction will not

be accepted. When RS = 0 and R/ = 1 (Table 2), the busy flag is output from DB7. The next instruction

must be written after ensuring that the busy flag is 0.

Address Counter (AC)

The address counter (AC) assigns addresses to DDRAM, CGRAM, or SEGRAM. When an address of an

instruction is written into the IR, the address information is sent from the IR to the AC. Selection of

DDRAM, CGRAM, and SEGRAM is also determined concurrently by the instruction.

After writing into (reading from) DDRAM, CGRAM, or SEGRAM, the AC is automatically incremented

by 1 (decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/ = 1

(Table 2).

Table 2

Register Selection

RS

0

R/

0

Operation

IR write as an internal operation (display clear, etc.)

Read busy flag (DB7) and address counter (DB0 to DB6)

DR write as an internal operation (DR to DDRAM, CGRAM, or SEGRAM)

DR read as an internal operation (DDRAM, CGRAM, or SEGRAM to DR)

0

1

0

1

302

HD66710

Display Data RAM (DDRAM)

Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its capacity is 80 ×

8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used

as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the

liquid crystal display.

The DDRAM address (ADD) is set in the address counter (AC) as hexadecimal.

•

1-line display (N = 0) (Figure 2)

When there are fewer than 80 display characters, the display begins at the head position. For

example, if using only the HD66710, 16 characters are displayed. See Figure 3.

When the display shift operation is performed, the DDRAM address shifts. See Figure 3.

High order

bits

Low order

bits

Example: DDRAM address 4E

AC

1

0

1

0

AC6AC5 AC4 AC3AC2 AC1AC0

(hexadecimal)

Figure 1 DDRAM Address

Display position

(digit)

1

2

3

4

5

79

80

DDRAM

address

. . . . . . . . . . . . . . . . . .

00 01 02 03 04

4E 4F

(hexadecimal)

Figure 2 1-Line Display

1

2

3

4

5

6

7

8

9 10111213141516

Display position

COM9 to 16

DRAM address

00 01 02 03 04 05 06 07

08 09 0A 0B 0C 0D 0E 0F

COM1 to 8

1

2

3

4

5

6

7

8

9 10111213141516

01 02 03 04 05 06 07 08

09 0A 0B 0C 0D 0E 0F 10

COM1 to 8

COM9 to 16 (Left shift display)

COM9 to 16 (Right shift display)

4F 00 01 02 03 04 05 06

07 08 09 0A 0B 0C 0D 0E

Figure 3 1-line by 16-Character Display Example

303

HD66710

•

2-line display (N = 1, and NW = 0)

Case 1: The first line is displayed from COM1 to COM16, and the second line is displayed from

COM17 to COM32. Care is required because the end address of the first line and the start address

of the second line are not consecutive. For example, the case is shown in Figure 5 where 16 × 2-

line display is performed using the HD66710. When a display shift operation is performed, the

DDRAM address shifts. See Figure 4.

1

2

3

4

5

6

7

8

9 10111213141516

Display position

COM9 to 16

00 01 02 03 04 05 06 07

08 09 0A 0B 0C 0D 0E 0F

COM1 to 8

40 41 42 43 44 45 46 47

48 49 4A 4B 4C 4D 4E 4F

COM17 to 24

COM25 to 32

DDRAM address

01 02 03 04 05 06 07 08

41 42 43 44 45 46 47 48

09 0A 0B 0C 0D 0E 0F 10

49 4A 4B 4C 4D 4E 4F 50

COM1 to 8

COM9 to 16

(Left shift display)

(Right shift display)

COM17 to 24

COM25 to 32

27 00 01 02 03 04 05 06

67 40 41 42 43 44 45 46

07 08 09 0A 0B 0C 0D 0E

47 48 49 4A 4B 4C 4D 4E

COM1 to 8

COM9 to 16

COM17 to 24

COM25 to 32

Figure 4 2-line by 16-Character Display Example

Case 2: Figure 5 shows the case where the EXT pin is fixed to high, the HD66710 and the 40-

output extension driver are used to extend the number of display characters.

In this case, the start address from COM9 to COM16 of the HD66710 is 0AH, and that from

COM25 to COM32 of the HD66710 is 4AH. To display 24 characters, the addresses starting at

SEG11 should be used.

When a display shift operation is performed, the DDRAM address shifts. See Figure 5.

Display position

COM9 to COM16

DDRAM address

1

2

3

4

5

6

7

8 9 101112 1314151617 18192021222324

COM1 to

COM8

00 01 02 03 04 05 06

07 08 09 0A 0B

0C 0D 0E 0F 10

11 12 13 14 15 16 17

HD66710

Extension

HD66710

Extension

SEG1 to SEG35 driver (1)

SEG11 to SEG35 driver (1)

Seg1 to Seg25 (SEG1 to SEG10: Seg1 to Seg35

skip)

1

2

3

4

5

6

7

8 9 101112 131415 1617 18192021222324

COM1 to

COM8

COM17 to

COM9 to

COM16

COM25 to

01 02 03 04 05 06 07

08 09 0A 0B 0C

0D 0E 0F 10 11

12 13 14 15 16 17 18

(Left shift display)

(Right shift display)

41 42 43 44 45 46 47

48 49 4A 4B 4C

4D 4E 4F 50 51

52 53 54 55 56 57 58

COM24

COM32

COM1 to

COM8

COM17 to

COM9 to

COM16

COM25 to

27 00 01 02 03 04 05

67 40 41 42 43 44 45

06 07 08 09 0A

46 47 48 49 4A

0B 0C 0D 0E 0F

4B 4C 4D 4E 4F

10 11 12 13 14 15 16

50 51 52 53 54 55 56

COM32

COM24

Figure 5 2-Line by 24 Character Display Example

304

HD66710

•

4-line display (NW = 1)

Case 1: The first line is displayed from COM1 to COM8, the second line is displayed from COM9

to COM16, the third line is displayed from COM17 to COM24, and the fourth line is displayed

from COM25 to COM32. Care is required because the DDRAM addresses of each line are not

consecutive. For example, the case is shown in Figure 6 where 8 × 4-line display is performed

using the HD66710.

When a display shift operation is performed, the DDRAM address shifts. See Figure 6.

1

2 3 4 5 6 7 8

Display position

DDRAM address

00 01 02 03 04 05 06 07

COM1 to 8

COM9 to 16

COM17 to 24

20 21 22 23 24 25 26 27

40 41 42 43 44 45 46 47

60 61 62 63 64 65 66 67

COM25 to 32

1

2

3

4

5

6

7

8

1 2 3 4 5 6 7 8

01 02 03 04 05 06 07 08

13 00 01 02 03 04 05 06

COM1 to 8

COM9 to 16

COM17 to 24

21 22 23 24 25 26 27 28

33

20 21 22 23 24 25 26

(Left shift display)

(Right shift display)

41 42 43 44 45 46 47 48

61 62 63 64 65 66 67 68

53 40 41 42 43 44 45 46

73 60 61 62 63 64 65 66

COM25 to 32

Figure 6 4-Line Display

305

HD66710

Case 2: The case is shown in figure where the EXT pin is fixed high, and the HD66710 and the

40-output extension driver are used to extend the number of display characters.

When a display shift operation is performed, the DDRAM address shifts. See Figure 7.

1

2

3

4

5

6

7

8 9 10 111213141516 17 1819 20

Display position

DDRAM address

COM1 to 8

COM9 to 16

COM17 to 24

COM25 to 32

00 01 02 03 04 05 06

07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13

20 21 22 23 24 25 26

27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33

40 41 42 43 44 45 46

60 61 62 63 64 65 66

47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53

67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73

HD66710

Extension driver (1)

Extension driver (2)

1

2

3

4

5

6

7

8

9 1011 12131415 1617181920

1 2 3 4 5 6 7 8 9 1011121314151617181920

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 00

21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 20

41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 40

13 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12

33 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32

53 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52

73 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72

(Display shift right)

61 62 63 64 65

67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 60

66

(Display shift left)

Figure 7 4-Line by 20-Character Display Example

306

HD66710

Character Generator ROM (CGROM)

The character generator ROM generates 5 × 8 dot character patterns from 8-bit character codes (Table 3).

It can generate 240 5 × 8 dot character patterns. User-defined character patterns are also available using a

mask-programmed ROM.

Character Generator RAM (CGRAM)

The character generator RAM allows the user to redefine the character patterns. In the case of 5 × 8

characters, up to eight may be redefined.

Write the character codes at the addresses shown as the left column of Table 3 to show the character

patterns stored in CGRAM.

See Table 5 for the relationship between CGRAM addresses and data and display patterns.

Segment RAM (SEGRAM)

The segment RAM (SEGRAM) is used to enable control of segments such as an icon and a mark by the

user program.

For a 1-line display, SEGRAM is read from the COM17 output, and as for 2- or 4-line displays, it is from

the COM33 output, to performs 40-segment display.

As shown in Table 6, bits in SEGRAM corresponding to segments to be displayed are directly set by the

MPU, regardless of the contents of DDRAM and CGRAM.

SEGRAM data is stored in eight bits. The lower six bits control the display of each segment, and the

upper two bits control segment blinking.

Modifying Character Patterns

•

Character pattern development procedure

The following operations correspond to the numbers listed in Figure 8:

1. Determine the correspondence between character codes and character patterns.

2. Create a listing indicating the correspondence between EPROM addresses and data.

3. Program the character patterns into an EPROM.

4. Send the EPROM to Hitachi.

5. Computer processing of the EPROM is performed at Hitachi to create a character pattern listing,

which is sent to the user.

6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and

samples are sent to the user for evaluation. When it is confirmed by the user that the character

patterns are correctly written, mass production of the LSI will proceed at Hitachi.

307

HD66710

Hitachi

User

Start

Computer

processing

Determine

character patterns

1

2

3

4

Create character

pattern listing

Create EPROM

address data listing

5

Evaluate

character

patterns

Write EPROM

EPROM → Hitachi

No

OK?

Yes

Art work

M/T

Masking

Trial

Sample

evaluation

6

No

OK?

Yes

Mass

production

Note: For a description of the numbers used in this figure, refer to the preceding page.

Figure 8 Character Pattern Development Procedure

308

HD66710

Table 3

Correspondence between Character Codes and Character Patterns (Hitachi Standard

HD66710)

Upper 4

Bits

Lower

4 Bits

0001

0000

0010 0011 0100 0101 0110 0111 1000 1001

1010 1011 1100 1101 1110 1111

CG

RAM

(1)

xxxx0000

xxxx0001

xxxx0010

xxxx0011

xxxx0100

xxxx0101

xxxx0110

xxxx0111

xxxx1000

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(1)

xxxx1001 (2)

(3)

xxxx1010

xxxx1011

xxxx1100

xxxx1101

xxxx1110

(4)

(5)

(6)

(7)

xxxx1111 (8)

Note: The user can specify any pattern in the character-generator RAM.

309

HD66710

•

Programming character patterns

This section explains the correspondence between addresses and data used to program character

patterns in EPROM. The HD66710 character generator ROM can generate 240 5 × 8 dot character

patterns.

Character patterns

EPROM address data and character pattern data correspond with each other to form a 5 × 8 dot

character pattern (Table 4).

Table 4

Example of Correspondence between EPROM Address Data and Character Pattern

(5 × 8 Dots)

EPROM Address

Data

O4 O3 O2 O1 O0

MSB

LSB

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Character code

Line position

“0”

Notes: 1. EPROM addresses A11 to A4 correspond to a character code.

2. EPROM addresses A2 to A0 specify a line position of the character pattern. EPROM address

A3 should be set to 0.

3. EPROM data O4 to O0 correspond to character pattern data.

4. Area which are lit (indicated by shading) are stored as 1, and unlit are as 0.

5. The eighth line is also stored in the CGROM, and should also be programmed. If the eighth line

is used for a cursor, this data should all be set to zero.

6. EPROM data bits O7 to O5 are invalid. 0 should be written in all bits.

310

HD66710

Handling unused character patterns

1. EPROM data outside the character pattern area: This is ignored by the character generator ROM

for display operation so any data is acceptable.

2. EPROM data in CGRAM area: Always fill with zeros. (EPROM addresses 00H to FFH.)

3. Treatment of unused user patterns in the HD66710 EPROM: According to the user application,

these are handled in either of two ways:

a. When unused character patterns are not programmed: If an unused character code is written

into DDRAM, all its dots are lit, because the EPROM is filled with 1s after it is erased.

b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused

character codes are written into DDRAM. (This is equivalent to a space.)

Table 5

Example of Correspondence between Character Code and Character Pattern (5 × 8

Dots) in CGRAM

a) When Character Pattern in 5

× 8 Dots

Character code (DDRAM data)

CGRAM address

CGRAM data

MSB

LSB

D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 O7 O6 O5 O4 O3 O2 O1 O0

0

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

1

0

1

0

1

0

1

0

1

0

Character

pattern

(1)

0

*

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

1

0

1

0

1

0

1

0

1

0

Character

pattern

(8)

311

HD66710

Table 5

Example of Correspondence between Character Code and Character Pattern (5 × 8

Dots) in CGRAM (cont)

b) When Character Pattern in 6

× 8 Dots

Character code (DDRAM data)

CGRAM address

CGRAM data

MSB

LSB

D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 O7 O6 O5 O4 O3 O2 O1 O0

*

0

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Character

pattern

(1)

0

*

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

0

1

0

1

0

1

0

1

0

1

0

Character

pattern

(8)

Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).

2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the

cursor position and its display is formed by a logical OR with the cursor.

3. The character data is stored with the rightmost character element in bit 0, as shown in Table 5.

Characters with 5 dots in width (FW = 0) are stored in bits 0 to 4, and characters with 6 dots in

width (FW = 1) are stored in bits 0 to 5.

4. When the upper four bits (bits 7 to 4) of the character code are 0, CGRAM is selected.

Bit 3 of the character code is invalid (*). Therefore, for example, the character codes 00

(hexadecimal) and 08 (hexadecimal) correspond to the same CGRAM address.

5. A set bit in the CGRAM data corresponds to display selection, and 0 to non-selection.

6. When the BE bit of the function set register is 1, pattern blinking control of the lower six bits is

controlled using the upper two bits (bits 7 and 6) in CGRAM.

When bit 7 is 1, of the lower six bits, only those which are set are blinked on the display.

When bit 6 is 1, a bit 4 pattern can be blinked as for a 5-dot font width, and a bit 5 pattern can

be blinked as for a 6-dot font width.

*

Indicates no effect.

312

HD66710

Table 6

Relationships between SEGRAM Addresses and Display Patterns

SEGRAM data

SEGRAM

address

a) 5-dot font width

D7 D6 D5 D4 D3 D2 D1 D0

b) 6-dot font width

A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

B1 B0 S1 S2 S3 S4 S5 S6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0

*

S1 S2 S3 S4 S5

S6 S7 S8 S9 S10 B1 B0 S7 S8 S9 S10S11S12

S11S12S13S14S15 B1 B0 S13S14S15S16S17S18

S16S17S18S19S20 B1 B0 S19S20S21S22S23S24

S21S22S23S24S25 B1 B0 S25S26S27S28S29S30

S26S27S28S29S30 B1 B0 S31S32S33S34S35S36

S31S32S33S34S35 B1 B0 S37S38S39S40S41S42

S36S37S38S39S40 B1 B0 S43S44S45S46S47S48

Pattern on/off

Blinking control

Notes: 1. Data set to SEGRAM is output when COM17 is selected, as for a 1-line display, and output

when COM33 is selected, as for a 2-line or a 4-line display.

2. S1 to S48 are pin numbers of the segment output driver.

S1 is positioned to the left of the monitor.

S37 to S48 are extension driver outputs for a 6-dot character width.

3. After S40 output at 5-dot font and S48 output at 6-dot font, S1 output is repeated again.

4. As for a 5-dot font width, lower five bits (D4 to D0) are display on.off information of each

segment. For a 6-dot character width, the lower six bits (D5 to D0) are the display information

for each segment.

5. When the BE bit of the function set register is 1, pattern blinking of the lower six bits is

controlled using the upper two bits (bits 7 and 6) in SEGRAM.

When bit 7 is 1, only a bit set to “1” of the lower six bits is blinked on the display.

When bit 6 is 1, only a bit 4 pattern can be blinked as for a 5-dot font width, and only a bit 5

pattern can be blinked as for 6-dot font width.

6. Bit 5 (D5) is invalid for a 5-dot font width.

7. Set bits in the CGRAM data correspond to display selection, and zeros to non-selection.

313

HD66710

i) 5-dot font width (FW = 0)

S40

S10

S5

S1

S2

S3

S6

S7

S8

S36 S37 S38

S1

S2

S3

S9

S4

S39

ii) 6-dot font width (FW = 1)

S47

S5

S11

S5

S1

S2

S3

S6

S7

S8

S9

S12

S43 S44 S45

S48 S1

S2

S3

S6

S4

S10

S46

S4

<< Extension driver >>

Figure 9 Relationships between SEGRAM Data and Display

314

HD66710

Timing Generation Circuit

The timing generation circuit generates timing signals for the operation of internal circuits such as

DDRAM, CGROM, CGRAM, and SEGRAM. RAM read timing for display and internal operation timing

by MPU access are generated separately to avoid interfering with each other. Therefore, when writing

data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas

other than the display area.

Liquid Crystal Display Driver Circuit

The liquid crystal display driver circuit consists of 33 common signal drivers and 40 segment signal

drivers. When the character font and number of lines are selected by a program, the required common

signal drivers automatically output drive waveforms, while the other common signal drivers continue to

output non-selection waveforms.

Character pattern data is sent serially through a 40-bit shift register and latched when all needed data has

arrived. The latched data then enables the driver to generate drive waveform outputs.

Sending serial data always starts at the display data character pattern corresponding to the last address of

the display data RAM (DDRAM).

Since serial data is latched when the display data character pattern corresponding to the starting address

enters the internal shift register, the HD66710 drives from the head display.

Cursor/Blink Control Circuit

The cursor/blink (or white-black inversion) control is used to produce a cursor or a flashing area on the

display at a position corresponding to the location in stored in the address counter (AC).

For example (Figure 10), when the address counter is 08H, a cursor is displayed at a position

corresponding to DDRAM address 08H.

315

HD66710

AC6 AC5 AC4 AC3 AC2 AC1 AC0

AC

0

1

0

For a 1-line display

Display position

1

2

3

4

5

6

7

8

9

10

09

11

0A

DDRAM address

(hexadecimal)

00

01

02

03

04

05

06

07

08

Cursor position

For a 2-line display

Display position

1

2

3

4

5

6

7

8

9

10

09

49

11

0A

4A

00

40

01

41

02

42

03

43

04

44

05

45

06

46

07

47

08

48

DDRAM address

(hexadecimal)

Cursor position

Note: Even if the address counter (AC) points to an address in the character generator RAM (CGRAM) or

segment RAM (SEGRAM), cursor/blink black-white inversion will still occur, although it will produce

meaningless results.

Figure 10 Cursor/Blink Display Example

316

HD66710

Interfacing to the MPU

The HD66710 can send data in either two 4-bit operations or one 8-bit operation, thus allowing

interfacing with 4- or 8-bit MPUs.

•

For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3

are disabled. The data transfer between the HD66710 and the MPU is completed after the 4-bit data

has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit

operation, DB4 to DB7) are transfered before the four low order bits (for 8-bit operation, DB0 to

DB3).

The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two

more 4-bit operations then transfer the busy flag and address counter data.

•

For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.

RS

R/W

E

DB7

DB6

DB5

DB4

IR7

IR6

IR5

IR4

IR3

IR2

IR1

IR0

BF

AC3

AC2

AC1

AC0

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

AC6

AC5

AC4

Instruction register (IR)

write

Busy flag (BF) and

address counter (AC)

read

Data register (DR)

read

Figure 11 4-Bit Transfer Example

317

HD66710

Reset Function

Initializing by Internal Reset Circuit

An internal reset circuit automatically initializes the HD66710 when the power is turned on. The

following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state

until the initialization ends (BF = 1). The busy state lasts for 15 ms after V_CCrises to 4.5V or 40 ms after

the V_CCrises to 2.7V.

1. Display clear

2. Function set:

DL = 1; 8-bit interface data

N = 0; 1-line display

RE = 0; Extension register write disable

3. Display on/off control:

D = 0; Display off

C = 0; Cursor off

B = 0; Blinking off

BE = 0; CGRAM/SEGRAM blinking off

LP = 0; Not in low power mode

4. Entry mode set:

I/D = 1; Increment by 1

S = 0; No shift

5. Extension function set:

FW = 0; 5-dot character width

B/W = 0; Normal cursor (eighth line)

NW = 0; 1- or 2-line display (depending on N)

6. SEGRAM address set:

HDS = 000; No scroll

Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using

Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail

to initialize the HD66710. For such a case, initialization must be performed by the MPU as

explained in the section, Initializing by Instruction.

318

HD66710

Instructions

Outline

Only the instruction register (IR) and the data register (DR) of the HD66710 can be controlled by the

MPU. Before starting internal operation of the HD66710, control information is temporarily stored in

these registers to allow interfacing with various MPUs, which operate at different speeds, or various

peripheral control devices. The internal operation of the HD66710 is determined by signals sent from the

MPU. These signals, which include register selection (RS), read/write (R/ ), and the data bus (DB0 to

DB7), make up the HD66710 instructions (Table 7). There are four categories of instructions that:

•

Designate HD66710 functions, such as display format, data length, etc.

Set internal RAM addresses

Perform data transfer with internal RAM

Perform miscellaneous functions

Normally, instructions that perform data transfer with internal RAM are used the most. However, auto-

incrementation by 1 (or auto-decrementation by 1) of internal HD66710 RAM addresses after each data

write can lighten the program load of the MPU. Since the display shift instruction (Table 7) can perform

concurrently with display data write, the user can minimize system development time with maximum

programming efficiency.

When an instruction is being executed for internal operation, no instruction other than the busy

flag/address read instruction can be executed.

Because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0

before sending another instruction from the MPU.

Note: Be sure the HD66710 is not in the busy state (BF = 1) before sending an instruction from the

MPU to the HD66710. If an instruction is sent without checking the busy flag, the time between

the first instruction and next instruction will take much longer than the instruction time itself.

Refer to Table 7 for the list of each instruction execution time.

319

HD66710

Table 7

Instructions

Execution Time

Code

(Max) (when f_cpor

Instruction RS R/

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description

f_OSCis 270 kHz)

Clear

display

0

1

Clears entire display and

sets DDRAM address 0 in

address counter.

1.52 ms

Return

home

0

1

—

Sets DDRAM address 0 in

address counter. Also

returns display from being

shifted to original position.

DDRAM contents remain

unchanged.

Entry mode 0

set

0

1

I/D

C

S

B

Sets cursor move direction 37 µs

and specifies display shift.

These operations are

performed during data write

and read.

Display

on/off

0

1

D

Sets entire display (D) on/off, 37 µs

cursor on/off (C), and

blinking of cursor position

character (B).

control

(RE = 0)

Extension

function set

(RE = 1)

FW B/W NW Sets a font width, a black-

white inverting cursor (B/W),

a 6-dot font width (FW), and

a 4-line display (NW).

37 µs

Cursor or

display

shift

0

1

S/C R/L

—

Moves cursor and shifts

display without changing

DDRAM contents.

37 µs

Function

set

(RE = 0)

DL

N

RE

—

Sets interface data length

(DL), number of display lines

(N), and extension register

write enable (RE).

(RE = 1)

0

1

DL

RE BE LP Sets CGRAM/SEGRAM

blinking enable (BE), and low

power mode (LP). LP is

available when the EXT pin

is low.

37 µs

Set

0

1

ACG ACG ACG ACG ACG ACG Sets CGRAM address.

CGRAM data is sent and

37 µs

CGRAM

address

(RE = 0)

received after this setting.

Set

ADD ADD ADD ADD ADD ADD ADD Sets DDRAM address.

DDRAM data is sent and

DDRAM

address

(RE = 0)

received after this setting.

Set

HDS HDS HDS *— ASG ASG ASG Sets SEGRAM address.

DDRAM data is sent and

SEGRAM

address

(RE = 1)

received after this setting.

Also sets a horizontal dot

scroll quantity (HDS).

320

HD66710

Table 7

Instructions (cont)

Execution Time

Code

(max) (when f_cpor

Instruction RS R/

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description

f_OSCis 270 kHz)

Read busy

flag &

0

1

BF AC AC AC AC AC AC AC Reads busy flag (BF)

indicating internal operation

0 µs

address

is being performed and reads

address counter contents.

Write data

to RAM

(RE = 0/1)

1

0

Write data

Read data

Writes data into DDRAM,

CGRAM, or SEGRAM. To

write data to DDRAM

CGRAM, clear RE to 0; or to

write data to SEGRAM, set

RE to 1.

37 µs

t_ADD= 5.5 µs*

Read data

from RAM

(RE = 0/1)

1

Reads data from DDRAM,

CGRAM, or SEGRAM. To

read data from DDRAM or

CGRAM, clear RE to 0; to

read data from SEGRAM,

set RE to 1.

37 µs

t_ADD= 5.5 µs*

I/D = 1: Increment

I/D = 0: Decrement

DDRAM: Display data

RAM

S

D

C

B

= 1: Accompanies display shift

= 1: Display on

= 1: Cursor on

CGRAM: Character

generator RAM

SEGRAM: Segment RAM

= 1: Blink on

FW = 1: 6-dot font width

B/W = 1: Black-white inverting cursor on

NW = 1: Four lines

NW = 0: One or two lines

S/C = 1: Display shift

ACG: CGRAM address

S/C = 0: Cursor move

R/L = 1: Shift to the right

R/L = 0: Shift to the left

DL = 1: 8 bits, DL = 0: 4 bits

ADD: DDRAM address

(corresponds to

cursor address)

ASEG:Segment RAM

address

N

= 1: 2 lines, N = 0: 1 line

RE = 1: Extension register access enable

BE = 1: CGRAM/SEGRAM blinking enable

LP = 1: Low power mode

HDS: Horizontal dot scroll

quantity

BF = 1: Internally operating

BF = 0: Instructions acceptable

AC:

Address counter

used for both DD,

CG, and SEGRAM

addresses.

Notes: 1. — indicates no effect.

*

After execution of the CGRAM/DDRAM/SEGRAM data write or read instruction, the RAM

address counter is incremented or decremented by 1. The RAM address counter is updated

after the busy flag turns off.

In Figure 12, t_ADDis the time elapsed after the busy flag turns off until the address counter is

updated.

2. Extension time changes as frequency changes. For example, when f is 300 kHz, the execution

time is: 37 µs × 270/300 = 33 µs.

3. Execution time in a low power mode (LP = 1 & EXT = low) becomes four times as long as for a

1-line mode, and twice as long as for a 2- or 4-line mode.

321

HD66710

Busy state

(DB7 pin)

Busy state

Address counter

(DB0 to DB6 pins)

A

A + 1

t_ADD

Note: t _ADDdepends on the operation frequency

t _ADD= 1.5/(f_cpor f_OSC) seconds

Figure 12 Address Counter Update

322

HD66710

Instruction Description

Clear Display

Clear display writes space code (20)H (character pattern for character code (20)H must be a blank

pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter, and returns

the display to its original status if it was shifted. In other words, the display disappears and the cursor or

blinking goes to the left edge of the display (in the first line if 2 lines are displayed). It also sets I/D to 1

(increment mode) in entry mode. S of entry mode does not change. It resets the extended register enable

bit (RE) to 0 in function set.

Return Home

Return home sets DDRAM address 0 into the address counter, and returns the display to its original status

if it was shifted. The DDRAM contents do not change.

The cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed). It resets

the extended register enable bit (RE) to 0 in function set. In addition, flicker may occur in a moment at

the time of this instruction issue.

Entry Mode Set

I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is

written into or read from DDRAM.

The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1.

The same applies to writing and reading of CGRAM and SEGRAM.

S: Shifts the entire display either to the right (I/D = 0) or to the left (I/D = 1) when S is 1 during DDRAM

write. The display does not shift if S is 0.

If S is 1, it will seem as if the cursor does not move but the display does. The display does not shift when

reading from DDRAM. Also, writing into or reading out from CGRAM and SEGRAM does not shift the

display. In a low power mode (LP = 1), do not set S = 1 because the whole display does not normally

shift.

Display On/Off Control

When extension register enable bit (RE) is 0, bits D, C, and B are accessed.

D: The display is on when D is 1 and off when D is 0. When off, the display data remains in DDRAM,

but can be displayed instantly by setting D to 1.

C: The cursor is displayed when C is 1 and not displayed when C is 0. Even if the cursor disappears, the

function of I/D or other specifications will not change during display data write. The cursor is displayed

using 5 dots in the 8th line for 5 × 8 dot character font.

323

HD66710

B: The character indicated by the cursor blinks when B is 1 (Figure 13). The blinking is displayed as

switching between all blank dots and displayed characters at a speed of 370-ms intervals when f_cpor f_OSCis

270 kHz. The cursor and blinking can be set to display simultaneously. (The blinking frequency changes

according to f_OSCor the reciprocal of f_cp. For example, when f_cpis 300 kHz, 370 × 270/300 = 333 ms.)

Extended Function Set

When the extended register enable bit (RE) is 1, FW, B/W, and NW bit shown below are accessed. Once

these registers are accessed, the set values are held even if the RE bit is set to zero.

FW: When FW is 1, each displayed character is controlled with a 6-dot width. The user font in CGRAM

is displayed with a 6-bit character width from bits 5 to 0. As for fonts stored in CGROM, no display area

is assigned to the leftmost bit, and the font is displayed with a 5-bit character width. If the FW bit is

changed, data in DDRAM and CGRAM SEGRAM is destroyed. Therefore, set FW before data is written

to RAM. When font width is set to 6 dots, the frame frequency decreases to 5/6 compared to 5-dot time.

See “Oscillator Circuit” for details.

B/W: When B/W is 1, the character at the cursor position is cyclically displayed with black-white

invertion. At this time, bits C and B in display on/off control register are “Don’t care”. When f_CPor f_OSCis

270 kHz, display is changed by switching every 370 ms.

NW: When NW is 1, 4-line display is performed. At this time, bit N in the function set register is “Don’t

care”.

Note: After changing the N or NW or LP bit, please issue the return home or clear display instructions

to cancel to shift display.

Alternating

display

i) Cursor display example

ii) Blink display example

Alternating

display

iii) White-black inverting

display example

Figure 13 Cursor Blink Width Control

324

HD66710

i) 5-dot character width

ii) 6-dot character width

Figure 14 Character Width Control

Cursor or Display Shift

Cursor or display shift shifts the cursor position or display to the right or left without writing or reading

display data (Table 8). This function is used to correct or search the display. In a 2-line display, the

cursor moves to the second line when it passes the 40th digit of the first line. In a 4-line display, the

cursor moves to the second line when it passes the 20th character of the line. Note that, all line displays

will shift at the same time. When the displayed data is shifted repeatedly each line moves only

horizontally. The second line display does not shift into the first line position.

These instruction reset the extended register enable bit (RE) to 0 in function set.

The address counter (AC) contents will not change if the only action performed is a display shift.

In low power mode (LP = 1), whole-display shift cannot be normally performed.

Function Set

Only when the extended register enable bit (RE) is 1, the BE bit shown below can be accessed. Bits DL

and N can be accessed regardless of RE.

DL: Sets the interface data length. Data is sent or received in 8-bit lengths (DB7 to DB0) when DL is 1,

and in 4-bit lengths (DB7 to DB4) when DL is 0.

When 4-bit length is selected, data must be sent or received twice.

Table 8

Shift Function

S/C

0

R/L

0

Shifts the cursor position to the left. (AC is decremented by one.)

0

1

Shifts the cursor position to the right. (AC is incremented by one.)

Shifts the entire display to the left. The cursor follows the display shift.

Shifts the entire display to the right. The cursor follows the display shift.

1

0

1

325

HD66710

N: When bit NW in the extended function set is 0, a 1- or a 2-line display is set. When N is 0, 1-line

display is selected; when N is 1, 2-line display is selected. When NW is 1, a 4-line display is set. At this

time, N is “Don’t care”.

RE: When the RE bit is 1, bit BE and LP in the extended function set registe, the SEGRAM address set

register, and the extended function set register can be accessed. When bit RE is 0, the registers described

above cannot be accessed, and the data in these registers is held.

To maintain compatibility with the HD44780, the RE bit should be fixed to 0.

Clear display, return home and cursor or display shift instruction a reset the RE bit to 0.

BE: When the RE bit is 1, this bit can be rewritten. When this bit is 1, the user font in CGRAM and the

segment in SEGRAM can be blinked according to the upper two bits of CGRAM and SEGRAM.

LP: When the RE bit is 1, this bit can be rewritten. When LP is set to 1 and the EXT pin is low (without

an extended driver), the HD66710 operates in low power mode. In 1-line display mode, the HD66710

operates on a 4-division clock, and in a 2-line or a 4-line display mode, the HD66710 operates on a 2-

division clock. According to these operations, instruction execution takes four times or twice as long.

Notice that in a low power mode, display shift cannot be performed.

Note: Perform the DL, N, NW, FW functions at the head of the program before executing any

instructions (except for the read busy flag and address instruction). From this point, if bit N, NW,

or FW is changed after other instructions are executed, RAM contents may be lost.

After changing the N or NW or LP bit, please issue the return home or clear display instruction

cancel to shift display.

Set CGRAM Address

A CGRAM address can be set while the RE bit is cleared to 0. Set CGRAM address sets the CGRAM

address binary AAAAAA into the address counter.

Data is then written to or read from the MPU for CGRAM.

Table 9

Display Line Set

No. of

Display

Lines

Character

Font

Duty

Factor

Maximum Number of Characters/1

Line with Extended Drivers

N

0

1

*

NW

0

1

2

4

5 × 8 dots

1/17

1/33

50 characters

30 characters

20 characters

0

1

Note:

*

Indicates don’t care.

326

HD66710

Set DDRAM Address

Set DDRAM address sets the DDRAM address binary AAAAAAA into the address counter while the RE

bit is cleared to 0.

Data is then written to or read from the MPU for DDRAM.

However, when N and NW is 0 (1-line display), AAAAAAA can be 00H to 4FH. When N is 1 and NW is

0 (2-line display), AAAAAAA is (00)H to (27)H for the first line, and (40)H to (67)H for the second line.

When NW is 1 (4-line display), AAAAAAA is (00)H to (13)H for the first line, (20)H to (33)H for the

second line, (40)H to (53)H for the third line, and (60)H to (73)H for the fourth line.

Set SEGRAM Address

Only when the extended register enable bit (RE) is 1, HS2 to HS0 and the SEGRAM address can be set.

The SEGRAM address in the binary form AAA is set to the address counter. SEGRAM can then be

written to or read from by the MPU.

Note: When performing a horizontal scroll is described above by connecting an extended driver, the

maximum number of characters per line decreases by one. In other words, 49 characters, 29

characters, and 19 characters are displayed in 1-line, 2-line, and 4-line modes, respectively.

Notice that in low power mode (LP = 1), the display shift and scroll cannot be performed.

Read Busy Flag and Address

Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating

on a previously received instruction. If BF is 1, the internal operation is in progress. The next instruction

will not be accepted until BF is reset to 0. Check the BF status before the next write operation. At the

same time, the value of the address counter in binary AAAAAAA is read out. This address counter is

used by all CG, DD, and SEGRAM addresses, and its value is determined by the previous instruction.

The address contents are the same as for CGRAM, DDRAM, and SEGRAM address set instructions.

Table 10

HS2 to HS0 Settings

HS2

0

HS1

0

HS0

Description

0

No shift.

0

1

Shift the display position to the left by one dot.

Shift the display position to the left by two dots.

Shift the display position to the left by three dots.

Shift the display position to the left by four dots.

Shift the display position to the left by five dots.

No shift.

0

1

0

1

0

1

0

1

0 or 1

327

HD66710

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Clear

display

Code

0

1

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Return

home

Note: * Don’t care.

0

1

*

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

I/D

Entry

mode set

0

1

S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Display

on/off control

0

1

D

C

B

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

FW B/W NW

RE = 1

Code

Extended

function set

0

1

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

3/C R/L

Cursor or

display shift

Code

0

1

*

Note: * Don’t care.

Note: * BE and LP

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DL RE BE* LP*

0

N

Function set

can be rewritten

while RE = 1.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Set CGRAM

address

0

1

A

RE = 0

Code

Highest

order bit

Lowest

order bit

Figure 15 Character Width Control

328

HD66710

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

A

Set DDRAM

address

RE = 0

Highest

order bit

Lowest

order bit

DB6 DB5

DB3

DB2 DB1 DB0

RS R/W DB7

DB4

HS0

RE = 1

Code

Set SEGRAM

address

0

1

A

HS2 HS1

*

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Read busy flag

and address

0

1

BF

A

Highest

order bit

Lowest

order bit

Figure 15 Character Width Control (cont)

329

HD66710

Write Data to CG, DD, or SEGRAM

This instruction writes 8-bit binary data DDDDDDDD to CG, DD or SEGRAM. If the RE bit is cleared,

CG or DDRAM is selected, as determined by the previous specification of the address set instruction; if

the RE bit is set, SEGRAM is selected. After a write, the address is automatically incremented or

decremented by 1 according to the entry mode. The entry mode also determines the display shift

direction.

Read Data from CG, DD, or SEGRAM

This instruction reads 8-bit binary data DDDDDDDD from CG, DD, or SEGRAM. If the RE bit is

cleared, CG or DDRAM is selected, as determined by the previous specification of the address set

instruction; if the RE bit is set, SEGRAM is selected. If no address is specified, the first data read will be

invalid. When executing serial read instructions, the next address is normally read from the next address.

An address set instruction need not be executed just before this read instruction when shifting the cursor

by a cursor shift instruction (when reading from DDRAM). A cursor shift instruction is the same as a set

DDRAM address instruction.

After a read, the entry mode automatically increases or decreases the address by 1. However, a display

shift is not executed regardless of the entry mode.

Note: The address counter (AC) is automatically incremented or decremented after write instructions to

CG, DD or SEGRAM. The RAM data selected by the AC cannot be read out at this time even if

read instructions are executed. Therefore, to read data correctly, execute either an address set

instruction or a cursor shift instruction (only with DDRAM), or alternatively, execute a

preliminary read instruction to ensure the address is correctly set up before accessing the data.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Write data to

CG, DD, or SEGRAM

1

0

D

RE = 0/1

Code

Higher

Lower

order bits

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RE = 0/1

Code

Read data from

CG, DD, or SEGRAM

1

0

D

Higher

Lower

order bits

Figure 15 Character Width Control (cont)

330

HD66710

Interfacing the HD66710

1) Interface to 8-Bit MPUs

HD66710 can interface to 8-bit MPU directly with E clock, or to 8-bit MCU through I/O port. When

number of I/O port in MCU, or interfacing bus width, 4-bit interface function is useful.

RS

R/W

E

Internal

signal

Internal operation

Busy

Not

Busy

DB7

Data

Busy

Instruction

write

Instruction

write

Busy flag check Busy flag check Busy flag check

Figure 16 Example of 8-Bit Data Transfer Timing Sequence

Connection to H8/325 with port (when single chip mode)

C0

C1

C2

E

H8/325

HD66710

RS

R/W

8

A0–A7

DB0–DB7

Figure 17 8-Bit MPU Interface

331

HD66710

2) Interface to 4-Bit MPUs

HD66710 can interface to 4-bit MCU through I/O port. 4-bit data for high and low order must be

transferred twice continuously. The DL bit in function set selects the interface data length.

RS

R/W

E

Internal

signal

Internal operation

Not

Busy

Busy AC3

AC3

D7

D3

DB7

IR7 IR3

Instruction

write

Instruction

write

Busy flag check

Figure 18 Example of 4-Bit Data Transfer Timing Sequence

HMCS4019R

HD66710

COM1–

16

40

D15

D14

D13

RS

R/W

E

COM16

Connected to

the LCD

SEG1–

SEG40

4

R10–R13

DB4 –DB7

Figure 19 Interface to HMCS4019R

332

HD66710

Oscillator Circuit

•

Relationship between Oscillation frequency and Liquid Crystal Display Frame Frequency

The liquid crystal display frame frequencies of Figure 21 apply only when the oscillation frequency is

270 kHz (one clock period: 3.7 µs).

1) When an external clock is used

2) When an internal oscillator is used

The oscillator frequency can be

adjusted by oscillator resistance

(Rf). If Rf is increased or power

supply voltage is decreased, the

oscillator frequency decreases.

The recommended oscillator

resistor is as follows.

Clock

OSC1

Rf

OSC2

HD66710

• Rf = 91 kΩ ± 2% (V_CC= 5V)

• Rf = 75 kΩ ± 2% (V_CC= 3V)

Figure 20 Oscillator Circuit

(1) 1 /17 duty cycle

200 clocks (6-dot font width: 240 clocks)

1

2

3

4

16 17

1

2

3

16 17

V_CC

V1

COM1

V4

V5

1 frame

Normal Display Mode (LP = 0)

5-Dot Font Width 6-Dot Font Width

Low Power Mode (LP = 1)

5-Dot Font Width 6-Dot Font Width

Item

Line selection period 200 clocks

Frame frequency

240 clocks

66.2 Hz

50 clocks

79.4 Hz

60 clocks

66.2 Hz

79.4 Hz

(2) 1 /33 duty cycle

100 clocks (6-dot font width: 120 clocks)

1

2

3

4

32 33

1

2

3

32 33

V_CC

V1

COM1

V4

V5

1 frame

Normal Display Mode (LP = 0)

5-Dot Font Width 6-Dot Font Width

Low Power Mode (LP = 1)

5-Dot Font Width 6-Dot Font Width

Item

Line selection period 100 clocks

Frame frequency

120 clocks

68.2 Hz

50 clocks

81.8 Hz

60 clocks

68.2 Hz

81.8 Hz

Figure 21 Frame Frequency

333

HD66710

Power Supply for Liquid Crystal Display Drive

1) When an external power supply is used

V_CC

R

V_CC

V1

V2

V3

V4

V5

R

R0

R

VR

V_EE

2) When an internal booster is used

(Boosting twice)

(Boosting three times)

V_CC

Vci

NTC-type

Vci

NTC-type

R

V1

V2

V3

V4

V5

V1

GND

thermistor

GND

thermistor

GND

V2

R0

R

R0

R

C1

C2

C1

V3

C2

1µF

+

V4

V5OUT2

V5OUT3

V5OUT2

R

V5

1µF

V5OUT3

+

1µF

+

GND

Notes: 1. Boosting output voltage should not exceed the power supply voltage (2) (13V max.)

in the absolute maximum ratings. Especially, voltage of over 4.3V should not be input

to the reference voltage (Vci) when boosting three times.

2. Vci input terminal is used for reference voltage and power supply for the internal booster.

Input current into the Vci pin needs three times or more of load current through the

bleeder resistor for LCD. So, when it adjusts LCD driving voltage (Vlcd), input voltage

should be controlled with transistor to supply LCD load current.

3. Please notice connection (+/–) when it uses capacitors with poler.

334

HD66710

Table 11

Duty Factor and Power Supply for Liquid Crystal Display Drive

Item

Data

Number of Lines

Duty factor

1

2/4

1/17

1/5

R

1/33

1/6.7

R

Bias

Divided resistance

R

R0

R

2.7R

Note: R changes depending on the size of liquid crystal penel. Normally, R must be 4.7 kΩ to 20 kΩ.

335

HD66710

Extension Driver LSI Interface

By bringing the EXT pin high, segment driver pins (SEG37 to SEG40) functions as the extended driver

interface outputs. From these pins, a latch pulse (CL1), a shift clock (CL2), data (D), and an AC signal

(M) are output. The same data is output from the SEG36 pin of the HD66710 and the start segment pin

(Seg1) of the extension driver. Due to the character baundary, the Seg1 output is used for the 5-dot font

width. For the 6-dot font width, the SEG36 output is used, and the Seg1 output of the extension driver

must not be used. When the extension driver LSI interface is used, ground level (GND) must be higher

than the V5 level.

Table 12

Required Number of 40-Output Extension Driver

Controller

Display Line

16 × 2 lines

20 × 2 lines

24 × 2 lines

40 × 2 lines

12 × 4 lines

16 × 4 lines

20 × 4 lines

HD66710*

HD44780

HD66702

5-Dot Width

Not required

1

5-Dot Width

6-Dot Width

5-Dot Width

Not required

1

2

1

2

Disabled

4

3

1

2

1

2

3

Disabled

Note:

*

The number of display lines can be extended to 30 × 2 lines or 20 × 4 lines.

1) 1-chip operation

(EXT = Low, 5-dot font width)

2) When using the extension driver

(EXT = High, 5-dot font width)

V_CC

EXT

HD66710

GND

EXT

COM1–

COM33

24 × 2-line display

SEG1–

SEG35

COM1–

COM33

HD66710

16 × 2-line display

SEG1–

SEG40

M

D

Seg1–

Seg35

SEG1–SEG40

CL2

CL1

Extension driver

Figure 22 HD66710 and the Extension Driver Connection

336

HD66710

When using one HD66710, the start address of COM9–COM16/COM25–COM33 is calculated by adding

8 to the start address of COM9–COM16 COM25–COM32. When extending the address, the start address

is calculated by adding A(10) to COM9–COM16/COM25 to COM32. The relationship betweenmodes

and display start addresses is shown below.

Table 13

Display Start Address in Each Mode

Number of Lines

2-Line Mode

1-Line Mode

4-Line Mode

EXT Low/High

D00±1

Output

EXT Low

D00±1

D08±1

—

EXT High

D00±1

D0A±1

—

EXT Low

D00±1

D08±1

D40±1

D48±1

—

EXT High

D00±1

D0A±1

D40±1

D4A±1

—

COM1–COM8

COM9–COM16

COM17–COM24

COM25–COM32

COM17

D20±1

D40±1

—

D60±1

S00

—

COM33

—

S00

Notes: 1. When an EXT pin is low, the extension driver is not used; otherwise, the extension driver is

used.

2. D— is the start address of display data RAM (DDRAM) for each display line.

3. S— is the start address of segment RAM (SEGRAM).

4. ±1 following D— indicates increment or decrement at display shift.

337

HD66710

Interface to Liquid Crystal Display

•

Example of 5-dot font width connection

1

8

9

16

HD66710

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

±

+ – x ÷ = ≠

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG40

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

EXT

a) 16 × 1-line + 40-segment display (5-dot font, 1/17 duty)

1

8

9

16

HD66710

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM33

± + – x ÷ = ≠

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG40

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

EXT

b) 16 × 2-line + 40-segment display (5-dot font, 1/33 duty)

Figure 23 Liquid Crystal Display and HD66710 Connections (Single-Chip Operation)

338

HD66710

•

Example of 6-dot font width connection

1

2

6

7

8

12

HD66710

Note: The DDRAM address between

6th and 7th digits is not contiguous.

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

±

+

–

x

÷

= ≠

COM33

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG36

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

EXT

a) 12 × 2-line + 36-segment display (6-dot font, 1/33 duty)

Figure 24 Liquid Crystal Display and HD66710 Connections (6-Dot Font Width)

339

HD66710

Instruction and Display Correspondence

•

8-bit operation, 16-digit × 1-line display with internal reset

Refer to Table 14 for an example of an 16-digit × 1-line display in 8-bit operation. The HD66710

functions must be set by the function set instruction prior to the display. Since the display data RAM

can store data for 80 characters, a character unit scroll can be performed by a display shift instruction.

A dot unit smooth scroll can also be performed by a horizontal scroll instruction. Since data of display

RAM (DDRAM) is not changed by a display shift instruction, the display can be returned to the first

set display when the return home operation is performed.

•

4-bit operation, 16-digit × 1-line display with internal reset

The program must set all functions prior to the 4-bit operation (Table 15). When the power is turned

on, 8-bit operation is automatically selected and the first write is performed as an 8-bit operation.

Since DB0 to DB3 are not connected, a rewrite is then required. However, since one operation is

completed in two accesses for 4-bit operation, a rewrite is needed to set the functions (see Table 15).

Thus, DB4 to DB7 of the function set instruction is written twice.

8-bit operation, 16-digit × 2-line display with internal reset

For a 2-line display, the cursor automatically moves from the first to the second line after the 40th

digit of the first line has been written. Thus, if there are only 16 characters in the first line, the

DDRAM address must be again set after the 16th character is completed (See Table 16).

The display shift is performed for the first and second lines. If the shift is repeated, the display of the

second line will not move to the first line. The same display will only shift within its own line for the

number of times the shift is repeated.

•

8-bit operation, 8-digit × 4-line display with internal reset

The RE bit must be set by the function set instruction and then the NW bit must be set by an

extension function set instruction. In this case, 4-line display is always performed regardless of the N

bit setting (Table 17).

In a 4-line display, the cursor automatically moves from the first to the second line after the 20th digit

of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM

address must be set again after the 8th character is completed. Display shifts are performed on all

lines simultaneously.

Note: When using the internal reset, the electrical characteristics in the Power Supply Conditions Using

Internal Reset Circuit table must be satisfied. If not, the HD66710 must be initialized by

instructions. See the section, Initializing by Instruction.

340

HD66710

Table 14

8-Bit Operation, 16-Digit × 1-Line Display Example with Internal Reset

Instruction

Step

No. RS R/

D7

D6

D5

D4

D3

D2

D1

D0

Display

Operation

1

Power supply on (the HD66710 is initialized by the internal reset

circuit)

Initialized. No display.

2

Function set

Sets to 8-bit operation and

selects 1-line display.

0

1

0

1

0

1

0

1

*

Bit 2 must always be cleared.

3

4

Display on/off control

Turns on display and cursor.

Entire display is in space mode

because of initialization.

_

0

1

0

Entry mode set

Sets mode to increment the

address by one and to shift the

cursor to the right at the time of

write to the RAM.

0

Display is not shifted.

5

Write data to CGRAM/DDRAM

Writes H. DDRAM has already

been selected by initialization

when the power was turned on.

H_

1

0

1

0

1

0

1

6

7

Write data to CGRAM/DDRAM

Writes I.

HI_

1

0

1

0

·

8

Write data to CGRAM/DDRAM

Writes I.

HITACHI_

1

0

1

0

1

0

1

0

1

0

1

0

9

Entry mode set

Sets mode to shift display at the

time of write.

0

10

Write data to CGRAM/DDRAM

Writes a space.

ITACHI

_

1

0

1

341

HD66710

Table 14

8-Bit Operation, 16-Digit × 1-Line Display Example with Internal Reset (cont)

Instruction

Step

No. RS R/

D7

D6

D5

D4

D3

D2

D1

D0

Display

Operation

11

Write data to CGRAM/DDRAM

Writes M.

TACHI M_

1

0

1

0

1

0

1

12

·

13

14

15

16

17

18

19

20

Write data to CGRAM/DDRAM

Writes O.

MICROKO_

MICROK_O

ICROCO_

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

1

*

Cursor or display shift

Shifts only the cursor position to

the left.

0

Cursor or display shift

Shifts only the cursor position to

the left.

0

*

Write data to CGRAM/DDRAM

Writes C over K.

1

0

1

0

1

*

1

*

The display moves to the left.

Cursor or display shift

Shifts the display and cursor

position to the right.

MICROCO_

ICROCOM_

0

Cursor or display shift

Shifts the display and cursor

position to the right.

0

*

Write data to CGRAM/DDRAM

0 1 0

Writes M.

1

0

1

·

21

Return home

Returns both display and cursor

to the original position (address

0).

H_ITACHI

0

1

0

342

HD66710

Table 15

4-Bit Operation, 16-Digit × 1-Line Display Example with Internal Reset

Instruction

Step

No. RS R/

D7

D6

D5

D4

D3

D2

D1

D0

Display

Operation

1

Power supply on (the HD66710 is initialized by the internal reset

circuit)

Initialized. No display.

2

Function set

Sets to 4-bit operation.

Clear bit 2. In this case,

operation is handled as 8 bits by

initialization. *

0

1

0

—

3

Function set

Sets 4-bit operation and

selects1-line display. Clear BE,

LP bits. 4-bit operation starts

from this step.

0

1

0

—

4

5

6

7

Function set

Sets 4-bit operation and

selects1-line display. Clear RE

bit.

0

1

*

0

*

—

Return home

Returns both display and cursor

to the original position (address

0).

0

1

0

—

Display on/off control

Turns on display and cursor.

Entire display is in space mode

because of initialization.

_

0

1

0

1

0

1

0

—

Entry mode set

Sets mode to increment the

address by one and to shift the

cursor to the right at the time of

write to the DD/CGRAM.

Display is not shifted.

0

1

0

1

0

—

8

Write data to CGRAM/DDRAM

Writes H.

H_

1

0

1

0

—

DDRAM has already been

selected by initialization.

Note: 1. The control is the same as for 8-bit operation beyond step #8.

2. When DB3 to DB0 pins are open in 4-bit mode, the RE, BE, LP bits are set to “1” at step #2.

So, these bits are clear to “0” at step #3.

343

HD66710

Table 16

8-Bit Operation, 16-Digit × 2-Line Display Example with Internal Reset

Instruction

Step

No. RS R/

D7

D6

D5

D4

D3

D2

D1

D0

Display

Operation

1

2

Power supply on (the HD66710 is initialized by the internal reset

circuit)

Initialized. No display.

Function set

Sets to 8-bit operation and

selects 1-line display.

Clear bit 2.

0

1

0

1

0

1

0

1

*

3

4

Display on/off control

Turns on display and cursor. All

display is in space mode

because of initialization.

_

0

1

0

Entry mode set

Sets mode to increment the

address by one and to shift the

cursor to the right at the time of

write to the RAM.

0

Display is not shifted.

5

6

Write data to CGRAM/DDRAM

Writes H. DDRAM has already

been selected by initialization

when the power was turned on.

H_

1

0

1

0

1

0

·

7

8

Write data to CGRAM/DDRAM

Writes I.

HITACHI_

1

0

1

0

1

0

1

0

Set DDRAM address

Sets RAM address so that the

cursor is positioned at the head

of the second line.

HITACHI

_

0

1

0

344

HD66710

Table 16

8-Bit Operation, 16-Digit × 2-Line Display Example with Internal Reset (cont)

Instruction

Step

No. RS R/

D7

D6

D5

D4

D3

D2

D1

D0

Display

Operation

9

Write data to CGRAM/DDRAM

Writes a space.

HITACHI

M_

1

0

1

0

1

0

1

10

·

11

12

13

14

Write data to CGRAM/DDRAM

Writes O.

HITACHI

1

0

1

0

1

0

1

0

1

MICROCO_

Entry mode set

Sets mode to shift display at the

time of write.

HITACHI

0

MICROCO_

Write data to CGRAM/DDRAM

0 1 0

Writes M.

ITACHI

1

0

ICROCOM_

·

15

Return home

Returns both display and cursor

to the original position (address

0).

H_ITACHI

0

1

0

MICROCOM

345

HD66710

Table 17

8-Bit Operation, 8-Digit × 4-Line Display Example with Internal Reset

Instruction

Step

No. RS R/

D7

D6

D5

D4

D3

D2

D1

D0

Display

Operation

1

2

3

4

5

6

Power supply on (the HD66710 is initialized by the internal reset

circuit)

Initialized. No display.

Function set

Sets to 8 bit operation and the

extended register enable bit.

0

1

0

1

0

1

0

*

4-line mode set

Sets 4-line display.

0

1

Function set

Clear extended register enable bit

Clears the extended register

enable bit. Setting the N bit is

“don’t care”.

0

1

0

1

0

1

*

Display on/off control

Turns on display and cursor.

Entire display is in space mode

because of initialization.

_

0

1

0

Entry mode set

Sets mode to increment the

address by one and to shift the

cursor to the right at the time of

write to the RAM. Display is not

shifted.

0

1

0

1

0

7

Write data to CGRAM/DDRAM

Writes H. DDRAM has already

been selected by initialization

when the power was turned on.

H_

1

0

1

0

8

—

346

HD66710

Table 17

8-Bit Operation, 8-Digit × 4-Line Display Example with Internal Reset (cont)

Instruction

Step

No. RS R/

D7

D6

D5

D4

D3

D2

D1

D0

Display

Operation

9

Write data to CGRAM/DDRAM

Writes I.

HITACHI_

1

0

1

0

1

0

1

0

1

10

Set DDRAM address

Sets RAM address so that the

cursor is positioned at the head

of the second line.

HITACHI

_

0

1

0

1

0

11 Write data to CGRAM/DDRAM

Writes 0.

HITACHI

0_

1

0

1

347

HD66710

Initializing by Instruction

If the power supply conditions for correctly operating the internal reset circuit are not met, initialization

by instructions becomes necessary.

Power on

• Wait for more than 15 ms

after V_CCrises to 4.5V

(V_CC= 5V)

• Wait for more than 40 ms

after V_CCrises to 2.7V

(V_CC= 3V)

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

*

Wait for more than 4.1 ms

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

*

Wait for more than 100 µs

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

*

BF can be checked after the following instructions.

When BF is not checked, the waiting time between

instructions is longer than the execution instuction

time. (See Table 7.)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function set

0

1

N

0

*

0

*

0

1

S

Display off

0

1

0

1

0

Display clear

Entry mode set

I/D

Initialization ends

Figure 25 8-Bit Interface

348

HD66710

Power on

Important Notice

Notes: 1. When DB3 to DB0 pins are open in 4-bit mode,

the N, RE, BE, LP bits are set to “1”. In this case,

instruction time becomes four times in a low

power mode (LP = “1”).

• Wait for more than 15 ms

after V_CCrises to 4.5V

(V_CC= 5V)

• Wait for more than 40 ms

after V_CCrises to 2.7V

(V_CC= 3V)

2. The low power mode is available in this step, so

instruction time takes four times.

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

RS R/W DB7 DB6 DB5 DB4

0

1

Wait for more than 4.1 ms

RS R/W DB7 DB6 DB5 DB4

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

0

1

Wait for more than 100 µs

BF cannot be checked before this instruction.

Function set (Interface is 8 bits long.)

RS R/W DB7 DB6 DB5 DB4

*1

0

1

BF can be checked after the following instructions.

When BF is not checked, the waiting time between

instructions is longer than the execution instuction

time. (See Table 7.)

RS R/W DB7 DB6 DB5 DB4

*1

*2

0

1

0

Function set (4-bit mode).

0

N

0

N

0

1

0

1

0

1

0

*

Function set (4-bit mode, N specification).

BE, LP are clear to “0”

1

Function set (4-bit mode, N specification).

*

0

1

0

S

Display off

0

Display clear

0

Entry mode set (I/D, S specification)

I/D

Initialization ends

Figure 26 4-Bit Interface

349

HD66710

Horizontal Dot Scroll

Dot unit shifts are performed by setting the horizontal dot scroll bit (HDS) when the extension register is

enabled (RE = 1). By combining this with character unit display shift instructions, smooth horizontal

scrolling can be performed on a 6-dot font width display as shown below.

6-dot font width (FW = 1)

5-dot font width (FW = 0)

No shift performed

Shift to the left by one dot

Shift to the left by two dots

Shift to the left by three dots

Shift to the left by four dots

Shift to the left by one dot

Shift to the left by two dots

Shift to the left by three dots

Shift to the left by four dots

Shift to the left by five dots

Figure 27 Shift in 5- and 6-Dot Font Width

(1) Method of smooth scroll to the left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Enable the extension register

1

2

0

1

DL

N

1

*

0

1

0

1

Shift the whole display to the left by one dot

*

CPU Wait

Shift the whole display to the left by two dots

Shift the whole display to the left by three dots

Shift the whole display to the left by four dots

Shift the whole display to the left by five dots^*1

3

4

5

6

0

1

0

1

0

*

CPU Wait

1

CPU Wait

0

CPU Wait

0

1

CPU Wait

7

8

0

1

0

Perform no shift

*

Shift the whole display to the left by one character^*2

0

1

0

CPU Wait

Notes: 1. When the font width is five (FW = 0), this step is skipped.

2. The extended register enable bit (RE) is cleared.

Figure 28 Smooth Scroll to the Left

350

HD66710

(2) Method of smooth scroll to the right

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Shift the whole display to the right by one

character ^*2

1

2

0

1

*

0

1

DL

N

1

Enable the extension register

*

CPU Wait

Shift the whole display to the left by five dots^*1

Shift the whole display to the left by four dots

3

4

5

6

7

8

0

1

0

1

*

CPU Wait

0

CPU Wait

1

Shift the whole display to the left by three dots

Shift the whole display to the left by two dots

CPU Wait

1

0

CPU Wait

0

1

Shift the whole display to the left by one dot

Perform no shift

CPU Wait

0

Notes: 1.

2.

When the font width is five (FW = 0), this step is skipped.

The extended register enable bit (RE) is cleared.

Figure 28 Smooth Scroll to the Left (cont)

351

HD66710

Low Power Mode

When LP bit is 1 and the EXT pin is low (without an extended driver), the HD66710 operates in low

power mode. In 1-line display mode, the HD66710 operates on a 4-division clock, and in 2-line or 4-line

display mode, it operates on 2-division clock. So, instruction execution takes four times or twice as long.

Notice that in this mode, display shift and scroll cannot be performed. Clear display shift with the return

home instruction, and the horizontal scroll quantity.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Extended register enable

0

1

DL

N

BE

0

1

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AS2 AS1 AS0

Clear horizontal scroll quantity

HDS = “000”

0

1

0

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DL BE

Set a low power mode

Return home

0

1

N

1

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

Note: In this operation, instruction execution time

takes four times or twice as long.

Low power operation

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Reset a power mode

Return home

0

1

DL

N

BE

1

0

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

Figure 29 Low Power Mode Operation

352

HD66710

Absolute Maximum Ratings

Item

Symbol

Value

Unit

V

Notes*

Power supply voltage (1)

Power supply voltage (2)

Input voltage

V_CC

–0.3 to +7.0

–0.3 to +15.0

–0.3 to V_CC+0.3

–20 to +75

–55 to +125

1

V_CC–V5

Vt

V

1, 2

1

V

Operating temperature

Storage temperature

T_opr

°C

T_stg

4

Notes: If the LSI is used above these absolute maximum ratings, it may become permanently damaged.

Using the LSI within the following electrical characteristic limits is strongly recommended for normal

operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction

and cause poor reliability.

* Refer to the Electrical Characteristics Notes section following these tables.

353

HD66710

DC Characteristics (V_CC= 2.7V to 5.5V, T_a= –20°C to +75°C*³)

Item

Symbol Min

Typ

Max

Unit

Test Condition

Notes*

Input high voltage (1) VIH1

(except OSC1)

0.7V_CC

—

V_CC

V

6

Input low voltage (1)

(except OSC1)

VIL1

–0.3

—

0.2V_CC

0.6

V

6

–0.3

Input high voltage (2) VIH2

(OSC1)

0.7V_CC

V_CC

V

15

7

Input low voltage (2)

(OSC1)

VIL2

—

2

0.2V_CC

—

V

Output high voltage (1) VOH1 0.75V_CC

(D0–D7)

V

–I_OH= 0.1 mA

I_OL= 0.1 mA

Output low voltage (1) VOL1

(D0–D7)

—

0.2V_CC

—

V

7

Output high voltage (2) VOH2 0.8V_CC

(except D0–D7)

V

–I_OH= 0.04 mA

I_OL= 0.04 mA

8

Output low voltage (2) VOL2

(except D0–D7)

—

0.2V_CC

20

V

8

Driver on resistance

(COM)

R_COM

kΩ

±Id = 0.05 mA (COM)

VLCD = 4V

13

9

Driver on resistance

(SEG)

R_SEG

2

30

±Id = 0.05 mA (SEG)

VLCD = 4V

I/O leakage current

Pull-up MOS current

I_LI

–1

5

—

1

µA

VIN = 0 to V_CC

–Ip

50

120

V

= 3V

(D0–D7, RS, R/

)

V^CIN^C= 0V

Power supply current

I_CC

—

150

80

300

—

µA

R_foscillation, external clock 10, 14

V_CC= 3V, f_OSC= 270 kHz

I_LP1

I_LP2

LP mode, 1/17 duty

V_CC= 3V, f_OSC= 270 kHz

100

—

LP mode, 1/33 duty

V_CC= 3V, f_OSC= 270 kHz

LCD voltage

VLCD1 3.0

VLCD2 3.0

—

13.0

V

V_CC–V5, 1/5 bias

16

V_CC–V5, 1/6.7 bias

Note:

*

Refer to the Electrical Characteristics Notes section following these tables.

Booster Characteristics

Item

Symbol Min

Typ

Max

Unit

Test Condition

Notes*

Output voltage

(V5OUT2 pin)

VUP2 7.5

8.7

—

V

Vci = 4.5V, I0 = 0.25 mA,

C = 1 µF, f_OSC= 270 kHz,

T_a= 25°C

18, 19

Output

VUP3 7.0

7.7

—

V

Vci = 2.7V, I0 = 0.25 mA,

C = 1 µF, f_OSC= 270 kHz,

T_a= 25°C

18, 19

voltage(V5OUT3 pin)

Input voltage

Note:

VCi

1.0

5.0

18, 19,

20

*

Refer to the Electrical Characteristics Notes section following these tables.

354

HD66710

AC Characteristics (V_CC= 2.7V to 5.5V, T_a= –20°C to +75°C*³)

Clock Characteristics

Item

Symbol Min

Typ

270

50

Max Unit Test Condition Notes*

External

clock

operation

External clock frequency

External clock duty

f_cp

125

45

350

55

kHz

%

11

Duty

t_rcp

External clock rise time

External clock fall time

—

0.2

350

µs

t_fcp

—

µs

R_f

Clock oscillation frequency f_OSC

190

270

kHz

R_f= 91 kΩ,

12

oscillation

V_CC= 5V

Note:

*

Refer to the Electrical Characteristics Notes section following these tables.

Bus Timing Characteristics (1) (V_CC= 2.7V to 4.5V, T_a= –20°C to +75°C*³)

Write Operation

Item

Symbol Min

Typ

—

Max

—

Unit

Test Condition

Enable cycle time

Enable pulse width (high level)

Enable rise/fall time

t_cycE

1000

450

—

ns

Figure 30

PW_EH

t_Er, t_Ef

—

25

—

Address set-up time (RS, R/ to E) t_AS

60

Address hold time

Data set-up time

Data hold time

t_AH

t_DSW

t_H

20

—

195

10

—

Read Operation

Item

Symbol Min

Typ

—

Max

—

Unit

Test Condition

Enable cycle time

Enable pulse width (high level)

Enable rise/fall time

t_cycE

1000

450

—

ns

Figure 31

PW_EH

t_Er, t_Ef

—

25

—

Address set-up time (RS, R/ to E) t_AS

60

Address hold time

Data delay time

Data hold time

t_AH

20

—

t_DDR

t_DHR

—

360

—

5

355

HD66710

Bus Timing Characteristics (2) (V_CC= 4.5V to 5.5V, T_a= –20°C to +75°C*³)

Write Operation

Item

Symbol Min

Typ

—

Max

—

Unit

Test Condition

Enable cycle time

Enable pulse width (high level)

Enable rise/fall time

t_cycE

500

230

—

ns

Figure 30

PW_EH

t_Er, t_Ef

—

20

—

Address set-up time (RS, R/ to E) t_AS

40

Address hold time

Data set-up time

Data hold time

t_AH

t_DSW

t_H

10

—

80

—

10

—

Read Operation

Item

Symbol Min

Typ

—

Max

—

Unit

Test Condition

Enable cycle time

Enable pulse width (high level)

Enable rise/fall time

t_cycE

500

230

—

ns

Figure 31

PW_EH

t_Er, t_Ef

—

20

—

Address set-up time (RS, R/ to E) t_AS

40

10

—

Address hold time

Data delay time

Data hold time

t_AH

—

t_DDR

t_DHR

160

—

5

Segment Extension Signal Timing (V_CC= 2.7V to 5.5V, T_a= –20°C to +75°C*³)

Item

Symbol Min

Typ

—

Max

—

Unit

Test Condition

Clock pulse width

High level

Low level

t_CWH

t_CWL

t_CSU

t_SU

500

300

–1000

—

ns

Figure 32

—

Clock set-up time

Data set-up time

Data hold time

M delay time

—

t_DH

—

t_DM

t_ct

1000

600

Clock rise/fall time

356

HD66710

Power Supply Conditions Using Internal Reset Circuit

Item

Symbol Min

Typ

—

Max

10

Unit

Test Condition

Power supply rise time

Power supply off time

t_rCC

0.1

1

ms

Figure 33

t_OFF

—

Electrical Characteristics Notes

1. All voltage values are referred to GND = 0V. If the LSI is used above these absolute maximum

ratings, it may become permanently damaged. Using the LSI within the following electrical

characteristic limits is strongly recommended for normal operation. If these electrical characteristic

conditions are also exceeded, the LSI will malfunction and cause poor reliability.

2. V_CC≥ V5 must be maintained. In addition, if the SEG37/CL1, SEG38/CL2, SEG39/D, and SEG40/M

are used as extension driver interface signals (EXT = high), GND ≥ V5 must be maintained.

3. For die products, specified up to 75°C.

4. For die products, specified by the die shipment specification.

5. The following four circuits are I/O pin configurations except for liquid crystal display output.

Input pin

Pin: E (MOS without pull-up)

Pins: RS, R/W (MOS with pull-up)

V_CC

V_CCV_CC

PMOS

NMOS

(pull up MOS)

NMOS

I/O pin

Pins: DB0 –DB7

V_CC

(MOS with pull-up)

(pull-up MOS)

(input circuit)

PMOS

Input enable

NMOS

V_CC

NMOS

PMOS

Output enable

data

NMOS

(output circuit)

(tristate)

357

HD66710

6. Applies to input pins and I/O pins, excluding the OSC1 pin.

7. Applies to I/O pins.

8. Applies to output pins.

9. Current flowing through pull-up MOSs, excluding output drive MOSs.

10. Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive

current flows through the input circuit to the power supply. To avoid this from happening, the input

level must be fixed high or low.

11. Applies only to external clock operation.

T_h

T_l

Oscillator

Open

OSC1

OSC2

0.7 V_CC

0.5 V_CC

0.3 V_CC

t_rcp

× 100%

t_fcp

T_h

_h+ T_l

Duty =

T

12. Applies only to the internal oscillator operation using oscillation resistor Rf.

R_f: 75 kΩ ± 2% (when V_CC= 3 V to 4V)

OSC1

R_f: 91 kΩ ± 2% (when V_CC= 4 V to 5V)

R_f

Since the oscillation frequency varies depending on the OSC1 and

OSC2 pin capacitance, the wiring length to these pins should be minimized.

OSC2

V_CC= 5V

V_CC= 3V

500

400

300

500

400

300

max.

typ.

(270)

max.

200

100

200

100

typ.

min.

150

min.

150

(75)

(91)

100

50

R_f(kΩ)

358

HD66710

13. RCOM is the resistance between the power supply pins (V_CC, V1, V4, V5) and each common signal

pin (COM1 to COM33).

RSEG is the resistance between the power supply pins (V_CC, V2, V3, V5) and each segment signal pin

(SEG1 to SEG40).

14. The following graphs show the relationship between operation frequency and current consumption.

V

_CC= 5V

V

_CC= 3V

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

max.

typ.

max.

typ.

typ. (LP mode)

0

100 200 300 400 500

f_OSCor f_cp(kHz)

0

100 200 300 400 500

f_OSCor f_cp(kHz)

15. Applies to the OSC1 pin.

16. Each COM and SEG output voltage is within ±0.15V of the LCD voltage (V_CC, V1, V2, V3, V4, V5)

when there is no load.

17. The TEST pin must be fixed to the ground, and the EXT or V_CCpin must also be connected to the

ground.

18. Booster characteristics test circuits are shown below.

Boosting twice

V_CC

Boosting three times

V_CC

Vci

C1

C2

Rload

I_O

Vci

C1

C2

Rload

I_O

1 µF

+

V5OUT2

1 µF

+

V5OUT3

GND

359

HD66710

19. Reference data

The following graphs show the liquid crystal voltage booster characteristics.

VUP2 = V_CC–V5OUT2

VUP3 = V_CC–V5OUT3

(1) VUP2, VUP3 vs Vci

Boosting twice

Boosting three times

11

10

9

15

14

13

12

11

10

9

typ.

8

7

6

8

7

5

4

6

2.0

3.0

4.0

5.0

2.0

3.0

4.0

5.0

Vci (V)

Test condition: Vci = V_CC, f_cp= 270 kHz

T_a= 25°C, Rload = 25 kΩ

Ta = 25°C, Rload = 25 kΩ

(2) VUP2, VUP3 vs I_o

Boosting twice

9.0

Boosting three times

8.0

8.5

7.5

7.0

typ.

min.

8.0

7.5

7.0

6.5

6.0

6.5

typ.

min.

6.0

5.5

5.0

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

I_o(mA)

Test condition: Vci = V_CC= 4.5V

R_f= 91 kΩ, T_a= 25°C

Test condition: Vci = V_CC= 2.7V

R_f= 75 kΩ, T_a= 25°C

(3) VUP2, VUP3 vs T_a

Boosting twice

Boosting three times

9.0

8.5

8.0

7.5

7.0

8.0

7.5

7.0

6.5

6.0

typ.

min.

–60 –20

0

20

60

100

–60 –20

0

20

60 100

T_a(°C)

Test condition: Vci = V_CC= 4.5V

R_f= 91 kΩ, I_o= 0.25 mA

Test condition: Vci = V_CC= 2.7V

R_f= 75 kΩ, I_o= 0.25 mA

360

HD66710

(4) VUP2, VUP3 vs Capacitance

Boosting twice

9.0

Boosting three times

typ.

min.

8.0

7.5

7.0

6.5

6.0

typ.

min.

8.5

8.0

7.5

7.0

0.5

1.0

1.5

0.5

1.0

1.5

C (µF)

Test condition: Vci = V_CC= 4.5V

R_f= 91 kΩ, I_o= 0.25 mA

Test condition: Vci = V_CC= 2.7V

R_f= 75 kΩ, I_o= 0.25 mA

20. Vci ≤ V_CCmust be maintained.

Load Circuits

AC Characteristics Test Load Circuits

Data bus: DB0–DB7

Segment extension signals: CL1, CL2, D, M

Test

point

Test

point

30 pF

50 pF

361

HD66710

Timing Characteristics

VIH1

VIL1

VIH1

VIL1

RS

R/W

E

t_AS

t_AH

VIL1

PW_EH

t_AH

t_Ef

VIH1

VIL1

VIH1

VIL1

t_Er

t_DSW

t_H

VIH1

VIL1

VIH1

VIL1

Valid data

t_cycE

DB0 to DB7

Figure 30 Write Operation

VIH1

VIL1

VIH1

VIL1

RS

R/W

E

t_AS

t_AH

VIH1

PW_EH

t_AH

t_Ef

VIH1

VIL1

VIH1

VIL1

t_Er

t_DDR

t_DHR

VOH1

*VOL1

Valid data

t_cycE

DB0 to DB7

*

VOL1

Note: VOL1 is assumed to be 0.8V at 2 MHz operation.

Figure 31 Read Operation

362

HD66710

t_ct

VOH2

t_CWH

CL1

CL2

D

VOL2

t_CWH

VOH2

VOL2

t_CSU

t_CWL

t_ct

VOH2

VOL2

t_DH

t_SU

M

VOL2

t_DM

Figure 32 Interface Timing with External Driver

*2

2.7V/4.5V

V_CC

0.2V

t_rcc

t_OFF*1

t_OFF≥1 ms

0.1 ms ≤ t_rcc≤ 10 ms

Notes: 1. t_OFFcompensates for the power oscillation period caused by momentary power

supply oscillations.

2. Specified at 4.5V for standard voltage operation, and at 2.7V for low voltage operation.

3. If the above electrical conditions are not satisfied, the internal reset circuit will not

operate normally. In this case, the LSI must be initialized by software. (Refer to the

Initializing by Instruction section.)

Figure 33 Power Supply Sequemce

363


型号：	HD66710BXXFS
厂家：	HITACHI SEMICONDUCTOR
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HD66710BXXFS [HITACHI]

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