HM5116405SI-7 [HITACHI]
EDO DRAM, 4MX4, 70ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-26/24;
| 型号： | HM5116405SI-7 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | EDO DRAM, 4MX4, 70ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-26/24 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总30页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM5116405I Series
4,194,304-word × 4-bit Dynamic RAM
ADE-203-757A (Z)
Rev. 1.0
Mar. 17, 1997
Description
The Hitachi HM5116405I Series is CMOS dynamic RAM organized 4,194,304-word × 4-bit. It employs
the most advanced CMOS technology for high performance and low power. The HM5116405I Series
offers Extended Data Out (EDO) Page Mode as a high speed access mode. It is packaged in 26-pin plastic
SOJ.
Features
•
•
•
Single 5 V (±10%)
Access time: 60 ns/70 ns (max)
Power dissipation
Active mode : 440 mW/385 mW (max)
Standby mode : 11 mW (max)
:
0.83 mW (max) (L-version)
•
•
EDO page mode capability
Refresh cycles
4096 refresh cycles : 64 ms
: 128 ms (L-version)
•
3 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
•
•
Battery backup operation (L-version)
Test function
16-bit parallel test mode
Temperatre range: –40 to +85˚C
•
HM5116405I Series
Ordering Information
Type No.
Access time
Package
HM5116405SI-6
HM5116405SI-7
60 ns
70 ns
300-mil 26-pin plastic SOJ
(CP-26/24DB)
HM5116405LSI-6
HM5116405LSI -7
60 ns
70 ns
2
HM5116405I Series
Pin Arrangement
HM5116405SI/LSI Series
VCC
I/O1
I/O2
WE
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
RAS
A11
A9
A10
A0
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
9
A1
10
11
12
13
A2
A3
VCC
(Top view)
Pin Description
Pin name
Function
Address input
A0 to A11
— Row/Refresh address
— Column address
A0 to A11
A0 to A9
I/O1 to I/O4
RAS
CAS
WE
Data input/Data output
Row address strobe
Column address strobe
Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
3
HM5116405I Series
Block Diagram
RAS
CAS
WE
OE
Timing and control
A0
Column decoder
4M array
A1
to
Column
address
buffers
•
•
•
A9
4M array
4M array
4M array
I/O1
to
I/O4
•
•
•
I/O buffers
Row
address
buffers
A10
A11
4
HM5116405I Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +7.0
–1.0 to +7.0
50
VCC
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
–40 to +85
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = –40 to +85˚C)
Parameter
Symbol
VCC
Min
4.5
Typ
5.0
—
Max
5.5
6.5
0.8
Unit
V
Note
Supply voltage
Input high voltage
Input low voltage
1
1
1
VIH
2.4
V
VIL
–1.0
—
V
Note: 1. All voltage referred to VSS.
DC Characteristics (Ta = –40 to +85˚C, VCC = 5 V ± 10%, VSS = 0 V)
HM5116405I
–6
Max
–7
Max
Parameter
Symbol Min
Min
—
Unit
mA
mA
Test conditions
1
2
,
Operating current*
Standby current
*
ICC1
ICC2
—
—
80
2
70
2
tRC = min
—
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
—
1
—
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
150
150
µA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
80
5
—
—
70
5
mA
mA
tRC = min
RAS = VIH
CAS = VIL
Dout = enable
CAS-before-RAS refresh
current
ICC6
—
80
—
70
mA
tRC = min
5
HM5116405I Series
DC Characteristics (cont.)
HM5116405I
–6
Max
70
–7
Max
Parameter
EDO page mode current*1, *3 ICC7
Symbol Min
Min
—
Unit
mA
µA
Test conditions
—
—
65
tHPC = min
Battery backup current
ICC10
350
—
350
CMOS interface
Dout = High-Z, CBR
refresh: tRC = 31.3 µs
t
RAS ≤ 0.3 µs
Input leakage current
Output leakage current
ILI
–10
–10
10
10
–10
–10
10
10
µA
µA
0 V ≤ Vin ≤ 7 V
ILO
0 V ≤ Vin ≤ 7 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
Capacitance (Ta = 25˚C, VCC = 5 V ±10%)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
5
7
7
1
CI2
—
pF
1
Output capacitance (Data-in, Data-out) CI/O
—
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
6
HM5116405I Series
AC Characteristics (Ta = –40 to +85˚C, VCC = 5 V ±10%, VSS = 0 V) *1, *2, *18
Test Conditions
•
•
•
•
•
Input rise and fall time: 2 ns
Input levels: VIL = 0 V, VIH = 3 V
Input timing reference levels: 0.8 V, 2.4 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5116405I
–6
Max
–7
Max
Parameter
Symbol
tRC
Min
104
40
10
60
10
0
Min
124
50
Unit
ns
Notes
Random read or write cycle time
RAS precharge time
—
—
—
—
—
—
tRP
ns
CAS precharge time
tCP
13
ns
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
10000 70
10000 13
10000 ns
10000 ns
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
—
—
—
—
45
30
—
—
—
—
—
—
50
0
—
—
—
—
52
35
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
0
10
0
10
14
12
13
40
5
13
14
12
13
45
5
3
4
CAS hold time
CAS to RAS precharge time
OE to Din delay time
OE delay time from Din
CAS delay time from Din
Transition time (rise and fall)
15
0
18
0
5
6
6
7
0
0
2
2
7
HM5116405I Series
Read Cycle
HM5116405I
–6
Max
60
–7
Max
Parameter
Symbol
tRAC
Min
—
Min
—
Unit
ns
Notes
Access time from RAS
Access time from CAS
70
18
8, 9, 20
tCAC
—
15
—
ns
9, 10, 17,
20
Access time from address
tAA
—
30
—
35
ns
9, 11, 17,
20
Access time from OE
tOEA
tRCS
tRCH
—
0
15
—
—
—
—
—
—
—
—
—
15
15
—
—
15
15
—
—
—
—
0
18
—
—
—
—
—
—
—
—
—
15
15
—
—
15
15
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9, 20
Read command setup time
Read command hold time to CAS
0
0
12
Read command hold time from RAS tRCHR
60
0
70
0
Read command hold time to RAS
Column address to RAS lead time
Column address to CAS lead time
CAS to output in low-Z
tRRH
tRAL
tCAL
tCLZ
tOH
12
30
18
0
35
23
0
Output data hold time
3
3
22
Output data hold time from OE
Output buffer turn-off time
Output buffer turn-off to OE
CAS to Din delay time
tOHO
tOFF
tOEZ
tCDD
tOHR
tOFR
tWEZ
tWED
tRDD
tRNCD
3
3
—
—
15
3
—
—
18
3
13, 22
13
5
Output data hold time from RAS
Output buffer turn-off to RAS
Output buffer turn-off to WE
WE to Din delay time
22
—
—
15
15
60
—
—
18
18
70
22
RAS to Din delay time
RAS next CAS delay time
8
HM5116405I Series
Write Cycle
HM5116405I
–6
Max
–7
Max
Parameter
Symbol
tWCS
tWCH
tWP
Min
0
Min
0
Unit
ns
Notes
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
—
—
—
—
—
—
—
—
14
10
10
10
10
0
—
—
—
—
—
—
13
10
13
13
0
ns
ns
tRWL
tCWL
tDS
ns
ns
ns
15
15
Data-in hold time
tDH
10
13
ns
Read-Modify-Write Cycle
HM5116405I
–6
–7
Parameter
Symbol
tRWC
Min
135
79
Max
—
Min
161
92
Max
—
Unit
ns
Notes
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
OE hold time from WE
tRWD
—
—
ns
14
14
14
tCWD
34
—
40
—
ns
tAWD
49
—
57
—
ns
tOEH
15
—
18
—
ns
Refresh Cycle
HM5116405I
–6
Max
–7
Parameter
Symbol
tCSR
Min
5
Min
5
Max
—
Unit
ns
Notes
CAS setup time (CBR refresh cycle)
CAS hold time (CBR refresh cycle)
WE setup time (CBR refresh cycle)
WE hold time (CBR refresh cycle)
RAS precharge to CAS hold time
—
tCHR
10
0
—
—
—
—
10
0
—
ns
tWRP
—
ns
tWRH
10
5
10
5
—
ns
tRPC
—
ns
9
HM5116405I Series
EDO Page Mode Cycle
HM5116405I
–6
Max
–7
Max
Parameter
Symbol
tHPC
Min
25
—
—
35
3
Min
Unit
Notes
21
EDO page mode cycle time
EDO page mode RAS pulse width
Access time from CAS precharge
RAS hold time from CAS precharge
Output data hold time from CAS low
CAS hold time referred OE
CAS to OE setup time
—
30
—
ns
tRASP
tCPA
tCPRH
tDOH
100000 —
100000 ns
16
35
—
—
—
—
—
—
40
3
40
—
—
—
—
—
ns
ns
ns
ns
ns
ns
9, 17, 20
9, 17
tCOL
10
5
13
5
tCOP
Read command hold time from CAS tRCHC
precharge
35
40
EDO Page Mode Read-Modify-Write Cycle
HM5116405I
–6
Max
–7
Max
Parameter
Symbol
Min
Min
Unit
Notes
EDO page mode read- modify-write
cycle time
tHPRWC
68
—
79
ns
WE delay time from CAS precharge
tCPW
54
—
62
ns
14
Test Mode Cycle *19
HM5116405I
-6
-7
Parameter
Symbol
tWTS
Min
0
Max
—
Min
0
Max
—
Unit
ns
Notes
Test mode WE setup time
Test mode WE hold time
tWTH
10
—
10
—
ns
Refresh
Parameter
Symbol
tREF
tREF
Max
Unit
ms
Notes
Refresh period
64
4096 cycles
4096 cycles
Refresh period (L-version)
128
ms
10
HM5116405I Series
Notes: 1. AC measurements assume tT = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If
the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are
required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
≥
15. These parameters are referred to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA
.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to device.
19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M
×4 are don’t care during test mode. Test mode is set by performing a WE-and-CAS-before-RAS
(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1
to I/O4) and read out from each I/O.
If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read
cycle, then the device has passed. If they are not equal, data output pin is a low state, then the
device has failed.
Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
To get out of test mode and enter a normal operation mode, perform either a regular CAS-
before-RAS refresh cycle or RAS-only refresh cycle.
20. In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
11
HM5116405I Series
21. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO
page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater
than the specified tHPC (min) value. The value of CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
Data output turns off and becomes high impedance from later risting edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF
.
22. Data output turns off and becomes high impedance from later rising edge of RAS and CAS .
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH and between tOFR and tOFF
.
23. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ V ≤ VIL (max))
IN
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
12
HM5116405I Series
Timing Waveforms*23
Read Cycle
13
HM5116405I Series
t
t
RC
t
RAS
RP
RAS
t
t
CSH
CRP
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
RAD
RAL
CAL
t
t
t
CAH
ASR
Row
ASC
t
RAH
Address
Column
t
RRH
t
RCHR
t
t
RCH
CDD
t
RCS
WE
t
WED
t
DZC
t
RDD
High-Z
Din
t
t
t
OED
DZO
OEA
OE
t
OEZ
t
OHO
t
CAC
t
OFF
t
AA
t
OH
t
t
RAC
OFR
t
t
CLZ
OHR
t
WEZ
Dout
Dout
14
HM5116405I Series
Early Write Cycle
t
t
RC
t
RAS
RP
RAS
CAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
WCH
WCS
WE
t
t
DH
DS
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
15
HM5116405I Series
Delayed Write Cycle*18
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
CAS
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
t
CWL
RWL
WP
t
RCS
WE
t
t
t
DH
DZC
DS
High-Z
Din
Din
t
t
OEH
DZO
t
OED
OE
t
OEZ
t
CLZ
High-Z
Dout
Invalid Dout
16
HM5116405I Series
Read-Modify-Write Cycle*18
t
t
RWC
RAS
t
RP
RAS
t
T
t
t
t
CRP
RCD
CAS
CAS
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
Address
Row
Column
t
t
t
t
t
CWD
CWL
t
RCS
AWD
RWD
RWL
t
WP
WE
Din
OE
t
t
DH
DZC
t
DS
High-Z
Din
t
OED
t
OEH
t
DZO
t
OEA
t
CAC
t
t
OEZ
t
t
AA
t
RAC
OHO
High-Z
Dout
Dout
CLZ
17
HM5116405I Series
RAS-Only Refresh Cycle
t
RC
t
t
RAS
RP
RAS
t
T
t
t
t
CRP
CRP
RPC
CAS
t
t
RAH
ASR
Address
Row
t
OFR
t
OFF
High-Z
Dout
18
HM5116405I Series
CAS-Before-RAS Refresh Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
t
t
t
t
CRP
t
CSR
CHR
RPC
RPC
t
T
CAS
t
CP
t
t
t
WRH
CP
WRP
WE
Address
t
OFR
t
OFF
High-Z
Dout
19
HM5116405I Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
CAS
t
t
RAL
RAD
t
t
t
t
CAH
RAH
ASR
ASC
Address
Row
Column
t
t
t
RRH
t
WRH
t
WRP
RCH
t
RRH
t
WRH
WRP
t
t
RCS
DZC
WE
t
WED
t
t
CDD
RDD
High-Z
Din
t
t
OED
DZO
t
OEA
OE
t
OEZ
t
CAC
t
WEZ
OHO
t
AA
t
t
t
t
RAC
OFF
OH
t
CLZ
Dout
Dout
t
OFR
t
OHR
20
HM5116405I Series
EDO Page Mode Read Cycle
t
RP
t
RNCD
t
HPC
t
RASP
RAS
CAS
t
t
t
t
CRP
HPC
t
HPC
t
CPRH
CP
t
t
T
CSH
t
CP
t
t
CP
t
RSH
t
t
CAS
CAS
CAS
CAS
t
RCHC
t
RCHR
tRCS
t
RRH
RCH
tRCS
tRCH
t
WE
t
RAL
t
WED
t
t
tCAH
tCAH
tASC
tASC
tCAH
tRAH
CAH
ASC
tASC
tASR
Address
Row
Column 1
Column 2
t
Column 3
t
CAL
Column 4
t
t
CAL
CAL
CAL
t
t
RDD
CDD
t
DZC
High-Z
Din
t
t
t
COP
COL
DZO
t
OED
OE
t
t
OFR
CPA
t
CPA
t
OEA
t
t
t
CPA
AA
t
OHR
OEZ
AA
t
t
OEZ
AA
t
t
CAC
t
CAC
t
OEZ
t
t
t
OHO
CAC
AA
t
t
t
t
t
CAC
WEZ
OHO
OFF
OH
tOEA
t
t
RAC
OEA
t
DOH
t
OHO
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
21
HM5116405I Series
EDO Page Mode Early Write Cycle
t
t
RASP
RP
RAS
t
T
t
t
t
RSH
CSH
HPC
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
CAS
t
t
CAH
t
t
t
t
t
t
ASC
ASR RAH
ASC CAH
ASC CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
WCH
WCH
WCS
WCS
WCS
WCH
WE
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
22
HM5116405I Series
EDO Page Mode Delayed Write Cycle*18
t
RASP
t
RP
RAS
t
t
t
t
CP
CRP
T
CP
t
t
t
t
CSH
HPC
RSH
CAS
t
t
t
CAS
RCD
CAS
CAS
t
RAD
t
t
t
t
ASR
ASC
t
ASC
t
ASC
t
t
RAH
CAH
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
CWL
CWL
t
CWL
t
RWL
t
t
RCS
RCS
RCS
WE
t
t
t
WP
WP
WP
t
t
t
t
t
t
t
DZC DS
DZC DS
DZC DS
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
DZO
DZO
DZO
OED
t
t
OED
OED
t
t
t
OEH
OEH
OEH
OE
t
t
t
CLZ
CLZ
CLZ
t
t
t
OEZ
OEZ
OEZ
High-Z
Dout
Invalid Dout
Invalid Dout
Invalid Dout
23
HM5116405I Series
EDO Page Mode Read-Modify-Write Cycle*18
t
RASP
t
RP
RAS
t
t
T
HPRWC
t
t
t
t
RSH
CAS
t
CRP
CP
CP
t
t
t
CAS
RCD
CAS
CAS
t
RAD
t
t
t
t
ASC
t
CAH
ASR
ASC
RAH
ASC
t
t
t
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
t
t
t
CWL
RWD
AWD
CWL
CPW
AWD
CWL
CPW
AWD
t
RWL
t
t
t
t
t
CWD
CWD
RCS
CWD
RCS
WE
t
t
t
t
t
WP
t
DS
RCS
DZO
WP
DS
WP
t
t
t
DS
t
DZC
DZC
DZC
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
OED
OED
OED
t
t
t
DZO
DZO
t
t
t
OEH
OEH
OEH
OE
t
t
t
OHO
OHO
OHO
t
t
t
t
t
t
OEA
CAC
OEA
CAC
OEA
CAC
t
t
t
AA
AA
AA
t
t
CPA
CPA
t
t
RAC
t
t
t
OEZ
t
t
OEZ
OEZ
CLZ
CLZ
CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
24
HM5116405I Series
EDO Page Mode Mix Cycle (1)
t
RP
t
RASP
RAS
t
CRP
t
T
t
t
t
CP
CP
CP
t
t
t
t
CAS
CAS
CAS
CAS
CAS
t
CSH
t
RSH
tRCD
t
t
tRCS
RRH
RCH
tWCS
tRCS
tWCH
t
t
WE
CPW
AWD
tWP
t
RAL
tCAH
tASC
tRAH
tASC
t
tASC tCAH
tCAH
CAH
tASC
tASR
Address
Row
Column 1
t
Column 2
t
Column 3
t
Column 4
CAL
CAL
CAL
t
t
RDD
CAL
t
t
CDD
DH
t
t
DH
Din 1
DS
t
DS
High-Z
Din
Din 3
t
OED
t
WED
OE
t
t
OFR
WEZ
t
CPA
CPA
t
t
t
t
CPA
t
AA
t
AA
t
OEZ
OEZ
t
t
t
OEA
AA
CAC
OHO
t
CAC
tOHO
t
t
OEA
CAC
t
t
OFF
OH
t
DOH
Dout
Dout 2
Dout 3
Dout 4
25
HM5116405I Series
EDO Page Mode Mix Cycle (2)
t
RNCD
t
RP
t
RASP
RAS
CAS
t
CRP
t
t
T
t
CSH
t
CP
CP
t
t
t
t
CAS
CAS
CAS
CAS
tRCD
tRCS
tRCHR
t
RSH
t
RCS
t
RRH
RCH
tWCS
tWCH
t
RCS
tRCH
t
tWP
t
WE
CPW
t
RAL
tASC
tRAH
t
CAH
tASC
tASC tCAH
tCAH
tCAH
tASC
tASR
Address
Row
Column 1
Column 2
t
Column 3
t
Column 4
t
t
CAL
CAL
CAL
CAL
t
DS
t
t
RDD
CDD
t
t
t
DH
DS
DH
High-Z
Din
Din 2
Din 3
t
t
OED
t
COP
OED
t
WED
t
COL
OE
t
OFR
WEZ
t
t
OEA
t
t
t
t
CPA
t
AA
t
CPA
t
OEA
AA
OEZ
t
t
AA
OEZ
t
CAC
t
t
CAC
OEZ
OHO
t
t
CAC
RAC
t
OEA
t
t
t
OFF
OH
t
OHO
OHO
Dout
Dout 1
Dout 4
Dout 3
26
HM5116405I Series
Test Mode Cycle *19
*,**
Reset Cycle
Set Cycle**
Test Mode Cycle
Normal Mode
RAS
CAS
WE
*
CBR or RAS-only refresh
** Address, Din, OE: H or L
27
HM5116405I Series
Test Mode Set Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
t
t
t
t
t
CRP
RPC
CSR
CHR
RPC
t
T
CAS
WE
t
t
t
t
CP
CP
WTS
WTH
Address
t
OFR
t
OFF
High-Z
Dout
28
HM5116405I Series
Package Dimensions
HM5116405SI/LSI Series (CP-26/24DB)
Unit: mm
16.90
17.27 Max
26
1
21 19
14
13
6
8
0.74
1.30 Max
1.27
0.10
6.71 ± 0.25
0.43 ± 0.10
0.41 ± 0.08
2.54
Hitachi Code
JEDEC Code
EIAJ Code
Weight
CP-26/24DB
MO-077-AA
SC-632-A
0.8 g
29
HM5116405I Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Revision Record
Rev. Date
1.0 Mar. 17, 1997
Contents of Modification
Drawn by Approved by
Initial issue
30
相关型号：
©2020 ICPDF网 联系我们和版权申明