HM5118165 [HITACHI]
16M EDO DRAM (1-Mword x 16-bit) 1 k Refresh; 16M EDO DRAM ( 1 - Mword ×16位), 1千刷新型号: | HM5118165 |
厂家: | HITACHI SEMICONDUCTOR |
描述: | 16M EDO DRAM (1-Mword x 16-bit) 1 k Refresh |
文件: | 总34页 (文件大小:251K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HM5118165 Series
16 M EDO DRAM (1-Mword × 16-bit)
1 k Refresh
ADE-203-636D (Z)
Rev. 4.0
Nov. 1997
Description
The Hitachi HM5118165 is a CMOS dynamic RAM organized as 1,048,576-word × 16-bit. It employs the
most advanced 0.5 µm CMOS technology for high performance and low power. The HM5118165 offers
Extended Data Out (EDO) Page Mode as a high speed access mode. It is packaged in 42-pin plastic SOJ
and 50-pin plastic TSOP II.
Features
•
•
•
Single 5 V (±10%)
Access time : 50 ns/60 ns/70 ns (max)
Power dissipation
Active mode : 1045 mW/935 mW/825 mW (max)
Standby mode : 11 mW (max)
: 0.83 mW (max) (L-version)
EDO page mode capability
Refresh cycles
•
•
1024 refresh cycles : 16 ms
: 128 ms (L-version)
•
4 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
Self refresh (L-version)
•
•
2CAS-byte control
Battery backup operation (L-version)
HM5118165 Series
Ordering Information
Type No.
Access time
Package
HM5118165J-5
HM5118165J-6
HM5118165J-7
50 ns
60 ns
70 ns
400-mil 42-pin plastic SOJ (CP-42D)
HM5118165LJ-5
HM5118165LJ-6
HM5118165LJ-7
50 ns
60 ns
70 ns
HM5118165TT-5
HM5118165TT-6
HM5118165TT-7
50 ns
60 ns
70 ns
400-mil 50-pin plastic TSOP II (TTP-50/44DC)
HM5118165LTT-5
HM5118165LTT-6
HM5118165LTT-7
50 ns
60 ns
70 ns
2
HM5118165 Series
Pin Arrangement
HM5118165J/LJ Series
HM5118165TT/LTT Series
V
1
50
49
48
47
46
45
44
43
42
41
40
V
SS
CC
V
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
1
SS
CC
I/O0
I/O1
I/O2
I/O3
2
I/O15
I/O14
I/O13
I/O12
I/O15
I/O14
I/O13
I/O12
I/O0
I/O1
I/O2
I/O3
2
3
3
4
5
4
V
6
V
5
CC
SS
I/O4
I/O5
I/O6
I/O7
NC
7
I/O11
I/O10
I/O9
I/O8
NC
V
V
6
SS
CC
8
I/O11
I/O10
I/O9
I/O8
NC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
7
9
8
10
11
9
10
11
12
13
14
15
16
17
18
19
20
21
LCAS
UCAS
OE
NC
NC
WE
RAS
NC
NC
A0
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
LCAS
UCAS
OE
A9
A9
A8
A8
A7
A7
A6
A1
A1
A6
A5
A2
A2
A5
A4
A3
A3
A4
V
V
V
V
CC
CC
SS
SS
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
— Row/Refresh address A0 to A9
A0 to A9
— Column address
Data input/Data output
Row address strobe
A0 to A9
I/O0 to I/O15
RAS
UCAS, LCAS Column address strobe
WE
OE
VCC
VSS
NC
Read/Write enable
Output enable
Power supply
Ground
No connection
3
HM5118165 Series
Block Diagram
RAS UCAS LCAS
WE
OE
Timing and control
A0
Column decoder
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
A1
to
Column
address
buffers
•
•
•
A9
I/O0
to
I/O15
I/O buffers
•
•
•
Row
address
buffers
4
HM5118165 Series
Truth Table
RAS
LCAS
UCAS
WE
D
OE
Output
Open
Valid
Operation
H
D
L
D
H
L
D
Standby
Lower byte Read cycle
Upper byte
L
H
L
L
H
L
H
L
Valid
L
L
H
L
Valid
Word
L
L
H
L
L*2
D
Open
Open
Open
Lower byte Early write cycle
Upper byte
L
H
L
L*2
L*2
L*2
L*2
L*2
H to L
H to L
H to L
D
D
L
L
D
Word
L
L
H
L
H
Undefined Lower byte Delayed write cycle
Undefined Upper byte
L
H
L
H
L
L
H
Undefined Word
L
L
H
L
L to H
L to H
L to H
D
Valid
Valid
Valid
Open
Open
Open
Open
Open
Lower byte Read-modify-write cycle
L
H
L
Upper byte
Word
L
L
L
H
H
L
H
L
Word
Word
Word
Word
RAS-only refresh cycle
H to L
H to L
H to L
L
D
D
CAS-before-RAS refresh cycle or
Self refresh cycle (L-version)
H
L
D
D
L
D
D
L
L
H
H
Read cycle (Output disabled)
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. tWCS ≥ 0 ns Early write cycle
tWCS < 0 ns Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.)
However write OPERATION and output High-Z control are done independently by each UCAS,
LCAS.
ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
5
HM5118165 Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +7.0
–1.0 to +7.0
50
VCC
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
4.5
Typ
5.0
—
Max
5.5
6.5
0.8
Unit
Notes
Supply voltage
V
V
V
1, 2
1
Input high voltage
Input low voltage
VIH
2.4
VIL
–1.0
—
1
Notes: 1. All voltage referred to VSS
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS
pins must be on the same level.
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM5118165
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Test conditions
Operating current*1, *2
ICC1
ICC2
—
—
200 —
170 — 150 mA
tRC = min
Standby current
2
—
2
—
2
mA
TTL interface
RAS, UCAS, LCAS = VIH
Dout = High-Z
—
—
1
—
1
—
1
mA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
150 —
150 — 150 µA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
6
HM5118165 Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont.)
HM5118165
-5 -6
Symbol Min Max Min Max Min Max Unit
-7
Parameter
Test conditions
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
200 —
170 — 150 mA
mA
tRC = min
5
—
5
—
5
RAS = VIH,
UCAS, LCAS = VIL
Dout = enable
CAS-before-RAS refresh
current
ICC6
—
190 —
170 — 150 mA
tRC = min
EDO page mode current*1, *3 ICC7
—
—
185 —
500 —
165 — 145 mA
tHPC = min
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10
500 — 500 µA
CMOS interface
Dout = High-Z
CBR refresh: tRC = 125 µs
t
RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
300 —
300 — 300 µA
CMOS interface
RAS, UCAS, LCAS ≤ 0.2
V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–10 10 –10 10 –10 10 µA
–10 10 –10 10 –10 10 µA
0 V ≤ Vin ≤ 7 V
ILO
0 V ≤ Vout ≤ 7 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4 VCC 2.4 VCC 2.4 VCC
0.4 0.4 0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
0
0
0
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while UCAS and LCAS = VIH.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
Capacitance (Ta = 25°C, VCC = 5 V ± 10%)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
5
7
7
1
CI2
—
pF
1
CI/O
—
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS, UCAS and LCAS = VIH to disable Dout.
7
HM5118165 Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *2, *18, *19, *20
Test Conditions
•
•
•
•
•
Input rise and fall time: 2 ns
Input levels: 0 V, 3.0 V
Input timing reference levels: 0.8 V, 2.4 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5118165
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit
Notes
Random read or write cycle time
RAS precharge time
CAS precharge time
RAS pulse width
tRC
84
30
7
—
—
—
104
40
—
—
—
124
50
—
—
—
ns
ns
ns
tRP
tCP
10
13
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
50
7
10000 60
10000 10
10000 70
10000 13
10000 ns
10000 ns
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
0
—
—
—
—
37
25
—
—
—
—
—
—
50
0
—
—
—
—
45
30
—
—
—
—
—
—
50
0
—
—
—
—
52
35
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
10
0
10
0
0
21
21
3
7
10
14
12
13
40
5
13
14
12
13
45
5
11
9
RAS to column address delay time tRAD
4
RAS hold time
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
10
35
5
CAS hold time
23
22
5
CAS to RAS precharge time
OE to Din delay time
OE delay time from Din
CAS delay time from Din
Transition time (rise and fall)
13
0
15
0
18
0
6
0
0
0
6
2
2
2
7
8
HM5118165 Series
Read Cycle
HM5118165
-5
-6
-7
Parameter
Symbol Min
Max Min
Max Min
Max Unit
Notes
8, 9
Access time from RAS
Access time from CAS
Access time from address
Access time from OE
tRAC
tCAC
tAA
—
—
—
—
0
50
13
25
13
—
—
—
—
—
—
—
0
60
15
30
15
—
—
—
—
—
—
—
0
70
18
35
18
—
—
—
ns
ns
ns
ns
ns
ns
ns
9, 10, 17
9, 11, 17
9
tOEA
tRCS
tRCH
tRCHR
Read command setup time
Read command hold time to CAS
21
0
0
0
12, 22
Read command hold time from
50
60
70
RAS
Read command hold time to RAS
tRRH
0
—
—
—
—
—
—
13
13
—
—
13
13
—
—
—
0
—
—
—
—
—
—
15
15
—
—
15
15
—
—
—
0
—
—
—
—
—
—
15
15
—
—
15
15
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
27
Column address to RAS lead time tRAL
Column address to CAS lead time tCAL
25
15
0
30
18
0
35
23
0
CAS to output in low-Z
tCLZ
Output data hold time
tOH
3
3
3
Output data hold time from OE
Output buffer turn-off time
Output buffer turn-off to OE
CAS to Din delay time
tOHO
tOFF
tOEZ
tCDD
tOHR
tOFR
tWEZ
tWED
tRDD
tRNCD
3
3
3
—
—
13
3
—
—
15
3
—
—
18
3
13, 27
13
5
Output data hold time from RAS
Output buffer turn-off to RAS
Output buffer turn-off to WE
WE to Din delay time
27
—
—
13
13
50
—
—
15
15
60
—
—
18
18
70
27
RAS to Din delay time
RAS next CAS delay time
9
HM5118165 Series
Write Cycle
HM5118165
-5
-6
-7
Parameter
Symbol Min
Max Min
Max Min
Max Unit
Notes
14, 21
21
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
tWCS
tWCH
tWP
0
7
7
7
7
0
7
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
10
10
10
10
0
13
10
13
13
0
tRWL
tCWL
tDS
23
15, 23
15, 23
Data-in hold time
tDH
10
13
Read-Modify-Write Cycle
-5
-6
-7
Parameter
Symbol Min
Max Min
Max Min
Max Unit
Notes
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
tRWC
tRWD
tCWD
111
67
30
42
13
—
—
—
—
—
135
79
34
49
15
—
—
—
—
—
161
92
40
57
18
—
—
—
—
—
ns
ns
ns
ns
ns
14
14
14
Column address to WE delay time tAWD
OE hold time from WE
tOEH
Refresh Cycle
HM5118165
-5
-6
-7
Parameter
Symbol Min
Max Min
Max Min
Max Unit
Notes
21
CAS setup time (CBR refresh cycle) tCSR
CAS hold time (CBR refresh cycle) tCHR
5
7
5
—
—
—
5
—
—
—
5
—
—
—
ns
ns
ns
10
5
10
5
22
RAS precharge to CAS hold time
tRPC
21
10
HM5118165 Series
EDO Page Mode Cycle
HM5118165
-5
-6
-7
Min Max
30
Parameter
Symbol Min Max
Min Max
Unit
Notes
25
EDO page mode cycle time
tHPC
20
—
—
28
3
—
25
100000 —
—
—
ns
EDO page mode RAS pulse width tRASP
Access time from CAS precharge tCPA
100000 — 100000 ns
16
28
—
—
—
—
—
—
35
3
35
—
—
—
—
—
—
40
3
40
—
—
—
—
—
ns
ns
ns
ns
ns
ns
9, 17, 22
RAS hold time from CAS precharge tCPRH
Output data hold time from CAS low tDOH
9
CAS hold time referred OE
CAS to OE setup time
tCOL
7
10
5
13
5
tCOP
tRCHC
5
Read command hold time from
28
35
40
CAS precharge
EDO Page Mode Read-Modify-Write Cycle
HM5118165
-5
-6
-7
Parameter
Symbol Min
Max Min
Max Min
Max Unit
Notes
EDO page mode read-modify-write tHPRWC
cycle time
57
—
68
—
79
—
ns
WE delay time from CAS precharge tCPW
45
—
54
—
62
—
ns
14, 22
Refresh
Parameter
Symbol
tREF
Max
16
Unit
ms
Note
Refresh period
1024 cycles
1024 cycles
Refresh period (L-version)
tREF
128
ms
11
HM5118165 Series
Self Refresh Mode (L-version)
HM5118165L
-5
-6
-7
Parameter
Symbol Min
Max Min
Max Min
Max Unit
Notes
RAS pulse width (self refresh)
tRASS
100
—
100
—
100
—
µs
28, 29, 30,
31
RAS precharge time (self refresh) tRPS
CAS hold time (self refresh) tCHS
90
—
—
110
–50
—
—
130
–50
—
—
ns
ns
–50
Notes: 1. AC measurements assume tT = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD ≥ tRAD (max) + tAA (max) – tCAC (max), then access time is controlled
exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
≥
15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE
leading edge in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA
.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.
UCAS and LCAS cannot be staggered within the same write/read cycles.
12
HM5118165 Series
20 All the VCC and VSS pins shall be supplied with the same voltages.
21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS.
22. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the later rising edge of UCAS or LCAS.
23. tCWL, tDH, tDS and tCSH should be satisfied by both UCAS and LCAS.
24. tCP is determined by the time that both UCAS and LCAS are high.
25. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO
page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater
than the specified tHPC (min) value. The value of CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
26. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF
.
28. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If tRASS ≥ 100 µs, then RAS
precharge time should use tRPS instead of tRP.
29. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering
into self refresh mode.
30. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles
of distributed CBR refresh with 15.6 µs interval should be executed within 16 ms immediately
after exiting from and before entering into the self refresh mode.
31. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
32. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ V ≤ VIL (max))
IN
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
13
HM5118165 Series
Notes concerning 2CAS control
Please do not separate the UCAS/LCAS operation timing intentionally. However skew between
UCAS/LCAS are allowed under the following conditions.
1. Each of the UCAS/LCAS should satisfy the timing specifications individually.
2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS
Delayed write
UCAS
Early write
LCAS
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is
satisfied, EDO page mode can be performed.
RAS
UCAS
LCAS
t
UL
4. Byte control operation by remaining UCAS or LCAS high is guaranteed.
14
HM5118165 Series
Timing Waveforms*32
Read Cycle
t
t
RC
t
RAS
RP
RAS
t
t
CSH
CRP
t
t
t
RCD
RSH
CAS
t
T
UCAS
LCAS
t
t
t
RAD
RAL
CAL
t
t
t
CAH
ASR
Row
ASC
t
RAH
Address
Column
t
RRH
t
RCHR
t
t
RCH
CDD
t
RCS
WE
t
WED
t
DZC
t
RDD
High-Z
Din
t
t
t
OED
DZO
OEA
OE
t
OEZ
t
OHO
t
CAC
t
OFF
t
AA
t
OH
t
t
RAC
OFR
t
t
CLZ
OHR
t
WEZ
Dout
Dout
15
HM5118165 Series
Early Write Cycle
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
UCAS
LCAS
tASR tRAH
tASC
tCAH
Row
Column
Address
tWCS
tWCH
WE
tDS
tDH
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
16
HM5118165 Series
Delayed Write Cycle*18
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
UCAS
LCAS
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
t
CWL
RWL
WP
t
RCS
WE
t
t
t
DH
DZC
DS
High-Z
Din
Din
t
t
OEH
DZO
t
OED
OE
t
OEZ
t
CLZ
High-Z
Dout
Invalid Dout
17
HM5118165 Series
Read-Modify-Write Cycle*18
t
t
RWC
RAS
t
RP
RAS
t
T
t
t
t
CRP
RCD
CAS
UCAS
LCAS
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
Address
Row
Column
t
t
t
t
t
CWD
CWL
t
RCS
AWD
RWD
RWL
t
WP
WE
Din
OE
t
t
DH
DZC
t
DS
High-Z
Din
t
OED
t
OEH
t
DZO
t
OEA
t
CAC
t
t
OEZ
t
t
AA
t
RAC
OHO
High-Z
Dout
Dout
CLZ
18
HM5118165 Series
RAS-Only Refresh Cycle
t
RC
t
t
RAS
RP
RAS
t
T
t
t
t
CRP
CRP
RPC
UCAS
LCAS
t
t
RAH
ASR
Address
Row
t
OFR
t
OFF
High-Z
Dout
19
HM5118165 Series
CAS-Before-RAS Refresh Cycle
t
t
RC
RC
t
t
t
t
t
RP
RP
RAS
RP
RAS
RAS
t
T
t
t
t
t
t
CRP
RPC
CP
RPC
CP
t
t
t
t
CHR
CSR
CHR
CSR
UCAS
LCAS
Address
t
OFR
t
OFF
High-Z
Dout
20
HM5118165 Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
UCAS
LCAS
t
t
RAL
RAD
t
t
t
t
CAH
RAH
ASR
ASC
Address
Row
Column
t
RRH
t
t
RCS
DZC
t
RCH
WE
t
WED
t
t
CDD
RDD
High-Z
Din
t
t
OED
DZO
t
OEA
OE
t
OEZ
t
CAC
t
WEZ
OHO
t
AA
t
t
t
t
RAC
OFF
OH
t
CLZ
Dout
Dout
t
OFR
t
OHR
21
HM5118165 Series
EDO Page Mode Read Cycle
t
RP
t
t
RNCD
t
HPC
t
RASP
RAS
t
t
t
CRP
HPC
t
HPC
t
CPRH
CP
t
t
T
CSH
t
CP
t
t
CP
t
RSH
t
t
CAS
UCAS
LCAS
CAS
CAS
CAS
t
RCHC
t
RCHR
tRCS
t
t
RRH
RCH
tRCS
tRCH
WE
t
RAL
t
t
CAH
t
tCAH
tCAH
WED
tASC
tASC
tCAH
tRAH
ASC
tASC
tASR
Address
Row
Column 1
Column 2
t
Column 3
t
CAL
Column 4
t
t
CAL
CAL
CAL
t
t
RDD
CDD
t
DZC
High-Z
Din
t
t
t
DZO
COP
COL
t
OED
OE
t
t
OFR
CPA
t
CPA
t
OEA
t
t
t
CPA
AA
t
OHR
OEZ
AA
t
t
OEZ
AA
t
t
CAC
t
CAC
t
OEZ
t
t
t
OHO
CAC
AA
t
t
t
t
t
CAC
WEZ
OHO
OFF
OH
tOEA
t
t
RAC
OEA
t
DOH
t
OHO
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
22
HM5118165 Series
EDO Page Mode Read Cycle (2CAS)
t
RP
t
RNCD
t
RASP
RAS
t
t
t
t
HPC
HPC
CRP
HPC
t
t
t
T
CSH
t
CP
t
t
CP
CP
t
RSH
t
t
CAS
LCAS
UCAS
CAS
CAS
t
CAS
t
RCHC
t
t
tRCS
RRH
RCH
WE
t
RAL
t
WED
t
CAH
tASC
tCAH
t
tCAH
tCAH
tASC
tRAH ASC
tASC
tASR
Address
Row
Column 1
t
Column 2
t
Column 3
t
CAL
Column 4
CAL
CAL
t
t
RDD
t
CAL
t
DZC
CDD
High-Z
Din
t
t
t
DZO
COP
COL
t
OED
OE
t
t
OFR
CPA
t
CPA
t
OEA
t
t
t
t
OHR
OEZ
AA
t
t
OEZ
AA
t
CAC
CAC
t
OEZ
t
t
OHO
AA
t
t
t
t
CAC
OHO
OFF
OH
t
t
DOH
OEA
t
RAC
t
OHO
L Dout
U Dout
Dout 1
Dout 2
Dout 2
Dout 4
t
CPA
AA
t
t
OEA
t
CAC
Dout 4
Dout 1
Dout 3
23
HM5118165 Series
EDO Page Mode Early Write Cycle
tRASP
tRP
RAS
tT
tCSH
tHPC
tRSH
tCAS
tCP
tCAS
tCP
tCRP
tCAS
tRCD
UCAS
LCAS
tRAH
tASR
tASC tCAH
tASC
tCAH
tCAH
tASC
Row
Column 1
Column 2
Column N
Address
tWCH
tWCH
tWCS
tWCS
tWCS tWCH
WE
tDS
tDH
tDS
tDH
tDS
tDH
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
24
HM5118165 Series
EDO Page Mode Delayed Write Cycle*18
t
RASP
t
RP
RAS
t
t
t
t
CP
CRP
T
CP
t
t
t
t
CSH
HPC
RSH
CAS
t
t
t
CAS
RCD
CAS
UCAS
LCAS
t
RAD
t
t
t
t
ASR
ASC
t
ASC
t
ASC
t
t
RAH
CAH
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
CWL
CWL
t
CWL
t
RWL
t
t
RCS
RCS
RCS
WE
t
t
t
WP
WP
WP
t
t
t
t
t
t
t
DZC DS
DZC DS
DZC DS
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
DZO
DZO
DZO
OED
t
t
OED
OED
t
t
t
OEH
OEH
OEH
OE
t
t
t
CLZ
CLZ
CLZ
t
t
t
OEZ
OEZ
OEZ
High-Z
Dout
Invalid Dout
Invalid Dout
Invalid Dout
25
HM5118165 Series
EDO Page Mode Read-Modify-Write Cycle*18
t
RASP
t
RP
RAS
t
t
T
HPRWC
t
t
t
t
RSH
CAS
t
CRP
CP
CP
t
t
t
CAS
RCD
CAS
UCAS
LCAS
t
RAD
t
t
t
t
ASC
t
CAH
ASR
ASC
RAH
ASC
t
t
t
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
t
t
t
CWL
RWD
AWD
CWL
CPW
AWD
CWL
CPW
AWD
t
RWL
t
t
t
t
t
CWD
CWD
RCS
CWD
RCS
WE
t
t
t
t
t
WP
t
DS
RCS
DZO
WP
DS
WP
t
t
t
DS
t
DZC
DZC
DZC
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
OED
OED
OED
t
t
t
DZO
DZO
t
t
t
OEH
OEH
OEH
OE
t
t
t
OHO
OHO
OHO
t
t
t
t
t
t
OEA
CAC
OEA
CAC
OEA
CAC
t
t
t
AA
AA
AA
t
t
CPA
CPA
t
t
RAC
t
t
t
OEZ
t
t
OEZ
OEZ
CLZ
CLZ
CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
26
HM5118165 Series
EDO Page Mode Mix Cycle (1)
t
RP
t
RASP
RAS
t
CRP
t
T
t
t
t
CP
CP
CP
t
t
t
t
CAS
CAS
UCAS
CAS
CAS
LCAS
t
CSH
t
RSH
tRCD
t
t
tRCS
RRH
RCH
tWCS
tRCS
tWCH
t
t
CPW
AWD
tWP
WE
t
RAL
tCAH
tASC
tRAH
tASC
t
tASC tCAH
tCAH
CAH
tASC
tASR
Address
Row
Column 1
Column 2
t
Column 3
Column 4
CAL
t
RDD
t
CAL
t
t
CDD
DH
t
t
DH
DS
t
DS
High-Z
Din
Din 1
Din 3
t
OED
t
WED
OE
t
t
OFR
WEZ
t
CPA
CPA
t
t
t
t
CPA
t
AA
t
AA
t
OEZ
OEZ
t
t
t
OEA
AA
CAC
OHO
t
CAC
tOHO
Dout 3
t
t
OEA
CAC
t
t
OFF
OH
t
DOH
Dout
Dout 2
Dout 4
27
HM5118165 Series
EDO Page Mode Mix Cycle (2)
t
RP
t
RNCD
t
RASP
RAS
t
CRP
t
t
T
t
CSH
t
CP
t
CP
CP
t
t
t
t
CAS
UCAS
LCAS
CAS
CAS
CAS
tRCD
tRCS
tRCHR
t
RSH
t
RCS
t
RRH
tWCS
tWCH
t
RCS
tRCH
t
RCH
tWP
t
CPW
WE
t
RAL
tASC
tRAH
t
CAH
tASC
tASC tCAH
Column 2
tCAH
tCAH
tASC
tASR
Address
Row
Column 1
Column 3
t
Column 4
t
t
CAL
CAL
CAL
t
DS
t
t
RDD
CDD
t
t
t
DH
DS
DH
High-Z
Din
Din 2
Din 3
t
t
OED
t
COP
OED
t
WED
t
COL
OE
t
OFR
WEZ
t
t
OEA
t
t
t
t
CPA
t
AA
t
CPA
t
OEA
AA
OEZ
t
t
AA
OEZ
t
CAC
t
t
CAC
OEZ
OHO
t
t
RAC
CAC
t
OEA
t
t
t
OFF
OH
t
OHO
OHO
Dout
Dout 1
Dout 4
Dout 3
28
HM5118165 Series
Self Refresh Cycle (L-version)*28, 29, 30, 31
t
t
t
RASS
RP
RPS
RAS
t
T
t
t
t
CRP
RPC
CP
t
CSR
t
CHS
UCAS
LCAS
t
OFR
t
OFF
High-Z
Dout
29
HM5118165 Series
Package Dimensions
HM5118165J/LJ Series (CP-42D)
Unit: mm
27.06
27.43 Max
22
42
21
1
0.74
1.30 Max
1.27
9.40 ± 0.25
CP-42D
Conforms
—
Weight (reference value) 1.75 g
0.43 ± 0.10
0.41 ± 0.08
0.10
Hitachi Code
JEDEC
EIAJ
Dimension including the plating thickness
Base material dimension
30
HM5118165 Series
HM5118165TT/LTT Series (TTP-50/44DC)
Unit: mm
20.95
21.35 Max
50
40 36
26
25
11 15
0.80
1
0.80
0.27 ± 0.07
0.25 ± 0.05
M
0.13
11.76 ± 0.20
1.15 Max
0° – 5°
0.50 ± 0.10
3.20
0.10
Hitachi Code
JEDEC
EIAJ
TTP-50/44DC
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.50 g
31
HM5118165 Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi Semiconductor
(America) Inc.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1897
U S A
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Tel: 800-285-1601
Fax:303-297-0447
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
32
HM5118165 Series
Revision Record
Rev. Date
Contents of Modification
Initial issue
Drawn by Approved by
Y. Kasama M. Mishima
Y. Kasama M. Mishima
1.0
2.0
Sep. 30, 1996
Nov. 26, 1996
Addition of HM5118165-5 Series
Power dissipation (active)
1018/907 mW(max) to 1045/935/825 mW (max)
DC Characteristics
ICC7 max: 185/165 mA to 185/165/145 mA
AC Characteristics
tRCD min: 20/20 ns to 11/14/14 ns
tRAD min: 15/15 ns to 9/12/12 ns
tRSH min: 15/18 ns to 10/13/13 ns
t
t
RRH min: 0/0 ns to 5/5/5 ns
RWC min: 136/161 ns to 111/135/161 ns
tRPC min: 0/0 ns to 5/5/5 ns
Timing Waveforms
Addition of tRNCD timing to EDO page mode mix
cycle (2)
3.0
4.0
Feb. 24, 1997
Nov. 1997
AC Characteristics
Y. Kasama Y. Matsuno
t
RRH min: 5/5/5 ns to 0/0/0 ns
Change of Subtitle
33
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