HM5164160ALJ-7 [HITACHI]
Fast Page DRAM, 4MX16, 70ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, SOJ-50;
| 型号： | HM5164160ALJ-7 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Fast Page DRAM, 4MX16, 70ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, SOJ-50 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总32页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM5164160A Series
HM5165160A Series
4194304-word × 16-bit Dynamic Random Access Memory
ADE-203-596 (Z)
Preliminary
Rev. 0.1
Jan. 22, 1997
Description
The Hitachi HM5164160A Series, HM5165160A Series are CMOS dynamic RAMs organized as 4,194,304-
word × 16-bit. They employ the most advanced CMOS technology for high performance and low power.
The HM5164160A Series, HM5165160A Series offer Fast Page Mode as a high speed access mode. They
have the package variations of standard 400-mil 50-pin plastic SOJ and standard 400-mil 50-pin plastic
TSOPII.
Features
•
•
Single 3.3 V (±0.3 V)
High speed
Access time: 50 ns/60 ns/70 ns (max)
Low power dissipation
•
Active mode : TBD/432 mW/360 mW (max) (HM5164160A Series)
: TBD/630 mW/540 mW (max) (HM5165160A Series)
Standby mode : 7.2 mW (max)
: TBD (L-version)
•
•
Fast page mode capability
Long refresh period
8192 RAS only refresh cycles
4096 CBR/Hidden refresh cycles : 64 ms
: 128 ms (L-version)
: 64 ms (HM5165160A Series)
4096 CBR/Hidden refresh cycles : 64 ms
: 128 ms (L-version)
: 64 ms (HM5164160A Series)
4096 RAS only refresh cycles
Preliminary: This document contains information on a new product. Specifications and information
contained herein are subject to change without notice.
HM5164160A Series, HM5165160A Series
•
4 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
Self refresh (L-version)
2CAS-byte control
•
•
Battery backup operation (L-version)
Ordering Information
Type No.
Access time
Package
HM5164160AJ-5
HM5164160AJ-6
HM5164160AJ-7
50 ns
60 ns
70 ns
400-mil 50-pin plastic SOJ (CP-50DA)
HM5164160ALJ-5
HM5164160ALJ-6
HM5164160ALJ-7
50 ns
60 ns
70 ns
HM5165160AJ-5
HM5165160AJ-6
HM5165160AJ-7
50 ns
60 ns
70 ns
HM5165160ALJ-5
HM5165160ALJ-6
HM5165160ALJ-7
50 ns
60 ns
70 ns
HM5164160ATT-5
HM5164160ATT-6
HM5164160ATT-7
50 ns
60 ns
70 ns
400-mil 50-pin plastic TSOP II (TTP-50DB)
HM5164160ALTT-5
HM5164160ALTT-6
HM5164160ALTT-7
50 ns
60 ns
70 ns
HM5165160ATT-5
HM5165160ATT-6
HM5165160ATT-7
50 ns
60 ns
70 ns
HM5165160ALTT-5
HM5165160ALTT-6
HM5165160ALTT-7
50 ns
60 ns
70 ns
2
HM5164160A Series, HM5165160A Series
Pin Arrangement
HM5164160AJ/ALJ Series
HM5164160ATT/ALTT Series
VSS
VSS
V
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1
1
CC
I/O15
I/O14
I/O13
I/O12
I/O15
I/O14
I/O13
I/O12
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
2
2
3
3
4
4
5
5
V
V
6
6
SS
SS
I/O11
I/O10
I/O9
I/O8
NC
I/O11
I/O10
I/O9
I/O8
NC
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
V
VCC
WE
RAS
NC
VCC
WE
RAS
NC
SS
SS
LCAS
UCAS
OE
LCAS
UCAS
OE
NC
NC
NC
NC
NC
NC
NC
NC
A12
A11
A10
A9
A12
A11
A10
A9
NC
NC
A0
A0
A1
A1
A2
A2
A8
A8
A3
A3
A7
A7
A4
A4
A6
A6
A5
A5
V
SS
V
SS
V
VCC
CC
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
— Row/Refresh address A0 to A12
A0 to A12
— Column address
Data input/Data output
Row address strobe
A0 to A8
I/O0 to I/O15
RAS
UCAS, LCAS Column address strobe
WE
OE
VCC
VSS
NC
Read/Write enable
Output enable
Power supply
Ground
No connection
3
HM5164160A Series, HM5165160A Series
Pin Arrangement
HM5165160AJ/ALJSeries
HM5165160ATT/ALTT Series
VSS
VSS
V
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1
1
CC
I/O15
I/O14
I/O13
I/O12
I/O15
I/O14
I/O13
I/O12
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
2
2
3
3
4
4
5
5
V
V
6
6
SS
SS
I/O11
I/O10
I/O9
I/O8
NC
I/O11
I/O10
I/O9
I/O8
NC
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
V
VCC
WE
RAS
NC
VCC
WE
RAS
NC
SS
SS
LCAS
UCAS
OE
LCAS
UCAS
OE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A11
A10
A9
A11
A10
A9
A0
A0
A1
A1
A2
A2
A8
A8
A3
A3
A7
A7
A4
A4
A6
A6
A5
A5
V
SS
V
SS
V
VCC
CC
(Top view)
(Top view)
Pin Description
Pin name
Function
Address input
— Row/Refresh address A0 to A11
A0 to A11
— Column address
Data input/Data output
Row address strobe
A0 to A9
I/O0 to I/O15
RAS
UCAS, LCAS Column address strobe
WE
OE
VCC
VSS
NC
Read/Write enable
Output enable
Power supply
Ground
No connection
4
HM5164160A Series, HM5165160A Series
Block Diagram (HM5164160A Series)
RAS UCAS LCAS
WE
OE
Timing and control
A0
Column decoder
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
A1
to
Column
address
buffers
•
•
•
A8
I/O0
to
I/O15
I/O buffers
•
•
•
Row
address
buffers
A9
to
A12
5
HM5164160A Series, HM5165160A Series
Block Diagram (HM5165160A Series)
RAS UCAS LCAS
WE
OE
Timing and control
Column decoder
A0
A1
to
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
Column
address
buffers
•
•
•
A9
I/O0
to
I/O buffers
•
•
•
I/O15
Row
address
buffers
A10
to
A11
6
HM5164160A Series, HM5165160A Series
Truth Table
RAS
LCAS
UCAS
WE
D
OE
Output
Open
Valid
Operation
Standby
H
D
L
D
H
L
D
L
H
L
Lower byte Read cycle
Upper byte
L
H
L
H
L
Valid
L
L
H
L
Valid
Word
L
L
H
L
L*2
L*2
L*2
L*2
L*2
L*2
H to L
H to L
H to L
D
D
Open
Open
Open
Lower byte Early write cycle
Upper byte
L
H
L
D
L
L
D
Word
L
L
H
L
H
Undefined Lower byte Delayed write cycle
Undefined Upper byte
L
H
L
H
L
L
H
Undefined Word
L
L
H
L
L to H
L to H
L to H
D
Valid
Valid
Valid
Open
Open
Open
Open
Open
Lower byte Read-modify-write cycle
L
H
L
Upper byte
Word
L
L
L
H
H
L
H
L
Word
Word
Word
Word
RAS-only refresh cycle
H to L
H to L
H to L
L
H
D
CAS-before-RAS refresh cycle or
Self refresh cycle (L-version)
H
L
H
D
L
H
D
L
L
H
H
Read cycle (Output disabled)
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. tWCS ≥ 0 ns Early write cycle
tWCS < 0 ns Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output HIZ control are done independently by each UCAS, LCAS.
ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
7
HM5164160A Series, HM5165160A Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to VCC + 0.5 (≤ 4.6 V (max))
VCC
–0.5 to +4.6
50
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
3.0
Typ
3.3
—
Max
Unit
V
Notes
Supply voltage
3.6
1, 2
1
Input high voltage
Input low voltage
VIH
2.0
VCC + 0.3
0.8
V
VIL
–0.3
—
V
1
Notes: 1. All voltage referred to VSS
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins
must be on the same level.
8
HM5164160A Series, HM5165160A Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5164160A Series)
HM5164160A
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit Test conditions
Operating current*1, *2
ICC1
ICC2
—
—
TBD
TBD
—
—
120
2
—
—
100 mA tRC = min
Standby current
2
mA TTL interface
RAS, UCAS, LCAS = VIH
Dout = High-Z
—
—
TBD
TBD
—
—
1
—
—
1
mA CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
TBD
TBD µA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2 ICC3
—
—
TBD
TBD
—
—
120
5
—
—
100 mA tRC = min
mA RAS = VIH
UCAS, LCAS = VIL
Dout = enable
120 mA tRC = min
Standby current*1
ICC5
5
CAS-before-RAS refresh
current
ICC6
—
TBD
—
140
—
Fast page mode current*1, *3 ICC7
—
—
TBD
TBD
—
—
100
—
—
90
mA tPC = min
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10
TBD
TBD µA
CMOS interface
Dout = High-Z
CBR refresh: tRC = 31.3 µs
t
RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
TBD
—
TBD
—
TBD µA
CMOS interface
RAS, UCAS,
LCAS ≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
TBD TBD –10 10
TBD TBD –10 10
–10 10
–10 10
µA
µA
0 V ≤ Vin ≤ VCC + 0.3 V
ILO
0 V ≤ Vout ≤ VCC
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
TBD TBD 2.4 VCC 2.4 VCC
TBD TBD 0.4 0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
0
0
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less within one page mode cycle tPC.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
9
HM5164160A Series, HM5165160A Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5165160A Series)
HM5165160A
-5
-6
-7
Parameter
Symbol Min Max Min Max Min Max Unit Test conditions
Operating current*1, *2
ICC1
ICC2
—
—
TBD
TBD
—
—
175
2
—
—
150 mA tRC = min
Standby current
2
mA TTL interface
RAS, UCAS, LCAS = VIH
Dout = High-Z
—
—
TBD
TBD
—
—
1
—
—
1
mA CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
TBD
TBD µA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2 ICC3
—
—
TBD
TBD
—
—
175
5
—
—
150 mA tRC = min
mA RAS = VIH
UCAS, LCAS = VIL
Dout = enable
Standby current*1
ICC5
5
CAS-before-RAS refresh
current
ICC6
—
TBD
—
140
—
120 mA tRC = min
Fast page mode current*1, *3 ICC7
—
—
TBD
TBD
—
—
120
—
—
110 mA tPC = min
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10
TBD
TBD µA
TBD µA
CMOS interface
Dout = High-Z
CBR refresh: tRC = 31.3 µs
t
RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
TBD
—
TBD
—
CMOS interface
RAS, UCAS,
LCAS ≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
TBD TBD –10 10
TBD TBD –10 10
–10 10
–10 10
µA
µA
0 V ≤ Vin ≤ VCC + 0.3 V
ILO
0 V ≤ Vout ≤ VCC
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
TBD TBD 2.4 VCC 2.4 VCC
TBD TBD 0.4 0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
0
0
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less within one page mode cycle tPC.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
10
HM5164160A Series, HM5165160A Series
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
5
7
7
1
CI2
—
pF
1
CI/O
—
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS, UCAS and LCAS = VIH to disable Dout.
11
HM5164160A Series, HM5165160A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *18, *19
Test Conditions
•
•
•
•
Input rise and fall time: 5 ns
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5164160A/HM5165160A
-5
-6
-7
Parameter
Symbol Min Max
Min
110
40
10
60
15
0
Max
—
Min Max
Unit Notes
Random read or write cycle time
RAS precharge time
CAS precharge time
RAS pulse width
tRC
TBD
TBD
TBD
—
—
—
130
50
—
—
—
ns
ns
ns
tRP
—
tCP
—
10
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
TBD TBD
TBD TBD
10000 70
10000 18
10000 ns
10000 ns
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
TBD
TBD
TBD
TBD
—
—
—
—
—
—
—
—
45
30
—
—
—
—
—
—
50
0
—
—
—
—
52
35
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
0
10
0
21
21
3
10
20
15
15
60
5
15
20
15
18
70
5
TBD TBD
TBD TBD
RAS to column address delay time tRAD
4
RAS hold time
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
TBD
TBD
TBD
TBD
TBD
TBD
—
—
—
—
—
—
CAS hold time
23
22
5
CAS to RAS precharge time
OE to Din delay time
OE delay time from Din
CAS delay time from Din
Transition time (rise and fall)
15
0
18
0
6
0
0
6
TBD TBD
3
3
7
12
HM5164160A Series, HM5165160A Series
Read Cycle
HM5164160A/HM5165160A
-5
-6
Min
—
—
—
—
0
-7
Parameter
Symbol Min Max
Max
60
15
30
15
—
Min Max
Unit Notes
Access time from RAS
Access time from CAS
Access time from address
Access time from OE
Read command setup time
tRAC
tCAC
tAA
—
TBD
TBD
TBD
TBD
—
—
—
—
—
0
70
18
35
18
—
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8, 9
—
9, 10, 17
9, 11, 17
9, 25
—
tOEA
tRCS
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
Read command hold time to CAS tRCH
Read command hold time to RAS tRRH
Column address to RAS lead time tRAL
Column address to CAS lead time tCAL
—
0
—
0
12, 22
12
—
5
—
5
—
—
—
—
—
—
15
15
—
—
30
30
0
—
35
35
0
—
—
CAS to output in low-Z
tCLZ
tOH
—
—
Output data hold time
—
3
—
3
Output data hold time from OE
Output buffer turn-off time
Output buffer turn-off to OE
CAS to Din delay time
tOHO
tOFF
tOEZ
tCDD
—
3
—
3
TBD
TBD
—
—
—
15
15
15
—
—
—
18
13
13
5
—
TBD
Write Cycle
HM5164160A/HM5165160A
-5
Symbol Min Max
-6
-7
Parameter
Min
0
Max
—
Min Max
Unit Notes
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
tWCS
tWCH
tWP
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
14, 21
21
10
10
15
15
0
—
15
10
18
18
0
—
tRWL
tCWL
tDS
—
—
23
—
15, 23
15, 23
Data-in hold time
tDH
10
—
15
13
HM5164160A Series, HM5165160A Series
Read-Modify-Write Cycle
HM5164160A/HM5165160A
-5
-6
-7
Parameter
Symbol Min Max
Min
155
85
Max
—
Min Max
Unit Notes
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
tRWC
tRWD
tCWD
TBD
TBD
TBD
TBD
TBD
—
—
—
—
—
181
98
46
63
18
—
—
—
—
—
ns
—
ns
ns
ns
ns
14
14
14
40
—
Column address to WE delay time tAWD
55
—
OE hold time from WE
tOEH
15
—
Refresh Cycle
HM5164160A/HM5165160A
-5
Symbol Min Max
-6
Min
5
-7
Parameter
Max
—
Min Max
Unit Notes
CAS setup time (CBR refresh cycle) tCSR
CAS hold time (CBR refresh cycle) tCHR
WE setup time (CBR refresh cycle) tWRP
WE hold time (CBR refresh cycle) tWRH
TBD
TBD
TBD
TBD
TBD
—
—
—
—
—
5
—
—
—
—
—
ns
ns
ns
ns
ns
21
22
10
0
—
10
0
—
10
0
—
10
0
RAS precharge to CAS hold time
tRPC
—
21
Fast Page Mode Cycle
HM5164160A/HM5165160A
-5
Symbol Min Max
-6
-7
Parameter
Min
40
—
Max
Min Max
45
Unit Notes
Fast page mode cycle time
tPC
TBD
—
—
—
—
ns
Fast page mode RAS pulse width tRASP
Access time from CAS precharge tCPA
RAS hold time from CAS precharge tCPRH
TBD
TBD
—
100000 —
100000 ns
16
—
—
35
—
—
40
—
ns
ns
9, 17, 22
TBD
35
40
14
HM5164160A Series, HM5165160A Series
Fast Page Mode Read-Modify-Write Cycle
HM5164160A/HM5165160A
-5
Symbol Min Max
-6
-7
Parameter
Min
85
Max
Min Max
Unit Notes
Fast page mode read-modify-write tPRWC
cycle time
TBD
—
—
96
—
ns
WE delay time from CAS precharge tCPW
TBD
—
60
—
68
—
ns
14, 22
Refresh (HM5164160A Series)
Parameter
Symbol
tREF
Max
64
Unit
ms
Note
Refresh period
8192 cycles
4096 cycles
Refresh period (L-version)
tREF
128
ms
Refresh (HM5165160A Series)
Parameter
Symbol
tREF
Max
64
Unit
ms
Note
Refresh period
4096 cycles
4096 cycles
Refresh period (L-version)
tREF
128
ms
Self Refresh Mode (L-version)
HM5164160AL/HM5165160AL
-5
Symbol Min Max
-6
-7
Parameter
Min
100
110
–50
Max
—
Min Max
Unit Notes
RAS pulse width (Self refresh)
tRASS
TBD
TBD
TBD
—
—
—
100
130
–50
—
—
—
µs
ns
ns
26
RAS precharge time (Self refresh) tRPS
CAS hold time (Self refresh) tCHS
—
—
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
15
HM5164160A Series, HM5165160A Series
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and
are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD
(min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW
(min), the cycle is a read-modify-write and the data output will contain data read from the selected
cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access
time) is indeterminate.
15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE
leading edge in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in fast page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA
.
18. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.
UCAS and LCAS cannot be staggered within the same write/read cycles.
19. All the VCC and VSS pins shall be supplied with the same voltages.
20. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS.
22. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the later rising edge of UCAS or LCAS.
23. tCWL, tDH, tDS and tCHS should be satisfied by both UCAS and LCAS.
24. tCP is determined by the time that both UCAS and LCAS are high.
25. When output buffers are enabled once, sustain the low impedance state until valid data is obtained.
When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS
line noise, which causes to degrade VIH min/VIL max level.
26. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition
state from normal operation mode to self refresh mode. If tRASS ≥ 100 µs, then RAS precharge time
should use tRPS instead of tRP.
27. CBR burst refresh or 4096 cycles of distributed CBR refresh with 15.6 µs interval should be
executed within 64 ms immediately after exiting from and before entering into the self refresh
mode.
28. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self
refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
29. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ V ≤ VIL (max))
IN
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL.
16
HM5164160A Series, HM5165160A Series
Notes concerning 2CAS control
Please do not separate the UCAS/LCAS operation timing intentionally. However skew between
UCAS/LCAS are allowed under the following conditions.
1. Each of the UCAS/LCAS should satisfy the timing specifications individually.
2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS
Delayed write
UCAS
Early write
LCAS
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is
satisfied, fast page mode can be performed.
RAS
UCAS
LCAS
t
UL
4. Byte control operation by remaining UCAS or LCAS high is guaranteed.
17
HM5164160A Series, HM5165160A Series
Timing Waveforms*29
Read Cycle
t
t
RC
t
RAS
RP
RAS
t
t
CSH
CRP
t
t
t
RCD
RSH
CAS
t
T
UCAS
LCAS
t
t
t
RAD
RAL
CAL
t
t
t
CAH
ASR
ASC
t
RAH
Row
Column
Address
t
RRH
t
RCH
t
RCS
WE
t
t
CDD
DZC
High-Z
Din
t
t
t
OED
OEA
DZO
OE
t
t
OEZ
t
CAC
OHO
t
AA
t
OFF
t
RAC
t
t
OH
CLZ
Dout
Dout
18
HM5164160A Series, HM5165160A Series
Early Write Cycle
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
UCAS
LCAS
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
WCH
WCS
WE
t
t
DH
DS
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
19
HM5164160A Series, HM5165160A Series
Delayed Write Cycle*20
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
UCAS
LCAS
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
t
CWL
RWL
WP
t
RCS
WE
t
t
t
DH
DZC
DS
High-Z
Din
Din
t
t
OEH
DZO
t
OED
OE
t
OEZ
t
CLZ
High-Z
Dout
Invalid Dout
20
HM5164160A Series, HM5165160A Series
Read-Modify-Write Cycle*20
t
t
RWC
RAS
t
RP
RAS
t
T
t
t
t
CRP
RCD
CAS
UCAS
LCAS
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
Address
Row
Column
t
t
t
t
t
CWD
CWL
t
RCS
AWD
RWD
RWL
t
WP
WE
Din
OE
t
t
DH
DZC
t
DS
High-Z
Din
t
OED
t
OEH
t
DZO
t
OEA
t
CAC
t
t
OEZ
t
t
AA
t
RAC
OHO
High-Z
Dout
Dout
CLZ
21
HM5164160A Series, HM5165160A Series
RAS-Only Refresh Cycle
t
RC
t
t
RP
RAS
RAS
t
T
t
t
t
CRP
RPC
CRP
UCAS
LCAS
t
t
ASR
RAH
Row
Address
Dout
t
OFF
High-Z
CAS-Before-RAS Refresh Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
t
t
t
t
t
CRP
RPC
CSR
CHR
RPC
t
T
UCAS
LCAS
t
CP
t
t
t
WRH
CP
WRP
WE
Address
Dout
t
OFF
High-Z
22
HM5164160A Series, HM5165160A Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
UCAS
LCAS
t
t
RAL
RAD
t
t
t
t
CAH
ASR RAH
Row
ASC
Address
Column
t
RRH
t
RCS
t
RCH
WE
t
t
CDD
DZC
High-Z
Din
t
t
OED
DZO
t
OEA
OE
t
t
t
CAC
OEZ
t
AA
OHO
t
t
t
RAC
OFF
OH
t
CLZ
Dout
Dout
23
HM5164160A Series, HM5165160A Series
Fast Page Mode Read Cycle
t
RASP
t
t
RP
CPRH
RAS
t
T
t
t
t
t
CSH
PC
RSH
t
CRP
t
t
t
t
t
RCD
CAS
CP
CAS
CAL
CP
CAS
UCAS
LCAS
t
t
RAL
CAL
t
t
t
RAD
CAL
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Row
Address
Column 1
Column 2
Column N
t
t
t
t
RCS
RCS
RRH
RCH
t
t
t
t
t
t
RCS
DZC
RCH
CDD
RCH
CDD
WE
Din
OE
t
t
DZC
DZC
t
CDD
High-Z
High-Z
High-Z
t
t
t
t
t
t
OED
DZO
OED
DZO OED
DZO
t
t
t
CPA
RAC
CPA
t
t
t
t
t
t
OH
AA
OH
AA
OH
AA
t
OHO
t
t
OHO
OHO
t
t
t
OEA
OEA
OEA
t
t
CAC
t
t
t
t
t
CAC
CAC
CLZ
OFF
OFF
OEZ
OFF
OEZ
t
t
t
t
CLZ
t
OEZ
CLZ
Dout 1
Dout 2
Dout N
Dout
24
HM5164160A Series, HM5165160A Series
Fast Page Mode Early Write Cycle
t
t
RP
RASP
RAS
t
T
t
t
t
RSH
CSH
PC
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
UCAS
LCAS
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
WCH
WCS
WCH
WCS
WCH
WCS
WE
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
25
HM5164160A Series, HM5165160A Series
Fast Page Mode Delayed Write Cycle*20
t
RASP
t
RP
RAS
t
t
t
t
CP
CRP
T
CP
t
t
t
t
CSH
PC
RSH
CAS
t
t
t
CAS
RCD
CAS
UCAS
LCAS
t
RAD
t
t
t
t
ASR
ASC
t
ASC
t
ASC
t
t
RAH
CAH
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
CWL
CWL
t
CWL
t
RWL
t
t
RCS
RCS
RCS
WE
Din
t
t
t
WP
WP
WP
t
t
t
t
t
t
t
DZC DS
DZC DS
DZC DS
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
t
t
t
DZO
DZO
DZO
OED
t
t
OED
OED
t
t
t
OEH
OEH
OEH
OE
t
t
t
CLZ
CLZ
CLZ
t
t
t
OEZ
OEZ
OEZ
High-Z
Dout
Invalid Dout
Invalid Dout
Invalid Dout
26
HM5164160A Series, HM5165160A Series
Fast Page Mode Read-Modify-Write Cycle*20
t
RASP
t
RP
RAS
t
t
T
PRWC
t
t
t
t
RSH
CAS
t
CRP
CP
CP
t
t
t
CAS
RCD
CAS
UCAS
LCAS
t
RAD
t
t
t
t
ASC
t
CAH
ASR
ASC
RAH
ASC
t
t
t
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
t
t
t
RWD
AWD
CWL
CPW
AWD
CWL
t
CPW
AWD
CWL
t
RCS
RWL
t
t
t
t
CWD
CWD
RCS
CWD
WE
t
t
t
t
t
WP
t
DS
RCS
DZO
WP
DS
WP
t
t
t
DS
t
DZC
DZC
DZC
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
OED
OED
OED
t
t
t
DZO
DZO
t
t
t
OEH
OEH
OEH
OE
t
t
t
OHO
OHO
OHO
t
t
t
t
t
t
OEA
CAC
OEA
CAC
OEA
CAC
t
t
t
AA
AA
AA
t
t
CPA
CPA
t
t
RAC
t
t
t
OEZ
t
t
OEZ
OEZ
CLZ
CLZ
CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
27
HM5164160A Series, HM5165160A Series
Self Refresh Cycle (L-version)*26, 27, 28
t
t
t
RASS
RP
RPS
RAS
t
T
t
t
t
CRP
RPC
CP
t
CSR
t
CHS
UCAS
LCAS
t
t
WRH
WRP
WE
t
OFF
High-Z
Dout
28
HM5164160A Series, HM5165160A Series
Package Dimensions
HM5164160AJ/ALJ Series
HM5165160AJ/ALJ Series (CP-50DA)
Unit: mm
20.95
21.38 Max
50
26
1
25
0.47
1.09 Max
9.40 ± 0.25
0.80
0.32 ± 0.08
0.10
29
HM5164160A Series, HM5165160A Series
HM5164160ATT/ALTT Series
HM5165160ATT/ALTT Series (TTP-50DB)
Unit: mm
20.95
21.35 Max
50
26
25
1
0.80
+0.08
–0.07
M
0.32
0.16
11.76 ± 0.20
0 – 5°
0.10
1.075 Max
0.5 ± 0.1
30
HM5164160A Series, HM5165160A Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other
reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such
use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Tel: 415-589-8300
Fax: 535-1533
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Berkshire SL6 8YA
United Kingdom
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 0628-585000
Fax: 0628-778322
Tel: 27359218
Fax: 27306071
31
HM5164160A Series, HM5165160A Series
Revision Record
Rev. Date
0.0 Jun. 3, 1996
Contents of Modification
Drawn by Approved by
Initial issue
32
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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