HM5264165A60 [HITACHI]

64M LVTTL interface SDRAM 133 MHz/100 MHz; LVTTL 64M SDRAM接口的133 MHz / 100 MHz的
HM5264165A60
型号: HM5264165A60
厂家: HITACHI SEMICONDUCTOR    HITACHI SEMICONDUCTOR
描述:

64M LVTTL interface SDRAM 133 MHz/100 MHz
LVTTL 64M SDRAM接口的133 MHz / 100 MHz的

动态存储器
文件: 总67页 (文件大小:853K)
中文:  中文翻译
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HM5264165F-75/A60/B60  
HM5264805F-75/A60/B60  
HM5264405F-75/A60/B60  
64M LVTTL interface SDRAM  
133 MHz/100 MHz  
1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank  
/4-Mword × 4-bit × 4-bank  
PC/133, PC/100 SDRAM  
ADE-203-940B (Z)  
Rev. 1.0  
Nov. 10, 1999  
Description  
The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi  
HM5264805F is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The Hitachi HM5264405F  
is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs are referred to the  
rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.  
Features  
3.3 V power supply  
Clock frequency: 133 MHz/100 MHz (max)  
LVTTL interface  
Single pulsed RAS  
4 banks can operate simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length: 1/2/4/8/full page  
2 variations of burst sequence  
Sequential (BL = 1/2/4/8/full page)  
Interleave (BL = 1/2/4/8)  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Programmable CAS latency: 2/3  
Byte control by DQM:DQM (HM5264805F/HM5264405F)  
DQMU/DQML (HM5264165F)  
Refresh cycles: 4096 refresh cycles/64 ms  
2 variations of refresh  
Auto refresh  
Self refresh  
Full page burst length capability  
Sequential burst  
Burst stop capability  
Ordering Information  
Type No.  
Frequency  
CAS latency Package  
HM5264165FTT-75*1  
HM5264165FTT-A60  
HM5264165FTT-B60*2  
133 MHz  
100 MHz  
100 MHz  
3
2/3  
3
400-mil 54-pin plastic TSOP II (TTP-54D)  
HM5264165FLTT-75*1  
HM5264165FLTT-A60  
HM5264165FLTT-B60*2  
133 MHz  
100 MHz  
100 MHz  
3
2/3  
3
HM5264805FTT-75*1  
HM5264805FTT-A60  
HM5264805FTT-B60*2  
133 MHz  
100 MHz  
100 MHz  
3
2/3  
3
HM5264805FLTT-75*1  
HM5264805FLTT-A60  
HM5264805FLTT-B60*2  
133 MHz  
100 MHz  
100 MHz  
3
2/3  
3
HM5264405FTT-75*1  
HM5264405FTT-A60  
HM5264405FTT-B60*2  
133 MHz  
100 MHz  
100 MHz  
3
2/3  
3
HM5264405FLTT-75*1  
HM5264405FLTT-A60  
HM5264405FLTT-B60*2  
133 MHz  
100 MHz  
100 MHz  
3
2/3  
3
Note: 1. 100 MHz operation at CAS latency = 2.  
2. 66 MHz operation at CAS latency = 2.  
2
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Pin Arrangement (HM5264165F)  
54-pin TSOP  
1
2
3
4
5
6
7
8
9
VCC  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
VSS  
DQ0  
DQ15  
VCC  
Q
DQ1  
DQ2  
VSSQ  
DQ14  
DQ13  
VSS  
Q
DQ3  
DQ4  
VCC  
Q
DQ12  
DQ11  
VCC  
Q
DQ5  
DQ6  
VSSQ  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
DQ10  
DQ9  
VSS  
Q
DQ7  
VCC  
DQML  
WE  
VCC  
Q
DQ8  
VSS  
NC  
DQMU  
CLK  
CKE  
NC  
CAS  
RAS  
CS  
A13  
A12  
A10  
A0  
A11  
A9  
A8  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
VCC  
VSS  
(Top view)  
Pin Description  
Pin name  
Function  
Address input  
Row address  
Column address A0 to A7  
Bank select address A12/A13 (BS) CKE  
Pin name  
Function  
A0 to A13  
WE  
Write enable  
A0 to A11  
DQMU/DQML Input/output mask  
CLK  
Clock input  
Clock enable  
DQ0 to DQ15 Data-input/output  
VCC  
Power for internal circuit  
Ground for internal circuit  
Power for DQ circuit  
Ground for DQ circuit  
No connection  
CS  
Chip select  
VSS  
RAS  
CAS  
Row address strobe command  
Column address strobe command  
VCCQ  
VSSQ  
NC  
3
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Pin Arrangement (HM5264805F)  
54-pin TSOP  
1
VCC  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
VSS  
2
DQ0  
DQ7  
3
VCCQ  
VSSQ  
4
NC  
NC  
5
DQ1  
DQ6  
6
VSSQ  
VCC  
Q
7
NC  
NC  
8
DQ2  
DQ5  
9
VCCQ  
VSSQ  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
NC  
NC  
DQ3  
DQ4  
VSSQ  
NC  
VCC  
NC  
VSS  
NC  
DQM  
CLK  
CKE  
NC  
A11  
A9  
Q
VCC  
NC  
WE  
CAS  
RAS  
CS  
A13  
A12  
A10  
A0  
A8  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
VCC  
VSS  
(Top view)  
Pin Description  
Pin name  
Function  
Address input  
Row address  
Column address  
Pin name  
WE  
Function  
A0 to A13  
Write enable  
A0 to A11  
A0 to A8  
DQM  
Input/output mask  
Clock input  
CLK  
Bank select address A12/A13 (BS) CKE  
Clock enable  
DQ0 to DQ7  
CS  
Data-input/output  
VCC  
Power for internal circuit  
Ground for internal circuit  
Power for DQ circuit  
Ground for DQ circuit  
No connection  
Chip select  
VSS  
RAS  
Row address strobe command  
Column address strobe command  
VCCQ  
VSSQ  
NC  
CAS  
4
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Pin Arrangement (HM5264405F)  
54-pin TSOP  
1
2
3
4
5
6
7
8
9
VCC  
NC  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
VSS  
NC  
VSS  
NC  
VCCQ  
Q
NC  
DQ0  
DQ3  
VSS  
Q
NC  
NC  
VCC  
NC  
NC  
Q
VCCQ  
VSSQ  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
NC  
NC  
DQ1  
DQ2  
VSSQ  
NC  
VCC  
NC  
VSS  
NC  
DQM  
CLK  
CKE  
NC  
A11  
A9  
Q
VCC  
NC  
WE  
CAS  
RAS  
CS  
A13  
A12  
A10  
A0  
A8  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
VCC  
VSS  
(Top view)  
Pin Description  
Pin name  
Function  
Address input  
Row address  
Column address  
Pin name  
WE  
Function  
A0 to A13  
Write enable  
A0 to A11  
A0 to A9  
DQM  
Input/output mask  
Clock input  
CLK  
Bank select address A12/A13 (BS) CKE  
Clock enable  
DQ0 to DQ3  
CS  
Data-input/output  
VCC  
Power for internal circuit  
Ground for internal circuit  
Power for DQ circuit  
Ground for DQ circuit  
No connection  
Chip select  
VSS  
RAS  
Row address strobe command  
Column address strobe command  
VCCQ  
VSSQ  
NC  
CAS  
5
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Block Diagram (HM5264165F)  
A0 to A13  
A0 to A7  
A0 to A13  
Refresh  
counter  
Column address  
counter  
Column address  
buffer  
Row address  
buffer  
Row decoder  
Row decoder  
Row decoder  
Row decoder  
Memory array  
Bank 0  
Memory array  
Bank 1  
Memory array  
Bank 2  
Memory array  
Bank 3  
4096 row  
4096 row  
4096 row  
4096 row  
X 256 column  
X 16 bit  
X 256 column  
X 16 bit  
X 256 column  
X 16 bit  
X 256 column  
X 16 bit  
Control logic &  
timing generator  
Input  
buffer  
Output  
buffer  
DQ0 to DQ15  
6
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Block Diagram (HM5264805F)  
A0 to A13  
A0 to A8  
A0 to A13  
Refresh  
counter  
Column address  
counter  
Column address  
buffer  
Row address  
buffer  
Row decoder  
Row decoder  
Row decoder  
Row decoder  
Memory array  
Bank 0  
Memory array  
Bank 1  
Memory array  
Bank 2  
Memory array  
Bank 3  
4096 row  
X 512 column  
X 8 bit  
4096 row  
X 512 column  
X 8 bit  
4096 row  
X 512 column  
X 8 bit  
4096 row  
X 512 column  
X 8 bit  
Control logic &  
timing generator  
Input  
buffer  
Output  
buffer  
DQ0 to DQ7  
7
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Block Diagram (HM5264405F)  
A0 to A13  
A0 to A9  
A0 to A13  
Refresh  
counter  
Column address  
counter  
Column address  
buffer  
Row address  
buffer  
Row decoder  
Row decoder  
Row decoder  
Row decoder  
Memory array  
Bank 0  
Memory array  
Bank 1  
Memory array  
Bank 2  
Memory array  
Bank 3  
4096 row  
4096 row  
4096 row  
4096 row  
X 1024 column  
X 4 bit  
X 1024 column  
X 4 bit  
X 1024 column  
X 4 bit  
X 1024 column  
X 4 bit  
Control logic &  
timing generator  
Input  
buffer  
Output  
buffer  
DQ0 to DQ3  
8
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Pin Functions  
CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK  
rising edge.  
CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are  
ignored. However, internal operations (bank active, burst operations, etc.) are held.  
RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs,  
they function in a different way. These pins define operation commands (read, write, etc.) depending on the  
combination of their voltage levels. For details, refer to the command operation section.  
A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active  
command cycle CLK rising edge. Column address (AY0 to AY7; HM5264165F, AY0 to AY8;  
HM5264805F, AY0 to AY9; HM5264405F) is determined by A0 to A7, A8 or A9 (A7; HM5264165F, A8;  
HM5264805F, A9; HM5264405F) level at the read or write command cycle CLK rising edge. And this  
column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at  
the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command  
cycle, only the bank that is selected by A12/A13 (BS) is precharged. For details refer to the command  
operation section.  
A12/A13 (input pins): A12/A13 are bank select signal (BS). The memory array of the HM5264165F,  
HM5264805F, the HM5264405F is divided into bank 0, bank 1, bank 2 and bank 3. HM5264165F contain  
4096-row × 256-column × 16-bit. HM5264805F contain 4096-row × 512-column × 8-bit. HM5264405F  
contain 4096-row × 1024-column × 4-bit. If A12 is Low and A13 is Low, bank 0 is selected. If A12 is High  
and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and  
A13 is High, bank 3 is selected.  
CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK  
rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down  
mode, clock suspend mode and self refresh mode.  
DQM, DQMU/DQML (input pins): DQM, DQMU/DQML controls input/output buffers.  
Read operation: If DQM, DQMU/DQML is High, the output buffer becomes High-Z. If the DQM,  
DQMU/DQML is Low, the output buffer becomes Low-Z. (The latency of DQM, DQMU/DQML during  
reading is 2 clocks.)  
Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If  
DQM, DQMU/DQML is Low, the data is written. (The latency of DQM, DQMU/DQML during writing is 0  
clock.)  
DQ0 to DQ15 (DQ pins): Data is input to and output from these pins (DQ0 to DQ15; HM5264165F, DQ0  
to DQ7; HM5264805F, DQ0 to DQ3; HM5264405F).  
VCC and VCCQ (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the  
output buffer.)  
9
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the  
output buffer.)  
Command Operation  
Command Truth Table  
The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins.  
CKE  
A0  
CS RAS CAS WE A12/A13 A10 to A11  
Command  
Symbol  
DESL  
NOP  
n - 1 n  
Ignore command  
H
H
H
H
H
H
H
H
H
H
×
×
×
×
×
×
×
×
×
×
V
×
H
L
L
L
L
L
L
L
L
L
L
L
×
×
×
×
×
×
×
L
×
×
×
V
V
V
V
V
×
×
×
V
No operation  
H
H
H
H
H
H
L
H
H
L
H
L
×
Burst stop in full page  
Column address and read command  
Read with auto-precharge  
BST  
×
READ  
READ A  
H
H
L
V
V
V
V
V
V
×
L
H
L
Column address and write command WRIT  
L
Write with auto-precharge  
Row address strobe and bank active  
Precharge select bank  
Precharge all bank  
WRIT A  
L
L
H
V
L
ACTV  
PRE  
H
H
H
L
H
L
L
PALL  
L
L
H
×
V
Refresh  
REF/SELF H  
MRS  
L
H
L
×
Mode register set  
H
L
L
V
Note: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input  
Ignore command [DESL]: When this command is set (CS is High), the SDRAM ignore command input at  
the clock. However, the internal status is held.  
No operation [NOP]: This command is not an execution command. However, the internal operations  
continue.  
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page  
(256; HM5264165F, 512; HM5264805F, 1024; HM5264405F)), and is illegal otherwise. When data  
input/output is completed for a full page of data, it automatically returns to the start address, and input/output  
is performed repeatedly.  
10  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Column address strobe and read command [READ]: This command starts a read operation. In addition,  
the start address of burst read is determined by the column address (AY0 to AY7; HM5264165F, AY0 to  
AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (BS). After the read operation,  
the output buffer becomes High-Z.  
Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a  
burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.  
Column address strobe and write command [WRIT]: This command starts a write operation. When the  
burst write mode is selected, the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F,  
AY0 to AY9; HM5264405F) and the bank select address (A12/A13) become the burst write start address.  
When the single write mode is selected, data is only written to the location specified by the column address  
(AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select  
address (A12/A13).  
Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a  
burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page,  
this command is illegal.  
Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by  
A12/A13 (BS) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0 is  
activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank  
2 is activated. When A12 and A13 are High, bank 3 is activated.  
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by  
A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If  
A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.  
Precharge all banks [PALL]: This command starts a precharge operation for all banks.  
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation,  
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.  
Mode register set [MRS]: The SDRAM has a mode register that defines how it operates. The mode register  
is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode  
register configuration. After power on, the contents of the mode register are undefined, execute the mode  
register set command to set up the mode register.  
11  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
DQM Truth Table (HM5264165F)  
CKE  
Command  
Symbol  
ENBU  
n - 1  
H
n
×
×
×
×
DQMU  
DQML  
Upper byte write enable/output enable  
Lower byte write enable/output enable  
Upper byte write inhibit/output disable  
Lower byte write inhibit/output disable  
L
×
H
×
×
L
×
H
ENBL  
H
MASKU  
MASKL  
H
H
Note: H: VIH. L: VIL. ×: VIH or VIL.  
Write: IDID is needed.  
Read: IDOD is needed.  
DQM Truth Table (HM5264805F/HM5264405F)  
CKE  
Command  
Symbol  
n - 1  
H
n
×
×
DQM  
Write enable/output enable  
Write inhibit/output disable  
ENB  
L
MASK  
H
H
Note: H: VIH. L: VIL. ×: VIH or VIL.  
Write: IDID is needed.  
Read: IDOD is needed.  
The SDRAM can mask input/output data by means of DQM, DQMU/DQML.  
DQMU masks the upper byte and DQML masks the lower byte. (HM5264165F)  
During reading, the output buffer is set to Low-Z by setting DQM, DQMU/DQML to Low, enabling data  
output. On the other hand, when DQM, DQMU/DQML is set to High, the output buffer becomes High-Z,  
disabling data output.  
During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set  
to High, the previous data is held (the new data is not written). Desired data can be masked during burst read  
or burst write by setting DQMU/DQML. For details, refer to the DQM, DQMU/DQML control section of the  
SDRAM operating instructions.  
12  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
CKE Truth Table  
CKE  
Current state  
Command  
n - 1  
H
L
n
L
CS  
×
RAS CAS WE  
Address  
Active  
Clock suspend mode entry  
Clock suspend  
×
×
×
L
L
H
×
H
×
H
×
×
×
×
L
L
H
×
H
×
H
×
×
×
×
×
×
×
×
×
×
×
×
×
Any  
L
×
×
Clock suspend  
Clock suspend mode exit  
Auto-refresh command (REF)  
Self-refresh entry (SELF)  
Power down entry  
L
H
H
L
×
×
Idle  
Idle  
Idle  
H
H
H
H
L
L
H
H
H
×
L
L
L
L
H
L
Self refresh  
Power down  
Self refresh exit (SELFX)  
Power down exit  
H
H
H
H
H
×
L
H
L
L
H
×
L
H
Note: H: VIH. L: VIL. ×: VIH or VIL.  
Clock suspend mode entry: The SDRAM enters clock suspend mode from active mode by setting CKE to  
Low. When command is input during CKE is low, the command is valid. The clock suspend mode changes  
depending on the current status (1 clock before) as shown below.  
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining  
the bank active status.  
READ suspend and READ with Auto-precharge suspend: The data being output is held (and continues to  
be output).  
WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not  
accepted. However, the internal state is held.  
Clock suspend: During clock suspend mode, keep the CKE to Low.  
Clock suspend mode exit: The SDRAM exits from clock suspend mode by setting CKE to High during the  
clock suspend state.  
IDLE: In this state, all banks are not selected, and completed precharge operation.  
Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM starts auto-  
refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the  
auto-refresh operation, refresh address and bank select address are generated inside the SDRAM. For every  
auto-refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh  
the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In  
addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge  
command is required after auto-refresh.  
13  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts self-  
refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-  
refresh is performed internally and automatically, external refresh operations are unnecessary.  
Power down mode entry: When this command is executed during the IDLE state, the SDRAM enters power  
down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit.  
Self-refresh exit: When this command is executed during self-refresh mode, the SDRAM can exit from self-  
refresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state.  
Power down exit: When this command is executed at the power down mode, the SDRAM can exit from  
power down mode. After exiting from power down mode, the SDRAM enters the IDLE state.  
Function Truth Table  
The following table shows the operations that are performed when each command is issued in each mode of  
the SDRAM.  
The following table assumes that CKE is high.  
Current state  
CS  
H
L
RAS CAS WE  
Address  
Command  
DESL  
Operation  
Precharge  
×
×
×
×
×
×
Enter IDLE after tRP  
Enter IDLE after tRP  
NOP  
H
H
H
H
L
H
H
L
H
L
NOP  
L
BST  
L
H
L
BA, CA, A10 READ/READ A ILLEGAL*4  
L
L
BA, CA, A10 WRIT/WRIT A  
ILLEGAL*4  
ILLEGAL*4  
NOP*6  
L
H
H
L
H
L
BA, RA  
ACTV  
L
L
BA, A10  
PRE, PALL  
REF, SELF  
MRS  
L
L
H
L
×
ILLEGAL  
ILLEGAL  
NOP  
L
L
L
MODE  
Idle  
H
L
×
×
×
×
×
×
DESL  
H
H
H
H
L
H
H
L
H
L
NOP  
NOP  
L
BST  
NOP  
L
H
L
BA, CA, A10 READ/READ A ILLEGAL*5  
L
L
BA, CA, A10 WRIT/WRIT A  
ILLEGAL*5  
L
H
H
L
H
L
BA, RA  
BA, A10  
×
ACTV  
Bank and row active  
NOP  
L
L
PRE, PALL  
REF, SELF  
MRS  
L
L
H
L
Refresh  
L
L
L
MODE  
Mode register set  
14  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Current state  
CS  
H
L
RAS CAS WE  
Address  
Command  
DESL  
Operation  
NOP  
Row active  
×
×
×
×
×
×
H
H
H
H
L
H
H
L
H
L
NOP  
NOP  
L
BST  
NOP  
L
H
L
BA, CA, A10 READ/READ A Begin read  
L
L
BA, CA, A10 WRIT/WRIT A  
Begin write  
L
H
H
BA, RA  
ACTV  
Other bank active  
ILLEGAL on same bank*3  
L
L
L
H
L
L
L
L
H
L
L
BA, A10  
PRE, PALL  
REF, SELF  
MRS  
Precharge  
L
H
L
×
ILLEGAL  
L
L
MODE  
ILLEGAL  
Read  
×
×
×
×
×
×
DESL  
Continue burst to end  
Continue burst to end  
Burst stop to full page  
H
H
H
H
H
L
H
L
NOP  
BST  
H
BA, CA, A10 READ/READ A Continue burst read to CAS  
latency and New read  
L
L
H
L
L
L
BA, CA, A10 WRIT/WRIT A  
Term burst read/start write  
H
H
BA, RA  
ACTV  
Other bank active  
ILLEGAL on same bank*3  
L
L
H
L
BA, A10  
PRE, PALL  
Term burst read and  
Precharge  
L
L
H
L
L
×
L
L
×
H
L
×
REF, SELF  
MRS  
ILLEGAL  
ILLEGAL  
MODE  
Read with auto-  
precharge  
×
×
DESL  
Continue burst to end and  
precharge  
L
H
H
H
×
×
NOP  
BST  
Continue burst to end and  
precharge  
L
L
L
L
H
H
H
L
H
L
L
ILLEGAL  
H
L
BA, CA, A10 READ/READ A ILLEGAL*4  
L
BA, CA, A10 WRIT/WRIT A  
ILLEGAL*4  
H
H
BA, RA  
ACTV  
Other bank active  
ILLEGAL on same bank*3  
L
L
L
L
L
L
H
L
L
L
H
L
BA, A10  
×
PRE, PALL  
REF, SELF  
MRS  
ILLEGAL*4  
ILLEGAL  
ILLEGAL  
MODE  
15  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Current state  
CS  
H
L
RAS CAS WE  
Address  
Command  
DESL  
Operation  
Write  
×
×
×
×
×
×
Continue burst to end  
Continue burst to end  
Burst stop on full page  
H
H
H
H
L
H
H
L
H
L
NOP  
L
BST  
L
H
L
BA, CA, A10 READ/READ A Term burst and New read  
L
L
BA, CA, A10 WRIT/WRIT A  
Term burst and New write  
L
H
H
BA, RA  
ACTV  
Other bank active  
ILLEGAL on same bank*3  
L
L
H
L
BA, A10  
PRE, PALL  
Term burst write and  
Precharge*2  
L
L
H
L
L
×
L
L
×
H
L
×
REF, SELF  
MRS  
ILLEGAL  
ILLEGAL  
MODE  
Write with auto-  
precharge  
×
×
DESL  
Continue burst to end and  
precharge  
L
H
H
H
×
×
NOP  
BST  
Continue burst to end and  
precharge  
L
L
L
L
H
H
H
L
H
L
L
ILLEGAL  
H
L
BA, CA, A10 READ/READ A ILLEGAL*4  
L
BA, CA, A10 WRIT/WRIT A  
ILLEGAL*4  
H
H
BA, RA  
ACTV  
Other bank active  
ILLEGAL on same bank*3  
L
L
L
H
L
L
L
×
H
L
L
×
L
H
L
×
BA, A10  
PRE, PALL  
REF, SELF  
MRS  
ILLEGAL*4  
×
ILLEGAL  
MODE  
ILLEGAL  
Refresh (auto-  
refresh)  
×
DESL  
Enter IDLE after tRC  
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
×
×
NOP  
BST  
Enter IDLE after tRC  
Enter IDLE after tRC  
H
L
BA, CA, A10 READ/READ A ILLEGAL*5  
L
BA, CA, A10 WRIT/WRIT A  
ILLEGAL*5  
ILLEGAL*5  
ILLEGAL*5  
ILLEGAL  
H
H
L
H
L
BA, RA  
BA, A10  
×
ACTV  
L
PRE, PALL  
REF, SELF  
MRS  
L
H
L
L
L
MODE  
ILLEGAL  
Notes: 1. H: VIH. L: VIL. ×: VIH or VIL. The other combinations are inhibit.  
2. An interval of tDPL is required between the final valid data input and the precharge command.  
3. If tRRD is not satisfied, this operation is illegal.  
4. Illegal for same bank, except for another bank.  
5. Illegal for all banks.  
6. NOP for same bank, except for another bank.  
16  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
From PRECHARGE state, command operation  
To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM enters the IDLE state after  
tRP has elapsed from the completion of precharge.  
From IDLE state, command operation  
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.  
To [ACTV]: The bank specified by the address pins and the ROW address is activated.  
To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh).  
To [MRS]: The SDRAM enters the mode register set cycle.  
From ROW ACTIVE state, command operation  
To [DESL], [NOP] or [BST]: These commands result in no operation.  
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)  
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)  
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)  
Attempting to make the currently active bank active results in an illegal command.  
To [PRE], [PALL]: These commands set the SDRAM to precharge mode. (However, an interval of tRAS is  
required.)  
From READ state, command operation  
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.  
To [BST]: This command stops a full-page burst.  
To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS  
latency, the data output resulting from the next command will start.  
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.  
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)  
Attempting to make the currently active bank active results in an illegal command.  
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode.  
17  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
From READ with AUTO-PRECHARGE state, command operation  
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and  
the SDRAM then enters precharge mode.  
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)  
Attempting to make the currently active bank active results in an illegal command.  
From WRITE state, command operation  
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.  
To [BST]: This command stops a full-page burst.  
To [READ], [READ A]: These commands stop a burst and start a read cycle.  
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.  
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)  
Attempting to make the currently active bank active results in an illegal command.  
To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode.  
From WRITE with AUTO-PRECHARGE state, command operation  
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the  
synchronous DRAM enters precharge mode.  
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)  
Attempting to make the currently active bank active results in an illegal command.  
From REFRESH state, command operation  
To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the SDRAM automatically enters the  
IDLE state.  
18  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Simplified State Diagram  
SELF  
REFRESH  
SR ENTRY  
SR EXIT  
*1  
MRS  
REFRESH  
MODE  
REGISTER  
SET  
AUTO  
IDLE  
REFRESH  
CKE  
CKE_  
IDLE  
POWER  
DOWN  
ACTIVE  
ACTIVE  
CLOCK  
SUSPEND  
CKE_  
CKE  
ROW  
ACTIVE  
BST  
(on full page)  
BST  
(on full page)  
WRITE  
READ  
Write  
WRITE  
WITH  
AP  
READ  
WITH  
AP  
Read  
CKE_  
CKE_  
WRITE  
SUSPEND  
READ  
READ  
SUSPEND  
WRITE  
READ  
WRITE  
CKE  
CKE  
READ  
WITH AP  
WRITE  
WITH AP  
WRITE  
WITH AP  
READ  
WITH AP  
PRECHARGE  
CKE_  
CKE_  
WRITEA  
SUSPEND  
READA  
SUSPEND  
WRITEA  
READA  
CKE  
CKE  
PRECHARGE PRECHARGE  
POWER  
APPLIED  
POWER  
ON  
PRECHARGE  
PRECHARGE  
Automatic transition after completion of command.  
Transition resulting from command input.  
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and  
enter the IDLE state.  
19  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Mode Register Configuration  
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The  
mode register consists of five sections, each of which is assigned to address pins.  
A13, A12, A11, A10, A9, A8: (OPCODE): The SDRAM has two types of write modes. One is the burst  
write mode, and the other is the single write mode. These bits specify write mode.  
Burst read and burst write: Burst write is performed for the specified burst length starting from the column  
address specified in the write cycle.  
Burst read and single write: Data is only written to the column address specified during the write cycle,  
regardless of the burst length.  
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.  
A6, A5, A4: (LMODE): These pins specify the CAS latency.  
A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.  
A2, A1, A0: (BL): These pins specify the burst length.  
A12  
A11  
OPCODE  
A13  
A10  
A9  
A8  
A7  
0
A6  
A5  
A4  
A3  
BT  
A2  
A1  
BL  
A0  
LMODE  
A6 A5 A4 CAS latency  
A3 Burst type  
Burst length  
BT=0 BT=1  
A2 A1 A0  
R
R
2
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
0
1
Sequential  
Interleave  
1
2
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
4
R
8
8
R
R
R
R
R
R
A9 A8  
Write mode  
A10  
A13 A12  
A11  
R
0
0
1
1
0
1
0
1
Burst read and burst write  
0
X
X
X
0
X
X
X
0
X
X
X
0
X
X
X
F.P.  
R
Burst read and single write  
R
F.P. = Full Page  
R is Reserved (inhibit)  
X: 0 or 1  
20  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Burst Sequence  
Burst length = 2  
Starting Ad. Addressing(decimal)  
Burst length = 4  
Starting Ad. Addressing(decimal)  
A0  
0
Sequential Interleave  
A1  
0
A0 Sequential  
Interleave  
0, 1,  
1, 0,  
0, 1,  
1, 0,  
0
1
0
1
0, 1, 2, 3,  
1, 2, 3, 0,  
2, 3, 0, 1,  
0, 1, 2, 3,  
1, 0, 3, 2,  
2, 3, 0, 1,  
3, 2, 1, 0,  
1
0
1
1
3,  
0, 1, 2,  
Burst length = 8  
Starting Ad.  
Addressing(decimal)  
A2 A1 A0 Sequential  
Interleave  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0, 1, 2, 3, 4, 5, 6, 7,  
1, 2, 3, 4, 5, 6, 7, 0,  
2, 3, 4, 5, 6, 7, 0, 1,  
3, 4, 5, 6, 7, 0, 1, 2,  
4, 5, 6, 7, 0, 1, 2, 3,  
5, 6, 7, 0, 1, 2, 3, 4,  
6, 7, 0, 1, 2, 3, 4, 5,  
7, 0, 1, 2, 3, 4, 5, 6,  
0, 1, 2, 3, 4, 5, 6, 7,  
1, 0, 3, 2, 5, 4, 7, 6,  
2, 3, 0, 1, 6, 7, 4, 5,  
3, 2, 1, 0, 7, 6, 5, 4,  
4, 5, 6, 7, 0, 1, 2, 3,  
5, 4, 7, 6, 1, 0, 3, 2,  
6, 7, 4, 5, 2, 3, 0, 1,  
7, 6, 5, 4, 3, 2, 1, 0,  
21  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Operation of the SDRAM  
Read/Write Operations  
Bank active: Before executing a read or write operation, the corresponding bank and the row address must be  
activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to  
the status of the A12/A13 pin, and the row address (AX0 to AX11) is activated by the A0 to A11 pins at the  
bank active command cycle. An interval of tRCD is required between the bank active command input and the  
following read/write command input.  
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in  
the (CAS Latency - 1) cycle after read command set. HM5264165F, HM5264805F series, HM5264405F can  
perform a burst read operation.  
The burst length can be set to 1, 2, 4, 8 or full-page (256; HM5264165F, 512; HM5264805F, 1024;  
HM5264405F). The start address for a burst read is specified by the column address (AY0 to AY7;  
HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address  
(A12/A13) at the read command set cycle. In a read operation, data output starts after the number of clocks  
specified by the CAS Latency. The CAS Latency can be set to 2 or 3.  
When the burst length is 1, 2, 4, 8, the Dout buffer automatically becomes High-Z at the next clock after the  
successive burst-length data has been output.  
The CAS latency and burst length must be specified at the mode register.  
CAS Latency  
CLK  
t
RCD  
Command  
Address  
READ  
ACTV  
Row  
Column  
out 3  
out 1 out 2  
out 0  
out 1 out 2  
CL = 2  
CL = 3  
Dout  
out 3  
out 0  
CL = CAS latency  
Burst Length = 4  
22  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Burst Length  
CLK  
t
RCD  
Command  
Address  
ACTV  
Row  
READ  
Column  
out 0  
BL = 1  
out 0 out 1  
BL = 2  
BL = 4  
BL = 8  
out 3  
out 3  
out 3  
out 0 out 1 out 2  
out 0 out 1 out 2  
out 0 out 1 out 2  
Dout  
out 5 out 6 out 7  
out 4  
out 4  
out 0-1  
out 6 out 7 out 8  
out 0 out 1  
out 5  
BL = full page  
BL : Burst Length  
CAS Latency = 2  
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9,  
A8) of the mode register.  
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write  
starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can  
be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column  
address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the  
bank select address (A12/A13) at the write command set cycle.  
CLK  
t
RCD  
Command  
Address  
ACTV  
Row  
WRIT  
Column  
in 0  
in 0  
BL = 1  
in 1  
in 1  
in 1  
BL = 2  
BL = 4  
BL = 8  
in 3  
in 0  
in 0  
in 2  
in 2  
Din  
in 5  
in 5  
in 6 in 7  
in 6 in 7  
in 3 in 4  
in 4  
in 3  
in 8  
in 0  
in 1  
in 0 in 1 in 2  
in 0-1  
BL = full page  
CAS Latency = 2, 3  
23  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write  
operation, data is only written to the column address (AY0 to AY7; HM5264165F, AY0 to AY8;  
HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) specified by the write  
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).  
CLK  
t
RCD  
Command  
WRIT  
ACTV  
Row  
Column  
in 0  
Address  
Din  
Auto Precharge  
Read with auto-precharge: In this operation, since precharge is automatically performed after completing a  
read operation, a precharge command need not be executed after each read operation. The command executed  
for the same bank after the execution of this command must be the bank active (ACTV) command. In  
addition, an interval defined by lAPR is required before execution of the next command.  
CAS latency  
Precharge start cycle  
3
2
2 cycle before the final data is output  
1 cycle before the final data is output  
Burst Read (Burst Length = 4)  
CLK  
ACTV  
READ A  
ACTV  
CL=2 Command  
DQ (input)  
l
RAS  
out0  
out1  
out2  
out3  
l
APR  
CL=3 Command  
DQ (input)  
ACTV  
READ A  
ACTV  
l
RAS  
out0  
out1  
out2  
out3  
l
APR  
Note: Internal auto-precharge starts at the timing indicated by " ".  
And an interval of t (l ) is required between previous active (ACTV) command and internal precharge  
"
".  
RAS RAS  
24  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Write with auto-precharge: In this operation, since precharge is automatically performed after completing  
a burst write or single write operation, a precharge command need not be executed after each write operation.  
The command executed for the same bank after the execution of this command must be the bank active  
(ACTV) command. In addition, an interval of lAPW is required between the final valid data input and input of  
next command.  
Burst Write (Burst Length = 4)  
CLK  
WRIT A  
ACTV  
ACTV  
Command  
DQ (input)  
IRAS  
in0 in1 in2 in3  
lAPW  
Note: Internal auto-precharge starts at the timing indicated by " ".  
and an interval of tRAS (lRAS) is required between previous active (ACTV) command  
and internal precharge " ".  
Single Write  
CLK  
WRIT A  
ACTV  
ACTV  
Command  
IRAS  
DQ (input)  
in  
lAPW  
Note: Internal auto-precharge starts at the timing indicated by " ".  
and an interval of tRAS (lRAS) is required between previous active (ACTV) command  
and internal precharge " ".  
25  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Full-page Burst Stop  
Burst stop command during burst read: The burst stop (BST) command is used to stop data output during  
a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The  
timing from command input to the last data changes depending on the CAS latency setting. In addition, the  
BST command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8.  
CAS latency  
BST to valid data  
BST to high impedance  
2
3
1
2
2
3
CAS Latency = 2, Burst Length = full page  
CLK  
BST  
Command  
DQ (output)  
out  
out  
out  
out  
out  
out  
l
= 2 clocks  
BSH  
l
= 1 clock  
BSR  
CAS Latency = 3, Burst Length = full page  
CLK  
BST  
Command  
DQ (output)  
out  
out  
out  
out  
out  
l
out  
out  
l
= 3 clocks  
BSH  
= 2 clocks  
BSR  
26  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Burst stop command at burst write: The burst stop command (BST command) is used to stop data input  
during a full-page burst write. No data is written in the same clock as the BST command, and in subsequent  
clocks. In addition, the BST command is only valid during full-page burst mode, and is illegal with burst  
lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge  
command.  
Burst Length = full page  
CLK  
BST  
PRE/PALL  
Command  
DQ (input)  
in  
in  
t
DPL  
I
= 0 clock  
BSW  
27  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Command Intervals  
Read command to Read command interval:  
1. Same bank, same ROW address: When another read command is executed at the same ROW address  
of the same bank as the preceding read command execution, the second read can be performed after an  
interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data  
read by the second command will be valid.  
READ to READ Command Interval (same ROW address in same bank)  
CLK  
Command  
READ  
ACTV  
Row  
READ  
Column B  
Column A  
Address  
BS  
Dout  
out A0  
out B2 out B3  
out B0 out B1  
CAS Latency = 3  
Burst Length = 4  
Bank 0  
Column =B  
Dout  
Bank0  
Active  
Column =A Column =B Column =A  
Read Read Dout  
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read  
commands cannot be executed; it is necessary to separate the two read commands with a precharge command  
and a bank-active command.  
3. Different bank: When the bank changes, the second read can be performed after an interval of no less  
than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a burst  
read that is not yet finished, the data read by the second command will be valid.  
READ to READ Command Interval (different bank)  
CLK  
Command  
READ READ  
ACTV  
Row 0  
ACTV  
Column A  
Row 1  
Column B  
Address  
BS  
Dout  
out A0  
out B2 out B3  
out B0 out B1  
Bank3  
Dout  
Bank0  
Dout  
CAS Latency = 3  
Burst Length = 4  
Bank0  
Active  
Bank3 Bank0 Bank3  
Active Read Read  
28  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Write command to Write command interval:  
1. Same bank, same ROW address: When another write command is executed at the same ROW address  
of the same bank as the preceding write command, the second write can be performed after an interval of no  
less than 1 clock. In the case of burst writes, the second write command has priority.  
WRITE to WRITE Command Interval (same ROW address in same bank)  
CLK  
Command  
Address  
WRIT  
ACTV  
Row  
WRIT  
Column B  
Column A  
BS  
Din  
in A0  
in B2 in B3  
in B0 in B1  
Bank0  
Active  
Column =A Column =B  
Write Write  
Burst Write Mode  
Burst Length = 4  
Bank 0  
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands  
cannot be executed; it is necessary to separate the two write commands with a precharge command and a  
bank-active command.  
3. Different bank: When the bank changes, the second write can be performed after an interval of no less  
than 1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second  
write command has priority.  
WRITE to WRITE Command Interval (different bank)  
CLK  
Command  
Address  
ACTV  
Row 0  
ACTV  
WRIT WRIT  
Column A  
Column B  
Row 1  
BS  
Din  
in A0  
in B2 in B3  
in B0 in B1  
Burst Write Mode  
Burst Length = 4  
Bank0  
Active  
Bank3 Bank0 Bank3  
Active Write Write  
29  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Read command to Write command interval:  
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the  
same bank as the preceding read command, the write command can be performed after an interval of no less  
than 1 clock. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z  
before data input.  
READ to WRITE Command Interval (1)  
CLK  
Command  
READ WRIT  
DQM, CL=2  
DQMU  
/DQML  
CL=3  
in B0  
in B3  
in B1 in B2  
Din  
Burst Length = 4  
Burst write  
High-Z  
Dout  
READ to WRITE Command Interval (2)  
CLK  
Command  
READ  
WRIT  
DQM,  
DQMU/DQML  
2 clock  
High-Z  
High-Z  
CL=2  
Dout  
CL=3  
Din  
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands  
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-  
active command.  
3. Different bank: When the bank changes, the write command can be performed after an interval of no less  
than 1 clock, provided that the other bank is in the bank-active state. However, DQM, DQMU/DQML must  
be set High so that the output buffer becomes High-Z before data input.  
30  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Write command to Read command interval:  
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the  
same bank as the preceding write command, the read command can be performed after an interval of no less  
than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle before the  
read command is executed.  
WRITE to READ Command Interval (1)  
CLK  
Command  
WRIT  
in A0  
READ  
DQM,  
DQMU/DQML  
Din  
Dout  
out B0  
out B1  
out B2  
out B3  
Column = A  
Write  
Burst Write Mode  
CAS Latency = 2  
Burst Length = 4  
Bank 0  
CAS Latency  
Column = B  
Dout  
Column = B  
Read  
WRITE to READ Command Interval (2)  
CLK  
WRIT  
in A0  
READ  
Command  
DQM,  
DQMU/DQML  
Din  
in A1  
Dout  
out B0  
out B1  
out B2  
out B3  
Burst Write Mode  
CAS Latency = 2  
Burst Length = 4  
Bank 0  
Column = A  
Write  
CAS Latency  
Column = B  
Dout  
Column = B  
Read  
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands  
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-  
active command.  
3. Different bank: When the bank changes, the read command can be performed after an interval of no less  
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write,  
data will continue to be written until one clock before the read command is executed (as in the case of the  
same bank and the same address).  
31  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Read with auto precharge to Read command interval  
1. Different bank: When some banks are in the active state, the second read command (another bank) is  
executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by  
the second command is valid. The internal auto-precharge of one bank starts at the next clock of the second  
command.  
Read with Auto Precharge to Read Command Interval (Different bank)  
CLK  
Command  
BS  
READ A  
READ  
Dout  
out A0  
out A1  
out B0  
out B1  
bank0  
Read A  
bank3  
Read  
CAS Latency = 3  
Burst Length = 4  
Note: Internal auto-precharge starts at the timing indicated by "  
".  
2. Same bank: The consecutive read command (the same bank) is illegal.  
Write with auto precharge to Write command interval  
1. Different bank: When some banks are in the active state, the second write command (another bank) is  
executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of  
one bank starts at the next clock of the second command .  
Write with Auto Precharge to Write Command Interval (Different bank)  
CLK  
Command  
BS  
WRIT A  
in A0  
WRIT  
in B0  
Din  
in A1  
in B1  
in B2  
in B3  
bank0  
Write A  
bank3  
Write  
Burst Length = 4  
Note: Internal auto-precharge starts at the timing indicated by "  
".  
2. Same bank: The consecutive write command (the same bank) is illegal.  
32  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Read with auto precharge to Write command interval  
1. Different bank: When some banks are in the active state, the second write command (another bank) is  
executed. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before  
data input. The internal auto-precharge of one bank starts at the next clock of the second command.  
Read with Auto Precharge to Write Command Interval (Different bank)  
CLK  
Command  
BS  
READ A WRIT  
CL = 2  
CL = 3  
Din  
DQM,  
DQMU/DQML  
in B0  
in B1  
in B2  
in B3  
Dout  
High-Z  
Burst Length = 4  
bank0  
bank3  
Read A Write  
Note: Internal auto-precharge starts at the timing indicated by "  
".  
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It  
is necessary to separate the two commands with a bank active command.  
33  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Write with auto precharge to Read command interval  
1. Different bank: When some banks are in the active state, the second read command (another bank) is  
executed. However, in case of a burst write, data will continue to be written until one clock before the read  
command is executed. The internal auto-precharge of one bank starts at the next clock of the second  
command.  
Write with Auto Precharge to Read Command Interval (Different bank)  
CLK  
Command  
BS  
WRIT A  
in A0  
READ  
DQM,  
DQMU/DQML  
Din  
Dout  
out B0  
out B1  
out B2 out B3  
CAS Latency = 3  
Burst Length = 4  
bank0  
Write A  
bank3  
Read  
Note: Internal auto-precharge starts at the timing indicated by "  
".  
Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. . It is  
necessary to separate the two commands with a bank active command.  
34  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Read command to Precharge command interval (same bank):  
When the precharge command is executed for the same bank as the read command that preceded it, the  
minimum interval between the two commands is one clock. However, since the output buffer then becomes  
High-Z after the clocks defined by lHZP, there is a case of interruption toburst read data output will be  
interrupted, if the precharge command is input during burst read. To read all data by burst read, the clocks  
defined by lEP must be assured as an interval from the final data output to precharge command execution.  
READ to PRECHARGE Command Interval (same bank): To output all data  
CAS Latency = 2, Burst Length = 4  
CLK  
PRE/PALL  
out A2  
READ  
Command  
Dout  
out A0  
out A1  
out A3  
CL=2  
l
= -1 cycle  
EP  
CAS Latency = 3, Burst Length = 4  
CLK  
PRE/PALL  
out A1  
READ  
Command  
Dout  
out A0  
out A2  
out A3  
CL=3  
l
= -2 cycle  
EP  
35  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
READ to PRECHARGE Command Interval (same bank): To stop output data  
CAS Latency = 2, Burst Length = 1, 2, 4, 8, full page burst  
CLK  
PRE/PALL  
READ  
Command  
Dout  
High-Z  
out A0  
=2  
l
HZP  
CAS Latency = 3, Burst Length = 1, 2, 4, 8, full page burst  
CLK  
PRE/PALL  
READ  
Command  
Dout  
High-Z  
out A0  
l
=3  
HZP  
36  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Write command to Precharge command interval (same bank): When the precharge command is executed  
for the same bank as the write command that preceded it, the minimum interval between the two commands is  
1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of  
DQM, DQMU/DQML for assurance of the clock defined by tDPL  
.
WRITE to PRECHARGE Command Interval (same bank)  
Burst Length = 4 (To stop write operation)  
CLK  
PRE/PALL  
Command  
WRIT  
DQM,  
DQMU/DQML  
Din  
t
DPL  
CLK  
PRE/PALL  
WRIT  
Command  
DQM,  
DQMU/DQML  
Din  
in A0  
in A1  
t
DPL  
Burst Length = 4 (To write all data)  
CLK  
PRE/PALL  
Command  
WRIT  
in A0  
DQM,  
DQMU/DQML  
Din  
in A1  
in A2  
in A3  
t
DPL  
37  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Bank active command interval:  
1. Same bank: The interval between the two bank-active commands must be no less than tRC.  
2. In the case of different bank-active commands: The interval between the two bank-active commands  
must be no less than tRRD  
.
Bank Active to Bank Active for Same Bank  
CLK  
Command  
Address  
BS  
ACTV  
ROW  
ACTV  
ROW  
t
RC  
Bank 0  
Active  
Bank 0  
Active  
Bank Active to Bank Active for Different Bank  
CLK  
ACTV  
ACTV  
Command  
Address  
ROW:0  
ROW:1  
BS  
t
RRD  
Bank 0  
Active  
Bank 3  
Active  
38  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Mode register set to Bank-active command interval: The interval between setting the mode register and  
executing a bank-active command must be no less than lRSA  
.
CLK  
Command  
Address  
MRS  
ACTV  
CODE  
BS & ROW  
I
RSA  
Mode  
Bank  
Register Set Active  
39  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
DQM Control  
The DQM mask the DQ data.  
The DQMU and DQML mask the upper and lower bytes of the DQ data, respectively. The timing of  
DQMU/DQML is different during reading and writing.  
Reading: When data is read, the output buffer can be controlled by DQM, DQMU/DQML. By setting  
DQM, DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM,  
DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output.  
However, internal reading operations continue. The latency of DQM, DQMU/DQML during reading is 2  
clocks.  
Writing: Input data can be masked by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low,  
data can be written. In addition, when DQM, DQMU/DQML is set to High, the corresponding data is not  
written, and the previous data is held. The latency of DQM, DQMU/DQML during writing is 0 clock.  
Reading  
CLK  
DQM,  
DQMU/DQML  
High-Z  
DQ (output)  
out 0  
l
out 1  
out 3  
= 2 Latency  
DOD  
Writing  
CLK  
DQM,  
DQMU/DQML  
DQ (input)  
in 3  
in 0  
in 1  
l
= 0 Latency  
DID  
40  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Refresh  
Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the auto-  
refresh command updates the internal counter every time it is executed and determines the banks and the  
ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096  
cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes High-  
Z after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the  
auto-refresh, an additional precharge operation by the precharge command is not required.  
Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held  
Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-  
refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh  
to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.  
(1) Enter self-refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval to  
all refresh addresses are completed.  
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 µs after  
exiting from self-refresh mode.  
Others  
Power-down mode: The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In  
power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down  
mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the  
power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not  
performed.  
Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM  
enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal  
state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command  
input is enabled from the next clock. For details, refer to the "CKE Truth Table".  
Power-up sequence: The SDRAM should be gone on the following sequence with power up.  
The CLK, CKE, CS, DQM, DQMU/DQML and DQ pins keep low till power stabilizes.  
The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.  
The CKE and DQM, DQMU/DQML is driven to high between power stabilizes and the initialization  
sequence.  
This SDRAM has VCC clamp diodes for CLK, CKE, CS, DQM, DQMU/DQML and DQ pins. If these pins go  
high before power up, the large current flows from these pins to VCC through the diodes.  
Initialization sequence: When 200 µs or more has past after the above power-up sequence, all banks must  
be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands  
(REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by  
keeping DQM, DQMU/DQML and CKE to High, the output buffer becomes High-Z during Initialization  
sequence, to avoid DQ bus contention on memory system formed with a number of device.  
41  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Initialization sequence  
Power up sequence  
100 µs  
200 µs  
VCC, VCC  
Q
0 V  
CKE, DQM,  
DQMU/DQML  
Low  
Low  
Low  
CLK  
CS, DQ  
Power stabilize  
Absolute Maximum Ratings  
Parameter  
Symbol  
Value  
Unit  
Note  
Voltage on any pin relative to VSS  
VT  
–0.5 to VCC + 0.5  
V
1
(4.6 (max))  
Supply voltage relative to VSS  
Short circuit output current  
Power dissipation  
VCC  
–0.5 to +4.6  
50  
V
1
Iout  
PT  
mA  
W
1.0  
Operating temperature  
Storage temperature  
Topr  
Tstg  
0 to +70  
–55 to +125  
°C  
°C  
Note: 1. Respect to VSS.  
DC Operating Conditions (Ta = 0 to +70˚C)  
Parameter  
Symbol  
VCC, VCCQ  
VSS, VSSQ  
VIH  
Min  
3.0  
0
Max  
3.6  
Unit  
V
Notes  
Supply voltage  
1, 2  
3
0
V
Input high voltage  
Input low voltage  
2.0  
–0.3  
VCC + 0.3  
0.8  
V
1, 4  
1, 5  
VIL  
V
Notes: 1. All voltage referred to VSS.  
2. The supply voltage with all VCC and VCCQ pins must be on the same level.  
3. The supply voltage with all VSS and VSSQ pins must be on the same level.  
4. VIH (max) = VCC + 2.0 V for pulse width 3 ns at VCC.  
5. VIL (min) = VSS – 2.0 V for pulse width 3 ns at VSS.  
42  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
VIL/VIH Clamp  
This SDRAM has VIL and VIH clamp for CLK, CKE, CS, DQM and D/Q pins.  
Minimum VIL Clamp Current  
VIL (V)  
–2  
I (mA)  
–32  
–25  
–19  
–13  
–8  
–1.8  
–1.6  
–1.4  
–1.2  
–1  
–4  
–0.9  
–0.8  
–0.6  
–0.4  
–0.2  
0
–2  
–0.6  
0
0
0
0
0
–2  
–1.5  
–1  
–0.5  
0
–5  
–10  
–15  
–20  
–25  
–30  
–35  
VIL (V)  
43  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Minimum VIH Clamp Current  
VIH (V)  
I (mA)  
10  
8
VCC + 2  
VCC + 1.8  
VCC + 1.6  
VCC + 1.4  
VCC + 1.2  
VCC + 1  
5.5  
3.5  
1.5  
0.3  
0
VCC + 0.8  
VCC + 0.6  
VCC + 0.4  
VCC + 0.2  
VCC + 0  
0
0
0
0
10  
8
6
4
2
0
V
CC + 0  
VCC + 0.5  
VCC + 1  
VIH (V)  
VCC + 1.5  
VCC + 2  
44  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
IOL/IOH Characteristics  
Output Low Current (IOL)  
IOL  
IOL  
Vout (V)  
0
Min (mA)  
0
Max (mA)  
0
0.4  
27  
71  
0.65  
0.85  
1
41  
108  
134  
151  
188  
194  
203  
209  
212  
220  
223  
51  
58  
1.4  
70  
1.5  
72  
1.65  
1.8  
75  
77  
1.95  
3
77  
80  
3.45  
81  
250  
200  
150  
100  
min  
max  
50  
0
0
0.5  
1
1.5  
2
2.5  
3
3.5  
Vout (V)  
45  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Output High Current (IOH) (Ta = 0 to +70˚C, VCC, VCCQ = 3.0 V to 3.45 V, VSS, VSSQ = 0 V)  
IOH  
IOH  
Vout (V)  
3.45  
3.3  
3
Min (mA)  
Max (mA)  
–3  
–28  
0
–75  
2.6  
2.4  
2
–21  
–34  
–59  
–67  
–73  
–78  
–81  
–89  
–93  
–130  
–154  
–197  
–227  
–248  
–270  
–285  
–345  
–503  
1.8  
1.65  
1.5  
1.4  
1
0
0
0
0.5  
1
1.5  
2
2.5  
3
3.5  
–100  
–200  
–300  
min  
max  
–400  
–500  
–600  
Vout (V)  
46  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
DC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)  
(HM5264165F)  
HM5264165F  
-75  
-A60  
-B60  
Parameter  
Symbol Min Max Min Max Min Max Unit Test conditions  
Notes  
Operating current  
Burst length = 1  
1, 2, 3  
(CAS latency = 2)  
ICC1  
ICC1  
65  
65  
1.5  
65  
65  
1.5  
65  
65  
mA tRC = min  
(CAS latency = 3)  
mA  
Standby current in power down ICC2P  
1.5 mA CKE = VIL,  
CK = 12 ns  
6
t
Standby current in power down ICC2PS  
(input signal stable)  
1
1
1
mA CKE = VIL, tCK = ∞  
7
Standby current in non power ICC2N  
down  
10  
5
10  
5
10  
5
mA CKE, CS = VIH,  
4
t
CK = 12 ns  
Standby current in non power ICC2NS  
down (input signal stable)  
mA CKE = VIH, tCK = ∞  
9
Active standby current in power ICC3P  
down  
4
4
4
mA CKE = VIL,  
1, 2, 6  
2, 7  
1, 2, 4  
t
CK = 12 ns  
Active standby current in power ICC3PS  
down (input signal stable)  
3
3
3
mA CKE = VIL, tCK = ∞  
Active standby current in non ICC3N  
power down  
18  
12  
18  
12  
18  
12  
mA CKE, CS = VIH,  
t
CK = 12 ns  
Active standby current in non ICC3NS  
power down (input signal  
stable)  
mA CKE = VIH, tCK = 2, 9  
Burst operating current  
(CAS latency = 2)  
(CAS latency = 3)  
Refresh current  
ICC4  
ICC4  
ICC5  
ICC6  
65  
80  
110  
1
65  
65  
110  
1
65  
65  
mA tCK = min, BL = 4  
mA  
1, 2, 5  
110 mA tRC = min  
3
8
Self refresh current  
1
mA VIH VCC – 0.2 V  
VIL 0.2 V  
Self refresh current (L-version) ICC6  
0.4  
1
0.4  
1
0.4 mA  
Input leakage current  
Output leakage current  
ILI  
–1  
–1  
–1  
1
µA  
0 Vin VCC  
ILO  
–1.5 1.5 –1.5 1.5 –1.5 1.5 µA  
0 Vout VCC  
DQ = disable  
Output high voltage  
Output low voltage  
VOH  
VOL  
2.4  
2.4  
2.4  
V
V
IOH = –4 mA  
IOL = 4 mA  
0.4  
0.4  
0.4  
47  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
DC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)  
(HM5264805F)  
HM5264805F  
-75  
-A60  
-B60  
Parameter  
Symbol Min Max Min Max Min Max Unit Test conditions  
Notes  
Operating current  
Burst length = 1  
1, 2, 3  
(CAS latency = 2)  
ICC1  
ICC1  
60  
60  
1.5  
60  
60  
1.5  
60  
60  
mA tRC = min  
(CAS latency = 3)  
mA  
Standby current in power down ICC2P  
1.5 mA CKE = VIL,  
CK = 12 ns  
6
t
Standby current in power down ICC2PS  
(input signal stable)  
1
1
1
mA CKE = VIL, tCK = ∞  
7
Standby current in non power ICC2N  
down  
10  
5
10  
5
10  
5
mA CKE, CS = VIH,  
4
t
CK = 12 ns  
Standby current in non power ICC2NS  
down (input signal stable)  
mA CKE = VIH, tCK = ∞  
9
Active standby current in power ICC3P  
down  
4
4
4
mA CKE = VIL,  
1, 2, 6  
2, 7  
1, 2, 4  
t
CK = 12 ns  
Active standby current in power ICC3PS  
down (input signal stable)  
3
3
3
mA CKE = VIL, tCK = ∞  
Active standby current in non ICC3N  
power down  
18  
12  
18  
12  
18  
12  
mA CKE, CS = VIH,  
t
CK = 12 ns  
Active standby current in non ICC3NS  
power down (input signal  
stable)  
mA CKE = VIH, tCK = 2, 9  
Burst operating current  
(CAS latency = 2)  
(CAS latency = 3)  
Refresh current  
ICC4  
ICC4  
ICC5  
ICC6  
60  
75  
110  
1
60  
60  
110  
1
60  
60  
mA tCK = min, BL = 4  
mA  
1, 2, 5  
110 mA tRC = min  
3
8
Self refresh current  
1
mA VIH VCC – 0.2 V  
VIL 0.2 V  
Self refresh current (L-version) ICC6  
0.4  
1
0.4  
1
0.4 mA  
Input leakage current  
Output leakage current  
ILI  
–1  
–1  
–1  
1
µA  
0 Vin VCC  
ILO  
–1.5 1.5 –1.5 1.5 –1.5 1.5 µA  
0 Vout VCC  
DQ = disable  
Output high voltage  
Output low voltage  
VOH  
VOL  
2.4  
2.4  
2.4  
V
V
IOH = –4 mA  
IOL = 4 mA  
0.4  
0.4  
0.4  
48  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
DC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)  
(HM5264405F)  
HM5264405F  
-75  
-A60  
-B60  
Parameter  
Symbol Min Max Min Max Min Max Unit Test conditions  
Notes  
Operating current  
Burst length = 1  
1, 2, 3  
(CAS latency = 2)  
ICC1  
ICC1  
60  
60  
1.5  
60  
60  
1.5  
60  
60  
mA tRC = min  
(CAS latency = 3)  
mA  
Standby current in power down ICC2P  
1.5 mA CKE = VIL,  
CK = 12 ns  
6
t
Standby current in power down ICC2PS  
(input signal stable)  
1
1
1
mA CKE = VIL, tCK = ∞  
7
Standby current in non power ICC2N  
down  
10  
5
10  
5
10  
5
mA CKE, CS = VIH,  
4
t
CK = 12 ns  
Standby current in non power ICC2NS  
down (input signal stable)  
mA CKE = VIH, tCK = ∞  
9
Active standby current in power ICC3P  
down  
4
4
4
mA CKE = VIL,  
1, 2, 6  
2, 7  
1, 2, 4  
t
CK = 12 ns  
Active standby current in power ICC3PS  
down (input signal stable)  
3
3
3
mA CKE = VIL, tCK = ∞  
Active standby current in non ICC3N  
power down  
18  
12  
18  
12  
18  
12  
mA CKE, CS = VIH,  
t
CK = 12 ns  
Active standby current in non ICC3NS  
power down (input signal  
stable)  
mA CKE = VIH, tCK = 2, 9  
Burst operating current  
(CAS latency = 2)  
(CAS latency = 3)  
Refresh current  
ICC4  
ICC4  
ICC5  
ICC6  
55  
70  
110  
1
55  
55  
110  
1
55  
55  
mA tCK = min, BL = 4  
mA  
1, 2, 5  
110 mA tRC = min  
3
8
Self refresh current  
1
mA VIH VCC – 0.2 V  
VIL 0.2 V  
Self refresh current (L-version) ICC6  
0.4  
1
0.4  
1
0.4 mA  
Input leakage current  
Output leakage current  
ILI  
–1  
–1  
–1  
1
µA  
0 Vin VCC  
ILO  
–1.5 1.5 –1.5 1.5 –1.5 1.5 µA  
0 Vout VCC  
DQ = disable  
Output high voltage  
Output low voltage  
VOH  
VOL  
2.4  
2.4  
2.4  
V
V
IOH = –4 mA  
IOL = 4 mA  
0.4  
0.4  
0.4  
49  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the  
output open condition.  
2. One bank operation.  
3. Input signals are changed once per one clock.  
4. Input signals are changed once per two clocks.  
5. Input signals are changed once per four clocks.  
6. After power down mode, CLK operating current.  
7. After power down mode, no CLK operating current.  
8. After self refresh mode set, self refresh current.  
9. Input signals are VIH or VIL fixed.  
Capacitance (Ta = 25°C, VCC, VCCQ = 3.3 V ± 0.3 V)  
Parameter  
Symbol  
CI1  
Min  
2.5  
2.5  
4
Max  
3.5  
3.8  
6.5  
Unit  
pF  
Notes  
Input capacitance (CLK)  
Input capacitance (Input)  
Output capacitance (DQ)  
1, 2, 4  
1, 2, 4  
1, 2, 3, 4  
CI2  
pF  
CO  
pF  
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.  
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.  
3. DQM, DQMU/DQML = VIH to disable Dout.  
4. This parameter is sampled and not 100% tested.  
50  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
AC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)  
HM5264165F/HM5264805F/HM5264405F  
-75  
-A60  
-B60  
HITACHI PC/100  
Symbol Symbol Min Max  
Parameter  
Min Max  
Min Max  
Unit Notes  
System clock cycle time  
(CAS latency = 2)  
tCK  
Tclk  
Tclk  
Tch  
Tcl  
10  
10  
10  
3
15  
10  
3
ns  
ns  
ns  
ns  
1
(CAS latency = 3)  
CLK high pulse width  
CLK low pulse width  
tCK  
7.5  
2.5  
2.5  
tCKH  
tCKL  
1
1
3
3
Access time from CLK  
(CAS latency = 2)  
tAC  
tAC  
tOH  
Tac  
Tac  
Toh  
2.7  
2
6
3
6
3
8
ns  
ns  
ns  
ns  
ns  
1, 2  
(CAS latency = 3)  
5.4  
5.4  
6
6
Data-out hold time  
6
6
1, 2  
CLK to Data-out low impedance tLZ  
2
2
1, 2, 3  
1, 4  
CLK to Data-out high  
impedance  
tHZ  
(CAS latency = 2, 3)  
Input setup time  
tAS, tCS, Tsi  
tDS, tCES  
1.5  
1.5  
0.8  
2
2
ns  
ns  
ns  
ns  
1, 5, 6  
CKE setup time for power down tCESP  
exit  
Tpde  
2
2
1
Input hold time  
tAH, tCH, Thi  
tDH, tCEH  
1
1
1, 5  
1
Ref/Active to Ref/Active  
command period  
tRC  
Trc  
67.5 —  
70  
70  
Active to Precharge command tRAS  
period  
Tras  
Trcd  
Trp  
45  
20  
20  
10  
15  
120000 50  
120000 50  
120000 ns  
1
Active command to column  
command (same bank)  
tRCD  
20  
20  
10  
20  
20  
20  
10  
20  
ns  
ns  
ns  
ns  
1
Precharge to active command tRP  
period  
1
Write recovery or data-in to  
precharge lead time  
tDPL  
Tdpl  
Trrd  
1
Active (a) to Active (b)  
command period  
tRRD  
1
Transition time (rise and fall)  
Refresh period  
tT  
1
5
1
5
1
5
ns  
tREF  
64  
64  
64  
ms  
51  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.5 V.  
2. Access time is measured at 1.5 V. Load condition is CL = 50 pF.  
3. tLZ (min) defines the time at which the outputs achieves the low impedance state.  
4. tHZ (max) defines the time at which the outputs achieves the high impedance state.  
5. tCES define CKE setup time to CLK rising edge except power down exit command.  
6. tAS/tAH: Address, tCS/tCH: CS, RAS, CAS, WE, DQM, DQMU/DQML  
tDS/tDH: Data-in, tCES/tCEH: CKE  
Test Conditions  
Input and output timing reference levels: 1.5 V  
Input waveform and output load: See following figures  
2.4 V  
I/O  
2.0 V  
input  
0.8 V  
0.4 V  
CL  
t
t
T
T
52  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Relationship Between Frequency and Minimum Latency  
HM5264165F/  
HM5264805F/  
HM5264405F  
Parameter  
-75  
-A60/B60  
Frequency (MHz)  
133  
100  
HITACHI  
Symbol  
PC/100  
Symbol  
tCK (ns)  
7.5  
10  
Notes  
Active command to column command  
(same bank)  
lRCD  
lRC  
lRAS  
lRP  
lDPL  
lRRD  
3
2
1
Active command to active command  
(same bank)  
9
6
3
2
2
7
5
2
1
2
= [lRAS+ lRP]  
1
Active command to precharge command  
(same bank)  
1
1
1
1
Precharge command to active command  
(same bank)  
Write recovery or data-in to precharge  
command (same bank)  
Tdpl  
Active command to active command  
(different bank)  
Self refresh exit time  
lSREX  
lAPW  
Tsrx  
Tdal  
1
5
1
3
2
Last data in to active command  
(Auto precharge, same bank)  
= [lDPL + lRP]  
Self refresh exit to command input  
lSEC  
9
7
= [lRC]  
3
Precharge command to high impedance  
(CAS latency = 2)  
lHZP  
lHZP  
lAPR  
Troh  
Troh  
2
3
1
2
3
1
(CAS latency = 3)  
Last data out to active command  
(Auto precharge, same bank)  
Last data out to precharge (early precharge)  
(CAS latency = 2)  
lEP  
–1  
–2  
1
–1  
–2  
1
(CAS latency = 3)  
lEP  
Column command to column command  
Write command to data in latency  
DQM to data in  
lCCD  
lWCD  
lDID  
lDOD  
lCLE  
lRSA  
Tccd  
Tdwd  
Tdqm  
Tdqz  
Tcke  
Tmrd  
0
0
0
0
DQM to data out  
2
2
CKE to CLK disable  
1
1
Register set to active command  
1
1
53  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
HM5264165F/  
HM5264805F/  
HM5264405F  
Parameter  
-75  
-A60/B60  
Frequency (MHz)  
133  
100  
HITACHI  
Symbol  
PC/100  
Symbol  
tCK (ns)  
7.5  
0
10  
0
Notes  
CS to command disable  
Power down exit to command input  
lCDD  
lPEC  
1
1
Burst stop to output valid data hold  
(CAS latency = 2)  
lBSR  
lBSR  
1
2
1
2
(CAS latency = 3)  
Burst stop to output high impedance  
(CAS latency = 2)  
lBSH  
lBSH  
lBSW  
2
3
0
2
3
0
(CAS latency = 3)  
Burst stop to write data ignore  
Notes: 1. lRCD to lRRD are recommended value.  
2. Be valid [DESL] or [NOP] at next command of self refresh exit.  
3. Except [DESL] and [NOP].  
54  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Timing Waveforms  
Read Cycle  
t
CK  
t
t
CKH CKL  
CLK  
CKE  
t
RC  
V
IH  
t
t
RAS  
RP  
t
RCD  
t
t
t
t
t
t
t
t
t
CH  
CH  
CH  
CH  
t
CS  
CS  
CS  
CS  
CH  
CS  
CS  
t
t
t
t
t
t
t
t
t
t
t
t
CH  
CH  
CH  
CH  
CH  
CH  
CS  
CS  
CS  
CS  
CS  
CS  
RAS  
t
t
t
t
CH  
CH  
CS  
CS  
CAS  
t
t
t
t
CH  
CS  
CH  
CS  
t
t
CH  
CS  
WE  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AH  
AH  
AH  
AH  
AH  
AH  
AH  
AS  
AS  
AS  
AS  
AS  
AS  
AS  
BS  
t
t
t
t
AH  
AH  
AS  
AS  
A10  
t
t
t
t
AH  
AS  
AH  
AS  
Address  
t
t
CH  
CS  
DQM,  
DQMU/DQML  
DQ (input)  
t
t
t
t
AC  
AC  
AC  
HZ  
DQ (output)  
t
AC  
t
OH  
t
t
t
CAS latency = 2  
OH  
OH  
OH  
t
LZ  
Burst length = 4  
Bank 0 access  
= V or V  
Bank 0  
Read  
Bank 0  
Active  
Bank 0  
Precharge  
IH  
IL  
55  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Write Cycle  
t
CK  
t
t
CKH CKL  
CLK  
CKE  
t
RC  
V
IH  
t
t
RAS  
RP  
t
RCD  
t
t
t
t
t
t
CH  
CH  
CH  
CS  
CS  
CS  
t
t
t
t
t
t
t
t
CH  
CH  
CH  
CH  
CS  
CS  
CS  
CS  
CS  
t
t
t
t
CH  
CH  
CS  
CS  
RAS  
t
t
t
t
t
t
CH  
CH  
CH  
CS  
CS  
CS  
t
t
CH  
CS  
CAS  
WE  
t
t
CH  
CS  
t
t
t
t
t
t
t
t
CH  
AH  
CH  
AH  
CS  
AS  
CS  
AS  
t
t
t
t
t
t
t
t
AH  
AH  
AH  
AH  
AS  
AS  
AS  
AS  
BS  
t
t
t
t
t
t
AH  
AH  
AH  
AS  
AS  
AS  
A10  
t
t
t
t
AH  
AH  
AS  
AS  
Address  
t
t
t
CH  
CS  
DQM,  
DQMU/DQML  
t
t
DH  
t
DS  
DH  
t
t
t
DS  
t
DH  
DS  
DH  
DS  
DQ (input)  
t
DPL  
DQ (output)  
Bank 0  
Precharge  
Bank 0  
Write  
CAS latency = 2  
Burst length = 4  
Bank 0 access  
Bank 0  
Active  
= V or V  
IH  
IL  
56  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Mode Register Set Cycle  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
CLK  
V
IH  
CKE  
CS  
RAS  
CAS  
WE  
BS  
code  
C: b’  
Address  
valid  
C: b  
R: b  
DQM,  
DQMU/DQML  
b+3  
b’+1 b’+2 b’+3  
b’  
DQ (output)  
b
High-Z  
DQ (input)  
l
RSA  
l
l
RCD  
RP  
Output mask  
l
= 3  
RCD  
Precharge  
If needed  
Mode  
register  
Set  
Bank 3  
Active  
Bank 3  
Read  
CAS latency = 3  
Burst length = 4  
= V or V  
IH  
IL  
Read Cycle/Write Cycle  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20  
CLK  
CKE  
V
IH  
Read cycle  
RAS-CAS delay = 3  
CAS latency = 3  
Burst length = 4  
CS  
RAS  
= V or V  
IH  
IL  
CAS  
WE  
BS  
Address  
DQM,  
DQMU/DQML  
R:a  
C:a  
R:b  
C:b  
C:b'  
C:b"  
DQ (output)  
DQ (input)  
a
a+1 a+2 a+3  
b
b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3  
High-Z  
Bank 0  
Active  
Bank 0  
Read  
Bank 3  
Active  
Bank 3 Bank 0  
Bank 3  
Read  
Bank 3  
Read  
Bank 3  
Precharge  
Read  
Precharge  
V
IH  
CKE  
Write cycle  
RAS-CAS delay = 3  
CAS latency = 3  
Burst length = 4  
CS  
RAS  
= V or V  
IH  
IL  
CAS  
WE  
BS  
Address  
DQM,  
DQMU/DQML  
R:a  
C:a  
a
R:b  
C:b  
C:b'  
C:b"  
High-Z  
DQ (output)  
DQ (input)  
a+1 a+2 a+3  
b
b+1 b+2 b+3 b'  
b'+1 b" b"+1b"+2 b"+3  
Bank 0  
Active  
Bank 0  
Write  
Bank 3  
Active  
Bank 3  
Write  
Bank 0  
Precharge  
Bank 3  
Write  
Bank 3  
Write  
Bank 3  
Precharge  
57  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Read/Single Write Cycle  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20  
CLK  
CKE  
V
IH  
CS  
RAS  
CAS  
WE  
BS  
R:a  
C:a  
R:b  
C:a' C:a  
a
Address  
DQM,  
DQMU/DQML  
DQ (input)  
DQ (output)  
a
a+1 a+2 a+3  
a
a+1 a+2 a+3  
Bank 0  
Active  
Bank 0  
Read  
Bank 3  
Active  
Bank 0 Bank 0  
Write Read  
Bank 0  
Precharge  
Bank 3  
Precharge  
V
IH  
CKE  
CS  
RAS  
CAS  
WE  
BS  
R:a  
C:a  
R:b  
C:a  
C:b C:c  
Address  
DQM,  
DQMU/DQML  
a
b
c
DQ (input)  
DQ (output)  
a
a+1  
a+3  
Bank 0  
Active  
Bank 0  
Read  
Bank 0  
Write  
Bank 0 Bank 0  
Write Write  
Bank 0  
Precharge  
Bank 3  
Active  
Read/Single write  
RAS-CAS delay = 3  
CAS latency = 3  
Burst length = 4  
= V or V  
IH  
IL  
58  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Read/Burst Write Cycle  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
BS  
Address  
R:a  
C:a  
R:b  
C:a'  
DQM,  
DQMU/DQML  
a
a+1 a+2 a+3  
DQ (input)  
DQ (output)  
a
a+1 a+2 a+3  
Bank 0  
Active  
Bank 0  
Read  
Bank 3  
Active  
Clock  
suspend  
Bank 0  
Precharge  
Bank 3  
Precharge  
Bank 0  
Write  
V
CKE  
IH  
CS  
RAS  
CAS  
WE  
BS  
R:a  
C:a  
R:b  
C:a  
a
Address  
DQM,  
DQMU/DQML  
a+1 a+2 a+3  
DQ (input)  
DQ (output)  
a
a+1  
a+3  
Bank 0  
Active  
Bank 0  
Read  
Bank 0  
Write  
Bank 0  
Precharge  
Bank 3  
Active  
Read/Burst write  
RAS-CAS delay = 3  
CAS latency = 3  
Burst length = 4  
= V or V  
IH  
IL  
59  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Full Page Read/Write Cycle  
CLK  
V
IH  
CKE  
Read cycle  
RAS-CAS delay = 3  
CAS latency = 3  
Burst length = full page  
CS  
RAS  
= V or V  
IH  
IL  
CAS  
WE  
BS  
R:a  
C:a  
R:b  
Address  
DQM,  
DQMU/DQML  
DQ (output)  
a
a+1  
a+2 a+3  
High-Z  
DQ (input)  
Bank 0  
Active  
Bank 0  
Read  
Bank 3  
Active  
Bank 3  
Precharge  
Burst stop  
V
CKE  
IH  
Write cycle  
RAS-CAS delay = 3  
CAS latency = 3  
CS  
Burst length = full page  
RAS  
= V or V  
IH  
IL  
CAS  
WE  
BS  
R:a  
C:a  
R:b  
Address  
DQM,  
DQMU/DQML  
DQ (output)  
High-Z  
DQ (input)  
a
a+1  
a+2 a+3  
Bank 3  
a+4  
a+5 a+6  
Bank 0  
Active  
Bank 0  
Write  
Burst stop  
Bank 3  
Precharge  
Active  
60  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Auto Refresh Cycle  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
CLK  
CKE  
V
IH  
CS  
RAS  
CAS  
WE  
BS  
Address  
C:a  
A10=1  
R:a  
DQM,  
DQMU/DQML  
DQ (input)  
a
a+1  
High-Z  
DQ (output)  
t
t
RC  
t
RP  
RC  
Refresh cycle and  
Read cycle  
Active  
Bank 0  
Read  
Bank 0  
Auto Refresh  
Precharge  
If needed  
Auto Refresh  
RAS-CAS delay = 2  
CAS latency = 2  
Burst length = 4  
= V or V  
IH  
IL  
Self Refresh Cycle  
CLK  
CKE  
CS  
l
SREX  
CKE Low  
RAS  
CAS  
WE  
BS  
Address  
A10=1  
DQM,  
DQMU/DQML  
DQ (input)  
High-Z  
DQ (output)  
t
t
RP  
t
RC  
RC  
Self refresh cycle  
RAS-CAS delay = 3  
CAS latency = 3  
Burst length = 4  
Auto  
refresh  
Self refresh entry  
command  
Precharge command  
If needed  
Next  
Self refresh exit  
ignore command  
or No operation  
Next  
Self refresh entry  
command  
clock  
clock  
enable  
enable  
= V or V  
IH  
IL  
61  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Clock Suspend Mode  
t
t
CES  
t
CES  
CEH  
8
0
1
2
3
4
5
6
7
9
10 11 12 13 14 15 16 17 18 19 20  
CLK  
CKE  
Read cycle  
RAS-CAS delay = 2  
CAS latency = 2  
Burst length = 4  
CS  
RAS  
= V or V  
IH  
IL  
CAS  
WE  
BS  
Address  
R:a  
C:a  
R:b  
C:b  
DQM,  
DQMU/DQML  
DQ (output)  
DQ (input)  
a
a+1 a+2  
a+3  
b
b+1 b+2 b+3  
High-Z  
Bank0 Active clock  
Active suspend start  
Active clock Bank0  
suspend end Read  
Bank3 Read suspend Read suspend  
Bank0  
Earliest Bank3  
Precharge  
Bank3  
Active  
start  
end Read Precharge  
CKE  
Write cycle  
RAS-CAS delay = 2  
CAS latency = 2  
Burst length = 4  
CS  
RAS  
= V or V  
IH  
IL  
CAS  
WE  
BS  
R:b  
a+1  
Address  
DQM,  
DQMU/DQML  
DQ (output)  
DQ (input)  
R:a  
C:a  
a
C:b  
High-Z  
a+2  
a+3  
b
b+1 b+2 b+3  
Bank0  
Active clock Bank0 Bank3 Write suspend Write suspend Bank3  
Earliest Bank3  
Precharge  
Bank0 Active clock  
Active suspend start  
Precharge  
end Write  
supend end Write Active  
start  
62  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Power Down Mode  
CLK  
CKE  
CS  
CKE Low  
RAS  
CAS  
WE  
BS  
Address  
A10=1  
R: a  
DQM,  
DQMU/DQML  
DQ (input)  
High-Z  
DQ (output)  
t
RP  
Power down cycle  
RAS-CAS delay = 3  
CAS latency = 3  
Burst length = 4  
Power down entry  
Power down  
mode exit  
Active Bank 0  
Precharge command  
If needed  
= V or V  
IH  
IL  
Initialization Sequence  
53  
52  
0
1
2
3
4
5
6
7
8
9
10  
48  
49  
50  
51  
54  
55  
CLK  
V
IH  
CKE  
CS  
RAS  
CAS  
WE  
code  
valid  
Address  
Valid  
DQM,  
DQMU/DQML  
V
IH  
High-Z  
DQ  
t
RP  
t
t
RC  
t
RC  
RSA  
Bank active  
If needed  
All banks  
Precharge  
Mode register  
Set  
Auto Refresh  
Auto Refresh  
63  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Package Dimensions  
HM5264165FTT/FLTT  
HM5264805FTT/FLTT  
HM5264405FTT/FLTT Series (TTP-54D)  
Unit: mm  
22.22  
22.72 Max  
54  
28  
27  
1
0.80  
0.13  
+0.10  
*0.30  
–0.05  
M
0.28 ± 0.05  
0.80  
11.76 ± 0.20  
0.91 Max  
0° – 5°  
0.50 ± 0.10  
0.10  
Hitachi Code  
TTP-54D  
JEDEC  
EIAJ  
*Dimension including the plating thickness  
Base material dimension  
Weight (reference value) 0.53 g  
64  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Cautions  
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,  
copyright, trademark, or other intellectual property rights for information contained in this document.  
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual  
property rights, in connection with use of the information contained in this document.  
2. Products and product specifications may be subject to change without notice. Confirm that you have  
received the latest product standards or specifications before final design, purchase or use.  
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,  
contact Hitachi’s sales office before using the product in an application that demands especially high  
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of  
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,  
safety equipment or medical equipment for life support.  
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for  
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and  
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the  
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or  
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the  
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage  
due to operation of the Hitachi product.  
5. This product is not designed to be radiation resistant.  
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without  
written approval from Hitachi.  
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor  
products.  
Hitachi, Ltd.  
Semiconductor & Integrated Circuits.  
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan  
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109  
URL  
NorthAmerica  
Europe  
: http:semiconductor.hitachi.com/  
: http://www.hitachi-eu.com/hel/ecg  
Asia (Singapore)  
Asia (Taiwan)  
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm  
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm  
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm  
Japan  
: http://www.hitachi.co.jp/Sicd/indx.htm  
For further information write to:  
Hitachi Semiconductor  
(America) Inc.  
Hitachi Europe GmbH  
Hitachi Asia (Hong Kong) Ltd.  
Group III (Electronic Components)  
7/F., North Tower, World Finance Centre,  
Harbour City, Canton Road, Tsim Sha Tsui,  
Kowloon, Hong Kong  
Tel: <852> (2) 735 9218  
Fax: <852> (2) 730 0281  
Hitachi Asia Pte. Ltd.  
16 Collyer Quay #20-00  
Hitachi Tower  
Singapore 049318  
Tel: 535-2100  
Electronic components Group  
Dornacher Straße 3  
D-85622 Feldkirchen, Munich  
Germany  
Tel: <49> (89) 9 9180-0  
Fax: <49> (89) 9 29 30 00  
179 East Tasman Drive,  
San Jose,CA 95134  
Tel: <1> (408) 433-1990  
Fax: <1>(408) 433-0223  
Fax: 535-1533  
Hitachi Asia Ltd.  
Taipei Branch Office  
3F, Hung Kuo Building. No.167,  
Tun-Hwa North Road, Taipei (105)  
Tel: <886> (2) 2718-3666  
Fax: <886> (2) 2718-8180  
Telex: 40815 HITEC HX  
Hitachi Europe Ltd.  
Electronic Components Group.  
Whitebrook Park  
Lower Cookham Road  
Maidenhead  
Berkshire SL6 8YA, United Kingdom  
Tel: <44> (1628) 585000  
Fax: <44> (1628) 778322  
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.  
65  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Revision Record  
Rev. Date  
Contents of Modification  
Drawn by  
Approved by  
0.0 Jul. 17, 1998 Initial issue  
M. Takahashi J. Kitano  
K. Nishimoto J. Kitano  
0.1 Dec. 28, 1998 Addition of HM5264165/HM5264805/  
HM5264405FTT/FLTT-75 (133MHz)  
Unification with HM5264165/HM5264805/  
HM5264405FTT/FLTT-B6  
Change of part number to HM5264165/HM5264805/  
HM5264405F-75/A60/B60  
Change figure of mode register configuration  
DC Operating conditions  
Change of notes 4 to 5  
DC Characteristics (Common)  
ICC2N max: —/20/— mA to 16/16/16 mA  
I
CC3P max: —/TBD/— mA to 4/4/4 mA  
ICC3PS max: —/TBD/— mA to 3/3/3 mA  
ICC3N max: —/30/— mA to 20/20/20 mA  
I
I
I
CC3NS max: —/20/— mA to 15/15/15 mA  
CC5 max: —/140/— mA to 115/115/115 mA  
CC6 max: —/TBD/— mA to 0.4/0.4/0.4 mA  
DC Characteristics (HM5264165F)  
ICC1 max(CL = 2): —/100/— mA to 85/75/70 mA  
I
I
I
CC1 max(CL = 3): —/100/— mA to 85/75/75 mA  
CC4 max (CL = 2): —/120/— mA to 90/90/70 mA  
CC4 max (CL = 3): —/120/— mA to 110/90/90 mA  
DC Characteristics (HM5264805F)  
ICC1 max(CL = 2): —/90/— mA to 80/70/65 mA  
I
I
I
CC1 max(CL = 3): —/90/— mA to 80/70/70 mA  
CC4 max (CL = 2): —/100/— mA to 80/80/65 mA  
CC4 max (CL = 3): —/100/— mA to 100/80/80 mA  
DC Characteristics (HM5264405F)  
ICC1 max(CL = 2): —/90/— mA to 80/70/65 mA  
I
I
I
CC1 max(CL = 3): —/90/— mA to 80/70/70 mA  
CC4 max (CL = 2): —/90/— mA to 70/70/60 mA  
CC4 max (CL = 3): —/90/— mA to 90/70/70 mA  
AC Characteristics  
tDPL min: —/15/— ns to 10/10/10 ns  
Relationship between frequency and minimum latency  
lDPL: —/2 to 2/1  
l
HZP (CL = 2): —/— to 2/2  
lEP (CL = 2): —/— to –1/–1  
l
l
BSR (CL = 2): —/— to 1/1  
BSH (CL = 2): —/— to 2/2  
66  
HM5264165F/HM5264805F/HM5264405F-75/A60/B60  
Revision Record (cont.)  
Rev. Date  
Contents of Modification  
Drawn by  
Approved by  
1.0 Nov. 10, 1999 Ordering information  
Addition of notes 1 and 2  
CKE Truth table  
Clock suspend mode entry  
CS: H to ×  
Addition of description to clock suspend mode entry  
DC Characteristics (common)  
I
CC2P max: 3/3/3 mA to 1.5/1.5/1.5 mA  
ICC2PS max: 2/2/2 mA to 1/1/1 mA  
ICC2N max: 16/16/16 mA to 10/10/10 mA  
I
CC2NS max: 9/9/9 mA to 5/5/5 mA  
ICC3N max: 20/20/20 mA to 18/18/18 mA  
I
I
CC3NS max: 15/15/15 mA to 12/12/12 mA  
CC5 max:115/115/115 mA to 110/110/110 mA  
DC Characteristics (HM5264165F)  
ICC1 max (CL = 2): 85/75/70 mA to 65/65/65 mA  
I
I
I
CC1 max (CL = 3): 85/75/75 mA to 65/65/65 mA  
CC4 max (CL = 2): 90/90/70 mA to 65/65/65 mA  
CC4 max (CL = 3): 110/90/90 mA to 80/65/65 mA  
DC Characteristics (HM5264805F)  
ICC1 max (CL = 2): 80/70/65 mA to 60/60/60 mA  
I
I
I
CC1 max (CL = 3): 80/70/70 mA to 60/60/60 mA  
CC4 max (CL = 2): 80/80/65 mA to 60/60/60 mA  
CC4 max (CL = 3): 100/80/80 mA to 75/60/60 mA  
DC Characteristics (HM5264405F)  
ICC1 max (CL = 2): 80/70/65 mA to 60/60/60 mA  
I
I
I
CC1 max (CL = 3): 80/70/70 mA to 60/60/60 mA  
CC4 max (CL = 2): 70/70/60 mA to 55/55/55 mA  
CC4 max (CL = 3): 90/70/70 mA to 70/55/55 mA  
Capacitance  
CI1 max: 4 pF to 3.5 pF  
CI2 max: 5 pF to 3.8 pF  
Relationship Between Frequency and Minimum Latency  
lAPW (-A60/B60): 4 to 3  
67  

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