HM62W16255HCLTT-10 [HITACHI]
4M High Speed SRAM (256-kword x 16-bit); 4M高速SRAM （ 256千字×16位）
| 型号： | HM62W16255HCLTT-10 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 4M High Speed SRAM (256-kword x 16-bit) |
| 文件： | 总18页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62W16255HC Series
4M High Speed SRAM (256-kword × 16-bit)
ADE-203-1200 (Z)
Preliminary
Rev. 0.0
Sep. 1, 2000
Description
The HM62W16255HC is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. The HM62W16255HC is
packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting.
Features
•
•
•
Single 3.3 V supply: 3.3 V ± 0.3 V
Access time: 10 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
•
•
All inputs and outputs
•
•
•
Operating current: 145 mA (max)
TTL standby current: 40 mA (max)
CMOS standby current: 5 mA (max)
: 1 mA (max) (L-version)
•
•
•
Data retention current: 0.6 mA (max) (L-version)
Data retention voltage: 2.0 V (min) (L-version)
Center VCC and VSS type pinout
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest
Hitachi’s Sales Dept. regarding specification.
HM62W16255HC Series
Ordering Information
Type No.
Access time
10 ns
Package
HM62W16255HCJP-10
HM62W16255HCLJP-10
HM62W16255HCTT-10
HM62W16255HCLTT-10
400-mil 44-pin plastic SOJ (CP-44D)
10 ns
10 ns
400-mil 44-pin plastic TSOPII (TTP-44DE)
10 ns
2
HM62W16255HC Series
Pin Arrangement
44-pin SOJ
44-pin TSOP
A0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
44
A17
A16
A15
OE
A0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
UB
UB
CS
LB
CS
LB
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A5
I/O16
I/O15
I/O14
I/O13
VSS
I/O1
I/O2
I/O3
I/O4
I/O16
I/O15
I/O14
I/O13
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
21
22
V
V
V
V
CC
SS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
SS
CC
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
A6
A7
A8
A9
(Top View)
(Top View)
Pin Description
Pin name
Function
A0 to A17
Address input
I/O1 to I/O16
Data input/output
Chip select
CS
OE
WE
UB
LB
Output enable
Write enable
Upper byte select
Lower byte select
Power supply
Ground
VCC
VSS
NC
No connection
3
HM62W16255HC Series
Block Diagram
(LSB)
A14
A13
A12
A5
VCC
VSS
Memory matrix
1024 rows × 32 columns ×
8 blocks × 16 bit
Row
decoder
A6
A7
A11
A10
A3
(4,194,304 bits)
A1
(MSB)
CS
I/O1
.
Column I/O
.
.
Input
data
control
Column decoder
I/O8
CS
I/O9
.
.
.
I/O16
(MSB)
A8 A9 A17 A15 A16 A0 A2 A4
(LSB)
WE
CS
LB
UB
OE
CS
4
HM62W16255HC Series
Operation Table
CS OE WE LB UB Mode
VCC current I/O1–I/O8
I/O9–I/O16
High-Z
High-Z
Output
High-Z
Output
High-Z
Input
Ref. cycle
—
H
L
L
L
L
L
L
L
L
L
×
H
L
L
L
L
×
×
×
×
×
×
×
Standby
ISB, ISB1
ICC
High-Z
High-Z
Output
Output
High-Z
High-Z
Input
H
H
H
H
H
L
×
×
Output disable
Read
—
L
L
ICC
Read cycle
Read cycle
Read cycle
—
L
H
L
Lower byte read ICC
Upper byte read ICC
H
H
L
H
L
—
ICC
ICC
Write
Write cycle
Write cycle
Write cycle
—
L
L
H
L
Lower byte write ICC
Upper byte write ICC
Input
High-Z
Input
L
H
H
High-Z
High-Z
L
H
—
ICC
High-Z
Note: ×: H or L
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Supply voltage relative to VSS
Voltage on any pin relative to VSS
Power dissipation
–0.5 to +4.6
–0.5*1 to VCC + 0.5*2
VT
V
PT
1.0
W
Operating temperature
Storage temperature
Topr
Tstg
Tbias
0 to +70
°C
°C
°C
–55 to +125
–10 to +85
Storage temperature under bias
Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns
5
HM62W16255HC Series
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC*3
VSS*4
VIH
Min
3.0
Typ
3.3
0
Max
Unit
V
Supply voltage
3.6
0
0
V
Input voltage
2.0
—
VCC + 0.5*2
V
VIL
–0.5*1
—
0.8
V
Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns
3. The supply voltage with all VCC pins must be on the same level.
4. The supply voltage with all VSS pins must be on the same level.
DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
Symbol Min
Typ*1
—
Max
2
Unit Test conditions
Input leakage current
Output leakage current
Operating power supply current
|ILI|
|ILO|
ICC
—
—
—
µA
µA
Vin = VSS to VCC
Vin = VSS to VCC
—
2
—
145
mA Min cycle
CS = VIL, Iout = 0 mA
Other inputs = VIH/VIL
Standby power supply current
ISB
—
—
—
40
5
mA Min cycle, CS = VIH,
Other inputs = VIH/VIL
ISB1
TBD
mA f = 0 MHz
V
CC ≥ CS ≥ VCC – 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
—*2
—
TBD*2
—
1.0*2
0.4
—
Output voltage
VOL
VOH
V
V
IOL = 8 mA
2.4
—
IOH = –4 mA
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
6
HM62W16255HC Series
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol
Cin
Min
—
Typ
—
Max
6
Unit
pF
Test conditions
Vin = 0 V
Input capacitance*1
Input/output capacitance*1
CI/O
—
—
8
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
7
HM62W16255HC Series
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
3.3 V
1.5 V
319 Ω
Dout
Dout
353Ω
Zo=50 Ω
5 pF
30 pF
RL=50 Ω
Output load (B)
(for tCLZ, tOLZ, tLBLZ, tUBLZ, tCHZ, tOHZ
Output load (A)
,
t
LBHZ, tUBHZ, tWHZ, and tOW)
Read Cycle
HM62W16255HC
-10
Parameter
Symbol
tRC
Min
10
—
—
—
—
3
Max
—
10
10
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
Address access time
tAA
Chip select access time
tACS
Output enable to output valid
Byte select to output valid
Output hold from address change
Chip select to output in low-Z
Output enable to output in low-Z
Byte select to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
Byte deselect to output in high-Z
tOE
tLB, tUB
tOH
5
—
—
—
—
5
tCLZ
3
1
1
1
1
1
1
tOLZ
0
tLBLZ, tUBLZ
tCHZ
0
—
—
—
tOHZ
5
tLBHZ, tUBHZ
5
8
HM62W16255HC Series
Write Cycle
HM62W16255HC
-10
Min
10
7
Parameter
Symbol
tWC
Max
—
—
—
—
—
—
—
—
—
—
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
Address valid to end of write
Chip select to end of write
Write pulse width
tAW
tCW
7
8
tWP
7
7
Byte select to end of write
Address setup time
tLBW, tUBW
tAS
7
9, 10
0
5
6
Write recovery time
tWR
0
Data to write time overlap
Data hold from write time
Write disable to output in low-Z
Output disable to output in high-Z
Write enable to output in high-Z
tDW
5
tDH
0
tOW
3
1
1
1
tOHZ
tWHZ
—
—
5
Notes: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the
WE transition, output remains a high impedance state.
3. WE and/or CS must be high during address transition time.
4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
5. tAS is measured from the latest address transition to the latest of CS, WE, LB or UB going low.
6. tWR is measured from the earliest of CS, WE, LB or UB going high to the first address transition.
7. A write occurs during the overlap of low CS, low WE and low LB or low UB.
8. tCW is measured from the later of CS going low to the end of write.
9. tLBW is measured from the later of LB going low to the end of write.
10. tUBW is measured from the later of UB going low to the end of write.
9
HM62W16255HC Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
tRC
Address
Valid address
tAA
tACS
CS
OE
LB
1
1
*
tCHZ
tOE
tOHZ
*
tLB
1
1
tLBHZ
*
tUB
UB
tUBHZ
*
1
tLBLZ
*
4
4
*
*
High Impedance
Dout
(Lower byte)
Valid data
1
tUBLZ
*
tOH
1
tOLZ
*
1
tCLZ
*
4
4
*
*
High Impedance
Dout
(Upper byte)
Valid data
10
HM62W16255HC Series
Read Timing Waveform (2) (WE = VIH, LB = VIL, UB, = VIL)
tRC
Address
Valid address
tAA
tOH
1
tCHZ
*
tACS
CS
OE
1
tOE
tOHZ
*
1
tOLZ
*
1
tCLZ
*
4
4
*
*
High Impedance
Dout
(Lower/Upper
byte)
Valid data
11
HM62W16255HC Series
Write Timing Waveform (1) (LB, UB Controlled)
tWC
Valid address
Address
tAW
tWR
tAS
tWP
WE*3
CS*3
tCW
OE
LB
tLBW
tUBW
UB
tOLZ
tOW
tWHZ
tOHZ
High impedance
High impedance
Dout
(Lower byte)
Dout
(Upper byte)
tDW
tDH
Valid data
tDH
Valid data
Din
(Lower byte)
tDW
Din
(Upper byte)
12
HM62W16255HC Series
Write Timing Waveform (2) (WE Controlled)
tWC
Valid address
Address
tWR
tAW
tAS
tWP
WE*3
CS*3
tCW
OE
tUBW
tLBW
LB, UB
tOLZ
tOW
tWHZ
tOHZ
High impedance
Dout
(Lower/Upper
byte)
2
*
tDW
tDH
Valid data
Din
(Lower/Upper
byte)
13
HM62W16255HC Series
Write Timing Waveform (3) (CS Controlled)
tWC
Valid address
Address
tWR
tAW
tAS
tWP
WE *3
CS *3
tCW
OE
tUBW
tLBW
LB, UB
tOLZ
tOW
tWHZ
tOHZ
4
*
High impedance
Dout
(Lower/Upper
byte)
2
*
tDW
tDH
Valid data
Din
(Lower/Upper
byte)
14
HM62W16255HC Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Typ*1 Max Unit Test conditions
VCC for data retention
VDR
2.0
—
—
V
VCC ≥ CS ≥ VCC – 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Data retention current
ICCDR
—
TBD 600
µA
VCC = 3 V
V
CC ≥ CS ≥ VCC – 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Chip deselect to data retention time
Operation recovery time
tCDR
tR
0
5
—
—
—
—
ns
See retention waveform
ms
Note: 1. Typical values are at VCC = 3.0 V, Ta = +25˚C, and not guaranteed.
Low VCC Data Retention Timing Waveform
Data retention mode
tCDR
tR
VCC
3.0 V
VDR
2.0 V
CS
0 V
V
CC ≥ CS ≥ VCC – 0.2 V
15
HM62W16255HC Series
Package Dimensions
HM62W16255HCJP/HCLJP Series (CP-44D)
Unit: mm
28.33
28.90 Max
44
23
22
1
0.74
1.30 Max
1.27
9.40 ± 0.25
*0.43 ± 0.10
0.41 ± 0.08
0.10
Hitachi Code
JEDEC
EIAJ
CP-44D
Conforms
—
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
1.8 g
16
HM62W16255HC Series
HM62W16255HCTT/HCLTT Series (TTP-44DE)
Unit: mm
18.41
18.81 Max
44
23
22
1
0.80
0.13
0.80
*0.27 ± 0.07
0.25 ± 0.05
M
11.76 ± 0.20
1.005 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
TTP-44DE
JEDEC
—
EIAJ
—
0.43 g
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
17
HM62W16255HC Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
Asia
: http://semiconductor.hitachi.com/
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: http://www.hitachi.co.jp/Sicd/indx.htm
Japan
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive, Dornacher Straße 3
Hitachi Europe GmbH
Electronic Components Group
Hitachi Asia Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7th Flr, North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
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D-85622 Feldkirchen, Munich
Tel: <1> (408) 433-1990 Germany
Fax: <1>(408) 433-0223 Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Fax: 535-1533
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Ltd.
Taipei Branch Office
3rd Flr, Hung Kuo Building, No.167,
Tun Hwa North Road, Taipei (105)
Taiwan
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 585160
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 23222 HAS-TP
Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
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18
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