HN58X2402-SR [HITACHI]
Two-wire serial interface 2k / 4k / 8k / 16k / 32k / 64k EEPROM; 两线串行接口2K / 4K / 8K / 16K / 32K / 64K EEPROM
| 型号： | HN58X2402-SR |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Two-wire serial interface 2k / 4k / 8k / 16k / 32k / 64k EEPROM |
| 文件： | 总21页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HN58X2402-SR/HN58X2404-SR/
HN58X2408-SR/HN58X2416-SR/
HN58X2432-SR/HN58X2464-SR
Two-wire serial interface
2k EEPROM (256-word × 8-bit)
4k EEPROM (512-word × 8-bit)
8k EEPROM (1-kword × 8-bit)/16k EEPROM (2-kword × 8-bit)
32k EEPROM (4-kword × 8-bit)/64k EEPROM(8-kword × 8-bit)
ADE-203-920A (Z)
Rev. 1.0
Dec. 11, 1998
Description
HN58X24xx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable
ROM). They realize high speed, low power consumption and a high level of reliability by employing
advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also
have a 32-byte page programming function to make their write operation faster.
Features
•
•
•
•
Single supply: 1.8 V to 5.5 V
Two-wire serial interface (I2CTM serial bus*1)
Clock frequency: 400 kHz
Power dissipation:
Standby: 3 µA(max)
Active (Read): 1 mA(max)
Active (Write): 3 mA(max)
•
•
•
•
•
Automatic page write: 32-byte/page
Write cycle time: 10 ms (2.7 V to 5.5 V )/15ms (1.8 V to 2.7 V )
Endurance: 105 Cycles (Page write mode)
Data retention: 10 Years
Small size packages: TSSOP-8pin and SOP-8pin
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Note: 1. I2C is a trademark of Philips Corporation.
Ordering Information
Type No.
Internal organization Operating voltageFrequency Package
HN58X2402FP-SR 2k bit (256 × 8-bit)
1.8 V to 5.5 V
400 kHz
150 mil 8-pin plastic SOP
(FP-8DB)
HN58X2404FP-SR 4k bit (512 × 8-bit)
HN58X2408FP-SR 8k bit (1024 × 8-bit)
HN58X2416FP-SR 16k bit (2048 × 8-bit)
HN58X2432FP-SR 32k bit (4096 × 8-bit)
HN58X2464FP-SR 64k bit (8192 × 8-bit)
HN58X2402T-SR 2k bit (256 × 8-bit)
1.8 V to 5.5 V
400 kHz
8-pin plastic TSSOP
(TTP-8D)
HN58X2404T-SR 4k bit (512 × 8-bit)
HN58X2408T-SR 8k bit (1024 × 8-bit)
HN58X2416T-SR 16k bit (2048 × 8-bit)
HN58X2432T-SR 32k bit (4096 × 8-bit)
HN58X2464T-SR 64k bit (8192 × 8-bit)
2
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Pin Arrangement
8-pin TSSOP
8-pin SOP
1
A0
A1
8
VCC
WP
2
3
4
7
6
5
A2
SCL
SDA
VSS
(Top view)
Pin Description
Pin name
A0 to A2
SCL
Function
Device address
Serial clock input
Serial data input/output
Write protect
SDA
WP
VCC
Power supply
VSS
Ground
3
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Block Diagram
High voltage generator
Memory array
VCC
VSS
WP
A0, A1, A2
SCL
Control
logic
Y-serect & Sense amp.
Serial-parallel converter
SDA
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
Supply voltage relative to VSS
Input voltage relative to VSS
Operating temperature range*1
Storage temperature range
–0.6 to +7.0
–0.5*2 to +7.0*3
–20 to +85
V
Vin
V
Topr
Tstg
˚C
˚C
–65 to +125
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min): –3.0 V for pulse width ≤ 50 ns.
3. Should not exceed VCC + 1.0 V.
4
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
DC Operating Conditions
Parameter
Symbol
VCC
Min
Typ
—
0
Max
Unit
V
Supply voltage
1.8
5.5
VSS
0
0
V
Input high voltage
Input low voltage
VIH
VCC × 0.7
–0.3*1
–20
—
—
—
VCC + 1.0
VCC × 0.3
85
V
VIL
V
Operating temperature
Topr
˚C
Notes: 1. VIL (min): –1.0 V for pulse width ≤ 50 ns.
DC Characteristics (Ta = –20 to +85˚C, VCC = 1.8 V to 5.5 V)
Parameter
Symbol Min
Typ
—
Max
2.0
2.0
3.0
1.0
3.0
0.4
Unit
µA
µA
µA
mA
mA
V
Test conditions
Input leakage current
Output leakage current
Standby VCC current
Read VCC current
Write VCC current
Output low voltage
ILI
—
—
—
—
—
—
VCC = 5.5 V, Vin = 0 to 5.5 V
VCC = 5.5 V, Vout = 0 to 5.5 V
Vin = VSS or VCC
ILO
—
ISB
1.0
—
ICC1
ICC2
VOL2
VCC = 5.5 V, Read at 400 kHz
VCC = 5.5 V, Write at 400 kHz
VCC = 4.5 to 5.5 V, IOL = 1.6 mA
—
—
V
V
CC = 2.7 to 4.5 V, IOL = 0.8 mA
CC = 1.8 to 2.7 V, IOL = 0.4 mA
VOL1
—
—
0.2
V
VCC = 1.8 to 2.7 V, IOL = 0.2 mA
Capacitance (Ta = 25˚C, f = 1 MHz)
Parameter
Symbol Min
Typ
Max
Unit
Test
conditions
Input capacitance (A0 to A2, SCL, WP) Cin*1
Output capacitance (SDA)
CI/O*1
—
—
—
—
6.0
6.0
pF
pF
Vin = 0 V
Vout = 0 V
Note: 1. This parameter is sampled and not 100% tested.
5
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
AC Characteristics (Ta = –20 to +85˚C, VCC = 1.8 to 5.5 V)
Test Conditions
•
Input pules levels:
VIL = 0.2 × VCC
VIH = 0.8 × VCC
•
•
•
Input rise and fall time: ≤ 20 ns
Input and output timing reference levels: 0.5 × VCC
Output load: TTL Gate + 100 pF
Parameter
Symbol Min
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
400
—
Unit
kHz
ns
Notes
Clock frequency
Clock pulse width low
Clock pulse width high
Noise suppression time
Access time
fSCL
tLOW
tHIGH
tI
—
1200
600
—
—
ns
50
ns
1
tAA
100
1200
600
600
0
900
—
ns
Bus free time for next mode
Start hold time
tBUF
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
ns
—
ns
Start setup time
—
ns
Data in hold time
Data in setup time
Input rise time
—
ns
100
—
—
ns
300
300
—
ns
1
1
Input fall time
tF
—
ns
Stop setup time
tSU.STO
tDH
600
50
ns
Data out hold time
—
ns
Write cycle time
VCC = 2.7 V to 5.5 V
VCC = 1.8 V to 2.7 V
tWC
—
10
ms
ms
2
2
tWC
—
15
Notes: 1. This parameter is sampled and not 100% tested.
2. tWC is the time from a stop condition to the end of internally controlled write cycle.
6
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Timing Waveforms
Bus Timing
1/fSCL
tLOW
tR
tF
tHIGH
SCL
tSU.STA
tHD.DAT
tSU.DAT
tHD.STA
tSU.STO
SDA
(in)
tBUF
tAA
tDH
SDA
(out)
Write Cycle Timing
Stop condition
Start condition
SCL
SDA
D0 in
tWC
(Internally controlled)
Write data
(Address (n))
ACK
7
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock
data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400
kHz.
Serial Input/Output data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that
pin is open-drain driven structure. Use proper resistor value for your system by considering VOL, IOL and the
SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later, the
SDA transition needs to be completed during SCL low period.
Data Validity (SDA data change timing waveform)
SCL
SDA
Data
Data
change
change
Note:
High-to-low and low-to-high chang of SDA should be done during SCL low periods.
Device address (A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to
distinguish each device and device address pins should be connected to VCC or VSS. When device address
code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one
device can be activated. As for 4k to 16k EEPROM, whole or some device address pins don't need to be
fixed since device address code provided from the SDA pin is used as memory address signal.
8
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Pin Connections for A0 to A2
Pin connection
Max connect
Memory size number
A2 A1
A0
Notes
2k bit
4k bit
8k bit
16k bit
8
4
2
1
VCC/VSS*1 VCC/VSS VCC/VSS
VCC/VSS VCC/VSS ×*2
Use A0 for memory address a8
VCC/VSS
×
×
×
×
Use A0, A1 for memory address a8 and a9
×
Use A0, A1, A2 for memory address a8, a9 and
a10
32k bit
64k bit
8
8
VCC/VSS VCC/VSS VCC/VSS
VCC/VSS VCC/VSS VCC/VSS
Notes: 1. “VCC/VSS” means that device address pin should be connected to VCC or VSS.
2. × = Don’t care (Open is also approval.)
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in
the following table. When the WP is low, write operation for all memory arrays are allowed. The read
operation is always activated irrespective of the WP pin status. WP should be fixed high or low during
operations since WP does not provide a latch function.
Write Protect Area
Write protect area
WP pin status 2k bit
4k bit
8k bit
16k bit
32k bit
64k bit
VIH
Upper 1/2
(1k bit)
Upper 1/2
(2k bit)
Upper 1/2
(4k bit)
Upper 1/2
(8k bit)
Upper 1/4
(8k bit)
Upper 1/4
(16k bit)
VIL
Normal read/write operation
9
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Functional Description
Start Condition
A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation.
(See start condition and stop condition)
Stop Condition
A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts
after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the
write data inputs and place the device in a internally-timed write cycle to the memories. After the
internally-timed write cycle which is specified as tWC, the device enters a standby mode. (See write cycle
timing)
Start Condition and Stop Condition
SCL
SDA
(in)
Start condition
Stop condition
Acknowledge
All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero
to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter
keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation,
EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM
sends a zero to acknowledge after receiving the device address word. After sending read data, the
EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge,
it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment) and
a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM
receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending
read data.
10
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Acknowledge Timing Waveform
1
2
8
9
SCL
SDA IN
Acknowledge
out
SDA OUT
Device Addressing
The EEPROM device requires an 8-bit device address word following a start condition to enable the chip
for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address
code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to
distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed by
the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device out of
all devices which are connected to the bus. This means that the device is selected if the inputted 3-bit
device address code is equal to the corresponding hard-wired A2-A0 pin status. As for the 4kbit, 8kbit and
16kbit EEPROMs, whole or some bits of their device address code may be used as the memory address
bits. For example, A0 is used as a8 of memory address for the 4kbit, A0 and A1 are used as a8 and a9 for
the 8kbit. The 16kbit doesn't use the device address code instead all 3 bits are used as the memory address
bits a8, a9 and a10. The eighth bit of the device address word is the read/write(R/W) bit. A write operation
is initiated if this bit is low and a read operation is initiated if this bit is high. Upon a compare of the device
address word, the EEPROM enters the read or write operation after outputting the zero as an acknowledge.
The EEPROM turns to a stand-by state if the device code is not “1010” or device address code doesn’t
coincide with status of the correspond hard-wired device address pins A0 to A2.
Device Address Word
Device address word (8-bit)
Device code (fixed)
Device address code*1
R/W code*2
R/W
2k, 32k, 64k 1
0
0
0
0
1
1
1
1
0
0
0
0
A2
A2
A2
a10
A1
A1
a9
a9
A0
a8
a8
a8
4k
1
1
1
R/W
8k
R/W
16k
R/W
Notes: 1. A2 to A0 are device address and a10 to a8 are memory address.
2. R/W=“1” is read and R/W = “0” is write.
11
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Write Operations
Byte Write:
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends
acknowledgment "0" at the ninth clock cycle. After these, the 2kbit to 16kbit EEPROMs receive 8-bit
memory address word, on the other hand the 32kbit and 64kbit EEPROMs receive 2 sequence 8-bit
memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0"
and receives a following 8-bit write data. After receipt of write data, the EEPROM outputs
acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an internally-timed
write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The EEPROM
returns to a standby mode after completion of the write cycle.
Byte Write Operation
Device
Memory
address
address (n)
Write data (n)
2k to 16k
Start
1 0 1 0
W
ACK
R/W
ACK
ACK
Stop
Device
address
1st Memory
address (n)
2nd Memory
address (n)
Write data (n)
W
1 0 1 0
32k to 64k
Start
ACK
R/W
ACK
ACK
Stop
Notes: 1. Don‘t care bits for 32k and 64k.
2. Don‘t care bit for 32k.
12
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 32 bytes to
be written in a single write cycle. The page write is the same sequence as the byte write except for inputting
the more write data. The page write is initiated by a start condition, device address word, memory
address(n) and write data(Dn) with every ninth bit acknowledgment. The EEPROM enters the page write
operation if the EEPROM receives more write data(Dn+1) instead of receiving a stop condition. The a0 to
a4 address bits are automatically incremented upon receiving write data(Dn+1). The EEPROM can
continue to receive write data up to 32 bytes. If the a0 to a4 address bits reaches the last address of the
page, the a0 to a4 address bits will roll over to the first address of the same page and previous write data
will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters
internally-timed write cycle.
Page Write Operation
Device
Memory
address
address (n)
Write data (n)
Write data (n+m)
2k to
16k
W
1 0 1 0
Stop
ACK
ACK
R/W
ACK
ACK
Start
Device
address
1st Memory
address (n)
2nd Memory
address (n)
Write data (n)
ACK
Write data (n+m)
32k to
64k
W
1 0 1 0
ACK
R/W
ACK
ACK
ACK
Stop
Start
Notes: 1. Don‘t care bits for 32k and 64k.
2. Don‘t care bit for 32k.
13
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Acknowledge Polling:
Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not.
This features is initiated by the stop condition after inputting write data. This requires the 8-bit device
address word following the start condition during a internally-timed write cycle. Acknowledge polling will
operate R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a
internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has
completed. See Write Cycle Polling using ACK.
Write Cycle Polling using ACK
Send
write command
Send
stop condition
to initiate write cycle
Send
start condition
Send
device address word
with R/W = 0
No
No
ACK
returned
Yes
Next operation is
addressing the memory
Yes
Send
Send
Send
memory address
start condition
stop condition
Send
stop condition
Proceed random address
read operation
Proceed write operation
14
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Read Operation
There are three read operations: current address read, random read, and sequential read. Read operations are
initiated the same way as write operations with the exception of R/W = “1”.
Current Address Read:
The internal address counter maintains the last address accessed during the last read or write operation,
with incremented by one. Current address read accesses the address kept by the internal address counter.
After receiving a start condition and the device address word(R/W is “1”), the EEPROM outputs the 8-bit
current address data from the most significant bit following acknowledgment “0” If the EEPROM receives
acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops the read
operation and is turned to a standby state. In case the EEPROM have accessed the last address of the last
page at previous read operation, the current address will roll over and returns to zero address. In case the
EEPROM have accessed the last address of the page at previous write operation, the current address will
roll over within page addressing and returns to the first address in the same page. The current address is
valid while power is on. The current address after power on will be indefinite. The random read operation
described below is necessary to define the memory address.
Current Address Read Operation
Device
address
Read data (n+1)
ACK No ACK
2k to 64k
Start
1 0 1 0
R
Stop
R/W
Notes: 1. Don‘t care bit for 16k.
2. Don‘t care bits for 8k and 16k.
3. Don‘t care bits for 4k, 8k and 16k.
Random Read:
This is a read operation with defined read address. A random read requires a dummy write to set read
address. The EEPROM receives a start condition, device address word(R/W=0) and memory address (8-bit
for 2kbit to 16kbit EEPROMs, 2 × 8-bit for 32kbit and 64kbit EEPROMs) sequentially. The EEPROM
outputs acknowledgment “0” after receiving memory address then enters a current address read with
receiving a start condition. The EEPROM outputs the read data of the address which was defined in the
dummy write operation. After receiving acknowledgment “1”(no acknowledgment) and a following stop
condition, the EEPROM stops the random read operation and returns to a standby state.
15
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Random Read Operation
Device
Memory
Device
address
address (n)
address
Read data (n)
ACK No ACK
@@@
# # #
2k to
16k
W
R
1 0 1 0
1 0 1 0
Start
ACK
R/W
Start
Stop
R/W
ACK
Dummy write
Currect address read
Device
address
1st Memory
address (n)
2nd Memory
address (n)
Device
address
Read data (n)
No ACK
@@@
# # #
32k to
64k
W
R
1 0 1 0
1 0 1 0
R/W
ACK
ACK
R/W
ACK
Start
ACK
Start
Stop
Dummy write
Currect address read
Notes: 1. Don‘t care bits for 32k and 64k.
2. Don‘t care bit for 32k.
3. 2nd device address code (#) should be same as 1st (@).
Sequential Read:
Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives
acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are
coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The
address will roll over and returns address zero if it reaches the last address of the last page. The sequential
read can be continued after roll over. The sequential read is terminated if the EEPROM receives
acknowledgment “1” (no acknowledgment) and a following stop condition.
Sequential Read Operation
Device
address
Read data (n) Read data (n+1) Read data (n+2) Read data (n+m)
2k to
64k
R
1 0 1 0
ACK
ACK
R/W
ACK
ACK
No ACK
Stop
Start
16
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Notes
Data protection at VCC On/Off
When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc)
may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional
programming, this EEPROM have a power on reset function. Be careful of the notices described below in
order for the power on reset function to operate correctly.
•
SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition
during VCC on/off may cause the trigger for the unintentional programming.
•
•
VCC should be turned off after the EEPROM is placed in a standby state.
VCC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the
unintentional programming mode.
•
VCC turn on speed should be longer than 10 us.
Write/Erase Endurance and Data retention Time
The endurance is 105 cycles in case of page programming and 104 cycles in case of byte programming (1%
cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed
less than 104 cycles.
Noise Suppression Time
This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than
50 ns. Be careful not to allow noise of width more than 50 ns.
17
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Package Dimensions
HN58X2402FP/HN58X2404FP/HN58X2408FP/HN58X2416FP/HN58X2432FP/HN58X2464FP-SR
(FP-8DB)
Preliminary
Unit: mm
4.89
5.15 Max
5
8
1
4
6.02 ± 0.18
0.69 Max
1.06
0° – 8°
+ 0.289
1.27
0.60
– 0.194
+0.063
*0.42
–0.064
0.40 ± 0.06
0.10
M
0.25
Hitachi Code
JEDEC
EIAJ
FP-8DB
—
—
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.08 g
18
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Package Dimensions (cont.)
HN58X2402T/HN58X2404T/HN58X2408T/HN58X2416T/HN58X2432T/HN58X2464T-SR (TTP-8D)
Preliminary
Unit: mm
3.00
3.20 Max
8
5
1
4
0.65
1.00
+0.08
–0.07
*0.22
0.13 M
0.20 ± 0.06
+0.10
6.40
–0.20
0.675 Max
0.10
0° – 8°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
TTP-8D
—
—
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.034 g
19
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
: http:semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
Asia (Taiwan)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe GmbH
Electronic components Group
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
2000 Sierra Point Parkway Dornacher Straße 3
Brisbane, CA 94005-1897 D-85622 Feldkirchen, Munich
Tel: <1> (800) 285-1601
Fax: <1> (303) 297-0447
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
20
HN58X2402/58X2404/58X2408/58X2416/58X2432/58X2464-SR
Revision Record
Rev. Date
1.0 Dec. 11, 1998
Contents of Modification
Drawn by
Approved by
Initial issue
21
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