HM24C128 [HMSEMI]

Low-voltage Operation;


型号：	HM24C128
厂家：	H&M Semiconductor
描述：	Low-voltage Operation
文件：	总15页 (文件大小：584K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SPECIFICATION

HM24C128/HM24C256/HM24C512

Version 1.1

Shenzhen H&M Semiconductor Co.Ltd

http：//www.hmsemi.com

▉Features

Low-voltage Operation

1.7 (VCC = 1.7V to 5.5V)



–

Low-Power Devices (ISB = 6 µA @ 5.5V) Available

Operating Ambient Temperature: -40°C to +85°C



 Internally Organized 16,384 X 8 (128K), 32,768 X 8 (256K),65,536X8(512K bits)

 Two-wire Serial Interface

 Schmitt Trigger, Filtered Inputs for Noise Suppression

 Bidirectional Data Transfer Protocol

 1MHz(5V),400 kHz (1.7V, 2.7V, 5V) Compatibility

 Write Protect Pin for Hardware Data Protection

 64-byte Page (128K/256K) Write Modes,128-bye (512k)Write Modes

 Partial Page Writes Allowed

 Self-timed Write Cycle (5 ms max)

 High-reliability

–

Endurance: 1 Million Write Cycles

Data Retention: 100 Years

 8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages

█General Description

The HM24C128/HM24C256/HM24C512 provides 131,072/262,144 /524,288bits of

serial electrically erasable and programmable read-only memory (EEPROM) organized

as4096 words of 8 bits each The device is optimized for use in many industrial and

applications where low-power and low-voltage operation are essential. The

HM24C128/HM24C256/HM24C512 is available in space-saving 8-lead PDIP, 8-lead SOP, and

TSSOP packages and is accessed via a Two-wire serial interface. In addition, the

HM24C128/HM24C256/HM24C512 is available in 1.7V (1.7V to 5.5V)

█Pin Configuration

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Pin Descriptions

█

number

Designation

Type

Name and Functions

Address Inputs

DEVICE/PAGE ADDRESSES (A1, A0):

The A1 and A0 pins are device address

inputs that are hardwired or left not

connected for hardware compatibility with

other 24Cxx devices. When the pins are

hardwired, as many as four 128K/256K

devices may be addressed on a single bus

system (device addressing is discussed in

detail under the Device Addressing

section). If the pins are left floating, the

A2, A1 and A0 pins will be internally pulled

down to GND if the capacitive coupling to

the circuit board VCC plane is <3 pF. If

coupling is >3 pF, recommends connecting

the address pins to GND.

1 –

A0 – A1

Serial Data

SERIAL DATA (SDA): The SDA pin is

bi-directional for serial data transfer. This

pin is open-drain driven and may be

wire-ORed with any number of other

open-drain or open- collector devices.

Serial Clock Input

SERIAL CLOCK (SCL): The SCL input is

used to positive edge clock data into each

EEPROM device and negative edge clock

data out of each device.

I/O

Open-drain

SDA

SCL

Write Protect

WRITE PROTECT (WP): The write

protect input, when connected to GND,

allows normal write operations. When WP

is connected high to VCC, all write

operations to the memory are inhibited. If

the pin is left floating, the WP pin will be

internally pulled down to GND if the

capacitive coupling to the circuit board VCC

plane is <3 pF. If coupling is >3 pF,

recommends connecting the pin to GND.

Switching WP to VCC prior to a write

operation creates a software write protect

function. The write protection feature is

enabled and operates as shown in the

following Table 1.

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GND

VCC

Ground

Power Supply

No connect

Table 1: Write Protect

Part of the Array Protected

WP Pin Status:

HM24C128

Full (128K) Array

HM24C256

Full (256K) Array

Normal Read/Write Operations

HM24C512

Full(512K)Array

At VCC

At GND

█Block Diagram

█Functional Description

1. Memory Organization

HM24C128, 128K SERIAL EEPROM: The 128K is internally organized as

256 pages of 64 bytes each. Random word addressing requires a 14-bit data

word address.

HM24C256, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64

bytes each. Random word addressing requires a 15-bit data word address.

HM24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128

bytes each. Random word addressing requires a 16-bit data word address.

2. Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.

Data on the SDA pin may change only during SCL low time periods (see to Figure 1 on page 5). Data

changes during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must

precede any other command (see to Figure 2 on page 5).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read

sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2 on

page 5).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM

in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received each word. This

happens during the ninth clock cycle.

STANDBY MODE: The HM24C128/HM24C256 features a low-power standby mode which is

enabled:

(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part

can be reset by following these steps:

Clock up to 9 cycles.

Look for SDA high in each cycle while SCL is high.

Create a start condition.

Figure 1. Data Validity

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Figure 2. Start and Stop Definition

Figure 3. Output Acknowledge

3. Device Addressing

The 128K/256K/512K EEPROM devices all require an 8-bit device address word following a start

condition to enable the chip for a read or write operation (see to Figure 4 on page 5).

The device address word consists of a mandatory “1”, “0” sequence for the first four most

significant bits as shown. This is common to all the Serial EEPROM devices.

The 128K/256K /512K uses the three device address bits A2, A1, A0 to allow as many

as eight devices on the same bus. These bits must compare to their corresponding

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hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that

biases them to a logic low condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is

initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the

chip will return to a standby state.

NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins

prevent small noise spikes from activating the device.

DATA SECURITY: The HM24C128/HM24C256 has a hardware data protection

scheme that allows the user to write protect the entire memory when the WP pin is

at VCC.

4. Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the device address

word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0”

and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will

output a “0” and the addressing device, such as a microcontroller, must terminate the write

sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, t_WR

to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not

PAGE WRITE: The 128K/256K devices are capable of 64-byte page writes.

A page write is initiated the same as a byte write, but the microcontroller does not send a stop

condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of

the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM wil

respond with a “0” after each data word received. The microcontroller must terminate the page

write sequence with a stop condition (see Figure 6 on page 8).

The data word address lower six (128K/256K) bits are internally incremented following the receipt

of each data word. The higher data word address bits are not incremented, retaining the memory

page row location. When the word address, internally generated, reaches the page boundary, the

following byte is placed at the beginning of the same page. If more than 64 data words are

transmitted to the EEPROM, the data word address will “roll over” and previous data will be

overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and

the EEPROM inputs are disabled, acknowledge polling can be initiated. This

involves sending a start condition followed by the device address word. The

read/write bit is representative of the operation desired. Only if the internal write

cycle has completed will the EEPROM respond with a “0”, allowing the read or write

sequence to continue.

5. Read Operations

Read operations are initiated the same way as write operations with the exception that the

read/write select bit in the device address word is set to “1”. There are three read operations:

current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the last address

accessed during the last read or write operation, incremented by one. This address stays valid

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between operations as long as the chip power is maintained. The address “roll over” during read is

from the last byte of the last memory page to the first byte of the first page. The address “roll over”

during write is from the last byte of the cur- rent page to the first byte of the same page.

Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by

the EEPROM, the current address data word is serially clocked out. The microcontroller does not

respond with an input “0” but does generate a following stop condition (see Figure 7 on page 8).

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word

address. Once the device address word and data word address are clocked in and acknowledged by

the EEPROM, the microcontroller must generate another start condition. The microcontroller now

initiates a current address read by sending a device address with the read/write select bit high. The

EEPROM acknowledges the device address and serially clocks out the data word. The

microcontroller does not respond with a “0” but does generate a following stop condition (see

Figure 8 on page 8).

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random

address read. After the microcontroller receives a data word, it responds with an acknowledge. As

long as the EEPROM receives an acknowledge, it will continue to increment the data word address

and serially clock out sequential data words. When the memory address limit is reached, the data

word address will “roll over” and the sequential read will continue. The sequential read operation

is terminated when the microcontroller does not respond with a “0” but does generate a following

stop condition (see Figure 9 on page 9)

Figure 4. Device Address

Figure 5. Byte Write

Figure 6. Page Write

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Figure 7. Current Address Read

Figure 8. Random Read

Figure 9. Sequential Read

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█Electrical Characteristics

Absolute Maximum Stress Ratings

DC Supply Voltage . . . -0.3V to +6.5V

Input / Output Voltage. .. GND-0.3V to VCC+0.3V

Operating Ambient Temperature . . .-40°C to +85°C

Storage Temperature . . . . . . . . . -55°C to +125°C

*Comments

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this

device. These are stress ratings only. Functional operation of this device at these or any other conditions

above those indicated in the operational sections of this specification is not implied or intended

Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

█DC Electrical Characteristics

Applicable over recommended operating range from: T_A= –40ꢀC to +85ꢀC, VCC

Parameter

Symbol

Min.

Typ

Max.

Unit Condition

V_CC1

V_CC2

V_CC3

1.7

2.5

2.7

4.5

5.5

1.0

3.0

1.0

2.0

5.0

Supply Voltage

Supply Current V

V_CC4

I_CC1

I_CC2

I_SB1

I_SB2

I_SB3

I_SB4

0.4

2.0

0.6

1.0

µA

READ at 400 kHz

= 5.0V

WRITE at 400 kHz

V_IN= VCC or VSS

Standby Current V

= 1.8V

= 2.5V

= 2.7V

= 5.0V

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I_LI

0.10

0.05

3.0

µA

V_IN= VCC or VSS

V_OUT= VCC or VSS

Input Leakage Current

Output Leakage Current

Input Low Level

I_LO

V_IL

V_IH

–0.6

VCCx0.7

VCCx0.3

VCC+0.5

0.4

Input High Level

Output Low Level VCC =5.0V

Output Low Level VCC =3.0V

Output Low Level VCC =1.8V

V_OL3

V_OL2

I_OL= 3.0 mA

I_OL= 2.1 mA

0.4

V_OL1

0.2

I_OL= 0.15 mA

█

Pin Capacitance

Applicable over recommended operating range from T_A= 25ꢀC, f = 1.0 MHz, VCC

Min. Typ. Max. Unit Condition

Parameter

Symbol

C_I/O

Input/Output Capacitance (SDA)

Input Capacitance (A0, A1, A2, SCL)

V_I/O= 0V

V_IN= 0V

C_IN

█

AC Electrical Characteristics

Applicable over recommended operating range from T_A= –40ꢀC to +85ꢀC, VCC

+1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)

1.7, 2.7, 5.0-volt

Parameter

Symbol

Units

Min.

Typ.

Max.

Clock Frequency, SCL

400

f_SCL

t_LOW

t_HIGH

t_I

Clock Pulse Width Low

Clock Pulse Width High

Noise Suppression Time

Clock Low to Data Out Valid

1.2

0.6

µs

0.9

t_AA

0.1

Time the bus must be free

before a new transmission can

start

1.2

µs

t_BUF

Start Hold Time

Start Setup Time

Data In Hold Time

Data In Setup Time

Inputs Rise Time

Inputs Fall Time

0.6

µs

t_HD.STA

t_SU.STA

t_HD.DAT

t_SU.DAT

t_R

100

0.3

300

t_F

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Stop Setup Time

t_SU.STO

t_DH

0.6

µs

Data Out Hold Time

Write Cycle Time

t_WR

5.0V, 25ꢀC, Byte Mode

Endurance

Write Cycles

Bus Timing

Figure 10. SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle Timing

Figure 11. SCL: Serial Clock, SDA: Serial Data I/O

1. The write cycle time t_WRis the time from a valid stop condition of a write

sequence to the end of the internal clear/write cycle.

Note:

▉Ordering Information

Code Number

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Part Number

XXX

X X

4 5

1.Prefix

2.Series Name

5.Temperature Range

I=Ind Temp(-40℃-85℃)

24:Two-wire(I2C) Interface

E=Exp Temp(-40℃ -125℃)

3.EEPROM Density

6. Packing Type

T=Tube

C128=128K bits

C256=256K bits

R=Tape & Reel

4.Package Type

D=DIP

S=SOP

T=TSSOP

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▉Packaging Information

1.TSSOP

COMMON

DIMENSIONS

MILLIMETER

SYMBOL

MIN

─

NOM

─

MAX

1.2

0.05

0.80

0.34

0.20

0.10

2.90

─

1.00

0.44

─

0.15

1.05

0.54

0.28

0.24

0.19

0.15

3.10

0.22

─

0.13

3.00

6.40BSC

4.40

0.65 BSC

0.60

4.30

0.45

4.50

0.75

.00REF

.25BSC

0.09

0.20

─

SYMBOL

θ1

θ2

θ3

0^o

10^o

─

8^o

14^o

12^o

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2.SOP

MILLIMETER

NOM

－

SYMBOL

MIN

－

MAX

1.77

0.28

1.60

0.75

0.48

0.43

0.26

0.21

5.10

6.20

4.10

0.08

1.20

0.55

0.39

0.38

0.21

0.19

4.70

5.80

3.70

0.18

1.40

0.65

－

0.41

－

0.20

4.90

6.00

3.90

1.27BSC

0.50

0.65

0.80

8°

1.05BSC

－

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3. DIP

MILLIMETER

NOM

3.80

SYMBOL

MIN

3.60

0.51

3.10

1.50

0.44

0.43

MAX

4.00

－

3.30

3.50

1.70

0.53

0.48

1.60

－

0.46

1.52BSC

－

0.25

0.24

9.05

6.15

0.31

0.26

9.45

6.55

0.25

9.25

6.35

2.54BSC

7.62BSC

－

7.62

9.50

0.94

－

3.00

－

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