BH66F2660_技术文档

Body Fat Measurment Flash MCU

BH66F2650/BH66F2660

Revision: V1.10 Date: �anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Table of Contents

Features................................................................................................................7

CPU Featꢀꢁes ..............................................................................................................................7

Peꢁipheꢁal Featꢀꢁes......................................................................................................................7

General Description.............................................................................................8

Selection Table.....................................................................................................9

Block Diagram......................................................................................................9

Pin Assignment..................................................................................................10

Pin Description .................................................................................................. 11

Absolute Maximum Ratings..............................................................................15

D.C. Characteristics...........................................................................................15

Opeꢁating Voltage Chaꢁacteꢁistics..............................................................................................15

Standbꢂ Cꢀꢁꢁent Chaꢁacteꢁistics ................................................................................................16

Opeꢁating Cꢀꢁꢁent Chaꢁacteꢁistics..............................................................................................17

A.C. Characteristics...........................................................................................18

High Speed Inteꢁnal Oscillatoꢁ – HIRC – Fꢁeqꢀencꢂ Accꢀꢁacꢂ..................................................1ꢆ

Low Speed Inteꢁnal Oscillatoꢁ Chaꢁacteꢁistics – LIRC ...............................................................1ꢆ

Opeꢁating Fꢁeqꢀencꢂ Chaꢁacteꢁistic Cꢀꢁves..............................................................................19

Sꢂstem Staꢁt Up Time Chaꢁacteꢁistics .......................................................................................19

Input/Output Characteristics ............................................................................20

Memory Characteristics....................................................................................22

LVD/LVR Electrical Characteristics..................................................................22

24-bit A/D Converter Electrical Characteristics .............................................. 23

12-bit D/A Converter Electrical Characteristics .............................................. 24

Operational Ampliﬁer Electrical Characteristics (Body Fat Circuit) ............. 24

Power-on Reset Characteristics.......................................................................25

System Architecture..........................................................................................25

Clocking and Pipelining..............................................................................................................ꢅ5

Pꢁogꢁam Coꢀnteꢁ........................................................................................................................ꢅ6

Stack ..........................................................................................................................................ꢅ7

Aꢁithmetic and Logic Unit – ALU ................................................................................................ꢅ7

Flash Program Memory.....................................................................................28

Stꢁꢀctꢀꢁe.....................................................................................................................................ꢅꢆ

Special Vectoꢁs ..........................................................................................................................ꢅꢆ

Look-ꢀp Table.............................................................................................................................ꢅ9

Table Pꢁogꢁam Example.............................................................................................................ꢅ9

In Ciꢁcꢀit Pꢁogꢁamming – ICP ....................................................................................................30

On-Chip Debꢀg Sꢀppoꢁt – OCDS ..............................................................................................31

In Application Pꢁogꢁamming – IAP .............................................................................................31

Rev. 1.10

ꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

RAM Data Memory.............................................................................................40

Stꢁꢀctꢀꢁe.....................................................................................................................................ꢃ0

Data Memoꢁꢂ Addꢁessing...........................................................................................................ꢃ1

Geneꢁal Pꢀꢁpose Data Memoꢁꢂ .................................................................................................ꢃ1

Special Pꢀꢁpose Data Memoꢁꢂ ..................................................................................................ꢃ1

Special Function Register Description............................................................44

Indiꢁect Addꢁessing Registeꢁs – IAR0ꢄ IAR1ꢄ IARꢅ ....................................................................ꢃꢃ

Memoꢁꢂ Pointeꢁs – MP0ꢄ MP1Lꢄ MP1Hꢄ MPꢅLꢄ MPꢅH..............................................................ꢃꢃ

Pꢁogꢁam Memoꢁꢂ Bank Pointeꢁ – PBP.......................................................................................ꢃ6

Accꢀmꢀlatoꢁ – ACC ...................................................................................................................ꢃ6

Pꢁogꢁam Coꢀnteꢁ Low Registeꢁ – PCL ......................................................................................ꢃ6

Look-ꢀp Table Registeꢁs – TBLPꢄ TBHPꢄ TBLH .........................................................................ꢃ6

Statꢀs Registeꢁ – STATUS ........................................................................................................ꢃ7

EEPROM Data Memory......................................................................................49

EEPROM Data Memoꢁꢂ Stꢁꢀctꢀꢁe .............................................................................................ꢃ9

EEPROM Registeꢁs ...................................................................................................................ꢃ9

Reading Data fꢁom the EEPROM ..............................................................................................51

Wꢁiting Data to the EEPROM.....................................................................................................51

Wꢁite Pꢁotection..........................................................................................................................51

EEPROM Inteꢁꢁꢀpt .....................................................................................................................51

Pꢁogꢁamming Consideꢁations.....................................................................................................5ꢅ

Oscillators ..........................................................................................................53

Oscillatoꢁ Oveꢁview ...................................................................................................................53

System Clock Conﬁgurations ....................................................................................................53

External High Speed Crystal Oscillator − HXT...........................................................................5ꢃ

Internal RC Oscillator − HIRC....................................................................................................55

External 32.768kHz Crystal Oscillator − LXT.............................................................................55

Internal 32kHz Oscillator − LIRC................................................................................................56

Operating Modes and System Clocks .............................................................56

Sꢂstem Clocks ...........................................................................................................................56

Sꢂstem Opeꢁation Modes...........................................................................................................57

Contꢁol Registeꢁs .......................................................................................................................5ꢆ

Opeꢁating Mode Switching.........................................................................................................61

Standbꢂ Cꢀꢁꢁent Consideꢁations................................................................................................65

Wake-ꢀp.....................................................................................................................................65

Watchdog Timer.................................................................................................66

Watchdog Timeꢁ Clock Soꢀꢁce...................................................................................................66

Watchdog Timeꢁ Contꢁol Registeꢁ..............................................................................................66

Watchdog Timeꢁ Opeꢁation ........................................................................................................67

Reset and Initialisation......................................................................................68

Reset Fꢀnctions .........................................................................................................................6ꢆ

Reset Initial Conditions .............................................................................................................7ꢅ

Rev. 1.10

3

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Input/Output Ports.............................................................................................76

Pꢀll-high Resistoꢁs .....................................................................................................................76

Poꢁt A Wake-ꢀp ..........................................................................................................................77

I/O Poꢁt Contꢁol Registeꢁs..........................................................................................................77

I/O Poꢁt Soꢀꢁce Cꢀꢁꢁent Contꢁol.................................................................................................7ꢆ

Pin-shaꢁed Fꢀnctions .................................................................................................................79

I/O Pin Stꢁꢀctꢀꢁes.......................................................................................................................ꢆ3

Pꢁogꢁamming Consideꢁations ....................................................................................................ꢆꢃ

Timer Modules – TM ..........................................................................................84

Intꢁodꢀction ................................................................................................................................ꢆꢃ

TM Opeꢁation .............................................................................................................................ꢆ5

TM Clock Soꢀꢁce........................................................................................................................ꢆ5

TM Inteꢁꢁꢀpts..............................................................................................................................ꢆ5

TM Exteꢁnal Pins........................................................................................................................ꢆ5

TM Inpꢀt/Oꢀtpꢀt Pin Selection ...................................................................................................ꢆ6

Pꢁogꢁamming Consideꢁations.....................................................................................................ꢆ7

Standard Type TM – STM ..................................................................................88

Standaꢁd TM Opeꢁation..............................................................................................................ꢆꢆ

Standaꢁd Tꢂpe TM Registeꢁ Descꢁiption ....................................................................................ꢆ9

Standaꢁd Tꢂpe TM Opeꢁation Modes.........................................................................................93

Periodic Type TM – PTM..................................................................................103

Peꢁiodic TM Opeꢁation .............................................................................................................103

Peꢁiodic Tꢂpe TM Registeꢁ Descꢁiption....................................................................................103

Peꢁiodic Tꢂpe TM Opeꢁating Modes ........................................................................................10ꢆ

Analog to Digital Converter – ADC................................................................. 117

A/D Oveꢁview ...........................................................................................................................117

Inteꢁnal Poweꢁ Sꢀpplꢂ .............................................................................................................117

A/D Data Rate Deﬁnition..........................................................................................................11ꢆ

A/D Conveꢁteꢁ Registeꢁ Descꢁiption.........................................................................................119

A/D Opeꢁation ..........................................................................................................................1ꢅ7

Sꢀmmaꢁꢂ of A/D Conveꢁsion Steps..........................................................................................1ꢅꢆ

Pꢁogꢁamming Consideꢁations...................................................................................................1ꢅ9

A/D Tꢁansfeꢁ Fꢀnction ..............................................................................................................1ꢅ9

A/D Conveꢁted Data.................................................................................................................130

A/D Conveꢁted Data to Voltage................................................................................................131

A/D Pꢁogꢁamming Example......................................................................................................131

Tempeꢁatꢀꢁe Sensoꢁ.................................................................................................................13ꢅ

Serial Interface Module – SIM.........................................................................132

SPI Inteꢁface ............................................................................................................................13ꢅ

I^ꢅC Inteꢁface .............................................................................................................................139

Serial Peripheral Interface – SPIA..................................................................148

SPIA Inteꢁface Opeꢁation .........................................................................................................1ꢃꢆ

SPIA Registeꢁs.........................................................................................................................150

Rev. 1.10

ꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

SPIA Commꢀnication ...............................................................................................................15ꢅ

SPIA Bꢀs Enable/Disable.........................................................................................................155

SPIA Opeꢁation ........................................................................................................................155

Eꢁꢁoꢁ Detection.........................................................................................................................156

UART Interface.................................................................................................157

UART Exteꢁnal Pin Inteꢁfacing .................................................................................................157

UART Data Tꢁansfeꢁ Scheme...................................................................................................157

UART Statꢀs and Contꢁol Registeꢁs.........................................................................................15ꢆ

Baꢀd Rate Geneꢁatoꢁ...............................................................................................................163

UART Setꢀp and Contꢁol..........................................................................................................165

UART Tꢁansmitteꢁ.....................................................................................................................166

UART Receiveꢁ ........................................................................................................................167

Managing Receiveꢁ Eꢁꢁoꢁs .......................................................................................................169

UART Modꢀle Inteꢁꢁꢀpt Stꢁꢀctꢀꢁe.............................................................................................170

UART Poweꢁ Down and Wake-ꢀp............................................................................................17ꢅ

Body Fat Measurement Function...................................................................173

Sine Wave Geneꢁatoꢁ...............................................................................................................173

Bodꢂ Fat Measꢀꢁement Registeꢁs............................................................................................176

Interrupts..........................................................................................................180

Inteꢁꢁꢀpt Registeꢁs....................................................................................................................1ꢆ0

Inteꢁꢁꢀpt Opeꢁation...................................................................................................................1ꢆ5

Exteꢁnal Inteꢁꢁꢀpt......................................................................................................................1ꢆ6

LVD Inteꢁꢁꢀpt............................................................................................................................1ꢆ7

EEPROM Inteꢁꢁꢀpt ...................................................................................................................1ꢆ7

A/D Conveꢁteꢁ Inteꢁꢁꢀpt............................................................................................................1ꢆ7

Mꢀlti-fꢀnction Inteꢁꢁꢀpts............................................................................................................1ꢆ7

Seꢁial Inteꢁface Modꢀle Inteꢁꢁꢀpt..............................................................................................1ꢆꢆ

SPIA Inteꢁꢁꢀpt...........................................................................................................................1ꢆꢆ

UART Inteꢁꢁꢀpt.........................................................................................................................1ꢆꢆ

Time Base Inteꢁꢁꢀpts................................................................................................................1ꢆꢆ

Timeꢁ Modꢀle Inteꢁꢁꢀpts...........................................................................................................190

Inteꢁꢁꢀpt Wake-ꢀp Fꢀnction......................................................................................................190

Pꢁogꢁamming Consideꢁations...................................................................................................191

Low Voltage Detector – LVD ...........................................................................192

LVD Registeꢁ............................................................................................................................19ꢅ

LVD Opeꢁation..........................................................................................................................193

16-bit Multiplication Division Unit – MDU...................................................... 194

MDU ꢁegisteꢁs ..........................................................................................................................19ꢃ

Mꢀltiplication Division Unit Opeꢁation.......................................................................................195

Application Circuits.........................................................................................197

Instruction Set..................................................................................................199

Intꢁodꢀction ..............................................................................................................................199

Instꢁꢀction Timing.....................................................................................................................199

Rev. 1.10

5

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Moving and Tꢁansfeꢁꢁing Data..................................................................................................199

Aꢁithmetic Opeꢁations...............................................................................................................199

Logical and Rotate Opeꢁation ..................................................................................................ꢅ00

Bꢁanches and Contꢁol Tꢁansfeꢁ ................................................................................................ꢅ00

Bit Opeꢁations ..........................................................................................................................ꢅ00

Table Read Opeꢁations ............................................................................................................ꢅ00

Otheꢁ Opeꢁations......................................................................................................................ꢅ00

Instruction Set Summary ................................................................................201

Table Conventions....................................................................................................................ꢅ01

Extended Instꢁꢀction Set..........................................................................................................ꢅ03

Instruction Deﬁnition.......................................................................................205

Extended Instruction Deﬁnition ................................................................................................ꢅ1ꢃ

Package Information .......................................................................................221

ꢃꢆ-pin LQFP (7mm×7mm) Oꢀtline Dimensions .......................................................................ꢅꢅꢅ

Rev. 1.10

6

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Features

CPU Features

•ꢀ OperatingꢀVoltage

ꢀ

♦

ꢀ

♦

ꢀ

♦

ꢀ

♦

f_SYS=4MHz:ꢀ2.2V~5.5V

f_SYS=8MHz:ꢀ2.2V~5.5V

f_SYS=12MHz:ꢀ2.7V~5.5V

f_SYS=16MHz:ꢀ3.3V~5.5V

•ꢀ Upꢀtoꢀ0.25μsꢀinstructionꢀcycleꢀwithꢀ16MHzꢀsystemꢀclockꢀatꢀV_DD=5V

•ꢀ Powerꢀdownꢀandꢀwake-upꢀfunctionsꢀtoꢀreduceꢀpowerꢀconsumption

•ꢀ FourꢀOscillators:

ꢀ

♦

ꢀ

♦

ꢀ

♦

ꢀ

♦

HighꢀSpeedꢀInternalꢀRCꢀ–ꢀHIRC

Externalꢀ32.768kHzꢀCrystalꢀ–ꢀLXT

HighꢀSpeedꢀExternalꢀCrystalꢀ–ꢀHXT

Internalꢀ32kHzꢀRCꢀ–ꢀLIRC

•ꢀ Multi-modeꢀoperation:ꢀFAST,ꢀSLOW,ꢀIDLEꢀandꢀSLEEP

•ꢀ Fullyꢀintegratedꢀinternalꢀ4MHz,ꢀ8MHzꢀorꢀ12MHzꢀoscillatorꢀrequiresꢀnoꢀexternalꢀcomponents

•ꢀ Allꢀinstructionsꢀexecutedꢀinꢀ1~3ꢀinstructionꢀcycles

•ꢀ Tableꢀreadꢀinstructions

•ꢀ 115ꢀpowerfulꢀinstructions

•ꢀ 8-levelꢀsubroutineꢀnesting

•ꢀ Bitꢀmanipulationꢀinstruction

Peripheral Features

•ꢀ FlashꢀProgramꢀMemory:ꢀ8K×16ꢀ~ꢀ16K×16

•ꢀ RAMꢀDataꢀMemory:ꢀ256×8ꢀ~ꢀ1024×8

•ꢀ TrueꢀEEPROMꢀMemory:ꢀ64×8ꢀ~ꢀ256×8

•ꢀ WatchdogꢀTimerꢀfunction

•ꢀ InꢀApplicationꢀProgrammingꢀ–ꢀIAP

•ꢀ Upꢀtoꢀ28ꢀbidirectionalꢀI/Oꢀlines

•ꢀ 2ꢀdifferentialꢀorꢀ4ꢀsingle-endꢀchannelsꢀ24-bitꢀresolutionꢀDeltaꢀSigmaꢀA/Dꢀconverter

•ꢀ Twoꢀpin-sharedꢀexternalꢀinterrupts

•ꢀ MultipleꢀTimerꢀModulesꢀforꢀtimeꢀmeasure,ꢀinputꢀcapture,ꢀcompareꢀmatchꢀoutput,ꢀPWMꢀoutputꢀorꢀ

singleꢀpulseꢀoutputꢀfunction

•ꢀ SerialꢀInterfaceꢀModuleꢀwithꢀDualꢀSPIꢀandꢀI²Cꢀinterfacesꢀ–ꢀSIM

•ꢀ SingleꢀSerialꢀPeripheralꢀInterfaceꢀ–ꢀSPIA

•ꢀ UARTꢀInterfaceꢀforꢀfullꢀduplexꢀasynchronousꢀcommunication

•ꢀ DualꢀTime-Baseꢀfunctionsꢀforꢀgenerationꢀofꢀﬁxedꢀtimeꢀinterruptꢀsignals

•ꢀ LowꢀVoltageꢀResetꢀfunctionꢀ–ꢀLVR

•ꢀ LowꢀVoltageꢀDetectꢀfunctionꢀ–ꢀLVD

•ꢀ BodyꢀFatꢀCircuit

•ꢀ 16-bitꢀMultiplicationꢀDivisionꢀUnit

•ꢀ Packageꢀtype:ꢀ48-pinꢀLQFP

Rev. 1.10

7

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

General Description

Thisꢀseriesꢀofꢀdevicesꢀareꢀspecificallyꢀdesignedꢀforꢀeight-electrodeꢀACꢀBodyꢀFatꢀScaleꢀapplications.ꢀ

MeasuringꢀbodyꢀfatꢀusesꢀaꢀtechniqueꢀwherebyꢀanꢀACꢀcurrentꢀflowingꢀthroughꢀtheꢀhumanꢀbodyꢀisꢀ

measuredꢀandꢀthenꢀusedꢀtoꢀcalculateꢀaꢀbodyꢀfatꢀvalue.ꢀTheꢀspecialisedꢀcircuitsꢀtoꢀdoꢀthisꢀareꢀaꢀweightꢀ

measurementꢀcircuitꢀandꢀaꢀfatꢀmeasurementꢀcircuit.ꢀTheꢀweightꢀmeasurementꢀcircuitꢀusesꢀanꢀexternalꢀloadꢀ

cellꢀtoꢀoutputꢀaꢀsignal,ꢀwhichꢀafterꢀampliﬁcationꢀbyꢀanꢀoperationalꢀampliﬁer,ꢀandꢀthenꢀconversionꢀusingꢀanꢀ

A/Dꢀconverter,ꢀreadsꢀtheꢀcorrespondingꢀvalueꢀasꢀtheꢀcalculatedꢀweight.ꢀTheꢀfatꢀmeasurementꢀcircuitꢀ

usesꢀanꢀACꢀsignalꢀviaꢀanꢀelectrodeꢀsliceꢀtoꢀﬂowꢀthroughꢀhumanꢀbody.ꢀAfterꢀampliﬁcationꢀbyꢀanꢀinternalꢀ

operationalꢀampliﬁer,ꢀandꢀthenꢀconversionꢀbyꢀanꢀA/Dꢀconverter,ꢀtheꢀmeasuredꢀvalueꢀisꢀoneꢀrepresentingꢀ

bodyꢀimpedance,ꢀwhichꢀisꢀusedꢀtoꢀcalculateꢀtheꢀcorrespondingꢀbodyꢀfatꢀvalue.

ThisꢀseriesꢀofꢀdevicesꢀareꢀFlashꢀMemoryꢀI/Oꢀtypeꢀ8-bitꢀhighꢀperformanceꢀRISCꢀarchitectureꢀ

microcontrollerꢀwhichꢀincludesꢀaꢀmulti-channelꢀ24-bitꢀDeltaꢀSigmaꢀA/Dꢀconverter,ꢀdesignedꢀforꢀ

applicationsꢀthatꢀinterfaceꢀdirectlyꢀtoꢀanalogꢀsignalsꢀandꢀwhichꢀrequireꢀaꢀlowꢀnoiseꢀandꢀhighꢀaccuracyꢀ

analog-to-digitalꢀconverter.ꢀOfferingꢀusersꢀtheꢀconvenienceꢀofꢀFlashꢀMemoryꢀmulti-programmingꢀ

features,ꢀtheꢀdevicesꢀalsoꢀincludesꢀaꢀwideꢀrangeꢀofꢀfunctionsꢀandꢀfeatures.ꢀOtherꢀmemoryꢀincludesꢀanꢀ

areaꢀofꢀRAMꢀDataꢀMemoryꢀasꢀwellꢀasꢀanꢀareaꢀofꢀtrueꢀEEPROMꢀmemoryꢀforꢀstorageꢀofꢀnon-volatileꢀ

dataꢀsuchꢀasꢀserialꢀnumbers,ꢀcalibrationꢀdataꢀetc.

Analogꢀfeaturesꢀincludeꢀaꢀmulti-channelꢀ24-bitꢀDeltaꢀSigmaꢀA/Dꢀconverter,ꢀPGAꢀandꢀLDOꢀandꢀotherꢀ

circuitryꢀspecificallyꢀdesignedꢀforꢀBodyꢀFatꢀScaleꢀapplications.ꢀMultipleꢀandꢀextremelyꢀflexibleꢀ

TimerꢀModulesꢀprovideꢀtiming,ꢀpulseꢀgenerationꢀandꢀPWMꢀgenerationꢀfunctions.ꢀCommunicationꢀ

withꢀtheꢀoutsideꢀworldꢀisꢀprovidedꢀbyꢀincludingꢀfullyꢀintegratedꢀSPI,ꢀI²CꢀandꢀUARTꢀinterfaceꢀ

functions,ꢀpopularꢀinterfacesꢀwhichꢀprovideꢀdesignersꢀwithꢀaꢀmeansꢀofꢀeasyꢀcommunicationꢀwithꢀ

externalꢀperipheralꢀhardware.ꢀProtectiveꢀfeaturesꢀsuchꢀasꢀanꢀinternalꢀWatchdogꢀTimer,ꢀLowꢀVoltageꢀ

ResetꢀandꢀLowꢀVoltageꢀDetectorꢀcoupledꢀwithꢀexcellentꢀnoiseꢀimmunityꢀandꢀESDꢀprotectionꢀensureꢀ

thatꢀreliableꢀoperationꢀisꢀmaintainedꢀinꢀhostileꢀelectricalꢀenvironments.ꢀ

Aꢀfullꢀchoiceꢀofꢀexternal,ꢀinternalꢀandꢀhighꢀandꢀlowꢀoscillatorsꢀfunctionsꢀareꢀprovidedꢀincludingꢀtwoꢀ

fullyꢀintegratedꢀsystemꢀoscillatorsꢀwhichꢀrequireꢀnoꢀexternalꢀcomponentsꢀforꢀtheirꢀimplementation.ꢀ

Theꢀabilityꢀtoꢀoperateꢀandꢀswitchꢀdynamicallyꢀbetweenꢀaꢀrangeꢀofꢀoperatingꢀmodesꢀusingꢀdifferentꢀ

clockꢀsourcesꢀgivesꢀusersꢀtheꢀabilityꢀtoꢀoptimiseꢀmicrocontrollerꢀoperationꢀandꢀminimiseꢀpowerꢀ

consumption.

Theꢀdevicesꢀalsoꢀincludeꢀaꢀmultiplication/divisionꢀunit.ꢀTheꢀinclusionꢀofꢀﬂexibleꢀI/Oꢀprogrammingꢀ

features,ꢀTime-Baseꢀfunctionsꢀalongꢀwithꢀmanyꢀotherꢀfeaturesꢀensureꢀthatꢀonlyꢀaꢀminimumꢀofꢀ

externalꢀcomponentsꢀisꢀrequiredꢀforꢀapplicationꢀimplementation,ꢀresultingꢀinꢀreducedꢀcomponentꢀ

costsꢀandꢀreductionsꢀinꢀcircuitꢀboardꢀareas.

Rev. 1.10

ꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Selection Table

Mostꢀfeaturesꢀareꢀcommonꢀtoꢀbothꢀdevices.ꢀTheꢀmainꢀfeaturesꢀdistinguishingꢀthemꢀareꢀMemoryꢀ

capacity.ꢀTheꢀfollowingꢀtableꢀsummarisesꢀtheꢀmainꢀfeaturesꢀofꢀeachꢀdevice.

A/D

Converter

Part No.

V_DD

ROM

RAM

EEPROM

I/O

Ext.Int.

BH66Fꢅ650

BH66Fꢅ660

ꢅ.ꢅV~5.5V

ꢆK×16

ꢅ56×ꢆ

6ꢃ×ꢆ

ꢅꢆ

ꢅ

ꢅꢃ-bit×ꢃ

ꢅ.ꢅV~5.5V 16K×16

10ꢅꢃ×ꢆ

ꢅ56×ꢆ

Part No.

Timer Module

Interface

MDU Time Base Stack

Package

10-bit PTM×3

16-bit STM×1

BH66Fꢅ650

SIM/UART/SPIA

√

ꢅ

ꢆ

ꢃꢆLQFP

10-bit PTM×3

16-bit STM×1

BH66Fꢅ660

ꢃꢆLQFP

Block Diagram

Exteꢁnal

HXT/LXT

Oscillatoꢁs

Inteꢁnal

HIRC/LIRC

Oscillatoꢁs

Watchdog

Timeꢁ

ꢆ-bit

RISC

MCU

Coꢁe

Reset

Ciꢁcꢀit

Flash/EEPROM

Pꢁogꢁamming Ciꢁcꢀitꢁꢂ

Low

Voltage

Detect

Voltage

Reset

Inteꢁꢁꢀpt

Contꢁolleꢁ

EEPROM

Data

Memoꢁꢂ

Flash

Pꢁogꢁam

Memoꢁꢂ

RAM Data

Memoꢁꢂ

Time

Base

IAP

Bodꢂ Fat

Ciꢁcꢀit

ꢅꢃ-bit

Delta Sigma

A/D Conveꢁteꢁ

Mꢀltiplication/

Division

Unit

Timeꢁ

Modꢀles

I/O

UART

SPIA

SPI/I^ꢅC

LDO/PGA

Rev. 1.10

9

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Pin Assignment

ꢃ5

ꢃꢆ ꢃ7 ꢃ6

ꢃꢃ ꢃ3 ꢃꢅ ꢃ1 ꢃ0 39 3ꢆ 37

36

35

3ꢃ

33

1

ꢅ

PC0/PTP1/PTP1I

PC1/PTCK1

PCꢅ/PTPꢅ/PTPꢅI

PC3/PTCKꢅ

PD0

VOREG/VREFP

AVSS/VREFN

VCM

AN0

3

ꢃ

5

3ꢅ

31

AN1

ANꢅ

AN3

RFC

CP0N

TO

FVR

BH66F2650/BH66V2650

BH66F2660/BH66V2660

48 LQFP-A

6

7

PD1

30

ꢅ9

ꢅꢆ

ꢅ7

ꢅ6

ꢅ5

PB3/SDO/SDIA/RX

PC5/SDOA/TX

PBꢅ/SCS/SCKA

PCꢃ/SCSA

PD2/RX

ꢆ

9

10

11

1ꢅ

PD3/TX

FIR

13 1ꢃ 1516 17 1ꢆ 19 ꢅ0 ꢅ1 ꢅꢅ ꢅ3 ꢅꢃ

45

48 47 46

44 43 42 41 40 39 38 37

36

1

2

PC0/PTP1/PTP1I

PC1/PTCK1

PC2/PTP2/PTP2I

PC3/PTCK2

PD0

VOREG/VREFP

AVSS/VREFN

VCM

35

34

33

3

4

5

AN0

AN1

AN2

AN3

RFC

CP0N

TO

HVR

HIR

32

31

BH66F2650-8/BH66V2650-8

BH66F2660-8/BH66V2660-8

48 LQFP-B

6

7

PD1

30

29

28

27

26

25

PB3/SDO/SDIA/RX

PC5/SDOA/TX

PB2/SCS/SCKA

PC4/SCSA

PD2/RX

8

9

10

11

12

PD3/TX

13 14 15 16 17 18 19 20 21 22 23 24

Note:ꢀ1.ꢀIfꢀtheꢀpin-sharedꢀpinꢀfunctionsꢀhaveꢀmultipleꢀoutputs,ꢀtheꢀdesiredꢀpin-sharedꢀfunctionꢀisꢀdeterminedꢀbyꢀtheꢀ

correspondingꢀsoftwareꢀcontrolꢀbits.

2.ꢀTheꢀOCDSDAꢀandꢀOCDSCKꢀpinsꢀareꢀsuppliedꢀasꢀdedicatedꢀOCDSꢀpinsꢀandꢀasꢀsuchꢀonlyꢀavailableꢀforꢀ

theꢀBH66V2650/BH66V2660ꢀdevicesꢀwhichꢀareꢀtheꢀOCDSꢀEVꢀchipꢀforꢀtheꢀBH66F2650/BH66F2660ꢀ

devices.

Rev. 1.10

10

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Pin Description

Pin Name

Function OPT

I/T

O/T

Descriptions

Geneꢁal pꢀꢁpose I/O.

PAWU

PA0

PAPU

PAS0

ST CMOS

Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.

XT1

PTP0

PAS0 LXT

—

LXT input pin

PA0/XT1/PTP0/PTP0I/

OCDSDA/ICPDA

PAS0

—

CMOS PTM0 oꢀtpꢀt

PTM0 captꢀꢁe inpꢀt

PTP0I

ST

—

OCDSDA

ICPDA

ST CMOS OCDS addꢁess/data lineꢄ foꢁ EV chip onlꢂ

ST CMOS ICP addꢁess/data line

—

PAWU

PAPU

PAS0

Geneꢁal pꢀꢁpose I/O.

ST CMOS

PA1

Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.

PAS0

INT0

INTEG ST

INTC0

—

Exteꢁnal inteꢁꢁꢀpt 0

LVD inpꢀt

PA1/INT0/LVDIN/

PTP0B/STCK

LVDIN

PAS0

AN

—

PTP0B

CMOS PTM0 inveꢁting oꢀtpꢀt

PAS0

IFS0

STCK

ST

—

STM clock inpꢀt

PAWU

PAPU

PAS0

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.

PAꢅ

ST CMOS

PA2/XT2/PTCK0/

OCDSCK/ICPCK

XT2

PAS0

—

ST

LXT LXT output pin

PTCK0

OCDSCK

ICPCK

—

PTM0 clock inpꢀt

OCDS clock inpꢀtꢄ foꢁ EV chip onlꢂ

ICP clock line

—

PAWU

PAPU

PAS0

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.

PA3

ST CMOS

OSCꢅ

SDOA

PTP1

PAS0

—

HXT HXT output pin

CMOS SPIA seꢁial data oꢀtpꢀt

CMOS PTM1 oꢀtpꢀt

PA3/OSCꢅ/SDOA/

PTP1/PTP1I

PAS0

IFS0

PTP1I

ST

—

PTM1 captꢀꢁe inpꢀt

PAWU

PAPU

PAS1

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.

PAꢃ

ST CMOS

OSC1

SCSA

PTPꢅ

PTPꢅI

PAS1 HXT

—

HXT input pin

PAꢃ/OSC1/SCSA/

PTPꢅ/PTPꢅI

PAS1

IFS1

ST CMOS SPIA slave select pin

PAS1

—

CMOS PTMꢅ oꢀtpꢀt

PTMꢅ captꢀꢁe inpꢀt

PAS1

IFS0

ST

—

PAWU

PAPU

PAS1

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.

PA5

ST CMOS

TX

PAS1

—

CMOS UART TX serial data output pin

SPIA seꢁial clock inpꢀt

PA5/TX/SCKA/STP/

STPI

PAS1

IFS1

SCKA

ST

—

STP

PAS1

—

CMOS STM oꢀtpꢀt

STM captꢀꢁe inpꢀt

STPI

ST

—

Rev. 1.10

11

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Pin Name

Function OPT

I/T

O/T

Descriptions

PAWU

PAPU

PAS1

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.

PA6

ST CMOS

PAS1

IFS1

RX

ST

—

UART RX serial data input pin

SPIA seꢁial data inpꢀt

STM clock inpꢀt

PA6/RX/SDIA/STCK

PAS1

IFS1

SDIA

STCK

PAS1

IFS0

PAWU

PAPU

PAS1

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-ꢀp and wake-ꢀp.

PA7

ST CMOS

SDI

PAS1

ST

—

SPI (SIM) seꢁial data inpꢀt

PA7/SDI/SDA/PTCKꢅ

SDA

ST NMOS IꢅC (SIM) data line

PAS1

IFS0

PTCKꢅ

PB0

ST

—

PTMꢅ clock inpꢀt

PBPU

PBS0

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-high.

ST CMOS

PB0/SCK/SCL

SCK

SCL

PBS0

ST CMOS SPI (SIM) seꢁial clock

ST NMOS IꢅC (SIM) clock line

PBPU

PBS0

Geneꢁal pꢀꢁpose I/O.

ST CMOS

PB1

Registeꢁ enabled pꢀll-high.

PBS0

INTEG ST

INTC0

PB1/INT1/STPB

INT1

—

Exteꢁnal inteꢁꢁꢀpt 1

STPB

PBꢅ

PBS0

—

CMOS STM inveꢁting oꢀtpꢀt

Geneꢁal pꢀꢁpose I/O.

PBPU

PBS0

ST CMOS

Registeꢁ enabled pꢀll-high.

PBꢅ/SCS/SCKA

SCS

PBS0

ST CMOS SPI (SIM) slave chip select

PBS0

IFS1

SCKA

ST CMOS SPIA seꢁial clock inpꢀt

PBPU

PBS0

Geneꢁal pꢀꢁpose I/O.

ST CMOS

PB3

SDO

SDIA

Registeꢁ enabled pꢀll-high.

PBS0

—

CMOS SPI (SIM) seꢁial data oꢀtpꢀt

PB3/SDO/SDIA/RX

PBS0

IFS1

ST

—

SPIA seꢁial data inpꢀt

PBS0

IFS1

RX

ST

UART RX serial data input pin

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-high.

PBꢃ~PB7

PBn

PBPU

ST CMOS

PCPU

PCS0

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-high.

PC0

PTP1

PTP1I

PC0/PTP1/PTP1I

PCS0

—

CMOS PTM1 oꢀtpꢀt

PCS0

IFS0

ST

—

PTM1 captꢀꢁe inpꢀt

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-high.

PC1

PTCK1

PCꢅ

PCPU

—

ST CMOS

PC1/PTCK1

ST

—

PTM1 clock inpꢀt

PCPU

PCS0

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-high.

ST CMOS

PCꢅ/PTPꢅ/PTPꢅI

PTPꢅ

PTPꢅI

PCS0

—

CMOS PTMꢅ oꢀtpꢀt

PCS0

IFS0

ST

—

PTMꢅ captꢀꢁe inpꢀt

Rev. 1.10

1ꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Pin Name

PC3/PTCKꢅ

Function OPT

I/T

O/T

Descriptions

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-high.

PC3

PTCKꢅ

PCꢃ

PCPU

—

ST CMOS

ST

—

PTMꢅ clock inpꢀt

PCPU

PCS1

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-high.

ST CMOS

PCꢃ/SCSA

PCS1

IFS1

SCSA

PC5

ST CMOS SPIA slave select pin

PCPU

PCS1

Geneꢁal pꢀꢁpose I/O.

ST CMOS

Registeꢁ enabled pꢀll-high.

PC5/SDOA/TX

PAS0

PCS1

SDOA

TX

—

CMOS SPIA seꢁial data oꢀtpꢀt

PCS1

CMOS UART TX serial data output pin

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-high.

PC6~ PC7

PD0~ PD1

PCn

PCPU

ST CMOS

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-high.

PDn

PDꢅ

RX

PDPU

PDS0

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-high.

PD2/RX

PDS0

IFS1

ST

—

UART RX serial data input pin

PDPU

PDS0

Geneꢁal pꢀꢁpose I/O.

Registeꢁ enabled pꢀll-high.

PD3

ST CMOS

PD3/TX

TX

PDS0

—

CMOS UART TX serial data output pin

A/D Converter

PWR

AN

—

LDO oꢀtpꢀt pin

VOREG

Positive poweꢁ sꢀpplꢂ foꢁ VCMꢄ

A/D conveꢁteꢁꢄ PGA

VOREG/VREFP

VREFP

AVSS

—

Exteꢁnal positive ꢁefeꢁence inpꢀt of A/D conveꢁteꢁ

Negative poweꢁ sꢀpplꢂ foꢁ VCMꢄ

A/D conveꢁteꢁꢄ PGA

PWR

AVSS/VREFN

VREFN

ANn

—

AN

—

Exteꢁnal negative ꢁefeꢁence inpꢀt of A/D conveꢁteꢁ

A/D inpꢀt pin

AN0 ~ AN3

VCM

—

Exteꢁnal inpꢀt voltage foꢁ A/D conveꢁteꢁ common mode

A/D conveꢁteꢁ Common mode voltage oꢀtpꢀt

VCM

—

AN

Body Fat Circuit

RFC

CP0N

TO

RFC

CP0N

TO

—

AN

—

A/D conveꢁteꢁ analog inpꢀt

Peak detectoꢁ inpꢀt

—

AN

Operational ampliﬁer output

Right hand channel 1

Right hand channel ꢅ

Right foot channel 1

HVR

HIR

FVR

FIR

HVR

HIR

FVR

FIR

AN

—

Right foot channel ꢅ

RFꢅ

RF1

FIL

RFꢅ

RF1

FIL

Refeꢁence ꢅ impedance channel

Refeꢁence 1 impedance channel

Left foot channel ꢅ

FVL

HVL

HIL

FVL

HVL

HIL

Left foot channel 1

Left hand channel 1

Left hand channel ꢅ

RF

Refeꢁence 1/ꢅ impedance channel

Sine wave oꢀtpꢀt

SIN

Rev. 1.10

13

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

OperatingꢀTemperature

StorageꢀTemperature

..................................................................................................... -50°Cꢀtoꢀ125°C

................................................................................................... -40°Cꢀtoꢀ85°C

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Pin Name

Power

Function OPT

I/T

O/T

Descriptions

VDD

VIN

—

PWR

—

Positive poweꢁ sꢀpplꢂ

LDO inpꢀt pin

VDD/VIN

VSS

Negative poweꢁ sꢀpplꢂ.

Legend: I/T: Inpꢀt tꢂpe;

O/T: Oꢀtpꢀt tꢂpe

PWR: Poweꢁ

OPT: Optional bꢂ ꢁegisteꢁ option;

ST: Schmitt Tꢁiggeꢁ inpꢀt;

NMOS: NMOS oꢀtpꢀt;

CMOS: CMOS oꢀtpꢀt

AN: Analog signal

HXT: High frequency crystal oscillator;

LXT: Low frequency crystal oscillator

Absolute Maximum Ratings

SupplyꢀVoltageꢀ......................................................................................................V_SS-0.3V~V_SS+6.0V

InputꢀVoltageꢀ.....................................................................................................V_SS-0.3VꢀtoꢀV_DD+0.3V

I_OHꢀTotalꢀ...................................................................................................................................... -80mA

I_OLꢀTotalꢀ....................................................................................................................................... 80mA

TotalꢀPowerꢀDissipationꢀ........................................................................................................... 500mW

Note:ꢀTheseꢀareꢀstressꢀratingsꢀonly.ꢀStressesꢀexceedingꢀtheꢀrangeꢀspecifiedꢀunderꢀ“Absoluteꢀ

MaximumꢀRatings”ꢀmayꢀcauseꢀsubstantialꢀdamageꢀtoꢀtheꢀdevices.ꢀFunctionalꢀoperationꢀofꢀ

theseꢀdevicesꢀatꢀotherꢀconditionsꢀbeyondꢀthoseꢀlistedꢀinꢀtheꢀspeciﬁcationꢀisꢀnotꢀimpliedꢀandꢀ

prolongedꢀexposureꢀtoꢀextremeꢀconditionsꢀmayꢀaffectꢀdeviceꢀreliability.

D.C. Characteristics

Forꢀdataꢀinꢀtheꢀfollowingꢀtables,ꢀnoteꢀthatꢀfactorsꢀsuchꢀasꢀoscillatorꢀtype,ꢀoperatingꢀvoltage,ꢀoperatingꢀ

frequency,ꢀpinꢀloadꢀconditions,ꢀtemperatureꢀandꢀprogramꢀinstructionꢀtype,ꢀetc.,ꢀcanꢀallꢀexertꢀanꢀ

inﬂuenceꢀonꢀtheꢀmeasuredꢀvalues.

Operating Voltage Characteristics

Ta=-ꢃ0°C ~ ꢆ5°C

Symbol

Parameter

Test Conditions

f_SYS=ꢃMHz

Min.

ꢅ.ꢅ

ꢅ.7

3.3

ꢅ.ꢅ

ꢅ.7

ꢅ.ꢅ

Typ.

—

Max.

5.5

Unit

f_SYS=ꢆMHz

Opeꢁating Voltage – HXT

V

f_SYS=1ꢅMHz

f_SYS=16MHz

f_SYS=ꢃMHz

V_DD

Opeꢁating Voltage – HIRC

f_SYS=ꢆMHz

V

f_SYS=1ꢅMHz

f_SYS=3ꢅ.76ꢆkHz

f_SYS=3ꢅkHz

Opeꢁating Voltage – LXT

V

Opeꢁating Voltage – LIRC

Rev. 1.10

1ꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Standby Current Characteristics

Ta=ꢅ5°C

Test Conditions

Conditions

Max.

85°C

0.7

Symbol

Standby Mode

Min.

Typ.

Max.

Unit

V_DD

ꢅ.ꢅV

—

0.ꢅ

0.6

0.ꢆ

3V WDT off

1.0

μA

5V

0.5

1.0

1.ꢅ

SLEEP Mode

ꢅ.ꢅV

1.ꢅ

ꢅ.ꢃ

ꢅ.9

3V WDT on

1.5

3.0

3.6

5V

3.0

5.0

6.0

ꢅ.ꢅV

ꢅ.ꢃ

ꢃ.0

ꢃ.ꢆ

IDLE0 Mode – LIRC

3V f_SUBon

3.0

5.0

6.0

μA

5V

5.0

10

1ꢅ

ꢅ.ꢅV

ꢅ.ꢃ

ꢃ.0

ꢃ.ꢆ

IDLE0 Mode – LXT

3V f_SUBon

3.0

5.0

6.0

μA

5V

5.0

10

1ꢅ

ꢅ.ꢅV

0.17

0.ꢅ5

0.ꢃꢆ

0.3ꢅ

0.ꢃ7

0.91

0.60

0.6ꢆ

1.33

0.17

0.ꢅ5

0.ꢃꢆ

0.3ꢅ

0.ꢃ7

0.91

0.60

0.6ꢆ

1.33

1.10

1.ꢆ0

0.ꢅꢃ

0.35

0.67

0.ꢃ5

0.66

1.ꢅ7

0.ꢆꢃ

0.95

1.ꢆ6

0.ꢅꢃ

0.35

0.67

0.ꢃ5

0.66

1.ꢅ7

0.ꢆꢃ

0.95

1.ꢆ6

1.60

ꢅ.50

0.ꢅ6

0.3ꢆ5

0.70

0.ꢃꢆ

0.70

1.30

0.ꢆ7

1.00

1.90

0.ꢅ6

0.3ꢆ5

0.70

0.ꢃꢆ

0.70

1.30

0.ꢆ7

1.00

1.90

ꢅ.60

3V f_SUBonꢄ f_SYS=ꢃMHz

mA

5V

ꢅ.ꢅV

I_STB

IDLE1 Mode – HIRC

3V f_SUBonꢄ f_SYS=ꢆMHz

5V

ꢅ.7V

3V f_SUBonꢄ f_SYS=1ꢅMHz

5V

ꢅ.ꢅV

3V f_SUBonꢄ f_SYS=ꢃMHz

5V

ꢅ.ꢅV

3V f_SUBonꢄ f_SYS=ꢆMHz

IDLE1 Mode – HXT

5V

ꢅ.7V

3V f_SUBonꢄ f_SYS=1ꢅMHz

5V

mA

3.3V

f_SUBonꢄ f_SYS=16MHz

5V

Notes:ꢀWhenꢀusingꢀtheꢀcharacteristicꢀtableꢀdata,ꢀtheꢀfollowingꢀnotesꢀshouldꢀbeꢀtakenꢀintoꢀconsideration:

1.ꢀAnyꢀdigitalꢀinputsꢀareꢀsetupꢀinꢀaꢀnon-ﬂoatingꢀcondition.

2.ꢀAllꢀmeasurementsꢀareꢀtakenꢀunderꢀconditionsꢀofꢀnoꢀloadꢀandꢀwithꢀallꢀperipheralsꢀinꢀanꢀoffꢀstate.

3.ꢀThereꢀareꢀnoꢀDCꢀcurrentꢀpaths.

4.ꢀAllꢀStandbyꢀCurrentꢀvaluesꢀareꢀtakenꢀafterꢀaꢀHALTꢀinstructionꢀexecutionꢀthusꢀstoppingꢀallꢀinstructionꢀ

execution.

Rev. 1.10

15

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Operating Current Characteristics

Ta=ꢅ5°C

Test Conditions

Conditions

Symbol

Operating Mode

Min. Typ. Max. Unit

V_DD

ꢅ.ꢅV

—

ꢆ

16

ꢅ0

SLOW Mode – LIRC

3V f_SYS= 3ꢅkHz

10

μA

5V

30

50

ꢅ.ꢅV

ꢆ

16

SLOW Mode – LXT

3V f_SYS= 3ꢅ76ꢆHz

10

ꢅ0

5V

30

50

ꢅ.ꢅV

0.3

0.ꢃ

0.ꢆ

0.6

0.ꢆ

1.6

1.0

1.ꢅ

ꢅ.ꢃ

0.ꢃ

0.5

1.0

0.ꢆ

1.0

ꢅ.0

1.ꢅ

1.5

3.0

3.ꢅ

ꢃ.0

0.5

0.6

1.ꢅ

1.0

1.ꢅ

ꢅ.ꢃ

1.ꢃ

1.ꢆ

3.6

0.6

0.75

1.5

1.ꢅ

1.5

3.0

ꢅ.ꢅ

ꢅ.75

ꢃ.5

ꢃ.ꢆ

6.0

3V f_SYS= ꢃMHz

mA

5V

ꢅ.ꢅV

FAST Mode – HIRC

3V f_SYS= ꢆMHz

5V

ꢅ.7V

I_DD

3V f_SYS= 1ꢅMHz

5V

ꢅ.ꢅV

3V f_SYS= ꢃMHz

5V

ꢅ.ꢅV

3V f_SYS= ꢆMHz

FAST Mode – HXT

5V

ꢅ.7V

3V f_SYS= 1ꢅMHz

5V

mA

3.3V

f_SYS= 16MHz

5V

Notes:ꢀWhenꢀusingꢀtheꢀcharacteristicꢀtableꢀdata,ꢀtheꢀfollowingꢀnotesꢀshouldꢀbeꢀtakenꢀintoꢀconsideration:

1.ꢀAnyꢀdigitalꢀinputsꢀareꢀsetupꢀinꢀaꢀnon-ﬂoatingꢀcondition.

2.ꢀAllꢀmeasurementsꢀareꢀtakenꢀunderꢀconditionsꢀofꢀnoꢀloadꢀandꢀwithꢀallꢀperipheralsꢀinꢀanꢀoffꢀstate.

3.ꢀThereꢀareꢀnoꢀDCꢀcurrentꢀpaths.

4.ꢀAllꢀOperatingꢀCurrentꢀvaluesꢀareꢀmeasuredꢀusingꢀaꢀcontinuousꢀNOPꢀinstructionꢀprogramꢀloop.

Rev. 1.10

16

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

A.C. Characteristics

Forꢀdataꢀinꢀtheꢀfollowingꢀtables,ꢀnoteꢀthatꢀfactorsꢀsuchꢀasꢀoscillatorꢀtype,ꢀoperatingꢀvoltage,ꢀoperatingꢀ

frequencyꢀandꢀtemperatureꢀetc.,ꢀcanꢀallꢀexertꢀanꢀinﬂuenceꢀonꢀtheꢀmeasuredꢀvalues.

High Speed Internal Oscillator – HIRC – Frequency Accuracy

DuringꢀtheꢀprogramꢀwritingꢀoperationꢀtheꢀwriterꢀwillꢀtrimꢀtheꢀHIRCꢀoscillatorꢀatꢀaꢀuserꢀselectedꢀ

HIRCꢀfrequencyꢀandꢀuserꢀselectedꢀvoltageꢀofꢀeitherꢀ3Vꢀorꢀ5V.ꢀ

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

V_DD

Temp.

ꢅ5°C

-1%

-ꢅ%

ꢃ

+1%

+ꢅ%

3V/5V

-ꢃ0°C ~ ꢆ5°C

ꢅ5°C

ꢃMHz Wꢁiteꢁ Tꢁimmed HIRC

Fꢁeqꢀencꢂ

MHz

-ꢅ.5%

-3%

ꢃ

+ꢅ.5%

+3%

ꢅ.ꢅV~5.5V

3V/5V

-ꢃ0°C ~ ꢆ5°C

ꢅ5°C

ꢃ

-1%

ꢆ

+1%

-ꢃ0°C ~ ꢆ5°C

ꢅ5°C

-ꢅ%

ꢆ

+ꢅ%

ꢆMHz Wꢁiteꢁ Tꢁimmed HIRC

Fꢁeqꢀencꢂ

f_HIRC

MHz

-ꢅ.5%

-3%

ꢆ

+ꢅ.5%

-3%

ꢅ.ꢅV~5.5V

5V

-ꢃ0°C ~ ꢆ5°C

ꢅ5°C

ꢆ

-1%

1ꢅ

+1%

-ꢃ0°C ~ ꢆ5°C

ꢅ5°C

-ꢅ%

+ꢅ%

1ꢅMHz Wꢁiteꢁ Tꢁimmed HIRC

Fꢁeqꢀencꢂ

-ꢅ.5%

-3%

+ꢅ.5%

+3%

ꢅ.7V~5.5V

-ꢃ0°C ~ ꢆ5°C

Notes:ꢀ1.ꢀTheꢀ3V/5VꢀvaluesꢀforꢀV_DDꢀareꢀprovidedꢀasꢀtheseꢀareꢀtheꢀtwoꢀselectableꢀﬁxedꢀvoltagesꢀatꢀwhichꢀtheꢀHIRCꢀ

frequencyꢀisꢀtrimmedꢀbyꢀtheꢀwriter.

2.ꢀTheꢀrowꢀbelowꢀtheꢀ3V/5VꢀtrimꢀvoltageꢀrowꢀisꢀprovidedꢀtoꢀshowꢀtheꢀvaluesꢀforꢀtheꢀfullꢀV_DDꢀrangeꢀoperatingꢀ

voltage.ꢀItꢀisꢀrecommendedꢀthatꢀtheꢀtrimꢀvoltageꢀisꢀﬁxedꢀatꢀ3Vꢀforꢀapplicationꢀvoltageꢀrangesꢀfromꢀ2.2Vꢀ

toꢀ3.6Vꢀandꢀﬁxedꢀatꢀ5Vꢀforꢀapplicationꢀvoltageꢀrangesꢀfromꢀ3.3Vꢀtoꢀ5.5V.

3.ꢀTheꢀminimumꢀandꢀmaximumꢀtoleranceꢀvaluesꢀprovidedꢀinꢀtheꢀtableꢀareꢀonlyꢀforꢀtheꢀfrequencyꢀatꢀwhichꢀ

theꢀwriterꢀtrimsꢀtheꢀHIRCꢀoscillator.ꢀAfterꢀtrimmingꢀatꢀthisꢀchosenꢀspecificꢀfrequencyꢀanyꢀchangeꢀinꢀ

HIRCꢀoscillatorꢀfrequencyꢀusingꢀtheꢀoscillatorꢀregisterꢀcontrolꢀbitsꢀbyꢀtheꢀapplicationꢀprogramꢀwillꢀgiveꢀaꢀ

frequencyꢀtoleranceꢀtoꢀwithinꢀ±20%.

Low Speed Internal Oscillator Characteristics – LIRC

Ta=25°C, unless otherwise speciﬁed

Test Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

Temp.

ꢅ5°C

-5%

3ꢅ

+5%

f_LIRC

LIRC Fꢁeqꢀencꢂ

ꢅ.ꢅV~5.5V

kHz

-ꢃ0°C~ꢆ5°C

-10%

+10%

Rev. 1.10

17

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Operating Frequency Characteristic Curves

System Operating Frequency

16MHz

1ꢅMHz

ꢆMHz

ꢃMHz

ꢅ.ꢅV

ꢅ.7V

3.3V

5.5V

Operating Voltage

System Start Up Time Characteristics

Ta=-ꢃ0°C~ꢆ5°C

Min. Typ. Max. Unit

Test Conditions

Symbol

Parameter

V_DD

—

Conditions

f_SYS= f_H~ f_H/6ꢃꢄ f_H= f_HXT

f_SYS= f_H~ f_H/6ꢃꢄ f_H= f_HIRC

f_SYS= f_SUB= f_LXT

—

1ꢅꢆ

16

—

t_HXT

t_HIRC

t_LXT

Sꢂstem Staꢁt-ꢀp Time

Wake-ꢀp fꢁom condition

wheꢁe f_SYSis off

—

10ꢅꢃ

ꢅ

—

f_SYS= f_SUB= f_LIRC

t_LIRC

f_SYS= f_H~ f_H/6ꢃꢄ

f_H= f_HXToꢁ f_HIRC

Sꢂstem Staꢁt-ꢀp Time

Wake-ꢀp fꢁom condition

wheꢁe f_SYSis on

t_SST

—

ꢅ

—

t_H

—

f_SYS= f_SUB= f_LXToꢁ f_LIRC

—

ꢅ

—

t_SUB

t_HXT

t_HIRC

t_LXT

f_HXTswitches from off → on

f_HIRCswitches fꢁom off → on

f_LXTswitches from off → on

10ꢅꢃ

16

Sꢂstem Speed Switch Time

FAST to SLOW Mode oꢁ

SLOW to FAST Mode

10ꢅꢃ

Sꢂstem Reset Delaꢂ Time

Reset soꢀꢁce fꢁom Poweꢁ-on ꢁeset oꢁ

LVR haꢁdwaꢁe ꢁeset

—

RR_POR=5V/ms

—

ꢃꢅ

ꢃꢆ

5ꢃ

ms

t_RSTD

Sꢂstem Reset Delaꢂ Time

LVRC/WDTC/RSTC softwaꢁe ꢁeset

Sꢂstem Reset Delaꢂ Time

Reset source from WDT overﬂow

—

1ꢃ

ꢃ5

16

90

1ꢆ

ms

t_SRESET

Minimꢀm Softwaꢁe Reset Width to Reset

1ꢅ0

μs

Notes:ꢀ1.ForꢀtheꢀSystemꢀStart-upꢀtimeꢀvalues,ꢀwhetherꢀf_SYSꢀisꢀonꢀorꢀoffꢀdependsꢀuponꢀtheꢀmodeꢀtypeꢀandꢀtheꢀchosenꢀ

f_SYSꢀsystemꢀoscillator.ꢀDetailsꢀareꢀprovidedꢀinꢀtheꢀSystemꢀOperatingꢀModesꢀsection.

2.ꢀTheꢀtimeꢀunits,ꢀshownꢀbyꢀtheꢀsymbolsꢀt_HXT,ꢀt_HIRCꢀetc.ꢀareꢀtheꢀinverseꢀofꢀtheꢀcorrespondingꢀfrequencyꢀvaluesꢀ

asꢀprovidedꢀinꢀtheꢀfrequencyꢀtables.ꢀForꢀexampleꢀt_HIRCꢀ=ꢀ1/f_HIRC,ꢀt_SYSꢀ=ꢀ1/f_SYSꢀetc.

3.ꢀIfꢀtheꢀLIRCꢀisꢀusedꢀasꢀtheꢀsystemꢀclockꢀandꢀifꢀitꢀisꢀoffꢀwhenꢀinꢀtheꢀSLEEPꢀMode,ꢀthenꢀanꢀadditionalꢀLIRCꢀ

startꢀupꢀtime,ꢀt_START,ꢀasꢀprovidedꢀinꢀtheꢀLIRCꢀfrequencyꢀtable,ꢀmustꢀbeꢀaddedꢀtoꢀtheꢀt_SSTꢀtimeꢀinꢀtheꢀtableꢀ

above.

4.ꢀTheꢀSystemꢀSpeedꢀSwitchꢀTimeꢀisꢀeffectivelyꢀtheꢀtimeꢀtakenꢀforꢀtheꢀnewlyꢀactivatedꢀoscillatorꢀtoꢀstartꢀup.

Rev. 1.10

1ꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Input/Output Characteristics

Ta=ꢅ5°C

Test Conditions

Conditions

Symbol

V_IL

Parameter

Min. Typ. Max. Unit

V_DD

5V

—

0

—

3ꢅ

65

1.5

0.ꢅV_DD

5.0

Inpꢀt Low Voltage foꢁ I/O Poꢁts

Inpꢀt High Voltage foꢁ I/O Poꢁts

Sink Cꢀꢁꢁent foꢁ I/O Poꢁts

—

V

5V

—

3.5

0.ꢆV_DD

16

V_IH

V_DD

—

3V

5V

I_OL

V_OL=0.1V_DD

mA

3ꢅ

—

V_OH= 0.9V_DD

ꢄ

3V

5V

3V

5V

3V

5V

3V

5V

SLEDCn[m+1ꢄ m] = 00B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

-0.7 -1.5

-1.5 -ꢅ.9

-1.3 -ꢅ.5

-ꢅ.5 -5.1

-1.ꢆ -3.6

-3.6 -7.3

—

V_OH= 0.9V_DD

ꢄ

SLEDCn[m+1ꢄ m] = 00B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

V_OH= 0.9V_DD

ꢄ

SLEDCn[m+1ꢄ m] = 01B

(n = 0ꢄ1;m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

V_OH= 0.9V_DD

ꢄ

SLEDCn[m+1ꢄ m] = 01B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

I_OH

Soꢀꢁce Cꢀꢁꢁent foꢁ I/O Poꢁts

mA

V_OH= 0.9V_DD

ꢄ

SLEDCn[m+1ꢄ m] = 10B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

V_OH= 0.9V_DD

ꢄ

SLEDCn[m+1ꢄ m] = 10B

(n = 0ꢄ1;m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

V_OH= 0.9V_DD

ꢄ

SLEDCn[m+1ꢄ m] = 11B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

-ꢃ

-ꢆ

V_OH= 0.9V_DD

ꢄ

SLEDCn[m+1ꢄ m] = 11B

-16

(n = 0ꢄ1;m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

3V

5V

I_OL= 16mA

I_OL= 3ꢅmA

—

0.3

0.5

V_OL

Oꢀtpꢀt Low Voltage foꢁ I/O Poꢁts

V

Rev. 1.10

19

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Test Conditions

Min. Typ. Max. Unit

Conditions

Symbol

Parameter

V_DD

I_OH= -0.7mAꢄ

3V

SLEDCn[m+1ꢄ m] = 00B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

ꢅ.7

ꢃ.5

ꢅ.7

ꢃ.5

ꢅ.7

ꢃ.5

ꢅ.7

ꢃ.5

—

I_OH= -1.5mAꢄ

SLEDCn[m+1ꢄ m] = 00B

(n = 0ꢄ1;m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

5V

3V

5V

3V

5V

3V

5V

I_OH= -1.3mAꢄ

SLEDCn[m+1ꢄ m] = 01B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

I_OH= -ꢅ.5mAꢄ

SLEDCn[m+1ꢄ m] = 01B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

V_OH

Oꢀtpꢀt High Voltage foꢁ I/O Poꢁts

V

I_OH= -1.ꢆmAꢄ

SLEDCn[m+1ꢄ m] = 10B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

I_OH= -3.6mAꢄ

SLEDCn[m+1ꢄ m] = 10B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

I_OH= -ꢃmAꢄ

SLEDCn[m+1ꢄ m] = 11B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

I_OH= -ꢆmAꢄ

SLEDCn[m+1ꢄ m] = 11B

(n = 0ꢄ1; m = 0 oꢁ ꢅ oꢁ ꢃ oꢁ 6)

3V

5V

ꢅ0

10

—

60

30

—

100

50

R_PH

Pꢀll-High Resistance foꢁ I/O Poꢁts ^(Note)

Inpꢀt Leakage Cꢀꢁꢁent

—

kΩ

I_LEAK

t_TPI

t_TCK

t_INT

3V/5V V_IN= V_DDoꢁ V_IN= V_SS

±1

μA

μs

STPIꢄ PTPnI Inpꢀt Pin Minimꢀm Pꢀlse

Width

—

0.3

10

—

STCKꢄ PTCKn Inpꢀt Pin Minimꢀm

Pꢀlse Width

μs

Exteꢁnal Inteꢁꢁꢀpt Minimꢀm Pꢀlse

Width

Note:ꢀTheꢀR_PHꢀinternalꢀpullꢀhighꢀresistanceꢀvalueꢀisꢀcalculatedꢀbyꢀconnectingꢀtoꢀgroundꢀandꢀenablingꢀtheꢀinputꢀpinꢀ

withꢀaꢀpull-highꢀresistorꢀandꢀthenꢀmeasuringꢀtheꢀinputꢀsinkꢀcurrentꢀatꢀtheꢀspeciﬁedꢀsupplyꢀvoltageꢀlevel.ꢀ

DividingꢀtheꢀvoltageꢀbyꢀthisꢀmeasuredꢀcurrentꢀprovidesꢀtheꢀR_PHꢀvalue.

Memory Characteristics

Ta=-ꢃ0°C~ꢆ5°C

Test Conditions

Symbol

Parameter

V_DDfoꢁ Read / Wꢁite

Min. Typ. Max. Unit

V_DD

Conditions

V_RW

—

V_DDmin

—

V_DDmax

V

Program Flash / Data EEPROM Memory

t_DEW

I_DDPGM

E_P

Eꢁase / Wꢁite Cꢂcle Time

Pꢁogꢁamming / Eꢁase Cꢀꢁꢁent on V_DD

Cell Endꢀꢁance

—

ꢅ.ꢅ

—

ꢅ.5

—

ꢅ.ꢆ

5.0

—

ms

mA

100K

—

E/W

Yeaꢁ

t_RETD

ROM Data Retention Time

Ta = ꢅ5°C

ꢃ0

—

RAM Data Memory

V_DR

RAM Data Retention Voltage

—

1.0

—

V

Rev. 1.10

ꢅ0

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

LVD/LVR Electrical Characteristics

Ta=ꢅ5°C

Test Conditions

Symbol

Parameter

Opeꢁating Voltage

Min. Typ. Max. Unit

V_DD

—

Conditions

V_DD

—

ꢅ.ꢅ

—

5.5

V

LVR enableꢄ voltage select ꢅ.10V

LVR enableꢄ voltage select ꢅ.55V

LVR enableꢄ voltage select 3.15V

LVR enableꢄ voltage select 3.ꢆ0V

LVD enableꢄ voltage select 1.0ꢃV

LVD enableꢄ voltage select ꢅ.ꢅ0V

LVD enableꢄ voltage select ꢅ.ꢃ0V

LVD enableꢄ voltage select ꢅ.70V

LVD enableꢄ voltage select 3.00V

LVD enableꢄ voltage select 3.30V

LVD enableꢄ voltage select 3.60V

LVD enableꢄ voltage select ꢃ.00V

-5%

ꢅ.1

+5%

-5% ꢅ.55 +5%

-5% 3.15 +5%

V_LVR

Low Voltage Reset Voltage

V

-5%

3.ꢆ

+5%

-10% 1.0ꢃ +10%

-5%

—

ꢅ.ꢅ

ꢅ.ꢃ

ꢅ.7

3.0

3.3

3.6

ꢃ.0

—

+5%

1ꢆ

V_LVD

Low Voltage Detection Voltage

V

3V LVD enableꢄ LVR enableꢄ VBGEN=0

5V LVD enableꢄ LVR enableꢄ VBGEN=0

3V LVD enableꢄ LVR enableꢄ VBGEN=1

5V LVD enableꢄ LVR enableꢄ VBGEN=1

—

ꢅ0

ꢅ5

I_LVRLVDBGOpeꢁating Cꢀꢁꢁent

μA

μs

—

150

30

—

ꢅ5

Foꢁ LVR enableꢄ VBGEN=0ꢄ

LVD off → on

—

15

t_LVDS

LVDO Stable Time

Foꢁ LVR disableꢄ VBGEN=0ꢄ

LVD off → on

—

150

ꢃꢆ0

ꢅꢃ0

Minimꢀm Low Voltage Width to

Reset

t_LVR

t_LVD

—

1ꢅ0

60

ꢅꢃ0

1ꢅ0

μs

Minimꢀm Low Voltage Width to

Inteꢁꢁꢀpt

I_LVR

I_LVD

Additional Cꢀꢁꢁent foꢁ LVR Enable

Additional Cꢀꢁꢁent foꢁ LVD Enable

—

LVD disableꢄ VBGEN=0

LVR disableꢄ VBGEN=0

—

ꢅꢃ

μA

24-bit A/D Converter Electrical Characteristics

LDO + VCM Test conditions: MCU HALTꢄ otheꢁ fꢀnction disable;

V_DD=V_INꢄ Ta=ꢅ5°C

Test Conditions

Symbol

V_IN

I_Q

Parameter

Min.

Typ.

Max.

Unit

V_DD

Conditions

LDO Inpꢀt Voltage

—

ꢅ.6

—

5.5

V

LDOVS[1:0]=00Bꢄ V_IN=3.6Vꢄ

No load

LDO Qꢀiescent Cꢀꢁꢁent

—

ꢃ00

5ꢅ0

μA

LDOVS[1:0]=00Bꢄ V_IN=3.6Vꢄ

I_LOAD=0.1mA

ꢅ.ꢃ

ꢅ.6

ꢅ.9

3.3

LDOVS[1:0]=01Bꢄ V_IN=3.6Vꢄ

I_LOAD=0.1mA

V_{OUT_LDO}LDO Oꢀtpꢀt Voltage

-5%

—

+ 5%

V

LDOVS[1:0]=10Bꢄ V_IN=3.6Vꢄ

I_LOAD=0.1mA

LDOVS[1:0]=11Bꢄ V_IN=3.6Vꢄ

I_LOAD=0.1mA

LDOVS[1:0]=00Bꢄ V_IN=V_{OUT_LDO}+0.ꢅVꢄ

0mA ≤ I_LOAD≤ 10mA

ΔV_LOAD

LDO Load Regꢀlation^{(Note 1)}

0.105 0.ꢅ1 %/mA

Rev. 1.10

ꢅ1

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

LDOVS[1:0]=00Bꢄ V_IN=3.6Vꢄ

I_LOAD=10mA, ∆V_{OUT_LDO}=ꢅ%

—

ꢅꢅ0

ꢅ00

1ꢆ0

160

LDOVS[1:0]=01Bꢄ V_IN=3.6Vꢄ

I_LOAD=10mA, ∆V_{OUT_LDO}=ꢅ%

—

V_{DROP_LDO}LDO Dꢁopoꢀt Voltage^(Noteꢅ)

mV

LDOVS[1:0]=10Bꢄ V_IN=3.6Vꢄ

I_LOAD=10mA, ∆V_{OUT_LDO}=ꢅ%

LDOVS[1:0]=11Bꢄ V_IN=3.6Vꢄ

I_LOAD=10mA, ∆V_{OUT_LDO}=ꢅ%

LDO Tempeꢁatꢀꢁe

Coefﬁcient

Ta=-ꢃ0°C~ꢆ5°Cꢄ LDOVS[1:0]=00Bꢄ

V_IN=3.6Vꢄ I_LOAD=100μA

TC_LDO

0.ꢃꢆ mV/°C

LDOVS[1:0]=00B, 2.6V ≤ V_IN≤ 5.5V,

I_LOAD=100μA

0.7

0.ꢅ

%/V

ΔV_{LINE_LDO}LDO Line Regꢀlation

—

LDOVS[1:0]=00B, 2.6V ≤ V_IN≤ 3.6V,

I_LOAD=100μA

—

-5%

—

%/V

V

V_{OUT_VCM}VCM Oꢀtpꢀt Voltage

—

V_OREG=3.3Vꢄ No load

1.ꢅ5 + 5%

VCM Tempeꢁatꢀꢁe

Coefﬁcient

Ta=-ꢃ0°C~ꢆ5°Cꢄ V_OREG=3.3Vꢄ

I_LOAD=10μA

TC_VCM

—

0.ꢅꢃ mV/°C

ΔV_{LINE_VCM}VCM Line Regꢀlation

—

2.4V ≤ V_OREG≤ 3.3V, No load

—

0.3

10

%/V

ms

t_VCMS

VCM Tꢀꢁn on Stable Time

V_OREG=3.3Vꢄ No load

Soꢀꢁce Cꢀꢁꢁent foꢁ VCM

Oꢀtpꢀt Pin

I_OH

—

V_OREG=3.3V, ∆V_{OUT_VCM}=-ꢅ%

V_OREG=3.3V, ∆V_{OUT_VCM}=+ꢅ%

1

—

mA

Sink Cꢀꢁꢁent foꢁ VCM

Oꢀtpꢀt Pin

I_OL

A/D Converter & A/D Converter Internal Reference Voltage (Delta Sigma A/D Converter)

—

LDOEN=0

LDOEN=1

ꢅ.ꢃ

—

3.3

Sꢀpplꢂ Voltage foꢁ VCMꢄ

A/D conveꢁteꢁꢄ PGAꢄ OPA

V_OREG

V

VCM enableꢄ VRBUFP=1 and

VRBUFN=1

—

750

600

900

750

Additional Cꢀꢁꢁent foꢁ A/D

Conveꢁteꢁ Enable

I_ADC

μA

VCM enableꢄ VRBUFP=0 and

VRBUFN=0

I_ADSTB

N_R

Standbꢂ Cꢀꢁꢁent

Resolꢀtion

—

MCU enteꢁs SLEEP modeꢄ No Load

—

1

μA

ꢅꢃ

Bit

V_OREG=3.3Vꢄ V_REF=1.ꢅ5Vꢄ

∆SI=±450mV, PGA gain=1

INL

Integꢁal Non-lineaꢁitꢂ

—

±50

±ꢅ00

ppm

NFB

Noise Fꢁee Bits

—

PGA gain=1ꢅꢆꢄ Data ꢁate=10Hz

—

15.ꢃ

1ꢆ.1

—

Bit

ENOB

Effective Nꢀmbeꢁ of Bits

A/D Conveꢁteꢁ

Clock Fꢁeqꢀencꢂ

f_ADCK

f_ADO

V_REFP

V_REFN

—

ꢃ0

ꢃ09.6

ꢃꢃ0

kHz

Hz

V

—

f_MCLK=ꢃMHzꢄ FLMS[ꢅ:0]=000B

f_MCLK=ꢃMHzꢄ FLMS[ꢅ:0]=010B

ꢃ

—

5ꢅ1

A/D Conveꢁteꢁ

Oꢀtpꢀt Data Rate

10

130ꢅ

V_REFN

+ 0.ꢆ

—

V_OREG

VREFS=1ꢄ VRBUFP=0ꢄ VRBUFN=0

Exteꢁnal Refeꢁence Inpꢀt

Voltage

V_REFP

- 0.ꢆ

—

0

—

V

V_REF

VGS[1:0]=00Bꢄ V_REF=V_REFP−V_REFN

0.ꢆ0

1.75

PGA

Common Mode Voltage

Range

V_OREG

- 0.95

V_{CM_PGA}

—

0.ꢃ

—

V

Diffeꢁential Inpꢀt Voltage

Range

-V_REF

/Gain

+V_REF

/Gain

ΔD_I

Gain=PGS × AGS

Rev. 1.10

ꢅꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

Temperature Sensor

Ta=-ꢃ0°C~ꢆ5°Cꢄ V_REF=1.ꢅ5Vꢄ

VGS[1:0]=00B (Gain=1)ꢄ VRBUFP=0ꢄ

VRBUFN=0

Tempeꢁatꢀꢁe Sensoꢁ

Temperature Coefﬁcient

TC_TS

—

175

—

μV/°C

Note:ꢀ1.ꢀLoadꢀregulationꢀisꢀmeasuredꢀatꢀaꢀconstantꢀjunctionꢀtemperature,ꢀusingꢀpulseꢀtestingꢀwithꢀaꢀlowꢀONꢀtimeꢀ

andꢀisꢀguaranteedꢀupꢀtoꢀtheꢀmaximumꢀpowerꢀdissipation.ꢀPowerꢀdissipationꢀisꢀdeterminedꢀbyꢀtheꢀinput/

outputꢀdifferentialꢀvoltageꢀandꢀtheꢀoutputꢀcurrent.ꢀGuaranteedꢀmaximumꢀpowerꢀdissipationꢀwillꢀnotꢀbeꢀ

availableꢀoverꢀtheꢀfullꢀinput/outputꢀrange.ꢀTheꢀmaximumꢀallowableꢀpowerꢀdissipationꢀatꢀanyꢀambientꢀ

temperatureꢀisꢀP_D=(T_J(MAX)-Ta)/θ_JA.

2.ꢀDropoutꢀvoltageꢀisꢀdeﬁnedꢀasꢀtheꢀinputꢀvoltageꢀminusꢀtheꢀoutputꢀvoltageꢀthatꢀproducesꢀaꢀ2%ꢀchangeꢀinꢀtheꢀ

outputꢀvoltageꢀfromꢀtheꢀvalueꢀatꢀappointedꢀV_IN.

12-bit D/A Converter Electrical Characteristics

Ta=ꢅ5°C

Test Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

V_DD

—

Conditions

V_DACO

V_REF

Oꢀtpꢀt Voltage Range

Refeꢁence Voltage

—

V_SS

—

V_REF

V_DD

V

—

1.05

Additional Cꢀꢁꢁent foꢁ D/A

Conveꢁteꢁ Enable

I_DAC

—

V_REF=5V

—

ꢃ50

μA

DNL

INL

Diffeꢁential Non-lineaꢁitꢂ

Integꢁal Non-lineaꢁitꢂ

—

2.4V ≤ V_DD≤ 5.5V

—

±ꢃ

±ꢆ

LSB

Operational Ampliﬁer Electrical Characteristics (Body Fat Circuit)

Ta=ꢅ5°C

Test Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

V_DD

Conditions

V_DD

I_CC

Sꢀpplꢂ Voltage

Supply Current Per Signal Ampliﬁer

—

ꢅ.ꢃ

—

5.5

V

5V Io=0A

150

360

500

μA

OP0, OP1, OP2

SR

Slew Rate at Unitꢂ Gain

Gain Bandwidth Pꢁodꢀct

3V R_L=100kΩ, C_L=100pF

7.5

—

ꢅ

V/μs

GBW

MHz

Rev. 1.10

ꢅ3

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Power-on Reset Characteristics

Ta=ꢅ5°C

Test Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

V_DD

Conditions

V_POR

V_DDStaꢁt Voltage to Ensꢀꢁe Poweꢁ-on Reset

V_DDRising Rate to Ensꢀꢁe Poweꢁ-on Reset

—

100

—

mV

RR_POR

—

0.035

V/ms

Minimꢀm Time foꢁ V_DDStaꢂs at V_PORto

Ensꢀꢁe Poweꢁ-on Reset

t_POR

1

—

ms

V_DD

t_POR

RR_POR

V_POR

Time

System Architecture

Aꢀkeyꢀfactorꢀinꢀtheꢀhigh-performanceꢀfeaturesꢀofꢀtheꢀrangeꢀofꢀmicrocontrollersꢀisꢀattributedꢀtoꢀtheirꢀ

internalꢀsystemꢀarchitecture.ꢀThisꢀseriesꢀofꢀdevicesꢀtakeꢀadvantageꢀofꢀtheꢀusualꢀfeaturesꢀfoundꢀwithinꢀ

RISCꢀmicrocontrollersꢀprovidingꢀincreasedꢀspeedꢀofꢀoperationꢀandꢀenhancedꢀperformance.ꢀTheꢀ

pipeliningꢀschemeꢀisꢀimplementedꢀinꢀsuchꢀaꢀwayꢀthatꢀinstructionꢀfetchingꢀandꢀinstructionꢀexecutionꢀ

areꢀoverlapped,ꢀhenceꢀinstructionsꢀareꢀeffectivelyꢀexecutedꢀinꢀoneꢀorꢀtwoꢀcyclesꢀforꢀmostꢀofꢀtheꢀ

standardꢀorꢀextendedꢀinstructionsꢀrespectively.ꢀTheꢀexceptionsꢀtoꢀthisꢀareꢀbranchꢀorꢀcallꢀinstructionsꢀ

whichꢀneedꢀoneꢀmoreꢀcycle.ꢀAnꢀ8-bitꢀwideꢀALUꢀisꢀusedꢀinꢀpracticallyꢀallꢀinstructionꢀsetꢀoperations,ꢀ

whichꢀcarriesꢀoutꢀarithmeticꢀoperations,ꢀlogicꢀoperations,ꢀrotation,ꢀincrement,ꢀdecrement,ꢀbranchꢀ

decisions,ꢀetc.ꢀTheꢀinternalꢀdataꢀpathꢀisꢀsimplifiedꢀbyꢀmovingꢀdataꢀthroughꢀtheꢀAccumulatorꢀandꢀ

theꢀALU.ꢀCertainꢀinternalꢀregistersꢀareꢀimplementedꢀinꢀtheꢀDataꢀMemoryꢀandꢀcanꢀbeꢀdirectlyꢀ

orꢀindirectlyꢀaddressed.ꢀTheꢀsimpleꢀaddressingꢀmethodsꢀofꢀtheseꢀregistersꢀalongꢀwithꢀadditionalꢀ

architecturalꢀfeaturesꢀensureꢀthatꢀaꢀminimumꢀofꢀexternalꢀcomponentsꢀisꢀrequiredꢀtoꢀprovideꢀaꢀ

functionalꢀI/OꢀorꢀA/Dꢀcontrolꢀsystemꢀwithꢀmaximumꢀreliabilityꢀandꢀflexibility.ꢀThisꢀmakesꢀtheꢀ

devicesꢀsuitableꢀforꢀlow-cost,ꢀhigh-volumeꢀproductionꢀforꢀcontrollerꢀapplications.

Clocking and Pipelining

Theꢀmainꢀsystemꢀclock,ꢀderivedꢀfromꢀeitherꢀaꢀHXT,ꢀLXT,ꢀHIRCꢀorꢀLIRCꢀoscillatorꢀisꢀsubdividedꢀ

intoꢀfourꢀinternallyꢀgeneratedꢀnon-overlappingꢀclocks,ꢀT1~T4.ꢀTheꢀProgramꢀCounterꢀisꢀincrementedꢀ

atꢀtheꢀbeginningꢀofꢀtheꢀT1ꢀclockꢀduringꢀwhichꢀtimeꢀaꢀnewꢀinstructionꢀisꢀfetched.ꢀTheꢀremainingꢀ

T2~T4ꢀclocksꢀcarryꢀoutꢀtheꢀdecodingꢀandꢀexecutionꢀfunctions.ꢀInꢀthisꢀway,ꢀoneꢀT1~T4ꢀclockꢀ

cycleꢀformsꢀoneꢀinstructionꢀcycle.ꢀAlthoughꢀtheꢀfetchingꢀandꢀexecutionꢀofꢀinstructionsꢀtakesꢀplaceꢀ

inꢀconsecutiveꢀinstructionꢀcycles,ꢀtheꢀpipeliningꢀstructureꢀofꢀtheꢀmicrocontrollerꢀensuresꢀthatꢀ

instructionsꢀareꢀeffectivelyꢀexecutedꢀinꢀoneꢀinstructionꢀcycle.ꢀTheꢀexceptionꢀtoꢀthisꢀareꢀinstructionsꢀ

whereꢀtheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀareꢀchanged,ꢀsuchꢀasꢀsubroutineꢀcallsꢀorꢀjumps,ꢀinꢀwhichꢀ

caseꢀtheꢀinstructionꢀwillꢀtakeꢀoneꢀmoreꢀinstructionꢀcycleꢀtoꢀexecute.

Rev. 1.10

ꢅꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

f_SYS

(Sꢂstem Clock)

Phase Clock T1

Phase Clock Tꢅ

Phase Clock T3

Phase Clock Tꢃ

Pꢁogꢁam Coꢀnteꢁ

Pipelining

PC

PC+1

PC+ꢅ

Fetch Inst. (PC)

Execꢀte Inst. (PC-1)

Fetch Inst. (PC+1)

Execꢀte Inst. (PC)

Fetch Inst. (PC+ꢅ)

Execꢀte Inst. (PC+1)

System Clocking and Pipelining

Forꢀinstructionsꢀinvolvingꢀbranches,ꢀsuchꢀasꢀjumpꢀorꢀcallꢀinstructions,ꢀtwoꢀmachineꢀcyclesꢀareꢀ

requiredꢀtoꢀcompleteꢀinstructionꢀexecution.ꢀAnꢀextraꢀcycleꢀisꢀrequiredꢀasꢀtheꢀprogramꢀtakesꢀoneꢀ

cycleꢀtoꢀﬁrstꢀobtainꢀtheꢀactualꢀjumpꢀorꢀcallꢀaddressꢀandꢀthenꢀanotherꢀcycleꢀtoꢀactuallyꢀexecuteꢀtheꢀ

branch.ꢀTheꢀrequirementꢀforꢀthisꢀextraꢀcycleꢀshouldꢀbeꢀtakenꢀintoꢀaccountꢀbyꢀprogrammersꢀinꢀtimingꢀ

sensitiveꢀapplications.

Fetch Inst. 1

Execꢀte Inst. 1

Fetch Inst. ꢅ

1

ꢅ

3

ꢃ

5

MOV Aꢄ[1ꢅH]

CALL DELAY

CPL [1ꢅH]

:

Execꢀte Inst. ꢅ

Fetch Inst. 3

Flꢀsh Pipeline

Fetch Inst. 6

Execꢀte Inst. 6

Fetch Inst. 7

6 DELAY: NOP

Instruction Fetching

Program Counter

Duringꢀprogramꢀexecution,ꢀtheꢀProgramꢀCounterꢀisꢀusedꢀtoꢀkeepꢀtrackꢀofꢀtheꢀaddressꢀofꢀtheꢀnextꢀ

instructionꢀtoꢀbeꢀexecuted.ꢀItꢀisꢀautomaticallyꢀincrementedꢀbyꢀoneꢀeachꢀtimeꢀanꢀinstructionꢀisꢀex-

ecutedꢀexceptꢀforꢀinstructions,ꢀsuchꢀasꢀ“JMP”ꢀorꢀ“CALL”ꢀthatꢀdemandsꢀaꢀjumpꢀtoꢀaꢀnon-consecutiveꢀ

ProgramꢀMemoryꢀaddress.ꢀOnlyꢀtheꢀlowerꢀ8ꢀbits,ꢀknownꢀasꢀtheꢀProgramꢀCounterꢀLowꢀRegister,ꢀareꢀ

directlyꢀaddressableꢀbyꢀtheꢀapplicationꢀprogram.ꢀ

Whenꢀexecutingꢀinstructionsꢀrequiringꢀjumpsꢀtoꢀnon-consecutiveꢀaddressesꢀsuchꢀasꢀaꢀjumpꢀ

instruction,ꢀaꢀsubroutineꢀcall,ꢀinterruptꢀorꢀreset,ꢀetc.,ꢀtheꢀmicrocontrollerꢀmanagesꢀprogramꢀcontrolꢀ

byꢀloadingꢀtheꢀrequiredꢀaddressꢀintoꢀtheꢀProgramꢀCounter.ꢀForꢀconditionalꢀskipꢀinstructions,ꢀonceꢀ

theꢀconditionꢀhasꢀbeenꢀmet,ꢀtheꢀnextꢀinstruction,ꢀwhichꢀhasꢀalreadyꢀbeenꢀfetchedꢀduringꢀtheꢀpresentꢀ

instructionꢀexecution,ꢀisꢀdiscardedꢀandꢀaꢀdummyꢀcycleꢀtakesꢀitsꢀplaceꢀwhileꢀtheꢀcorrectꢀinstructionꢀisꢀ

obtained.

Program Counter

Device

Program Counter High Byte

PCL Register

PCL7~PCL0

BH66Fꢅ650

BH66Fꢅ660

PC1ꢅ~PCꢆ

PBP0ꢄ PC1ꢅ~PCꢆ

Program Counter

Rev. 1.10

ꢅ5

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

TheꢀlowerꢀbyteꢀofꢀtheꢀProgramꢀCounter,ꢀknownꢀasꢀtheꢀProgramꢀCounterꢀLowꢀregisterꢀorꢀPCL,ꢀisꢀ

availableꢀforꢀprogramꢀcontrolꢀandꢀisꢀaꢀreadableꢀandꢀwriteableꢀregister.ꢀByꢀtransferringꢀdataꢀdirectlyꢀ

intoꢀthisꢀregister,ꢀaꢀshortꢀprogramꢀjumpꢀcanꢀbeꢀexecutedꢀdirectly.ꢀHowever,ꢀasꢀonlyꢀthisꢀlowꢀbyteꢀ

isꢀavailableꢀforꢀmanipulation,ꢀtheꢀjumpsꢀareꢀlimitedꢀtoꢀtheꢀpresentꢀpageꢀofꢀmemory,ꢀthatꢀisꢀ256ꢀ

locations.ꢀWhenꢀsuchꢀprogramꢀjumpsꢀareꢀexecutedꢀitꢀshouldꢀalsoꢀbeꢀnotedꢀthatꢀaꢀdummyꢀcycleꢀ

willꢀbeꢀinserted.ꢀManipulatingꢀtheꢀPCLꢀregisterꢀmayꢀcauseꢀprogramꢀbranching,ꢀsoꢀanꢀextraꢀcycleꢀisꢀ

neededꢀtoꢀpre-fetch.

Stack

ThisꢀisꢀaꢀspecialꢀpartꢀofꢀtheꢀmemoryꢀwhichꢀisꢀusedꢀtoꢀsaveꢀtheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀonly.ꢀ

Theꢀstackꢀisꢀorganizedꢀintoꢀ8ꢀlevelsꢀandꢀisꢀneitherꢀpartꢀofꢀtheꢀdataꢀnorꢀpartꢀofꢀtheꢀprogramꢀspace,ꢀ

andꢀisꢀneitherꢀreadableꢀnorꢀwriteable.ꢀTheꢀactivatedꢀlevelꢀisꢀindexedꢀbyꢀtheꢀStackꢀPointer,ꢀandꢀisꢀ

neitherꢀreadableꢀnorꢀwriteable.ꢀAtꢀaꢀsubroutineꢀcallꢀorꢀinterruptꢀacknowledgeꢀsignal,ꢀtheꢀcontentsꢀofꢀ

theꢀProgramꢀCounterꢀareꢀpushedꢀontoꢀtheꢀstack.ꢀAtꢀtheꢀendꢀofꢀaꢀsubroutineꢀorꢀanꢀinterruptꢀroutine,ꢀ

signaledꢀbyꢀaꢀreturnꢀinstruction,ꢀRETꢀorꢀRETI,ꢀtheꢀProgramꢀCounterꢀisꢀrestoredꢀtoꢀitsꢀpreviousꢀvalueꢀ

fromꢀtheꢀstack.ꢀAfterꢀaꢀdeviceꢀreset,ꢀtheꢀStackꢀPointerꢀwillꢀpointꢀtoꢀtheꢀtopꢀofꢀtheꢀstack.

Pꢁogꢁam Coꢀnteꢁ

Top of Stack

Stack Level 1

Stack Level ꢅ

Stack Level 3

Stack

Pointeꢁ

Pꢁogꢁam Memoꢁꢂ

:

Bottom of Stack

Stack Level ꢆ

Ifꢀtheꢀstackꢀisꢀfullꢀandꢀanꢀenabledꢀinterruptꢀtakesꢀplace,ꢀtheꢀinterruptꢀrequestꢀﬂagꢀwillꢀbeꢀrecordedꢀ

butꢀtheꢀacknowledgeꢀsignalꢀwillꢀbeꢀinhibited.ꢀWhenꢀtheꢀStackꢀPointerꢀisꢀdecremented,ꢀbyꢀRETꢀorꢀ

RETI,ꢀtheꢀinterruptꢀwillꢀbeꢀserviced.ꢀThisꢀfeatureꢀpreventsꢀstackꢀoverﬂowꢀallowingꢀtheꢀprogrammerꢀ

toꢀuseꢀtheꢀstructureꢀmoreꢀeasily.ꢀHowever,ꢀwhenꢀtheꢀstackꢀisꢀfull,ꢀaꢀCALLꢀsubroutineꢀinstructionꢀcanꢀ

stillꢀbeꢀexecutedꢀwhichꢀwillꢀresultꢀinꢀaꢀstackꢀoverﬂow.ꢀPrecautionsꢀshouldꢀbeꢀtakenꢀtoꢀavoidꢀsuchꢀ

casesꢀwhichꢀmightꢀcauseꢀunpredictableꢀprogramꢀbranching.ꢀIfꢀtheꢀstackꢀisꢀoverﬂow,ꢀtheꢀﬁrstꢀProgramꢀ

Counterꢀsaveꢀinꢀtheꢀstackꢀwillꢀbeꢀlost.

Arithmetic and Logic Unit – ALU

Theꢀarithmetic-logicꢀunitꢀorꢀALUꢀisꢀaꢀcriticalꢀareaꢀofꢀtheꢀmicrocontrollerꢀthatꢀcarriesꢀoutꢀarithmeticꢀ

andꢀlogicꢀoperationsꢀofꢀtheꢀinstructionꢀset.ꢀConnectedꢀtoꢀtheꢀmainꢀmicrocontrollerꢀdataꢀbus,ꢀtheꢀALUꢀ

receivesꢀrelatedꢀinstructionꢀcodesꢀandꢀperformsꢀtheꢀrequiredꢀarithmeticꢀorꢀlogicalꢀoperationsꢀafterꢀ

whichꢀtheꢀresultꢀwillꢀbeꢀplacedꢀinꢀtheꢀspeciﬁedꢀregister.ꢀAsꢀtheseꢀALUꢀcalculationꢀorꢀoperationsꢀmayꢀ

resultꢀinꢀcarry,ꢀborrowꢀorꢀotherꢀstatusꢀchanges,ꢀtheꢀstatusꢀregisterꢀwillꢀbeꢀcorrespondinglyꢀupdatedꢀtoꢀ

reﬂectꢀtheseꢀchanges.ꢀTheꢀALUꢀsupportsꢀtheꢀfollowingꢀfunctions:

•ꢀ Arithmeticꢀoperations:ꢀ

ADD,ꢀADDM,ꢀADC,ꢀADCM,ꢀSUB,ꢀSUBM,ꢀSBC,ꢀSBCM,ꢀDAAꢀ

LADD,ꢀLADDM,ꢀLADC,ꢀLADCM,ꢀLSUB,ꢀLSUBM,ꢀLSBC,ꢀLSBCM,ꢀLDAAꢀ

•ꢀ Logicꢀoperations:ꢀ

AND,ꢀOR,ꢀXOR,ꢀANDM,ꢀORM,ꢀXORM,ꢀCPL,ꢀCPLAꢀ

LAND,ꢀLANDM,ꢀLOR,ꢀLORM,ꢀLXOR,ꢀLXORM,ꢀLCPL,ꢀLCPLAꢀ

Rev. 1.10

ꢅ6

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

•ꢀ Rotation:ꢀ

RRA,ꢀRR,ꢀRRCA,ꢀRRC,ꢀRLA,ꢀRL,ꢀRLCA,ꢀRLC,ꢀꢀ

LRRA,ꢀLRR,ꢀLRRCA,ꢀLRRC,ꢀLRLA,ꢀLRL,ꢀLRLCA,ꢀLRLC

•ꢀ IncrementꢀandꢀDecrement:ꢀ

INCA,ꢀINC,ꢀDECA,ꢀDEC,ꢀLINCA,ꢀLINC,ꢀLDECA,ꢀLDEC

•ꢀ Branchꢀdecision:ꢀ

JMP,ꢀSZ,ꢀSZA,ꢀSNZ,ꢀSIZ,ꢀSDZ,ꢀSIZA,ꢀSDZA,ꢀCALL,ꢀRET,ꢀRETI,ꢀꢀ

LSNZ,ꢀLSZ,ꢀLSZA,ꢀLSIZ,ꢀLSIZA,ꢀLSDZ,ꢀLSDZA

Flash Program Memory

TheꢀProgramꢀMemoryꢀisꢀtheꢀlocationꢀwhereꢀtheꢀuserꢀcodeꢀorꢀprogramꢀisꢀstored.ꢀForꢀtheꢀBH66F2650/

BH66F2660ꢀdevicesꢀtheꢀProgramꢀMemoryꢀisꢀFlashꢀtype,ꢀwhichꢀmeansꢀitꢀcanꢀbeꢀprogrammedꢀandꢀ

re-programmedꢀaꢀlargeꢀnumberꢀofꢀtimes,ꢀallowingꢀtheꢀuserꢀtheꢀconvenienceꢀofꢀcodeꢀmodiﬁcationꢀ

onꢀtheꢀsameꢀdevice.ꢀByꢀusingꢀtheꢀappropriateꢀprogrammingꢀtools,ꢀtheꢀFlashꢀdevicesꢀofferꢀusersꢀtheꢀ

ﬂexibilityꢀtoꢀconvenientlyꢀdebugꢀandꢀdevelopꢀtheirꢀapplicationsꢀwhileꢀalsoꢀofferingꢀaꢀmeansꢀofꢀﬁeldꢀ

programmingꢀandꢀupdating.

Structure

TheꢀProgramꢀMemoryꢀhasꢀaꢀcapacityꢀofꢀ8K×16ꢀ~ꢀ16K×16ꢀbits.ꢀTheꢀProgramꢀMemoryꢀisꢀaddressedꢀ

byꢀtheꢀProgramꢀCounterꢀandꢀalsoꢀcontainsꢀdata,ꢀtableꢀinformationꢀandꢀinterruptꢀentries.ꢀTableꢀdata,ꢀ

whichꢀcanꢀbeꢀsetupꢀinꢀanyꢀlocationꢀwithinꢀtheꢀProgramꢀMemory,ꢀisꢀaddressedꢀbyꢀaꢀseparateꢀtableꢀ

pointerꢀregister.

Device

Capacity

ꢆK×16

Banks

—

BH66Fꢅ650

BH66Fꢅ660

16K×16

0~1

BH66F2650 BH66F2660

0000H

Reset

000ꢃH

0030H

Inteꢁꢁꢀpt

Vectoꢁ

Inteꢁꢁꢀpt

Vectoꢁ

16 bits

Bank 1

1FFFH

ꢅ000H

3FFFH

Program Memory Structure

Special Vectors

WithinꢀtheꢀProgramꢀMemory,ꢀcertainꢀlocationsꢀareꢀreservedꢀforꢀtheꢀresetꢀandꢀinterrupts.ꢀTheꢀlocationꢀ

000Hꢀisꢀreservedꢀforꢀuseꢀbyꢀtheꢀdeviceꢀresetꢀforꢀprogramꢀinitialisation.ꢀAfterꢀaꢀdeviceꢀresetꢀisꢀ

initiated,ꢀtheꢀprogramꢀwillꢀjumpꢀtoꢀthisꢀlocationꢀandꢀbeginꢀexecution.

Rev. 1.10

ꢅ7

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Look-up Table

AnyꢀlocationꢀwithinꢀtheꢀProgramꢀMemoryꢀcanꢀbeꢀdeﬁnedꢀasꢀaꢀlook-upꢀtableꢀwhereꢀprogrammersꢀcanꢀ

storeꢀﬁxedꢀdata.ꢀToꢀuseꢀtheꢀlook-upꢀtable,ꢀtheꢀtableꢀpointerꢀmustꢀﬁrstꢀbeꢀsetupꢀbyꢀplacingꢀtheꢀaddressꢀ

ofꢀtheꢀlookꢀupꢀdataꢀtoꢀbeꢀretrievedꢀinꢀtheꢀtableꢀpointerꢀregister,ꢀTBLPꢀandꢀTBHP.ꢀTheseꢀregistersꢀ

deﬁneꢀtheꢀtotalꢀaddressꢀofꢀtheꢀlook-upꢀtable.

Afterꢀsettingꢀupꢀtheꢀtableꢀpointer,ꢀtheꢀtableꢀdataꢀcanꢀbeꢀretrievedꢀfromꢀtheꢀProgramꢀMemoryꢀusingꢀtheꢀ

correspondingꢀtableꢀreadꢀinstructionꢀsuchꢀasꢀ“TABRDꢀ[m]”ꢀorꢀ“TABRDLꢀ[m]”ꢀrespectivelyꢀwhenꢀ

theꢀmemoryꢀ[m]ꢀisꢀlocatedꢀinꢀsectorꢀ0.ꢀIfꢀtheꢀmemoryꢀ[m]ꢀisꢀlocatedꢀinꢀotherꢀsectors,ꢀtheꢀdataꢀcanꢀbeꢀ

retrievedꢀfromꢀtheꢀprogramꢀmemoryꢀusingꢀtheꢀcorrespondingꢀextendedꢀtableꢀreadꢀinstructionꢀsuchꢀasꢀ

“LTABRDꢀ[m]”ꢀorꢀ“LTABRDLꢀ[m]”ꢀrespectively.ꢀWhenꢀtheꢀinstructionꢀisꢀexecuted,ꢀtheꢀlowerꢀorderꢀ

tableꢀbyteꢀfromꢀtheꢀProgramꢀMemoryꢀwillꢀbeꢀtransferredꢀtoꢀtheꢀuserꢀdeﬁnedꢀDataꢀMemoryꢀregisterꢀ[m]ꢀ

asꢀspeciﬁedꢀinꢀtheꢀinstruction.ꢀTheꢀhigherꢀorderꢀtableꢀdataꢀbyteꢀfromꢀtheꢀProgramꢀMemoryꢀwillꢀbeꢀ

transferredꢀtoꢀtheꢀTBLHꢀspecialꢀregister.ꢀ

Theꢀaccompanyingꢀdiagramꢀillustratesꢀtheꢀaddressingꢀdataꢀﬂowꢀofꢀtheꢀlook-upꢀtable.

Pꢁogꢁam Memoꢁꢂ

Last Page oꢁ

TBHP Registeꢁ

Data

16 bits

TBLP Registeꢁ

Useꢁ Selected

Registeꢁ TBLH

Registeꢁ

High Bꢂte

Low Bꢂte

Table Program Example

Theꢀfollowingꢀexampleꢀshowsꢀhowꢀtheꢀtableꢀpointerꢀandꢀtableꢀdataꢀisꢀdeﬁnedꢀandꢀretrievedꢀfromꢀtheꢀ

microcontroller.ꢀThisꢀexampleꢀusesꢀrawꢀtableꢀdataꢀlocatedꢀinꢀtheꢀProgramꢀMemoryꢀwhichꢀisꢀstoredꢀ

thereꢀusingꢀtheꢀORGꢀstatement.ꢀTheꢀvalueꢀatꢀthisꢀORGꢀstatementꢀisꢀ“1F00H”ꢀwhichꢀrefersꢀtoꢀtheꢀ

startꢀaddressꢀofꢀtheꢀlastꢀpageꢀwithinꢀtheꢀ8KꢀProgramꢀMemoryꢀofꢀtheꢀBH66F2650ꢀdevice.ꢀTheꢀtableꢀ

pointerꢀlowꢀbyteꢀregisterꢀisꢀsetupꢀhereꢀtoꢀhaveꢀanꢀinitialꢀvalueꢀofꢀ“06H”.ꢀThisꢀwillꢀensureꢀthatꢀtheꢀ

ﬁrstꢀdataꢀreadꢀfromꢀtheꢀdataꢀtableꢀwillꢀbeꢀatꢀtheꢀProgramꢀMemoryꢀaddressꢀ“1F06H”ꢀorꢀ6ꢀlocationsꢀ

afterꢀtheꢀstartꢀofꢀtheꢀlastꢀpage.ꢀNoteꢀthatꢀtheꢀvalueꢀforꢀtheꢀtableꢀpointerꢀisꢀreferencedꢀtoꢀtheꢀaddressꢀ

speciﬁedꢀbyꢀTBLPꢀandꢀTBHPꢀifꢀtheꢀ“TABRDꢀ[m]”ꢀorꢀ“LTABRDꢀ[m]”ꢀinstructionꢀisꢀbeingꢀused.ꢀTheꢀ

highꢀbyteꢀofꢀtheꢀtableꢀdataꢀwhichꢀinꢀthisꢀcaseꢀisꢀequalꢀtoꢀ“0”ꢀwillꢀbeꢀtransferredꢀtoꢀtheꢀTBLHꢀregisterꢀ

automaticallyꢀwhenꢀtheꢀ“TABRDꢀ[m]”ꢀorꢀ“LTABRDꢀ[m]”ꢀinstructionꢀisꢀexecuted.ꢀ

BecauseꢀtheꢀTBLHꢀregisterꢀisꢀaꢀread/writeꢀregisterꢀandꢀcanꢀbeꢀrestored,ꢀcareꢀshouldꢀbeꢀtakenꢀ

toꢀensureꢀitsꢀprotectionꢀifꢀbothꢀtheꢀmainꢀroutineꢀandꢀInterruptꢀServiceꢀRoutineꢀuseꢀtableꢀreadꢀ

instructions.ꢀIfꢀusingꢀtheꢀtableꢀreadꢀinstructions,ꢀtheꢀInterruptꢀServiceꢀRoutinesꢀmayꢀchangeꢀtheꢀ

valueꢀofꢀtheꢀTBLHꢀandꢀsubsequentlyꢀcauseꢀerrorsꢀifꢀusedꢀagainꢀbyꢀtheꢀmainꢀroutine.ꢀAsꢀaꢀruleꢀitꢀisꢀ

recommendedꢀthatꢀsimultaneousꢀuseꢀofꢀtheꢀtableꢀreadꢀinstructionsꢀshouldꢀbeꢀavoided.ꢀHowever,ꢀinꢀ

situationsꢀwhereꢀsimultaneousꢀuseꢀcannotꢀbeꢀavoided,ꢀtheꢀinterruptsꢀshouldꢀbeꢀdisabledꢀpriorꢀtoꢀtheꢀ

executionꢀofꢀanyꢀmainꢀroutineꢀtable-readꢀinstructions.ꢀNoteꢀthatꢀallꢀtableꢀrelatedꢀinstructionsꢀrequireꢀ

twoꢀinstructionꢀcyclesꢀtoꢀcompleteꢀtheirꢀoperation.

Rev. 1.10

ꢅꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Table Read Program Example

tempreg1 db ? ; temporary register #1

tempreg2 db ? ; temporary register #2

:

mov a,06h

mov tblp,a

mov a,1Fh

mov tbhp,a

:

; initialise low table pointer - note that this address is referenced

; to the last page or the page that tbhp pointed

; initialise high table pointer

:

tabrd tempreg1 ; transfers value in table referenced by table pointer data at program

; memory address “1F06H” transferred to tempreg1 and TBLH

dec tblp

; reduce value of table pointer by one

tabrd tempreg2 ; transfers value in table referenced by table pointer

; data at program memory address “1F05H” transferred to

; tempreg2 and TBLH in this example the data “1AH” is

; transferred to tempreg1 and data “0FH” to register tempreg2

:

org 1F00h

; sets initial address of program memory

dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh

:

In Circuit Programming – ICP

TheꢀprovisionꢀofꢀFlashꢀtypeꢀProgramꢀMemoryꢀprovidesꢀtheꢀuserꢀwithꢀaꢀmeansꢀofꢀconvenientꢀandꢀeasyꢀ

upgradesꢀandꢀmodiﬁcationsꢀtoꢀtheirꢀprogramsꢀonꢀtheꢀsameꢀdevice.ꢀAsꢀanꢀadditionalꢀconvenience,ꢀ

aꢀmeansꢀofꢀprogrammingꢀtheꢀmicrocontrollerꢀin-circuitꢀhasꢀprovidedꢀusingꢀaꢀ4-pinꢀinterface.ꢀThisꢀ

providesꢀmanufacturersꢀwithꢀtheꢀpossibilityꢀofꢀmanufacturingꢀtheirꢀcircuitꢀboardsꢀcompleteꢀwithꢀaꢀ

programmedꢀorꢀun-programmedꢀmicrocontroller,ꢀandꢀthenꢀprogrammingꢀorꢀupgradingꢀtheꢀprogramꢀ

atꢀaꢀlaterꢀstage.ꢀThisꢀenablesꢀproductꢀmanufacturersꢀtoꢀeasilyꢀkeepꢀtheirꢀmanufacturedꢀproductsꢀ

suppliedꢀwithꢀtheꢀlatestꢀprogramꢀreleasesꢀwithoutꢀremovalꢀandꢀre-insertionꢀofꢀtheꢀdevice.

TheꢀFlashꢀMCUꢀtoꢀWriterꢀProgrammingꢀPinꢀcorrespondenceꢀtableꢀisꢀasꢀfollows:

Writer Pins

ICPDA

ICPCK

VDD

MCU Programming Pins

Pin Description

Pꢁogꢁamming Seꢁial Data/Addꢁess

Pꢁogꢁamming Clock

Poweꢁ Sꢀpplꢂ

PA0

PAꢅ

VDD

VSS

Gꢁoꢀnd

TheꢀProgramꢀMemoryꢀandꢀEEPROMꢀdataꢀMemoryꢀcanꢀbothꢀbeꢀprogrammedꢀseriallyꢀin-circuitꢀusingꢀ

thisꢀ4-wireꢀinterface.ꢀDataꢀisꢀdownloadedꢀandꢀuploadedꢀseriallyꢀonꢀaꢀsingleꢀpinꢀwithꢀanꢀadditionalꢀ

lineꢀforꢀtheꢀclock.ꢀTwoꢀadditionalꢀlinesꢀareꢀrequiredꢀforꢀtheꢀpowerꢀsupply.ꢀTheꢀtechnicalꢀdetailsꢀ

regardingꢀtheꢀin-circuitꢀprogrammingꢀofꢀtheꢀdeviceꢀareꢀbeyondꢀtheꢀscopeꢀofꢀthisꢀdocumentꢀandꢀwillꢀ

beꢀsuppliedꢀinꢀsupplementaryꢀliterature.

Duringꢀtheꢀprogrammingꢀprocess,ꢀtakingꢀcontrolꢀofꢀtheꢀICPDAꢀandꢀICPCKꢀpinsꢀforꢀdataꢀandꢀclockꢀ

programmingꢀpurposes.ꢀTheꢀuserꢀmustꢀthereꢀtakeꢀcareꢀtoꢀensureꢀthatꢀnoꢀotherꢀoutputsꢀareꢀconnectedꢀ

toꢀtheseꢀtwoꢀpins.

Rev. 1.10

ꢅ9

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Wꢁiteꢁ Connectoꢁ

Signals

MCU Pꢁogꢁamming

Pins

Wꢁiteꢁ_VDD

VDD

ICPDA

ICPCK

PA0

PAꢅ

Wꢁiteꢁ_VSS

VSS

*

To otheꢁ Ciꢁcꢀit

Note:ꢀ*ꢀmayꢀbeꢀresistorꢀorꢀcapacitor.ꢀTheꢀresistanceꢀofꢀ*ꢀmustꢀbeꢀgreaterꢀthanꢀ1kΩꢀorꢀtheꢀcapacitanceꢀ

ofꢀ*ꢀmustꢀbeꢀlessꢀthanꢀ1nF.

On-Chip Debug Support – OCDS

ThereꢀisꢀanꢀEVꢀchipꢀnamedꢀBH66V2650/BH66V2660ꢀwhichꢀisꢀusedꢀtoꢀemulateꢀtheꢀrealꢀMCUꢀdeviceꢀ

namedꢀBH66F2650/BH66F2660.ꢀThisꢀEVꢀchipꢀdeviceꢀalsoꢀprovidesꢀanꢀ“On-ChipꢀDebug”ꢀfunctionꢀ

toꢀdebugꢀtheꢀdeviceꢀduringꢀtheꢀdevelopmentꢀprocess.ꢀTheꢀEVꢀchipꢀandꢀtheꢀactualꢀMCUꢀdeviceꢀareꢀ

almostꢀfunctionallyꢀcompatibleꢀexceptꢀforꢀtheꢀ“On-ChipꢀDebug”ꢀfunction.ꢀUsersꢀcanꢀuseꢀtheꢀEVꢀchipꢀ

deviceꢀtoꢀemulateꢀtheꢀrealꢀchipꢀdeviceꢀbehaviorꢀbyꢀconnectingꢀtheꢀOCDSDAꢀandꢀOCDSCKꢀpinsꢀ

toꢀtheꢀHT-IDEꢀdevelopmentꢀtools.ꢀTheꢀOCDSDAꢀpinꢀisꢀtheꢀOCDSꢀData/Addressꢀinput/outputꢀpinꢀ

whileꢀtheꢀOCDSCKꢀpinꢀisꢀtheꢀOCDSꢀclockꢀinputꢀpin.ꢀWhenꢀusersꢀuseꢀtheꢀEVꢀchipꢀforꢀdebugging,ꢀ

otherꢀfunctionsꢀwhichꢀareꢀsharedꢀwithꢀtheꢀOCDSDAꢀandꢀOCDSCKꢀpinsꢀinꢀtheꢀactualꢀMCUꢀdeviceꢀ

willꢀhaveꢀnoꢀeffectꢀinꢀtheꢀEVꢀchip.ꢀHowever,ꢀtheꢀtwoꢀOCDSꢀpinsꢀwhichꢀareꢀpin-sharedꢀwithꢀtheꢀICPꢀ

programmingꢀpinsꢀareꢀstillꢀusedꢀasꢀtheꢀFlashꢀMemoryꢀprogrammingꢀpinsꢀforꢀICP.ꢀForꢀaꢀmoreꢀdetailedꢀ

OCDSꢀdescription,ꢀreferꢀtoꢀtheꢀcorrespondingꢀdocument.

e-Link Pins

OCDSDA

OCDSCK

VDD

EV Chip Pins

OCDSDA

OCDSCK

VDD

Pin Description

On-chip Debꢀg Sꢀppoꢁt Data/Addꢁess inpꢀt/oꢀtpꢀt

On-chip Debꢀg Sꢀppoꢁt Clock inpꢀt

Poweꢁ Sꢀpplꢂ

VSS

Gꢁoꢀnd

In Application Programming – IAP

TheꢀdevicesꢀofferꢀIAPꢀfunctionꢀtoꢀupdateꢀdataꢀorꢀapplicationꢀprogramꢀtoꢀFashꢀROM.ꢀUsersꢀcanꢀdeﬁneꢀ

anyꢀROMꢀlocationꢀforꢀIAP,ꢀbutꢀthereꢀareꢀsomeꢀfeaturesꢀwhichꢀuserꢀmustꢀnoticeꢀinꢀusingꢀIAPꢀfunction.

IAP Features BH66F2650 Conﬁgurations BH66F2660 Conﬁgurations

Eꢁase Page

3ꢅ woꢁds / page

3ꢅ woꢁds / time

1 woꢁd / time

6ꢃ woꢁds / page

6ꢃ woꢁds / time

1 woꢁd / time

Wꢁiting Woꢁd

Reading Woꢁd

Rev. 1.10

30

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

In Application Programming Control Registers

TheꢀAddressꢀregisters,ꢀFARLꢀandꢀFARH,ꢀtheꢀDataꢀregisters,ꢀFD0L/FD0H,ꢀFD1L/FD1H,ꢀFD2L/FD2Hꢀ

andꢀFD3L/FD3H,ꢀandꢀtheꢀControlꢀregisters,ꢀFC0,ꢀFC1ꢀandꢀFC2,ꢀareꢀtheꢀcorrespondingꢀFlashꢀaccessꢀ

registersꢀlocatedꢀinꢀDataꢀMemoryꢀsectorꢀ1ꢀforꢀIAP.ꢀIfꢀusingꢀtheꢀindirectꢀaddressingꢀmethodꢀtoꢀaccessꢀ

theꢀFC0,ꢀFC1ꢀandꢀFC2ꢀregisters,ꢀallꢀreadꢀandꢀwriteꢀoperationsꢀtoꢀtheꢀregistersꢀmustꢀbeꢀperformedꢀ

usingꢀtheꢀIndirectꢀAddressingꢀRegister,ꢀIAR1ꢀorꢀIAR2,ꢀandꢀtheꢀMemoryꢀPointerꢀpair,ꢀMP1L/MP1Hꢀ

orꢀMP2L/MP2H.ꢀBecauseꢀtheꢀFC0,ꢀFC1ꢀandꢀFC2ꢀcontrolꢀregistersꢀareꢀlocatedꢀatꢀtheꢀaddressꢀofꢀ

43H~45HꢀinꢀDataꢀMemoryꢀsectorꢀ1,ꢀtheꢀdesiredꢀvalueꢀrangedꢀfromꢀ43Hꢀtoꢀ45Hꢀmustꢀﬁrstꢀbeꢀwrittenꢀ

intoꢀtheꢀMP1LꢀorꢀMP2LꢀMemoryꢀPointerꢀlowꢀbyteꢀandꢀtheꢀvalueꢀ“01H”ꢀmustꢀalsoꢀbeꢀwrittenꢀintoꢀtheꢀ

MP1HꢀorꢀMP2HꢀMemoryꢀPointerꢀhighꢀbyte.

Bit

Register Name

7

6

5

4

3

2

1

FRDEN

D1

0

FRD

D0

FC0

CFWEN FMODꢅ FMOD1 FMOD0 FWPEN

FWT

Dꢅ

FC1

D7

—

D6

—

D5

—

Dꢃ

—

D3

—

FCꢅ

—

CLWB

A0

FARL

A7

A6

A5

Aꢃ

A3

Aꢅ

A1

FARH (BH66Fꢅ650)

—

A1ꢅ

Dꢃ

A11

D3

A10

Dꢅ

A9

Aꢆ

FARH (BH66Fꢅ660)

FD0L

—

A13

D5

A9

Aꢆ

D7

D15

D7

D15

D7

D15

D7

D15

D6

D1ꢃ

D6

D1ꢃ

D6

D1ꢃ

D6

D1ꢃ

D1

D0

FD0H

D13

D5

D1ꢅ

Dꢃ

D11

D3

D10

Dꢅ

D9

Dꢆ

FD1L

D1

D0

FD1H

D13

D5

D1ꢅ

Dꢃ

D11

D3

D10

Dꢅ

D9

Dꢆ

FDꢅL

D1

D0

FDꢅH

D13

D5

D1ꢅ

Dꢃ

D11

D3

D10

Dꢅ

D9

Dꢆ

FD3L

D1

D0

FD3H

D13

D1ꢅ

D11

D10

D9

Dꢆ

IAP Registers List

• FC0 Register

Bit

Name

R/W

7

CFWEN

R/W

0

6

FMODꢅ

R/W

0

5

4

3

2

1

0

FMOD1

R/W

0

FMOD0

R/W

0

FWPEN

R/W

0

FWT

R/W

0

FRDEN

FRD

R/W

0

R/W

0

POR

Bitꢀ7

CFWEN:ꢀFlashꢀMemoryꢀWriteꢀEnableꢀControl

0:ꢀFlashꢀmemoryꢀwriteꢀfunctionꢀisꢀdisabled

1:ꢀFlashꢀmemoryꢀwriteꢀfunctionꢀhasꢀbeenꢀsuccessfullyꢀenabled

Whenꢀthisꢀbitꢀisꢀclearedꢀtoꢀ“0”ꢀbyꢀapplicationꢀprogram,ꢀtheꢀFlashꢀmemoryꢀwriteꢀ

functionꢀisꢀdisabled.ꢀNoteꢀthatꢀwritingꢀaꢀ“1”ꢀintoꢀthisꢀbitꢀresultsꢀinꢀnoꢀaction.ꢀThisꢀbitꢀisꢀ

usedꢀtoꢀindicateꢀthatꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀstatus.ꢀWhenꢀthisꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀ

byꢀhardware,ꢀitꢀmeansꢀthatꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀisꢀenabledꢀsuccessfully.ꢀ

Otherwise,ꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀisꢀdisabledꢀasꢀtheꢀbitꢀcontentꢀisꢀ“0”.

Bitꢀ6~4

FMOD2~FMOD0:ꢀModeꢀSelection

000:ꢀWriteꢀprogramꢀmemory

001:ꢀPageꢀeraseꢀprogramꢀmemory

010:ꢀReserved

011:ꢀReadꢀprogramꢀmemory

100:ꢀReserved

101:ꢀReserved

110:ꢀFWENꢀmodeꢀ–ꢀFlashꢀmemoryꢀWriteꢀfunctionꢀEnableꢀmode

111:ꢀReserved

Rev. 1.10

31

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Bitꢀ3

Bitꢀ2

FWPEN:ꢀFlashꢀMemoryꢀWriteꢀProcedureꢀEnableꢀControl

0:ꢀDisable

1:ꢀEnable

Whenꢀthisꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀandꢀtheꢀFMODꢀﬁeldꢀisꢀsetꢀtoꢀ“110”,ꢀtheꢀIAPꢀcontrollerꢀwillꢀ

executeꢀtheꢀ“Flashꢀmemoryꢀwriteꢀfunctionꢀenable”ꢀprocedure.ꢀOnceꢀtheꢀFlashꢀmemoryꢀ

writeꢀfunctionꢀisꢀsuccessfullyꢀenabled,ꢀitꢀisꢀnotꢀnecessaryꢀtoꢀsetꢀtheꢀFWPENꢀbitꢀanyꢀ

more.

FWT:ꢀFlashꢀMemoryꢀWriteꢀInitiateꢀControl

0:ꢀDoꢀnotꢀinitiateꢀFlashꢀmemoryꢀwriteꢀorꢀFlashꢀmemoryꢀwriteꢀprocessꢀisꢀcompleted

1:ꢀInitiateꢀFlashꢀmemoryꢀwriteꢀprocess

ThisꢀbitꢀisꢀsetꢀbyꢀsoftwareꢀandꢀclearedꢀbyꢀhardwareꢀwhenꢀtheꢀFlashꢀmemoryꢀwriteꢀ

processꢀisꢀcompleted.

Bitꢀ1

Bitꢀ0

FRDEN:ꢀFlashꢀMemoryꢀReadꢀEnableꢀControl

0:ꢀFlashꢀmemoryꢀreadꢀdisable

1:ꢀFlashꢀmemoryꢀreadꢀenable

FRD:ꢀFlashꢀMemoryꢀReadꢀInitiateꢀControl

0:ꢀDoꢀnotꢀinitiateꢀFlashꢀmemoryꢀreadꢀorꢀFlashꢀmemoryꢀreadꢀprocessꢀisꢀcompleted

1:ꢀInitiateꢀFlashꢀmemoryꢀreadꢀprocess

ThisꢀbitꢀisꢀsetꢀbyꢀsoftwareꢀandꢀclearedꢀbyꢀhardwareꢀwhenꢀtheꢀFlashꢀmemoryꢀreadꢀ

processꢀisꢀcompleted.

• FC1 Register

Bit

Name

R/W

7

6

D6

R/W

0

5

D5

R/W

0

4

Dꢃ

R/W

0

3

D3

R/W

0

2

Dꢅ

R/W

0

1

D1

R/W

0

D0

R/W

0

D7

R/W

0

POR

Bitꢀ7~0

D7~D0:ꢀWholeꢀChipꢀResetꢀPattern

Whenꢀuserꢀwritesꢀaꢀspecificꢀvalueꢀofꢀ“55H”ꢀtoꢀthisꢀregister,ꢀitꢀwillꢀgenerateꢀaꢀresetꢀ

signalꢀtoꢀresetꢀwholeꢀchip.

• FC2 Register

Bit

7

6

5

4

3

2

1

0

CLWB

R/W

0

Name

R/W

—

POR

Bitꢀ7~1ꢀ

Bitꢀ0

Unimplemented,ꢀreadꢀasꢀ"0".

CLWB:ꢀFlashꢀMemoryꢀWriteꢀBufferꢀClearꢀControl

0:ꢀDoꢀnotꢀinitiateꢀWriteꢀBufferꢀClearꢀprocessꢀorꢀWriteꢀBufferꢀClearꢀprocessꢀisꢀ

completed

1:ꢀInitiateꢀWriteꢀBufferꢀClearꢀprocess

ThisꢀbitꢀisꢀsetꢀbyꢀsoftwareꢀandꢀclearedꢀbyꢀhardwareꢀwhenꢀtheꢀWriteꢀBufferꢀClearꢀ

processꢀisꢀcompleted.

• FARL Register

Bit

Name

R/W

7

A7

R/W

0

6

A6

R/W

0

5

A5

R/W

0

4

Aꢃ

R/W

0

3

A3

R/W

0

2

Aꢅ

R/W

0

1

A1

R/W

0

A0

R/W

0

POR

Bitꢀ7~0ꢀ

FlashꢀMemoryꢀAddressꢀbitꢀ7~bitꢀ0

Rev. 1.10

3ꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

• FARH Register – BH66F2650

Bit

Name

R/W

7

6

5

4

3

A11

R/W

0

2

1

A9

R/W

0

Aꢆ

R/W

0

—

A1ꢅ

R/W

0

A10

R/W

0

POR

Bitꢀ7~5ꢀ

Bitꢀ4~0ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

FlashꢀMemoryꢀAddressꢀbitꢀ12~bitꢀ8

• FARH Register – BH66F2660

Bit

Name

R/W

7

6

5

4

3

A11

R/W

0

2

1

A9

R/W

0

Aꢆ

R/W

0

—

A13

R/W

0

A1ꢅ

R/W

0

A10

R/W

0

POR

Bitꢀ7~6ꢀ

Bitꢀ5~0ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

FlashꢀMemoryꢀAddressꢀbitꢀ13~bitꢀ8

• FD0L Register

Bit

Name

R/W

7

D7

R/W

0

6

D6

R/W

0

5

D5

R/W

0

4

Dꢃ

R/W

0

3

D3

R/W

0

2

Dꢅ

R/W

0

1

D1

R/W

0

D0

R/W

0

POR

Bitꢀ7~0ꢀ

TheꢀﬁrstꢀFlashꢀMemoryꢀDataꢀbitꢀ7~bitꢀ0

• FD0H Register

Bit

Name

R/W

7

6

5

4

3

2

1

D9

R/W

0

Dꢆ

R/W

0

D15

R/W

0

D1ꢃ

R/W

0

D13

R/W

0

D1ꢅ

R/W

0

D11

R/W

0

D10

R/W

0

POR

Bitꢀ7~0ꢀ

TheꢀﬁrstꢀFlashꢀMemoryꢀDataꢀbitꢀ15~bitꢀ8

• FD1L Register

Bit

Name

R/W

7

D7

R/W

0

6

D6

R/W

0

5

D5

R/W

0

4

Dꢃ

R/W

0

3

D3

R/W

0

2

Dꢅ

R/W

0

1

D1

R/W

0

D0

R/W

0

POR

Bitꢀ7~0ꢀ

TheꢀsecondꢀFlashꢀMemoryꢀDataꢀbitꢀ7~bitꢀ0

• FD1H Register

Bit

Name

R/W

7

6

5

4

3

2

1

D9

R/W

0

Dꢆ

R/W

0

D15

R/W

0

D1ꢃ

R/W

0

D13

R/W

0

D1ꢅ

R/W

0

D11

R/W

0

D10

R/W

0

POR

Bitꢀ7~0ꢀ

TheꢀsecondꢀFlashꢀMemoryꢀDataꢀbitꢀ15~bitꢀ8

Rev. 1.10

33

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

• FD2L Register

Bit

Name

R/W

7

D7

R/W

0

6

D6

R/W

0

5

D5

R/W

0

4

Dꢃ

R/W

0

3

D3

R/W

0

2

Dꢅ

R/W

0

1

D1

R/W

0

D0

R/W

0

POR

Bitꢀ7~0ꢀ

TheꢀthirdꢀFlashꢀMemoryꢀDataꢀbitꢀ7~bitꢀ0

• FD2H Register

Bit

Name

R/W

7

6

5

4

3

2

1

D9

R/W

0

Dꢆ

R/W

0

D15

R/W

0

D1ꢃ

R/W

0

D13

R/W

0

D1ꢅ

R/W

0

D11

R/W

0

D10

R/W

0

POR

Bitꢀ7~0ꢀ

TheꢀthirdꢀFlashꢀMemoryꢀDataꢀbitꢀ15~bitꢀ8

• FD3L Register

Bit

Name

R/W

7

D7

R/W

0

6

D6

R/W

0

5

D5

R/W

0

4

Dꢃ

R/W

0

3

D3

R/W

0

2

Dꢅ

R/W

0

1

D1

R/W

0

D0

R/W

0

POR

Bitꢀ7~0ꢀ

TheꢀfourthꢀFlashꢀMemoryꢀDataꢀbitꢀ7~bitꢀ0

• FD3H Register

Bit

Name

R/W

7

6

5

4

3

2

1

D9

R/W

0

Dꢆ

R/W

0

D15

R/W

0

D1ꢃ

R/W

0

D13

R/W

0

D1ꢅ

R/W

0

D11

R/W

0

D10

R/W

0

POR

Bitꢀ7~0ꢀ

TheꢀfourthꢀFlashꢀMemoryꢀDataꢀbitꢀ15~bitꢀ8

Flash Memory Write Function Enable Procedure

InꢀorderꢀtoꢀallowꢀusersꢀtoꢀchangeꢀtheꢀFlashꢀmemoryꢀdataꢀthroughꢀtheꢀIAPꢀcontrolꢀregisters,ꢀusersꢀ

mustꢀﬁrstꢀenableꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀbyꢀtheꢀfollowingꢀprocedure:

1.ꢀWriteꢀ“110”ꢀintoꢀtheꢀFMOD2~FMOD0ꢀbitsꢀtoꢀselectꢀtheꢀFWENꢀmode.

2.ꢀSetꢀtheꢀFWPENꢀbitꢀtoꢀ“1”.ꢀTheꢀstepꢀ1ꢀandꢀstepꢀ2ꢀcanꢀbeꢀexecutedꢀsimultaneously.

3.ꢀTheꢀpatternꢀdataꢀwithꢀaꢀsequenceꢀofꢀ00H,ꢀ04H,ꢀ0DH,ꢀ09H,ꢀC3Hꢀandꢀ40Hꢀmustꢀbeꢀwrittenꢀintoꢀtheꢀ

FD1L,ꢀFD1H,ꢀFD2L,ꢀFD2H,ꢀFD3LꢀandꢀFD3Hꢀregistersꢀrespectively.

4.ꢀAꢀcounterꢀwithꢀaꢀtime-outꢀperiodꢀofꢀ300μsꢀwillꢀbeꢀactivatedꢀtoꢀallowꢀusersꢀwritingꢀtheꢀcorrectꢀ

patternꢀdataꢀintoꢀtheꢀFD1L/FD1H~FD3L/FD3Hꢀregisterꢀpairs.ꢀTheꢀcounterꢀclockꢀisꢀderivedꢀfromꢀ

LIRCꢀoscillator.

5.ꢀIfꢀtheꢀcounterꢀoverﬂowsꢀorꢀtheꢀpatternꢀdataꢀisꢀincorrect,ꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀwillꢀ

notꢀbeꢀenabledꢀandꢀusersꢀmustꢀagainꢀrepeatꢀtheꢀaboveꢀprocedure.ꢀThenꢀtheꢀFWPENꢀbitꢀwillꢀ

automaticallyꢀbeꢀclearedꢀtoꢀ“0”ꢀbyꢀhardware.

6.ꢀIfꢀtheꢀpatternꢀdataꢀisꢀcorrectꢀbeforeꢀtheꢀcounterꢀoverﬂows,ꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀwillꢀ

beꢀenabledꢀandꢀtheꢀFWPENꢀbitꢀwillꢀautomaticallyꢀbeꢀclearedꢀtoꢀ“0”ꢀbyꢀhardware.ꢀTheꢀCFWENꢀ

bitꢀwillꢀalsoꢀbeꢀsetꢀtoꢀ“1”ꢀbyꢀhardwareꢀtoꢀindicateꢀthatꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀisꢀ

successfullyꢀenabled.

7.ꢀOnceꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀisꢀenabled,ꢀtheꢀuserꢀcanꢀchangeꢀtheꢀFlashꢀROMꢀdataꢀ

throughꢀtheꢀFlashꢀcontrolꢀregister.

8.ꢀToꢀdisableꢀtheꢀFlashꢀmemoryꢀwriteꢀoperation,ꢀtheꢀuserꢀcanꢀclearꢀtheꢀCFWENꢀbitꢀtoꢀ“0”.

Rev. 1.10

3ꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

No

Is coꢀnteꢁ

oveꢁflow ?

Flash Memoꢁꢂ

Wꢁite Fꢀnction

Yes

Enable Pꢁocedꢀꢁe

FWPEN=0

Set FMOD [ꢅ:0] =110 & FWPEN=1

Select FWEN mode & Staꢁt Flash wꢁite

Haꢁdwaꢁe activate a coꢀnteꢁ

No

Is patteꢁn

coꢁꢁect ?

Wꢁtie the following patteꢁn to Flash Data ꢁegisteꢁs

FD1L= 00h ꢄ FD1H = 0ꢃh

Yes

FDꢅL= 0Dh ꢄ FDꢅH = 09h

FD3L= C3h ꢄ FD3H = ꢃ0h

CFWEN=0

Failed

CFWEN = 1

Sꢀccess

END

Flash Memory Write Function Enable Procedure

Rev. 1.10

35

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Flash Memory Read/Write Procedure

AfterꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀisꢀsuccessfullyꢀenabledꢀthroughꢀtheꢀprecedingꢀIAPꢀprocedure,ꢀ

usersꢀmustꢀﬁrstꢀeraseꢀtheꢀcorrespondingꢀFlashꢀmemoryꢀpageꢀandꢀthenꢀinitiateꢀtheꢀFlashꢀmemoryꢀwriteꢀ

operation.ꢀForꢀtheꢀBH66F2650/BH66F2660ꢀdevicesꢀtheꢀnumberꢀofꢀtheꢀpageꢀeraseꢀoperationꢀareꢀ32ꢀ

wordsꢀandꢀ64ꢀwordsꢀperꢀpageꢀrespectively,ꢀtheꢀavailableꢀpageꢀeraseꢀaddressꢀisꢀspeciﬁedꢀbyꢀFARHꢀ

registerꢀandꢀtheꢀcontentꢀofꢀFARLꢀ[7:5]ꢀandꢀFARL[7:6]bitꢀﬁeldꢀrespectively.

Erase Page

FARH

FARL [7:5]

000

FARL [4:0]

x xxxx

0

1

ꢅ

3

ꢃ

5

6

7

ꢆ

9

0000 0000

0000 0001

001

010

011

100

101

110

111

000

001

:

1ꢅ6

1ꢅ7

1ꢅꢆ

1ꢅ9

0000 1111

0001 0000

110

111

000

001

x xxxx

:

ꢅ5ꢃ

ꢅ55

0001 1111

110

111

x xxxx

“x”: don’t caꢁe

BH66F2650 Erase Page Number and Selection

Erase Page

FARH

FARL [7:6]

FARL [5:0]

xx xxxx

0

1

ꢅ

3

ꢃ

5

0000 0000

0000 0001

00

01

10

11

00

01

:

1ꢅ6

1ꢅ7

1ꢅꢆ

1ꢅ9

0001 1111

0010 0000

10

11

00

01

xx xxxx

:

ꢅ5ꢃ

ꢅ55

0011 1111

10

11

xx xxxx

“x”: don’t caꢁe

BH66F2660 Erase Page Number and Selection

Rev. 1.10

36

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Read

Flash Memoꢁꢂ

Set FMOD [ꢅ:0]=011

& FRDEN=1

Set Flash Addꢁess ꢁegisteꢁs

FARH=xxhꢄ FARL=xxh

Set FRD=1

No

FRD=0 ?

Yes

Read data valꢀe:

FD0L=xxhꢄ FD0H=xxh

No

Read Finish ?

Yes

Cleaꢁ FRDEN bit

END

Read Flash Memory Procedure

Rev. 1.10

37

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Wꢁite

Flash Memoꢁꢂ

Flash Memoꢁꢂ Wꢁite Fꢀnction Enable

Pꢁocedꢀꢁe

Set Page Eꢁase addꢁess: FARH/FARL

Set FMOD [ꢅ:0]=001 & FWT=1

Select “Page Eꢁase mode”

& Initiate wꢁite opeꢁation

No

FWT=0 ?

Yes

Set FMOD [ꢅ:0]=000

Select “Wꢁite Flash Mode”

Set Wꢁite staꢁting addꢁess: FARH/FARL

Wꢁite data to data ꢁegisteꢁ: FD0L/FD0H

Yes

No

Page data

Wꢁite finish

Set FWT=1

Yes

No

FWT=0 ?

No

Wꢁite Finish ?

Yes

Cleaꢁ CFWEN=0

END

Write Flash Memory Procedure

Note:ꢀWhenꢀtheꢀFWTꢀorꢀFRDꢀbitꢀisꢀsetꢀtoꢀ“1”,ꢀtheꢀMCUꢀisꢀstopped.

Rev. 1.10

3ꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

RAM Data Memory

TheꢀDataꢀMemoryꢀisꢀaꢀvolatileꢀareaꢀofꢀ8-bitꢀwideꢀRAMꢀinternalꢀmemoryꢀandꢀisꢀtheꢀlocationꢀwhereꢀ

temporaryꢀinformationꢀisꢀstored.

Categorisedꢀintoꢀthreeꢀtypes,ꢀtheꢀﬁrstꢀofꢀtheseꢀisꢀanꢀareaꢀofꢀRAMꢀwhereꢀspecialꢀfunctionꢀregistersꢀareꢀ

located.ꢀTheseꢀregistersꢀhaveꢀﬁxedꢀlocationsꢀandꢀareꢀnecessaryꢀforꢀcorrectꢀoperationꢀofꢀtheꢀdevices.ꢀ

Manyꢀofꢀtheseꢀregistersꢀcanꢀbeꢀreadꢀfromꢀandꢀwrittenꢀtoꢀdirectlyꢀunderꢀprogramꢀcontrol,ꢀhowever,ꢀ

someꢀremainꢀprotectedꢀfromꢀuserꢀmanipulation.ꢀTheꢀsecondꢀareaꢀofꢀDataꢀMemoryꢀisꢀreservedꢀforꢀ

generalꢀpurposeꢀuse.ꢀAllꢀlocationsꢀwithinꢀthisꢀareaꢀareꢀreadꢀandꢀwriteꢀaccessibleꢀunderꢀprogramꢀ

control.ꢀTheꢀthirdꢀareaꢀisꢀusedꢀforꢀtheꢀSineꢀPatternꢀfunction.ꢀTheꢀaddressesꢀofꢀtheꢀSineꢀPatternꢀ

MemoryꢀareaꢀoverlopꢀthoseꢀinꢀtheꢀSpecialꢀPurposeꢀDataꢀMemoryꢀarea.

Structure

TheꢀDataꢀMemoryꢀisꢀsubdividedꢀintoꢀseveralꢀsectors,ꢀallꢀofꢀwhichꢀareꢀimplementedꢀinꢀ8-bitꢀwideꢀ

RAM.ꢀEachꢀofꢀtheꢀDataꢀMemoryꢀSectorꢀisꢀcategorizedꢀintoꢀthreeꢀtypes,ꢀtheꢀspecialꢀPurposeꢀDataꢀ

MemoryꢀandꢀtheꢀGeneralꢀPurposeꢀDataꢀMemory.ꢀWhileꢀtheꢀ00H~3FHꢀofꢀSectorꢀ3ꢀisꢀSineꢀPatternꢀ

Memory.

TheꢀstartꢀaddressꢀofꢀtheꢀDataꢀMemoryꢀforꢀtheꢀdevicesꢀisꢀtheꢀaddressꢀ00H.ꢀSwitchingꢀbetweenꢀtheꢀ

differentꢀDataꢀMemoryꢀsectorsꢀisꢀachievedꢀbyꢀsettingꢀtheꢀMemoryꢀPointersꢀtoꢀtheꢀcorrectꢀvalue.

Special Purpose

Data Memory

Sine Pattern

Data Memory

General Purpose

Data Memory

Device

Available Sectors

Capacity

Address

Capacity

Address

0: 00H~7FH

1: ꢅ0H~5AH

0: ꢆ0H~FFH

1: ꢆ0H~FFH

BH66Fꢅ650

6ꢃ×ꢆ

3: 00H~3FH

ꢅ56×ꢆ

0: ꢆ0H~FFH

1: ꢆ0H~FFH

:

6: ꢆ0H~FFH

7: ꢆ0H~FFH

0: 00H~7FH

1: ꢅ0H~5AH

BH66Fꢅ660

3: 00H~3FH

10ꢅꢃ×ꢆ

00H

ꢅ0H

5AH

Special Pꢀꢁpose

Data Memoꢁꢂ

Sectoꢁ 3

Sine Patteꢁn Memoꢁꢂ

3FH

Sectoꢁ 1

7FH

ꢆ0H

Geneꢁal Pꢀꢁpose

Data Memoꢁꢂ

Sectoꢁ 0

Sectoꢁ N

FFH

Note:ꢀForꢀtheꢀBH66F2650,ꢀN=1;ꢀForꢀtheꢀBH66F2660,ꢀN=7

Data Memory Structure

Rev. 1.10

39

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Data Memory Addressing

Forꢀtheseꢀdevicesꢀthatꢀsupportꢀtheꢀextendedꢀinstructions,ꢀthereꢀisꢀnoꢀBankꢀPointerꢀforꢀDataꢀMemoryꢀ

addressing.ꢀForꢀDataꢀMemoryꢀtheꢀdesiredꢀSectorꢀisꢀpointedꢀbyꢀtheꢀMP1HꢀorꢀMP2Hꢀregisterꢀandꢀtheꢀ

certainꢀDataꢀMemoryꢀaddressꢀinꢀtheꢀselectedꢀsectorꢀisꢀspeciﬁedꢀbyꢀtheꢀMP1LꢀorꢀMP2Lꢀregisterꢀwhenꢀ

usingꢀindirectꢀaddressingꢀaccess.

DirectꢀAddressingꢀcanꢀbeꢀusedꢀinꢀallꢀsectorsꢀusingꢀtheꢀcorrespondingꢀinstructionꢀwhichꢀcanꢀaddressꢀ

allꢀavailableꢀdataꢀmemoryꢀspace.ꢀForꢀtheꢀaccessedꢀdataꢀmemoryꢀwhichꢀisꢀlocatedꢀinꢀanyꢀdataꢀ

memoryꢀsectorsꢀexceptꢀsectorꢀ0,ꢀtheꢀextendedꢀinstructionsꢀcanꢀbeꢀusedꢀtoꢀaccessꢀtheꢀdataꢀmemoryꢀ

insteadꢀofꢀusingꢀtheꢀindirectꢀaddressingꢀaccess.ꢀTheꢀmainꢀdifferenceꢀbetweenꢀstandardꢀinstructionsꢀ

andꢀextendedꢀinstructionsꢀisꢀthatꢀtheꢀdataꢀmemoryꢀaddressꢀ“m”ꢀinꢀtheꢀextendedꢀinstructionsꢀhasꢀ9ꢀorꢀ

11ꢀvalidꢀbitsꢀdependingꢀonꢀwhichꢀdeviceꢀisꢀselected,ꢀtheꢀhighꢀbyteꢀindicatesꢀaꢀsectorꢀandꢀtheꢀlowꢀbyteꢀ

indicatesꢀaꢀspeciﬁcꢀaddress.

General Purpose Data Memory

Allꢀmicrocontrollerꢀprogramsꢀrequireꢀanꢀareaꢀofꢀread/writeꢀmemoryꢀwhereꢀtemporaryꢀdataꢀcanꢀbeꢀ

storedꢀandꢀretrievedꢀforꢀuseꢀlater.ꢀItꢀisꢀthisꢀareaꢀofꢀRAMꢀmemoryꢀthatꢀisꢀknownꢀasꢀGeneralꢀPurposeꢀ

DataꢀMemory.ꢀThisꢀareaꢀofꢀDataꢀMemoryꢀisꢀfullyꢀaccessibleꢀbyꢀtheꢀuserꢀprogramingꢀforꢀbothꢀreadingꢀ

andꢀwritingꢀoperations.ꢀByꢀusingꢀtheꢀbitꢀoperationꢀinstructionsꢀindividualꢀbitsꢀcanꢀbeꢀsetꢀorꢀresetꢀ

underꢀprogramꢀcontrolꢀgivingꢀtheꢀuserꢀaꢀlargeꢀrangeꢀofꢀﬂexibilityꢀforꢀbitꢀmanipulationꢀinꢀtheꢀDataꢀ

Memory.

Special Purpose Data Memory

ThisꢀareaꢀofꢀDataꢀMemoryꢀisꢀwhereꢀregisters,ꢀnecessaryꢀforꢀtheꢀcorrectꢀoperationꢀofꢀtheꢀ

microcontroller,ꢀareꢀstored.ꢀMostꢀofꢀtheꢀregistersꢀareꢀbothꢀreadableꢀandꢀwriteableꢀbutꢀsomeꢀareꢀ

protectedꢀandꢀareꢀreadableꢀonly,ꢀtheꢀdetailsꢀofꢀwhichꢀareꢀlocatedꢀunderꢀtheꢀrelevantꢀSpecialꢀFunctionꢀ

Registerꢀsection.ꢀNoteꢀthatꢀforꢀlocationsꢀthatꢀareꢀunused,ꢀanyꢀreadꢀinstructionꢀtoꢀtheseꢀaddressesꢀwillꢀ

returnꢀtheꢀvalueꢀ“00H”.

Rev. 1.10

ꢃ0

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Sectoꢁ 0

Sectoꢁ 1

Sectoꢁ 0

Sectoꢁ 1

EEC

00H

01H

0ꢅH

03H

0ꢃH

05H

06H

07H

0ꢆH

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

1ꢅH

13H

1ꢃH

15H

16H

17H

1ꢆH

19H

1AH

1BH

1CH

1DH

1EH

1FH

ꢅ0H

ꢅ1H

ꢅꢅH

ꢅ3H

ꢅꢃH

ꢅ5H

ꢅ6H

ꢅ7H

ꢅꢆH

ꢅ9H

ꢅAH

ꢅBH

ꢅCH

ꢅDH

ꢅEH

ꢅFH

30H

31H

3ꢅH

33H

3ꢃH

35H

36H

37H

3ꢆH

39H

3AH

3BH

3CH

3DH

3EH

3FH

IAR0

MP0

IAR1

ꢃ0H

ꢃ1H

ꢃꢅH

ꢃ3H

ꢃꢃH

ꢃ5H

ꢃ6H

ꢃ7H

ꢃꢆH

ꢃ9H

ꢃAH

ꢃBH

ꢃCH

ꢃDH

ꢃEH

ꢃFH

50H

51H

5ꢅH

53H

5ꢃH

55H

56H

57H

5ꢆH

59H

5AH

5BH

5CH

5DH

5EH

5FH

60H

61H

6ꢅH

63H

6ꢃH

65H

66H

67H

6ꢆH

69H

6AH

6BH

6CH

6DH

6EH

6FH

70H

71H

7ꢅH

73H

7ꢃH

75H

76H

77H

7ꢆH

79H

7AH

7BH

7CH

7DH

7EH

7FH

EEA

EED

MP1L

MP1H

ACC

FC0

FC1

FCꢅ

PCL

FARL

FARH

FD0L

FD0H

FD1L

FD1H

FDꢅL

FDꢅH

FD3L

FD3H

IFS0

TBLP

TBLH

TBHP

STATUS

STMC0

STMC1

STMDL

STMDH

STMAL

STMAH

IARꢅ

MPꢅL

MPꢅH

RSTFC

SCC

HIRCC

HXTC

LXTC

PA

STMRP

PTM0C0

PTM0C1

PTM0DL

PTM0DH

PTM0AL

PTM0AH

PTM0RPL

PTM0RPH

IFS1

PAS0

PAS1

PBS0

PDS0

PCS0

PCS1

SLEDC0

SLEDC1

PAC

PAPU

PAWU

RSTC

LVRC

LVDC

MFI0

MDUWR0

MDUWR1

MDUWRꢅ

MDUWR3

MDUWRꢃ

MDUWR5

MDUWCTRL

MFI1

MFIꢅ

WDTC

INTEG

INTC0

INTC1

INTCꢅ

INTC3

PB

PBC

PBPU

PC

PTM1C0

PTM1C1

PTM1DL

PTM1DH

PTM1AL

PTM1AH

PTM1RPL

PTM1RPH

PTMꢅC0

PTMꢅC1

PTMꢅDL

PTMꢅDH

PTMꢅAL

PTMꢅAH

PTMꢅRPL

PTMꢅRPH

ADCS

ADCR0

ADCR1

PWRC

PGAC0

PGAC1

PGACS

ADRL

PCC

PCPU

PSCR

TB0C

TB1C

USR

UCR1

ADRM

ADRH

DSDAH

DSDAL

DSDACC

SGC

UCRꢅ

TXR_RXR

BRG

SIMC0

SIMC1

SIMD

SIMA/SIMCꢅ

SIMTOC

SGN

SGDNR

OPAC

SWC0

SWC1

SWCꢅ

DACO

FTRC

PD

SPIAC0

SPIAC1

SPIAD

PDC

PDPU

: Unꢀsedꢄ ꢁead as 00H

: Reseꢁvedꢄ cannot be changed

Special Purpose Data Memory Structure – BH66F2650

Rev. 1.10

ꢃ1

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Sectoꢁ 0

Sectoꢁ 1

Sectoꢁ 0

Sectoꢁ 1

EEC

00H

01H

0ꢅH

03H

0ꢃH

05H

06H

07H

0ꢆH

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

1ꢅH

13H

1ꢃH

15H

16H

17H

1ꢆH

19H

1AH

1BH

1CH

1DH

1EH

1FH

ꢅ0H

ꢅ1H

ꢅꢅH

ꢅ3H

ꢅꢃH

ꢅ5H

ꢅ6H

ꢅ7H

ꢅꢆH

ꢅ9H

ꢅAH

ꢅBH

ꢅCH

ꢅDH

ꢅEH

ꢅFH

30H

31H

3ꢅH

33H

3ꢃH

35H

36H

37H

3ꢆH

39H

3AH

3BH

3CH

3DH

3EH

3FH

IAR0

MP0

IAR1

ꢃ0H

ꢃ1H

ꢃꢅH

ꢃ3H

ꢃꢃH

ꢃ5H

ꢃ6H

ꢃ7H

ꢃꢆH

ꢃ9H

ꢃAH

ꢃBH

ꢃCH

ꢃDH

ꢃEH

ꢃFH

50H

51H

5ꢅH

53H

5ꢃH

55H

56H

57H

5ꢆH

59H

5AH

5BH

5CH

5DH

5EH

5FH

60H

61H

6ꢅH

63H

6ꢃH

65H

66H

67H

6ꢆH

69H

6AH

6BH

6CH

6DH

6EH

6FH

70H

71H

7ꢅH

73H

7ꢃH

75H

76H

77H

7ꢆH

79H

7AH

7BH

7CH

7DH

7EH

7FH

EEA

EED

MP1L

MP1H

ACC

FC0

FC1

FCꢅ

PCL

FARL

FARH

FD0L

FD0H

FD1L

FD1H

FDꢅL

FDꢅH

FD3L

FD3H

IFS0

TBLP

TBLH

TBHP

STATUS

PBP

STMC0

STMC1

STMDL

STMDH

STMAL

STMAH

IARꢅ

MPꢅL

MPꢅH

RSTFC

SCC

HIRCC

HXTC

LXTC

PA

STMRP

PTM0C0

PTM0C1

PTM0DL

PTM0DH

PTM0AL

PTM0AH

PTM0RPL

PTM0RPH

IFS1

PAS0

PAS1

PBS0

PDS0

PCS0

PCS1

SLEDC0

SLEDC1

PAC

PAPU

PAWU

RSTC

LVRC

LVDC

MFI0

MDUWR0

MDUWR1

MDUWRꢅ

MDUWR3

MDUWRꢃ

MDUWR5

MDUWCTRL

MFI1

MFIꢅ

WDTC

INTEG

INTC0

INTC1

INTCꢅ

INTC3

PB

PBC

PBPU

PC

PTM1C0

PTM1C1

PTM1DL

PTM1DH

PTM1AL

PTM1AH

PTM1RPL

PTM1RPH

PTMꢅC0

PTMꢅC1

PTMꢅDL

PTMꢅDH

PTMꢅAL

PTMꢅAH

PTMꢅRPL

PTMꢅRPH

ADCS

ADCR0

ADCR1

PWRC

PGAC0

PGAC1

PGACS

ADRL

PCC

PCPU

PSCR

TB0C

TB1C

USR

UCR1

ADRM

ADRH

DSDAH

DSDAL

DSDACC

SGC

UCRꢅ

TXR_RXR

BRG

SIMC0

SIMC1

SIMD

SIMA/SIMCꢅ

SIMTOC

SGN

SGDNR

OPAC

SWC0

SWC1

SWCꢅ

DACO

FTRC

PD

SPIAC0

SPIAC1

SPIAD

PDC

PDPU

: Unꢀsedꢄ ꢁead as 00H

: Reseꢁvedꢄ cannot be changed

Special Purpose Data Memory Structure – BH66F2660

Rev. 1.10

ꢃꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Special Function Register Description

MostꢀofꢀtheꢀSpecialꢀFunctionꢀRegisterꢀdetailsꢀwillꢀbeꢀdescribedꢀinꢀtheꢀrelevantꢀfunctionalꢀsections,ꢀ

howeverꢀseveralꢀregistersꢀrequireꢀaꢀseparateꢀdescriptionꢀinꢀthisꢀsection.

Indirect Addressing Registers – IAR0, IAR1, IAR2

TheꢀIndirectꢀAddressingꢀRegisters,ꢀIAR0,ꢀIAR1ꢀandꢀIAR2,ꢀalthoughꢀhavingꢀtheirꢀlocationsꢀinꢀnormalꢀ

RAMꢀregisterꢀspace,ꢀdoꢀnotꢀactuallyꢀphysicallyꢀexistꢀasꢀnormalꢀregisters.ꢀTheꢀmethodꢀofꢀindirectꢀ

addressingꢀforꢀRAMꢀdataꢀmanipulationꢀusesꢀtheseꢀIndirectꢀAddressingꢀRegistersꢀandꢀMemoryꢀ

Pointers,ꢀinꢀcontrastꢀtoꢀdirectꢀmemoryꢀaddressing,ꢀwhereꢀtheꢀactualꢀmemoryꢀaddressꢀisꢀspeciﬁed.ꢀ

ActionsꢀonꢀtheꢀIAR0,ꢀIAR1ꢀandꢀIAR2ꢀregistersꢀwillꢀresultꢀinꢀnoꢀactualꢀreadꢀorꢀwriteꢀoperationꢀtoꢀ

theseꢀregistersꢀbutꢀratherꢀtoꢀtheꢀmemoryꢀlocationꢀspeciﬁedꢀbyꢀtheirꢀcorrespondingꢀMemoryꢀPointers,ꢀ

MP0,ꢀMP1L/MP1HꢀorꢀMP2L/MP2H.ꢀActingꢀasꢀaꢀpair,ꢀIAR0ꢀandꢀMP0ꢀcanꢀtogetherꢀaccessꢀdataꢀonlyꢀ

fromꢀSectorꢀ0ꢀwhileꢀtheꢀIAR1ꢀregisterꢀtogetherꢀwithꢀtheꢀMP1L/MP1HꢀregisterꢀpairꢀandꢀIAR2ꢀregisterꢀ

togetherꢀwithꢀtheꢀMP2L/MP2HꢀregisterꢀpairꢀcanꢀaccessꢀdataꢀfromꢀanyꢀDataꢀMemoryꢀSector.ꢀAsꢀ

theꢀIndirectꢀAddressingꢀRegistersꢀareꢀnotꢀphysicallyꢀimplemented,ꢀreadingꢀtheꢀIndirectꢀAddressingꢀ

Registersꢀwillꢀreturnꢀaꢀresultꢀofꢀ“00H”ꢀandꢀwritingꢀtoꢀtheꢀregistersꢀwillꢀresultꢀinꢀnoꢀoperation.

Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2H

FiveꢀMemoryꢀPointers,ꢀknownꢀasꢀMP0,ꢀMP1L,ꢀMP1H,ꢀMP2L,ꢀMP2H,ꢀareꢀprovided.ꢀTheseꢀMemoryꢀ

PointersꢀareꢀphysicallyꢀimplementedꢀinꢀtheꢀDataꢀMemoryꢀandꢀcanꢀbeꢀmanipulatedꢀinꢀtheꢀsameꢀwayꢀ

asꢀnormalꢀregistersꢀprovidingꢀaꢀconvenientꢀwayꢀwithꢀwhichꢀtoꢀaddressꢀandꢀtrackꢀdata.ꢀWhenꢀanyꢀ

operationꢀtoꢀtheꢀrelevantꢀIndirectꢀAddressingꢀRegistersꢀisꢀcarriedꢀout,ꢀtheꢀactualꢀaddressꢀthatꢀtheꢀ

microcontrollerꢀisꢀdirectedꢀtoꢀisꢀtheꢀaddressꢀspeciﬁedꢀbyꢀtheꢀrelatedꢀMemoryꢀPointer.ꢀMP0,ꢀtogetherꢀ

withꢀIndirectꢀAddressingꢀRegister,ꢀIAR0,ꢀareꢀusedꢀtoꢀaccessꢀdataꢀfromꢀSectorꢀ0,ꢀwhileꢀMP1L/MP1Hꢀ

togetherꢀwithꢀIAR1ꢀandꢀMP2L/MP2HꢀtogetherꢀwithꢀIAR2ꢀareꢀusedꢀtoꢀaccessꢀdataꢀfromꢀallꢀsectorsꢀ

accordingꢀtoꢀtheꢀcorrespondingꢀMP1HꢀorꢀMP2Hꢀregister.ꢀDirectꢀAddressingꢀcanꢀbeꢀusedꢀinꢀallꢀ

sectorsꢀusingꢀtheꢀcorrespondingꢀinstructionꢀwhichꢀcanꢀaddressꢀallꢀavailableꢀdataꢀmemoryꢀspace.

TheꢀfollowingꢀexampleꢀshowsꢀhowꢀtoꢀclearꢀaꢀsectionꢀofꢀfourꢀDataꢀMemoryꢀlocationsꢀalreadyꢀdeﬁnedꢀ

asꢀlocationsꢀadres1ꢀtoꢀadres4.

Indirect Addressing Program Example 1

data .section ´data´

adres1 db ?

adres2 db ?

adres3 db ?

adres4 db ?

block

db ?

code .section at 0 ´code´

org 00h

start:

mov a, 04h

; setup size of block

mov block, a

ꢀ

movꢀa,ꢀoffsetꢀadres1ꢀ ꢀ

ꢀ

;ꢀAccumulatorꢀloadedꢀwithꢀﬁrstꢀRAMꢀaddress

;ꢀsetupꢀmemoryꢀpointerꢀwithꢀﬁrstꢀRAMꢀaddress

movꢀmp0,ꢀaꢀꢀ ꢀꢀꢀꢀꢀ

ꢀ

loop:

ꢀ

clrꢀIAR0ꢀ

inc mp0

ꢀ

;ꢀclearꢀtheꢀdataꢀatꢀaddressꢀdeﬁnedꢀbyꢀMP0

; increment memory pointer

sdz block

jmp loop

; check if last memory location has been cleared

continue:

Rev. 1.10

ꢃ3

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Indirect Addressing Program Example 2

data .section ´data´

adres1 db ?

adres2 db ?

adres3 db ?

adres4 db ?

block

db ?

code .section at 0 ´code´

org 00h

start:

mov a, 04h

mov block, a

mov a, 01h

; setup size of block

; setup the memory sector

mov mp1h, a

ꢀ

movꢀa,ꢀoffsetꢀadres1ꢀ ꢀ ;ꢀAccumulatorꢀloadedꢀwithꢀﬁrstꢀRAMꢀaddress

ꢀ

movꢀmp1l,ꢀaꢀ

ꢀ

;ꢀsetupꢀmemoryꢀpointerꢀwithꢀﬁrstꢀRAMꢀaddress

loop:

ꢀ

clrꢀIAR1ꢀ

incꢀmp1lꢀ

sdz block

jmp loop

ꢀ

;ꢀclearꢀtheꢀdataꢀatꢀaddressꢀdeﬁnedꢀbyꢀMP1L

;ꢀincrementꢀmemoryꢀpointerꢀMP1L

; check if last memory location has been cleared

continue:

Theꢀimportantꢀpointꢀtoꢀnoteꢀhereꢀisꢀthatꢀinꢀtheꢀexampleꢀshownꢀabove,ꢀnoꢀreferenceꢀisꢀmadeꢀtoꢀspeciﬁcꢀ

DataꢀMemoryꢀaddresses.

Direct Addressing Program Example using extended instructions

data .section ´data´

temp db ?

code .section at 0 ´code´

org 00h

start:

lmov a, [m]

lsub a, [m+1]

snz c

; move [m] data to acc

; compare [m] and [m+1] data

; [m]>[m+1]?

jmp continue

lmov a, [m]

mov temp, a

lmov a, [m+1]

lmov [m], a

mov a, temp

lmov [m+1], a

; no

; yes, exchange [m] and [m+1] data

continue:

Note:ꢀhereꢀ“m”ꢀisꢀaꢀdataꢀmemoryꢀaddressꢀlocatedꢀinꢀanyꢀdataꢀmemoryꢀsectors.ꢀForꢀexample,ꢀ

m=1F0H,ꢀitꢀindicatesꢀaddressꢀ0F0HꢀinꢀSectorꢀ1.

Rev. 1.10

ꢃꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Program Memory Bank Pointer – PBP

ForꢀtheꢀBH66F2660ꢀdeviceꢀtheꢀProgramꢀMemoryꢀisꢀdividedꢀintoꢀseveralꢀbanks.ꢀSelectingꢀtheꢀ

requiredꢀProgramꢀMemoryꢀareaꢀisꢀachievedꢀusingꢀtheꢀProgramꢀMemoryꢀBankꢀPointer,ꢀPBP.ꢀTheꢀPBPꢀ

registerꢀshouldꢀbeꢀproperlyꢀconﬁguredꢀbeforeꢀtheꢀdeviceꢀexecutesꢀtheꢀ“Branch”ꢀoperationꢀusingꢀtheꢀ

“JMP”ꢀorꢀ“CALL”ꢀinstruction.ꢀAfterꢀthatꢀaꢀjumpꢀtoꢀaꢀnon-consecutiveꢀProgramꢀMemoryꢀaddressꢀ

whichꢀisꢀlocatedꢀinꢀaꢀcertainꢀbankꢀselectedꢀbyꢀtheꢀprogramꢀmemoryꢀbankꢀpointerꢀbitsꢀwillꢀoccur.

PBP Register – BH66F2660

Bit

Name

R/W

7

6

5

4

3

2

1

0

PBP0

R/W

0

—

POR

Bitꢀ7~1ꢀ

Bitꢀ0

Unimplemented,ꢀreadꢀasꢀ“0”

PBP0:ꢀSelectꢀProgramꢀMemoryꢀBanks

0:ꢀBankꢀ0

1:ꢀBankꢀ1

Accumulator – ACC

TheꢀAccumulatorꢀisꢀcentralꢀtoꢀtheꢀoperationꢀofꢀanyꢀmicrocontrollerꢀandꢀisꢀcloselyꢀrelatedꢀwithꢀ

operationsꢀcarriedꢀoutꢀbyꢀtheꢀALU.ꢀTheꢀAccumulatorꢀisꢀtheꢀplaceꢀwhereꢀallꢀintermediateꢀresultsꢀ

fromꢀtheꢀALUꢀareꢀstored.ꢀWithoutꢀtheꢀAccumulatorꢀitꢀwouldꢀbeꢀnecessaryꢀtoꢀwriteꢀtheꢀresultꢀofꢀ

eachꢀcalculationꢀorꢀlogicalꢀoperationꢀsuchꢀasꢀaddition,ꢀsubtraction,ꢀshift,ꢀetc.,ꢀtoꢀtheꢀDataꢀMemoryꢀ

resultingꢀinꢀhigherꢀprogrammingꢀandꢀtimingꢀoverheads.ꢀDataꢀtransferꢀoperationsꢀusuallyꢀinvolveꢀ

theꢀtemporaryꢀstorageꢀfunctionꢀofꢀtheꢀAccumulator;ꢀforꢀexample,ꢀwhenꢀtransferringꢀdataꢀbetweenꢀ

oneꢀuser-definedꢀregisterꢀandꢀanother,ꢀitꢀisꢀnecessaryꢀtoꢀdoꢀthisꢀbyꢀpassingꢀtheꢀdataꢀthroughꢀtheꢀ

Accumulatorꢀasꢀnoꢀdirectꢀtransferꢀbetweenꢀtwoꢀregistersꢀisꢀpermitted.

Program Counter Low Register – PCL

Toꢀprovideꢀadditionalꢀprogramꢀcontrolꢀfunctions,ꢀtheꢀlowꢀbyteꢀofꢀtheꢀProgramꢀCounterꢀisꢀmadeꢀ

accessibleꢀtoꢀprogrammersꢀbyꢀlocatingꢀitꢀwithinꢀtheꢀSpecialꢀPurposeꢀareaꢀofꢀtheꢀDataꢀMemory.ꢀByꢀ

manipulatingꢀthisꢀregister,ꢀdirectꢀjumpsꢀtoꢀotherꢀprogramꢀlocationsꢀareꢀeasilyꢀimplemented.ꢀLoadingꢀ

aꢀvalueꢀdirectlyꢀintoꢀthisꢀPCLꢀregisterꢀwillꢀcauseꢀaꢀjumpꢀtoꢀtheꢀspeciﬁedꢀProgramꢀMemoryꢀlocation,ꢀ

however,ꢀasꢀtheꢀregisterꢀisꢀonlyꢀ8-bitꢀwide,ꢀonlyꢀjumpsꢀwithinꢀtheꢀcurrentꢀProgramꢀMemoryꢀpageꢀareꢀ

permitted.ꢀWhenꢀsuchꢀoperationsꢀareꢀused,ꢀnoteꢀthatꢀaꢀdummyꢀcycleꢀwillꢀbeꢀinserted.

Look-up Table Registers – TBLP, TBHP, TBLH

Theseꢀthreeꢀspecialꢀfunctionꢀregistersꢀareꢀusedꢀtoꢀcontrolꢀoperationꢀofꢀtheꢀlook-upꢀtableꢀwhichꢀisꢀ

storedꢀinꢀtheꢀProgramꢀMemory.ꢀTBLPꢀandꢀTBHPꢀareꢀtheꢀtableꢀpointersꢀandꢀindicateꢀtheꢀlocationꢀ

whereꢀtheꢀtableꢀdataꢀisꢀlocated.ꢀTheirꢀvalueꢀmustꢀbeꢀsetupꢀbeforeꢀanyꢀtableꢀreadꢀcommandsꢀareꢀ

executed.ꢀTheirꢀvalueꢀcanꢀbeꢀchanged,ꢀforꢀexampleꢀusingꢀtheꢀ“INC”ꢀorꢀ“DEC”ꢀinstructions,ꢀallowingꢀ

forꢀeasyꢀtableꢀdataꢀpointingꢀandꢀreading.ꢀTBLHꢀisꢀtheꢀlocationꢀwhereꢀtheꢀhighꢀorderꢀbyteꢀofꢀtheꢀtableꢀ

dataꢀisꢀstoredꢀafterꢀaꢀtableꢀreadꢀdataꢀinstructionꢀhasꢀbeenꢀexecuted.ꢀNoteꢀthatꢀtheꢀlowerꢀorderꢀtableꢀ

dataꢀbyteꢀisꢀtransferredꢀtoꢀaꢀuserꢀdeﬁnedꢀlocation.ꢀ

Rev. 1.10

ꢃ5

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Status Register – STATUS

Thisꢀ8-bitꢀregisterꢀcontainsꢀtheꢀSCꢀﬂag,ꢀCZꢀﬂag,ꢀzeroꢀﬂagꢀ(Z),ꢀcarryꢀﬂagꢀ(C),ꢀauxiliaryꢀcarryꢀﬂagꢀ(AC),ꢀ

overﬂowꢀﬂagꢀ(OV),ꢀpowerꢀdownꢀﬂagꢀ(PDF),ꢀandꢀwatchdogꢀtime-outꢀﬂagꢀ(TO).ꢀTheseꢀarithmetic/

logicalꢀoperationꢀandꢀsystemꢀmanagementꢀﬂagsꢀareꢀusedꢀtoꢀrecordꢀtheꢀstatusꢀandꢀoperationꢀofꢀtheꢀ

microcontroller.ꢀ

WithꢀtheꢀexceptionꢀofꢀtheꢀTOꢀandꢀPDFꢀﬂags,ꢀbitsꢀinꢀtheꢀstatusꢀregisterꢀcanꢀbeꢀalteredꢀbyꢀinstructionsꢀ

likeꢀmostꢀotherꢀregisters.ꢀAnyꢀdataꢀwrittenꢀintoꢀtheꢀstatusꢀregisterꢀwillꢀnotꢀchangeꢀtheꢀTOꢀorꢀPDFꢀﬂag.ꢀ

Inꢀaddition,ꢀoperationsꢀrelatedꢀtoꢀtheꢀstatusꢀregisterꢀmayꢀgiveꢀdifferentꢀresultsꢀdueꢀtoꢀtheꢀdifferentꢀ

instructionꢀoperations.ꢀTheꢀTOꢀﬂagꢀcanꢀbeꢀaffectedꢀonlyꢀbyꢀaꢀsystemꢀpower-up,ꢀaꢀWDTꢀtime-outꢀorꢀ

byꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀorꢀ“HALT”ꢀinstruction.ꢀTheꢀPDFꢀﬂagꢀisꢀaffectedꢀonlyꢀbyꢀexecutingꢀ

theꢀ“HALT”ꢀorꢀ“CLRꢀWDT”ꢀinstructionꢀorꢀduringꢀaꢀsystemꢀpower-up.ꢀ

TheꢀZ,ꢀOV,ꢀAC,ꢀC,ꢀSCꢀandꢀCZꢀﬂagsꢀgenerallyꢀreﬂectꢀtheꢀstatusꢀofꢀtheꢀlatestꢀoperations.ꢀ

•ꢀ Cꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀduringꢀanꢀadditionꢀoperationꢀorꢀifꢀaꢀborrowꢀdoesꢀnotꢀtakeꢀ

placeꢀduringꢀaꢀsubtractionꢀoperation;ꢀotherwiseꢀCꢀisꢀcleared.ꢀCꢀisꢀalsoꢀaffectedꢀbyꢀaꢀrotateꢀthroughꢀ

carryꢀinstruction.ꢀ

•ꢀ ACꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀoutꢀofꢀtheꢀlowꢀnibblesꢀinꢀaddition,ꢀorꢀnoꢀborrowꢀfromꢀ

theꢀhighꢀnibbleꢀintoꢀtheꢀlowꢀnibbleꢀinꢀsubtraction;ꢀotherwiseꢀACꢀisꢀcleared.ꢀ

•ꢀ Zꢀisꢀsetꢀifꢀtheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀzero;ꢀotherwiseꢀZꢀisꢀcleared.ꢀ

•ꢀ OVꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀintoꢀtheꢀhighest-orderꢀbitꢀbutꢀnotꢀaꢀcarryꢀoutꢀofꢀtheꢀ

highest-orderꢀbit,ꢀorꢀviceꢀversa;ꢀotherwiseꢀOVꢀisꢀcleared.ꢀ

•ꢀ PDFꢀisꢀclearedꢀbyꢀaꢀsystemꢀpower-upꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀinstruction.ꢀPDFꢀisꢀsetꢀbyꢀ

executingꢀtheꢀ“HALT”ꢀinstruction.ꢀ

•ꢀ TOꢀisꢀclearedꢀbyꢀaꢀsystemꢀpower-upꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀorꢀ“HALT”ꢀinstruction.ꢀTOꢀisꢀ

setꢀbyꢀaꢀWDTꢀtime-out.ꢀ

•ꢀ CZꢀisꢀtheꢀoperationalꢀresultꢀofꢀdifferentꢀflagsꢀforꢀdifferentꢀinstructions.ꢀReferꢀtoꢀregisterꢀ

deﬁnitionsꢀforꢀmoreꢀdetails.

•ꢀ SCꢀisꢀtheꢀresultꢀofꢀtheꢀ“XOR”ꢀoperationꢀwhichꢀisꢀperformedꢀbyꢀtheꢀOVꢀﬂagꢀandꢀtheꢀMSBꢀofꢀtheꢀ

currentꢀinstructionꢀoperationꢀresult.ꢀ

Inꢀaddition,ꢀonꢀenteringꢀanꢀinterruptꢀsequenceꢀorꢀexecutingꢀaꢀsubroutineꢀcall,ꢀtheꢀstatusꢀregisterꢀwillꢀ

notꢀbeꢀpushedꢀontoꢀtheꢀstackꢀautomatically.ꢀIfꢀtheꢀcontentsꢀofꢀtheꢀstatusꢀregistersꢀareꢀimportantꢀandꢀifꢀ

theꢀsubroutineꢀcanꢀcorruptꢀtheꢀstatusꢀregister,ꢀprecautionsꢀmustꢀbeꢀtakenꢀtoꢀcorrectlyꢀsaveꢀit.

Rev. 1.10

ꢃ6

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

STATUS Register

Bit

Name

R/W

7

SC

R/W

x

6

CZ

R/W

x

5

TO

R

4

PDF

R

3

OV

R/W

x

2

Z

1

AC

R/W

x

0

C

R/W

x

R/W

x

POR

0

“x” ꢀnknown

Bitꢀ7

SC:ꢀXORꢀOperationꢀResultꢀ-ꢀperformedꢀbyꢀtheꢀOVꢀﬂagꢀandꢀtheꢀMSBꢀofꢀtheꢀinstructionꢀ

operationꢀresult.ꢀ

Bitꢀ6

CZ:ꢀOperationalꢀResultꢀofꢀDifferentꢀFlagsꢀforꢀDifferentꢀInstructions.ꢀ

ForꢀSUB/SUBM/LSUB/LSUBMꢀinstructions,ꢀtheꢀCZꢀﬂagꢀisꢀequalꢀtoꢀtheꢀZꢀﬂag.ꢀ

ForꢀSBC/SBCM/LSBC/LSBCMꢀinstructions,ꢀtheꢀCZꢀflagꢀisꢀtheꢀ“AND”ꢀoperationꢀ

resultꢀwhichꢀisꢀperformedꢀbyꢀtheꢀpreviousꢀoperationꢀCZꢀﬂagꢀandꢀcurrentꢀoperationꢀzeroꢀ

ﬂag.ꢀ

Forꢀotherꢀinstructions,ꢀtheꢀCZꢀﬂagꢀwillꢀnotꢀbeꢀaffected.

Bitꢀ5

Bitꢀ4

Bitꢀ3

TO:ꢀWatchdogꢀTime-OutꢀFlag

0:ꢀAfterꢀpowerꢀupꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀorꢀ“HALT”ꢀinstruction

1:ꢀAꢀwatchdogꢀtime-outꢀoccurred.

PDF:ꢀPowerꢀDownꢀFlag

0:ꢀAfterꢀpowerꢀupꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀinstruction

1:ꢀByꢀexecutingꢀtheꢀ“HALT”ꢀinstruction

OV:ꢀOverﬂowꢀFlag

0:ꢀNoꢀoverﬂow

1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀintoꢀtheꢀhighest-orderꢀbitꢀbutꢀnotꢀaꢀcarryꢀoutꢀofꢀtheꢀ

highest-orderꢀbitꢀorꢀviceꢀversa.

Bitꢀ2

Bitꢀ1

Z:ꢀZeroꢀFlag

0:ꢀTheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀnotꢀzero

1:ꢀTheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀzero

AC:ꢀAuxiliaryꢀﬂag

0:ꢀNoꢀauxiliaryꢀcarry

1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀoutꢀofꢀtheꢀlowꢀnibblesꢀinꢀaddition,ꢀorꢀnoꢀborrowꢀ

fromꢀtheꢀhighꢀnibbleꢀintoꢀtheꢀlowꢀnibbleꢀinꢀsubtraction

Bitꢀ0

C:ꢀCarryꢀFlag

0:ꢀNoꢀcarry-out

1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀduringꢀanꢀadditionꢀoperationꢀorꢀifꢀaꢀborrowꢀdoesꢀ

notꢀtakeꢀplaceꢀduringꢀaꢀsubtractionꢀoperationꢀ

Cꢀisꢀalsoꢀaffectedꢀbyꢀaꢀrotateꢀthroughꢀcarryꢀinstruction.

Rev. 1.10

ꢃ7

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

EEPROM Data Memory

TheseꢀdevicesꢀcontainꢀanꢀareaꢀofꢀinternalꢀEEPROMꢀDataꢀMemory.ꢀEEPROM,ꢀwhichꢀstandsꢀforꢀ

ElectricallyꢀErasableꢀProgrammableꢀReadꢀOnlyꢀMemory,ꢀisꢀbyꢀitsꢀnatureꢀaꢀnon-volatileꢀformꢀ

ofꢀre-programmableꢀmemory,ꢀwithꢀdataꢀretentionꢀevenꢀwhenꢀitsꢀpowerꢀsupplyꢀisꢀremoved.ꢀByꢀ

incorporatingꢀthisꢀkindꢀofꢀdataꢀmemory,ꢀaꢀwholeꢀnewꢀhostꢀofꢀapplicationꢀpossibilitiesꢀareꢀmadeꢀ

availableꢀtoꢀtheꢀdesigner.ꢀTheꢀavailabilityꢀofꢀEEPROMꢀstorageꢀallowsꢀinformationꢀsuchꢀasꢀproductꢀ

identificationꢀnumbers,ꢀcalibrationꢀvalues,ꢀspecificꢀuserꢀdata,ꢀsystemꢀsetupꢀdataꢀorꢀotherꢀproductꢀ

informationꢀtoꢀbeꢀstoredꢀdirectlyꢀwithinꢀtheꢀproductꢀmicrocontroller.ꢀTheꢀprocessꢀofꢀreadingꢀandꢀ

writingꢀdataꢀtoꢀtheꢀEEPROMꢀmemoryꢀhasꢀbeenꢀreducedꢀtoꢀaꢀveryꢀtrivialꢀaffair.

EEPROM Data Memory Structure

TheꢀEEPROMꢀDataꢀMemoryꢀcapacityꢀisꢀ64×8ꢀ~ꢀ256×8ꢀbitsꢀforꢀtheseꢀdevices.ꢀUnlikeꢀtheꢀProgramꢀ

MemoryꢀandꢀRAMꢀDataꢀMemory,ꢀtheꢀEEPROMꢀDataꢀMemoryꢀisꢀnotꢀdirectlyꢀmappedꢀintoꢀmemoryꢀ

spaceꢀandꢀisꢀthereforeꢀnotꢀdirectlyꢀaddressableꢀinꢀtheꢀsameꢀwayꢀasꢀtheꢀotherꢀtypesꢀofꢀmemory.ꢀReadꢀ

andꢀWriteꢀoperationsꢀtoꢀtheꢀEEPROMꢀareꢀcarriedꢀoutꢀinꢀsingleꢀbyteꢀoperationsꢀusingꢀanꢀaddressꢀandꢀ

aꢀdataꢀregisterꢀinꢀSectorꢀ0ꢀandꢀaꢀsingleꢀcontrolꢀregisterꢀinꢀSectorꢀ1.

EEPROM Registers

ThreeꢀregistersꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀinternalꢀEEPROMꢀDataꢀMemory.ꢀTheseꢀareꢀtheꢀ

addressꢀregister,ꢀEEA,ꢀtheꢀdataꢀregister,ꢀEEDꢀandꢀaꢀsingleꢀcontrolꢀregister,ꢀEEC.ꢀAsꢀbothꢀtheꢀEEAꢀ

andꢀEEDꢀregistersꢀareꢀlocatedꢀinꢀSectorꢀ0,ꢀtheyꢀcanꢀbeꢀdirectlyꢀaccessedꢀinꢀtheꢀsameꢀwasꢀasꢀanyꢀ

otherꢀSpecialꢀFunctionꢀRegister.ꢀTheꢀEECꢀregisterꢀhowever,ꢀbeingꢀlocatedꢀinꢀSectorꢀ1,ꢀcanꢀbeꢀreadꢀ

fromꢀorꢀwrittenꢀtoꢀindirectlyꢀusingꢀtheꢀMP1L/MP1HꢀorꢀMP2L/MP2HꢀMemoryꢀPointerꢀandꢀIndirectꢀ

AddressingꢀRegister,ꢀIAR1/IAR2.ꢀBecauseꢀtheꢀEECꢀcontrolꢀregisterꢀisꢀlocatedꢀatꢀaddressꢀ40Hꢀinꢀ

Sectorꢀ1,ꢀtheꢀMP1LꢀorꢀMP2LꢀMemoryꢀPointerꢀmustꢀﬁrstꢀbeꢀsetꢀtoꢀtheꢀvalueꢀ40HꢀandꢀtheꢀMP1Hꢀorꢀ

MP2HꢀMemoryꢀPointerꢀhighꢀbyteꢀsetꢀtoꢀtheꢀvalue,ꢀ01H,ꢀbeforeꢀanyꢀoperationsꢀonꢀtheꢀEECꢀregisterꢀ

areꢀexecuted.

Bit

Register Name

7

6

5

4

3

2

1

0

EEA (BH66Fꢅ650)

EEA (BH66Fꢅ660)

EED

—

EEA5

EED5

—

EEAꢃ

EEDꢃ

—

EEA3

EED3

WREN

EEAꢅ

EEDꢅ

WR

EEA1

EED1

RDEN

EEA0

EED0

RD

EEA7

EED7

—

EEA6

EED6

—

EEC

EEPROM Register List

• EEA Register – BH66F2650

Bit

Name

R/W

7

6

5

4

EEAꢃ

R/W

0

3

2

1

0

EEA0

R/W

0

—

EEA5

R/W

0

EEA3

R/W

0

EEAꢅ

R/W

0

EEA1

R/W

0

POR

Bitꢀ7~6ꢀ

Bitꢀ5~0

Unimplemented,ꢀreadꢀasꢀ“0”

EEA5~EEA0:ꢀDataꢀEEPROMꢀAddress

DataꢀEEPROMꢀaddressꢀbitꢀ5~bitꢀ0

Rev. 1.10

ꢃꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

• EEA Register – BH66F2660

Bit

Name

R/W

7

EEA7

R/W

0

6

EEA6

R/W

0

5

EEA5

R/W

0

4

EEAꢃ

R/W

0

3

EEA3

R/W

0

2

EEAꢅ

R/W

0

1

EEA1

R/W

0

EEA0

R/W

0

POR

Bitꢀ7~0

EEA7~EEA0:ꢀDataꢀEEPROMꢀAddress

DataꢀEEPROMꢀaddressꢀbitꢀ7~bitꢀ0

• EED Register

Bit

7

6

EED6

R/W

0

5

EED5

R/W

0

4

EEDꢃ

R/W

0

3

EED3

R/W

0

2

EEDꢅ

R/W

0

1

EED1

R/W

0

EED0

R/W

0

Name

R/W

EED7

R/W

0

POR

Bitꢀ7~0ꢀ

EED7~EED0:ꢀDataꢀEEPROMꢀData

DataꢀEEPROMꢀdataꢀbitꢀ7~bitꢀ0

• EEC Register

Bit

7

6

5

4

3

WREN

R/W

0

2

WR

R/W

0

1

RDEN

R/W

0

RD

R/W

0

Name

R/W

—

POR

Bitꢀ7~4ꢀꢀꢀꢀꢀꢀ Unimplemented,ꢀreadꢀasꢀ“0”

Bitꢀ3ꢀꢀꢀꢀꢀꢀꢀ

WREN:ꢀDataꢀEEPROMꢀWriteꢀEnable

0:ꢀDisable

1:ꢀEnable

ThisꢀisꢀtheꢀDataꢀEEPROMꢀWriteꢀEnableꢀBitꢀwhichꢀmustꢀbeꢀsetꢀhighꢀbeforeꢀDataꢀ

EEPROMꢀwriteꢀoperationsꢀareꢀcarriedꢀout.ꢀClearingꢀthisꢀbitꢀtoꢀ“0”ꢀwillꢀinhibitꢀDataꢀ

EEPROMꢀwriteꢀoperations.

Bitꢀ2ꢀꢀꢀꢀꢀꢀꢀ

WR:ꢀEEPROMꢀWriteꢀControl

0:ꢀWriteꢀcycleꢀhasꢀﬁnished

1:ꢀActivateꢀaꢀwriteꢀcycle

ThisꢀisꢀtheꢀDataꢀEEPROMꢀWriteꢀControlꢀBitꢀandꢀwhenꢀsetꢀhighꢀbyꢀtheꢀapplicationꢀ

programꢀwillꢀactivateꢀaꢀwriteꢀcycle.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀresetꢀtoꢀ“0”ꢀbyꢀtheꢀ

hardwareꢀafterꢀtheꢀwriteꢀcycleꢀhasꢀﬁnished.ꢀSettingꢀthisꢀbitꢀhighꢀwillꢀhaveꢀnoꢀeffectꢀifꢀ

theꢀWRENꢀhasꢀnotꢀﬁrstꢀbeenꢀsetꢀhigh.

Bitꢀ1ꢀꢀꢀꢀꢀꢀꢀ

Bitꢀ0ꢀꢀꢀꢀꢀꢀꢀ

RDEN:ꢀDataꢀEEPROMꢀReadꢀEnable

0:ꢀDisable

1:ꢀEnable

ThisꢀisꢀtheꢀDataꢀEEPROMꢀReadꢀEnableꢀBitꢀwhichꢀmustꢀbeꢀsetꢀhighꢀbeforeꢀDataꢀ

EEPROMꢀreadꢀoperationsꢀareꢀcarriedꢀout.ꢀClearingꢀthisꢀbitꢀtoꢀ“0”ꢀwillꢀinhibitꢀDataꢀ

EEPROMꢀreadꢀoperations.

RD:ꢀEEPROMꢀReadꢀControl

0:ꢀReadꢀcycleꢀhasꢀﬁnished

1:ꢀActivateꢀaꢀreadꢀcycle

ThisꢀisꢀtheꢀDataꢀEEPROMꢀReadꢀControlꢀBitꢀandꢀwhenꢀsetꢀhighꢀbyꢀtheꢀapplicationꢀ

programꢀwillꢀactivateꢀaꢀreadꢀcycle.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀresetꢀtoꢀ“0”ꢀbyꢀtheꢀ

hardwareꢀafterꢀtheꢀreadꢀcycleꢀhasꢀﬁnished.ꢀSettingꢀthisꢀbitꢀhighꢀwillꢀhaveꢀnoꢀeffectꢀifꢀ

theꢀRDENꢀhasꢀnotꢀﬁrstꢀbeenꢀsetꢀhigh.

Note:ꢀTheꢀWREN,ꢀWR,ꢀRDENꢀandꢀRDꢀcannotꢀbeꢀsetꢀhighꢀatꢀtheꢀsameꢀtimeꢀinꢀoneꢀinstruction.ꢀTheꢀ

WRꢀandꢀRDꢀcannotꢀbeꢀsetꢀhighꢀatꢀtheꢀsameꢀtime.

Rev. 1.10

ꢃ9

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Reading Data from the EEPROM

ToꢀreadꢀdataꢀfromꢀtheꢀEEPROM,ꢀtheꢀreadꢀenableꢀbit,ꢀRDEN,ꢀinꢀtheꢀEECꢀregisterꢀmustꢀﬁrstꢀbeꢀsetꢀ

highꢀtoꢀenableꢀtheꢀreadꢀfunction.ꢀTheꢀEEPROMꢀaddressꢀofꢀtheꢀdataꢀtoꢀbeꢀreadꢀmustꢀthenꢀbeꢀplacedꢀ

inꢀtheꢀEEAꢀregister.ꢀIfꢀtheꢀRDꢀbitꢀinꢀtheꢀEECꢀregisterꢀisꢀnowꢀsetꢀhigh,ꢀaꢀreadꢀcycleꢀwillꢀbeꢀinitiated.ꢀ

SettingꢀtheꢀRDꢀbitꢀhighꢀwillꢀnotꢀinitiateꢀaꢀreadꢀoperationꢀifꢀtheꢀRDENꢀbitꢀhasꢀnotꢀbeenꢀset.ꢀWhenꢀ

theꢀreadꢀcycleꢀterminates,ꢀtheꢀRDꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀ“0”,ꢀafterꢀwhichꢀtheꢀdataꢀcanꢀ

beꢀreadꢀfromꢀtheꢀEEDꢀregister.ꢀTheꢀdataꢀwillꢀremainꢀinꢀtheꢀEEDꢀregisterꢀuntilꢀanotherꢀreadꢀorꢀwriteꢀ

operationꢀisꢀexecuted.ꢀTheꢀapplicationꢀprogramꢀcanꢀpollꢀtheꢀRDꢀbitꢀtoꢀdetermineꢀwhenꢀtheꢀdataꢀisꢀ

validꢀforꢀreading.

Writing Data to the EEPROM

TheꢀEEPROMꢀaddressꢀofꢀtheꢀdataꢀtoꢀbeꢀwrittenꢀmustꢀﬁrstꢀbeꢀplacedꢀinꢀtheꢀEEAꢀregisterꢀandꢀtheꢀdataꢀ

placedꢀinꢀtheꢀEEDꢀregister.ꢀToꢀwriteꢀdataꢀtoꢀtheꢀEEPROM,ꢀtheꢀwriteꢀenableꢀbit,ꢀWREN,ꢀinꢀtheꢀEECꢀ

registerꢀmustꢀﬁrstꢀbeꢀsetꢀhighꢀtoꢀenableꢀtheꢀwriteꢀfunction.ꢀAfterꢀthis,ꢀtheꢀWRꢀbitꢀinꢀtheꢀEECꢀregisterꢀ

mustꢀbeꢀimmediatelyꢀsetꢀhighꢀtoꢀinitiateꢀaꢀwriteꢀcycle.ꢀTheseꢀtwoꢀinstructionsꢀmustꢀbeꢀexecutedꢀ

consecutively.ꢀTheꢀglobalꢀinterruptꢀbitꢀEMIꢀshouldꢀalsoꢀﬁrstꢀbeꢀclearedꢀbeforeꢀimplementingꢀanyꢀ

writeꢀoperations,ꢀandꢀthenꢀsetꢀagainꢀafterꢀtheꢀwriteꢀcycleꢀhasꢀstarted.ꢀNoteꢀthatꢀsettingꢀtheꢀWRꢀbitꢀ

highꢀwillꢀnotꢀinitiateꢀaꢀwriteꢀcycleꢀifꢀtheꢀWRENꢀbitꢀhasꢀnotꢀbeenꢀset.ꢀAsꢀtheꢀEEPROMꢀwriteꢀcycleꢀisꢀ

controlledꢀusingꢀanꢀinternalꢀtimerꢀwhoseꢀoperationꢀisꢀasynchronousꢀtoꢀmicrocontrollerꢀsystemꢀclock,ꢀ

aꢀcertainꢀtimeꢀwillꢀelapseꢀbeforeꢀtheꢀdataꢀwillꢀhaveꢀbeenꢀwrittenꢀintoꢀtheꢀEEPROM.ꢀDetectingꢀwhenꢀ

theꢀwriteꢀcycleꢀhasꢀﬁnishedꢀcanꢀbeꢀimplementedꢀeitherꢀbyꢀpollingꢀtheꢀWRꢀbitꢀinꢀtheꢀEECꢀregisterꢀorꢀ

byꢀusingꢀtheꢀEEPROMꢀinterrupt.ꢀWhenꢀtheꢀwriteꢀcycleꢀterminates,ꢀtheꢀWRꢀbitꢀwillꢀbeꢀautomaticallyꢀ

clearedꢀtoꢀ“0”ꢀbyꢀtheꢀmicrocontroller,ꢀinformingꢀtheꢀuserꢀthatꢀtheꢀdataꢀhasꢀbeenꢀwrittenꢀtoꢀtheꢀ

EEPROM.ꢀTheꢀapplicationꢀprogramꢀcanꢀthereforeꢀpollꢀtheꢀWRꢀbitꢀtoꢀdetermineꢀwhenꢀtheꢀwriteꢀcycleꢀ

hasꢀended.

Write Protection

Protectionꢀagainstꢀinadvertentꢀwriteꢀoperationꢀisꢀprovidedꢀinꢀseveralꢀways.ꢀAfterꢀtheꢀdeviceꢀisꢀ

powered-onꢀtheꢀWriteꢀEnableꢀbitꢀinꢀtheꢀcontrolꢀregisterꢀwillꢀbeꢀclearedꢀpreventingꢀanyꢀwriteꢀ

operations.ꢀAlsoꢀatꢀpower-onꢀtheꢀMemoryꢀPointerꢀhighꢀbyteꢀregister,ꢀMP1HꢀorꢀMP2H,ꢀwillꢀbeꢀresetꢀ

toꢀ“0”,ꢀwhichꢀmeansꢀthatꢀDataꢀMemoryꢀSectorꢀ0ꢀwillꢀbeꢀselected.ꢀAsꢀtheꢀEEPROMꢀcontrolꢀregisterꢀ

isꢀlocatedꢀinꢀSectorꢀ1,ꢀthisꢀaddsꢀaꢀfurtherꢀmeasureꢀofꢀprotectionꢀagainstꢀspuriousꢀwriteꢀoperations.ꢀ

Duringꢀnormalꢀprogramꢀoperation,ꢀensuringꢀthatꢀtheꢀWriteꢀEnableꢀbitꢀinꢀtheꢀcontrolꢀregisterꢀisꢀ

clearedꢀwillꢀsafeguardꢀagainstꢀincorrectꢀwriteꢀoperations.

EEPROM Interrupt

TheꢀEEPROMꢀwriteꢀinterruptꢀisꢀgeneratedꢀwhenꢀanꢀEEPROMꢀwriteꢀcycleꢀhasꢀended.ꢀTheꢀEEPROMꢀ

interruptꢀmustꢀﬁrstꢀbeꢀenabledꢀbyꢀsettingꢀtheꢀDEEꢀbitꢀinꢀtheꢀrelevantꢀinterruptꢀregister.ꢀHoweverꢀasꢀ

theꢀEEPROMꢀisꢀcontainedꢀwithinꢀaꢀMulti-functionꢀInterrupt,ꢀtheꢀassociatedꢀmulti-functionꢀinterruptꢀ

enableꢀbitꢀmustꢀalsoꢀbeꢀset.ꢀWhenꢀanꢀEEPROMꢀwriteꢀcycleꢀends,ꢀtheꢀDEFꢀrequestꢀflagꢀandꢀitsꢀ

associatedꢀmulti-functionꢀinterruptꢀrequestꢀﬂagꢀwillꢀbothꢀbeꢀset.ꢀIfꢀtheꢀglobal,ꢀEEPROMꢀandꢀMulti-

functionꢀinterruptsꢀareꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀaꢀjumpꢀtoꢀtheꢀassociatedꢀMulti-functionꢀ

Interruptꢀvectorꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀservicedꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀﬂagꢀ

willꢀbeꢀautomaticallyꢀreset,ꢀtheꢀEEPROMꢀinterruptꢀﬂagꢀmustꢀbeꢀmanuallyꢀresetꢀbyꢀtheꢀapplicationꢀ

program.ꢀMoreꢀdetailsꢀcanꢀbeꢀobtainedꢀinꢀtheꢀInterruptꢀsection.

Rev. 1.10

50

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Programming Considerations

CareꢀmustꢀbeꢀtakenꢀthatꢀdataꢀisꢀnotꢀinadvertentlyꢀwrittenꢀtoꢀtheꢀEEPROM.ꢀProtectionꢀcanꢀbeꢀ

enhancedꢀbyꢀensuringꢀthatꢀtheꢀWriteꢀEnableꢀbitꢀisꢀnormallyꢀclearedꢀtoꢀ“0”ꢀwhenꢀnotꢀwriting.ꢀAlsoꢀ

theꢀMemoryꢀPointerꢀhighꢀbyteꢀregister,ꢀMP1HꢀorꢀMP2H,ꢀcouldꢀbeꢀnormallyꢀclearedꢀtoꢀ“0”ꢀasꢀthisꢀ

wouldꢀinhibitꢀaccessꢀtoꢀSectorꢀ1ꢀwhereꢀtheꢀEEPROMꢀcontrolꢀregisterꢀexist.ꢀAlthoughꢀcertainlyꢀnotꢀ

necessary,ꢀconsiderationꢀmightꢀbeꢀgivenꢀinꢀtheꢀapplicationꢀprogramꢀtoꢀtheꢀcheckingꢀofꢀtheꢀvalidityꢀofꢀ

newꢀwriteꢀdataꢀbyꢀaꢀsimpleꢀreadꢀbackꢀprocess.

WhenꢀwritingꢀdataꢀtheꢀWRꢀbitꢀmustꢀbeꢀsetꢀhighꢀimmediatelyꢀafterꢀtheꢀWRENꢀbitꢀhasꢀbeenꢀsetꢀhigh,ꢀ

toꢀensureꢀtheꢀwriteꢀcycleꢀexecutesꢀcorrectly.ꢀTheꢀglobalꢀinterruptꢀbitꢀEMIꢀshouldꢀalsoꢀbeꢀclearedꢀ

beforeꢀaꢀwriteꢀcycleꢀisꢀexecutedꢀandꢀthenꢀre-enabledꢀafterꢀtheꢀwriteꢀcycleꢀstarts.ꢀNoteꢀthatꢀtheꢀdeviceꢀ

shouldꢀnotꢀenterꢀtheꢀIDLEꢀorꢀSLEEPꢀmodeꢀuntilꢀtheꢀEEPROMꢀreadꢀorꢀwriteꢀoperationꢀisꢀtotallyꢀ

complete.ꢀOtherwise,ꢀtheꢀEEPROMꢀreadꢀorꢀwriteꢀoperationꢀwillꢀfail.

Programming Examples

• Reading Data from the EEPROM − Polling Method

MOVꢀ A,ꢀEEPROM_ADRESꢀ

MOVꢀ EEA,ꢀA

ꢀ

;ꢀuserꢀdeﬁnedꢀaddress

MOVꢀ A,ꢀ40Hꢀꢀ

MOVꢀ MP1L,ꢀAꢀ

MOVꢀ A,ꢀ01Hꢀꢀ

MOVꢀ MP1H,ꢀA

SETꢀ IAR1.1ꢀ ꢀ

SETꢀ IAR1.0ꢀ ꢀ

BACK:

ꢀ

;ꢀsetupꢀmemoryꢀpointerꢀMP1L

;ꢀMP1LꢀpointsꢀtoꢀEECꢀregister

;ꢀsetupꢀmemoryꢀpointerꢀMP1H

ꢀ

;ꢀsetꢀRDENꢀbit,ꢀenableꢀreadꢀoperations

;ꢀstartꢀReadꢀCycleꢀ-ꢀsetꢀRDꢀbit

SZꢀ IAR1.0ꢀ ꢀ

JMPꢀ BACK

ꢀ

;ꢀcheckꢀforꢀreadꢀcycleꢀend

;ꢀdisableꢀEEPROMꢀread/write

;ꢀmoveꢀreadꢀdataꢀtoꢀregister

CLRꢀ IAR1ꢀ

CLRꢀ MP1H

ꢀ

MOVꢀ A,ꢀEEDꢀꢀ

MOVꢀ READ_DATA,ꢀA

• Writing Data to the EEPROM − Polling Method

MOVꢀ A,ꢀEEPROM_ADRESꢀ

MOVꢀ EEA,ꢀA

ꢀ

;ꢀuserꢀdeﬁnedꢀaddress

MOVꢀ A,ꢀEEPROM_DATAꢀ

MOVꢀ EED,ꢀA

ꢀ

;ꢀuserꢀdeﬁnedꢀdata

MOVꢀ A,ꢀ040Hꢀꢀ

MOVꢀ MP1L,ꢀAꢀ

MOVꢀ A,ꢀ01Hꢀꢀ

MOVꢀ MP1H,ꢀA

CLRꢀ EMI

ꢀ

;ꢀsetupꢀmemoryꢀpointerꢀMP1L

;ꢀMP1LꢀpointsꢀtoꢀEECꢀregister

;ꢀsetupꢀmemoryꢀpointerꢀMP1H

SETꢀ IAR1.3ꢀ ꢀ

SETꢀ IAR1.2ꢀ ꢀ

ꢀ

;ꢀsetꢀWRENꢀbit,ꢀenableꢀwriteꢀoperations

;ꢀstartꢀWriteꢀCycleꢀ-ꢀsetꢀWRꢀbitꢀ–ꢀexecutedꢀimmediately

;ꢀafterꢀsetꢀWRENꢀbit

ꢀ

SETꢀꢀEMI

BACK:

SZꢀ IAR1.2ꢀ ꢀ

JMPꢀ BACK

ꢀ

;ꢀcheckꢀforꢀwriteꢀcycleꢀend

;ꢀdisableꢀEEPROMꢀread/write

CLRꢀ IAR1ꢀ

CLRꢀ MP1H

ꢀ

Rev. 1.10

51

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Oscillators

Variousꢀoscillatorꢀoptionsꢀofferꢀtheꢀuserꢀaꢀwideꢀrangeꢀofꢀfunctionsꢀaccordingꢀtoꢀtheirꢀvariousꢀ

applicationꢀrequirements.ꢀTheꢀflexibleꢀfeaturesꢀofꢀtheꢀoscillatorꢀfunctionsꢀensureꢀthatꢀtheꢀbestꢀ

optimisationꢀcanꢀbeꢀachievedꢀinꢀtermsꢀofꢀspeedꢀandꢀpowerꢀsaving.ꢀOscillatorꢀselectionsꢀandꢀoperationꢀ

areꢀselectedꢀthroughꢀrelevantꢀcontrolꢀregisters.

Oscillator Overview

Inꢀadditionꢀtoꢀbeingꢀtheꢀsourceꢀofꢀtheꢀmainꢀsystemꢀclockꢀtheꢀoscillatorsꢀalsoꢀprovideꢀclockꢀsourcesꢀ

forꢀtheꢀWatchdogꢀTimerꢀandꢀTimeꢀBaseꢀInterrupts.ꢀExternalꢀoscillatorsꢀrequiringꢀsomeꢀexternalꢀ

componentsꢀasꢀwellꢀasꢀfullyꢀintegratedꢀinternalꢀoscillators,ꢀrequiringꢀnoꢀexternalꢀcomponents,ꢀareꢀ

providedꢀtoꢀformꢀaꢀwideꢀrangeꢀofꢀbothꢀfastꢀandꢀslowꢀsystemꢀoscillators.ꢀAllꢀoscillatorꢀoptionsꢀareꢀ

selectedꢀthroughꢀtheꢀregisters.ꢀTheꢀhigherꢀfrequencyꢀoscillatorsꢀprovideꢀhigherꢀperformanceꢀbutꢀ

carryꢀwithꢀitꢀtheꢀdisadvantageꢀofꢀhigherꢀpowerꢀrequirements,ꢀwhileꢀtheꢀoppositeꢀisꢀofꢀcourseꢀtrueꢀforꢀ

theꢀlowerꢀfrequencyꢀoscillators.ꢀWithꢀtheꢀcapabilityꢀofꢀdynamicallyꢀswitchingꢀbetweenꢀfastꢀandꢀslowꢀ

systemꢀclock,ꢀtheseꢀdevicesꢀhaveꢀtheꢀﬂexibilityꢀtoꢀoptimizeꢀtheꢀperformance/powerꢀratio,ꢀaꢀfeatureꢀ

especiallyꢀimportantꢀinꢀpowerꢀsensitiveꢀportableꢀapplications.

Type

Exteꢁnal Cꢁꢂstal

Name

HXT

Freq.

ꢃꢄ ꢆꢄ 1ꢅꢄ 16MHz

ꢃꢄ ꢆꢄ 1ꢅMHz

3ꢅ.76ꢆkHz

3ꢅkHz

Pins

OSC1/OSCꢅ

—

Inteꢁnal High Speed RC

Exteꢁnal Low Speed Cꢁꢂstal

Inteꢁnal Low Speed RC

HIRC

LXT

XT1/XT2

—

LIRC

System Clock Conﬁgurations

Thereꢀareꢀfourꢀmethodsꢀofꢀgeneratingꢀtheꢀsystemꢀclock,ꢀtwoꢀhighꢀspeedꢀoscillatorsꢀandꢀtwoꢀlowꢀspeedꢀ

oscillators.ꢀTheꢀhighꢀspeedꢀoscillatorsꢀareꢀtheꢀexternalꢀcrystal/ceramicꢀoscillatorꢀandꢀtheꢀinternalꢀ

4/8/12MHzꢀRCꢀoscillator.ꢀTheꢀtwoꢀlowꢀspeedꢀoscillatorsꢀareꢀtheꢀinternalꢀ32kHzꢀRCꢀoscillatorꢀandꢀ

theꢀexternalꢀ32.768kHzꢀcrystalꢀoscillator.ꢀSelectingꢀwhetherꢀtheꢀlowꢀorꢀhighꢀspeedꢀoscillatorꢀisꢀusedꢀ

asꢀtheꢀsystemꢀoscillatorꢀisꢀimplementedꢀusingꢀtheꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSCCꢀregisterꢀandꢀasꢀtheꢀ

systemꢀclockꢀcanꢀbeꢀdynamicallyꢀselected.

TheꢀactualꢀsourceꢀclockꢀusedꢀforꢀtheꢀlowꢀspeedꢀoscillatorsꢀisꢀchosenꢀviaꢀtheꢀFSSꢀbitꢀinꢀtheꢀSCCꢀ

registerꢀwhileꢀforꢀtheꢀhighꢀspeedꢀoscillatorꢀtheꢀsourceꢀclockꢀisꢀselectedꢀbyꢀtheꢀFHSꢀbitꢀinꢀtheꢀSCCꢀ

register.ꢀTheꢀfrequencyꢀofꢀtheꢀslowꢀspeedꢀorꢀhighꢀspeedꢀsystemꢀclockꢀisꢀdeterminedꢀusingꢀtheꢀ

CKS2~CKS0ꢀbitsꢀinꢀtheꢀSCCꢀregister.ꢀNoteꢀthatꢀtwoꢀoscillatorꢀselectionsꢀmustꢀbeꢀmadeꢀnamelyꢀoneꢀ

highꢀspeedꢀandꢀoneꢀlowꢀspeedꢀsystemꢀoscillators.ꢀItꢀisꢀnotꢀpossibleꢀtoꢀchooseꢀaꢀno-oscillatorꢀselectionꢀ

forꢀeitherꢀtheꢀhighꢀorꢀlowꢀspeedꢀoscillator.

Rev. 1.10

5ꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

f_H

FHS

High Speed

f_H/ꢅ

f_H/ꢃ

f_H/ꢆ

f_H/16

Oscillatoꢁs

HXTEN

HXT

IDLE0

SLEEP

Pꢁescaleꢁ

f_SYS

HIRCEN

HIRC

f_H/3ꢅ

f_H/6ꢃ

FSS

Low Speed

Oscillatoꢁs

CKSꢅ~CKS0

LXTEN

LXT

f_SUB

IDLEꢅ

SLEEP

f_LIRC

LIRC

f_LIRC

System Clock Conﬁgurations

External High Speed Crystal Oscillator − HXT

TheꢀsimpleꢀconnectionꢀofꢀaꢀcrystalꢀacrossꢀOSC1ꢀandꢀOSC2ꢀwillꢀcreateꢀtheꢀnecessaryꢀphaseꢀshiftꢀandꢀ

feedbackꢀforꢀoscillation.ꢀHowever,ꢀforꢀsomeꢀcrystalsꢀandꢀmostꢀresonatorꢀtypes,ꢀtoꢀensureꢀoscillationꢀ

andꢀaccurateꢀfrequencyꢀgeneration,ꢀitꢀisꢀnecessaryꢀtoꢀaddꢀtwoꢀsmallꢀvalueꢀexternalꢀcapacitors,ꢀC1ꢀandꢀ

C2.ꢀTheꢀexactꢀvaluesꢀofꢀC1ꢀandꢀC2ꢀshouldꢀbeꢀselectedꢀinꢀconsultationꢀwithꢀtheꢀcrystalꢀorꢀresonatorꢀ

manufacturer’sꢀspeciﬁcation.

Forꢀoscillatorꢀstabilityꢀandꢀtoꢀminimiseꢀtheꢀeffectsꢀofꢀnoiseꢀandꢀcrosstalk,ꢀitꢀisꢀimportantꢀtoꢀensureꢀ

thatꢀtheꢀcrystalꢀandꢀanyꢀassociatedꢀresistorsꢀandꢀcapacitorsꢀalongꢀwithꢀinterconnectingꢀlinesꢀareꢀallꢀ

locatedꢀasꢀcloseꢀtoꢀtheꢀMCUꢀasꢀpossible.

Internal

Oscillator

Circuit

C1

OSC1

OSCꢅ

R_P

R_F

To inteꢁnal

ciꢁcꢀits

Cꢅ

Note: 1. R_Pis noꢁmallꢂ not ꢁeqꢀiꢁed. C1 and Cꢅ aꢁe ꢁeqꢀiꢁed.

ꢅ. Althoꢀgh not shown OSC1/OSCꢅ pins have a paꢁasitic

capacitance of aꢁoꢀnd 7pF.

Crystal/Resonator Oscillator – HXT

HXT Oscillator C1 and C2 Values

Crystal Frequency

1ꢅMHz

C1

0pF

C2

0pF

ꢆMHz

0pF

ꢃMHz

0pF

1MHz

100pF

Note: C1 and Cꢅ valꢀes aꢁe foꢁ gꢀidance onlꢂ.

Crystal Recommended Capacitor Values

Rev. 1.10

53

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Internal RC Oscillator − HIRC

TheꢀinternalꢀRCꢀoscillatorꢀisꢀaꢀfullyꢀintegratedꢀsystemꢀoscillatorꢀrequiringꢀnoꢀexternalꢀcomponents.ꢀ

TheꢀinternalꢀRCꢀoscillatorꢀhasꢀaꢀfixedꢀfrequencyꢀofꢀ4/8/12MHz.ꢀDeviceꢀtrimmingꢀduringꢀtheꢀ

manufacturingꢀprocessꢀandꢀtheꢀinclusionꢀofꢀinternalꢀfrequencyꢀcompensationꢀcircuitsꢀareꢀusedꢀtoꢀ

ensureꢀthatꢀtheꢀinﬂuenceꢀofꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀtemperatureꢀandꢀprocessꢀvariationsꢀonꢀtheꢀ

oscillationꢀfrequencyꢀareꢀminimised.ꢀNoteꢀthatꢀifꢀthisꢀinternalꢀsystemꢀclockꢀoptionꢀisꢀselected,ꢀasꢀitꢀ

requiresꢀnoꢀexternalꢀpinsꢀforꢀitsꢀoperation,ꢀI/OꢀpinsꢀareꢀfreeꢀforꢀuseꢀasꢀnormalꢀI/Oꢀpins.

External 32.768kHz Crystal Oscillator − LXT

Theꢀexternalꢀ32.768kHzꢀcrystalꢀsystemꢀoscillatorꢀisꢀoneꢀofꢀtheꢀlowꢀfrequencyꢀoscillatorꢀchoices,ꢀwhichꢀ

isꢀselectedꢀviaꢀaꢀsoftwareꢀcontrolꢀbit,ꢀFSS.ꢀThisꢀclockꢀsourceꢀhasꢀaꢀﬁxedꢀfrequencyꢀofꢀ32.768kHzꢀandꢀ

requiresꢀaꢀ32.768kHzꢀcrystalꢀtoꢀbeꢀconnectedꢀbetweenꢀpinsꢀXT1ꢀandꢀXT2.ꢀTheꢀexternalꢀresistorꢀandꢀ

capacitorꢀcomponentsꢀconnectedꢀtoꢀtheꢀ32.768kHzꢀcrystalꢀareꢀnecessaryꢀtoꢀprovideꢀoscillation.ꢀForꢀ

applicationsꢀwhereꢀpreciseꢀfrequenciesꢀareꢀessential,ꢀtheseꢀcomponentsꢀmayꢀbeꢀrequiredꢀtoꢀprovideꢀ

frequencyꢀcompensationꢀdueꢀtoꢀdifferentꢀcrystalꢀmanufacturingꢀtolerances.ꢀAfterꢀtheꢀLXTꢀoscillatorꢀ

isꢀenabledꢀbyꢀsettingꢀtheꢀLXTENꢀbitꢀtoꢀ“1”,ꢀthereꢀisꢀaꢀtimeꢀdelayꢀassociatedꢀwithꢀtheꢀLXTꢀoscillatorꢀ

waitingꢀforꢀitꢀtoꢀstart-up.

WhenꢀtheꢀmicrocontrollerꢀentersꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀtheꢀsystemꢀclockꢀisꢀswitchedꢀoffꢀtoꢀstopꢀ

microcontrollerꢀactivityꢀandꢀtoꢀconserveꢀpower.ꢀHowever,ꢀinꢀmanyꢀmicrocontrollerꢀapplicationsꢀ

itꢀmayꢀbeꢀnecessaryꢀtoꢀkeepꢀtheꢀinternalꢀtimersꢀoperationalꢀevenꢀwhenꢀtheꢀmicrocontrollerꢀisꢀinꢀ

theꢀSLEEPꢀorꢀIDLEꢀMode.ꢀToꢀdoꢀthis,ꢀanotherꢀclock,ꢀindependentꢀofꢀtheꢀsystemꢀclock,ꢀmustꢀbeꢀ

provided.ꢀ

However,ꢀforꢀsomeꢀcrystals,ꢀtoꢀensureꢀoscillationꢀandꢀaccurateꢀfrequencyꢀgeneration,ꢀitꢀisꢀnecessaryꢀ

toꢀaddꢀtwoꢀsmallꢀvalueꢀexternalꢀcapacitors,ꢀC1ꢀandꢀC2.ꢀTheꢀexactꢀvaluesꢀofꢀC1ꢀandꢀC2ꢀshouldꢀbeꢀ

selectedꢀinꢀconsultationꢀwithꢀtheꢀcrystalꢀorꢀresonatorꢀmanufacturer’sꢀspecification.ꢀTheꢀexternalꢀ

parallelꢀfeedbackꢀresistor,ꢀR_P,ꢀandꢀtheꢀpullꢀhighꢀresistor,ꢀR_U,ꢀareꢀrequired.

Theꢀpin-sharedꢀsoftwareꢀcontrolꢀbitsꢀdetermineꢀifꢀtheꢀXT1/XT2ꢀpinsꢀareꢀusedꢀforꢀtheꢀLXTꢀoscillatorꢀ

orꢀasꢀI/Oꢀorꢀotherꢀpin-sharedꢀfunctionalꢀpins.

•ꢀ IfꢀtheꢀLXTꢀoscillatorꢀisꢀnotꢀusedꢀforꢀanyꢀclockꢀsource,ꢀtheꢀXT1/XT2ꢀpinsꢀcanꢀbeꢀusedꢀasꢀnormalꢀ

I/Oꢀorꢀotherꢀpin-sharedꢀfunctionalꢀpins.

•ꢀ IfꢀtheꢀLXTꢀoscillatorꢀisꢀusedꢀforꢀanyꢀclockꢀsource,ꢀtheꢀ32.768kHzꢀcrystalꢀshouldꢀbeꢀconnectedꢀtoꢀ

theꢀXT1/XT2ꢀpins.

Forꢀoscillatorꢀstabilityꢀandꢀtoꢀminimiseꢀtheꢀeffectsꢀofꢀnoiseꢀandꢀcrosstalk,ꢀitꢀisꢀimportantꢀtoꢀensureꢀ

thatꢀtheꢀcrystalꢀandꢀanyꢀassociatedꢀresistorsꢀandꢀcapacitorsꢀalongꢀwithꢀinterconnectingꢀlinesꢀareꢀallꢀ

locatedꢀasꢀcloseꢀtoꢀtheꢀMCUꢀasꢀpossible.

V_DD

Internal

Oscillator

Circuit

C1

XT1

XT2

3ꢅ.76ꢆ

kHz

Inteꢁnal RC

Oscillatoꢁ

R_P

R_U

To inteꢁnal

ciꢁcꢀits

Cꢅ

Note: 1. R_Pꢄ R_Uꢄ C1 and Cꢅ aꢁe ꢁeqꢀiꢁed.

2. Although not shown XT1/XTꢅ pins have a paꢁasitic

capacitance of aꢁoꢀnd 7pF.

External LXT Oscillator

Rev. 1.10

5ꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

LXT Oscillator C1 and C2 Values

Crystal Frequency

C1

C2

3ꢅ.76ꢆkHz

10pF

Note: 1. C1 and Cꢅ valꢀes aꢁe foꢁ gꢀidance onlꢂ.

ꢅ. R_P=5M~10MΩ is recommended.

3. R_U=10MΩ is recommended.

32.768kHz Crystal Recommended Capacitor Values

Internal 32kHz Oscillator − LIRC

Theꢀinternalꢀ32kHzꢀsystemꢀoscillatorꢀisꢀoneꢀofꢀtheꢀlowꢀfrequencyꢀoscillatorꢀchoices,ꢀwhichꢀisꢀ

selectedꢀviaꢀaꢀsoftwareꢀcontrolꢀbit,ꢀFSS.ꢀItꢀisꢀaꢀfullyꢀintegratedꢀRCꢀoscillatorꢀwithꢀaꢀtypicalꢀfrequencyꢀ

ofꢀ32kHzꢀatꢀ5V,ꢀrequiringꢀnoꢀexternalꢀcomponentsꢀforꢀitsꢀimplementation.ꢀDeviceꢀtrimmingꢀduringꢀ

theꢀmanufacturingꢀprocessꢀandꢀtheꢀinclusionꢀofꢀinternalꢀfrequencyꢀcompensationꢀcircuitsꢀareꢀusedꢀ

toꢀensureꢀthatꢀtheꢀinﬂuenceꢀofꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀtemperatureꢀandꢀprocessꢀvariationsꢀonꢀtheꢀ

oscillationꢀfrequencyꢀareꢀminimised.ꢀ

Operating Modes and System Clocks

Presentꢀdayꢀapplicationsꢀrequireꢀthatꢀtheirꢀmicrocontrollersꢀhaveꢀhighꢀperformanceꢀbutꢀoftenꢀstillꢀ

demandꢀthatꢀtheyꢀconsumeꢀasꢀlittleꢀpowerꢀasꢀpossible,ꢀconﬂictingꢀrequirementsꢀthatꢀareꢀespeciallyꢀ

trueꢀinꢀbatteryꢀpoweredꢀportableꢀapplications.ꢀTheꢀfastꢀclocksꢀrequiredꢀforꢀhighꢀperformanceꢀwillꢀ

byꢀtheirꢀnatureꢀincreaseꢀcurrentꢀconsumptionꢀandꢀofꢀcourseꢀviceꢀversa,ꢀlowerꢀspeedꢀclocksꢀreduceꢀ

currentꢀconsumption.ꢀAsꢀbothꢀhighꢀandꢀlowꢀspeedꢀclockꢀsourcesꢀareꢀprovidedꢀtheꢀmeansꢀtoꢀswitchꢀ

betweenꢀthemꢀdynamically,ꢀtheꢀuserꢀcanꢀoptimiseꢀtheꢀoperationꢀofꢀtheirꢀmicrocontrollerꢀtoꢀachieveꢀ

theꢀbestꢀperformance/powerꢀratio.

System Clocks

TheseꢀdevicesꢀhaveꢀdifferentꢀclockꢀsourcesꢀforꢀbothꢀtheꢀCPUꢀandꢀperipheralꢀfunctionꢀoperation.ꢀByꢀ

providingꢀtheꢀuserꢀwithꢀaꢀwideꢀrangeꢀofꢀclockꢀselectionsꢀusingꢀregisterꢀprogramming,ꢀaꢀclockꢀsystemꢀ

canꢀbeꢀconﬁguredꢀtoꢀobtainꢀmaximumꢀapplicationꢀperformance.

Theꢀmainꢀsystemꢀclock,ꢀcanꢀcomeꢀfromꢀeitherꢀaꢀhighꢀfrequency,ꢀf_H,ꢀorꢀlowꢀfrequency,ꢀf_SUB,ꢀsource,ꢀ

andꢀisꢀselectedꢀusingꢀtheꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSCCꢀregister.ꢀTheꢀhighꢀspeedꢀsystemꢀclockꢀisꢀ

sourcedꢀfromꢀanꢀHXTꢀorꢀHIRCꢀoscillator.ꢀTheꢀlowꢀspeedꢀsystemꢀclockꢀsourceꢀcanꢀbeꢀsourcedꢀ

fromꢀtheꢀinternalꢀclockꢀf_SUB.ꢀIfꢀf_SUBꢀisꢀselectedꢀthenꢀitꢀcanꢀbeꢀsourcedꢀbyꢀeitherꢀtheꢀLXTꢀorꢀLIRCꢀ

oscillators,ꢀselectedꢀviaꢀconﬁguringꢀtheꢀFSSꢀbitꢀinꢀtheꢀSCCꢀregister.ꢀTheꢀotherꢀchoice,ꢀwhichꢀisꢀaꢀ

dividedꢀversionꢀofꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀhasꢀaꢀrangeꢀofꢀf_H/2~f_H/64.

Rev. 1.10

55

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

f_H

High Speed

Oscillatoꢁs

FHS

f_H/ꢅ

f_H/ꢃ

HXTEN

HXT

f_H/ꢆ

IDLE0

SLEEP

Pꢁescaleꢁ

f_H/16

f_H/3ꢅ

f_H/6ꢃ

f_SYS

HIRCEN

HIRC

FSS

Low Speed

Oscillatoꢁs

LXTEN

LXT

CKSꢅ~CKS0

f_SUB

f_SYS

IDLEꢅ

SLEEP

f_LIRC

LIRC

f_LIRC

f_PSC

f_SYS/ꢃ

f_SUB

WDT

LVR

Pꢁescaleꢁ

Time Bases

f_LIRC

TB1[ꢅ:0] TB0[ꢅ:0]

CLKSEL[1:0]

Device Clock Conﬁgurations

Note:ꢀWhenꢀtheꢀsystemꢀclockꢀsourceꢀf_SYSꢀisꢀswitchedꢀtoꢀf_SUBꢀfromꢀf_H,ꢀtheꢀhighꢀspeedꢀoscillatorꢀcanꢀbeꢀ

stoppedꢀtoꢀconserveꢀtheꢀpowerꢀorꢀcontinueꢀtoꢀoscillateꢀtoꢀprovideꢀtheꢀclockꢀsource,ꢀf_H~f_H/64,ꢀ

forꢀperipheralꢀcircuitꢀtoꢀuse,ꢀwhichꢀisꢀdeterminedꢀbyꢀconﬁguringꢀtheꢀcorrespondingꢀhighꢀspeedꢀ

oscillatorꢀenableꢀcontrolꢀbit.

System Operation Modes

Thereꢀareꢀsixꢀdifferentꢀmodesꢀofꢀoperationꢀforꢀtheꢀmicrocontroller,ꢀeachꢀoneꢀwithꢀitsꢀownꢀ

specialꢀcharacteristicsꢀandꢀwhichꢀcanꢀbeꢀchosenꢀaccordingꢀtoꢀtheꢀspecificꢀperformanceꢀandꢀ

powerꢀrequirementsꢀofꢀtheꢀapplication.ꢀThereꢀareꢀtwoꢀmodesꢀallowingꢀnormalꢀoperationꢀofꢀtheꢀ

microcontroller,ꢀtheꢀFASTꢀModeꢀandꢀSLOWꢀMode.ꢀTheꢀremainingꢀfourꢀmodes,ꢀtheꢀSLEEP,ꢀIDLE0,ꢀ

IDLE1ꢀandꢀIDLE2ꢀModeꢀareꢀusedꢀwhenꢀtheꢀmicrocontrollerꢀCPUꢀisꢀswitchedꢀoffꢀtoꢀconserveꢀpower.

Register Setting

FHIDEN FSIDEN CKS2~CKS0

Operation

Mode

CPU

f_SYS

f_H

f_SUB

f_LIRC

FAST

On

x

000~110

f_H~f_H/6ꢃ

On

On/Off ⁽¹⁾

On

SLOW

111

000~110

111

f_SUB

Off

On

IDLE0

IDLE1

IDLEꢅ

SLEEP

Off

0

1

0

1

0

Off

On

Off

On

Off

On

xxx

On

000~110

111

On

Off

xxx

On/Off ^(ꢅ)

“x” don’t caꢁe

Note:ꢀ1.ꢀTheꢀf_Hꢀclockꢀwillꢀbeꢀswitchedꢀonꢀorꢀoffꢀbyꢀconﬁguringꢀtheꢀcorrespondingꢀoscillatorꢀenableꢀ

bitꢀinꢀtheꢀSLOWꢀmode.

2.ꢀTheꢀf_LIRCꢀclockꢀcanꢀbeꢀswitchedꢀonꢀorꢀoffꢀwhichꢀisꢀcontrolledꢀbyꢀtheꢀWDTꢀfunctionꢀbeingꢀ

enabledꢀorꢀdisabled.

Rev. 1.10

56

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

FAST Mode

Asꢀtheꢀnameꢀsuggestsꢀthisꢀisꢀoneꢀofꢀtheꢀmainꢀoperatingꢀmodesꢀwhereꢀtheꢀmicrocontrollerꢀhasꢀallꢀofꢀ

itsꢀfunctionsꢀoperationalꢀandꢀwhereꢀtheꢀsystemꢀclockꢀisꢀprovidedꢀbyꢀoneꢀofꢀtheꢀhighꢀspeedꢀoscillators.ꢀ

Thisꢀmodeꢀoperatesꢀallowingꢀtheꢀmicrocontrollerꢀtoꢀoperateꢀnormallyꢀwithꢀaꢀclockꢀsourceꢀwillꢀcomeꢀ

fromꢀoneꢀofꢀtheꢀhighꢀspeedꢀoscillators,ꢀeitherꢀtheꢀHXTꢀorꢀHIRCꢀoscillators.ꢀTheꢀhighꢀspeedꢀoscillatorꢀ

willꢀhoweverꢀfirstꢀbeꢀdividedꢀbyꢀaꢀratioꢀrangingꢀfromꢀ1ꢀtoꢀ64,ꢀtheꢀactualꢀratioꢀbeingꢀselectedꢀbyꢀ

theꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSCCꢀregister.ꢀAlthoughꢀaꢀhighꢀspeedꢀoscillatorꢀisꢀused,ꢀrunningꢀtheꢀ

microcontrollerꢀatꢀaꢀdividedꢀclockꢀratioꢀreducesꢀtheꢀoperatingꢀcurrent.

SLOW Mode

Thisꢀisꢀalsoꢀaꢀmodeꢀwhereꢀtheꢀmicrocontrollerꢀoperatesꢀnormallyꢀalthoughꢀnowꢀwithꢀaꢀslowerꢀspeedꢀ

clockꢀsource.ꢀTheꢀclockꢀsourceꢀusedꢀwillꢀbeꢀfromꢀf_SUB.ꢀTheꢀf_SUBꢀclockꢀisꢀderivedꢀfromꢀeitherꢀtheꢀ

LIRCꢀorꢀLXTꢀoscillator.ꢀ

SLEEP Mode

TheꢀSLEEPꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀFHIDENꢀandꢀ

FSIDENꢀbitꢀareꢀlow.ꢀInꢀtheꢀSLEEPꢀmodeꢀtheꢀCPUꢀwillꢀbeꢀstopped.ꢀHoweverꢀtheꢀf_LIRCꢀclockꢀcanꢀstillꢀ

continueꢀtoꢀoperateꢀifꢀtheꢀWDTꢀfunctionꢀisꢀenabled.

IDLE0 Mode

TheꢀIDLE0ꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀFHIDENꢀbitꢀinꢀ

theꢀSCCꢀregisterꢀisꢀlowꢀandꢀtheꢀFSIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀisꢀhigh.ꢀInꢀtheꢀIDLE0ꢀModeꢀtheꢀ

CPUꢀwillꢀbeꢀswitchedꢀoffꢀbutꢀtheꢀlowꢀspeedꢀoscillatorꢀwillꢀbeꢀturnedꢀonꢀtoꢀdriveꢀsomeꢀperipheralꢀ

functions.

IDLE1 Mode

TheꢀIDLE1ꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀFHIDENꢀbitꢀinꢀtheꢀ

SCCꢀregisterꢀisꢀhighꢀandꢀtheꢀFSIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀisꢀhigh.ꢀInꢀtheꢀIDLE1ꢀModeꢀtheꢀCPUꢀ

willꢀbeꢀswitchedꢀoffꢀbutꢀbothꢀtheꢀhighꢀandꢀlowꢀspeedꢀoscillatorsꢀwillꢀbeꢀturnedꢀonꢀtoꢀprovideꢀaꢀclockꢀ

sourceꢀtoꢀkeepꢀsomeꢀperipheralꢀfunctionsꢀoperational.

IDLE2 Mode

TheꢀIDLE2ꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀFHIDENꢀbitꢀinꢀtheꢀ

SCCꢀregisterꢀisꢀhighꢀandꢀtheꢀFSIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀisꢀlow.ꢀInꢀtheꢀIDLE2ꢀModeꢀtheꢀCPUꢀ

willꢀbeꢀswitchedꢀoffꢀbutꢀtheꢀhighꢀspeedꢀoscillatorꢀwillꢀbeꢀturnedꢀonꢀtoꢀprovideꢀaꢀclockꢀsourceꢀtoꢀkeepꢀ

someꢀperipheralꢀfunctionsꢀoperational.

Control Registers

Theꢀregisters,ꢀSCC,ꢀHIRCC,ꢀHXTCꢀandꢀLXTC,ꢀareꢀusedꢀforꢀtheꢀoverallꢀcontrolꢀofꢀtheꢀsystemꢀclockꢀ

withinꢀtheseꢀdevices.

Bit

Register

Name

7

CKSꢅ

—

6

CKS1

—

5

CKS0

—

4

3

FHS

HIRC1

—

2

1

0

SCC

HIRCC

HXTC

LXTC

—

FSS

HIRC0

HXTM

—

FHIDEN FSIDEN

HIRCF

HXTF

LXTF

HIRCEN

HXTEN

LXTEN

—

System Operating Mode Control Registers List

Rev. 1.10

57

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

SCC Register

Bit

Name

R/W

7

CKSꢅ

R/W

0

6

CKS1

R/W

0

5

CKS0

R/W

0

4

3

2

1

0

—

FHS

R/W

0

FSS

R/W

0

FHIDEN FSIDEN

R/W

0

R/W

0

POR

Bitꢀ7~5

CKS2~CKS0:ꢀSystemꢀClockꢀSelection

000:ꢀf_H

001:ꢀf_H/2

010:ꢀf_H/4

011:ꢀf_H/8

100:ꢀf_H/16

101:ꢀf_H/32

110:ꢀf_H/64

111:ꢀf_SUB

Theseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀwhichꢀclockꢀisꢀusedꢀasꢀtheꢀsystemꢀclockꢀsource.ꢀInꢀ

additionꢀtoꢀtheꢀsystemꢀclockꢀsourceꢀdirectlyꢀderivedꢀfromꢀf_Hꢀorꢀf_SUB,ꢀaꢀdividedꢀversionꢀ

ofꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀcanꢀalsoꢀbeꢀchosenꢀasꢀtheꢀsystemꢀclockꢀsource.

Bitꢀ4ꢀ

Bitꢀ3

Unimplemented,ꢀreadꢀasꢀ“0”

FHS:ꢀHighꢀFrequencyꢀClockꢀSelection

0:ꢀHIRC

1:ꢀHXT

Bitꢀ2

Bitꢀ1

FSS:ꢀLowꢀFrequencyꢀClockꢀSelection

0:ꢀLIRC

1:ꢀLXT

FHIDEN:ꢀHighꢀFrequencyꢀOscillatorꢀControlꢀwhenꢀCPUꢀisꢀSwitchedꢀOff

0:ꢀDisable

1:ꢀEnable

Thisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀwhetherꢀtheꢀhighꢀspeedꢀoscillatorꢀisꢀactivatedꢀorꢀstoppedꢀ

whenꢀtheꢀCPUꢀisꢀswitchedꢀoffꢀbyꢀexecutingꢀanꢀ“HALT”ꢀinstruction.

Bitꢀ0

FSIDEN:ꢀLowꢀFrequencyꢀOscillatorꢀControlꢀwhenꢀCPUꢀisꢀSwitchedꢀOff

0:ꢀDisable

1:ꢀEnable

Thisꢀbitꢀisꢀusedꢀtoꢀcontrolꢀwhetherꢀtheꢀlowꢀspeedꢀoscillatorꢀisꢀactivatedꢀorꢀstoppedꢀ

whenꢀtheꢀCPUꢀisꢀswitchedꢀoffꢀbyꢀexecutingꢀanꢀ“HALT”ꢀinstruction.ꢀTheꢀLIRCꢀ

oscillatorꢀisꢀcontrolledꢀbyꢀthisꢀbitꢀtogetherꢀwithꢀtheꢀWDTꢀfunctionꢀenableꢀcontrolꢀwhenꢀ

theꢀLIRCꢀisꢀselectedꢀtoꢀbeꢀtheꢀlowꢀspeedꢀoscillatorꢀclockꢀsourceꢀorꢀtheꢀWDTꢀfunctionꢀ

isꢀenabledꢀrespectively.ꢀIfꢀthisꢀbitꢀisꢀclearedꢀtoꢀ“0”ꢀbutꢀtheꢀWDTꢀfunctionꢀisꢀenabled,ꢀ

theꢀLIRCꢀoscillatorꢀwillꢀalsoꢀbeꢀenabled.

Rev. 1.10

5ꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

HIRCC Register

Bit

Name

R/W

7

6

5

4

3

HIRC1

R/W

0

2

HIRC0

R/W

0

1

0

HIRCEN

R/W

1

—

HIRCF

R

0

POR

Bitꢀ7~4ꢀ

Bitꢀ3~2

Unimplemented,ꢀreadꢀasꢀ“0”

HIRC1~HIRC0:ꢀHIRCꢀFrequencyꢀSelection

00:ꢀ4MHz

01:ꢀ8MHz

10:ꢀ12MHz

11:ꢀ4MHz

WhenꢀtheꢀHIRCꢀoscillatorꢀisꢀenabledꢀorꢀtheꢀHIRCꢀfrequencyꢀselectionꢀisꢀchangedꢀ

byꢀapplicationꢀprogram,ꢀtheꢀclockꢀfrequencyꢀwillꢀautomaticallyꢀbeꢀchangedꢀafterꢀtheꢀ

HIRCFꢀﬂagꢀisꢀsetꢀtoꢀ“1”.

Bitꢀ1

HIRCF:ꢀHIRCꢀOscillatorꢀStableꢀFlag

0:ꢀHIRCꢀunstable

1:ꢀHIRCꢀstable

ThisꢀbitꢀisꢀusedꢀtoꢀindicateꢀwhetherꢀtheꢀHIRCꢀoscillatorꢀisꢀstableꢀorꢀnot.ꢀWhenꢀtheꢀ

HIRCENꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀtoꢀenableꢀtheꢀHIRCꢀoscillatorꢀorꢀtheꢀHIRCꢀfrequencyꢀ

selectionꢀisꢀchangedꢀbyꢀapplicationꢀprogram,ꢀtheꢀHIRCFꢀbitꢀwillꢀﬁrstꢀbeꢀclearedꢀtoꢀ“0”ꢀ

andꢀthenꢀsetꢀtoꢀ“1”ꢀafterꢀtheꢀHIRCꢀoscillatorꢀisꢀstable.

Bitꢀ0

HIRCEN:ꢀHIRCꢀOscillatorꢀEnableꢀControl

0:ꢀDisable

1:ꢀEnable

HXTC Register

Bit

Name

R/W

7

6

5

4

3

2

HXTM

R/W

0

1

HXTF

R

0

HXTEN

R/W

0

—

POR

0

Bitꢀ7~3ꢀ

Bitꢀ2

Unimplemented,ꢀreadꢀasꢀ“0”

HXTM:ꢀHXTꢀModeꢀSelection

0:ꢀHXTꢀfrequencyꢀ ꢀ10MHz

≤

1:ꢀHXTꢀfrequencyꢀ 10MHz

>

ThisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀHXTꢀoscillatorꢀoperatingꢀmode.ꢀNoteꢀthatꢀthisꢀbitꢀmustꢀbeꢀ

properlyꢀconﬁguredꢀbeforeꢀtheꢀHXTꢀisꢀenabled.ꢀWhenꢀtheꢀHXTENꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀtoꢀ

enableꢀtheꢀHXTꢀoscillator,ꢀitꢀisꢀinvalidꢀtoꢀchangeꢀtheꢀvalueꢀofꢀthisꢀbit.

Bitꢀ1

Bitꢀ0

HXTF:ꢀHXTꢀOscillatorꢀStableꢀFlag

0:ꢀHXTꢀunstable

1:ꢀHXTꢀstable

ThisꢀbitꢀisꢀusedꢀtoꢀindicateꢀwhetherꢀtheꢀHXTꢀoscillatorꢀisꢀstableꢀorꢀnot.ꢀWhenꢀtheꢀ

HXTENꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀtoꢀenableꢀtheꢀHXTꢀoscillator,ꢀtheꢀHXTFꢀbitꢀwillꢀfirstꢀbeꢀ

clearedꢀtoꢀ“0”ꢀandꢀthenꢀsetꢀtoꢀ“1”ꢀafterꢀtheꢀHXTꢀoscillatorꢀisꢀstable.

HXTEN:ꢀHXTꢀOscillatorꢀEnableꢀControl

0:ꢀDisable

1:ꢀEnable

Rev. 1.10

59

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

LXTC Register

Bit

Name

R/W

7

6

5

4

3

2

1

LXTF

R

0

LXTEN

R/W

0

—

POR

0

Bitꢀ7~2ꢀ

Bitꢀ1

Unimplemented,ꢀreadꢀasꢀ“0”

LXTF:ꢀLXTꢀOscillatorꢀStableꢀFlag

0:ꢀLXTꢀunstable

1:ꢀLXTꢀstable

ThisꢀbitꢀisꢀusedꢀtoꢀindicateꢀwhetherꢀtheꢀLXTꢀoscillatorꢀisꢀstableꢀorꢀnot.ꢀWhenꢀtheꢀ

LXTENꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀtoꢀenableꢀtheꢀLXTꢀoscillator,ꢀtheꢀLXTFꢀbitꢀwillꢀﬁrstꢀbeꢀclearedꢀ

toꢀ“0”ꢀandꢀthenꢀsetꢀtoꢀ“1”ꢀafterꢀtheꢀLXTꢀoscillatorꢀisꢀstable.

Bitꢀ0

LXTEN:ꢀLXTꢀOscillatorꢀEnableꢀControl

0:ꢀDisable

1:ꢀEnable

Operating Mode Switching

Theꢀdeviceꢀcanꢀswitchꢀbetweenꢀoperatingꢀmodesꢀdynamicallyꢀallowingꢀtheꢀuserꢀtoꢀselectꢀtheꢀbestꢀ

performance/powerꢀratioꢀforꢀtheꢀpresentꢀtaskꢀinꢀhand.ꢀInꢀthisꢀwayꢀmicrocontrollerꢀoperationsꢀthatꢀ

doꢀnotꢀrequireꢀhighꢀperformanceꢀcanꢀbeꢀexecutedꢀusingꢀslowerꢀclocksꢀthusꢀrequiringꢀlessꢀoperatingꢀ

currentꢀandꢀprolongingꢀbatteryꢀlifeꢀinꢀportableꢀapplications.

Inꢀsimpleꢀterms,ꢀModeꢀSwitchingꢀbetweenꢀtheꢀFASTꢀModeꢀandꢀSLOWꢀModeꢀisꢀexecutedꢀusingꢀtheꢀ

CKS2~CKS0ꢀbitsꢀinꢀtheꢀSCCꢀregisterꢀwhileꢀModeꢀSwitchingꢀfromꢀtheꢀFAST/SLOWꢀModesꢀtoꢀtheꢀ

SLEEP/IDLEꢀModesꢀisꢀexecutedꢀviaꢀtheꢀHALTꢀinstruction.ꢀWhenꢀanꢀHALTꢀinstructionꢀisꢀexecuted,ꢀ

whetherꢀtheꢀdeviceꢀentersꢀtheꢀIDLEꢀModeꢀorꢀtheꢀSLEEPꢀModeꢀisꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀtheꢀ

FHIDENꢀandꢀFSIDENꢀbitsꢀinꢀtheꢀSCCꢀregister.

FAST

f_SYS=f_H~f_H/6ꢃ

f_Hon

SLOW

f_SYS=f_SUB

f_SUBon

CPU ꢁꢀn

f_SYSon

CPU ꢁꢀn

f_SYSon

f_SUBon

f_Hon/off

SLEEP

HALT instꢁꢀction execꢀted

CPU stop

IDLE0

HALT instꢁꢀction execꢀted

CPU stop

FHIDEN=0

FSIDEN=0

FSIDEN=1

f_Hoff

f_SUBoff

f_SUBon

IDLE2

IDLE1

HALT instꢁꢀction execꢀted

CPU stop

HALT instꢁꢀction execꢀted

CPU stop

FHIDEN=1

FSIDEN=0

f_Hon

FHIDEN=1

FSIDEN=1

f_Hon

f_SUBoff

f_SUBon

Rev. 1.10

60

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

FAST Mode to SLOW Mode Switching

WhenꢀrunningꢀinꢀtheꢀFASTꢀMode,ꢀwhichꢀusesꢀtheꢀhighꢀspeedꢀsystemꢀoscillator,ꢀandꢀthereforeꢀ

consumesꢀmoreꢀpower,ꢀtheꢀsystemꢀclockꢀcanꢀswitchꢀtoꢀrunꢀinꢀtheꢀSLOWꢀModeꢀbyꢀsetꢀtheꢀ

CKS2~CKS0ꢀbitsꢀtoꢀ“111”ꢀinꢀtheꢀSCCꢀregister.ꢀThisꢀwillꢀthenꢀuseꢀtheꢀlowꢀspeedꢀsystemꢀoscillatorꢀ

whichꢀwillꢀconsumeꢀlessꢀpower.ꢀUsersꢀmayꢀdecideꢀtoꢀdoꢀthisꢀforꢀcertainꢀoperationsꢀwhichꢀdoꢀnotꢀ

requireꢀhighꢀperformanceꢀandꢀcanꢀsubsequentlyꢀreduceꢀpowerꢀconsumption.

TheꢀSLOWꢀModeꢀisꢀsourcedꢀfromꢀtheꢀLXTꢀorꢀLIRCꢀoscillatorꢀdeterminedꢀbyꢀtheꢀFSSꢀbitꢀinꢀtheꢀSCCꢀ

registerꢀandꢀthereforeꢀrequiresꢀthisꢀoscillatorꢀtoꢀbeꢀstableꢀbeforeꢀfullꢀmodeꢀswitchingꢀoccurs.

FAST Mode

CKSꢅ~CKS0 = 111

SLOW Mode

FHIDEN=0ꢄ FSIDEN=0

HALT instꢁꢀction is execꢀted

SLEEP Mode

FHIDEN=0ꢄ FSIDEN=1

HALT instꢁꢀction is execꢀted

IDLE0 Mode

FHIDEN=1ꢄ FSIDEN=1

HALT instꢁꢀction is execꢀted

IDLE1 Mode

FHIDEN=1ꢄ FSIDEN=0

HALT instꢁꢀction is execꢀted

IDLE2 Mode

Rev. 1.10

61

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

SLOW Mode to FAST Mode Switching

InꢀSLOWꢀmodeꢀtheꢀsystemꢀclockꢀisꢀderivedꢀfromꢀf_SUB.ꢀWhenꢀsystemꢀclockꢀisꢀswitchedꢀbackꢀtoꢀtheꢀ

FASTꢀmodeꢀfromꢀf_SUB,ꢀtheꢀCKS2ꢀ~ꢀCKS0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ“000”ꢀ~ꢀ“110”ꢀandꢀthenꢀtheꢀsystemꢀ

clockꢀwillꢀrespectivelyꢀbeꢀswitchedꢀtoꢀf_Hꢀ~ꢀf_H/64.

However,ꢀifꢀf_HꢀisꢀnotꢀusedꢀinꢀSLOWꢀmodeꢀandꢀthusꢀswitchedꢀoff,ꢀitꢀwillꢀtakeꢀsomeꢀtimeꢀtoꢀre-

oscillateꢀandꢀstabiliseꢀwhenꢀswitchingꢀtoꢀtheꢀFASTꢀmodeꢀfromꢀtheꢀSLOWꢀMode.ꢀThisꢀisꢀmonitoredꢀ

usingꢀtheꢀHXTFꢀbitꢀinꢀtheꢀHXTCꢀregisterꢀorꢀtheꢀHIRCFꢀbitꢀinꢀtheꢀHIRCCꢀregister.ꢀTheꢀtimeꢀdurationꢀ

requiredꢀforꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀstabilizationꢀisꢀspeciﬁedꢀinꢀtheꢀtheꢀSystemꢀStartꢀUpꢀTimeꢀ

Characteristics.

SLOW Mode

CKSꢅ~CKS0 = 000~110

FAST Mode

FHIDEN=0ꢄ FSIDEN=0

HALT instꢁꢀction is execꢀted

SLEEP Mode

FHIDEN=0ꢄ FSIDEN=1

HALT instꢁꢀction is execꢀted

IDLE0 Mode

FHIDEN=1ꢄ FSIDEN=1

HALT instꢁꢀction is execꢀted

IDLE1 Mode

FHIDEN=1ꢄ FSIDEN=0

HALT instꢁꢀction is execꢀted

IDLE2 Mode

Entering the SLEEP Mode

ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheseꢀdevicesꢀtoꢀenterꢀtheꢀSLEEPꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ

instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀbothꢀtheꢀFHIDENꢀandꢀFSIDENꢀbitsꢀinꢀtheꢀSCCꢀregisterꢀ

equalꢀtoꢀ“0”.ꢀInꢀthisꢀmodeꢀallꢀtheꢀclocksꢀandꢀfunctionsꢀwillꢀbeꢀswitchedꢀoffꢀexceptꢀtheꢀWDTꢀfunction.ꢀ

Whenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:

•ꢀ Theꢀsystemꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ“HALT”ꢀ

instruction.

•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.

•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.

•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀﬂagꢀPDFꢀwillꢀbeꢀset,ꢀandꢀWDTꢀtimeoutꢀﬂagꢀTOꢀwillꢀbeꢀ

cleared.

•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀfunctionꢀisꢀenabled.ꢀIfꢀtheꢀWDTꢀ

functionꢀisꢀdisabled,ꢀtheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstopped.

Rev. 1.10

6ꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Entering the IDLE0 Mode

ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheseꢀdevicesꢀtoꢀenterꢀtheꢀIDLE0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ

instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀFHIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀequalꢀtoꢀ“0”ꢀandꢀtheꢀ

FSIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀequalꢀtoꢀ“1”.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀ

describedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:ꢀ

•ꢀ Theꢀf_Hꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ“HALT”ꢀinstruction,ꢀbutꢀ

theꢀf_SUBꢀclockꢀwillꢀbeꢀon.

•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.

•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.

•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀﬂagꢀPDFꢀwillꢀbeꢀset,ꢀandꢀWDTꢀtimeoutꢀﬂagꢀTOꢀwillꢀbeꢀ

cleared.

•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀfunctionꢀisꢀenabled.ꢀIfꢀtheꢀWDTꢀ

functionꢀisꢀdisabled,ꢀtheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstopped.

Entering the IDLE1 Mode

ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheseꢀdevicesꢀtoꢀenterꢀtheꢀIDLE0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ

instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀbothꢀtheꢀFHIDENꢀandꢀFSIDENꢀbitsꢀinꢀtheꢀSCCꢀregisterꢀ

equalꢀtoꢀ“1”.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀfollowingꢀ

willꢀoccur:ꢀ

•ꢀ Theꢀf_Hꢀandꢀf_SUBꢀclocksꢀwillꢀbeꢀonꢀbutꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ“HALT”ꢀinstruction.

•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.

•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.

•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀﬂagꢀPDFꢀwillꢀbeꢀset,ꢀandꢀWDTꢀtimeoutꢀﬂagꢀTOꢀwillꢀbeꢀ

cleared.

•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀfunctionꢀisꢀenabled.ꢀIfꢀtheꢀWDTꢀ

functionꢀisꢀdisabled,ꢀtheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstopped.

Entering the IDLE2 Mode

ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheseꢀdevicesꢀtoꢀenterꢀtheꢀIDLE2ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ

instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀFHIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀequalꢀtoꢀ“1”ꢀandꢀtheꢀ

FSIDENꢀbitꢀinꢀtheꢀSCCꢀregisterꢀequalꢀtoꢀ“0”.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀ

describedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:ꢀ

•ꢀ Theꢀf_Hꢀclockꢀwillꢀbeꢀonꢀbutꢀtheꢀf_SUBꢀclockꢀwillꢀbeꢀoffꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ

“HALT”ꢀinstruction.

•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.

•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.

•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀﬂagꢀPDFꢀwillꢀbeꢀset,ꢀandꢀWDTꢀtimeoutꢀﬂagꢀTOꢀwillꢀbeꢀ

cleared.

•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀfunctionꢀisꢀenabled.ꢀIfꢀtheꢀWDTꢀ

functionꢀisꢀdisabled,ꢀtheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstopped.

Rev. 1.10

63

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Standby Current Considerations

AsꢀtheꢀmainꢀreasonꢀforꢀenteringꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀtoꢀkeepꢀtheꢀcurrentꢀconsumptionꢀofꢀ

theseꢀdevicesꢀtoꢀasꢀlowꢀaꢀvalueꢀasꢀpossible,ꢀperhapsꢀonlyꢀinꢀtheꢀorderꢀofꢀseveralꢀmicro-ampsꢀexceptꢀ

inꢀtheꢀIDLE1ꢀandꢀIDLE2ꢀMode,ꢀthereꢀareꢀotherꢀconsiderationsꢀwhichꢀmustꢀalsoꢀbeꢀtakenꢀintoꢀaccountꢀ

byꢀtheꢀcircuitꢀdesignerꢀifꢀtheꢀpowerꢀconsumptionꢀisꢀtoꢀbeꢀminimised.ꢀSpecialꢀattentionꢀmustꢀbeꢀmadeꢀ

toꢀtheꢀI/Oꢀpinsꢀonꢀtheseꢀdevices.ꢀAllꢀhigh-impedanceꢀinputꢀpinsꢀmustꢀbeꢀconnectedꢀtoꢀeitherꢀaꢀﬁxedꢀ

highꢀorꢀlowꢀlevelꢀasꢀanyꢀﬂoatingꢀinputꢀpinsꢀcouldꢀcreateꢀinternalꢀoscillationsꢀandꢀresultꢀinꢀincreasedꢀ

currentꢀconsumption.ꢀThisꢀalsoꢀappliesꢀtoꢀtheꢀdevicesꢀwhichꢀhaveꢀdifferentꢀpackageꢀtypes,ꢀasꢀthereꢀ

mayꢀbeꢀunbonbedꢀpins.ꢀTheseꢀmustꢀeitherꢀbeꢀsetupꢀasꢀoutputsꢀorꢀifꢀsetupꢀasꢀinputsꢀmustꢀhaveꢀpull-

highꢀresistorsꢀconnected.

Careꢀmustꢀalsoꢀbeꢀtakenꢀwithꢀtheꢀloads,ꢀwhichꢀareꢀconnectedꢀtoꢀI/Oꢀpins,ꢀwhichꢀareꢀsetupꢀasꢀoutputs.ꢀ

Theseꢀshouldꢀbeꢀplacedꢀinꢀaꢀconditionꢀinꢀwhichꢀminimumꢀcurrentꢀisꢀdrawnꢀorꢀconnectedꢀonlyꢀtoꢀ

externalꢀcircuitsꢀthatꢀdoꢀnotꢀdrawꢀcurrent,ꢀsuchꢀasꢀotherꢀCMOSꢀinputs.ꢀAlsoꢀnoteꢀthatꢀadditionalꢀ

standbyꢀcurrentꢀwillꢀalsoꢀbeꢀrequiredꢀifꢀtheꢀLXTꢀorꢀLIRCꢀoscillatorꢀhasꢀenabled.

InꢀtheꢀIDLE1ꢀandꢀIDLEꢀ2ꢀModeꢀtheꢀhighꢀspeedꢀoscillatorꢀisꢀon,ꢀifꢀtheꢀperipheralꢀfunctionꢀclockꢀ

sourceꢀisꢀderivedꢀfromꢀtheꢀhighꢀspeedꢀoscillator,ꢀtheꢀadditionalꢀstandbyꢀcurrentꢀwillꢀalsoꢀbeꢀperhapsꢀ

inꢀtheꢀorderꢀofꢀseveralꢀhundredꢀmicro-amps.

Wake-up

ToꢀminimiseꢀpowerꢀconsumptionꢀtheꢀdeviceꢀcanꢀenterꢀtheꢀSLEEPꢀorꢀanyꢀIDLEꢀMode,ꢀwhereꢀtheꢀ

CPUꢀwillꢀbeꢀswitchedꢀoff.ꢀHowever,ꢀwhenꢀtheꢀdeviceꢀisꢀwokenꢀupꢀagain,ꢀitꢀwillꢀtakeꢀaꢀconsiderableꢀ

timeꢀforꢀtheꢀoriginalꢀsystemꢀoscillatorꢀtoꢀrestart,ꢀstabliseꢀandꢀallowꢀnormalꢀoperationꢀtoꢀresume.

AfterꢀtheꢀsystemꢀentersꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀitꢀcanꢀbeꢀwokenꢀupꢀfromꢀoneꢀofꢀvariousꢀsourcesꢀ

listedꢀasꢀfollows:

•ꢀ AnꢀexternalꢀfallingꢀedgeꢀonꢀPortꢀA

•ꢀ Aꢀsystemꢀinterrupt

•ꢀ AꢀWDTꢀoverﬂow

Whenꢀtheꢀdeviceꢀexecutesꢀtheꢀ“HALT”ꢀinstruction,ꢀtheꢀPDFꢀﬂagꢀwillꢀbeꢀsetꢀtoꢀ“1”.ꢀTheꢀPDFꢀﬂagꢀwillꢀ

beꢀclearedꢀtoꢀ“0ꢀifꢀtheꢀdeviceꢀexperiencesꢀaꢀsystemꢀpower-upꢀorꢀexecutesꢀtheꢀclearꢀWatchdogꢀTimerꢀ

instruction.ꢀIfꢀtheꢀsystemꢀisꢀwokenꢀupꢀbyꢀaꢀWDTꢀoverﬂow,ꢀaꢀWatchdogꢀTimerꢀresetꢀwillꢀbeꢀinitiatedꢀ

andꢀtheꢀTOꢀﬂagꢀwillꢀbeꢀsetꢀtoꢀ“1”.ꢀTheꢀTOꢀﬂagꢀisꢀsetꢀifꢀaꢀWDTꢀtime-outꢀoccursꢀandꢀcausesꢀaꢀwake-

upꢀthatꢀonlyꢀresetsꢀtheꢀProgramꢀCounterꢀandꢀStackꢀPointer,ꢀotherꢀﬂagsꢀremainꢀinꢀtheirꢀoriginalꢀstatus.

EachꢀpinꢀonꢀPortꢀAꢀcanꢀbeꢀsetupꢀusingꢀtheꢀPAWUꢀregisterꢀtoꢀpermitꢀaꢀnegativeꢀtransitionꢀonꢀtheꢀpinꢀ

toꢀwakeꢀupꢀtheꢀsystem.ꢀWhenꢀaꢀPortꢀAꢀpinꢀwake-upꢀoccurs,ꢀtheꢀprogramꢀwillꢀresumeꢀexecutionꢀatꢀ

theꢀinstructionꢀfollowingꢀtheꢀ“HALT”ꢀinstruction.ꢀIfꢀtheꢀsystemꢀisꢀwokenꢀupꢀbyꢀanꢀinterrupt,ꢀthenꢀ

twoꢀpossibleꢀsituationsꢀmayꢀoccur.ꢀTheꢀﬁrstꢀisꢀwhereꢀtheꢀrelatedꢀinterruptꢀisꢀdisabledꢀorꢀtheꢀinterruptꢀ

isꢀenabledꢀbutꢀtheꢀstackꢀisꢀfull,ꢀinꢀwhichꢀcaseꢀtheꢀprogramꢀwillꢀresumeꢀexecutionꢀatꢀtheꢀinstructionꢀ

followingꢀtheꢀ“HALT”ꢀinstruction.ꢀInꢀthisꢀsituation,ꢀtheꢀinterruptꢀwhichꢀwokeꢀupꢀtheꢀdeviceꢀwillꢀnotꢀ

beꢀimmediatelyꢀserviced,ꢀbutꢀwillꢀratherꢀbeꢀservicedꢀlaterꢀwhenꢀtheꢀrelatedꢀinterruptꢀisꢀﬁnallyꢀenabledꢀ

orꢀwhenꢀaꢀstackꢀlevelꢀbecomesꢀfree.ꢀTheꢀotherꢀsituationꢀisꢀwhereꢀtheꢀrelatedꢀinterruptꢀisꢀenabledꢀandꢀ

theꢀstackꢀisꢀnotꢀfull,ꢀinꢀwhichꢀcaseꢀtheꢀregularꢀinterruptꢀresponseꢀtakesꢀplace.ꢀIfꢀanꢀinterruptꢀrequestꢀ

flagꢀisꢀsetꢀhighꢀbeforeꢀenteringꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀtheꢀwake-upꢀfunctionꢀofꢀtheꢀrelatedꢀ

interruptꢀwillꢀbeꢀdisabled.

Rev. 1.10

6ꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Watchdog Timer

TheꢀWatchdogꢀTimerꢀisꢀprovidedꢀtoꢀpreventꢀprogramꢀmalfunctionsꢀorꢀsequencesꢀfromꢀjumpingꢀtoꢀ

unknownꢀlocations,ꢀdueꢀtoꢀcertainꢀuncontrollableꢀexternalꢀeventsꢀsuchꢀasꢀelectricalꢀnoise.

Watchdog Timer Clock Source

TheꢀWatchdogꢀTimerꢀclockꢀsourceꢀisꢀprovidedꢀbyꢀtheꢀinternalꢀclock,ꢀf_LIRC,ꢀwhichꢀisꢀinꢀturnꢀsuppliedꢀ

byꢀtheꢀLIRCꢀoscillator.ꢀTheꢀWatchdogꢀTimerꢀsourceꢀclockꢀisꢀthenꢀsubdividedꢀbyꢀaꢀratioꢀofꢀ2⁸ꢀtoꢀ2¹⁸ꢀtoꢀ

giveꢀlongerꢀtimeouts,ꢀtheꢀactualꢀvalueꢀbeingꢀchosenꢀusingꢀtheꢀWS2~WS0ꢀbitsꢀinꢀtheꢀWDTCꢀregister.ꢀ

TheꢀLIRCꢀinternalꢀoscillatorꢀhasꢀanꢀapproximateꢀfrequencyꢀofꢀ32kHzꢀandꢀthisꢀspecifiedꢀinternalꢀ

clockꢀperiodꢀcanꢀvaryꢀwithꢀV_DD,ꢀtemperatureꢀandꢀprocessꢀvariations.ꢀ

Watchdog Timer Control Register

Aꢀsingleꢀregister,ꢀWDTC,ꢀcontrolsꢀtheꢀrequiredꢀtimeoutꢀperiodꢀasꢀwellꢀasꢀtheꢀenable/disableꢀandꢀresetꢀ

MCUꢀoperation.

WDTC Register

Bit

Name

R/W

7

6

5

4

3

2

1

0

WEꢃ

R/W

0

WE3

R/W

1

WEꢅ

R/W

0

WE1

R/W

1

WE0

R/W

0

WSꢅ

R/W

0

WS1

R/W

1

WS0

R/W

1

POR

Bitꢀ7~3ꢀ

WE4~WE0:ꢀWDTꢀFunctionꢀSoftwareꢀControl

10101:ꢀDisable

01010:ꢀEnable

Others:ꢀResetꢀMCU

Whenꢀtheseꢀbitsꢀareꢀchangedꢀbyꢀtheꢀenvironmentalꢀnoiseꢀorꢀsoftwareꢀsettingꢀtoꢀresetꢀ

theꢀmicrocontroller,ꢀtheꢀresetꢀoperationꢀwillꢀbeꢀactivatedꢀafterꢀꢀaꢀdelayꢀtime,ꢀt_SRESET,ꢀandꢀ

theꢀWRFꢀbitꢀinꢀtheꢀRSTFCꢀregisterꢀwillꢀbeꢀsetꢀhigh.

Bitꢀ2~0

WS2~WS0:ꢀWDTꢀTime-outꢀPeriodꢀSelection

000:ꢀ2⁸/f_LIRC

001:ꢀ2¹⁰/f_LIRC

010:ꢀ2¹²/f_LIRC

011:ꢀ2¹⁴/f_LIRC

100:ꢀ2¹⁵/f_LIRC

101:ꢀ2¹⁶/f_LIRC

110:ꢀ2¹⁷/f_LIRC

111:ꢀ2¹⁸/f_LIRC

Theseꢀthreeꢀbitsꢀdetermineꢀtheꢀdivisionꢀratioꢀofꢀtheꢀwatchdogꢀtimerꢀsourceꢀclock,ꢀ

whichꢀinꢀturnꢀdeterminesꢀtheꢀtime-outꢀperiod.

Rev. 1.10

65

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

RSTFC Register

Bit

Name

R/W

7

6

5

4

3

RSTF

R/W

0

2

LVRF

R/W

x

1

0

WRF

—

LRF

R/W

0

R/W

POR

0

“x” ꢀnknown

Bitꢀ7~4ꢀ

Bitꢀ3

Unimplemented,ꢀreadꢀasꢀ“0”

RSTF:ꢀResetꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag

0:ꢀNotꢀoccurred

1:ꢀOccurred

Thisꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀbyꢀtheꢀRSTCꢀcontrolꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ

applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ“0”ꢀbyꢀtheꢀapplicationꢀ

program.

Bitꢀ2

Bitꢀ1

Bitꢀ0

LVRF:ꢀLVRꢀFunctionꢀResetꢀFlag

Describedꢀelsewhere.

LRF:ꢀLVRꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag

Describedꢀelsewhere.

WRF:ꢀWDTꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag

0:ꢀNotꢀoccur

1:ꢀOccurred

ThisꢀbitꢀisꢀsetꢀhighꢀbyꢀtheꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ

applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀzeroꢀbyꢀtheꢀapplicationꢀ

program.

Watchdog Timer Operation

TheꢀWatchdogꢀTimerꢀoperatesꢀbyꢀprovidingꢀaꢀdeviceꢀresetꢀwhenꢀitsꢀtimerꢀoverﬂows.ꢀThisꢀmeansꢀ

thatꢀinꢀtheꢀapplicationꢀprogramꢀandꢀduringꢀnormalꢀoperationꢀtheꢀuserꢀhasꢀtoꢀstrategicallyꢀclearꢀtheꢀ

WatchdogꢀTimerꢀbeforeꢀitꢀoverﬂowsꢀtoꢀpreventꢀtheꢀWatchdogꢀTimerꢀfromꢀexecutingꢀaꢀreset.ꢀThisꢀisꢀ

doneꢀusingꢀtheꢀclearꢀwatchdogꢀinstructions.ꢀIfꢀtheꢀprogramꢀmalfunctionsꢀforꢀwhateverꢀreason,ꢀjumpsꢀ

toꢀanꢀunknownꢀlocation,ꢀorꢀentersꢀanꢀendlessꢀloop,ꢀtheseꢀclearꢀinstructionsꢀwillꢀnotꢀbeꢀexecutedꢀinꢀtheꢀ

correctꢀmanner,ꢀinꢀwhichꢀcaseꢀtheꢀWatchdogꢀTimerꢀwillꢀoverﬂowꢀandꢀresetꢀtheꢀdevice.ꢀThereꢀareꢀﬁveꢀ

bits,ꢀWE4~WE0,ꢀinꢀtheꢀWDTCꢀregisterꢀtoꢀofferꢀtheꢀenable/disableꢀcontrolꢀandꢀresetꢀcontrolꢀofꢀtheꢀ

WatchdogꢀTimer.ꢀTheꢀWDTꢀfunctionꢀwillꢀbeꢀdisabledꢀwhenꢀtheꢀWE4~WE0ꢀbitsꢀareꢀsetꢀtoꢀaꢀvalueꢀofꢀ

10101BꢀwhileꢀtheꢀWDTꢀfunctionꢀwillꢀbeꢀenabledꢀifꢀtheꢀWE4~WE0ꢀbitsꢀareꢀequalꢀtoꢀ01010B.ꢀIfꢀtheꢀ

WE4~WE0ꢀbitsꢀareꢀsetꢀtoꢀanyꢀotherꢀvalues,ꢀotherꢀthanꢀ01010Bꢀandꢀ10101B,ꢀitꢀwillꢀresetꢀtheꢀdeviceꢀ

afterꢀaꢀdelayꢀtime,ꢀt_SRESET.ꢀAfterꢀpowerꢀonꢀtheseꢀbitsꢀwillꢀhaveꢀaꢀvalueꢀofꢀ01010B.

WE4~WE0 Bits

10101B

WDT Function

Disable

01010B

Enable

Anꢂ otheꢁ valꢀes

Reset MCU

Watchdog Timer Enable/Disable Control

Underꢀnormalꢀprogramꢀoperation,ꢀaꢀWatchdogꢀTimerꢀtime-outꢀwillꢀinitialiseꢀaꢀdeviceꢀresetꢀandꢀsetꢀ

theꢀstatusꢀbitꢀTO.ꢀHowever,ꢀifꢀtheꢀsystemꢀisꢀinꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀwhenꢀaꢀWatchdogꢀTimerꢀ

time-outꢀoccurs,ꢀtheꢀTOꢀbitꢀinꢀtheꢀstatusꢀregisterꢀwillꢀbeꢀsetꢀandꢀonlyꢀtheꢀProgramꢀCounterꢀandꢀStackꢀ

Pointerꢀwillꢀbeꢀreset.ꢀThreeꢀmethodsꢀcanꢀbeꢀadoptedꢀtoꢀclearꢀtheꢀcontentsꢀofꢀtheꢀWatchdogꢀTimer.ꢀ

TheꢀﬁrstꢀisꢀaꢀWDTꢀreset,ꢀwhichꢀmeansꢀaꢀcertainꢀvalueꢀexceptꢀ01010Bꢀandꢀ10101Bꢀwrittenꢀintoꢀtheꢀ

WE4~WE0ꢀbitꢀﬁled,ꢀtheꢀsecondꢀisꢀusingꢀtheꢀWatchdogꢀTimerꢀsoftwareꢀclearꢀinstructionꢀandꢀtheꢀthirdꢀ

isꢀviaꢀaꢀHALTꢀinstruction.ꢀ

Rev. 1.10

66

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

ThereꢀisꢀonlyꢀoneꢀmethodꢀofꢀusingꢀsoftwareꢀinstructionꢀtoꢀclearꢀtheꢀWatchdogꢀTimer.ꢀThatꢀisꢀtoꢀuseꢀ

theꢀsingleꢀ“CLRꢀWDT”ꢀinstructionꢀtoꢀclearꢀtheꢀWDT.

Theꢀmaximumꢀtimeꢀoutꢀperiodꢀisꢀwhenꢀtheꢀ2¹⁸ꢀdivisionꢀratioꢀisꢀselected.ꢀAsꢀanꢀexample,ꢀwithꢀaꢀ

32kHzꢀLIRCꢀoscillatorꢀasꢀitsꢀsourceꢀclock,ꢀthisꢀwillꢀgiveꢀaꢀmaximumꢀwatchdogꢀperiodꢀofꢀaroundꢀ8ꢀ

secondsꢀforꢀtheꢀ2¹⁸ꢀdivisionꢀratio,ꢀandꢀaꢀminimumꢀtimeoutꢀofꢀ8msꢀforꢀtheꢀ2⁸ꢀdivisionꢀration.

WDTC Registeꢁ

WEꢃ~WE0 bits

Reset MCU

CLR

“CLR WDT” Instꢁꢀction

“HALT” Instꢁꢀction

f_LIRC

f_LIRC/ꢅ^ꢆ

LIRC

ꢆ-stage Divideꢁ

WSꢅ~WS0

WDT Pꢁescaleꢁ

8-to-1 MUX

WDT Time-oꢀt

Watchdog Timer

Reset and Initialisation

Aꢀresetꢀfunctionꢀisꢀaꢀfundamentalꢀpartꢀofꢀanyꢀmicrocontrollerꢀensuringꢀthatꢀtheꢀdeviceꢀcanꢀbeꢀsetꢀtoꢀ

someꢀpredeterminedꢀconditionꢀirrespectiveꢀofꢀoutsideꢀparameters.ꢀTheꢀmostꢀimportantꢀresetꢀconditionꢀ

isꢀafterꢀpowerꢀisꢀﬁrstꢀappliedꢀtoꢀtheꢀmicrocontroller.ꢀInꢀthisꢀcase,ꢀinternalꢀcircuitryꢀwillꢀensureꢀthatꢀ

theꢀmicrocontroller,ꢀafterꢀaꢀshortꢀdelay,ꢀwillꢀbeꢀinꢀaꢀwell-deﬁnedꢀstateꢀandꢀreadyꢀtoꢀexecuteꢀtheꢀﬁrstꢀ

programꢀinstruction.ꢀAfterꢀthisꢀpower-onꢀreset,ꢀcertainꢀimportantꢀinternalꢀregistersꢀwillꢀbeꢀsetꢀtoꢀ

deﬁnedꢀstatesꢀbeforeꢀtheꢀprogramꢀcommences.ꢀOneꢀofꢀtheseꢀregistersꢀisꢀtheꢀProgramꢀCounter,ꢀwhichꢀ

willꢀbeꢀresetꢀtoꢀ“0”ꢀforcingꢀtheꢀmicrocontrollerꢀtoꢀbeginꢀprogramꢀexecutionꢀfromꢀtheꢀlowestꢀProgramꢀ

Memoryꢀaddress.ꢀ

AnotherꢀtypeꢀofꢀresetꢀisꢀwhenꢀtheꢀWatchdogꢀTimerꢀoverﬂowsꢀandꢀresets.ꢀAllꢀtypesꢀofꢀresetꢀoperationsꢀ

resultꢀinꢀdifferentꢀregisterꢀconditionsꢀbeingꢀsetup.ꢀAnotherꢀresetꢀexistsꢀinꢀtheꢀformꢀofꢀaꢀLowꢀVoltageꢀ

Reset,ꢀLVR,ꢀwhereꢀaꢀfullꢀreset,ꢀisꢀimplementedꢀinꢀsituationsꢀwhereꢀtheꢀpowerꢀsupplyꢀvoltageꢀfallsꢀ

belowꢀaꢀcertainꢀthreshold.ꢀ

Reset Functions

Thereꢀareꢀseveralꢀwaysꢀinꢀwhichꢀaꢀmicrocontrollerꢀresetꢀcanꢀoccur,ꢀthroughꢀeventsꢀoccurringꢀ

internally.

Power-on Reset

Theꢀmostꢀfundamentalꢀandꢀunavoidableꢀresetꢀisꢀtheꢀoneꢀthatꢀoccursꢀafterꢀpowerꢀisꢀﬁrstꢀappliedꢀtoꢀ

theꢀmicrocontroller.ꢀAsꢀwellꢀasꢀensuringꢀthatꢀtheꢀProgramꢀMemoryꢀbeginsꢀexecutionꢀfromꢀtheꢀﬁrstꢀ

memoryꢀaddress,ꢀaꢀpower-onꢀresetꢀalsoꢀensuresꢀthatꢀcertainꢀotherꢀregistersꢀareꢀpresetꢀtoꢀknownꢀ

conditions.ꢀAllꢀtheꢀI/Oꢀportꢀandꢀportꢀcontrolꢀregistersꢀwillꢀpowerꢀupꢀinꢀaꢀhighꢀconditionꢀensuringꢀthatꢀ

allꢀI/Oꢀportsꢀwillꢀbeꢀﬁrstꢀsetꢀtoꢀinputs.

VDD

Poweꢁ-on Reset

t_RSTD

SST Time-oꢀt

Power-On Reset Timing Chart

Rev. 1.10

67

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Internal Reset Control

Thereꢀisꢀanꢀinternalꢀresetꢀcontrolꢀregister,ꢀRSTC,ꢀwhichꢀisꢀusedꢀtoꢀprovideꢀaꢀresetꢀwhenꢀtheꢀdeviceꢀ

operatesꢀabnormallyꢀdueꢀtoꢀtheꢀenvironmentalꢀnoiseꢀinterference.ꢀIfꢀtheꢀcontentꢀofꢀtheꢀRSTCꢀregisterꢀ

isꢀsetꢀtoꢀanyꢀvalueꢀotherꢀthanꢀ01010101Bꢀorꢀ10101010B,ꢀitꢀwillꢀresetꢀtheꢀdeviceꢀafterꢀaꢀdelayꢀtime,ꢀ

t_SRESET.ꢀAfterꢀpowerꢀonꢀtheꢀregisterꢀwillꢀhaveꢀaꢀvalueꢀofꢀ01010101B.

RSTC7~RSTC0 Bits

01010101B

Reset Function

No opeꢁation

Reset MCU

10101010B

Anꢂ otheꢁ valꢀe

Internal Reset Function Control

• RSTC Register

Bit

Name

R/W

7

6

RSTC6

R/W

1

5

RSTC5

R/W

0

4

RSTCꢃ

R/W

1

3

RSTC3

R/W

0

2

RSTCꢅ

R/W

1

RSTC1

R/W

0

RSTC0

R/W

1

RSTC7

R/W

0

POR

Bitꢀ7~0

RSTC7~RSTC0:ꢀResetꢀFunctionꢀControl

01010101:ꢀNoꢀoperation

10101010:ꢀNoꢀoperation

Otherꢀvalues:ꢀResetꢀMCU

Ifꢀtheseꢀbitsꢀareꢀchangedꢀdueꢀtoꢀadverseꢀenvironmentalꢀconditions,ꢀtheꢀmicrocontrollerꢀ

willꢀbeꢀreset.ꢀTheꢀresetꢀoperationꢀwillꢀbeꢀactivatedꢀafterꢀaꢀdelayꢀtime,ꢀt_SRESETꢀandꢀtheꢀ

RSTFꢀbitꢀinꢀtheꢀRSTFCꢀregisterꢀwillꢀbeꢀsetꢀtoꢀ“1”.

• RSTFC Register

Bit

Name

R/W

7

6

5

4

3

RSTF

R/W

0

2

LVRF

R/W

x

1

0

WRF

—

LRF

R/W

0

R/W

POR

0

“x” ꢀnknown

Bitꢀ7~4ꢀ

Bitꢀ3

Unimplemented,ꢀreadꢀasꢀ“0”

RSTF:ꢀResetꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag

0:ꢀNotꢀoccurred

1:ꢀOccurred

Thisꢀbitꢀisꢀsetꢀtoꢀ“1”ꢀbyꢀtheꢀRSTCꢀcontrolꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ

applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ“0”ꢀbyꢀtheꢀapplicationꢀ

program.

Bitꢀ2

Bitꢀ1

Bitꢀ0

LVRF:ꢀLVRꢀFunctionꢀResetꢀFlag

Describedꢀelsewhere.

LRF:ꢀLVRꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag

Describedꢀelsewhere.

WRF:ꢀWDTꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag

Describedꢀelsewhere.

Rev. 1.10

6ꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

In Application Programing Reset

TheꢀdevicesꢀcontainꢀtheꢀIAPꢀfunction.ꢀSoꢀthereꢀexistsꢀanꢀIAPꢀreset,ꢀwhichꢀisꢀcausedꢀbyꢀwritingꢀdataꢀ

55HꢀtoꢀFC1ꢀregister.

Low Voltage Reset – LVR

Theꢀmicrocontrollersꢀcontainꢀaꢀlowꢀvoltageꢀresetꢀcircuitꢀinꢀorderꢀtoꢀmonitorꢀtheꢀsupplyꢀvoltageꢀofꢀtheꢀ

device.ꢀTheꢀLVRꢀfunctionꢀisꢀalwaysꢀenabledꢀwithꢀaꢀspeciﬁcꢀLVRꢀvoltageꢀV_LVR.ꢀIfꢀtheꢀsupplyꢀvoltageꢀ

ofꢀtheꢀdeviceꢀdropsꢀtoꢀwithinꢀaꢀrangeꢀofꢀ0.9V~V_LVRꢀsuchꢀasꢀmightꢀoccurꢀwhenꢀchangingꢀtheꢀbattery,ꢀ

theꢀLVRꢀwillꢀautomaticallyꢀresetꢀtheꢀdeviceꢀinternallyꢀandꢀtheꢀLVRFꢀbitꢀinꢀtheꢀRSTFCꢀregisterꢀwillꢀ

alsoꢀbeꢀsetꢀhigh.ꢀForꢀaꢀvalidꢀLVRꢀsignal,ꢀaꢀlowꢀsupplyꢀvoltage,ꢀi.e.,ꢀaꢀvoltageꢀinꢀtheꢀrangeꢀbetweenꢀ

0.9V~V_LVRꢀmustꢀexistꢀforꢀaꢀtimeꢀgreaterꢀthanꢀthatꢀspeciﬁedꢀbyꢀt_LVRꢀinꢀtheꢀLVD/LVRꢀcharacteristics.ꢀIfꢀ

theꢀlowꢀsupplyꢀvoltageꢀstateꢀdoesꢀnotꢀexceedꢀthisꢀvalue,ꢀtheꢀLVRꢀwillꢀignoreꢀtheꢀlowꢀsupplyꢀvoltageꢀ

andꢀwillꢀnotꢀperformꢀaꢀresetꢀfunction.ꢀTheꢀactualꢀV_LVRꢀvalueꢀcanꢀbeꢀselectedꢀbyꢀtheꢀLVS7~LVS0ꢀ

bitsꢀinꢀtheꢀLVRCꢀregister.ꢀIfꢀtheꢀLVS7~LVS0ꢀbitsꢀareꢀchangedꢀtoꢀsomeꢀcertainꢀvaluesꢀbyꢀtheꢀ

environmentalꢀnoiseꢀorꢀsoftwareꢀsetting,ꢀtheꢀLVRꢀwillꢀresetꢀtheꢀdeviceꢀafterꢀaꢀdelayꢀtime,ꢀt_SRESET.ꢀ

Whenꢀthisꢀhappens,ꢀtheꢀLRFꢀbitꢀinꢀtheꢀRSTFCꢀregisterꢀwillꢀbeꢀsetꢀhigh.ꢀAfterꢀpowerꢀonꢀtheꢀregisterꢀ

willꢀhaveꢀtheꢀvalueꢀofꢀ01010101B.ꢀNoteꢀthatꢀtheꢀLVRꢀfunctionꢀwillꢀbeꢀautomaticallyꢀdisabledꢀwhenꢀ

theꢀdeviceꢀentersꢀtheꢀpowerꢀdownꢀmode.

LVR

t_RSTD+ t_SST

Inteꢁnal Reset

Low Voltage Reset Timing Chart

• LVRC Register

Bit

Name

R/W

7

LVS7

R/W

0

6

LVS6

R/W

1

5

LVS5

R/W

0

4

LVSꢃ

R/W

1

3

LVS3

R/W

0

2

LVSꢅ

R/W

1

LVS1

R/W

0

LVS0

R/W

1

POR

Bitꢀ7~0ꢀ

LVS7~LVS0:ꢀLVRꢀVoltageꢀSelect

01010101:ꢀ2.1V

00110011:ꢀ2.55V

10011001:ꢀ3.15V

10101010:ꢀ3.8V

Otherꢀvalues:ꢀMCUꢀresetꢀ(registerꢀisꢀresetꢀtoꢀPORꢀvalue)

Whenꢀanꢀactualꢀlowꢀvoltageꢀconditionꢀoccurs,ꢀasꢀspeciﬁedꢀbyꢀoneꢀofꢀtheꢀfourꢀdeﬁnedꢀ

LVRꢀvoltageꢀvaluesꢀabove,ꢀanꢀMCUꢀresetꢀwillꢀbeꢀgenerated.ꢀTheꢀresetꢀoperationꢀ

willꢀbeꢀactivatedꢀafterꢀtheꢀlowꢀvoltageꢀconditionꢀkeepsꢀmoreꢀthanꢀaꢀt_LVRꢀtime.ꢀInꢀthisꢀ

situationꢀtheꢀregisterꢀcontentsꢀwillꢀremainꢀtheꢀsameꢀafterꢀsuchꢀaꢀresetꢀoccurs.

Anyꢀregisterꢀvalue,ꢀotherꢀthanꢀtheꢀfourꢀdeﬁnedꢀLVRꢀvaluesꢀabove,ꢀwillꢀalsoꢀresultꢀinꢀ

theꢀgenerationꢀofꢀanꢀMCUꢀreset.ꢀTheꢀresetꢀoperationꢀwillꢀbeꢀactivatedꢀafterꢀꢀaꢀdelayꢀ

time,ꢀt_SRESET.ꢀHoweverꢀinꢀthisꢀsituationꢀtheꢀregisterꢀcontentsꢀwillꢀbeꢀresetꢀtoꢀtheꢀPORꢀ

value.

Rev. 1.10

69

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

• RSTFC Register

Bit

Name

R/W

7

6

5

4

3

RSTF

R/W

0

2

LVRF

R/W

x

1

0

WRF

—

LRF

R/W

0

R/W

POR

0

“x” ꢀnknown

Bitꢀ7~4ꢀ

Bitꢀ3ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

RSTF:ꢀResetꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag

Describedꢀelsewhere.

Bitꢀ2

LVRF:ꢀLVRꢀFunctionꢀResetꢀFlag

0:ꢀNotꢀoccur

1:ꢀOccurred

ThisꢀbitꢀisꢀsetꢀhighꢀwhenꢀaꢀspeciﬁcꢀLowꢀVoltageꢀResetꢀsituationꢀconditionꢀoccurs.ꢀThisꢀ

bitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ“0”ꢀbyꢀtheꢀapplicationꢀprogram.

Bitꢀ1

LRF:ꢀLVRꢀControlꢀRegisterꢀSoftwareꢀResetꢀFlag

0:ꢀNotꢀoccur

1:ꢀOccurred

ThisꢀbitꢀisꢀsetꢀhighꢀifꢀtheꢀLVRCꢀregisterꢀcontainsꢀanyꢀnon-deﬁnedꢀLVRꢀvoltageꢀregisterꢀ

values.ꢀThisꢀinꢀeffectꢀactsꢀlikeꢀaꢀsoftware-resetꢀfunction.ꢀThisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ

“0”ꢀbyꢀtheꢀapplicationꢀprogram.

Bitꢀ0

WRF:ꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀﬂag

Describedꢀelsewhere.

Watchdog Time-out Reset during Normal Operation

TheꢀWatchdogꢀtime-outꢀResetꢀduringꢀnormalꢀoperationꢀisꢀtheꢀsameꢀasꢀLVRꢀresetꢀexceptꢀthatꢀtheꢀ

Watchdogꢀtime-outꢀﬂagꢀTOꢀwillꢀbeꢀsetꢀhigh.

WDT Time-oꢀt

t_RSTD+ t_SST

Inteꢁnal Reset

WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE Mode

TheꢀWatchdogꢀtime-outꢀResetꢀduringꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀaꢀlittleꢀdifferentꢀfromꢀotherꢀkindsꢀ

ofꢀreset.ꢀMostꢀofꢀtheꢀconditionsꢀremainꢀunchangedꢀexceptꢀthatꢀtheꢀProgramꢀCounterꢀandꢀtheꢀStackꢀ

Pointerꢀwillꢀbeꢀclearedꢀtoꢀ“0”ꢀandꢀtheꢀTOꢀﬂagꢀwillꢀbeꢀsetꢀhigh.ꢀReferꢀtoꢀtheꢀSystemꢀStartꢀUpꢀTimeꢀ

Characteristicsꢀforꢀt_SSTꢀdetails.

WDT Time-oꢀt

t_SST

Inteꢁnal Reset

WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart

Rev. 1.10

70

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Reset Initial Conditions

Theꢀdifferentꢀtypesꢀofꢀresetꢀdescribedꢀaffectꢀtheꢀresetꢀﬂagsꢀinꢀdifferentꢀways.ꢀTheseꢀﬂags,ꢀknownꢀ

asꢀPDFꢀandꢀTOꢀareꢀlocatedꢀinꢀtheꢀstatusꢀregisterꢀandꢀareꢀcontrolledꢀbyꢀvariousꢀmicrocontrollerꢀ

operations,ꢀsuchꢀasꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀfunctionꢀorꢀWatchdogꢀTimer.ꢀTheꢀresetꢀflagsꢀareꢀ

shownꢀinꢀtheꢀtable:

TO

0

PDF

Reset Conditions

0

ꢀ

1

Poweꢁ-on ꢁeset

ꢀ

LVR ꢁeset dꢀꢁing FAST oꢁ SLOW Mode opeꢁation

1

WDT time-oꢀt ꢁeset dꢀꢁing FAST oꢁ SLOW Mode opeꢁation

WDT time-oꢀt ꢁeset dꢀꢁing IDLE oꢁ SLEEP Mode opeꢁation

1

“ꢀ” stands foꢁ ꢀnchanged

Theꢀfollowingꢀtableꢀindicatesꢀtheꢀwayꢀinꢀwhichꢀtheꢀvariousꢀcomponentsꢀofꢀtheꢀmicrocontrollerꢀareꢀ

affectedꢀafterꢀaꢀpower-onꢀresetꢀoccurs.ꢀ

Item

Pꢁogꢁam Coꢀnteꢁ

Inteꢁꢁꢀpts

Condition after Reset

Reset to zeꢁo

All inteꢁꢁꢀpts will be disabled

WDTꢄ Time Bases

Timeꢁ Modꢀles

Inpꢀt/Oꢀtpꢀt Poꢁts

Stack Pointeꢁ

Cleaꢁ afteꢁ ꢁesetꢄ WDT begins coꢀnting

Timeꢁ Modꢀles will be tꢀꢁned off

I/O poꢁts will be setꢀp as inpꢀts

Stack Pointeꢁ will point to the top of the stack

Theꢀdifferentꢀkindsꢀofꢀresetsꢀallꢀaffectꢀtheꢀinternalꢀregistersꢀofꢀtheꢀmicrocontrollerꢀinꢀdifferentꢀways.ꢀ

Toꢀensureꢀreliableꢀcontinuationꢀofꢀnormalꢀprogramꢀexecutionꢀafterꢀaꢀresetꢀoccurs,ꢀitꢀisꢀimportantꢀtoꢀ

knowꢀwhatꢀconditionꢀtheꢀmicrocontrollerꢀisꢀinꢀafterꢀaꢀparticularꢀresetꢀoccurs.ꢀTheꢀfollowingꢀtableꢀ

describesꢀhowꢀeachꢀtypeꢀofꢀresetꢀaffectsꢀeachꢀofꢀtheꢀmicrocontrollerꢀinternalꢀregisters.

Register

Name

Reset

(Power On)

LVR Reset

(Normal Operation) (Normal Operation)

WDT Time-out

(IDLE/SLEEP)

IAR0

●

—

●

—

●

—

●

0000 0000

x x x x x x x x

0000 0000

x x x x x x x x

- - - x x x x x

- - x x x x x x

x x 0 0 x x x x

- - - - - - - 0

0000 0000

- - - - 0 x 0 0

0 0 0 - 0 0 0 0

- - - - 0 0 0 1

0000 0000

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

0000 0000

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - ꢀ ꢀ ꢀ ꢀ ꢀ

- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - - 0

0000 0000

- - - - ꢀ 1 ꢀ ꢀ

0 0 0 - 0 0 0 0

- - - - 0 0 0 1

0000 0000

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

0000 0000

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - ꢀ ꢀ ꢀ ꢀ ꢀ

- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

x x 1 ꢀ ꢀ ꢀ ꢀ ꢀ

- - - - - - - 0

0000 0000

- - - - ꢀ ꢀ ꢀ ꢀ

0 0 0 - 0 0 0 0

- - - - 0 0 0 1

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

0000 0000

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - ꢀ ꢀ ꢀ ꢀ ꢀ

- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

ꢀ ꢀ 11 ꢀ ꢀ ꢀ ꢀ

- - - - - - - ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - ꢀ ꢀ ꢀ ꢀ

ꢀ ꢀ ꢀ - ꢀ ꢀ ꢀ ꢀ

- - - - ꢀ ꢀ ꢀ ꢀ

MP0

IAR1

MP1L

MP1H

ACC

PCL

TBLP

TBLH

TBHP

STATUS

PBP

IARꢅ

MPꢅL

MPꢅH

RSTFC

SCC

HIRCC

Rev. 1.10

71

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Register

Name

Reset

(Power On)

LVR Reset

(Normal Operation) (Normal Operation)

WDT Time-out

(IDLE/SLEEP)

HXTC

●

—

●

—

●

- - - - - 0 0 0

- - - - - - 0 0

1111 1111

0000 0000

0101 0101

- - 0 0 0 0 0 0

0000 0000

- - 0 0 - - 0 0

0 1 0 1 0 0 11

- - - - 0 0 0 0

- 0 0 0 0 0 0 0

- 0 0 0 - 0 0 0

0000 0000

- - - 0 - - - 0

1111 1111

0000 0000

1111 1111

0000 0000

- - - - - - 0 0

0 - - - - 0 0 0

0 0 0 0 1 0 11

0000 00x0

0000 0000

x x x x x x x x

111 - 0 0 0 0

1000 0001

x x x x x x x x

0000 0000

1 1 1 - - - 0 0

- - 0 0 0 0 0 0

x x x x x x x x

- - 0 0 0 0 0 0

0000 0000

0 0 0 0 0 - - -

0000 0000

- - - - - 0 0 0

- - - - - - 0 0

1111 1111

0000 0000

0101 0101

- - 0 0 0 0 0 0

0000 0000

- - 0 0 - - 0 0

0 1 0 1 0 0 11

- - - - 0 0 0 0

- 0 0 0 0 0 0 0

- 0 0 0 - 0 0 0

0000 0000

- - - 0 - - - 0

1111 1111

0000 0000

1111 1111

0000 0000

- - - - - - 0 0

0 - - - - 0 0 0

0 0 0 0 1 0 11

0000 00x0

0000 0000

x x x x x x x x

111 - 0 0 0 0

1000 0001

x x x x x x x x

0000 0000

1 1 1 - - - 0 0

- - 0 0 0 0 0 0

x x x x x x x x

- - 0 0 0 0 0 0

0000 0000

0 0 0 0 0 - - -

0000 0000

- - - - - 0 0 0

- - - - - - 0 0

1111 1111

0000 0000

0101 0101

- - 0 0 0 0 0 0

0000 0000

- - 0 0 - - 0 0

0 1 0 1 0 0 11

- - - - 0 0 0 0

- 0 0 0 0 0 0 0

- 0 0 0 - 0 0 0

0000 0000

- - - 0 - - - 0

1111 1111

0000 0000

1111 1111

0000 0000

- - - - - - 0 0

0 - - - - 0 0 0

0 0 0 0 1 0 11

0000 00x0

0000 0000

x x x x x x x x

111 - 0 0 0 0

1000 0001

x x x x x x x x

0000 0000

1 1 1 - - - 0 0

- - 0 0 0 0 0 0

x x x x x x x x

- - 0 0 0 0 0 0

0000 0000

0 0 0 0 0 - - -

0000 0000

- - - - - ꢀ ꢀ ꢀ

- - - - - - ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - ꢀ ꢀ - - ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - ꢀ ꢀ ꢀ ꢀ

- ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

- ꢀ ꢀ ꢀ - ꢀ ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - ꢀ - - - ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - ꢀ ꢀ

ꢀ - - - - ꢀ ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

ꢀ ꢀ ꢀ - ꢀ ꢀ ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

ꢀ ꢀ ꢀ - - - ꢀ ꢀ

- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

ꢀ ꢀ ꢀ ꢀ ꢀ - - -

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

LXTC

PA

PAC

PAPU

PAWU

RSTC

LVRC

LVDC

MFI0

MFI1

MFIꢅ

WDTC

INTEG

INTC0

INTC1

INTCꢅ

INTC3

PB

PBC

PBPU

PC

PCC

PCPU

PSCR

TB0C

TB1C

USR

UCR1

UCRꢅ

TXR_RXR

BRG

SIMC0

SIMC1

SIMD

SIMA

SIMCꢅ

SIMTOC

SPIC0

SPIC1

SPID

EEA

EED

STMC0

STMC1

Rev. 1.10

7ꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Register

Name

Reset

(Power On)

LVR Reset

(Normal Operation) (Normal Operation)

WDT Time-out

(IDLE/SLEEP)

STMDL

●

0000 0000

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

x x x x x x x x

0 0 - - - - - -

- - - 0 0 0 0 0

0 0 1 0 0 0 - 0

0 0 0 0 0 0 0 -

0 - - - - 0 0 0

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 -

0000 0000

x x x x x x x x

0000 0000

- - - - 0 0 0 0

0 0 0 - - - - -

0 0 0 0 - - - -

- - 0 0 0 0 0 0

- - - 0 0 0 0 0

0 - - - 0 0 0 0

0000 0000

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 -

- - 0 0 0 0 0 0

0 - - 0 - - 0 0

- - - - 1 1 1 1

- - - - 0 0 0 0

0000 0000

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0 0 - - - - - -

- - - 0 0 0 0 0

0 0 1 0 0 0 - 0

0 0 0 0 0 0 0 -

0 - - - - 0 0 0

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 -

0000 0000

x x x x x x x x

0000 0000

- - - - 0 0 0 0

0 0 0 - - - - -

0 0 0 0 - - - -

- - 0 0 0 0 0 0

- - - 0 0 0 0 0

0 - - - 0 0 0 0

0000 0000

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 -

- - 0 0 0 0 0 0

0 - - 0 - - 0 0

- - - - 1 1 1 1

- - - - 0 0 0 0

0000 0000

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

0 0 - - - - - -

- - - 0 0 0 0 0

0 0 1 0 0 0 - 0

0 0 0 0 0 0 0 -

0 - - - - 0 0 0

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 -

0000 0000

x x x x x x x x

0000 0000

- - - - 0 0 0 0

0 0 0 - - - - -

0 0 0 0 - - - -

- - 0 0 0 0 0 0

- - - 0 0 0 0 0

0 - - - 0 0 0 0

0000 0000

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 -

- - 0 0 0 0 0 0

0 - - 0 - - 0 0

- - - - 1 1 1 1

- - - - 0 0 0 0

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

ꢀ ꢀ ꢀ ꢀ ꢀ - - -

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

ꢀ ꢀ - - - - - -

- - - ꢀ ꢀ ꢀ ꢀ ꢀ

ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ - ꢀ

ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ -

ꢀ - - - - ꢀ ꢀ ꢀ

- ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

- ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ -

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - ꢀ ꢀ ꢀ ꢀ

ꢀ ꢀ ꢀ - - - - -

ꢀ ꢀ ꢀ ꢀ - - - -

- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

- - - ꢀ ꢀ ꢀ ꢀ ꢀ

ꢀ - - - ꢀ ꢀ ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

- ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ -

- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

ꢀ - - ꢀ - - ꢀ ꢀ

- - - - ꢀ ꢀ ꢀ ꢀ

STMDH

STMAL

STMAH

STMRP

PTM0C0

PTM0C1

PTM0DL

PTM0DH

PTM0AL

PTM0AH

PTM0RPL

PTM0RPH

MDUWR0

MDUWR1

MDUWRꢅ

MDUWR3

MDUWRꢃ

MDUWR5

MDUWCTRL

ADCS

ADCR0

ADCR1

PWRC

PGAC0

PGAC1

PGACS

ADRL

ADRM

ADRH

DSDAH

DSDAL

DSDACC

SGC

SGN

SGDNR

OPAC

SWC0

SWC1

SWCꢅ

DACO

FTRC

PD

PDC

PDPU

Rev. 1.10

73

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Register

Name

Reset

(Power On)

LVR Reset

(Normal Operation) (Normal Operation)

WDT Time-out

(IDLE/SLEEP)

PTM1C0

●

—

●

—

●

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

- - - - 0 0 0 0

0000 0000

- - - - - - - 0

0000 0000

- - - 0 0 0 0 0

- - 0 0 0 0 0 0

0000 0000

0 0 - - 0 - - 0

- 0 0 0 - - 0 0

0000 0000

0 0 0 0 - - - -

- - 0 0 - - 0 0

- - - - 0 0 0 0

0000 0000

- - 0 0 0 0 0 0

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

- - - - 0 0 0 0

0000 0000

- - - - - - - 0

0000 0000

- - - 0 0 0 0 0

- - 0 0 0 0 0 0

0000 0000

0 0 - - 0 - - 0

- 0 0 0 - - 0 0

0000 0000

0 0 0 0 - - - -

- - 0 0 - - 0 0

- - - - 0 0 0 0

0000 0000

- - 0 0 0 0 0 0

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

- - - - 0 0 0 0

0000 0000

- - - - - - - 0

0000 0000

- - - 0 0 0 0 0

- - 0 0 0 0 0 0

0000 0000

0 0 - - 0 - - 0

- 0 0 0 - - 0 0

0000 0000

0 0 0 0 - - - -

- - 0 0 - - 0 0

- - - - 0 0 0 0

0000 0000

- - 0 0 0 0 0 0

ꢀ ꢀ ꢀ ꢀ ꢀ - - -

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - ꢀ ꢀ

ꢀ ꢀ ꢀ ꢀ ꢀ - - -

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - ꢀ ꢀ

- - - - ꢀ ꢀ ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - - - - - ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - - ꢀ ꢀ ꢀ ꢀ ꢀ

- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

ꢀ ꢀ - - ꢀ - - ꢀ

- ꢀ ꢀ ꢀ - - ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

ꢀ ꢀ ꢀ ꢀ - - - -

- - ꢀ ꢀ - - ꢀ ꢀ

- - - - ꢀ ꢀ ꢀ ꢀ

ꢀꢀꢀꢀ ꢀꢀꢀꢀ

- - ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

PTM1C1

PTM1DL

PTM1DH

PTM1AL

PTM1AH

PTM1RPL

PTM1RPH

PTMꢅC0

PTMꢅC1

PTMꢅDL

PTMꢅDH

PTMꢅAL

PTMꢅAH

PTMꢅRPL

PTMꢅRPH

EEC

FC0

FC1

FCꢅ

FARL

FARH

FD0L

FD0H

FD1L

FD1H

FDꢅL

FDꢅH

FD3L

FD3H

IFS0

IFS1

PAS0

PAS1

PBS0

PDS0

PCS0

PCS1

SLEDC0

SLEDC1

Note:ꢀ“u”ꢀstandsꢀforꢀunchanged

“x”ꢀstandsꢀforꢀunknown

“-”ꢀstandsꢀforꢀunimplemented

Rev. 1.10

7ꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Input/Output Ports

TheꢀmicrocontrollersꢀofferꢀconsiderableꢀflexibilityꢀonꢀtheirꢀI/Oꢀports.ꢀWithꢀtheꢀinputꢀorꢀoutputꢀ

designationꢀofꢀeveryꢀpinꢀfullyꢀunderꢀuserꢀprogramꢀcontrol,ꢀpull-highꢀselectionsꢀforꢀallꢀportsꢀandꢀ

wake-upꢀselectionsꢀonꢀcertainꢀpins,ꢀtheꢀuserꢀisꢀprovidedꢀwithꢀanꢀI/Oꢀstructureꢀtoꢀmeetꢀtheꢀneedsꢀofꢀaꢀ

wideꢀrangeꢀofꢀapplicationꢀpossibilities.ꢀ

Theseꢀdevicesꢀprovideꢀbidirectionalꢀinput/outputꢀlinesꢀlabeledꢀwithꢀportꢀnamesꢀPA~PD.ꢀTheseꢀI/Oꢀ

portsꢀareꢀmappedꢀtoꢀtheꢀRAMꢀDataꢀMemoryꢀwithꢀspeciﬁcꢀaddressesꢀasꢀshownꢀinꢀtheꢀSpecialꢀPurposeꢀ

DataꢀMemoryꢀtable.ꢀAllꢀofꢀtheseꢀI/Oꢀportsꢀcanꢀbeꢀusedꢀforꢀinputꢀandꢀoutputꢀoperations.ꢀForꢀinputꢀ

operation,ꢀtheseꢀportsꢀareꢀnon-latching,ꢀwhichꢀmeansꢀtheꢀinputsꢀmustꢀbeꢀreadyꢀatꢀtheꢀT2ꢀrisingꢀedgeꢀ

ofꢀinstructionꢀ“MOVꢀA,ꢀ[m]”,ꢀwhereꢀmꢀdenotesꢀtheꢀportꢀaddress.ꢀForꢀoutputꢀoperation,ꢀallꢀtheꢀdataꢀisꢀ

latchedꢀandꢀremainsꢀunchangedꢀuntilꢀtheꢀoutputꢀlatchꢀisꢀrewritten.

Bit

Register

Name

7

6

5

4

3

2

1

0

PA

PA7

PA6

PA5

PAꢃ

PA3

PAꢅ

PA1

PA0

PAC

PAC7

PAPU7

PAWU7

PB7

PAC5

PAPUꢃ

PAWU6

PB6

PAC5

PAPU5

PAWU5

PB5

PACꢃ

PAPUꢃ

PAWUꢃ

PBꢃ

PAC3

PAPU3

PAWU3

PB3

PACꢅ

PAPUꢅ

PAWUꢅ

PBꢅ

PAC1

PAPU1

PAWU1

PB1

PAC0

PAPU0

PAWU0

PB0

PAPU

PAWU

PB

PBC

PBPU

PC

PBC7

PBPU7

PC7

PBC6

PBPU6

PC6

PBC5

PBPU5

PC5

PBCꢃ

PBPUꢃ

PCꢃ

PBC3

PBPU3

PC3

PBCꢅ

PBPUꢅ

PCꢅ

PBC1

PBPU1

PC1

PBC0

PBPU0

PC0

PCC

PCPU

PD

PCC7

PCPU7

—

PCC6

PCPU6

—

PCC5

PCPU5

—

PCCꢃ

PCPUꢃ

—

PCC3

PCPU3

PD3

PCCꢅ

PCPUꢅ

PDꢅ

PCC1

PCPU1

PD1

PCC0

PCPU0

PD0

PDC

PDPU

—

PDC3

PDPU3

PDCꢅ

PDPUꢅ

PDC1

PDPU1

PDC0

PDPU0

—

“—” ꢀnimplemented

I/O Logic Function Registers List

Pull-high Resistors

Manyꢀproductꢀapplicationsꢀrequireꢀpull-highꢀresistorsꢀforꢀtheirꢀswitchꢀinputsꢀusuallyꢀrequiringꢀtheꢀ

useꢀofꢀanꢀexternalꢀresistor.ꢀToꢀeliminateꢀtheꢀneedꢀforꢀtheseꢀexternalꢀresistors,ꢀallꢀI/Oꢀpins,ꢀwhenꢀ

conﬁguredꢀasꢀanꢀinputꢀhaveꢀtheꢀcapabilityꢀofꢀbeingꢀconnectedꢀtoꢀanꢀinternalꢀpull-highꢀresistor.ꢀTheseꢀ

pull-highꢀresistorsꢀareꢀselectedꢀusingꢀregistersꢀPAPU~PDPU,ꢀandꢀareꢀimplementedꢀusingꢀweakꢀ

PMOSꢀtransistors.

Noteꢀthatꢀtheꢀpull-highꢀresistorꢀcanꢀbeꢀcontrolledꢀbyꢀtheꢀrelevantꢀpull-highꢀcontrolꢀregisterꢀonlyꢀwhenꢀ

theꢀpin-sharedꢀfunctionalꢀpinꢀisꢀselectedꢀasꢀaꢀdigitalꢀinputꢀorꢀNMOSꢀoutput.ꢀOtherwise,ꢀtheꢀpull-highꢀ

resistorsꢀcannotꢀbeꢀenabled.

PxPU Register

Bit

7

PxPU7

R/W

0

6

PxPUꢃ

R/W

0

5

PxPU5

R/W

0

4

PxPUꢃ

R/W

0

3

PxPU3

R/W

0

2

PxPUꢅ

R/W

0

1

PxPU1

R/W

0

PxPU0

R/W

0

Name

R/W

POR

PxPUn: I/OꢀPortꢀxꢀPinꢀPull-highꢀFunctionꢀControl

0:ꢀDisable

1:ꢀEnable

TheꢀPxPUnꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀpinꢀpull-highꢀfunction.ꢀHereꢀtheꢀ“x”ꢀcanꢀbeꢀA,ꢀB,ꢀCꢀandꢀ

D.ꢀHowever,ꢀtheꢀactualꢀavailableꢀbitsꢀforꢀeachꢀI/Oꢀportꢀmayꢀbeꢀdifferent.

Rev. 1.10

75

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Port A Wake-up

TheꢀHALTꢀinstructionꢀforcesꢀtheꢀmicrocontrollerꢀintoꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀwhichꢀpreservesꢀ

power,ꢀaꢀfeatureꢀthatꢀisꢀimportantꢀforꢀbatteryꢀandꢀotherꢀlow-powerꢀapplications.ꢀVariousꢀmethodsꢀ

existꢀtoꢀwake-upꢀtheꢀmicrocontroller,ꢀoneꢀofꢀwhichꢀisꢀtoꢀchangeꢀtheꢀlogicꢀconditionꢀonꢀoneꢀofꢀtheꢀPortꢀ

Aꢀpinsꢀfromꢀhighꢀtoꢀlow.ꢀThisꢀfunctionꢀisꢀespeciallyꢀsuitableꢀforꢀapplicationsꢀthatꢀcanꢀbeꢀwokenꢀupꢀ

viaꢀexternalꢀswitches.ꢀEachꢀpinꢀonꢀPortꢀAꢀcanꢀbeꢀselectedꢀindividuallyꢀtoꢀhaveꢀthisꢀwake-upꢀfeatureꢀ

usingꢀtheꢀPAWUꢀregister.

Noteꢀthatꢀtheꢀwake-upꢀfunctionꢀcanꢀbeꢀcontrolledꢀbyꢀtheꢀwake-upꢀcontrolꢀregistersꢀonlyꢀwhenꢀtheꢀ

pin-sharedꢀfunctionalꢀpinꢀisꢀselectedꢀasꢀgeneralꢀpurposeꢀinput/outputꢀandꢀtheꢀMCUꢀentersꢀtheꢀPowerꢀ

downꢀmode.

PAWU Register

Bit

7

PAWU7

R/W

0

6

PAWU6

R/W

0

5

PAWU5

R/W

0

4

PAWUꢃ

R/W

0

3

PAWU3

R/W

0

2

PAWUꢅ

R/W

0

1

PAWU1

R/W

0

PAWU0

R/W

0

Name

R/W

POR

PAWUn:ꢀPortꢀAꢀPinꢀWake-upꢀControl

0:ꢀDisable

1:ꢀEnable

I/O Port Control Registers

EachꢀI/OꢀportꢀhasꢀitsꢀownꢀcontrolꢀregisterꢀknownꢀasꢀPAC~PDC,ꢀtoꢀcontrolꢀtheꢀinput/outputꢀ

configuration.ꢀWithꢀthisꢀcontrolꢀregister,ꢀeachꢀCMOSꢀoutputꢀorꢀinputꢀcanꢀbeꢀreconfiguredꢀ

dynamicallyꢀunderꢀsoftwareꢀcontrol.ꢀEachꢀpinꢀofꢀtheꢀI/Oꢀportsꢀisꢀdirectlyꢀmappedꢀtoꢀaꢀbitꢀinꢀitsꢀ

associatedꢀportꢀcontrolꢀregister.ꢀForꢀtheꢀI/Oꢀpinꢀtoꢀfunctionꢀasꢀanꢀinput,ꢀtheꢀcorrespondingꢀbitꢀofꢀtheꢀ

controlꢀregisterꢀmustꢀbeꢀwrittenꢀasꢀaꢀ“1”.ꢀThisꢀwillꢀthenꢀallowꢀtheꢀlogicꢀstateꢀofꢀtheꢀinputꢀpinꢀtoꢀbeꢀ

directlyꢀreadꢀbyꢀinstructions.ꢀWhenꢀtheꢀcorrespondingꢀbitꢀofꢀtheꢀcontrolꢀregisterꢀisꢀwrittenꢀasꢀaꢀ“0”,ꢀ

theꢀI/OꢀpinꢀwillꢀbeꢀsetupꢀasꢀaꢀCMOSꢀoutput.ꢀIfꢀtheꢀpinꢀisꢀcurrentlyꢀsetupꢀasꢀanꢀoutput,ꢀinstructionsꢀ

canꢀstillꢀbeꢀusedꢀtoꢀreadꢀtheꢀoutputꢀregister.ꢀHowever,ꢀitꢀshouldꢀbeꢀnotedꢀthatꢀtheꢀprogramꢀwillꢀinꢀfactꢀ

onlyꢀreadꢀtheꢀstatusꢀofꢀtheꢀoutputꢀdataꢀlatchꢀandꢀnotꢀtheꢀactualꢀlogicꢀstatusꢀofꢀtheꢀoutputꢀpin.

PxC Register

Bit

7

PxC7

R/W

1

6

PxC5

R/W

1

5

PxC5

R/W

1

4

PxCꢃ

R/W

1

3

PxC3

R/W

1

2

PxCꢅ

R/W

1

PxC1

R/W

1

0

PxC0

R/W

1

Name

R/W

POR

PxCn:ꢀI/OꢀPortꢀxꢀPinꢀTypeꢀSelection

0:ꢀOutput

1:ꢀInput

TheꢀPxCnꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀpinꢀtypeꢀselection.ꢀHereꢀtheꢀ“x”ꢀcanꢀbeꢀA,ꢀB,ꢀCꢀandꢀD.ꢀ

However,ꢀtheꢀactualꢀavailableꢀbitsꢀforꢀeachꢀI/Oꢀportꢀmayꢀbeꢀdifferent.

Rev. 1.10

76

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

I/O Port Source Current Control

TheꢀdevicesꢀsupportꢀdifferentꢀsourceꢀcurrentꢀdrivingꢀcapabilityꢀforꢀeachꢀI/Oꢀport.ꢀWithꢀtheꢀ

correspondingꢀselectionꢀregisters,ꢀSLEDC0ꢀandꢀSLEDC1,ꢀeachꢀI/Oꢀportꢀcanꢀsupportꢀfourꢀlevelsꢀofꢀ

theꢀsourceꢀcurrentꢀdrivingꢀcapability.ꢀUsersꢀshouldꢀreferꢀtoꢀtheꢀInput/OutputꢀCharacteristicsꢀsectionꢀ

toꢀselectꢀtheꢀdesiredꢀsourceꢀcurrentꢀforꢀdifferentꢀapplications.

SLEDC0 Register

Bit

7

6

5

4

3

2

1

0

Name SLEDC07 SLEDC06 SLEDC05 SLEDC0ꢃ SLEDC03 SLEDC0ꢅ SLEDC01 SLEDC00

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7~6

Bitꢀ5~4

Bitꢀ3~2

Bitꢀ1~0

SLEDC07~SLEDC06:ꢀPB7~PB4ꢀSourceꢀCurrentꢀSelection

00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)

01:ꢀSourceꢀcurrent=Levelꢀ1

10:ꢀSourceꢀcurrent=Levelꢀ2

11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)

SLEDC05~SLEDC04:ꢀPB3~PB0ꢀSourceꢀCurrentꢀSelection

00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)

01:ꢀSourceꢀcurrent=Levelꢀ1

10:ꢀSourceꢀcurrent=Levelꢀ2

11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)

SLEDC03~SLEDC02:ꢀPA7~PA4ꢀSourceꢀCurrentꢀSelection

00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)

01:ꢀSourceꢀcurrent=Levelꢀ1

10:ꢀSourceꢀcurrent=Levelꢀ2

11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)

SLEDC01~SLEDC00:ꢀPA3~PA0ꢀSourceꢀCurrentꢀSelection

00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)

01:ꢀSourceꢀcurrent=Levelꢀ1

10:ꢀSourceꢀcurrent=Levelꢀ2

11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)

SLEDC1 Register

Bit

Name

R/W

7

6

5

4

3

2

1

0

—

SLEDC15 SLEDC1ꢃ SLEDC13 SLEDC1ꢅ SLEDC11 SLEDC10

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7~6ꢀ

Bitꢀ5~4

Unimplemented,ꢀreadꢀasꢀ“0”

SLEDC15~SLEDC14:ꢀPD3~PD0ꢀSourceꢀCurrentꢀSelection

00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)

01:ꢀSourceꢀcurrent=Levelꢀ1

10:ꢀSourceꢀcurrent=Levelꢀ2

11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)

Bitꢀ3~2

Bitꢀ1~0

SLEDC13~SLEDC12:ꢀPC7~PC4ꢀSourceꢀCurrentꢀSelection

00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)

01:ꢀSourceꢀcurrent=Levelꢀ1

10:ꢀSourceꢀcurrent=Levelꢀ2

11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)

SLEDC11~SLEDC10:ꢀPC3~PC0ꢀSourceꢀCurrentꢀSelection

00:ꢀSourceꢀcurrent=Levelꢀ0ꢀ(min.)

01:ꢀSourceꢀcurrent=Levelꢀ1

10:ꢀSourceꢀcurrent=Levelꢀ2

11:ꢀSourceꢀcurrent=Levelꢀ3ꢀ(max.)

Rev. 1.10

77

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Pin-shared Functions

Theꢀﬂexibilityꢀofꢀtheꢀmicrocontrollerꢀrangeꢀisꢀgreatlyꢀenhancedꢀbyꢀtheꢀuseꢀofꢀpinsꢀthatꢀhaveꢀmoreꢀ

thanꢀoneꢀfunction.ꢀLimitedꢀnumbersꢀofꢀpinsꢀcanꢀforceꢀseriousꢀdesignꢀconstraintsꢀonꢀdesignersꢀbutꢀbyꢀ

supplyingꢀpinsꢀwithꢀmulti-functions,ꢀmanyꢀofꢀtheseꢀdifﬁcultiesꢀcanꢀbeꢀovercome.ꢀForꢀtheseꢀpins,ꢀtheꢀ

desiredꢀfunctionꢀofꢀtheꢀmulti-functionꢀI/Oꢀpinsꢀisꢀselectedꢀbyꢀaꢀseriesꢀofꢀregistersꢀviaꢀtheꢀapplicationꢀ

programꢀcontrol.

Pin-shared Function Selection Registers

Theꢀlimitedꢀnumberꢀofꢀsuppliedꢀpinsꢀinꢀaꢀpackageꢀcanꢀimposeꢀrestrictionsꢀonꢀtheꢀamountꢀofꢀfunctionsꢀ

aꢀcertainꢀdeviceꢀcanꢀcontain.ꢀHoweverꢀbyꢀallowingꢀtheꢀsameꢀpinsꢀtoꢀshareꢀseveralꢀdifferentꢀfunctionsꢀ

andꢀprovidingꢀaꢀmeansꢀofꢀfunctionꢀselection,ꢀaꢀwideꢀrangeꢀofꢀdifferentꢀfunctionsꢀcanꢀbeꢀincorporatedꢀ

intoꢀevenꢀrelativelyꢀsmallꢀpackageꢀsizes.ꢀTheꢀdevicesꢀincludeꢀPortꢀ“x”ꢀoutputꢀfunctionꢀSelectionꢀ

registerꢀ“n”,ꢀlabeledꢀasꢀPxSn,ꢀandꢀInputꢀFunctionꢀSelectionꢀregisterꢀ“n”,ꢀlabeledꢀasꢀIFSn,ꢀwhichꢀcanꢀ

selectꢀtheꢀdesiredꢀfunctionsꢀofꢀtheꢀmulti-functionꢀpin-sharedꢀpins.

Whenꢀtheꢀpin-sharedꢀinputꢀfunctionꢀisꢀselectedꢀtoꢀbeꢀused,ꢀtheꢀcorrespondingꢀinputꢀandꢀoutputꢀ

functionsꢀselectionꢀshouldꢀbeꢀproperlyꢀmanaged.ꢀForꢀexample,ꢀifꢀtheꢀI²CꢀSDAꢀlineꢀisꢀused,ꢀtheꢀ

correspondingꢀoutputꢀpin-sharedꢀfunctionꢀshouldꢀbeꢀconfiguredꢀasꢀtheꢀSDI/SDAꢀfunctionꢀbyꢀ

configuringꢀtheꢀPxSnꢀregisterꢀandꢀtheꢀSDAꢀsignalꢀintputꢀshouldꢀbeꢀproperlyꢀselectedꢀusingꢀtheꢀ

IFSnꢀregister.ꢀHowever,ꢀifꢀtheꢀexternalꢀinterruptꢀfunctionꢀisꢀselectedꢀtoꢀbeꢀused,ꢀtheꢀrelevantꢀoutputꢀ

pin-sharedꢀfunctionꢀshouldꢀbeꢀselectedꢀasꢀanꢀI/Oꢀfunctionꢀandꢀtheꢀinterruptꢀinputꢀsignalꢀshouldꢀbeꢀ

selected.

Theꢀmostꢀimportantꢀpointꢀtoꢀnoteꢀisꢀtoꢀmakeꢀsureꢀthatꢀtheꢀdesiredꢀpin-sharedꢀfunctionꢀisꢀproperlyꢀ

selectedꢀandꢀalsoꢀdeselected.ꢀForꢀmostꢀpin-sharedꢀfunctions,ꢀtoꢀselectꢀtheꢀdesiredꢀpin-sharedꢀfunction,ꢀ

theꢀpin-sharedꢀfunctionꢀshouldꢀﬁrstꢀbeꢀcorrectlyꢀselectedꢀusingꢀtheꢀcorrespondingꢀpin-sharedꢀcontrolꢀ

register.ꢀAfterꢀthatꢀtheꢀcorrespondingꢀperipheralꢀfunctionalꢀsettingꢀshouldꢀbeꢀconﬁguredꢀandꢀthenꢀtheꢀ

peripheralꢀfunctionꢀcanꢀbeꢀenabled.ꢀHowever,ꢀaꢀspecialꢀpointꢀmustꢀbeꢀnotedꢀforꢀsomeꢀdigitalꢀinputꢀ

pins,ꢀsuchꢀasꢀINTn,ꢀxTCKn,ꢀxTPnI,ꢀetc,ꢀwhichꢀshareꢀtheꢀsameꢀpin-sharedꢀcontrolꢀconﬁgurationꢀwithꢀ

theirꢀcorrespondingꢀgeneralꢀpurposeꢀI/Oꢀfunctionsꢀwhenꢀsettingꢀtheꢀrelevantꢀpin-sharedꢀcontrolꢀbitꢀ

ﬁelds.ꢀToꢀselectꢀtheseꢀpinꢀfunctions,ꢀinꢀadditionꢀtoꢀtheꢀnecessaryꢀpin-sharedꢀcontrolꢀandꢀperipheralꢀ

functionalꢀsetupꢀaforementioned,ꢀtheyꢀmustꢀalsoꢀbeꢀsetupꢀasꢀanꢀinputꢀbyꢀsettingꢀtheꢀcorrespondingꢀbitꢀ

inꢀtheꢀI/Oꢀportꢀcontrolꢀregister.ꢀToꢀcorrectlyꢀdeselectꢀtheꢀpin-sharedꢀfunction,ꢀtheꢀperipheralꢀfunctionꢀ

shouldꢀfirstꢀbeꢀdisabledꢀandꢀthenꢀtheꢀcorrespondingꢀpin-sharedꢀfunctionꢀcontrolꢀregisterꢀcanꢀbeꢀ

modiﬁedꢀtoꢀselectꢀotherꢀpin-sharedꢀfunctions.

Bit

Register

Name

7

6

5

4

3

PTCKꢅPS

—

2

1

—

0

IFS0

IFS1

PTPꢅIPS PTP1IPS

—

STCKPS

RXPS0

—

SCSAPS SDIAPS SCKAPS

RXPS1

PAS0

PAS1

PBS0

PCS0

PCS1

PDS0

PAS07

PAS17

PBS07

—

PAS06

PAS16

PBS06

—

PAS05

PAS15

PBS05

PCS05

—

PAS0ꢃ

PAS1ꢃ

PBS0ꢃ

PCS0ꢃ

—

PAS03

PAS13

PBS03

—

PAS0ꢅ

PAS1ꢅ

PBS0ꢅ

—

PAS01

PAS11

PBS01

PCS01

PCS11

—

PAS00

PAS10

PBS00

PCS00

PCS10

—

PCS13

—

PCS1ꢅ

—

PDS07

PDS06

PDS05

PDS0ꢃ

Pin-shared Function Selection Registers List

Rev. 1.10

7ꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

• PAS0 Register

Bit

Name

R/W

7

PAS07

R/W

0

6

PAS06

R/W

0

5

PAS05

R/W

0

4

PAS0ꢃ

R/W

0

3

PAS03

R/W

0

2

PAS0ꢅ

R/W

0

1

PAS01

R/W

0

PAS00

R/W

0

POR

Bitꢀ7~6ꢀ

Bitꢀ5~4

Bitꢀ3~2

Bitꢀ1~0

PAS07~PAS06:ꢀPA3ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPA3/PTP1I

01:ꢀPTP1

10:ꢀSDOA

11:ꢀOSC2

PAS05~PAS04:ꢀPA2ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPA2/PTCK0

01:ꢀPA2/PTCK0

10:ꢀPA2/PTCK0

11:ꢀXT2

PAS03~PAS02:ꢀPA1ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPA1/INT0/STCK

01:ꢀPA1/INT0/STCK

10:ꢀLVDIN

11:ꢀPTP0B

PAS01~PAS00:ꢀPA0ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPA0/PTP0I

01:ꢀPA0/PTP0I

10:ꢀPTP0

11:ꢀXT1

• PAS1 Register

Bit

Name

R/W

7

6

PAS16

R/W

0

5

PAS15

R/W

0

4

PAS1ꢃ

R/W

0

3

PAS13

R/W

0

2

PAS1ꢅ

R/W

0

1

PAS11

R/W

0

PAS10

R/W

0

PAS17

R/W

0

POR

Bitꢀ7~6ꢀ

Bitꢀ5~4

Bitꢀ3~2

Bitꢀ1~0

PAS17~PAS16:ꢀPA7ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPA7/PTCK2

01:ꢀPA7/PTCK2

10:ꢀPA7/PTCK2

11:ꢀSDI/SDA

PAS15~PAS14:ꢀPA6ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPA6/STCK

01:ꢀSDIA

10:ꢀPA6/STCK

11:ꢀRX

PAS13~PAS12:ꢀPA5ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPA5/STPI

01:ꢀSTP

10:ꢀSCKA

11:ꢀTX

PAS11~PAS10:ꢀPA4ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPA4/PTP2I

01:ꢀPTP2

10:ꢀSCSA

11:ꢀOSC1

Rev. 1.10

79

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

• PBS0 Register

Bit

Name

R/W

7

PBS07

R/W

0

6

PBS06

R/W

0

5

PBS05

R/W

0

4

PBS0ꢃ

R/W

0

3

PBS03

R/W

0

2

PBS0ꢅ

R/W

0

1

PBS01

R/W

0

PBS00

R/W

0

POR

Bitꢀ7~6ꢀ

Bitꢀ5~4

Bitꢀ3~2

Bitꢀ1~0

PBS07~PBS06:ꢀPB3ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPB3

01:ꢀRX

10:ꢀSDIA

11:ꢀSDO

PBS05~PBS04:ꢀPB2ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPB2

01:ꢀPB2

10:ꢀSCS

11:ꢀSCKA

PBS03~PBS02:ꢀPB1ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPB1/INT1

01:ꢀPB1/INT1

10:ꢀSTPB

11:ꢀPB1/INT1

PBS01~PBS00:ꢀPB0ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPB0

01:ꢀPB0

10:ꢀSCK/SCL

11:ꢀPB0

• PCS0 Register

Bit

Name

R/W

7

6

5

PCS05

R/W

0

4

PCS0ꢃ

R/W

0

3

2

1

PCS01

R/W

0

PCS00

R/W

0

—

POR

Bitꢀ7~6ꢀ

Bitꢀ5~4

Unimplemented,ꢀreadꢀasꢀ“0”

PCS05~PCS04:ꢀPC2ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPC2/PTP2I

01:ꢀPTP2

10:ꢀPC2/PTP2I

11:ꢀPC2/PTP2I

Bitꢀ3~2ꢀ

Bitꢀ1~0

Unimplemented,ꢀreadꢀasꢀ“0”

PCS01~PCS00:ꢀPC0ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPC0/PTP1I

01:ꢀPC0/PTP1I

10:ꢀPTP1

11:ꢀPC0/PTP1I

Rev. 1.10

ꢆ0

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

• PCS1 Register

Bit

Name

R/W

7

6

5

4

3

PCS13

R/W

0

2

PCS1ꢅ

R/W

0

1

PCS11

R/W

0

PCS10

R/W

0

—

POR

Bitꢀ7~4ꢀ

Bitꢀ3~2ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

PCS13~PCS12:ꢀPC5ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPC5

01:ꢀPC5

10:ꢀTX

11:ꢀSDOA

Bitꢀ1~0

PCS11~PCS10:ꢀPC4ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPC4

01:ꢀPC4

10:ꢀPC4

11:ꢀSCSA

• PDS0 Register

Bit

Name

R/W

7

PDS07

R/W

0

6

PDS06

R/W

0

5

PDS05

R/W

0

4

PDS0ꢃ

R/W

0

3

2

1

0

—

POR

Bitꢀ7~6ꢀ

PDS07~PDS06:ꢀPD3ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPD3

01:ꢀPD3

10:ꢀTX

11:ꢀPD3

Bitꢀ5~4

PDS05~PDS04:ꢀPD2ꢀPin-SharedꢀFunctionꢀSelection

00:ꢀPD2

01:ꢀPD2

10:ꢀRX

11:ꢀPD2

Bitꢀ3~0ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

• IFS0 Register

Bit

7

6

5

4

3

PTCKꢅPS

R/W

2

1

0

STCKPS

R/W

Name

R/W

PTPꢅIPS PTP1IPS

—

R/W

0

R/W

0

POR

0

Bitꢀ7ꢀ

PTP2IPS:ꢀPTP2IꢀInputꢀSourceꢀPinꢀSelectionꢀ

0:ꢀPTP2IꢀonꢀPA4ꢀ

1:ꢀPTP2IꢀonꢀPC2

Bitꢀ6

PTP1IPS:ꢀPTP1IꢀInputꢀSourceꢀPinꢀSelection

0:ꢀPTP1IꢀonꢀPA3

1:ꢀPTP1IꢀonꢀPC0

Bitꢀ5~4ꢀ

Bitꢀ3

Unimplemented,ꢀreadꢀasꢀ“0”

PTCK2PS:ꢀPTCK2ꢀInputꢀSourceꢀPinꢀSelection

0:ꢀPTCK2ꢀonꢀPC3

1:ꢀPTCK2ꢀonꢀPA7

Bitꢀ2~1ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

Rev. 1.10

ꢆ1

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Bitꢀ0

STCKPS:ꢀSTCKꢀInputꢀSourceꢀPinꢀSelection

0:ꢀSTCKꢀonꢀPA1

1:ꢀSTCKꢀonꢀPA6

• IFS1 Register

Bit

7

6

SCSAPS

R/W

5

SDIAPS

R/W

0

4

SCKAPS

R/W

3

2

1

RXPS1

R/W

0

RXPS0

R/W

0

Name

R/W

—

POR

0

Bitꢀ7ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

Bitꢀ6

Bitꢀ5

Bitꢀ4

SCSAPS:ꢀSCSAꢀInputꢀSourceꢀPinꢀSelection

0:ꢀSCSAꢀonꢀPA4

1:ꢀSCSAꢀonꢀPC4

SDIAPS:ꢀSDIAꢀInputꢀSourceꢀPinꢀSelection

0:ꢀSDIAꢀonꢀPA6ꢀ

1:ꢀSDIAꢀonꢀPB3

SCKAPS:ꢀSCKAꢀInputꢀSourceꢀPinꢀSelection

0:ꢀSCKAꢀonꢀPA5ꢀ

1:ꢀSCKAꢀonꢀPB2

Bitꢀ3~2ꢀ

Bitꢀ1~0

Unimplemented,ꢀreadꢀasꢀ“0”

RXPS1~RXPS0:ꢀRXꢀInputꢀSourceꢀPinꢀSelection

00:ꢀRXꢀonꢀPA6

01:ꢀRXꢀonꢀPB3

10:ꢀRXꢀonꢀPD2

11:ꢀRXꢀonꢀPD2

I/O Pin Structures

TheꢀaccompanyingꢀdiagramꢀillustratesꢀtheꢀinternalꢀstructuresꢀofꢀtheꢀI/Oꢀlogicꢀfunction.ꢀAsꢀtheꢀexactꢀ

logicalꢀconstructionꢀofꢀtheꢀI/Oꢀpinꢀwillꢀdifferꢀfromꢀthisꢀdiagram,ꢀitꢀisꢀsuppliedꢀasꢀaꢀguideꢀonlyꢀtoꢀ

assistꢀwithꢀtheꢀfunctionalꢀunderstandingꢀofꢀtheꢀlogicꢀfunctionꢀI/Oꢀpins.ꢀTheꢀwideꢀrangeꢀofꢀpin-sharedꢀ

structuresꢀdoesꢀnotꢀpermitꢀallꢀtypesꢀtoꢀbeꢀshown.

VDD

Pꢀll-high

Registeꢁ

Select

Weak

Pꢀll-ꢀp

Contꢁol Bit

Data Bꢀs

D

Q

Wꢁite Contꢁol Registeꢁ

Chip Reset

CK

Q

S

I/O pin

Read Contꢁol Registeꢁ

Data Bit

D

Q

Wꢁite Data Registeꢁ

CK

Q

S

M

U

X

Read Data Registeꢁ

Sꢂstem Wake-ꢀp

PA onlꢂ

wake-ꢀp Select

Logic Function Input/Output Structure

Rev. 1.10

ꢆꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Programming Considerations

Withinꢀtheꢀuserꢀprogram,ꢀoneꢀofꢀtheꢀthingsꢀﬁrstꢀtoꢀconsiderꢀisꢀportꢀinitialisation.ꢀAfterꢀaꢀreset,ꢀallꢀ

ofꢀtheꢀI/Oꢀdataꢀandꢀportꢀcontrolꢀregistersꢀwillꢀbeꢀsetꢀtoꢀhigh.ꢀThisꢀmeansꢀthatꢀallꢀI/Oꢀpinsꢀwillꢀbeꢀ

defaultedꢀtoꢀanꢀinputꢀstate,ꢀtheꢀlevelꢀofꢀwhichꢀdependsꢀonꢀtheꢀotherꢀconnectedꢀcircuitryꢀandꢀwhetherꢀ

pull-highꢀselectionsꢀhaveꢀbeenꢀchosen.ꢀIfꢀtheꢀportꢀcontrolꢀregistersꢀareꢀthenꢀprogrammedꢀtoꢀsetupꢀ

someꢀpinsꢀasꢀoutputs,ꢀtheseꢀoutputꢀpinsꢀwillꢀhaveꢀanꢀinitialꢀhighꢀoutputꢀvalueꢀunlessꢀtheꢀassociatedꢀ

portꢀdataꢀregistersꢀareꢀﬁrstꢀprogrammed.ꢀSelectingꢀwhichꢀpinsꢀareꢀinputsꢀandꢀwhichꢀareꢀoutputsꢀcanꢀ

beꢀachievedꢀbyte-wideꢀbyꢀloadingꢀtheꢀcorrectꢀvaluesꢀintoꢀtheꢀappropriateꢀportꢀcontrolꢀregisterꢀorꢀ

byꢀprogrammingꢀindividualꢀbitsꢀinꢀtheꢀportꢀcontrolꢀregisterꢀusingꢀtheꢀ“SETꢀ[m].i”ꢀandꢀ“CLRꢀ[m].i”ꢀ

instructions.ꢀNoteꢀthatꢀwhenꢀusingꢀtheseꢀbitꢀcontrolꢀinstructions,ꢀaꢀread-modify-writeꢀoperationꢀtakesꢀ

place.ꢀTheꢀmicrocontrollerꢀmustꢀﬁrstꢀreadꢀinꢀtheꢀdataꢀonꢀtheꢀentireꢀport,ꢀmodifyꢀitꢀtoꢀtheꢀrequiredꢀnewꢀ

bitꢀvaluesꢀandꢀthenꢀrewriteꢀthisꢀdataꢀbackꢀtoꢀtheꢀoutputꢀports.ꢀ

PortꢀAꢀhasꢀtheꢀadditionalꢀcapabilityꢀofꢀprovidingꢀwake-upꢀfunctions.ꢀWhenꢀtheꢀdeviceꢀisꢀinꢀtheꢀ

SLEEPꢀorꢀIDLEꢀMode,ꢀvariousꢀmethodsꢀareꢀavailableꢀtoꢀwakeꢀtheꢀdeviceꢀup.ꢀOneꢀofꢀtheseꢀisꢀaꢀhighꢀ

toꢀlowꢀtransitionꢀofꢀanyꢀofꢀtheꢀPortꢀAꢀpins.ꢀSingleꢀorꢀmultipleꢀpinsꢀonꢀPortꢀAꢀcanꢀbeꢀsetupꢀtoꢀhaveꢀthisꢀ

function.

Timer Modules – TM

Oneꢀofꢀtheꢀmostꢀfundamentalꢀfunctionsꢀinꢀanyꢀmicrocontrollerꢀdevicesꢀisꢀtheꢀabilityꢀtoꢀcontrolꢀandꢀ

measureꢀtime.ꢀToꢀimplementꢀtimeꢀrelatedꢀfunctionsꢀeachꢀdeviceꢀincludesꢀseveralꢀTimerꢀModules,ꢀ

generallyꢀabbreviatedꢀtoꢀtheꢀnameꢀTM.ꢀTheꢀTMsꢀareꢀmulti-purposeꢀtimingꢀunitsꢀandꢀserveꢀtoꢀprovideꢀ

operationsꢀsuchꢀasꢀTimer/Counter,ꢀInputꢀCapture,ꢀCompareꢀMatchꢀOutputꢀandꢀSingleꢀPulseꢀOutputꢀ

asꢀwellꢀasꢀbeingꢀtheꢀfunctionalꢀunitꢀforꢀtheꢀgenerationꢀofꢀPWMꢀsignals.ꢀEachꢀofꢀtheꢀTMsꢀhasꢀtwoꢀ

interrupts.ꢀTheꢀadditionꢀofꢀinputꢀandꢀoutputꢀpinsꢀforꢀeachꢀTMꢀensuresꢀthatꢀusersꢀareꢀprovidedꢀwithꢀ

timingꢀunitsꢀwithꢀaꢀwideꢀandꢀﬂexibleꢀrangeꢀofꢀfeatures.

TheꢀcommonꢀfeaturesꢀofꢀtheꢀdifferentꢀTMꢀtypesꢀareꢀdescribedꢀhereꢀwithꢀmoreꢀdetailedꢀinformationꢀ

providedꢀinꢀtheꢀindividualꢀStandardꢀandꢀPeriodicꢀTMꢀsections.

Introduction

EachꢀdeviceꢀcontainsꢀfourꢀTMsꢀandꢀeachꢀindividualꢀTMꢀcanꢀbeꢀcategorisedꢀasꢀaꢀcertainꢀtype,ꢀnamelyꢀ

StandardꢀTypeꢀTMꢀorꢀPeriodicꢀTypeꢀTM.ꢀAlthoughꢀsimilarꢀinꢀnature,ꢀtheꢀdifferentꢀTMꢀtypesꢀvaryꢀ

inꢀtheirꢀfeatureꢀcomplexity.ꢀTheꢀcommonꢀfeaturesꢀtoꢀallꢀofꢀtheꢀStandardꢀandꢀPeriodicꢀTypeꢀTMsꢀ

willꢀbeꢀdescribedꢀinꢀthisꢀsectionꢀandꢀtheꢀdetailedꢀoperationꢀregardingꢀeachꢀofꢀtheꢀTMꢀtypesꢀwillꢀbeꢀ

describedꢀinꢀseparateꢀsections.ꢀTheꢀmainꢀfeaturesꢀandꢀdifferencesꢀbetweenꢀtheꢀthreeꢀtypesꢀofꢀTMsꢀareꢀ

summarisedꢀinꢀtheꢀaccompanyingꢀtable.

TM Function

Timeꢁ/Coꢀnteꢁ

STM

PTM

√

Inpꢀt Captꢀꢁe

√

Compaꢁe Match Oꢀtpꢀt

PWM Channels

√

1

Single Pꢀlse Oꢀtpꢀt

PWM Alignment

1

Edge

PWM Adjꢀstment Peꢁiod & Dꢀtꢂ

Dꢀtꢂ oꢁ Peꢁiod

TM Function Summary

Rev. 1.10

ꢆ3

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Device

STM

PTM

10-bit PTM0

10-bit PTM1

10-bit PTMꢅ

BH66Fꢅ650

16-bit STM

BH66Fꢅ660

TM Name/Type Reference

TM Operation

TheꢀdifferentꢀtypesꢀofꢀTMꢀofferꢀaꢀdiverseꢀrangeꢀofꢀfunctions,ꢀfromꢀsimpleꢀtimingꢀoperationsꢀtoꢀPWMꢀ

signalꢀgeneration.ꢀTheꢀkeyꢀtoꢀunderstandingꢀhowꢀtheꢀTMꢀoperatesꢀisꢀtoꢀseeꢀitꢀinꢀtermsꢀofꢀaꢀfreeꢀ

runningꢀcount-upꢀcounterꢀwhoseꢀvalueꢀisꢀthenꢀcomparedꢀwithꢀtheꢀvalueꢀofꢀpre-programmedꢀinternalꢀ

comparators.ꢀWhenꢀtheꢀfreeꢀrunningꢀcount-upꢀcounterꢀhasꢀtheꢀsameꢀvalueꢀasꢀtheꢀpre-programmedꢀ

comparator,ꢀknownꢀasꢀaꢀcompareꢀmatchꢀsituation,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀbeꢀgeneratedꢀwhichꢀ

canꢀclearꢀtheꢀcounterꢀandꢀperhapsꢀalsoꢀchangeꢀtheꢀconditionꢀofꢀtheꢀTMꢀoutputꢀpin.ꢀTheꢀinternalꢀTMꢀ

counterꢀisꢀdrivenꢀbyꢀaꢀuserꢀselectableꢀclockꢀsource,ꢀwhichꢀcanꢀbeꢀanꢀinternalꢀclockꢀorꢀanꢀexternalꢀpin.

TM Clock Source

TheꢀclockꢀsourceꢀwhichꢀdrivesꢀtheꢀmainꢀcounterꢀinꢀeachꢀTMꢀcanꢀoriginateꢀfromꢀvariousꢀsources.ꢀ

TheꢀselectionꢀofꢀtheꢀrequiredꢀclockꢀsourceꢀisꢀimplementedꢀusingꢀtheꢀSTCK2~STCK0ꢀandꢀ

PTnCK2~PTnCK0ꢀbitsꢀinꢀtheꢀSTMꢀandꢀPTMnꢀcontrolꢀregisters,ꢀwhereꢀ“n”ꢀstandsꢀforꢀtheꢀspeciﬁcꢀ

TMꢀserialꢀnumber.ꢀTheꢀclockꢀsourceꢀcanꢀbeꢀaꢀratioꢀofꢀtheꢀsystemꢀclock,ꢀf_SYS,ꢀorꢀtheꢀinternalꢀhighꢀ

clock,ꢀf_H,ꢀtheꢀf_SUBꢀclockꢀsourceꢀorꢀtheꢀexternalꢀSTCKꢀandꢀPTCKnꢀpin.ꢀTheꢀSTCKꢀandꢀPTCKnꢀpinꢀ

clockꢀsourceꢀisꢀusedꢀtoꢀallowꢀanꢀexternalꢀsignalꢀtoꢀdriveꢀtheꢀTMꢀasꢀanꢀexternalꢀclockꢀsourceꢀforꢀeventꢀ

counting.

TM Interrupts

TheꢀStandardꢀorꢀPeriodicꢀtypeꢀTMꢀhasꢀtwoꢀinternalꢀinterrupt,ꢀoneꢀforꢀeachꢀofꢀtheꢀinternalꢀcomparatorꢀ

AꢀorꢀcomparatorꢀP,ꢀwhichꢀgenerateꢀaꢀTMꢀinterruptꢀwhenꢀaꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀWhenꢀaꢀ

TMꢀinterruptꢀisꢀgenerated,ꢀitꢀcanꢀbeꢀusedꢀtoꢀclearꢀtheꢀcounterꢀandꢀalsoꢀtoꢀchangeꢀtheꢀstateꢀofꢀtheꢀTMꢀ

outputꢀpin.

TM External Pins

EachꢀofꢀtheꢀTMs,ꢀirrespectiveꢀofꢀwhatꢀtype,ꢀhasꢀtwoꢀTMꢀinputꢀpins,ꢀwithꢀtheꢀlabelꢀSTCK,ꢀPTCKnꢀ

andꢀSTPI,ꢀPTPnIꢀrespectively.ꢀTheꢀSTM,ꢀPTMnꢀinputꢀpin,ꢀSTCK,ꢀPTCKn,ꢀisꢀessentiallyꢀaꢀclockꢀ

sourceꢀforꢀtheꢀSTM,ꢀPTMnꢀandꢀisꢀselectedꢀusingꢀtheꢀSTCK2~STCK0ꢀorꢀPTnCK2~PTnCK0ꢀbitsꢀ

inꢀtheꢀSTMC0ꢀorꢀPTMnC0ꢀregister.ꢀThisꢀexternalꢀTMꢀinputꢀpinꢀallowsꢀanꢀexternalꢀclockꢀsourceꢀtoꢀ

driveꢀtheꢀinternalꢀTM.ꢀTheꢀSTCK,ꢀPTCKnꢀinputꢀpinꢀcanꢀbeꢀchosenꢀtoꢀhaveꢀeitherꢀaꢀrisingꢀorꢀfallingꢀ

activeꢀedge.ꢀTheꢀSTCKꢀandꢀPTCKnꢀpinsꢀareꢀalsoꢀusedꢀasꢀtheꢀexternalꢀtriggerꢀinputꢀpinꢀinꢀsingleꢀ

pulseꢀoutputꢀmodeꢀforꢀtheꢀSTMꢀandꢀPTMnꢀrespectively.

TheꢀotherꢀSTM,ꢀPTMnꢀinputꢀpin,ꢀSTPI,ꢀPTPnI,ꢀisꢀtheꢀcaptureꢀinputꢀwhoseꢀactiveꢀedgeꢀcanꢀbeꢀaꢀrisingꢀ

edge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀrisingꢀandꢀfallingꢀedgesꢀandꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀ

usingꢀtheꢀSTIO1~STIO0,ꢀPTnIO1~PTnIO0ꢀbitsꢀinꢀtheꢀSTMC1,ꢀPTMnC1ꢀregisterꢀrespectively.ꢀThereꢀ

isꢀanotherꢀcaptureꢀinput,ꢀPTCKn,ꢀforꢀPTMnꢀcaptureꢀinputꢀmode,ꢀwhichꢀcanꢀbeꢀusedꢀasꢀtheꢀexternalꢀ

triggerꢀinputꢀsourceꢀexceptꢀtheꢀPTPnIꢀpin.

TheꢀTMsꢀeachꢀhaveꢀoneꢀorꢀmoreꢀoutputꢀpins.ꢀTheꢀSTPB,ꢀPTP0BꢀisꢀtheꢀinvertedꢀsignalꢀofꢀtheꢀSTP,ꢀ

PTP0ꢀoutput.ꢀTheꢀTMꢀoutputꢀpinsꢀcanꢀbeꢀselectedꢀusingꢀtheꢀcorrespondingꢀpin-sharedꢀfunctionꢀ

selectionꢀbitsꢀdescribedꢀinꢀtheꢀPin-sharedꢀFunctionꢀsection.ꢀWhenꢀtheꢀTMꢀisꢀinꢀtheꢀCompareꢀMatchꢀ

OutputꢀMode,ꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀbyꢀtheꢀTMꢀtoꢀswitchꢀtoꢀaꢀhighꢀorꢀlowꢀlevelꢀorꢀtoꢀtoggleꢀ

whenꢀaꢀcompareꢀmatchꢀsituationꢀoccurs.ꢀTheꢀexternalꢀSTP,ꢀPTPnꢀorꢀSTPB,ꢀPTP0Bꢀoutputꢀpinꢀisꢀalsoꢀ

Rev. 1.10

ꢆꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

theꢀpinꢀwhereꢀtheꢀTMꢀgeneratesꢀtheꢀPWMꢀoutputꢀwaveform.ꢀAsꢀtheꢀTMꢀoutputꢀpinsꢀareꢀpin-sharedꢀ

withꢀotherꢀfunctions,ꢀtheꢀTMꢀoutputꢀfunctionꢀmustꢀﬁrstꢀbeꢀsetupꢀusingꢀrelevantꢀpin-sharedꢀfunctionꢀ

selectionꢀregister.

STM

PTMn

Input

Output

Input

Output

PTCK0ꢄ PTP0Iꢄ

PTCK1ꢄ PTP1I

PTCKꢅꢄ PTPꢅI

PTP0Bꢄ PTP0ꢄ

PTP1ꢄ PTPꢅ

STCKꢄ STPI

STPꢄ STPB

TM External Pins

TM Input/Output Pin Selection

SelectingꢀtoꢀhaveꢀaꢀTMꢀinput/outputꢀorꢀwhetherꢀtoꢀretainꢀitsꢀotherꢀsharedꢀfunctionꢀisꢀimplementedꢀ

usingꢀtheꢀrelevantꢀpin-sharedꢀfunctionꢀselectionꢀregisters,ꢀwithꢀtheꢀcorrespondingꢀselectionꢀbitsꢀinꢀ

eachꢀpin-sharedꢀfunctionꢀregisterꢀcorrespondingꢀtoꢀaꢀTMꢀinput/outputꢀpin.ꢀConﬁguringꢀtheꢀselectionꢀ

bitsꢀcorrectlyꢀwillꢀsetupꢀtheꢀcorrespondingꢀpinꢀasꢀaꢀTMꢀinput/output.ꢀTheꢀdetailsꢀofꢀtheꢀpin-sharedꢀ

functionꢀselectionꢀareꢀdescribedꢀinꢀtheꢀpin-sharedꢀfunctionꢀsection.

STCK

CCR captꢀꢁe inpꢀt

STPI

STM

CCR oꢀtpꢀt

STP

STPB

STM Function Pin Control Block Diagram

PTCKn

CCR captꢀꢁe inpꢀt

PTPnI

PTMn

CCR oꢀtpꢀt

PTPn

PTPnB

PTM Function Pin Control Block Diagram – n=0

PTCKn

CCR captꢀꢁe inpꢀt

PTPnI

PTMn

CCR oꢀtpꢀt

PTPn

PTM Function Pin Control Block Diagram – n=1 or 2

Rev. 1.10

ꢆ5

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Programming Considerations

TheꢀTMꢀCounterꢀRegistersꢀandꢀtheꢀCapture/CompareꢀCCRAꢀandꢀCCRPꢀregisters,ꢀallꢀhaveꢀaꢀlowꢀ

andꢀhighꢀbyteꢀstructure.ꢀTheꢀhighꢀbytesꢀcanꢀbeꢀdirectlyꢀaccessed,ꢀbutꢀasꢀtheꢀlowꢀbytesꢀcanꢀonlyꢀbeꢀ

accessedꢀviaꢀanꢀinternalꢀ8-bitꢀbuffer,ꢀreadingꢀorꢀwritingꢀtoꢀtheseꢀregisterꢀpairsꢀmustꢀbeꢀcarriedꢀoutꢀinꢀ

aꢀspeciﬁcꢀway.ꢀTheꢀimportantꢀpointꢀtoꢀnoteꢀisꢀthatꢀdataꢀtransferꢀtoꢀandꢀfromꢀtheꢀ8-bitꢀbufferꢀandꢀitsꢀ

relatedꢀlowꢀbyteꢀonlyꢀtakesꢀplaceꢀwhenꢀaꢀwriteꢀorꢀreadꢀoperationꢀtoꢀitsꢀcorrespondingꢀhighꢀbyteꢀisꢀ

executed.

AsꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀimplementedꢀinꢀtheꢀwayꢀshownꢀinꢀtheꢀfollowingꢀdiagramꢀandꢀ

accessingꢀtheseꢀregisterꢀpairsꢀisꢀcarriedꢀoutꢀinꢀaꢀspeciﬁcꢀwayꢀasꢀdescribedꢀabove,ꢀitꢀisꢀrecommendedꢀ

toꢀuseꢀtheꢀ“MOV”ꢀinstructionꢀtoꢀaccessꢀtheꢀCCRAꢀandꢀCCRPꢀlowꢀbyteꢀregisters,ꢀnamedꢀSTMAL,ꢀ

PTMnALꢀandꢀPTMnRPL,ꢀusingꢀtheꢀfollowingꢀaccessꢀprocedures.ꢀAccessingꢀtheꢀCCRAꢀorꢀCCRPꢀ

lowꢀbyteꢀregistersꢀwithoutꢀfollowingꢀtheseꢀaccessꢀproceduresꢀwillꢀresultꢀinꢀunpredictableꢀvalues.

PTMn Coꢀnteꢁ Registeꢁ (Read onlꢂ)

PTMnDL

ꢆ-bit Bꢀffeꢁ

PTMnAL

PTMnDH

STM Coꢀnteꢁ Registeꢁ (Read onlꢂ)

STMDL

STMDH

PTMnAH

ꢆ-bit Bꢀffeꢁ

PTMn CCRA Registeꢁ (Read/Wꢁite)

STMAL

STMAH

PTMnRPL

PTMnRPH

STM CCRA Registeꢁ (Read/Wꢁite)

PTMn CCRP Registeꢁ (Read/Wꢁite)

Data Bꢀs

Theꢀfollowingꢀstepsꢀshowꢀtheꢀreadꢀandꢀwriteꢀprocedures:

•ꢀ WritingꢀDataꢀtoꢀCCRAꢀorꢀCCRPꢀ

ꢀ

♦

Stepꢀ1.ꢀWriteꢀdataꢀtoꢀLowꢀByteꢀSTMAL,ꢀPTMnALꢀorꢀPTMnRPL

–ꢀnoteꢀthatꢀhereꢀdataꢀisꢀonlyꢀwrittenꢀtoꢀtheꢀ8-bitꢀbuffer.

ꢀ

♦

Stepꢀ2.ꢀWriteꢀdataꢀtoꢀHighꢀByteꢀSTMAH,ꢀPTMnAHꢀorꢀPTMnRPH

–ꢀhereꢀdataꢀisꢀwrittenꢀdirectlyꢀtoꢀtheꢀhighꢀbyteꢀregistersꢀandꢀsimultaneouslyꢀdataꢀisꢀlatchedꢀ

fromꢀtheꢀ8-bitꢀbufferꢀtoꢀtheꢀLowꢀByteꢀregisters.

•ꢀ ReadingꢀDataꢀfromꢀtheꢀCounterꢀRegistersꢀandꢀCCRAꢀorꢀCCRP

ꢀ

♦

Stepꢀ1.ꢀReadꢀdataꢀfromꢀtheꢀHighꢀByteꢀSTMDH,ꢀPTMnDH,ꢀSTMAH,ꢀPTMnAHꢀorꢀPTMnRPH

–ꢀhereꢀdataꢀisꢀreadꢀdirectlyꢀfromꢀtheꢀHighꢀByteꢀregistersꢀandꢀsimultaneouslyꢀdataꢀisꢀlatchedꢀ

fromꢀtheꢀLowꢀByteꢀregisterꢀintoꢀtheꢀ8-bitꢀbuffer.

ꢀ

♦

Stepꢀ2.ꢀReadꢀdataꢀfromꢀtheꢀLowꢀByteꢀSTMDL,ꢀPTMnDL,ꢀSTMAL,ꢀPTMnALꢀorꢀPTMnRPL

–ꢀthisꢀstepꢀreadsꢀdataꢀfromꢀtheꢀ8-bitꢀbuffer.

Rev. 1.10

ꢆ6

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Standard Type TM – STM

TheꢀStandardꢀTypeꢀTMꢀcontainsꢀﬁveꢀoperatingꢀmodes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀTimer/

EventꢀCounter,ꢀCaptureꢀInput,ꢀSingleꢀPulseꢀOutputꢀandꢀPWMꢀOutputꢀmodes.ꢀTheꢀStandardꢀTMꢀcanꢀ

alsoꢀbeꢀcontrolledꢀwithꢀtwoꢀexternalꢀinputꢀpinsꢀandꢀcanꢀdriveꢀtwoꢀexternalꢀoutputꢀpins.

STM Core

STM Input Pin

STM Output Pin

16-bit STM

STCKꢄ STPI

STPꢄ STPB

CCRP

Compaꢁatoꢁ P Match

ꢆ-bit Compaꢁatoꢁ P

bꢆ~b15

STMPF Inteꢁꢁꢀpt

STOC

000

001

010

011

100

101

110

111

f_SYS/ꢃ

f_SYS

f_H/16

f_H/6ꢃ

f_SUB

STP

Coꢀnteꢁ Cleaꢁ

0

1

Oꢀtpꢀt

Contꢁol

Polaꢁitꢂ

Contꢁol

16-bit Coꢀnt-ꢀp Coꢀnteꢁ

STPB

f_SUB

STON

STPAU

STCCLR

STM1ꢄ STM0

STIO1ꢄ STIO0

STPOL

PxSn

b0~b15

Pin Contꢁol

STCK

Compaꢁatoꢁ A Match

STIO1ꢄ STIO0

16-bit Compaꢁatoꢁ A

STMAF Inteꢁꢁꢀpt

STCKꢅ~STCK0

PxSn

IFSn

CCRA

Edge Detectoꢁ

Pin Contꢁol

STPI

PxSn

Standard Type TM Block Diagram

Standard TM Operation

TheꢀsizeꢀofꢀStandardꢀTMꢀisꢀ16-bitꢀwideꢀandꢀitsꢀcoreꢀisꢀaꢀ16-bitꢀcount-upꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀ

aꢀuserꢀselectableꢀinternalꢀorꢀexternalꢀclockꢀsource.ꢀThereꢀareꢀalsoꢀtwoꢀinternalꢀcomparatorsꢀwithꢀtheꢀ

names,ꢀComparatorꢀAꢀandꢀComparatorꢀP.ꢀTheseꢀcomparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀ

withꢀCCRPꢀandꢀCCRAꢀregisters.ꢀTheꢀCCRPꢀcomparatorꢀisꢀ8-bitꢀwideꢀwhoseꢀvalueꢀisꢀcomparedꢀ

withꢀtheꢀhighestꢀ8ꢀbitsꢀinꢀtheꢀcounterꢀwhileꢀtheꢀCCRAꢀisꢀtheꢀsixteenꢀbitsꢀandꢀthereforeꢀcomparesꢀallꢀ

counterꢀbits.

Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ16-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ

clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀSTONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ

automaticallyꢀbyꢀaꢀcounterꢀoverﬂowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ

Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀSTMꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀStandardꢀ

TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ

sourcesꢀincludingꢀanꢀinputꢀpinꢀandꢀcanꢀalsoꢀcontrolꢀanꢀoutputꢀpin.ꢀAllꢀoperatingꢀsetupꢀconditionsꢀareꢀ

selectedꢀusingꢀrelevantꢀinternalꢀregisters.

Rev. 1.10

ꢆ7

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Standard Type TM Register Description

OverallꢀoperationꢀofꢀtheꢀStandardꢀTMꢀisꢀcontrolledꢀusingꢀaꢀseriesꢀofꢀregisters.ꢀAꢀreadꢀonlyꢀregisterꢀ

pairꢀexistsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ16-bitꢀvalue,ꢀwhileꢀaꢀread/writeꢀregisterꢀpairꢀexistsꢀtoꢀstoreꢀ

theꢀinternalꢀ16-bitꢀCCRAꢀvalue.ꢀTheꢀSTMRPꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀ8-bitꢀCCRPꢀbits.ꢀTheꢀ

remainingꢀtwoꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀsetupꢀtheꢀdifferentꢀoperatingꢀandꢀcontrolꢀmodes.

Bit

Register

Name

7

STPAU

STM1

D7

6

STCKꢅ

STM0

D6

5

STCK1

STIO1

D5

4

STCK0

STIO0

Dꢃ

3

STON

STOC

D3

2

—

1

—

0

—

STMC0

STMC1

STMDL

STMDH

STMAL

STMAH

STMRP

STPOL

Dꢅ

STDPX

D1

STCCLR

D0

D15

D7

D1ꢃ

D6

D13

D5

D1ꢅ

Dꢃ

D11

D3

D10

Dꢅ

D9

Dꢆ

D1

D0

D15

D7

D1ꢃ

D6

D13

D5

D1ꢅ

Dꢃ

D11

D3

D10

Dꢅ

D9

Dꢆ

D1

D0

16-bit Standard TM Registers List

STMDL Register

Bit

Name

R/W

7

D7

R

6

D6

R

5

D5

R

4

Dꢃ

R

3

D3

R

2

1

D1

R

0

D0

R

Dꢅ

R

POR

0

Bitꢀ7~0

D7~D0:ꢀSTMꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0

STMꢀ16-bitꢀCounterꢀbitꢀ7~bitꢀ0

STMDH Register

Bit

Name

R/W

7

D15

R

6

D1ꢃ

R

5

D13

R

4

D1ꢅ

R

3

D11

R

2

D10

R

1

D9

R

0

Dꢆ

R

POR

0

Bitꢀ7~0

D15~D8:ꢀSTMꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0

STMꢀ16-bitꢀCounterꢀbitꢀ15~bitꢀ8

STMAL Register

Bit

Name

R/W

7

D7

R/W

0

6

D6

R/W

0

5

D5

R/W

0

4

Dꢃ

R/W

0

3

D3

R/W

0

2

Dꢅ

R/W

0

1

D1

R/W

0

D0

R/W

0

POR

Bitꢀ7~0

D7~D0:ꢀSTMꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0

STMꢀ16-bitꢀCCRAꢀbitꢀ7~bitꢀ0

Rev. 1.10

ꢆꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

STMAH Register

Bit

Name

R/W

7

6

5

4

3

2

1

D9

R/W

0

Dꢆ

R/W

0

D15

R/W

0

D1ꢃ

R/W

0

D13

R/W

0

D1ꢅ

R/W

0

D11

R/W

0

D10

R/W

0

POR

Bitꢀ7~0

D15~D8:ꢀSTMꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0

STMꢀ16-bitꢀCCRAꢀbitꢀ15~bitꢀ8

STMC0 Register

Bit

7

6

STCKꢅ

R/W

0

5

STCK1

R/W

0

4

STCK0

R/W

0

3

STON

R/W

0

2

1

0

Name

R/W

STPAU

R/W

0

—

POR

Bitꢀ7

STPAU:ꢀSTMꢀCounterꢀPauseꢀControl

0:ꢀRun

1:ꢀPause

Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀ“0”ꢀrestoresꢀ

normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀSTMꢀwillꢀremainꢀpoweredꢀ

upꢀandꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀ

thisꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀ

changesꢀtoꢀaꢀlowꢀvalueꢀagain.

Bitꢀ6~4

STCK2~STCK0:ꢀSelectꢀSTMꢀCounterꢀClock

000:ꢀf_SYS/4

001:ꢀf_SYS

010:ꢀf_H/16

011:ꢀf_H/64

100:ꢀf_SUB

101:ꢀf_SUB

110:ꢀSTCKꢀrisingꢀedgeꢀclock

111:ꢀSTCKꢀfallingꢀedgeꢀclock

TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀSTM.ꢀTheꢀexternalꢀpinꢀclockꢀ

sourceꢀcanꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀf_SYSꢀisꢀ

theꢀsystemꢀclock,ꢀwhileꢀf_Hꢀandꢀf_SUBꢀareꢀotherꢀinternalꢀclocks,ꢀtheꢀdetailsꢀofꢀwhichꢀcanꢀ

beꢀfoundꢀinꢀtheꢀoscillatorꢀsection.

Bitꢀ3

STON:ꢀSTMꢀCounterꢀOn/OffꢀControl

0:ꢀOff

1:ꢀOn

Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀSTM.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀ

theꢀcounterꢀtoꢀrunꢀwhileꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀSTM.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀ

willꢀstopꢀtheꢀcounterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀSTMꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀ

consumption.ꢀWhenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀ

willꢀbeꢀresetꢀtoꢀzero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀ

counterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀuntilꢀtheꢀbitꢀreturnsꢀhighꢀagain.ꢀIfꢀtheꢀSTMꢀisꢀinꢀ

theꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀtheꢀPWMꢀOutputꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀ

ModeꢀthenꢀtheꢀSTMꢀoutputꢀpinꢀwillꢀbeꢀresetꢀtoꢀitsꢀinitialꢀcondition,ꢀasꢀspeciﬁedꢀbyꢀtheꢀ

STOCꢀbit,ꢀwhenꢀtheꢀSTONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh.

Bitꢀ2~0ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

Rev. 1.10

ꢆ9

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

STMC1 Register

Bit

Name

R/W

7

STM1

R/W

0

6

STM0

R/W

0

5

STIO1

R/W

0

4

STIO0

R/W

0

3

STOC

R/W

0

2

STPOL

R/W

0

1

STDPX

R/W

0

STCCLR

R/W

POR

0

Bitꢀ7~6

STM1~STM0:ꢀSelectꢀSTMꢀOperatingꢀMode

00:ꢀCompareꢀMatchꢀOutputꢀMode

01:ꢀCaptureꢀInputꢀMode

10:ꢀPWMꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode

11:ꢀTimer/CounterꢀMode

TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀSTM.ꢀToꢀensureꢀreliableꢀoperationꢀ

theꢀSTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀSTM1ꢀandꢀSTM0ꢀ

bits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀSTMꢀoutputꢀpinꢀstateꢀisꢀundeﬁned.

Bitꢀ5~4

STIO1~STIO0:ꢀSelectꢀSTMꢀExternalꢀPinꢀ(STPꢀorꢀSTPI)ꢀFunction

CompareꢀMatchꢀOutputꢀMode

00:ꢀNoꢀchange

01:ꢀOutputꢀlow

10:ꢀOutputꢀhigh

11:ꢀToggleꢀoutput

PWMꢀOutputꢀMode/SingleꢀPulseꢀOutputꢀMode

00:ꢀPWMꢀoutputꢀinactiveꢀstate

01:ꢀPWMꢀoutputꢀactiveꢀstate

10:ꢀPWMꢀoutput

11:ꢀSingleꢀPulseꢀOutput

CaptureꢀInputꢀMode

00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀSTPI

01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀSTPI

10:ꢀInputꢀcaptureꢀatꢀrising/fallingꢀedgeꢀofꢀSTPI

11:ꢀInputꢀcaptureꢀdisabled

Timer/CounterꢀMode

Unused

TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀSTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ

certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ

modeꢀtheꢀSTMꢀisꢀrunning.

InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀ

STMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀ

A.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ

stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ

“0”,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀSTMꢀoutputꢀ

pinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀSTOCꢀbitꢀinꢀtheꢀSTMC1ꢀregister.ꢀNoteꢀthatꢀtheꢀoutputꢀ

levelꢀrequestedꢀbyꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀvalueꢀ

setupꢀusingꢀtheꢀSTOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀSTMꢀoutputꢀpinꢀwhenꢀ

aꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀSTMꢀoutputꢀpinꢀchangesꢀstate,ꢀitꢀcanꢀbeꢀresetꢀtoꢀitsꢀ

initialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀSTONꢀbitꢀfromꢀlowꢀtoꢀhigh.

InꢀtheꢀPWMꢀMode,ꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀSTMꢀoutputꢀpinꢀ

changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀ

functionꢀisꢀmodifiedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀonlyꢀchangeꢀtheꢀ

valuesꢀofꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀonlyꢀafterꢀtheꢀSTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀ

UnpredictableꢀPWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀareꢀchangedꢀ

whenꢀtheꢀSTMꢀisꢀrunning.

Rev. 1.10

90

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Bitꢀ3

STOC:ꢀSTMꢀSTPꢀOutputꢀControl

CompareꢀMatchꢀOutputꢀMode

0:ꢀInitialꢀlow

1:ꢀInitialꢀhigh

PWMꢀOutputꢀMode/SingleꢀPulseꢀOutputꢀMode

0:ꢀActiveꢀlow

1:ꢀActiveꢀhigh

ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀSTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ

whetherꢀSTMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀ

OutputꢀMode/SingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀSTMꢀisꢀinꢀtheꢀTimer/

CounterꢀMode.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀ

theꢀSTMꢀoutputꢀpinꢀbeforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀOutputꢀMode/Singleꢀ

PulseꢀOutputꢀModeꢀitꢀdeterminesꢀifꢀtheꢀPWMꢀsignalꢀisꢀactiveꢀhighꢀorꢀactiveꢀlow.

Bitꢀ2

STPOL:ꢀSTMꢀSTPꢀOutputꢀPolarityꢀControl

0:ꢀNon-inverted

1:ꢀInverted

ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀSTPꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀSTMꢀ

outputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀ“0”.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀ

STMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.

Bitꢀ1

Bitꢀ0

STDPX:ꢀSTMꢀPWMꢀDuty/PeriodꢀControl

0:ꢀCCRPꢀ–ꢀperiod;ꢀCCRAꢀ–ꢀduty

1:ꢀCCRPꢀ–ꢀduty;ꢀCCRAꢀ–ꢀperiod

ThisꢀbitꢀdeterminesꢀwhichꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀforꢀperiodꢀandꢀ

dutyꢀcontrolꢀofꢀtheꢀPWMꢀwaveform.

STCCLR:ꢀSTMꢀCounterꢀClearꢀConditionꢀSelection

0:ꢀComparatorꢀPꢀmatch

1:ꢀComparatorꢀAꢀmatch

Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀtheꢀ

StandardꢀTMꢀcontainsꢀtwoꢀcomparators,ꢀComparatorꢀAꢀandꢀComparatorꢀP,ꢀeitherꢀofꢀ

whichꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounter.ꢀWithꢀtheꢀSTCCLRꢀbitꢀsetꢀhigh,ꢀ

theꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ

Whenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀ

theꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀoverﬂow.ꢀAꢀcounterꢀoverﬂowꢀclearingꢀmethodꢀcanꢀ

onlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀbitsꢀareꢀallꢀclearedꢀtoꢀ“0”.ꢀTheꢀSTCCLRꢀbitꢀisꢀnotꢀ

usedꢀinꢀtheꢀPWMꢀOutput,ꢀSingleꢀPulseꢀOutputꢀorꢀCaptureꢀInputꢀMode.

STMRP Register

Bit

Name

R/W

7

D7

R/W

0

6

D6

R/W

0

5

D5

R/W

0

4

Dꢃ

R/W

0

3

D3

R/W

0

2

Dꢅ

R/W

0

1

D1

R/W

0

D0

R/W

0

POR

Bitꢀ7~0

D7~D0:ꢀSTMꢀCCRPꢀ8-bitꢀRegister,ꢀComparedꢀwithꢀtheꢀSTMꢀCounterꢀbitꢀ15~bitꢀ8

ComparatorꢀPꢀmatchꢀperiod

0:ꢀ65536ꢀSTMꢀclocks

1~255:ꢀ(1~255)ꢀ×ꢀ256ꢀSTMꢀclocks

TheseꢀeightꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀvalueꢀonꢀtheꢀinternalꢀCCRPꢀ8-bitꢀregister,ꢀwhichꢀ

areꢀthenꢀcomparedꢀwithꢀtheꢀinternalꢀcounter'sꢀhighestꢀeightꢀbits.ꢀTheꢀresultꢀofꢀthisꢀ

comparisonꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀifꢀtheꢀSTCCLRꢀbitꢀisꢀsetꢀtoꢀ“0”.ꢀ

SettingꢀtheꢀSTCCLRꢀbitꢀtoꢀ“0”ꢀensuresꢀthatꢀaꢀcompareꢀmatchꢀwithꢀtheꢀCCRPꢀvaluesꢀ

willꢀresetꢀtheꢀinternalꢀcounter.ꢀAsꢀtheꢀCCRPꢀbitsꢀareꢀonlyꢀcomparedꢀwithꢀtheꢀhighestꢀ

eightꢀcounterꢀbits,ꢀtheꢀcompareꢀvaluesꢀexistꢀinꢀ256ꢀclockꢀcycleꢀmultiples.ꢀClearingꢀallꢀ

eightꢀbitsꢀtoꢀ“0”ꢀisꢀinꢀeffectꢀallowingꢀtheꢀcounterꢀtoꢀoverﬂowꢀatꢀitsꢀmaximumꢀvalue.

Rev. 1.10

91

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Standard Type TM Operation Modes

TheꢀStandardꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀﬁveꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀMode,ꢀ

PWMꢀOutputꢀMode,ꢀSingleꢀPulseꢀOutputꢀMode,ꢀCaptureꢀInputꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀ

operatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀSTM1ꢀandꢀSTM0ꢀbitsꢀinꢀtheꢀSTMC1ꢀregister.

Compare Match Output Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀSTM1ꢀandꢀSTM0ꢀinꢀtheꢀSTMC1ꢀregister,ꢀshouldꢀbeꢀsetꢀtoꢀ“00”ꢀrespectively.ꢀ

Inꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀbyꢀthreeꢀmethods.ꢀTheseꢀareꢀ

aꢀcounterꢀoverﬂow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP.ꢀ

WhenꢀtheꢀSTCCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀcanꢀbeꢀcleared.ꢀOneꢀisꢀwhenꢀ

aꢀcompareꢀmatchꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀCCRPꢀbitsꢀareꢀallꢀ“0”ꢀwhichꢀallowsꢀtheꢀ

counterꢀtoꢀoverﬂow.ꢀHereꢀbothꢀSTMAFꢀandꢀSTMPFꢀinterruptꢀrequestꢀﬂagsꢀforꢀComparatorꢀAꢀandꢀ

ComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.

IfꢀtheꢀSTCCLRꢀbitꢀinꢀtheꢀSTMC1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ

matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀSTMAFꢀinterruptꢀrequestꢀﬂagꢀwillꢀbeꢀ

generatedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀwhenꢀ

STCCLRꢀisꢀhighꢀnoꢀSTMPFꢀinterruptꢀrequestꢀﬂagꢀwillꢀbeꢀgenerated.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀ

Mode,ꢀtheꢀCCRAꢀcanꢀnotꢀbeꢀsetꢀtoꢀ“0”.

Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀSTMꢀoutputꢀpin,ꢀwillꢀchangeꢀ

state.ꢀTheꢀSTMꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀaꢀSTMAFꢀinterruptꢀrequestꢀ

ﬂagꢀisꢀgeneratedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀSTMPFꢀinterruptꢀrequestꢀ

ﬂag,ꢀgeneratedꢀfromꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀeffectꢀonꢀtheꢀSTMꢀ

outputꢀpin.ꢀTheꢀwayꢀinꢀwhichꢀtheꢀSTMꢀoutputꢀpinꢀchangesꢀstateꢀareꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀ

theꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀinꢀtheꢀSTMC1ꢀregister.ꢀTheꢀSTMꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀtheꢀ

STIO1ꢀandꢀSTIO0ꢀbitsꢀtoꢀgoꢀhigh,ꢀtoꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀcompareꢀ

matchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀSTMꢀoutputꢀpin,ꢀwhichꢀisꢀsetupꢀafterꢀ

theꢀSTONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀSTOCꢀbit.ꢀNoteꢀthatꢀifꢀtheꢀSTIO1ꢀandꢀ

STIO0ꢀbitsꢀareꢀ“0”ꢀthenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.

Rev. 1.10

9ꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Coꢀnteꢁ oveꢁflow

CCRP=0

Coꢀnteꢁ Valꢀe

0xFFFF

STCCLR = 0; STM [1:0] = 00

CCRP > 0

Coꢀnteꢁ cleaꢁed bꢂ CCRP valꢀe

CCRP > 0

Coꢀnteꢁ

Restaꢁt

Resꢀme

Paꢀse

CCRP

CCRA

Stop

Time

STON

STPAU

STPOL

CCRP Int. flag

STMPF

CCRA Int. flag

STMAF

STM

O/P Pin

Oꢀtpꢀt not affected bꢂ

STMAF flag. Remains High

ꢀntil ꢁeset bꢂ STON bit

Oꢀtpꢀt pin set to

initial Level Low if

STOC=0

Oꢀtpꢀt Toggle

with STMAF flag

Oꢀtpꢀt Inveꢁts

when STPOL is high

Oꢀtpꢀt Pin

Note STIO [1:0] = 10

Active High Oꢀtpꢀt select

Reset to Initial valꢀe

Oꢀtpꢀt contꢁolled bꢂ

otheꢁ pin-shaꢁed fꢀnction

Heꢁe STIO [1:0] = 11

Toggle Oꢀtpꢀt select

Compare Match Output Mode – STCCLR=0

Note:ꢀ1.ꢀWithꢀSTCCLR=0ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter

2.ꢀTheꢀSTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀSTMAFꢀﬂag

3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsinitialꢀstateꢀbyꢀaꢀSTONꢀbitꢀrisingꢀedge

Rev. 1.10

93

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Coꢀnteꢁ Valꢀe

STCCLR = 1; STM [1:0] = 00

CCRA = 0

Coꢀnteꢁ oveꢁflow

CCRA > 0 Coꢀnteꢁ cleaꢁed bꢂ CCRA valꢀe

0xFFFF

CCRA

CCRP

CCRA=0

Resꢀme

Paꢀse

Stop

Coꢀnteꢁ Restaꢁt

Time

STON

STPAU

STPOL

No STMAF flag

geneꢁated on

CCRA oveꢁflow

CCRA Int. flag

STMAF

CCRP Int. flag

STMPF

STMPF not

geneꢁated

Oꢀtpꢀt does

not change

STM

O/P Pin

Oꢀtpꢀt not affected bꢂ

STMAF flag. Remains High

ꢀntil ꢁeset bꢂ STON bit

Oꢀtpꢀt Inveꢁts

when STPOL is high

Oꢀtpꢀt Toggle

with STMAF flag

Oꢀtpꢀt pin set to

initial Level Low if

STOC=0

Oꢀtpꢀt Pin

Reset to Initial valꢀe

Oꢀtpꢀt contꢁolled bꢂ

otheꢁ pin-shaꢁed fꢀnction

Note STIO [1:0] = 10

Active High Oꢀtpꢀt select

Heꢁe STIO [1:0] = 11

Toggle Oꢀtpꢀt select

Compare Match Output Mode – STCCLR=1

Note:ꢀ1.ꢀWithꢀSTCCLR=1ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter

2.ꢀTheꢀSTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀSTMAFꢀﬂag

3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀSTONꢀbitꢀrisingꢀedge

4.ꢀAꢀSTMPFꢀﬂagꢀisꢀnotꢀgeneratedꢀwhenꢀSTCCLR=1

Rev. 1.10

9ꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Timer/Counter Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀSTM1ꢀandꢀSTM0ꢀinꢀtheꢀSTMC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“11”ꢀrespectively.ꢀ

TheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀ

generatingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/CounterꢀModeꢀtheꢀSTMꢀ

outputꢀpinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀCompareꢀ

MatchꢀOutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀSTMꢀoutputꢀpinꢀisꢀnotꢀusedꢀinꢀ

thisꢀmode,ꢀtheꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunction.

PWM Output Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀSTM1ꢀandꢀSTM0ꢀinꢀtheꢀSTMC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“10”ꢀrespectivelyꢀ

andꢀalsoꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ“10”ꢀrespectively.ꢀTheꢀPWMꢀfunctionꢀwithinꢀ

theꢀSTMꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀsuchꢀasꢀmotorꢀcontrol,ꢀheatingꢀcontrol,ꢀ

illuminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀﬁxedꢀfrequencyꢀbutꢀofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀ

STMꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀgeneratedꢀwithꢀvaryingꢀequivalentꢀDCꢀRMSꢀ

values.

AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ

waveformꢀisꢀextremelyꢀflexible.ꢀInꢀtheꢀPWMꢀmode,ꢀtheꢀSTCCLRꢀbitꢀhasꢀnoꢀeffectꢀasꢀtheꢀPWMꢀ

period.ꢀBothꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀtoꢀgenerateꢀtheꢀPWMꢀwaveform,ꢀoneꢀregisterꢀ

isꢀusedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀandꢀthusꢀcontrolꢀtheꢀPWMꢀwaveformꢀfrequency,ꢀwhileꢀtheꢀotherꢀ

oneꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdutyꢀcycle.ꢀWhichꢀregisterꢀisꢀusedꢀtoꢀcontrolꢀeitherꢀfrequencyꢀorꢀdutyꢀcycleꢀ

isꢀdeterminedꢀusingꢀtheꢀSTDPXꢀbitꢀinꢀtheꢀSTMC1ꢀregister.ꢀTheꢀPWMꢀwaveformꢀfrequencyꢀandꢀdutyꢀ

cycleꢀcanꢀthereforeꢀbeꢀcontrolledꢀbyꢀtheꢀvaluesꢀinꢀtheꢀCCRAꢀandꢀCCRPꢀregisters.

Anꢀinterruptꢀﬂag,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRAꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀmatchꢀ

occursꢀfromꢀeitherꢀComparatorꢀAꢀorꢀComparatorꢀP.ꢀTheꢀSTOCꢀbitꢀinꢀtheꢀSTMC1ꢀregisterꢀisꢀusedꢀtoꢀ

selectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀwaveformꢀwhileꢀtheꢀtwoꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀareꢀusedꢀtoꢀ

enableꢀtheꢀPWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀSTMꢀoutputꢀpinꢀtoꢀaꢀﬁxedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀSTPOLꢀbitꢀ

isꢀusedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.

• 16-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=0

CCRP

Peꢁiod

Dꢀtꢂ

1~255

0

CCRP×ꢅ56

65536

CCRA

Ifꢀf_SYSꢀ=ꢀ16MHz,ꢀTMꢀclockꢀsourceꢀisꢀf_SYS/4,ꢀCCRPꢀ=ꢀ2ꢀandꢀCCRAꢀ=ꢀ128,

TheꢀSTMꢀPWMꢀoutputꢀfrequencyꢀ=ꢀ(f_SYS/4)ꢀ/ꢀ(2×256)ꢀ=ꢀf_SYSꢀ/ꢀ2048ꢀ=ꢀ7.8125ꢀkHz,ꢀ

dutyꢀ=ꢀ128ꢀ/ꢀ(2×256)ꢀ=ꢀ25%.

IfꢀtheꢀDutyꢀvalueꢀdeﬁnedꢀbyꢀtheꢀCCRAꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀthenꢀtheꢀ

PWMꢀoutputꢀdutyꢀisꢀ100%.

• 16-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=1

CCRP

Peꢁiod

Dꢀtꢂ

1~255

0

CCRA

CCRP×ꢅ56

65536

TheꢀPWMꢀoutputꢀperiodꢀisꢀdeterminedꢀbyꢀtheꢀCCRAꢀregisterꢀvalueꢀtogetherꢀwithꢀtheꢀTMꢀclockꢀ

whileꢀtheꢀPWMꢀdutyꢀcycleꢀisꢀdeﬁnedꢀbyꢀtheꢀCCRPꢀregisterꢀvalueꢀexceptꢀwhenꢀtheꢀCCRPꢀvalueꢀisꢀ

equalꢀtoꢀ“0”.

Rev. 1.10

95

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Coꢀnteꢁ Valꢀe

STDPX = 0; STM [1:0] = 10

Coꢀnteꢁ cleaꢁed bꢂ

CCRP

Coꢀnteꢁ Reset when

STON ꢁetꢀꢁns high

CCRP

CCRA

Coꢀnteꢁ Stop if

STON bit low

Paꢀse

Resꢀme

Time

STON

STPAU

STPOL

CCRA Int. flag

STMAF

CCRP Int. flag

STMPF

STM O/P Pin

(STOC=1)

STM O/P Pin

(STOC=0)

PWM Dꢀtꢂ Cꢂcle

set bꢂ CCRA

PWM ꢁesꢀmes

opeꢁation

Oꢀtpꢀt contꢁolled bꢂ

otheꢁ pin-shaꢁed fꢀnction

Oꢀtpꢀt Inveꢁts

when STPOL = 1

PWM Peꢁiod

set bꢂ CCRP

PWM Output Mode – STDPX=0

Note:ꢀ1.ꢀHereꢀSTDPX=0ꢀ–ꢀCounterꢀclearedꢀbyꢀCCRP

2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod

3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀSTIOꢀ[1:0]=00ꢀorꢀ01

4.ꢀTheꢀSTCCLRꢀbitꢀhasꢀnoꢀinﬂuenceꢀonꢀPWMꢀoperation

Rev. 1.10

96

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Coꢀnteꢁ Valꢀe

STDPX = 1; STM [1:0] = 10

Coꢀnteꢁ cleaꢁed bꢂ

CCRA

Coꢀnteꢁ Reset when

STON ꢁetꢀꢁns high

CCRA

CCRP

Coꢀnteꢁ Stop if

STON bit low

Paꢀse

Resꢀme

Time

STON

STPAU

STPOL

CCRP Int.

flag STMPF

CCRA Int.

flag STMAF

STM O/P Pin

(STOC=1)

STM O/P Pin

(STOC=0)

PWM ꢁesꢀmes

opeꢁation

PWM Dꢀtꢂ Cꢂcle

set bꢂ CCRP

Oꢀtpꢀt contꢁolled bꢂ

otheꢁ pin-shaꢁed fꢀnction

Oꢀtpꢀt Inveꢁts

when STPOL = 1

PWM Peꢁiod set bꢂ CCRA

PWM Output Mode – STDPX=1

Note:ꢀ1.ꢀHereꢀSTDPX=1ꢀ–ꢀCounterꢀclearedꢀbyꢀCCRA

2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod

3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀevenꢀwhenꢀSTIOꢀ[1:0]=00ꢀorꢀ01

4.ꢀTheꢀSTCCLRꢀbitꢀhasꢀnoꢀinﬂuenceꢀonꢀPWMꢀoperation

Rev. 1.10

97

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Single Pulse Output Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀSTM1ꢀandꢀSTM0ꢀinꢀtheꢀSTMC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“10”ꢀrespectivelyꢀ

andꢀalsoꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ“11”ꢀrespectively.ꢀTheꢀSingleꢀPulseꢀOutputꢀ

Mode,ꢀasꢀtheꢀnameꢀsuggests,ꢀwillꢀgenerateꢀaꢀsingleꢀshotꢀpulseꢀonꢀtheꢀSTMꢀoutputꢀpin.ꢀ

TheꢀtriggerꢀforꢀtheꢀpulseꢀoutputꢀleadingꢀedgeꢀisꢀaꢀlowꢀtoꢀhighꢀtransitionꢀofꢀtheꢀSTONꢀbit,ꢀwhichꢀcanꢀ

beꢀimplementedꢀusingꢀtheꢀapplicationꢀprogram.ꢀHoweverꢀinꢀtheꢀSingleꢀPulseꢀMode,ꢀtheꢀSTONꢀbitꢀ

canꢀalsoꢀbeꢀmadeꢀtoꢀautomaticallyꢀchangeꢀfromꢀlowꢀtoꢀhighꢀusingꢀtheꢀexternalꢀSTCKꢀpin,ꢀwhichꢀwillꢀ

inꢀturnꢀinitiateꢀtheꢀSingleꢀPulseꢀoutput.ꢀWhenꢀtheꢀSTONꢀbitꢀtransitionsꢀtoꢀaꢀhighꢀlevel,ꢀtheꢀcounterꢀ

willꢀstartꢀrunningꢀandꢀtheꢀpulseꢀleadingꢀedgeꢀwillꢀbeꢀgenerated.ꢀTheꢀSTONꢀbitꢀshouldꢀremainꢀhighꢀ

whenꢀtheꢀpulseꢀisꢀinꢀitsꢀactiveꢀstate.ꢀTheꢀgeneratedꢀpulseꢀtrailingꢀedgeꢀwillꢀbeꢀgeneratedꢀwhenꢀtheꢀ

STONꢀbitꢀisꢀclearedꢀtoꢀ“0”,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogramꢀorꢀwhenꢀaꢀ

compareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀ

HoweverꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀautomaticallyꢀclearꢀtheꢀSTONꢀbitꢀandꢀ

thusꢀgenerateꢀtheꢀSingleꢀPulseꢀoutputꢀtrailingꢀedge.ꢀInꢀthisꢀwayꢀtheꢀCCRAꢀvalueꢀcanꢀbeꢀusedꢀtoꢀ

controlꢀtheꢀpulseꢀwidth.ꢀAꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀgenerateꢀaꢀSTMꢀinterrupt.ꢀ

Theꢀcounterꢀcanꢀonlyꢀbeꢀresetꢀbackꢀtoꢀ“0”ꢀwhenꢀtheꢀSTONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhenꢀtheꢀ

counterꢀrestarts.ꢀInꢀtheꢀSingleꢀPulseꢀModeꢀCCRPꢀisꢀnotꢀused.ꢀTheꢀSTCCLRꢀandꢀSTDPXꢀbitsꢀareꢀnotꢀ

usedꢀinꢀthisꢀMode.

CCRA

Leading Edge

Tꢁailing Edge

S/W Command SET "STON"

S/W Command CLR "STON"

oꢁ

CCRA Compaꢁe Match

STON bit

0 → 1

STON bit

1 → 0

oꢁ

STCK Pin Tꢁansition

STP Oꢀtpꢀt Pin

Pꢀlse Width = CCRA Valꢀe

Single Pulse Generation

Rev. 1.10

9ꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Coꢀnteꢁ Valꢀe

STM [1:0] = 10 ; STIO [1:0] = 11

Coꢀnteꢁ stopped bꢂ

CCRA

Coꢀnteꢁ Reset when

STON ꢁetꢀꢁns high

CCRA

CCRP

Coꢀnteꢁ Stops

bꢂ softwaꢁe

Resꢀme

Paꢀse

Time

STON

Aꢀto. set bꢂ

STCK pin

Softwaꢁe Cleaꢁed bꢂ

Softwaꢁe

Tꢁiggeꢁ

Softwaꢁe

Cleaꢁ

Softwaꢁe

Tꢁiggeꢁ

Softwaꢁe

Tꢁiggeꢁ

CCRA match

STCK pin

STPAU

STCK pin

Tꢁiggeꢁ

STPOL

No CCRP

Inteꢁꢁꢀpts

geneꢁated

CCRP Int.

Flag STMPF

CCRA Int.

Flag STMAF

STM O/P Pin

(STOC=1)

STM O/P Pin

(STOC=0)

Oꢀtpꢀt Inveꢁts

when STPOL = 1

Pꢀlse Width

set bꢂ CCRA

Single Pulse Mode

Note:ꢀ1.ꢀCounterꢀstoppedꢀbyꢀCCRA

2.ꢀCCRPꢀisꢀnotꢀused

3.ꢀTheꢀpulseꢀtriggeredꢀbyꢀtheꢀSTCKꢀpinꢀorꢀbyꢀsettingꢀtheꢀSTONꢀbitꢀhigh

4.ꢀAꢀSTCKꢀpinꢀactiveꢀedgeꢀwillꢀautomaticallyꢀsetꢀtheꢀSTONꢀbitꢀhigh.

5.ꢀInꢀtheꢀSingleꢀPulseꢀMode,ꢀSTIOꢀ[1:0]ꢀmustꢀbeꢀsetꢀtoꢀ“11”ꢀandꢀcanꢀnotꢀbeꢀchanged.

Rev. 1.10

99

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Capture Input Mode

ToꢀselectꢀthisꢀmodeꢀbitsꢀSTM1ꢀandꢀSTM0ꢀinꢀtheꢀSTMC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“01”ꢀrespectively.ꢀ

Thisꢀmodeꢀenablesꢀexternalꢀsignalsꢀtoꢀcaptureꢀandꢀstoreꢀtheꢀpresentꢀvalueꢀofꢀtheꢀinternalꢀcounterꢀ

andꢀcanꢀthereforeꢀbeꢀusedꢀforꢀapplicationsꢀsuchꢀasꢀpulseꢀwidthꢀmeasurements.ꢀTheꢀexternalꢀsignalꢀ

isꢀsuppliedꢀonꢀtheꢀSTPIꢀpin,ꢀwhoseꢀactiveꢀedgeꢀcanꢀbeꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀrisingꢀ

andꢀfallingꢀedges;ꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀusingꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀinꢀ

theꢀSTMC1ꢀregister.ꢀTheꢀcounterꢀisꢀstartedꢀwhenꢀtheꢀSTONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhichꢀisꢀ

initiatedꢀusingꢀtheꢀapplicationꢀprogram.

WhenꢀtheꢀrequiredꢀedgeꢀtransitionꢀappearsꢀonꢀtheꢀSTPIꢀpinꢀtheꢀpresentꢀvalueꢀinꢀtheꢀcounterꢀwillꢀbeꢀ

latchedꢀintoꢀtheꢀCCRAꢀregistersꢀandꢀaꢀSTMꢀinterruptꢀgenerated.ꢀIrrespectiveꢀofꢀwhatꢀeventsꢀoccurꢀ

onꢀtheꢀSTPIꢀpinꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀfreeꢀrunꢀuntilꢀtheꢀSTONꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow.ꢀ

WhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀtheꢀcounterꢀwillꢀresetꢀbackꢀtoꢀzero;ꢀinꢀthisꢀwayꢀtheꢀCCRPꢀ

valueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀmaximumꢀcounterꢀvalue.ꢀWhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀ

fromꢀComparatorꢀP,ꢀaꢀSTMꢀinterruptꢀwillꢀalsoꢀbeꢀgenerated.ꢀCountingꢀtheꢀnumberꢀofꢀoverflowꢀ

interruptꢀsignalsꢀfromꢀtheꢀCCRPꢀcanꢀbeꢀaꢀusefulꢀmethodꢀinꢀmeasuringꢀlongꢀpulseꢀwidths.ꢀTheꢀSTIO1ꢀ

andꢀSTIO0ꢀbitsꢀcanꢀselectꢀtheꢀactiveꢀtriggerꢀedgeꢀonꢀtheꢀSTPIꢀpinꢀtoꢀbeꢀaꢀrisingꢀedge,ꢀfallingꢀedgeꢀorꢀ

bothꢀedgeꢀtypes.ꢀIfꢀtheꢀSTIO1ꢀandꢀSTIO0ꢀbitsꢀareꢀbothꢀsetꢀhigh,ꢀthenꢀnoꢀcaptureꢀoperationꢀwillꢀtakeꢀ

placeꢀirrespectiveꢀofꢀwhatꢀhappensꢀonꢀtheꢀSTPIꢀpin,ꢀhoweverꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀcounterꢀwillꢀ

continueꢀtoꢀrun.ꢀTheꢀSTCCLRꢀandꢀSTDPXꢀbitsꢀareꢀnotꢀusedꢀinꢀthisꢀMode.

Rev. 1.10

100

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Coꢀnteꢁ Valꢀe

STM [1:0] = 01

Coꢀnteꢁ cleaꢁed bꢂ

CCRP

Coꢀnteꢁ Coꢀnteꢁ

Stop

Reset

CCRP

YY

Resꢀme

Paꢀse

XX

Time

STON

STPAU

Active

edge

Active

edge

Active

edge

STM captꢀꢁe

pin STPI

CCRA Int.

Flag STMAF

CCRP Int. Flag

STMPF

CCRA

Valꢀe

XX

YY

XX

YY

STIO [1:0]

Valꢀe

00 – Rising edge

01 – Falling edge 10 – Both edges

11 – Disable Captꢀꢁe

Capture Input Mode

Note:ꢀ1.ꢀSTMꢀ[1:0]=01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀSTIOꢀ[1:0]ꢀbits

2.ꢀAꢀSTMꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀtheꢀcounterꢀvalueꢀtoꢀCCRA

3.ꢀSTCCLRꢀbitꢀnotꢀused

4.ꢀNoꢀoutputꢀfunctionꢀ−ꢀSTOCꢀandꢀSTPOLꢀbitsꢀareꢀnotꢀused

5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀ“0”.

Rev. 1.10

101

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Periodic Type TM – PTM

TheꢀPeriodicꢀTypeꢀTMꢀcontainsꢀﬁveꢀoperatingꢀmodes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀTimer/

EventꢀCounter,ꢀCaptureꢀInput,ꢀSingleꢀPulseꢀOutputꢀandꢀPWMꢀOutputꢀmodes.ꢀTheꢀPeriodicꢀTMꢀcanꢀ

beꢀcontrolledꢀwithꢀtwoꢀexternalꢀinputꢀpinsꢀandꢀcanꢀdriveꢀoneꢀorꢀtwoꢀexternalꢀoutputꢀpins.

CCRP

Compaꢁatoꢁ P Match

10-bit Compaꢁatoꢁ P

PTMnPF Inteꢁꢁꢀpt

000

001

010

011

100

101

110

111

f_SYS/ꢃ

f_SYS

PTnOC

b0~b9

f_H/16

f_H/6ꢃ

f_SUB

PTPn

Coꢀnteꢁ Cleaꢁ

0

1

Oꢀtpꢀt

Contꢁol

Polaꢁitꢂ

Contꢁol

10-bit Coꢀnt-ꢀp Coꢀnteꢁ

Contꢁol

PTPnB

f_SUB

PTnON

PTnPAU

PTnCCLR

PTnM1ꢄ PTnM0

PTnIO1ꢄ PTnIO0

PTnPOL

PxSn

b0~b9

Pin Contꢁol

PTCKn

Compaꢁatoꢁ A Match

PTnIO1ꢄ PTnIO0

Edge Detectoꢁ

10-bit Compaꢁatoꢁ A

PTMnAF Inteꢁꢁꢀpt

PxSn

PTnCKꢅ~PTnCK0

PxSn

IFSn

PTnCAPTS

Pin Contꢁol

0

1

PTPnI

CCRA

Note:ꢀTheꢀPTPnBꢀpinꢀonlyꢀexistsꢀwhenꢀn=0.

Periodic Type TM Block Diagram (n=0, 1 or 2)

Periodic TM Operation

TheꢀPeriodicꢀTypeꢀTMꢀcoreꢀisꢀaꢀ10-bitꢀcount-upꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀaꢀuserꢀselectableꢀinternalꢀ

orꢀexternalꢀclockꢀsource.ꢀThereꢀareꢀalsoꢀtwoꢀinternalꢀcomparatorsꢀwithꢀtheꢀnames,ꢀComparatorꢀAꢀ

andꢀComparatorꢀP.ꢀTheseꢀcomparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀwithꢀCCRPꢀandꢀCCRAꢀ

registers.ꢀTheꢀCCRPꢀcomparatorꢀisꢀ10-bitꢀwide.

Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ10-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ

clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀPTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ

automaticallyꢀbyꢀaꢀcounterꢀoverﬂowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ

Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀPTMnꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀPeriodicꢀ

TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ

sourcesꢀincludingꢀanꢀinputꢀpinꢀandꢀcanꢀalsoꢀcontrolꢀmoreꢀthanꢀoneꢀoutputꢀpin.ꢀAllꢀoperatingꢀsetupꢀ

conditionsꢀareꢀselectedꢀusingꢀrelevantꢀinternalꢀregisters.

Periodic Type TM Register Description

OverallꢀoperationꢀofꢀtheꢀPeriodicꢀTypeꢀTMꢀisꢀcontrolledꢀusingꢀaꢀseriesꢀofꢀregisters.ꢀAꢀreadꢀonlyꢀ

registerꢀpairꢀexistsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ10-bitꢀvalue,ꢀwhileꢀtwoꢀread/writeꢀregisterꢀpairsꢀexistꢀ

toꢀstoreꢀtheꢀinternalꢀ10-bitꢀCCRAꢀvalueꢀandꢀCCRPꢀvalue.ꢀTheꢀremainingꢀtwoꢀregistersꢀareꢀcontrolꢀ

registersꢀwhichꢀsetupꢀtheꢀdifferentꢀoperatingꢀandꢀcontrolꢀmodes.

Bit

Register

Name

7

6

5

4

3

2

1

0

PTMnC0

PTMnC1

PTMnDL

PTMnDH

PTMnAL

PTMnAH

PTMnRPL

PTMnRPH

PTnPAU PTnCKꢅ PTnCK1 PTnCK0 PTnON

—

PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCAPTS PTnCCLR

D7

—

D6

—

D5

—

Dꢃ

—

D3

—

Dꢅ

—

D1

D9

D1

D9

D1

D9

D0

Dꢆ

D0

Dꢆ

D0

Dꢆ

D7

—

D6

—

D5

—

Dꢃ

—

D3

—

Dꢅ

—

D7

—

D6

—

D5

—

Dꢃ

—

D3

—

Dꢅ

—

10-bit Periodic TM Register List (n=0, 1 or 2)

Rev. 1.10

10ꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

PTMnC0 Register

Bit

Name

R/W

7

6

5

4

3

PTnON

R/W

0

2

1

0

PTnPAU PTnCKꢅ PTnCK1 PTnCK0

—

R/W

0

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7ꢀ

PTnPAU:ꢀPTMnꢀCounterꢀPauseꢀControl

0:ꢀRun

1:ꢀPause

Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀrestoresꢀ

normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀPTMnꢀwillꢀremainꢀpoweredꢀ

upꢀandꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀ

thisꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀ

changesꢀtoꢀaꢀlowꢀvalueꢀagain.

Bitꢀ6~4

PTnCK2~PTnCK0:ꢀSelectꢀPTMnꢀCounterꢀClock

000:ꢀf_SYS/4

001:ꢀf_SYS

010:ꢀf_H/16

011:ꢀf_H/64

100:ꢀf_SUB

101:ꢀf_SUB

110:ꢀPTCKnꢀrisingꢀedgeꢀclock

111:ꢀPTCKnꢀfallingꢀedgeꢀclock

TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀPTMn.ꢀTheꢀexternalꢀpinꢀ

clockꢀsourceꢀcanꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀ

f_SYSꢀisꢀtheꢀsystemꢀclock,ꢀwhileꢀf_Hꢀandꢀf_SUBꢀareꢀotherꢀinternalꢀclocks,ꢀtheꢀdetailsꢀofꢀwhichꢀ

canꢀbeꢀfoundꢀinꢀtheꢀoscillatorꢀsection.

Bitꢀ3

PTnON:ꢀPTMnꢀCounterꢀOn/OffꢀControl

0:ꢀOff

1:ꢀOn

Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀPTMn.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀ

theꢀcounterꢀtoꢀrun,ꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀPTMn.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀ

stopꢀtheꢀcounterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀPTMnꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀ

consumption.ꢀWhenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀ

willꢀbeꢀresetꢀtoꢀzero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀ

counterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀuntilꢀtheꢀbitꢀreturnsꢀhighꢀagain.ꢀ

IfꢀtheꢀPTMnꢀisꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀPWMꢀoutputꢀModeꢀorꢀSingleꢀ

PulseꢀOutputꢀModeꢀthenꢀtheꢀPTMnꢀoutputꢀpinꢀwillꢀbeꢀresetꢀtoꢀitsꢀinitialꢀcondition,ꢀasꢀ

speciﬁedꢀbyꢀtheꢀPTnOCꢀbit,ꢀwhenꢀtheꢀPTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh.

Bitꢀ2~0ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

Rev. 1.10

103

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

PTMnC1 Register

Bit

Name

R/W

7

PTnM1

R/W

0

6

PTnM0

R/W

0

5

4

3

2

1

0

PTnIO1 PTnIO0

PTnOC PTnPOL PTnCAPTS PTnCCLR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7~6ꢀ

PTnM1~PTnM0:ꢀSelectꢀPTMnꢀOperatingꢀMode

00:ꢀCompareꢀMatchꢀOutputꢀMode

01:ꢀCaptureꢀInputꢀMode

10:ꢀPWMꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode

11:ꢀTimer/CounterꢀMode

TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀPTMn.ꢀToꢀensureꢀreliableꢀ

operationꢀtheꢀPTMnꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀ

PTnM1ꢀandꢀPTnM0ꢀbits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀPTMnꢀoutputꢀpinꢀstateꢀisꢀ

undeﬁned.

Bitꢀ5~4

PTnIO1~PTnIO0:ꢀSelectꢀPTMnꢀExternalꢀPinꢀ(PTPnꢀorꢀPTPnI/PTCKn)ꢀFunction

CompareꢀMatchꢀOutputꢀMode

00:ꢀNoꢀchange

01:ꢀOutputꢀlow

10:ꢀOutputꢀhigh

11:ꢀToggleꢀoutput

PWMꢀOutputꢀMode/SingleꢀPulseꢀOutputꢀMode

00:ꢀPWMꢀOutputꢀinactiveꢀstate

01:ꢀPWMꢀOutputꢀactiveꢀstate

10:ꢀPWMꢀoutput

11:ꢀSingleꢀpulseꢀoutput

CaptureꢀInputꢀMode

00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀPTPnIꢀorꢀPTCKn

01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀPTPnIꢀorꢀPTCKn

10:ꢀInputꢀcaptureꢀatꢀfalling/risingꢀedgeꢀofꢀPTPnIꢀorꢀPTCKn

11:ꢀInputꢀcaptureꢀdisabled

Timer/CounterꢀModeꢀ

Unused

TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀPTMnꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ

certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ

modeꢀtheꢀPTMnꢀisꢀrunning.

InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀ

PTMnꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ

TheꢀPTMnꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ

stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ

zero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀPTMnꢀ

outputꢀpinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀPTnOCꢀbitꢀinꢀtheꢀPTMnC1ꢀregister.ꢀNoteꢀthatꢀ

theꢀoutputꢀlevelꢀrequestedꢀbyꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀ

initialꢀvalueꢀsetupꢀusingꢀtheꢀPTnOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀPTMnꢀ

outputꢀpinꢀwhenꢀaꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀPTMnꢀoutputꢀpinꢀchangesꢀstate,ꢀ

itꢀcanꢀbeꢀresetꢀtoꢀitsꢀinitialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀPTnONꢀbitꢀfromꢀlowꢀtoꢀ

high.

InꢀtheꢀPWMꢀOutputꢀMode,ꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀPTMnꢀ

outputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀ

outputꢀfunctionꢀisꢀmodiﬁedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀonlyꢀchangeꢀ

theꢀvaluesꢀofꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀ

UnpredictableꢀPWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀareꢀchangedꢀ

whenꢀtheꢀPTMnꢀisꢀrunning.

Rev. 1.10

10ꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Bitꢀ3

PTnOC:ꢀPTMnꢀPTPnꢀOutputꢀControlꢀbit

CompareꢀMatchꢀOutputꢀMode

0:ꢀInitialꢀlow

1:ꢀInitialꢀhigh

PWMꢀOutputꢀMode/SingleꢀPulseꢀOutputꢀMode

0:ꢀActiveꢀlow

1:ꢀActiveꢀhigh

ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀPTMnꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ

whetherꢀPTMnꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀ

Mode/SingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀPTMnꢀisꢀinꢀtheꢀTimer/Counterꢀ

Mode.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀPTMnꢀ

outputꢀpinꢀbeforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀModeꢀitꢀdeterminesꢀifꢀtheꢀ

PWMꢀsignalꢀisꢀactiveꢀhighꢀorꢀactiveꢀlow.

Bitꢀ2

PTnPOL:ꢀPTMnꢀPTPnꢀOutputꢀPolarityꢀControl

0:ꢀNon-invert

1:ꢀInvert

ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀPTPnꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀ

PTMnꢀoutputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀeffectꢀ

ifꢀtheꢀPTMnꢀisꢀinꢀtheꢀTimer/CounterꢀMode.

Bitꢀ1

Bitꢀ0

PTnCAPTS:ꢀPTMnꢀCaptureꢀTriggerꢀSourceꢀSelection

0:ꢀFromꢀPTPnIꢀpin

1:ꢀFromꢀPTCKnꢀpin

PTnCCLR:ꢀSelectꢀPTMnꢀCounterꢀClearꢀCondition

0:ꢀPTMnꢀComparatorꢀPꢀmatch

1:ꢀPTMnꢀComparatorꢀAꢀmatch

Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀtheꢀ

PeriodicꢀTMꢀcontainsꢀtwoꢀcomparators,ꢀComparatorꢀAꢀandꢀComparatorꢀP,ꢀeitherꢀofꢀ

whichꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounter.ꢀWithꢀtheꢀPTnCCLRꢀbitꢀsetꢀhigh,ꢀ

theꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ

Whenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀ

theꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀoverﬂow.ꢀAꢀcounterꢀoverﬂowꢀclearingꢀmethodꢀcanꢀ

onlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀbitsꢀareꢀallꢀclearedꢀtoꢀzero.ꢀTheꢀPTnCCLRꢀbitꢀisꢀnotꢀ

usedꢀinꢀtheꢀPWMꢀOutputꢀMode,ꢀSingleꢀPulseꢀOutputꢀorꢀCaptureꢀInputꢀMode.

PTMnDL Register

Bit

7

6

D6

R

5

D5

R

4

Dꢃ

R

3

D3

R

2

Dꢅ

R

1

D1

R

0

D0

R

Name

R/W

D7

R

POR

0

Bitꢀ7~0

D7~D0:ꢀPTMnꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0

PTMnꢀ10-bitꢀCounterꢀbitꢀ7~bitꢀ0

PTMnDH Register

Bit

Name

R/W

7

6

5

4

3

2

1

D9

R

0

Dꢆ

R

—

POR

0

Bitꢀ7~2ꢀ

Bitꢀ1~0

Unimplemented,ꢀreadꢀasꢀ“0”

D9~D8:ꢀPTMnꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ1~bitꢀ0

PTMnꢀ10-bitꢀCounterꢀbitꢀ9~bitꢀ8

Rev. 1.10

105

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

PTMnAL Register

Bit

7

6

D6

R/W

0

5

D5

R/W

0

4

Dꢃ

R/W

0

3

D3

R/W

0

2

Dꢅ

R/W

0

1

D1

R/W

0

D0

R/W

0

Name

R/W

D7

R/W

0

POR

Bitꢀ7~0

D7~D0:ꢀPTMnꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0

PTMnꢀ10-bitꢀCCRAꢀbitꢀ7~bitꢀ0

PTMnAH Register

Bit

Name

R/W

7

6

5

4

3

2

1

D9

R/W

0

Dꢆ

R/W

0

—

POR

Bitꢀ7~2ꢀ

Bitꢀ1~0

Unimplemented,ꢀreadꢀasꢀ“0”

D9~D8:ꢀPTMnꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ1~bitꢀ0

PTMnꢀ10-bitꢀCCRAꢀbitꢀ9~bitꢀ8

PTMnRPL Register

Bit

Name

R/W

7

D7

R/W

0

6

D6

R/W

0

5

D5

R/W

0

4

Dꢃ

R/W

0

3

D3

R/W

0

2

Dꢅ

R/W

0

1

D1

R/W

0

D0

R/W

0

POR

Bitꢀ7~0ꢀ

D7~D0:ꢀPTMnꢀCCRPꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0

PTMnꢀ10-bitꢀCCRPꢀbitꢀ7~bitꢀ0

PTMnRPH Register

Bit

Name

R/W

7

6

5

4

3

2

1

D9

R/W

0

Dꢆ

R/W

0

—

POR

Bitꢀ7~2ꢀ

Bitꢀ1~0

Unimplemented,ꢀreadꢀasꢀ“0”

D9~D8:ꢀPTMnꢀCCRPꢀHighꢀByteꢀRegisterꢀbitꢀ1~bitꢀ0

PTMnꢀ10-bitꢀCCRPꢀbitꢀ9~bitꢀ8

Rev. 1.10

106

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Periodic Type TM Operating Modes

TheꢀPeriodicꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀﬁveꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀMode,ꢀ

PWMꢀOutputꢀMode,ꢀSingleꢀPulseꢀOutputꢀMode,ꢀCaptureꢀInputꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀ

operatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀPTnM1ꢀandꢀPTnM0ꢀbitsꢀinꢀtheꢀPTMnC1ꢀregister.

Compare Output Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀPTnM1ꢀandꢀPTnM0ꢀinꢀtheꢀPTMnC1ꢀregister,ꢀshouldꢀbeꢀsetꢀtoꢀ“00”ꢀ

respectively.ꢀInꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀbyꢀthreeꢀ

methods.ꢀTheseꢀareꢀaꢀcounterꢀoverﬂow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀmatchꢀ

fromꢀComparatorꢀP.ꢀWhenꢀtheꢀPTnCCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀcanꢀbeꢀ

cleared.ꢀOneꢀisꢀwhenꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀCCRPꢀbitsꢀareꢀallꢀ

zeroꢀwhichꢀallowsꢀtheꢀcounterꢀtoꢀoverﬂow.ꢀHereꢀbothꢀPTMnAFꢀandꢀPTMnPFꢀinterruptꢀrequestꢀﬂagsꢀ

forꢀComparatorꢀAꢀandꢀComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.

IfꢀtheꢀPTnCCLRꢀbitꢀinꢀtheꢀPTMnC1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ

matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀPTMnAFꢀinterruptꢀrequestꢀflagꢀwillꢀ

beꢀgeneratedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀ

whenꢀPTnCCLRꢀisꢀhighꢀnoꢀPTMnPFꢀinterruptꢀrequestꢀﬂagꢀwillꢀbeꢀgenerated.ꢀInꢀtheꢀCompareꢀMatchꢀ

OutputꢀMode,ꢀtheꢀCCRAꢀcanꢀnotꢀbeꢀclearedꢀtoꢀ“0”.

IfꢀtheꢀCCRAꢀbitsꢀareꢀallꢀzero,ꢀtheꢀcounterꢀwillꢀoverﬂowꢀwhenꢀitsꢀreachesꢀitsꢀmaximumꢀ10-bit,ꢀ3FFꢀ

Hex,ꢀvalue,ꢀhoweverꢀhereꢀtheꢀPTMnAFꢀinterruptꢀrequestꢀﬂagꢀwillꢀnotꢀbeꢀgenerated.

Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀPTMnꢀoutputꢀpin,ꢀwillꢀchangeꢀ

state.ꢀTheꢀPTMnꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀaꢀPTMnAFꢀinterruptꢀrequestꢀ

ﬂagꢀisꢀgeneratedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀPTMnPFꢀinterruptꢀrequestꢀ

ﬂag,ꢀgeneratedꢀfromꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀeffectꢀonꢀtheꢀPTMnꢀ

outputꢀpin.ꢀTheꢀwayꢀinꢀwhichꢀtheꢀPTMnꢀoutputꢀpinꢀchangesꢀstateꢀareꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀ

theꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀinꢀtheꢀPTMnC1ꢀregister.ꢀTheꢀPTMnꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀ

theꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀtoꢀgoꢀhigh,ꢀtoꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀ

compareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀPTMnꢀoutputꢀpin,ꢀwhichꢀisꢀ

setupꢀafterꢀtheꢀPTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀPTnOCꢀbit.ꢀNoteꢀthatꢀifꢀtheꢀ

PTnIO1ꢀandꢀPTnIO0ꢀbitsꢀareꢀzeroꢀthenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.

Rev. 1.10

107

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Coꢀnteꢁ oveꢁflow

CCRP=0

Coꢀnteꢁ Valꢀe

0x3FF

PTnCCLR = 0; PTnM [1:0] = 00

CCRP > 0

Coꢀnteꢁ cleaꢁed bꢂ CCRP valꢀe

CCRP > 0

Coꢀnteꢁ

Restaꢁt

Resꢀme

Paꢀse

CCRP

CCRA

Stop

Time

PTnON

PTnPAU

PTnPOL

CCRP Int. Flag

PTMnPF

CCRA Int. Flag

PTMnAF

PTMn O/P Pin

Oꢀtpꢀt not affected bꢂ

Oꢀtpꢀt Inveꢁts when

PTnPOL is high

PTMnAF flag. Remains High

ꢀntil ꢁeset bꢂ PTnON bit

Oꢀtpꢀt pin set to

initial Level Low if

PTnOC=0

Oꢀtpꢀt Toggle

with PTMnAF flag

Oꢀtpꢀt Pin

Reset to Initial valꢀe

Oꢀtpꢀt contꢁolled bꢂ otheꢁ

pin-shaꢁed fꢀnction

Heꢁe PTnIO [1:0] = 11

Toggle Oꢀtpꢀt select

Note PTnIO [1:0] = 10

Active High Oꢀtpꢀt select

Compare Match Output Mode – PTnCCLR=0 (n=0, 1 or 2)

Note:ꢀ1.ꢀWithꢀPTnCCLR=0ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter

2.ꢀTheꢀPTMnꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀPTMnAFꢀﬂag

3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀPTnONꢀbitꢀrisingꢀedge

Rev. 1.10

10ꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Coꢀnteꢁ Valꢀe

PTnCCLR = 1; PTnM [1:0] = 00

CCRA = 0

Coꢀnteꢁ oveꢁflow

CCRA > 0 Coꢀnteꢁ cleaꢁed bꢂ CCRA valꢀe

0x3FF

CCRA

CCRP

CCRA=0

Resꢀme

Paꢀse

Stop

Coꢀnteꢁ Restaꢁt

Time

PTnON

PTnPAU

PTnPOL

No PTMnAF flag

geneꢁated on

CCRA oveꢁflow

CCRA Int.

Flag PTMnAF

CCRP Int.

Flag PTMnPF

PTMnPF not

geneꢁated

Oꢀtpꢀt does

not change

PTMn O/P

Oꢀtpꢀt not affected bꢂ

PTMnAF flag. Remains High

ꢀntil ꢁeset bꢂ PTnON bit

Oꢀtpꢀt Inveꢁts

when PTnPOL is high

Oꢀtpꢀt Toggle

with PTMnAF flag

Oꢀtpꢀt pin set to

initial Level Low if

PTnOC=0

Oꢀtpꢀt Pin

Reset to Initial valꢀe

Oꢀtpꢀt contꢁolled bꢂ

otheꢁ pin-shaꢁed fꢀnction

Note PTnIO [1:0] = 10

Active High Oꢀtpꢀt select

Heꢁe PTnIO [1:0] = 11

Toggle Oꢀtpꢀt select

Compare Match Output Mode – PTnCCLR=1 (n=0, 1 or 2)

Note:ꢀ1.ꢀWithꢀPTnCCLR=1ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter

2.ꢀTheꢀPTMnꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀPTMnAFꢀﬂag

3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀPTnONꢀbitꢀrisingꢀedge

4.ꢀAꢀPTMnPFꢀﬂagꢀisꢀnotꢀgeneratedꢀwhenꢀPTnCCLR=1

Rev. 1.10

109

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Timer/Counter Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀPTnM1ꢀandꢀPTnM0ꢀinꢀtheꢀPTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“11”ꢀ

respectively.ꢀTheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀMatchꢀOutputꢀ

Modeꢀgeneratingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/CounterꢀModeꢀtheꢀ

PTMnꢀoutputꢀpinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀCompareꢀ

MatchꢀOutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀPTMnꢀoutputꢀpinꢀisꢀnotꢀusedꢀinꢀ

thisꢀmode,ꢀtheꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunction.

PWM Output Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀPTnM1ꢀandꢀPTnM0ꢀinꢀtheꢀPTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“10”ꢀ

respectively.ꢀTheꢀPWMꢀfunctionꢀwithinꢀtheꢀPTMnꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀ

suchꢀasꢀmotorꢀcontrol,ꢀheatingꢀcontrol,ꢀilluminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀfixedꢀ

frequencyꢀbutꢀofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀPTMnꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀ

generatedꢀwithꢀvaryingꢀequivalentꢀDCꢀRMSꢀvalues.

AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ

waveformꢀisꢀextremelyꢀﬂexible.ꢀInꢀtheꢀPWMꢀOutputꢀMode,ꢀtheꢀPTnCCLRꢀbitꢀhasꢀnoꢀeffectꢀonꢀtheꢀ

PWMꢀoperation.ꢀBothꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀtoꢀgenerateꢀtheꢀPWMꢀwaveform,ꢀ

oneꢀregisterꢀisꢀusedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀandꢀthusꢀcontrolꢀtheꢀPWMꢀwaveformꢀfrequency,ꢀ

whileꢀtheꢀotherꢀoneꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdutyꢀcycle.ꢀTheꢀPWMꢀwaveformꢀfrequencyꢀandꢀdutyꢀcycleꢀ

canꢀthereforeꢀbeꢀcontrolledꢀbyꢀtheꢀvaluesꢀinꢀtheꢀCCRAꢀandꢀCCRPꢀregisters.

Anꢀinterruptꢀﬂag,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRAꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀmatchꢀ

occursꢀfromꢀeitherꢀComparatorꢀAꢀorꢀComparatorꢀP.ꢀTheꢀPTnOCꢀbitꢀinꢀtheꢀPTMnC1ꢀregisterꢀisꢀusedꢀ

toꢀselectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀwaveformꢀwhileꢀtheꢀtwoꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀareꢀ

usedꢀtoꢀenableꢀtheꢀPWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀPTMnꢀoutputꢀpinꢀtoꢀaꢀﬁxedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀ

PTnPOLꢀbitꢀisꢀusedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.

• 10-bit PTMn, PWM Output Mode, Edge-aligned Mode

CCRP

Peꢁiod

Dꢀtꢂ

1~1023

0

1~10ꢅ3

10ꢅꢃ

CCRA

Ifꢀf_SYS=12MHz,ꢀPTMnꢀclockꢀsourceꢀselectꢀf_SYS/4,ꢀCCRP=512ꢀandꢀCCRA=128,ꢀ

TheꢀPTMnꢀPWMꢀoutputꢀfrequency=(f_SYS/4)/512=f_SYS/2048=5.8594kHz,ꢀduty=128/512=25%.ꢀ

IfꢀtheꢀDutyꢀvalueꢀdeﬁnedꢀbyꢀtheꢀCCRAꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀthenꢀtheꢀ

PWMꢀoutputꢀdutyꢀisꢀ100%.ꢀ

Rev. 1.10

110

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Coꢀnteꢁ Valꢀe

PTnM [1:0] = 10

Coꢀnteꢁ cleaꢁed bꢂ

CCRP

Coꢀnteꢁ Reset when

PTnON ꢁetꢀꢁns high

CCRP

CCRA

Coꢀnteꢁ Stop if

PTnON bit low

Paꢀse

Resꢀme

Time

PTnON

PTnPAU

PTnPOL

CCRA Int. Flag

PTMnAF

CCRP Int. Flag

PTMnPF

PTMn O/P Pin

(PTnOC=1)

PTMn O/P Pin

(PTnOC=0)

PWM Dꢀtꢂ Cꢂcle

set bꢂ CCRA

PWM ꢁesꢀmes

opeꢁation

Oꢀtpꢀt contꢁolled bꢂ

otheꢁ pin-shaꢁed fꢀnction

PWM Peꢁiod set bꢂ CCRP

Oꢀtpꢀt Inveꢁts

When PTnPOL = 1

PWM Output Mode (n=0, 1 or 2)

Note:ꢀ1.ꢀCounterꢀclearedꢀbyꢀCCRP

2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod

3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀPTnIO[1:0]=00ꢀorꢀ01

4.ꢀTheꢀPTnCCLRꢀbitꢀhasꢀnoꢀinﬂuenceꢀonꢀPWMꢀoperation

Rev. 1.10

111

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Single Pulse Output Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀPTnM1ꢀandꢀPTnM0ꢀinꢀtheꢀPTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“10”ꢀ

respectivelyꢀandꢀalsoꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ“11”ꢀrespectively.ꢀTheꢀSingleꢀ

PulseꢀOutputꢀMode,ꢀasꢀtheꢀnameꢀsuggests,ꢀwillꢀgenerateꢀaꢀsingleꢀshotꢀpulseꢀonꢀtheꢀPTMnꢀoutputꢀpin.

TheꢀtriggerꢀforꢀtheꢀpulseꢀoutputꢀleadingꢀedgeꢀisꢀaꢀlowꢀtoꢀhighꢀtransitionꢀofꢀtheꢀPTnONꢀbit,ꢀwhichꢀ

canꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogram.ꢀHoweverꢀinꢀtheꢀSingleꢀPulseꢀMode,ꢀtheꢀPTnONꢀ

bitꢀcanꢀalsoꢀbeꢀmadeꢀtoꢀautomaticallyꢀchangeꢀfromꢀlowꢀtoꢀhighꢀusingꢀtheꢀexternalꢀPTCKnꢀpin,ꢀ

whichꢀwillꢀinꢀturnꢀinitiateꢀtheꢀSingleꢀPulseꢀoutput.ꢀWhenꢀtheꢀPTnONꢀbitꢀtransitionsꢀtoꢀaꢀhighꢀlevel,ꢀ

theꢀcounterꢀwillꢀstartꢀrunningꢀandꢀtheꢀpulseꢀleadingꢀedgeꢀwillꢀbeꢀgenerated.ꢀTheꢀPTnONꢀbitꢀshouldꢀ

remainꢀhighꢀwhenꢀtheꢀpulseꢀisꢀinꢀitsꢀactiveꢀstate.ꢀTheꢀgeneratedꢀpulseꢀtrailingꢀedgeꢀwillꢀbeꢀgeneratedꢀ

whenꢀtheꢀPTnONꢀbitꢀisꢀclearedꢀtoꢀ“0”,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogramꢀorꢀ

whenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.

HoweverꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀautomaticallyꢀclearꢀtheꢀPTnONꢀbitꢀandꢀ

thusꢀgenerateꢀtheꢀSingleꢀPulseꢀoutputꢀtrailingꢀedge.ꢀInꢀthisꢀwayꢀtheꢀCCRAꢀvalueꢀcanꢀbeꢀusedꢀtoꢀ

controlꢀtheꢀpulseꢀwidth.ꢀAꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀgenerateꢀaꢀPTMnꢀinterrupt.ꢀ

Theꢀcounterꢀcanꢀonlyꢀbeꢀresetꢀbackꢀtoꢀ“0”ꢀwhenꢀtheꢀPTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhenꢀtheꢀ

counterꢀrestarts.ꢀInꢀtheꢀSingleꢀPulseꢀOutputꢀModeꢀCCRPꢀisꢀnotꢀused.ꢀTheꢀPTnCCLRꢀbitꢀisꢀnotꢀusedꢀ

inꢀthisꢀMode.

CCRA

Leading Edge

Trailing Edge

S/W Command SET "PTnON"

S/W Command CLR "PTnON"

or

CCRA Compare Match

PTnON bit

0 → 1

PTnON bit

1 → 0

or

PTCKn Pin Transition

PTPn Output Pin

Pulse Width = CCRA Value

Single Pulse Generation (n=0, 1 or 2)

Rev. 1.10

11ꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Coꢀnteꢁ Valꢀe

PTnM [1:0] = 10 ; PTnIO [1:0] = 11

Coꢀnteꢁ stopped bꢂ

CCRA

Coꢀnteꢁ Reset when

PTnON ꢁetꢀꢁns high

CCRA

CCRP

Coꢀnteꢁ Stops bꢂ

softwaꢁe

Resꢀme

Paꢀse

Time

PTnON

Aꢀto. set bꢂ

PTCKn pin

Softwaꢁe Cleaꢁed bꢂ

Softwaꢁe

Tꢁiggeꢁ

Softwaꢁe

Cleaꢁ

Softwaꢁe

Tꢁiggeꢁ

Softwaꢁe

Tꢁiggeꢁ

CCRA match

PTCKn pin

PTnPAU

PTCKn pin

Tꢁiggeꢁ

PTnPOL

No CCRP Inteꢁꢁꢀpts

geneꢁated

CCRP Int. Flag

PTMnPF

CCRA Int. Flag

PTMnAF

PTMn O/P Pin

(PTnOC=1)

PTMn O/P Pin

(PTnOC=0)

Oꢀtpꢀt Inveꢁts

when PTnPOL = 1

Pꢀlse Width

set bꢂ CCRA

Single Pulse Output Mode (n=0, 1 or 2)

Note:ꢀ1.ꢀCounterꢀstoppedꢀbyꢀCCRA

2.ꢀCCRPꢀisꢀnotꢀused

3.ꢀTheꢀpulseꢀisꢀtriggeredꢀbyꢀtheꢀPTCKnꢀpinꢀorꢀbyꢀsettingꢀtheꢀPTnONꢀbitꢀhigh

4.ꢀAꢀPTCKnꢀpinꢀactiveꢀedgeꢀwillꢀautomaticallyꢀsetꢀtheꢀPTnONꢀbitꢀhighꢀ

5.ꢀInꢀtheꢀSingleꢀPulseꢀOutputꢀMode,ꢀPTnIO[1:0]ꢀmustꢀbeꢀsetꢀtoꢀ“11”ꢀandꢀcannotꢀbeꢀchanged.ꢀ

Rev. 1.10

113

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Capture Input Mode

ToꢀselectꢀthisꢀmodeꢀbitsꢀPTnM1ꢀandꢀPTnM0ꢀinꢀtheꢀPTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“01”ꢀ

respectively.ꢀThisꢀmodeꢀenablesꢀexternalꢀsignalsꢀtoꢀcaptureꢀandꢀstoreꢀtheꢀpresentꢀvalueꢀofꢀtheꢀinternalꢀ

counterꢀandꢀcanꢀthereforeꢀbeꢀusedꢀforꢀapplicationsꢀsuchꢀasꢀpulseꢀwidthꢀmeasurements.ꢀTheꢀexternalꢀ

signalꢀisꢀsuppliedꢀonꢀtheꢀPTPnIꢀorꢀPTCKnꢀpinꢀwhichꢀisꢀselectedꢀusingꢀtheꢀPTnCAPTSꢀbitꢀinꢀtheꢀ

PTMnC1ꢀregister.ꢀTheꢀinputꢀpinꢀactiveꢀedgeꢀcanꢀbeꢀeitherꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀrisingꢀ

andꢀfallingꢀedges;ꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀusingꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀinꢀ

theꢀPTMnC1ꢀregister.ꢀTheꢀcounterꢀisꢀstartedꢀwhenꢀtheꢀPTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhichꢀisꢀ

initiatedꢀusingꢀtheꢀapplicationꢀprogram.

WhenꢀtheꢀrequiredꢀedgeꢀtransitionꢀappearsꢀonꢀtheꢀPTPnIꢀorꢀPTCKnꢀpinꢀtheꢀpresentꢀvalueꢀinꢀtheꢀ

counterꢀwillꢀbeꢀlatchedꢀintoꢀtheꢀCCRAꢀregistersꢀandꢀaꢀPTMnꢀinterruptꢀgenerated.ꢀIrrespectiveꢀ

ofꢀwhatꢀeventsꢀoccurꢀonꢀtheꢀPTPnIꢀorꢀPTCKnꢀpin,ꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀfreeꢀrunꢀuntilꢀtheꢀ

PTnONꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow.ꢀWhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀtheꢀcounterꢀwillꢀresetꢀ

backꢀtoꢀ“0”;ꢀinꢀthisꢀwayꢀtheꢀCCRPꢀvalueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀmaximumꢀcounterꢀvalue.ꢀWhenꢀaꢀ

CCRPꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀaꢀPTMnꢀinterruptꢀwillꢀalsoꢀbeꢀgenerated.ꢀCountingꢀ

theꢀnumberꢀofꢀoverflowꢀinterruptꢀsignalsꢀfromꢀtheꢀCCRPꢀcanꢀbeꢀaꢀusefulꢀmethodꢀinꢀmeasuringꢀ

longꢀpulseꢀwidths.ꢀTheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀcanꢀselectꢀtheꢀactiveꢀtriggerꢀedgeꢀonꢀtheꢀPTPnIꢀorꢀ

PTCKnꢀpinꢀtoꢀbeꢀaꢀrisingꢀedge,ꢀfallingꢀedgeꢀorꢀbothꢀedgeꢀtypes.ꢀIfꢀtheꢀPTnIO1ꢀandꢀPTnIO0ꢀbitsꢀareꢀ

bothꢀsetꢀhigh,ꢀthenꢀnoꢀcaptureꢀoperationꢀwillꢀtakeꢀplaceꢀirrespectiveꢀofꢀwhatꢀhappensꢀonꢀtheꢀPTPnIꢀorꢀ

PTCKnꢀpin,ꢀhoweverꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀrun.

AsꢀtheꢀPTPnIꢀorꢀPTCKnꢀpinꢀisꢀpinꢀsharedꢀwithꢀotherꢀfunctions,ꢀcareꢀmustꢀbeꢀtakenꢀifꢀtheꢀPTMnꢀisꢀinꢀ

theꢀCaptureꢀInputꢀMode.ꢀThisꢀisꢀbecauseꢀifꢀtheꢀpinꢀisꢀsetupꢀasꢀanꢀoutput,ꢀthenꢀanyꢀtransitionsꢀonꢀthisꢀ

pinꢀmayꢀcauseꢀanꢀinputꢀcaptureꢀoperationꢀtoꢀbeꢀexecuted.ꢀTheꢀPTnCCLR,ꢀPTnOCꢀandꢀPTnPOLꢀbitsꢀ

areꢀnotꢀusedꢀinꢀthisꢀMode.

Rev. 1.10

11ꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Coꢀnteꢁ Valꢀe

PTnM[1:0] = 01

Coꢀnteꢁ cleaꢁed bꢂ

CCRP

Coꢀnteꢁ

Stop

Coꢀnteꢁ

Reset

CCRP

YY

Resꢀme

Paꢀse

XX

Time

PTnON

PTnPAU

Active

edge

Active

edge

Active edge

PTMn Captꢀꢁe Pin

PTPnI oꢁ PTCKn

CCRA Int.

Flag PTMnAF

CCRP Int.

Flag PTMnPF

XX

YY

XX

YY

CCRA Valꢀe

00 - Rising edge

01 - Falling edge

10 - Both edges

11 - Disable Captꢀꢁe

PTnIO [1:0] Valꢀe

Capture Input Mode (n=0, 1 or 2)

Note:ꢀ1.ꢀPTnM[1:0]=01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀPTnIO[1:0]ꢀbits

2.ꢀAꢀPTMnꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀtheꢀcounterꢀvalueꢀtoꢀCCRA

3.ꢀPTnCCLRꢀbitꢀnotꢀused

4.ꢀNoꢀoutputꢀfunctionꢀ–ꢀPTnOCꢀandꢀPTnPOLꢀbitsꢀareꢀnotꢀusedꢀ

5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀ“0”.

Rev. 1.10

115

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Analog to Digital Converter – ADC

Theꢀneedꢀtoꢀinterfaceꢀtoꢀrealꢀworldꢀanalogꢀsignalsꢀisꢀaꢀcommonꢀrequirementꢀforꢀmanyꢀelectronicꢀ

systems.ꢀHowever,ꢀtoꢀproperlyꢀprocessꢀtheseꢀsignalsꢀbyꢀaꢀmicrocontroller,ꢀtheyꢀmustꢀfirstꢀbeꢀ

convertedꢀintoꢀdigitalꢀsignalsꢀbyꢀA/Dꢀconverters.ꢀByꢀintegratingꢀtheꢀA/Dꢀconversionꢀelectronicꢀ

circuitryꢀintoꢀtheꢀmicrocontroller,ꢀtheꢀneedꢀforꢀexternalꢀcomponentsꢀisꢀreducedꢀsigniﬁcantlyꢀwithꢀtheꢀ

correspondingꢀfollow-onꢀbeneﬁtsꢀofꢀlowerꢀcostsꢀandꢀreducedꢀcomponentꢀspaceꢀrequirements.

A/D Overview

Eachꢀdeviceꢀcontainsꢀaꢀhighꢀaccuracyꢀmulti-channelꢀ24-bitꢀDeltaꢀSigmaꢀAnalog-to-DigitalꢀConverterꢀ

whichꢀcanꢀdirectlyꢀinterfaceꢀtoꢀexternalꢀanalogꢀsignals,ꢀsuchꢀasꢀthatꢀfromꢀsensorsꢀorꢀotherꢀcontrolꢀ

signalsꢀandꢀconvertꢀtheseꢀsignalsꢀdirectlyꢀintoꢀaꢀ24-bitꢀdigitalꢀvalue.

Inꢀaddition,ꢀtheꢀPGAꢀgainꢀcontrol,ꢀA/DꢀconverterꢀgainꢀcontrolꢀandꢀA/Dꢀconverterꢀreferenceꢀgainꢀ

controlꢀdetermineꢀtheꢀamplificationꢀgainꢀforꢀA/Dꢀconverterꢀinputꢀsignal.ꢀTheꢀdesignerꢀcanꢀselectꢀ

theꢀbestꢀgainꢀcombinationꢀforꢀtheꢀdesiredꢀampliﬁcationꢀappliedꢀtoꢀtheꢀinputꢀsignal.ꢀTheꢀfollowingꢀ

blockꢀdiagramꢀillustratesꢀtheꢀA/Dꢀconverterꢀbasicꢀoperationalꢀfunction.ꢀTheꢀA/Dꢀconverterꢀinputꢀ

channelꢀcanꢀbeꢀarrangedꢀasꢀfourꢀsingle-endedꢀA/Dꢀinputꢀchannelsꢀorꢀtwoꢀdifferentialꢀinputꢀchannels.ꢀ

TheꢀinputꢀsignalꢀcanꢀbeꢀampliﬁedꢀbyꢀPGAꢀbeforeꢀenteringꢀtheꢀ24-bitꢀDeltaꢀSigmaꢀA/Dꢀconverter.ꢀ

TheꢀDeltaꢀSigmaꢀA/DꢀconverterꢀmodulatorꢀwillꢀoutputꢀoneꢀbitꢀconvertedꢀdataꢀtoꢀSINCꢀﬁlterꢀwhichꢀ

canꢀtransformꢀtheꢀconvertedꢀone-bitꢀdataꢀtoꢀ24ꢀbitsꢀandꢀstoreꢀthemꢀintoꢀtheꢀspeciﬁcꢀdataꢀregisters.ꢀ

Additionally,ꢀtheꢀdevicesꢀalsoꢀprovideꢀaꢀtemperatureꢀsensorꢀtoꢀcompensateꢀtheꢀA/Dꢀconverterꢀ

deviationꢀcausedꢀbyꢀtheꢀtemperature.ꢀWithꢀhighꢀaccuracyꢀandꢀperformance,ꢀtheꢀdevicesꢀareꢀveryꢀ

suitableꢀforꢀtheꢀWeightꢀScaleꢀrelatedꢀproducts.

Internal Power Supply

EachꢀdeviceꢀcontainsꢀanꢀLDOꢀandꢀVCMꢀforꢀtheꢀregulatedꢀpowerꢀsupply.ꢀTheꢀaccompanyingꢀblockꢀ

diagramꢀillustratesꢀtheꢀbasicꢀfunctionalꢀoperation.ꢀTheꢀinternalꢀLDOꢀcanꢀprovideꢀtheꢀﬁxedꢀvoltageꢀ

forꢀPGA,ꢀA/Dꢀconverterꢀorꢀtheꢀexternalꢀcomponents;ꢀasꢀwellꢀtheꢀV_CMꢀcanꢀbeꢀusedꢀasꢀtheꢀreferenceꢀ

voltageꢀforꢀA/Dꢀconverterꢀmodule.ꢀThereꢀareꢀfourꢀLDOꢀvoltageꢀlevels,ꢀ2.4V,ꢀ2.6V,ꢀ2.9Vꢀorꢀ3.3V,ꢀ

decidedꢀbyꢀLDOVS1~LDOVS0ꢀbitsꢀinꢀtheꢀPWRCꢀregister,ꢀasꢀwellꢀtheꢀVCMꢀvoltageꢀisꢀﬁxedꢀatꢀ1.25V.ꢀ

TheꢀLDOꢀandꢀVCMꢀfunctionsꢀcanꢀbeꢀcontrolledꢀbyꢀtheꢀLDOENꢀbitꢀandꢀcanꢀbeꢀpoweredꢀoffꢀtoꢀreduceꢀ

theꢀpowerꢀconsumption.ꢀIfꢀtheꢀVCMꢀisꢀdisabled,ꢀtheꢀVCMꢀoutputꢀpinꢀisꢀﬂoating.ꢀ

LDO

VIN

VOREG

(Sꢀpplꢂ voltage foꢁ

A/D conveꢁteꢁ & PGA)

ꢅ.ꢃV

ꢅ.6V

ꢅ.9V

3.3V

LDOEN

LDOBPS

LDOVS[1:0]

VCM

1.ꢅ5V

VCM

ADOFF

(Common mode voltage foꢁ

A/D conveꢁteꢁ & D/A conveꢁteꢁ)

Internal Power Supply Block Diagram

Rev. 1.10

116

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Register bits

Output Voltage

ADOFF

LDOEN

Bandgap

Off

VOREG

Disable

Enable

Disable

Enable

VCM

1

0

1

0

1

Disable

Enable

On

Power Control Table

PWRC Register

Bit

Name

R/W

7

LDOEN

R/W

0

6

5

4

3

2

1

0

—

LDOBPS LDOVS1 LDOVS0

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7

LDOEN:ꢀLDOꢀfunctionꢀcontrolꢀbit

0:ꢀDisable

1:ꢀEnable

IfꢀtheꢀLDOꢀisꢀdisabled,ꢀthereꢀwillꢀbeꢀnoꢀpowerꢀconsumptionꢀandꢀLDOꢀoutputꢀwillꢀbeꢀinꢀ

aꢀlowꢀlevelꢀbyꢀaꢀweaklyꢀpull-lowꢀresistor.

Bitꢀ6~3ꢀ

Bitꢀ2

Unimplemented,ꢀreadꢀasꢀ“0”

LDOBPS:ꢀLDOꢀBypassꢀfunctionꢀcontrolꢀbit

0:ꢀDisable

1:ꢀEnable

Bitꢀ1~0

LDOVS1~LDOVS0:ꢀLDOꢀoutputꢀvoltageꢀselection

00:ꢀ2.4V

01:ꢀ2.6V

10:ꢀ2.9V

11:ꢀ3.3V

A/D Data Rate Deﬁnition

TheꢀDeltaꢀSigmaꢀA/Dꢀconverterꢀdataꢀrateꢀcanꢀbeꢀcalculatedꢀusingꢀtheꢀfollowingꢀequation:

f_ADCKf_MCLK/N f_MCLK

CHOP OSR CHOP OSR NCHOP OSR

Data Rate 



f_ADCK:ꢀA/Dꢀclockꢀinput,ꢀderivedꢀfromꢀf_MCLK/N

f_MCLK:ꢀA/Dꢀclockꢀsource,ꢀderivedꢀfromꢀf_SYSꢀorꢀf_SYS/2/(ADCK+1)ꢀusingꢀtheꢀADCKꢀbitꢀﬁeld.

N:ꢀaꢀconstantꢀdividedꢀfactorꢀthatꢀcanꢀbeꢀequalꢀtoꢀ30ꢀorꢀ12ꢀdeterminedꢀbyꢀtheꢀFLMSꢀbitꢀﬁeld.

CHOP:ꢀSamplingꢀdataꢀamountꢀdoublingꢀfunctionꢀcontrolꢀandꢀcanꢀbeꢀequalꢀtoꢀ2ꢀorꢀ1ꢀdeterminedꢀbyꢀ

theꢀFLMSꢀbitꢀﬁeld.

OSR:ꢀOversamplingꢀrateꢀdeterminedꢀbyꢀtheꢀADORꢀﬁeld.

Forꢀexample ifꢀaꢀdataꢀrateꢀofꢀ8Hzꢀisꢀdesired anꢀf_MCLKꢀclockꢀsourceꢀwithꢀaꢀfrequencyꢀofꢀ4MHzꢀ

，

A/Dꢀconverterꢀcanꢀbeꢀselected.ꢀThenꢀsetꢀtheꢀFLMSꢀﬁeldꢀtoꢀ“000”ꢀtoꢀobtainꢀanꢀ“N”ꢀequalꢀtoꢀ30ꢀandꢀ

“CHOP”ꢀequalꢀtoꢀ2.ꢀFinally,ꢀsetꢀtheꢀADORꢀﬁeldꢀtoꢀ“001”ꢀtoꢀselectꢀanꢀoversamplingꢀrateꢀequalꢀtoꢀ

8192.ꢀTherefore,ꢀtheꢀDataꢀRateꢀ=ꢀ4MHzꢀ/ꢀ(30ꢀ×ꢀ2ꢀ×ꢀ8192)ꢀ=ꢀ8Hz.

NoteꢀthatꢀtheꢀA/DꢀconverterꢀhasꢀaꢀnotchꢀrejectionꢀfunctionꢀforꢀanꢀACꢀpowerꢀsupplyꢀwithꢀaꢀfrequencyꢀ

ofꢀ50Hzꢀorꢀ60Hzꢀwhenꢀtheꢀdataꢀrateꢀisꢀequalꢀtoꢀ10Hz.

Rev. 1.10

117

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

ADCK[4:0]

f_SYS

f_MCLK

CHSP[3:0]

Divider

AN0

AN2

AGS[1:0]

DCSET[2:0]

ADOFF

ADSLP

ADOFF ADRST

IN1

RFC

V_CM

V_TSOP

ADGN = x1, x2, x4, x8

A/D Converter

Interrupt

PGAOP

PGA

EOC

24

DI+

f_ADCK

24-bit ∆-Σ

A/D Converter

PGAGN=x1, x2, x4, x8,

x16, x32, x64, x128

INX

V_CM

SINC Filter

INIS

ADRH

ADRM

ADRL

DI−

INX[1:0]

PGAON

AN1

AN3

VREFGN = x1, x1/2, x1/4

REFN

ADCDL

REFP

IN2

V_CM

V_TSON

PGS[2:0]

VGS[1:0]

ADOR[2:0]

VRBUFN

FLMS[2:0]

VIN V_CMV_OREG

VRBUFP

CHSN[3:0]

DSDACVRS[1:0]

VREFS

VRP

0

VRN

1

0

V_DACO

12-bit

DSDAC[11:0]

D/A Converter

V_CM

AV_SS

VREFP

VREFN

DSDACEN

A/D Converter Structure

A/D Converter Register Description

OverallꢀoperationꢀofꢀtheꢀA/Dꢀconverterꢀisꢀcontrolledꢀbyꢀusingꢀ13ꢀregisters.ꢀThreeꢀreadꢀonlyꢀregistersꢀ

existꢀtoꢀstoreꢀtheꢀA/Dꢀconverterꢀdataꢀ24-bitꢀvalue.ꢀAꢀcontrolꢀregisterꢀnamedꢀasꢀPWRCꢀisꢀusedꢀtoꢀcontrolꢀ

theꢀrequiredꢀbiasꢀandꢀsupplyꢀvoltagesꢀforꢀPGAꢀandꢀA/Dꢀconverterꢀandꢀisꢀdescribedꢀinꢀtheꢀ“Internalꢀ

PowerꢀSupply”ꢀsection.ꢀThreeꢀregistersꢀareꢀD/Aꢀconverterꢀcontrolꢀregisters.ꢀTheꢀremainingꢀ6ꢀregistersꢀ

areꢀcontrolꢀregistersꢀwhichꢀsetꢀupꢀtheꢀgainꢀselectionsꢀandꢀcontrolꢀfunctionsꢀofꢀtheꢀA/Dꢀconverter.

Bit

Register

Name

7

—

6

VGS1

INIS

CHSNꢅ

D6

5

VGS0

INX1

4

3

2

1

0

PGS0

—

PGAC0

PGAC1

PGACS

ADRL

AGS1

INX0

CHSN0

Dꢃ

AGS0

PGSꢅ

PGS1

—

DCSETꢅ DCSET1 DCSET0

CHSN3

D7

CHSN1

D5

CHSP3

D3

CHSPꢅ

Dꢅ

CHSP1 CHSP0

D1

D9

D0

Dꢆ

ADRM

D15

Dꢅ3

ADRST

FLMSꢅ

—

D1ꢃ

D13

D1ꢅ

D11

D10

ADRH

Dꢅꢅ

Dꢅ1

Dꢅ0

D19

D1ꢆ

D17

—

D16

VREFS

—

ADCR0

ADCR1

ADCS

ADSLP

FLMS1

—

ADOFF

FLMS0

—

ADORꢅ

ADOR1 ADOR0

VRBUFN VRBUFP ADCDL

EOC

ADCKꢃ

Dꢆ

ADCK3

D7

ADCKꢅ

D6

ADCK1 ADCK0

DSDAH

DSDAL

DSDACC

D11

—

D10

D9

D5

D1

—

Dꢃ

D0

—

D3

Dꢅ

DSDACEN DSDACVRS1

DSDACVRS0

—

A/D Converter Register List

Rev. 1.10

11ꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Programmable Gain Ampliﬁer – PGA

Thereꢀareꢀthreeꢀregistersꢀrelatedꢀtoꢀtheꢀprogrammableꢀgainꢀcontrol,ꢀPGAC0,ꢀPGAC1ꢀandꢀPGACS.ꢀ

TheꢀPGAC0ꢀresisterꢀisꢀusedꢀtoꢀselectꢀtheꢀPGAꢀgain,ꢀA/DꢀconverterꢀgainꢀandꢀtheꢀA/Dꢀconverterꢀ

referenceꢀgain.ꢀAsꢀwell,ꢀtheꢀPGAC1ꢀregisterꢀisꢀusedꢀtoꢀdeﬁneꢀtheꢀinputꢀconnectionꢀandꢀdifferentialꢀ

inputꢀoffsetꢀvoltageꢀadjustmentꢀcontrol.ꢀInꢀaddition,ꢀTheꢀPGACSꢀregisterꢀisꢀusedꢀtoꢀselectꢀtheꢀ

inputꢀendsꢀforꢀtheꢀPGA.ꢀTherefore,ꢀtheꢀinputꢀchannelsꢀhaveꢀtoꢀbeꢀdeterminedꢀbyꢀtheꢀCHSP[3:0]ꢀ

andꢀCHSN[3:0]ꢀbitsꢀtoꢀdetermineꢀwhichꢀanalogꢀchannelꢀinputꢀpins,ꢀtemperatureꢀdetectorꢀinputsꢀorꢀ

internalꢀpowerꢀsupplyꢀareꢀactuallyꢀconnectedꢀtoꢀtheꢀinternalꢀdifferentialꢀA/Dꢀconverter.

PGAC0 Register

Bit

Name

R/W

7

6

VGS1

R/W

0

5

VGS0

R/W

0

4

AGS1

R/W

0

3

AGS0

R/W

0

2

PGSꢅ

R/W

0

1

PGS1

R/W

0

PGS0

R/W

0

—

POR

Bitꢀ7ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

Bitꢀ6~5

VGS1~VGS0:ꢀREFP/REFNꢀDifferentialꢀReferenceꢀVoltageꢀGainꢀSelection

00:ꢀVREFGN=1

01:ꢀVREFGN=1/2

10:ꢀVREFGN=1/4

11:ꢀReserved

Bitꢀ4~3

AGS1~AGS0:ꢀA/DꢀConverterꢀPGAOP/PGAONꢀDifferentialꢀInputꢀSignalꢀGainꢀ

Selection

00:ꢀADGN=1

01:ꢀADGN=2

10:ꢀADGN=4

11:ꢀADGN=8

Bitꢀ2~0

PGS2~PGS0:ꢀPGAꢀDI+/DI-ꢀDifferentialꢀChannelꢀInputꢀGainꢀSelection

000:ꢀPGAGN=1

001:ꢀPGAGN=2

010:ꢀPGAGN=4

011:ꢀPGAGN=8

100:ꢀPGAGN=16

101:ꢀPGAGN=32

110:ꢀPGAGN=64

111:ꢀPGAGN=128

Rev. 1.10

119

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

PGAC1 Register

Bit

Name

R/W

7

6

5

INX1

R/W

0

4

INX0

R/W

0

3

2

1

0

—

INIS

R/W

0

DCSETꢅ DCSET1 DCSET0

—

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7ꢀ

Bitꢀ6

Unimplemented,ꢀreadꢀasꢀ“0”

INIS:ꢀTheꢀSelectedꢀInputꢀEnds,ꢀIN1ꢀandꢀIN2ꢀInternalꢀConnectionꢀControlꢀBit

0:ꢀNotꢀconnected

1:ꢀConnected

Bitꢀ5~4

Bitꢀ3~1

INX1, INX0:ꢀTheꢀSelectedꢀInputꢀEnds,ꢀIN1/IN2ꢀandꢀtheꢀPGAꢀDifferentialꢀInputꢀEnds,ꢀ

DI+/DI-ꢀConnectionꢀControlꢀBits

INX[1,0]=00

INX[1,0]=01

INX[1,0]=10

INX[1,0]=11

IN1

INꢅ

DI+

DI-

IN1

INꢅ

DI+

DI-

IN1

INꢅ

DI+

DI-

IN1

INꢅ

DI+

DI-

DCSET2~DCSET0:ꢀDifferentialꢀInputꢀSignalꢀPGAOP/PGAONꢀOffsetꢀSelection

000:ꢀDCSETꢀ=ꢀ+0V

001:ꢀDCSETꢀ=ꢀ+0.25×ΔVR_I

010:ꢀDCSETꢀ=ꢀ+0.5×ΔVR_I

011:ꢀDCSETꢀ=ꢀ+0.75×ΔVR_I

100:ꢀDCSETꢀ=ꢀ+0V

101:ꢀDCSETꢀ=ꢀ-0.25×ΔVR_I

110:ꢀDCSETꢀ=ꢀ-0.5×ΔVR_I

111:ꢀDCSETꢀ=ꢀ-0.75×ΔVR_I

Theꢀvoltage,ꢀΔVR_I,ꢀisꢀtheꢀdifferentialꢀreferenceꢀvoltageꢀwhichꢀisꢀampliﬁedꢀbyꢀspeciﬁcꢀ

gainꢀselectionꢀbasedꢀonꢀtheꢀselectedꢀinputs.

Bitꢀ0ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

Rev. 1.10

1ꢅ0

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

PGACS Register

Bit

Name

R/W

7

CHSN3

R/W

0

6

CHSNꢅ

R/W

0

5

CHSN1

R/W

0

4

CHSN0

R/W

0

3

CHSP3

R/W

0

2

CHSPꢅ

R/W

0

1

CHSP1

R/W

0

CHSP0

R/W

0

POR

Bitꢀ7~4

CHSN3~CHSN0:ꢀNegativeꢀInputꢀEndꢀIN2ꢀSelection

0000:ꢀAN1

0001:ꢀAN3

0010:ꢀReserved

0011:ꢀReserved

0100:ꢀReserved

0101:ꢀV_DACO

0110:ꢀV_CM

0111:ꢀTemperatureꢀsensorꢀoutputꢀ–ꢀV_TSON

1xxx:ꢀReserved

Theseꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀnegativeꢀinput,ꢀIN2.ꢀIfꢀtheꢀIN2ꢀinputꢀisꢀselectedꢀasꢀ

aꢀsingleꢀendꢀinput,ꢀtheꢀV_CMꢀvoltageꢀmustꢀbeꢀselectedꢀasꢀtheꢀpositiveꢀinputꢀonꢀIN1ꢀforꢀ

singleꢀendꢀinputꢀapplications.ꢀItꢀisꢀrecommendedꢀthatꢀwhenꢀtheꢀV_TSONꢀsignalꢀisꢀselectedꢀ

asꢀtheꢀnegativeꢀinput,ꢀtheꢀV_TSOPꢀsignalꢀshouldꢀbeꢀselectedꢀasꢀtheꢀpositiveꢀinputꢀforꢀ

properꢀoperations.

Bitꢀ3~0

CHSP3~CHSP0:ꢀPositiveꢀInputꢀEndꢀIN1Selection

0000:ꢀAN0

0001:ꢀAN2

0010:ꢀReserved

0011:ꢀReserved

0100:ꢀReserved

0101:ꢀV_DACO

0110:ꢀV_CM

ꢀ

0111:ꢀTemperatureꢀsensorꢀoutputꢀ–ꢀV_TSOP

1xxx:ꢀRFC

Theseꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀpositiveꢀinput,ꢀIN1.ꢀIfꢀtheꢀIN1ꢀinputꢀisꢀselectedꢀasꢀaꢀ

singleꢀendꢀinput,ꢀtheꢀV_CMꢀvoltageꢀmustꢀbeꢀselectedꢀasꢀtheꢀnegativeꢀinputꢀonꢀIN2ꢀforꢀ

singleꢀendꢀinputꢀapplications.ꢀItꢀisꢀrecommendedꢀthatꢀwhenꢀtheꢀV_TSOPꢀsignalꢀisꢀselectedꢀ

asꢀtheꢀpositiveꢀinput,ꢀtheꢀV_TSONꢀsignalꢀshouldꢀbeꢀselectedꢀasꢀtheꢀnegativeꢀinputꢀforꢀ

properꢀoperations

Rev. 1.10

1ꢅ1

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

D/A Converter Registers – DSDAH, DSDAL, DSDACC

ThereꢀareꢀthreeꢀregistersꢀrelatedꢀtoꢀtheꢀD/Aꢀconverterꢀoutputꢀcontrol.ꢀ

• DSDAH Register

Bit

Name

R/W

7

6

5

D9

R/W

0

4

Dꢆ

R/W

0

3

D7

R/W

0

2

D6

R/W

0

1

D5

R/W

0

Dꢃ

R/W

0

D11

R/W

0

D10

R/W

0

POR

Bitꢀ7~0

D11~D4:ꢀD/AꢀConverterꢀOutputꢀControlꢀCode,ꢀOnlyꢀforꢀ12ꢀbitsꢀD/AꢀConverter

• DSDAL Register

Bit

Name

R/W

7

6

5

4

3

D3

R/W

0

2

Dꢅ

R/W

0

1

D1

R/W

0

D0

R/W

0

—

POR

Bitꢀ7~4ꢀ

Bitꢀ3~0

Unimplemented,ꢀreadꢀasꢀ“0”

D3~D0:ꢀD/AꢀConverterꢀOutputꢀControlꢀCode

Note:ꢀwritingꢀthisꢀregisterꢀonlyꢀwritesꢀtoꢀshadowꢀbuffer,ꢀandꢀuntilꢀwriteꢀDSDAHꢀ

registerꢀwillꢀalsoꢀcopyꢀtheꢀshadowꢀbufferꢀdataꢀtoꢀDSDALꢀregister.

• DSDACC Register

Bit

Name

R/W

7

6

5

4

3

2

1

0

DSDACEN DSDACVRS1 DSDACVRS0

—

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7

DSDACEN:ꢀD/AꢀConverterꢀEnableꢀorꢀDisableꢀControlꢀBit

0:ꢀDisable

1:ꢀEnable

Bitꢀ6~5

Bitꢀ4~0ꢀ

DSDACVRS1~DSDACVRS0:ꢀD/AꢀConverterꢀReferenceꢀVoltageꢀSelection

00:ꢀD/AꢀconverterꢀreferenceꢀvoltageꢀcomesꢀfromꢀV_OREG

01:ꢀD/AꢀconverterꢀreferenceꢀvoltageꢀcomesꢀfromꢀV_IN

1x:ꢀD/AꢀconverterꢀreferenceꢀvoltageꢀcomesꢀfromꢀV_CM

Unimplemented,ꢀreadꢀasꢀ“0”

Rev. 1.10

1ꢅꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

A/D Converter Data Registers – ADRL, ADRM, ADRH

Eachꢀdeviceꢀcontainsꢀanꢀinternalꢀ24-bitꢀDeltaꢀSigmaꢀA/DꢀConverter,ꢀitꢀrequiresꢀthreeꢀdataꢀregistersꢀ

toꢀstoreꢀtheꢀconvertedꢀvalue.ꢀTheseꢀareꢀaꢀhighꢀbyteꢀregister,ꢀknownꢀasꢀADRH,ꢀaꢀmiddleꢀbyteꢀregister,ꢀ

knownꢀasꢀADRM,ꢀandꢀaꢀlowꢀbyteꢀregister,ꢀknownꢀasꢀADRL.ꢀAfterꢀtheꢀconversionꢀprocessꢀtakesꢀ

place,ꢀtheseꢀregistersꢀcanꢀbeꢀdirectlyꢀreadꢀbyꢀtheꢀmicrocontrollerꢀtoꢀobtainꢀtheꢀdigitisedꢀconversionꢀ

value.ꢀD0~D23ꢀareꢀtheꢀA/Dꢀconversionꢀresultꢀdataꢀbits.

• ADRL Register

Bit

Name

R/W

7

D7

R

6

D6

R

5

D5

R

4

Dꢃ

R

3

D3

R

2

Dꢅ

R

1

D1

R

0

D0

R

POR

x

“x” ꢀnknown

Bitꢀ7~0

D7~D0:ꢀA/DꢀConversionꢀDataꢀRegisterꢀbitꢀ7~bitꢀ0

• ADRM Register

Bit

Name

R/W

7

D15

R

6

D1ꢃ

R

5

D13

R

4

D1ꢅ

R

3

D11

R

2

D10

R

1

D9

R

0

Dꢆ

R

POR

x

“x” ꢀnknown

Bitꢀ7~0

D15~D8:ꢀA/DꢀConversionꢀDataꢀRegisterꢀbitꢀ15~bitꢀ8

• ADRH Register

Bit

Name

R/W

7

Dꢅ3

R

6

Dꢅꢅ

R

5

Dꢅ1

R

4

Dꢅ0

R

3

D19

R

2

D1ꢆ

R

1

D17

R

0

D16

R

POR

x

“x” ꢀnknown

Bitꢀ7~0

D23~D16:ꢀA/DꢀConversionꢀDataꢀRegisterꢀbitꢀ23~bitꢀ16

Rev. 1.10

1ꢅ3

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

A/D Converter Control Registers − ADCR0, ADCR1, ADCS

ToꢀcontrolꢀtheꢀfunctionꢀandꢀoperationꢀofꢀtheꢀA/Dꢀconverter,ꢀthreeꢀcontrolꢀregistersꢀknownꢀasꢀADCR0,ꢀ

ADCR1ꢀandꢀADCSꢀareꢀprovided.ꢀTheseꢀ8-bitꢀregistersꢀdefineꢀfunctionsꢀsuchꢀasꢀtheꢀselectionꢀofꢀ

whichꢀreferenceꢀsourceꢀisꢀusedꢀforꢀtheꢀinternalꢀA/Dꢀconverter,ꢀtheꢀA/Dꢀconverterꢀclockꢀsource,ꢀtheꢀ

A/Dꢀconverterꢀoutputꢀdataꢀrateꢀasꢀwellꢀasꢀcontrollingꢀtheꢀpower-upꢀfunctionꢀandꢀmonitoringꢀtheꢀA/Dꢀ

converterꢀendꢀofꢀconversionꢀstatus.ꢀ

• ADCR0 Register

Bit

Name

R/W

7

ADRST

R/W

0

6

ADSLP

R/W

0

5

ADOFF

R/W

1

4

ADORꢅ

R/W

0

3

ADOR1

R/W

0

2

ADOR0

R/W

0

1

0

VREFS

R/W

0

—

POR

Bitꢀ7ꢀ

ADRST:ꢀA/DꢀConverterꢀSoftwareꢀResetꢀControlꢀbit.

0:ꢀDisable

1:ꢀEnable

ThisꢀbitꢀisꢀusedꢀtoꢀresetꢀtheꢀA/DꢀconverterꢀinternalꢀdigitalꢀSINCꢀﬁlter.ꢀThisꢀbitꢀisꢀsetꢀ

lowꢀforꢀA/Dꢀnormalꢀoperations.ꢀHowever,ꢀifꢀsetꢀhigh,ꢀtheꢀinternalꢀdigitalꢀSINCꢀﬁlterꢀ

willꢀbeꢀresetꢀandꢀtheꢀcurrentꢀA/Dꢀconvertedꢀdataꢀwillꢀbeꢀaborted.ꢀAꢀnewꢀA/Dꢀdataꢀ

conversionꢀprocessꢀwillꢀnotꢀbeꢀinitiatedꢀuntilꢀthisꢀbitꢀisꢀsetꢀlowꢀagain.

Bitꢀ6

ADSLP:ꢀA/DꢀConverterꢀSleepꢀModeꢀControlꢀbit

0:ꢀNormalꢀmode

1:ꢀSleepꢀmode

ThisꢀbitꢀisꢀusedꢀtoꢀdetermineꢀwhetherꢀtheꢀA/Dꢀconverterꢀentersꢀtheꢀsleepꢀmodeꢀorꢀ

notꢀwhenꢀtheꢀA/DꢀconverterꢀisꢀpoweredꢀonꢀbyꢀsettingꢀtheꢀADOFFꢀbitꢀlow.ꢀWhenꢀtheꢀ

A/DꢀconverterꢀisꢀpoweredꢀonꢀandꢀtheꢀADSLPꢀbitꢀisꢀlow,ꢀtheꢀA/Dꢀconverterꢀwillꢀoperateꢀ

normally.ꢀHowever,ꢀtheꢀA/DꢀconverterꢀwillꢀenterꢀtheꢀsleepꢀmodeꢀifꢀtheꢀADSLPꢀbitꢀisꢀ

setꢀhighꢀasꢀtheꢀA/Dꢀconverterꢀhasꢀbeenꢀpoweredꢀon.ꢀTheꢀwholeꢀA/Dꢀconverterꢀcircuitꢀ

willꢀbeꢀswitchedꢀoffꢀexceptꢀtheꢀPGAꢀandꢀinternalꢀBandgapꢀcircuitꢀtoꢀreduceꢀtheꢀpowerꢀ

consumptionꢀandꢀV_CMꢀstart-upꢀstableꢀtime.

Bitꢀ5

ADOFF:ꢀA/DꢀConverterꢀModuleꢀPowerꢀOn/OffꢀControlꢀbit

0:ꢀPowerꢀon

1:ꢀPowerꢀoff

ThisꢀbitꢀcontrolsꢀtheꢀpowerꢀofꢀtheꢀA/Dꢀconverterꢀmodule.ꢀThisꢀbitꢀshouldꢀbeꢀclearedꢀ

toꢀ“0”ꢀtoꢀenableꢀtheꢀA/Dꢀconverter.ꢀIfꢀtheꢀbitꢀisꢀsetꢀhighꢀthenꢀtheꢀA/Dꢀconverterꢀwillꢀ

beꢀswitchedꢀoffꢀreducingꢀtheꢀdeviceꢀpowerꢀconsumption.ꢀAsꢀtheꢀA/Dꢀconverterꢀwillꢀ

consumeꢀaꢀlimitedꢀamountꢀofꢀpower,ꢀevenꢀwhenꢀnotꢀexecutingꢀaꢀconversion,ꢀthisꢀmayꢀ

beꢀanꢀimportantꢀconsiderationꢀinꢀpowerꢀsensitiveꢀbatteryꢀpoweredꢀapplications.

ItꢀisꢀrecommendedꢀtoꢀsetꢀtheꢀADOFFꢀbitꢀhighꢀbeforeꢀtheꢀdeviceꢀentersꢀtheꢀIDLE/

SLEEPꢀmodeꢀforꢀsavingꢀpower.ꢀSettingꢀtheꢀADOFFꢀbitꢀhighꢀwillꢀpowerꢀdownꢀtheꢀA/Dꢀ

converterꢀmoduleꢀregardlessꢀofꢀtheꢀADSLPꢀandꢀADRSTꢀbitꢀsettings.

Bitꢀ4~2

ADOR2~ADOR0:ꢀA/DꢀConversionꢀOversamplingꢀRateꢀSelection

000:ꢀOversamplingꢀrateꢀOSR=16384

001:ꢀOversamplingꢀrateꢀOSR=8192

010:ꢀOversamplingꢀrateꢀOSR=4096

011:ꢀOversamplingꢀrateꢀOSR=2048

100:ꢀOversamplingꢀrateꢀOSR=1024

101:ꢀOversamplingꢀrateꢀOSR=512

110:ꢀOversamplingꢀrateꢀOSR=256

111:ꢀOversamplingꢀrateꢀOSR=128

Bitꢀ1ꢀ

Bitꢀ0

Unimplemented,ꢀreadꢀasꢀ“0”

VREFS:ꢀA/DꢀConverterꢀReferenceꢀVoltageꢀPairꢀSelection

0:ꢀInternalꢀreferenceꢀvoltageꢀpairꢀ–ꢀV_CMꢀ&ꢀAV_SS

1:ꢀExternalꢀreferenceꢀvoltageꢀpairꢀ–ꢀVREFPꢀ&ꢀVREFN

Rev. 1.10

1ꢅꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

• ADCR1 Register

Bit

Name

R/W

7

FLMSꢅ

R/W

0

6

FLMS1

R/W

0

5

FLMS0

R/W

0

4

3

2

1

0

VRBUFN VRBUFP ADCDL

EOC

R/W

0

—

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7~5

FLMS2~FLMS0:ꢀA/DꢀConverterꢀClockꢀDividedꢀRatioꢀSelectionꢀandꢀSampledꢀDataꢀ

DoublingꢀFunctionꢀ(CHOP)ꢀEnableꢀControl

000:ꢀCHOP=2,ꢀf_ADCKꢀ=ꢀf_MCLKꢀ/ꢀ30

010:ꢀCHOP=2,ꢀf_ADCKꢀ=ꢀf_MCLKꢀ/ꢀ12

Others:ꢀReserved

WhenꢀtheꢀCHOPꢀbitꢀisꢀequalꢀtoꢀ2,ꢀitꢀmeansꢀthatꢀtheꢀsampledꢀdataꢀamountꢀwillꢀbeꢀ

doubledꢀforꢀtheꢀnormalꢀconversionꢀmode.

Bitꢀ4

Bitꢀ3

Bitꢀ2

VRBUFN:ꢀA/DꢀConverterꢀNegativeꢀReferenceꢀVoltageꢀInputꢀ(VRN)ꢀBufferꢀControl

0:ꢀDisableꢀinputꢀbufferꢀandꢀenableꢀbypassꢀfunction

1:ꢀEnableꢀinputꢀbufferꢀandꢀdisableꢀbypassꢀfunction

VRBUFP:ꢀA/DꢀConverterꢀPositiveꢀReferenceꢀVoltageꢀInputꢀ(VRP)ꢀBufferꢀControl

0:ꢀDisableꢀinputꢀbufferꢀandꢀenableꢀbypassꢀfunction

1:ꢀEnableꢀinputꢀbufferꢀandꢀdisableꢀbypassꢀfunction

ADCDL:ꢀA/DꢀConvertedꢀDataꢀLatchꢀFunctionꢀEnableꢀControl

0:ꢀDisableꢀdataꢀlatchꢀfunction

1:ꢀEnableꢀdataꢀlatchꢀfunction

IfꢀtheꢀA/Dꢀconvertedꢀdataꢀlatchꢀfunctionꢀisꢀenabled,ꢀtheꢀlatestꢀconvertedꢀdataꢀvalueꢀwillꢀ

beꢀlatchedꢀandꢀnotꢀbeꢀupdatedꢀbyꢀanyꢀsubsequentꢀconvertedꢀresultsꢀuntilꢀthisꢀfunctionꢀ

isꢀdisabled.ꢀAlthoughꢀtheꢀconvertedꢀdataꢀisꢀlatchedꢀintoꢀtheꢀdataꢀregisters,ꢀtheꢀA/Dꢀ

converterꢀcircuitsꢀremainꢀoperational,ꢀbutꢀwillꢀnotꢀgenerateꢀinterruptꢀandꢀEOCꢀwillꢀnotꢀ

change.ꢀItꢀisꢀrecommendedꢀthatꢀthisꢀbitꢀshouldꢀbeꢀsetꢀhighꢀbeforeꢀreadingꢀtheꢀconvertedꢀ

dataꢀinꢀtheꢀADRL,ꢀADRMꢀandꢀADRHꢀregisters.ꢀAfterꢀtheꢀconvertedꢀdataꢀhasꢀbeenꢀ

readꢀout,ꢀtheꢀbitꢀcanꢀthenꢀbeꢀclearedꢀtoꢀlowꢀtoꢀdisableꢀtheꢀA/Dꢀconverterꢀdataꢀlatchꢀ

functionꢀandꢀallowꢀfurtherꢀconversionꢀvaluesꢀtoꢀbeꢀstored.ꢀInꢀthisꢀway,ꢀtheꢀpossibilityꢀ

ofꢀobtainingꢀundesiredꢀdataꢀduringꢀA/Dꢀconverterꢀconversionsꢀcanꢀbeꢀprevented.

Bitꢀ1

EOC:ꢀEndꢀofꢀA/DꢀConversionꢀFlag

0:ꢀA/Dꢀconversionꢀinꢀprogress

1:ꢀA/Dꢀconversionꢀended

Thisꢀbitꢀmustꢀbeꢀclearedꢀbyꢀsoftware.

Unimplemented,ꢀreadꢀasꢀ“0”

Bitꢀ0ꢀ

Rev. 1.10

1ꢅ5

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

• ADCS Register

Bit

Name

R/W

7

6

5

4

ADCKꢃ

R/W

0

3

ADCK3

R/W

0

2

ADCKꢅ

R/W

0

1

ADCK1

R/W

0

ADCK0

R/W

0

—

POR

Bitꢀ7~5ꢀ

Bitꢀ4~0

Unimplemented,ꢀreadꢀasꢀ“0”

ADCK4~ADCK0:ꢀA/DꢀConverterꢀClockꢀSourceꢀf_MCLKꢀDividedꢀRatioꢀSelection

00000~11110:ꢀf_MCLK=f_SYS/2ꢀ/ꢀ(ADCK[4:0]+1)

11111:ꢀf_MCLK=f_SYS

A/D Operation

TheꢀA/Dꢀconverterꢀprovidesꢀthreeꢀoperationalꢀmodes,ꢀwhichꢀareꢀPowerꢀdownꢀmode,ꢀSleepꢀmodeꢀandꢀ

Resetꢀmode,ꢀcontrolledꢀrespectivelyꢀbyꢀtheꢀADOFF,ꢀADSLPꢀandꢀADRSTꢀbitsꢀinꢀtheꢀADCR0ꢀregister.ꢀ

Theꢀfollowingꢀtableꢀillustratesꢀtheꢀoperatingꢀmodeꢀselection.

LDOEN ADOFF ADSLP ADRST

Operating Mode

Description

Bandgap offꢄ LDO offꢄ V_CMgeneꢁatoꢁ offꢄ

PGA offꢄ ADC offꢄ Tempeꢁatꢀꢁe sensoꢁ offꢄ

VRN/VRP buffer off, SINC ﬁlter off

0

1

0

1

0

x

1

0

1

0

x

0

1

x

0

1

Poweꢁ down mode

Bandgap onꢄ LDO onꢄ V_CMgeneꢁatoꢁ offꢄ

PGA offꢄ ADC offꢄ Tempeꢁatꢀꢁe sensoꢁ offꢄ

VRN/VRP buffer off, SINC ﬁlter off

Poweꢁ down mode

Sleep mode

(Exteꢁnal voltage mꢀst be

Bandgap onꢄ LDO offꢄ V_CMgeneꢁatoꢁ offꢄ

PGA onꢄ ADC offꢄ Tempeꢁatꢀꢁe sensoꢁ offꢄ

sꢀpplied on LDO oꢀtpꢀt pin) VRN/VRP buffer off, SINC ﬁlter on

Noꢁmal mode

(Exteꢁnal voltage mꢀst be

Bandgap onꢄ LDO offꢄ V_CMgeneꢁatoꢁ on/off⁽¹⁾ꢄ

PGA onꢄ ADC onꢄ Tempeꢁatꢀꢁe sensoꢁ on/off^(ꢅ)ꢄ

sꢀpplied on LDO oꢀtpꢀt pin) VRN/VRP bꢀffeꢁ on/off⁽³⁾, SINC ﬁlter on

Reset mode

(Exteꢁnal voltage mꢀst be

Bandgap onꢄ LDO offꢄ V_CMgeneꢁatoꢁ on/off⁽¹⁾ꢄ

PGA onꢄ ADC onꢄTempeꢁatꢀꢁe sensoꢁ on/off^(ꢅ)ꢄ

sꢀpplied on LDO oꢀtpꢀt pin) VRN/VRP bꢀffeꢁ on/off⁽³⁾, SINC ﬁlter reset

Bandgap onꢄ LDO onꢄ V_CMgeneꢁatoꢁ offꢄ

PGA onꢄ ADC offꢄ Tempeꢁatꢀꢁe sensoꢁ offꢄ

VRN/VRP buffer off, SINC ﬁlter on

Bandgap onꢄ LDO onꢄ V_CMgeneꢁatoꢁ on/off⁽¹⁾ꢄ

PGA onꢄ ADC onꢄ Tempeꢁatꢀꢁe sensoꢁ on/off^(ꢅ)ꢄ

VRN/VRP bꢀffeꢁ on/off⁽³⁾, SINC ﬁlter on

Bandgap onꢄ LDO onꢄ V_CMgeneꢁatoꢁ on/off⁽¹⁾ꢄ

PGA onꢄ ADC onꢄ Tempeꢁatꢀꢁe sensoꢁ on/off^(ꢅ)ꢄ

VRN/VRP bꢀffeꢁ on/off⁽³⁾, SINC ﬁlter reset

Sleep mode

Noꢁmal mode

Reset mode

“x” ꢀnknown

Note:ꢀ1.ꢀTheꢀV_CMꢀgeneratorꢀcanꢀbeꢀswitchedꢀonꢀorꢀoffꢀbyꢀtheꢀbandgapꢀonꢀorꢀoff.

2.ꢀTheꢀTemperatureꢀsensorꢀcanꢀbeꢀswitchedꢀonꢀorꢀoffꢀbyꢀconﬁguringꢀtheꢀCHSN[3:0]ꢀorꢀCHSP[3:0]ꢀbits

3.ꢀTheꢀVRNꢀbufferꢀcanꢀbeꢀswitchedꢀonꢀorꢀoffꢀbyꢀconﬁguringꢀtheꢀVRBUFNꢀbitꢀwhileꢀtheꢀVRPꢀbufferꢀcanꢀbeꢀ

switchedꢀonꢀorꢀoffꢀbyꢀconﬁguringꢀtheꢀVRBUFPꢀbit

A/D Operation Mode Selection

Rev. 1.10

1ꢅ6

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

ToꢀenableꢀtheꢀA/Dꢀconverter,ꢀtheꢀﬁrstꢀstepꢀisꢀtoꢀdisableꢀtheꢀA/Dꢀconverterꢀpowerꢀdownꢀandꢀsleepꢀ

modeꢀbyꢀclearingꢀtheꢀADOFFꢀandꢀADSLPꢀbitsꢀtoꢀmakeꢀsureꢀtheꢀA/Dꢀconverterꢀisꢀpoweredꢀup.ꢀTheꢀ

ADRSTꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀisꢀusedꢀtoꢀstartꢀandꢀresetꢀtheꢀA/Dꢀconverterꢀafterꢀpowerꢀon.ꢀToꢀsetꢀ

ADRSTꢀbitꢀfromꢀlowꢀtoꢀhighꢀandꢀthenꢀlowꢀagain,ꢀanꢀanalogꢀtoꢀdigitalꢀconvertedꢀdataꢀinꢀSINCꢀﬁlterꢀ

willꢀbeꢀinitiated.ꢀAfterꢀthisꢀsetupꢀisꢀcomplete,ꢀtheꢀA/DꢀConverterꢀisꢀreadyꢀforꢀoperation.ꢀTheseꢀthreeꢀ

bitsꢀareꢀusedꢀtoꢀcontrolꢀtheꢀoverallꢀstartꢀoperationꢀofꢀtheꢀinternalꢀanalogꢀtoꢀdigitalꢀconverter.

TheꢀEOCꢀbitꢀinꢀtheꢀADCR1ꢀregisterꢀisꢀusedꢀtoꢀindicateꢀwhenꢀtheꢀanalogꢀtoꢀdigitalꢀconversionꢀprocessꢀisꢀ

complete.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀsetꢀtoꢀ“1”ꢀbyꢀtheꢀHardwareꢀafterꢀaꢀconversionꢀcycleꢀhasꢀended.ꢀ

Inꢀaddition,ꢀtheꢀcorrespondingꢀA/Dꢀinterruptꢀrequestꢀﬂagꢀwillꢀbeꢀsetꢀinꢀtheꢀinterruptꢀcontrolꢀregister,ꢀ

andꢀifꢀtheꢀinterruptsꢀareꢀenabled,ꢀanꢀappropriateꢀinternalꢀinterruptꢀsignalꢀwillꢀbeꢀgenerated.ꢀThisꢀA/Dꢀ

internalꢀinterruptꢀsignalꢀwillꢀdirectꢀtheꢀprogramꢀﬂowꢀtoꢀtheꢀassociatedꢀA/Dꢀinternalꢀinterruptꢀaddressꢀ

forꢀprocessing.ꢀIfꢀtheꢀA/Dꢀinternalꢀinterruptꢀisꢀdisabled,ꢀtheꢀmicrocontrollerꢀcanꢀpollꢀtheꢀEOCꢀbitꢀinꢀtheꢀ

ADCR1ꢀregisterꢀtoꢀcheckꢀwhetherꢀitꢀhasꢀbeenꢀsetꢀ“1”ꢀasꢀanꢀalternativeꢀmethodꢀofꢀdetectingꢀtheꢀendꢀofꢀ

anꢀA/Dꢀconversionꢀcycle.ꢀTheꢀA/Dꢀconvertedꢀdataꢀwillꢀbeꢀupdatedꢀcontinuouslyꢀbyꢀtheꢀnewꢀconvertedꢀ

data.ꢀIfꢀtheꢀA/Dꢀconvertedꢀdataꢀlatchꢀfunctionꢀisꢀenabled,ꢀtheꢀlatestꢀconvertedꢀdataꢀwillꢀbeꢀlatchedꢀandꢀ

theꢀfollowingꢀnewꢀconvertedꢀdataꢀwillꢀbeꢀdiscardedꢀuntilꢀthisꢀdataꢀlatchꢀfunctionꢀisꢀdisabled.

TheꢀclockꢀsourceꢀforꢀtheꢀA/Dꢀconverterꢀshouldꢀbeꢀtypicallyꢀfixedꢀatꢀaꢀvalueꢀofꢀ4MHz,ꢀwhichꢀ

originatesꢀfromꢀtheꢀsystemꢀclockꢀf_SYS,ꢀandꢀcanꢀbeꢀchosenꢀtoꢀbeꢀeitherꢀf_SYSꢀorꢀaꢀsubdividedꢀversionꢀ

ofꢀf_SYS.ꢀTheꢀdivisionꢀratioꢀvalueꢀisꢀdeterminedꢀbyꢀtheꢀADCK4~ADCK0ꢀbitsꢀinꢀtheꢀADCSꢀregisterꢀtoꢀ

obtainꢀaꢀ4MHzꢀclockꢀsourceꢀforꢀtheꢀA/Dꢀconverter.

TheꢀdifferentialꢀreferenceꢀvoltageꢀsupplyꢀtoꢀtheꢀA/DꢀConverterꢀcanꢀbeꢀsuppliedꢀfromꢀeitherꢀtheꢀ

internalꢀpowerꢀsupply,ꢀV_CMꢀandꢀAV_SS,ꢀorꢀfromꢀanꢀexternalꢀreferenceꢀsource,ꢀVREFPꢀandꢀVREFN.ꢀ

TheꢀdesiredꢀselectionꢀisꢀmadeꢀusingꢀtheꢀVREFSꢀbitꢀinꢀtheꢀADCR0ꢀregister.

Summary of A/D Conversion Steps

Theꢀfollowingꢀsummarisesꢀtheꢀindividualꢀstepsꢀthatꢀshouldꢀbeꢀexecutedꢀinꢀorderꢀtoꢀimplementꢀanꢀ

A/Dꢀconversionꢀprocess.

•ꢀ Stepꢀ1

EnableꢀtheꢀpowerꢀLDO,ꢀVCMꢀforꢀPGAꢀandꢀA/Dꢀconverter.

•ꢀ Stepꢀ2

SelectꢀtheꢀPGA,ꢀA/Dꢀconverter,ꢀreferenceꢀvoltageꢀgainsꢀbyꢀPGAC0ꢀregister

•ꢀ Stepꢀ3

SelectꢀtheꢀPGAꢀsettingsꢀforꢀinputꢀconnection,ꢀV_CMꢀvoltageꢀlevelꢀandꢀbufferꢀoptionꢀbyꢀPGAC1ꢀ

register

•ꢀ Stepꢀ4

SelectꢀtheꢀrequiredꢀA/DꢀconversionꢀclockꢀsourceꢀbyꢀcorrectlyꢀprogrammingꢀbitsꢀADCK4~ADCK0ꢀ

inꢀtheꢀADCSꢀregister.

•ꢀ Stepꢀ5

SelectꢀoutputꢀdataꢀrateꢀbyꢀconﬁguringꢀtheꢀADOR[2:0]ꢀbitsꢀinꢀtheꢀADCR0ꢀregisterꢀandꢀFLMS[2:0]ꢀ

bitsꢀinꢀtheꢀADCR1ꢀregister.

•ꢀ Stepꢀ6

SelectꢀwhichꢀchannelꢀisꢀtoꢀbeꢀconnectedꢀtoꢀtheꢀinternalꢀPGAꢀbyꢀcorrectlyꢀprogrammingꢀtheꢀ

CHSP3~CHSP0ꢀandꢀCHSN3~CHSN0ꢀbitsꢀwhichꢀareꢀalsoꢀcontainedꢀinꢀtheꢀPGACSꢀregister.

•ꢀ Stepꢀ7

ReleaseꢀtheꢀpowerꢀdownꢀmodeꢀandꢀsleepꢀmodeꢀbyꢀclearingꢀtheꢀADOFFꢀandꢀADSLPꢀbitsꢀinꢀ

ADCR0ꢀregister.

Rev. 1.10

1ꢅ7

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

•ꢀ Stepꢀ8ꢀ

ResetꢀtheꢀA/DꢀbyꢀsettingꢀtheꢀADRSTꢀtoꢀhighꢀinꢀtheꢀADCR0ꢀregisterꢀandꢀclearingꢀthisꢀbitꢀtoꢀ“0”ꢀtoꢀ

releaseꢀresetꢀstatus.

•ꢀ Stepꢀ9

Ifꢀtheꢀinterruptsꢀareꢀtoꢀbeꢀused,ꢀtheꢀinterruptꢀcontrolꢀregistersꢀmustꢀbeꢀcorrectlyꢀconfiguredꢀtoꢀ

ensureꢀtheꢀA/Dꢀconverterꢀinterruptꢀfunctionꢀisꢀactive.ꢀTheꢀmasterꢀinterruptꢀcontrolꢀbit,ꢀEMI,ꢀandꢀ

theꢀA/Dꢀconverterꢀinterruptꢀbit,ꢀADE,ꢀmustꢀbothꢀbeꢀsetꢀhighꢀtoꢀdoꢀthis.

•ꢀ Stepꢀ10

Toꢀcheckꢀwhenꢀtheꢀanalogꢀtoꢀdigitalꢀconversionꢀprocessꢀisꢀcomplete,ꢀtheꢀEOCꢀbitꢀinꢀtheꢀADCR1ꢀ

registerꢀcanꢀbeꢀpolled.ꢀTheꢀconversionꢀprocessꢀisꢀcompleteꢀwhenꢀthisꢀbitꢀgoesꢀhigh.ꢀWhenꢀthisꢀ

occursꢀtheꢀA/DꢀdataꢀregistersꢀADRL,ꢀADRMꢀandꢀADRHꢀcanꢀbeꢀreadꢀtoꢀobtainꢀtheꢀconversionꢀ

value.ꢀAsꢀanꢀalternativeꢀmethod,ꢀifꢀtheꢀinterruptsꢀareꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀtheꢀprogramꢀ

canꢀwaitꢀforꢀanꢀA/Dꢀinterruptꢀtoꢀoccur.

Note:ꢀWhenꢀcheckingꢀforꢀtheꢀendꢀofꢀtheꢀconversionꢀprocess,ꢀifꢀtheꢀmethodꢀofꢀpollingꢀtheꢀEOCꢀbitꢀinꢀ

theꢀADCR1ꢀregisterꢀisꢀused,ꢀtheꢀinterruptꢀenableꢀstepꢀaboveꢀcanꢀbeꢀomitted.

Programming Considerations

DuringꢀmicrocontrollerꢀoperationsꢀwhereꢀtheꢀA/Dꢀconverterꢀisꢀnotꢀbeingꢀused,ꢀtheꢀA/Dꢀinternalꢀ

circuitryꢀcanꢀbeꢀswitchedꢀoffꢀtoꢀreduceꢀpowerꢀconsumption,ꢀbyꢀsettingꢀbitꢀADOFFꢀhighꢀinꢀtheꢀ

ADCR0ꢀregister.ꢀWhenꢀthisꢀhappens,ꢀtheꢀinternalꢀA/Dꢀconverterꢀcircuitsꢀwillꢀnotꢀconsumeꢀpowerꢀ

irrespectiveꢀofꢀwhatꢀanalogꢀvoltageꢀisꢀappliedꢀtoꢀtheirꢀinputꢀlines.

A/D Converter Transfer Function

Eachꢀdeviceꢀcontainsꢀaꢀ24-bitꢀDeltaꢀSigmaꢀA/Dꢀconverterꢀandꢀitsꢀfull-scaleꢀconvertedꢀdigitisedꢀvalueꢀ

isꢀfromꢀ8388607ꢀtoꢀ-8388608ꢀinꢀdecimalꢀvalue.ꢀTheꢀconvertedꢀdataꢀformatꢀisꢀformedꢀbyꢀaꢀtwo’sꢀ

complementꢀbinaryꢀvalue.ꢀTheꢀMSBꢀofꢀtheꢀconvertedꢀdataꢀisꢀtheꢀsignedꢀbit.ꢀSinceꢀtheꢀfull-scaleꢀ

analogꢀinputꢀvalueꢀisꢀequalꢀtoꢀtheꢀampliﬁedꢀvalueꢀofꢀtheꢀV_CMꢀorꢀdifferentialꢀreferenceꢀinputꢀvoltage,ꢀ

ΔVR_I,ꢀselectedꢀbyꢀtheꢀVREFSꢀbitꢀinꢀADCR0ꢀregister,ꢀthisꢀgivesꢀaꢀsingleꢀbitꢀanalogꢀinputꢀvalueꢀofꢀ

ΔVR_Iꢀdividedꢀbyꢀ8388608.

1ꢀLSBꢀ=ꢀΔVR_Iꢀ/ꢀ8388608

TheꢀA/DꢀConverterꢀinputꢀvoltageꢀvalueꢀcanꢀbeꢀcalculatedꢀusingꢀtheꢀfollowingꢀequation:

ΔSI_Iꢀ=ꢀ(PGAGNꢀ×ꢀADGNꢀ×ꢀΔDI±)ꢀ+ꢀDCSET

ΔVR_Iꢀ=ꢀVREGNꢀ×ꢀΔVR±

ADC_Conversion_Dataꢀ=ꢀ(ΔSI_Iꢀ/ꢀΔVR_I)ꢀ×ꢀK

WhereꢀKꢀisꢀequalꢀtoꢀ2²³

Note:ꢀ1.ꢀTheꢀPGAGN,ꢀADGN,ꢀVREGNꢀvaluesꢀareꢀdecidedꢀbyꢀtheꢀPGS,ꢀAGS,ꢀVGSꢀcontrolꢀbits.

2.ꢀΔSI_I:ꢀDifferentialꢀInputꢀSignalꢀafterꢀampliﬁcationꢀandꢀoffsetꢀadjustment.

3.ꢀPGAGN:ꢀProgrammableꢀGainꢀAmpliﬁerꢀgain

4.ꢀADGN:ꢀA/DꢀConverterꢀgain

5.ꢀVREGN:ꢀReferenceꢀvoltageꢀgain

6.ꢀΔDI±:ꢀDifferentialꢀinputꢀsignalꢀderivedꢀfromꢀexternalꢀchannelsꢀorꢀinternalꢀsignals

7.ꢀDCSET:ꢀOffsetꢀvoltage

8.ꢀΔVR±:ꢀDifferentialꢀReferenceꢀvoltage

9.ꢀΔVR_I:ꢀDifferentialꢀReferenceꢀinputꢀvoltageꢀafterꢀampliﬁcation

Rev. 1.10

1ꢅꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

DueꢀtoꢀtheꢀdigitalꢀsystemꢀdesignꢀofꢀtheꢀDeltaꢀSigmaꢀA/DꢀConverter,ꢀtheꢀmaximumꢀnumberꢀofꢀtheꢀ

A/Dꢀconvertedꢀvalueꢀisꢀ8388607ꢀandꢀtheꢀminimumꢀvalueꢀisꢀ-8388608,ꢀtherefore,ꢀweꢀcanꢀhaveꢀtheꢀ

middleꢀnumberꢀ0.ꢀTheꢀADC_Conversion_Dataꢀequationꢀillustratesꢀthisꢀrangeꢀofꢀconvertedꢀdataꢀ

variation.

A/D Conversion Data

Decimal Value

(2’s Compliment, Hexadecimal)

0x7FFFFF

0xꢆ00000

ꢆ3ꢆꢆ607

-ꢆ3ꢆꢆ60ꢆ

A/D Conversion Data Range

TheꢀaboveꢀA/DꢀconverterꢀconversionꢀdataꢀtableꢀillustratesꢀtheꢀrangeꢀofꢀA/Dꢀconversionꢀdata.

TheꢀfollowingꢀdiagramꢀshowsꢀtheꢀrelationshipꢀbetweenꢀtheꢀDCꢀinputꢀvalueꢀandꢀtheꢀA/Dꢀconvertedꢀ

dataꢀwhichꢀisꢀpresentedꢀbyꢀtheꢀTwo’sꢀComplement.

ꢅꢃ Digital oꢀtpꢀt

Two's complement

0111 1111 1111 1111 1111 1111

DC inpꢀt valꢀe

0

(D₊- D_-) * PGAGN * ADGN + DCSET

(REFP - REFN) * VREGN

1000 0000 0000 0000 0000 0000

Rev. 1.10

1ꢅ9

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

ꢅꢃ Digital oꢀtpꢀt

Two's complement

0111 1111 1111 1111 1111 1111

DC inpꢀt valꢀe

0

(D₊- D_-) * PGAGN * ADGN + DCSET

(REFP - REFN) * VREGN

1000 0000 0000 0000 0000 0000

A/D Converted Data

TheꢀA/DꢀconvertedꢀdataꢀisꢀrelatedꢀtoꢀtheꢀinputꢀvoltageꢀandꢀtheꢀPGAꢀselections.ꢀTheꢀformatꢀofꢀtheꢀ

A/Dꢀconverterꢀoutputꢀisꢀaꢀtwo’sꢀcomplementꢀbinaryꢀcode.ꢀTheꢀlengthꢀofꢀthisꢀoutputꢀcodeꢀisꢀ24ꢀbitsꢀ

andꢀtheꢀMSBꢀisꢀaꢀsignedꢀbit.ꢀWhenꢀtheꢀMSBꢀisꢀ“0”,ꢀwhichꢀrepresentsꢀtheꢀinputꢀisꢀ“positive”,ꢀonꢀtheꢀ

otherꢀhand,ꢀasꢀtheꢀMSBꢀisꢀ“1”,ꢀitꢀrepresentsꢀtheꢀinputꢀisꢀ“negative”.ꢀTheꢀmaximumꢀvalueꢀisꢀ8388607ꢀ

andꢀtheꢀminimumꢀvalueꢀisꢀ-8388608.ꢀIfꢀtheꢀinputꢀsignalꢀisꢀoverꢀtheꢀmaximumꢀvalue,ꢀtheꢀconvertedꢀ

dataꢀisꢀlimitedꢀbyꢀtheꢀ8388607,ꢀandꢀifꢀtheꢀinputꢀsignalꢀisꢀlessꢀthanꢀtheꢀminimumꢀvalue,ꢀtheꢀconvertedꢀ

dataꢀisꢀlimitedꢀbyꢀ-8388608.

Rev. 1.10

130

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

A/D Converted Data to Voltage

Theꢀdesignerꢀcanꢀrecoverꢀtheꢀconvertedꢀdataꢀbyꢀtheꢀfollowingꢀequations:

IfꢀMSB=0ꢀ(PositiveꢀConvertedꢀdata):ꢀInputꢀVoltage=

(Converted_data)  LSB  DCSET

PGA  ADGN

IfꢀMSB=1(NegativeꢀConvertedꢀdata):ꢀInputꢀvoltage=ꢀ

Two's_complement_of_Converted_data

PGAADGN

Note:ꢀTwo’sꢀcomplement=One’sꢀcomplementꢀ+1





 LSB  DCSET

A/D Programming Example

• Example: Using an EOC polling method to detect the end of conversion

#include bh66f2650.inc

data .section

'data'

ꢀ

adc_result_data_lꢀdbꢀ?

adc_result_data_mꢀdbꢀ?

adc_result_data_hꢀdbꢀ?

code .section

start:

‘code’

ꢀ

clrꢀꢀ ADEꢀꢀ

ꢀ

movꢀꢀ a,ꢀ083Hꢀꢀ

movꢀꢀ PWRC,ꢀaꢀꢀ

ꢀ

;ꢀDisableꢀA/Dꢀconverterꢀinterrupt

;ꢀPowerꢀcontrolꢀforꢀPGA,ꢀA/Dꢀconverter

;ꢀPWRC=10000011,ꢀLDOꢀenable,ꢀVCMꢀenable,ꢀLDOꢀBypass

;ꢀdisable,ꢀLDOꢀoutputꢀvoltage:ꢀ3.3V

ꢀ

mov

a, 000H

ꢀ

movꢀꢀ PGAC0,ꢀaꢀꢀ ꢀ

mov a, 000H

movꢀꢀ PGAC1,ꢀaꢀꢀ ꢀ

ꢀ

;ꢀPGAꢀgain=1,ꢀA/Dꢀconverterꢀgain=1,ꢀVREFꢀgain=1

ꢀ

;ꢀV_CM=1.25V,ꢀINIS,ꢀINX,ꢀDCSETꢀinꢀdefaultꢀvalue

;ꢀenableꢀbufferꢀforꢀVREF+

;ꢀenableꢀbufferꢀforꢀVREF-

;ꢀforꢀusingꢀexternalꢀreference

;ꢀforꢀ10Hzꢀoutputꢀdataꢀrate,ꢀADOR[2:0]=001,ꢀFLMS[2:0]=000

setꢀꢀ VRBUFPꢀꢀ

setꢀꢀ VRBUFNꢀꢀ

setꢀꢀ VREFSꢀꢀꢀ

clrꢀꢀ ADOR2ꢀꢀꢀ

clrꢀꢀ ADOR1

ꢀ

setꢀꢀ ADOR0

clrꢀꢀ FLMS2

c l r ꢀꢀ F L M S 1

c l r ꢀꢀ F L M S 0

ꢀ

clrꢀꢀ ADOFFꢀꢀꢀ

setꢀꢀ ADRSTꢀꢀꢀ

clrꢀꢀ ADRSTꢀꢀꢀ

ꢀ

;ꢀA/Dꢀconverterꢀexitꢀpowerꢀdownꢀmode.

;ꢀA/Dꢀconverterꢀinꢀresetꢀmode

;ꢀA/Dꢀconverterꢀinꢀconvertsionꢀ(continuosꢀmode)

;ꢀClearꢀ“EOC”ꢀﬂag

clrꢀꢀ EOCꢀꢀ

ꢀ

loop:

ꢀ

snzꢀꢀ EOCꢀꢀ

jmpꢀꢀ loopꢀꢀ

clrꢀꢀ adc_result_data_h

clrꢀꢀ adc_result_data_m

clrꢀꢀ adc_result_data_l

movꢀꢀ a,ꢀADRL

movꢀꢀ adc_result_data_l,ꢀaꢀꢀ;ꢀGetꢀLowꢀbyteꢀA/Dꢀconverterꢀvalue

movꢀꢀ a,ꢀADRM

movꢀꢀ adc_result_data_m,ꢀaꢀꢀ;ꢀGetꢀMiddleꢀbyteꢀA/Dꢀconverterꢀvalue

movꢀꢀ a,ꢀADRH

ꢀ

;ꢀPollingꢀ“EOC”ꢀﬂag

;ꢀWaitꢀforꢀreadꢀdata

movꢀꢀ adc_result_data_h,ꢀaꢀꢀ;ꢀGetꢀHighꢀbyteꢀA/Dꢀconverterꢀvalue

get_adc_value_ok:

ꢀ

clrꢀꢀ EOCꢀꢀ

jmp loop

ꢀ

;ꢀClearingꢀreadꢀﬂag

; for next data read

end

Rev. 1.10

131

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Temperature Sensor

Theꢀdevicesꢀprovideꢀanꢀinternalꢀtemperatureꢀsensorꢀtoꢀcompensateꢀtheꢀdeviceꢀdueꢀtoꢀtemperatureꢀ

effects.ꢀByꢀselectingꢀtheꢀPGAꢀinputꢀchannelsꢀasꢀV_TSOPꢀandꢀV_TSON,ꢀtheꢀA/DꢀConverterꢀcanꢀobtainꢀ

temperatureꢀinformationꢀallowingꢀcompenstiaonꢀtoꢀbeꢀmadeꢀtoꢀtheꢀA/Dꢀconvertedꢀdata.

V_OREG

I

V_TSO+

A/D Converter

PGA

V_TSO

-

AV_SS

Serial Interface Module – SIM

EachꢀdeviceꢀcontainsꢀaꢀSerialꢀInterfaceꢀModule,ꢀwhichꢀincludesꢀbothꢀtheꢀfourꢀlineꢀSPIꢀinterfaceꢀandꢀ

theꢀtwoꢀlineꢀI²Cꢀinterfaceꢀtypes,ꢀtoꢀallowꢀanꢀeasyꢀmethodꢀofꢀcommunicationꢀwithꢀexternalꢀperipheralꢀ

hardware.ꢀHavingꢀrelativelyꢀsimpleꢀcommunicationꢀprotocols,ꢀtheseꢀserialꢀinterfaceꢀtypesꢀallowꢀtheꢀ

microcontrollerꢀtoꢀinterfaceꢀtoꢀexternalꢀSPIꢀorꢀI²Cꢀbasedꢀhardwareꢀsuchꢀasꢀsensors,ꢀFlashꢀmemory,ꢀ

etc.ꢀAsꢀbothꢀinterfaceꢀtypesꢀshareꢀtheꢀsameꢀpinsꢀandꢀregisters,ꢀtheꢀchoiceꢀofꢀwhetherꢀtheꢀSPIꢀorꢀI²Cꢀ

typeꢀisꢀusedꢀisꢀmadeꢀusingꢀtheꢀSIMꢀoperatingꢀmodeꢀcontrolꢀbits,ꢀnamedꢀSIM2~SIM0,ꢀinꢀtheꢀSIMC0ꢀ

register.ꢀTheseꢀpull-highꢀresistorsꢀofꢀtheꢀSIMꢀpin-sharedꢀI/Oꢀpinsꢀareꢀselectedꢀusingꢀpull-highꢀcontrolꢀ

registersꢀwhenꢀtheꢀSIMꢀfunctionꢀisꢀenabledꢀandꢀtheꢀcorrespondingꢀpinsꢀareꢀusedꢀasꢀSIMꢀinputꢀpins.

SPI Interface

TheꢀSPIꢀinterfaceꢀisꢀoftenꢀusedꢀtoꢀcommunicateꢀwithꢀexternalꢀperipheralꢀdevicesꢀsuchꢀasꢀsensors,ꢀ

Flashꢀmemoryꢀdevicesꢀetc.ꢀOriginallyꢀdevelopedꢀbyꢀMotorola,ꢀtheꢀfourꢀlineꢀSPIꢀinterfaceꢀisꢀaꢀ

synchronousꢀserialꢀdataꢀinterfaceꢀthatꢀhasꢀaꢀrelativelyꢀsimpleꢀcommunicationꢀprotocolꢀsimplifyingꢀ

theꢀprogrammingꢀrequirementsꢀwhenꢀcommunicatingꢀwithꢀexternalꢀhardwareꢀdevices.

Theꢀcommunicationꢀisꢀfullꢀduplexꢀandꢀoperatesꢀasꢀaꢀslave/masterꢀtype,ꢀwhereꢀtheꢀdevicesꢀcanꢀbeꢀ

eitherꢀmasterꢀorꢀslave.ꢀAlthoughꢀtheꢀSPIꢀinterfaceꢀspeciﬁcationꢀcanꢀcontrolꢀmultipleꢀslaveꢀdevicesꢀ

fromꢀaꢀsingleꢀmaster,ꢀbutꢀtheseꢀdevicesꢀareꢀprovidedꢀonlyꢀoneꢀSCSꢀpin.ꢀIfꢀtheꢀmasterꢀneedsꢀtoꢀcontrolꢀ

multipleꢀslaveꢀdevicesꢀfromꢀaꢀsingleꢀmaster,ꢀtheꢀmasterꢀcanꢀuseꢀI/Oꢀpinꢀtoꢀselectꢀtheꢀslaveꢀdevices.

SPI Masteꢁ

SCK

SPI Slave

SCK

SDO

SDI

SDO

SCS

SPI Master/Slave Connection

Rev. 1.10

13ꢅ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

SPI Interface Operation

TheꢀSPIꢀinterfaceꢀisꢀaꢀfullꢀduplexꢀsynchronousꢀserialꢀdataꢀlink.ꢀItꢀisꢀaꢀfourꢀlineꢀinterfaceꢀwithꢀpinꢀ

namesꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCS.ꢀPinsꢀSDIꢀandꢀSDOꢀareꢀtheꢀSerialꢀDataꢀInputꢀandꢀSerialꢀDataꢀOutputꢀ

lines;ꢀSCKꢀisꢀtheꢀSerialꢀClockꢀlineꢀandꢀSCSꢀisꢀtheꢀSlaveꢀSelectꢀline.ꢀAsꢀtheꢀSPIꢀinterfaceꢀpinsꢀareꢀpin-

sharedꢀwithꢀnormalꢀI/OꢀpinsꢀandꢀwithꢀtheꢀI²Cꢀfunctionꢀpins,ꢀtheꢀSPIꢀinterfaceꢀmustꢀﬁrstꢀbeꢀenabledꢀ

byꢀsettingꢀtheꢀcorrectꢀbitsꢀinꢀtheꢀSIMC0ꢀandꢀSIMC2ꢀregisters.ꢀTheꢀSPIꢀcanꢀbeꢀdisabledꢀorꢀenabledꢀ

usingꢀtheꢀSIMENꢀbitꢀinꢀtheꢀSIMC0ꢀregister.ꢀCommunicationꢀbetweenꢀdevicesꢀconnectedꢀtoꢀtheꢀSPIꢀ

interfaceꢀisꢀcarriedꢀoutꢀinꢀaꢀslave/masterꢀmodeꢀwithꢀallꢀdataꢀtransferꢀinitiationsꢀbeingꢀimplementedꢀ

byꢀtheꢀmaster.ꢀTheꢀMasterꢀalsoꢀcontrolsꢀtheꢀclockꢀsignal.ꢀAsꢀtheseꢀdevicesꢀonlyꢀcontainsꢀaꢀsingleꢀSCSꢀ

pinꢀonlyꢀoneꢀslaveꢀdeviceꢀcanꢀbeꢀutilized.ꢀTheꢀSCSꢀpinꢀisꢀcontrolledꢀbyꢀsoftware,ꢀsetꢀCSENꢀbitꢀtoꢀ“1”ꢀ

toꢀenableꢀSCSꢀpinꢀfunction,ꢀsetꢀCSENꢀbitꢀtoꢀ“0”ꢀtheꢀSCSꢀpinꢀwillꢀbeꢀﬂoatingꢀstate.

Data Bꢀs

SIMD

SDI Pin

TX/RX Shift Register

SDO Pin

CKEG

CKPOLB

Clock Edge/Polaꢁitꢂ

Contꢁol

WCOL

TRF

Bꢀsꢂ Statꢀs

SCK Pin

SIMICF

Clock

Soꢀꢁce

Select

f_SYS

f_SUB

PTMꢅ CCRP match fꢁeqꢀencꢂ/ꢅ

SCS Pin

CSEN

SPI Block Diagram

TheꢀSPIꢀfunctionꢀinꢀtheseꢀdevicesꢀofferꢀtheꢀfollowingꢀfeatures:ꢀ

•ꢀ Fullꢀduplexꢀsynchronousꢀdataꢀtransferꢀ

•ꢀ BothꢀMasterꢀandꢀSlaveꢀmodesꢀ

•ꢀ LSBꢀﬁrstꢀorꢀMSBꢀﬁrstꢀdataꢀtransmissionꢀmodesꢀ

•ꢀ Transmissionꢀcompleteꢀﬂagꢀ

•ꢀ Risingꢀorꢀfallingꢀactiveꢀclockꢀedgeꢀ

TheꢀstatusꢀofꢀtheꢀSPIꢀinterfaceꢀpinsꢀisꢀdeterminedꢀbyꢀaꢀnumberꢀofꢀfactorsꢀsuchꢀasꢀwhetherꢀtheꢀdeviceꢀ

isꢀinꢀtheꢀmasterꢀorꢀslaveꢀmodeꢀandꢀuponꢀtheꢀconditionꢀofꢀcertainꢀcontrolꢀbitsꢀsuchꢀasꢀCSENꢀandꢀ

SIMEN.ꢀ

Rev. 1.10

133

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

SPI Registers

ThereꢀareꢀthreeꢀinternalꢀregistersꢀwhichꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀSPIꢀinterface.ꢀTheseꢀareꢀ

theꢀSIMDꢀdataꢀregisterꢀandꢀtwoꢀregistersꢀSIMC0ꢀandꢀSIMC2.ꢀNoteꢀthatꢀtheꢀSIMC1ꢀregisterꢀisꢀonlyꢀ

usedꢀbyꢀtheꢀI²Cꢀinterface.

Bit

Register

Name

7

SIMꢅ

D7

6

SIM1

D6

5

4

3

2

1

0

SIMC0

SIMD

SIM0

D5

—

Dꢃ

SIMDEB1

D3

SIMDEB0

Dꢅ

SIMEN SIMICF

D1

D0

SIMCꢅ

D7

D6

CKPOLB CKEG

MLS

CSEN

WCOL

TRF

SIM Registers List

TheꢀSIMDꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceived.ꢀTheꢀsameꢀregisterꢀisꢀusedꢀ

byꢀbothꢀtheꢀSPIꢀandꢀI²Cꢀfunctions.ꢀBeforeꢀtheꢀdeviceꢀwritesꢀdataꢀtoꢀtheꢀSPIꢀbus,ꢀtheꢀactualꢀdataꢀtoꢀ

beꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSIMDꢀregister.ꢀAfterꢀtheꢀdataꢀisꢀreceivedꢀfromꢀtheꢀSPIꢀbus,ꢀtheꢀ

deviceꢀcanꢀreadꢀitꢀfromꢀtheꢀSIMDꢀregister.ꢀAnyꢀtransmissionꢀorꢀreceptionꢀofꢀdataꢀfromꢀtheꢀSPIꢀbusꢀ

mustꢀbeꢀmadeꢀviaꢀtheꢀSIMDꢀregister.

• SIMD Register

Bit

Name

R/W

7

D7

R/W

x

6

D6

R/W

x

5

D5

R/W

x

4

Dꢃ

R/W

x

3

D3

R/W

x

2

Dꢅ

R/W

x

1

D1

R/W

x

0

D0

R/W

POR

x

“x” ꢀnknown

ThereꢀareꢀalsoꢀtwoꢀcontrolꢀregistersꢀforꢀtheꢀSPIꢀinterface,ꢀSIMC0ꢀandꢀSIMC2.ꢀNoteꢀthatꢀtheꢀSIMC2ꢀ

registerꢀalsoꢀhasꢀtheꢀnameꢀSIMAꢀwhichꢀisꢀusedꢀbyꢀtheꢀI²Cꢀfunction.ꢀTheꢀSIMC1ꢀregisterꢀisꢀnotꢀusedꢀ

byꢀtheꢀSPIꢀfunction,ꢀonlyꢀbyꢀtheꢀI²Cꢀfunction.ꢀRegisterꢀSIMC0ꢀisꢀusedꢀtoꢀcontrolꢀtheꢀenable/disableꢀ

functionꢀandꢀtoꢀsetꢀtheꢀdataꢀtransmissionꢀclockꢀfrequency.ꢀAlthoughꢀnotꢀconnectedꢀwithꢀtheꢀSPIꢀ

function,ꢀtheꢀSIMC0ꢀregisterꢀisꢀalsoꢀusedꢀtoꢀcontrolꢀtheꢀPeripheralꢀClockꢀPrescaler.ꢀRegisterꢀSIMC2ꢀ

isꢀusedꢀforꢀotherꢀcontrolꢀfunctionsꢀsuchꢀasꢀLSB/MSBꢀselection,ꢀwriteꢀcollisionꢀﬂagꢀetc.

• SIMC0 Register

Bit

Name

R/W

7

SIMꢅ

R/W

1

6

SIM1

R/W

1

5

SIM0

R/W

1

4

3

SIMDEB1

R/W

2

SIMDEB0

R/W

1

SIMEN

R/W

0

SIMICF

R/W

0

—

POR

0

Bitꢀ7~5

SIM2~SIM0:ꢀSIMꢀOperatingꢀModeꢀControl

000:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀf_SYS/4

001:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀf_SYS/16

010:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀf_SYS/64

011:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀf_SUB

100:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀPTM2ꢀCCRPꢀmatchꢀfrequency/2

101:ꢀSPIꢀslaveꢀmode

110:ꢀI²Cꢀslaveꢀmode

111:ꢀUnusedꢀmode

TheseꢀbitsꢀsetupꢀtheꢀoverallꢀoperatingꢀmodeꢀofꢀtheꢀSIMꢀfunction.ꢀAsꢀwellꢀasꢀselectingꢀ

ifꢀtheꢀI²CꢀorꢀSPIꢀfunction,ꢀtheyꢀareꢀusedꢀtoꢀcontrolꢀtheꢀSPIꢀMaster/Slaveꢀselectionꢀandꢀ

theꢀSPIꢀMasterꢀclockꢀfrequency.ꢀTheꢀSPIꢀclockꢀisꢀaꢀfunctionꢀofꢀtheꢀsystemꢀclockꢀbutꢀ

canꢀalsoꢀbeꢀchosenꢀtoꢀbeꢀsourcedꢀfromꢀtheꢀPTM2.ꢀIfꢀtheꢀSPIꢀSlaveꢀModeꢀisꢀselectedꢀ

thenꢀtheꢀclockꢀwillꢀbeꢀsuppliedꢀbyꢀanꢀexternalꢀMasterꢀdevice.

Bitꢀ4ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

Rev. 1.10

13ꢃ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Bitꢀ3~2

Bitꢀ1

SIMDEB[1:0]:ꢀI²CꢀDebounceꢀTimeꢀSelection

TheꢀSIMDEB[1:0]ꢀbitsꢀareꢀofꢀnoꢀusedꢀinꢀSPIꢀmodeꢀofꢀSIM,ꢀpleaseꢀignoreꢀtheseꢀ

selectionꢀbitsꢀwhenꢀoperateꢀinꢀSPIꢀmode.

SIMEN:ꢀSIMꢀControl

0:ꢀDisable

1:ꢀEnable

Theꢀbitꢀisꢀtheꢀoverallꢀon/offꢀcontrolꢀforꢀtheꢀSIMꢀinterface.ꢀWhenꢀtheꢀSIMENꢀbitꢀisꢀ

clearedꢀtoꢀ“0”ꢀtoꢀdisableꢀtheꢀSIMꢀinterface,ꢀtheꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCS,ꢀorꢀSDAꢀ

andꢀSCLꢀlinesꢀwillꢀbeꢀinꢀaꢀﬂoatingꢀconditionꢀandꢀtheꢀSIMꢀoperatingꢀcurrentꢀwillꢀbeꢀ

reducedꢀtoꢀaꢀminimumꢀvalue.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀSIMꢀinterfaceꢀisꢀenabled.ꢀTheꢀ

SIMꢀconﬁgurationꢀoptionꢀmustꢀhaveꢀﬁrstꢀenabledꢀtheꢀSIMꢀinterfaceꢀforꢀthisꢀbitꢀtoꢀbeꢀ

effective.ꢀIfꢀtheꢀSIMꢀisꢀconﬁguredꢀtoꢀoperateꢀasꢀanꢀSPIꢀinterfaceꢀviaꢀtheꢀSIM2~SIM0ꢀ

bits,ꢀtheꢀcontentsꢀofꢀtheꢀSPIꢀcontrolꢀregistersꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀwhenꢀ

theꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀshouldꢀthereforeꢀbeꢀﬁrstꢀinitialisedꢀbyꢀ

theꢀapplicationꢀprogram.ꢀIfꢀtheꢀSIMꢀisꢀconﬁguredꢀtoꢀoperateꢀasꢀanꢀI²Cꢀinterfaceꢀviaꢀtheꢀ

SIM2~SIM0ꢀbitsꢀandꢀtheꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀtheꢀcontentsꢀofꢀtheꢀI²Cꢀ

controlꢀbitsꢀsuchꢀasꢀHTXꢀandꢀTXAKꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀandꢀshouldꢀ

thereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀtheꢀapplicationꢀprogramꢀwhileꢀtheꢀrelevantꢀI²Cꢀflagsꢀ

suchꢀasꢀHCF,ꢀHAAS,ꢀHBB,ꢀSRWꢀandꢀRXAKꢀwillꢀbeꢀsetꢀtoꢀtheirꢀdefaultꢀstates.

Bitꢀ0

SIMICF:ꢀSIMꢀSPIꢀIncompleteꢀFlag

0:ꢀSIMꢀSPIꢀincompletedꢀisꢀnotꢀoccurred

1:ꢀSIMꢀSPIꢀincompletedꢀisꢀoccurred

TheꢀSIMICFꢀbitꢀisꢀdeterminedꢀbyꢀSCSꢀpin.ꢀWhenꢀSCSꢀpinꢀisꢀsetꢀhigh,ꢀitꢀwillꢀclearꢀtheꢀ

SPIꢀcounter.ꢀMeanwhile,ꢀtheꢀinterruptꢀisꢀoccurredꢀandꢀtheꢀincompleteꢀﬂag,ꢀSIMICF,ꢀisꢀ

setꢀhigh.

• SIMC2 Register

Bit

Name

R/W

7

D7

R/W

0

6

D6

R/W

0

5

CKPOLB

R/W

4

CKEG

R/W

0

3

2

CSEN

R/W

0

1

WCOL

R/W

0

MLS

R/W

0

TRF

R/W

0

POR

0

Bitꢀ7~6ꢀ

Bitꢀ5

D7~D6:ꢀUndeﬁnedꢀbit

Thisꢀbitꢀcanꢀbeꢀreadꢀorꢀwrittenꢀbyꢀuserꢀsoftwareꢀprogram.

CKPOLB:ꢀDeterminesꢀtheꢀBaseꢀConditionꢀofꢀtheꢀClockꢀLine

0:ꢀTheꢀSCKꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive

1:ꢀTheꢀSCKꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive

TheꢀCKPOLBꢀbitꢀdeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀ

thenꢀtheꢀSCKꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀCKPOLBꢀbitꢀisꢀ

low,ꢀthenꢀtheꢀSCKꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.

Bitꢀ4

CKEG:ꢀDeterminesꢀSPIꢀSCKꢀActiveꢀClockꢀEdgeꢀType

CKPOLB=0

0:ꢀSCKꢀisꢀhighꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀrisingꢀedge

1:ꢀSCKꢀisꢀhighꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀfallingꢀedge

CKPOLB=1

0:ꢀSCKꢀisꢀlowꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀfallingꢀedge

1:ꢀSCKꢀisꢀlowꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀrisingꢀedge

TheꢀCKEGꢀandꢀCKPOLBꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀwayꢀthatꢀtheꢀclockꢀsignalꢀoutputsꢀ

andꢀinputsꢀdataꢀonꢀtheꢀSPIꢀbus.ꢀTheseꢀtwoꢀbitsꢀmustꢀbeꢀconﬁguredꢀbeforeꢀdataꢀtransferꢀ

isꢀexecutedꢀotherwiseꢀanꢀerroneousꢀclockꢀedgeꢀmayꢀbeꢀgenerated.ꢀTheꢀCKPOLBꢀbitꢀ

determinesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀthenꢀtheꢀSCKꢀlineꢀ

willꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀCKPOLBꢀbitꢀisꢀlow,ꢀthenꢀtheꢀSCKꢀ

lineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀTheꢀCKEGꢀbitꢀdeterminesꢀactiveꢀclockꢀ

edgeꢀtypeꢀwhichꢀdependsꢀuponꢀtheꢀconditionꢀofꢀCKPOLBꢀbit.

Rev. 1.10

135

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Bitꢀ3

Bitꢀ2

MLS:ꢀSPIꢀDataꢀShiftꢀOrder

0:ꢀLSB

1:ꢀMSB

Thisꢀisꢀtheꢀdataꢀshiftꢀselectꢀbitꢀandꢀisꢀusedꢀtoꢀselectꢀhowꢀtheꢀdataꢀisꢀtransferred,ꢀeitherꢀ

MSBꢀorꢀLSBꢀﬁrst.ꢀSettingꢀtheꢀbitꢀhighꢀwillꢀselectꢀMSBꢀﬁrstꢀandꢀlowꢀforꢀLSBꢀﬁrst.

CSEN:ꢀSPIꢀSCSꢀPinꢀControl

0:ꢀDisable

1:ꢀEnable

TheꢀCSENꢀbitꢀisꢀusedꢀasꢀanꢀenable/disableꢀforꢀtheꢀSCSꢀpin.ꢀIfꢀthisꢀbitꢀisꢀlow,ꢀthenꢀtheꢀ

SCSꢀpinꢀwillꢀbeꢀdisabledꢀandꢀplacedꢀintoꢀaꢀﬂoatingꢀcondition.ꢀIfꢀtheꢀbitꢀisꢀhighꢀtheꢀSCSꢀ

pinꢀwillꢀbeꢀenabledꢀandꢀusedꢀasꢀaꢀselectꢀpin.

Bitꢀ1

Bitꢀ0

WCOL:ꢀSPIꢀWriteꢀCollisionꢀFlag

0:ꢀNoꢀcollision

1:ꢀCollision

TheꢀWCOLꢀﬂagꢀisꢀusedꢀtoꢀdetectꢀifꢀaꢀdataꢀcollisionꢀhasꢀoccurred.ꢀIfꢀthisꢀbitꢀisꢀhighꢀitꢀ

meansꢀthatꢀdataꢀhasꢀbeenꢀattemptedꢀtoꢀbeꢀwrittenꢀtoꢀtheꢀSIMDꢀregisterꢀduringꢀaꢀdataꢀ

transferꢀoperation.ꢀThisꢀwritingꢀoperationꢀwillꢀbeꢀignoredꢀifꢀdataꢀisꢀbeingꢀtransferred.ꢀ

Theꢀbitꢀcanꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.ꢀ

TRF:ꢀSPIꢀTransmit/ReceiveꢀCompleteꢀFlag

0:ꢀDataꢀisꢀbeingꢀtransferred

1:ꢀSPIꢀdataꢀtransmissionꢀisꢀcompleted

TheꢀTRFꢀbitꢀisꢀtheꢀTransmit/ReceiveꢀCompleteꢀﬂagꢀandꢀisꢀsetꢀhighꢀautomaticallyꢀwhenꢀ

anꢀSPIꢀdataꢀtransmissionꢀisꢀcompleted,ꢀbutꢀmustꢀclearedꢀtoꢀ“0”ꢀbyꢀtheꢀapplicationꢀ

program.ꢀItꢀcanꢀbeꢀusedꢀtoꢀgenerateꢀanꢀinterrupt.

SPI Communication

AfterꢀtheꢀSPIꢀinterfaceꢀisꢀenabledꢀbyꢀsettingꢀtheꢀSIMENꢀbitꢀhigh,ꢀthenꢀinꢀtheꢀMasterꢀMode,ꢀwhenꢀ

dataꢀisꢀwrittenꢀtoꢀtheꢀSIMDꢀregister,ꢀtransmission/receptionꢀwillꢀbeginꢀsimultaneously.ꢀWhenꢀtheꢀ

dataꢀtransferꢀisꢀcomplete,ꢀtheꢀTRFꢀflagꢀwillꢀbeꢀsetꢀautomatically,ꢀbutꢀmustꢀbeꢀclearedꢀusingꢀtheꢀ

applicationꢀprogram.ꢀInꢀtheꢀSlaveꢀMode,ꢀwhenꢀtheꢀclockꢀsignalꢀfromꢀtheꢀmasterꢀhasꢀbeenꢀreceived,ꢀ

anyꢀdataꢀinꢀtheꢀSIMDꢀregisterꢀwillꢀbeꢀtransmittedꢀandꢀanyꢀdataꢀonꢀtheꢀSDIꢀpinꢀwillꢀbeꢀshiftedꢀintoꢀ

theꢀSIMDꢀregister.ꢀTheꢀmasterꢀshouldꢀoutputꢀanꢀSCSꢀsignalꢀtoꢀenableꢀtheꢀslaveꢀdeviceꢀbeforeꢀaꢀ

clockꢀsignalꢀisꢀprovided.ꢀTheꢀslaveꢀdataꢀtoꢀbeꢀtransferredꢀshouldꢀbeꢀwellꢀpreparedꢀatꢀtheꢀappropriateꢀ

momentꢀrelativeꢀtoꢀtheꢀSCSꢀsignalꢀdependingꢀuponꢀtheꢀconﬁgurationsꢀofꢀtheꢀCKPOLBꢀbitꢀandꢀCKEGꢀ

bit.ꢀTheꢀaccompanyingꢀtimingꢀdiagramꢀshowsꢀtheꢀrelationshipꢀbetweenꢀtheꢀslaveꢀdataꢀandꢀSCSꢀsignalꢀ

forꢀvariousꢀconﬁgurationsꢀofꢀtheꢀCKPOLBꢀandꢀCKEGꢀbits.

TheꢀSPIꢀwillꢀcontinueꢀtoꢀfunctionꢀinꢀspecialꢀIDLEꢀModesꢀifꢀtheꢀclockꢀsourceꢀusedꢀbyꢀtheꢀSPIꢀ

interfaceꢀisꢀstillꢀactive.

Rev. 1.10

136

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

SIMEN=1ꢄ CSEN=0 (Exteꢁnal Pꢀll-high)

SCS

SIMENꢄ CSEN=1

SCK (CKPOLB=1ꢄ CKEG=0)

SCK (CKPOLB=0ꢄ CKEG=0)

SCK (CKPOLB=1ꢄ CKEG=1)

SCK (CKPOLB=0ꢄ CKEG=1)

SDO (CKEG=0)

D7/D0 D6/D1 D5/Dꢅ Dꢃ/D3 D3/Dꢃ Dꢅ/D5 D1/D6 D0/D7

SDO (CKEG=1)

SDI Data Captꢀꢁe

Wꢁite to SIMD

SPI Master Mode Timing

SCS

SCK (CKPOLB=1)

SCK (CKPOLB=0)

SDO

D7/D0 D6/D1 D5/Dꢅ Dꢃ/D3 D3/Dꢃ Dꢅ/D5 D1/D6 D0/D7

SDI Data Captꢀꢁe

Wꢁite to SIMD

(SDO does not change ꢀntil fiꢁst SCK edge)

SPI Slave Mode Timing – CKEG=0

SCS

SCK (CKPOLB=1)

SCK (CKPOLB=0)

SDO

D7/D0 D6/D1 D5/Dꢅ Dꢃ/D3 D3/Dꢃ Dꢅ/D5 D1/D6 D0/D7

SDI Data Captꢀꢁe

Wꢁite to SIMD

(SDO changes as soon as wꢁiting occꢀꢁs; SDO is floating if SCS=1)

Note: Foꢁ SPI slave modeꢄ if SIMEN=1 and CSEN=0ꢄ SPI is alwaꢂs enabled

and ignoꢁes the SCS level.

SPI Slave Mode Timing – CKEG=1

Rev. 1.10

137

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

SPI Tꢁansfeꢁ

A

Wꢁite Data

Cleaꢁ WCOL

into SIMD

Masteꢁ

Slave

Masteꢁ oꢁ Slave

?

Y

WCOL=1?

SIM[ꢅ:0]=000ꢄ 001ꢄ

010ꢄ 011 oꢁ 100

SIM[ꢅ:0]=101

N

Tꢁansmission

N

completed?

(TRF=1?)

Configꢀꢁe CKPOLBꢄ

CKEGꢄ CSEN and MLS

Y

Read Data

fꢁom SIMD

SIMEN=1

A

Cleaꢁ TRF

N

Tꢁansfeꢁ finished?

Y

END

SPI Transfer Control Flowchart

Rev. 1.10

13ꢆ

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

I²C Interface

TheꢀI²Cꢀinterfaceꢀisꢀusedꢀtoꢀcommunicateꢀwithꢀexternalꢀperipheralꢀdevicesꢀsuchꢀasꢀsensorsꢀetc.ꢀ

OriginallyꢀdevelopedꢀbyꢀPhilips,ꢀitꢀisꢀaꢀtwoꢀlineꢀlowꢀspeedꢀserialꢀinterfaceꢀforꢀsynchronousꢀserialꢀ

dataꢀtransfer.ꢀTheꢀadvantageꢀofꢀonlyꢀtwoꢀlinesꢀforꢀcommunication,ꢀrelativelyꢀsimpleꢀcommunicationꢀ

protocolꢀandꢀtheꢀabilityꢀtoꢀaccommodateꢀmultipleꢀdevicesꢀonꢀtheꢀsameꢀbusꢀhasꢀmadeꢀitꢀanꢀextremelyꢀ

popularꢀinterfaceꢀtypeꢀforꢀmanyꢀapplications.

VDD

SDA

SCL

Device

Slave

Device

Masteꢁ

Device

Slave

I²C Master/Slave Bus Connection

I²C Interface Operation

TheꢀI²Cꢀserialꢀinterfaceꢀisꢀaꢀtwoꢀlineꢀinterface,ꢀaꢀserialꢀdataꢀline,ꢀSDA,ꢀandꢀserialꢀclockꢀline,ꢀSCL.ꢀAsꢀ

manyꢀdevicesꢀmayꢀbeꢀconnectedꢀtogetherꢀonꢀtheꢀsameꢀbus,ꢀtheirꢀoutputsꢀareꢀbothꢀopenꢀdrainꢀtypes.ꢀ

Forꢀthisꢀreasonꢀitꢀisꢀnecessaryꢀthatꢀexternalꢀpull-highꢀresistorsꢀareꢀconnectedꢀtoꢀtheseꢀoutputs.ꢀNoteꢀ

thatꢀnoꢀchipꢀselectꢀlineꢀexists,ꢀasꢀeachꢀdeviceꢀonꢀtheꢀI²Cꢀbusꢀisꢀidentiﬁedꢀbyꢀaꢀuniqueꢀaddressꢀwhichꢀ

willꢀbeꢀtransmittedꢀandꢀreceivedꢀonꢀtheꢀI²Cꢀbus.ꢀ

WhenꢀtwoꢀdevicesꢀcommunicateꢀwithꢀeachꢀotherꢀonꢀtheꢀbidirectionalꢀI²Cꢀbus,ꢀoneꢀisꢀknownꢀasꢀtheꢀ

masterꢀdeviceꢀandꢀoneꢀasꢀtheꢀslaveꢀdevice.ꢀBothꢀmasterꢀandꢀslaveꢀcanꢀtransmitꢀandꢀreceiveꢀdata;ꢀ

however,ꢀitꢀisꢀtheꢀmasterꢀdeviceꢀthatꢀhasꢀoverallꢀcontrolꢀofꢀtheꢀbus.ꢀForꢀtheꢀdevices,ꢀwhichꢀonlyꢀ

operateꢀinꢀslaveꢀmode,ꢀthereꢀareꢀtwoꢀmethodsꢀofꢀtransferringꢀdataꢀonꢀtheꢀI²Cꢀbus,ꢀtheꢀslaveꢀtransmitꢀ

modeꢀandꢀtheꢀslaveꢀreceiveꢀmode.ꢀTheꢀpull-upꢀcontrolꢀfunctionꢀpin-sharedꢀwithꢀSCL/SDAꢀpinꢀisꢀstillꢀ

applicableꢀevenꢀifꢀI²Cꢀdeviceꢀisꢀactivatedꢀandꢀtheꢀrelatedꢀinternalꢀpull-upꢀregisterꢀcouldꢀbeꢀcontrolledꢀ

byꢀitsꢀcorrespondingꢀpull-upꢀcontrolꢀregister.

Data Bꢀs

I^ꢅC Data Registeꢁ

(SIMD)

I^ꢅC Addꢁess Registeꢁ

(SIMA)

Addꢁess Match–HAAS

Addꢁess

I^ꢅC Inteꢁꢁꢀpt

Diꢁection Contꢁol

HTX

Compaꢁatoꢁ

f_SYS

SCL Pin

SDA Pin

Deboꢀnce

Ciꢁcꢀitꢁꢂ

Data in MSB

Shift Registeꢁ

Read/Wꢁite Slave

SRW

M

U

X

Data oꢀt MSB

TXAK

SIMDEB[1:0]

ꢆ-bit Data Tꢁansfeꢁ Conplete–HCF

Tꢁansmit/Receive

Contꢁol Unit

Detect Staꢁt oꢁ Stop

HBB

SIMTOF

f_SUB

SIMTOEN

Time-oꢀt Contꢁol

Addꢁess Match

I²C Block Diagram

Rev. 1.10

139

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

START signal

fꢁom Masteꢁ

Send slave addꢁess

and R/W bit fꢁom Masteꢁ

Acknowledge

fꢁom slave

Send data bꢂte

fꢁom Masteꢁ

Acknowledge

fꢁom slave

STOP signal

fꢁom Masteꢁ

I²C Registers

ThereꢀareꢀthreeꢀcontrolꢀregistersꢀassociatedꢀwithꢀtheꢀI²Cꢀbus,ꢀSIMC0,ꢀSIMC1ꢀandꢀSIMTOC,ꢀoneꢀ

addressꢀregister,ꢀSIMAꢀandꢀoneꢀdataꢀregister,ꢀSIMD.ꢀTheꢀSIMDꢀregister,ꢀwhichꢀisꢀshownꢀinꢀtheꢀ

aboveꢀSPIꢀsection,ꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceivedꢀonꢀtheꢀI²Cꢀbus.ꢀNoteꢀthatꢀ

theꢀSIMAꢀregisterꢀalsoꢀhasꢀtheꢀnameꢀSIMC2ꢀwhichꢀisꢀusedꢀbyꢀtheꢀSPIꢀfunction.ꢀBitꢀSIMENꢀandꢀbitsꢀ

SIM2~SIM0ꢀinꢀregisterꢀSIMC0ꢀareꢀusedꢀbyꢀtheꢀI²Cꢀinterface.ꢀTheꢀSIMTOCꢀregisterꢀisꢀusedꢀforꢀI²Cꢀ

time-outꢀcontrol.

Bit

Register

Name

7

6

5

4

—

3

2

1

0

SIMICF

RXAK

D0

SIMC0

SIMC1

SIMD

SIMꢅ

HCF

D7

SIM1

HAAS

D6

SIM0

HBB

D5

SIMDEB1 SIMDEB0 SIMEN

HTX

Dꢃ

A3

TXAK

D3

SRW

Dꢅ

IAMWU

D1

SIMA

A6

A5

Aꢃ

Aꢅ

A1

A0

D0

SIMTOC SIMTOEN SIMTOF SIMTOS5 SIMTOSꢃ SIMTOS3 SIMTOSꢅ SIMTOS1 SIMTOS0

I²C Register List

• SIMC0 Register

Bit

Name

R/W

7

SIMꢅ

R/W

1

6

SIM1

R/W

1

5

SIM0

R/W

1

4

3

2

1

SIMEN

R/W

0

SIMICF

R/W

0

—

SIMDEB1 SIMDEB0

R/W

0

R/W

0

POR

Bitꢀ7~5

SIM2~SIM0:ꢀSIMꢀOperatingꢀModeꢀControl

000:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀf_SYS/4

001:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀf_SYS/16

010:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀf_SYS/64

011:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀf_SUB

100:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀPTM2ꢀCCRPꢀmatchꢀfrequency/2

101:ꢀSPIꢀslaveꢀmode

110:ꢀI²Cꢀslaveꢀmode

111:ꢀUnusedꢀmode

TheseꢀbitsꢀsetupꢀtheꢀoverallꢀoperatingꢀmodeꢀofꢀtheꢀSIMꢀfunction.ꢀAsꢀwellꢀasꢀselectingꢀ

ifꢀtheꢀI²CꢀorꢀSPIꢀfunction,ꢀtheyꢀareꢀusedꢀtoꢀcontrolꢀtheꢀSPIꢀMaster/Slaveꢀselectionꢀandꢀ

theꢀSPIꢀMasterꢀclockꢀfrequency.ꢀTheꢀSPIꢀclockꢀisꢀaꢀfunctionꢀofꢀtheꢀsystemꢀclockꢀbutꢀ

canꢀalsoꢀbeꢀchosenꢀtoꢀbeꢀsourcedꢀfromꢀtheꢀPTM2.ꢀIfꢀtheꢀSPIꢀSlaveꢀModeꢀisꢀselectedꢀ

thenꢀtheꢀclockꢀwillꢀbeꢀsuppliedꢀbyꢀanꢀexternalꢀMasterꢀdevice.

Rev. 1.10

1ꢃ0

�anꢀaꢁꢂ 0ꢃꢄ ꢅ01ꢆ

BH66F2650/BH66F2660

Body Fat Measurment Flash MCU

Bitꢀ4ꢀ

Unimplemented,ꢀreadꢀasꢀ“0”

Bitꢀ3~2

SIMDEB1~SIMDEB0:ꢀI²CꢀDebounceꢀTimeꢀSelection

00:ꢀNoꢀdebounce

01:ꢀ2ꢀsystemꢀclockꢀdebounce

1x:ꢀ4ꢀsystemꢀclockꢀdebounce