HT0610_技术文档

HT0610

33´120 LCD Driver

Features

·

Operating voltage: 2.4V~3.5V

External contrast control

33 common/120 segment LCD driver output

Low power icon mode driven by com32

Four static icon driver circuit

33´120=3960 bits capacity of built-in graphic display

data RAM (BGDRAM)

High accuracy voltage regulator with temperature co-

efficient (0.00%, -0.18%, -0.22%, -0.35%)

Low power consumption

·

Master and slave mode available for multi-chip

operation

·

-

8-bit Parallel interface with general MCU

Read/write mode 170mA (Typical)

Display mode 160mA (Typical)

Standby mode 15mA (Typical; Display off; internal

oscillator enable)

-

On-chip oscillator circuit for display clock, external

clock can also be used

-

·

Selectable multiplex ratio: 1/16, 1/32, 1/33

Selectable bias ratio: 1/5 or 1/7

-

Standby mode < 1mA (Typical; Display off; external

oscillator enable)

External driving circuit for external bias supply

On-chip selectable voltage doublers and tripler

Wide range of operating temperature: -30°C to 85°C

·

CMOS process

TCP available

S/W controlled electronic contrast control function

(16 levels)

General Description

The HT0610 is a driver and controller LSI for graphic

dot-matrix liquid crystal display systems. It has 33 com-

mon and 120 segment driver circuits. This chip is con-

nected directly to an MCU, accepts 8-bit parallel display

data and stores an on-chip graphic display data RAM

(BGDRAM) of 33´120 bits. It provides a high-flexible

display section due to the one-to-one correspondence

between BGDRAM bits and LCD panel pixels. It per-

forms BGDRAM read/write operation with no externally

operating clock to minimize power consumption. In ad-

dition, because it contains power supply circuits neces-

sary to drive an LCD, it is possible to make a display

system with minimal components.

Rev. 1.00

1

February 24, 2004

HT0610

Block Diagram

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Operation of LCD Driver

Description of block diagram module

Block

Description

This module determines whether the input data is interpreted as data or command.

Data is directed to this module based upon the input of the DCOM pin. If DCOM High,

then data is written to BGDRAM ( Built-in Graphic Display data RAM) . DCOM pin Low

indicates that the input at D0~D7 is interpreted as a Command.

CE is the master chip selection signal . A High input enable the input lines ready to sam-

ple signals.

Command Decoder and

Command Interface

RES pin of same function as Power On Reset (POR). Once RES received the reset sig-

nal, all internal circuitry will back to its initial status. Refer to Command Description

section for more information.

The parallel interface consists of 8 bi-directional data lines (D0~D7),RW, and CS. The

RW input High indicates a read operation from the BGDRAM . RW input Low indicates a

write to BGDRAM or Internal Command Registers depending on the status of DCOM

pin input.

Parallel Interface

The CS input serves as data latch signal (clock).

The BGDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The

size of the BGDRAM is determined by number of row times the number of column

(120´33 =3960 bits). Figure as follow is a description of the BGDRAM address map. For

mechanical flexibility, re-mapping on both Segment and Common outputs are provided

Built-in Graphic Display

data RAM (BGDRAM)

This module is an on chip low power RC oscillator circuitry. The oscillator frequency can

be selected in the range of 15kHz to 50kHz by external resistor. One can enable the cir-

cuitry by software command. For external clock provided, feed the clock to OSC2 and

leave OSC1 open.

Display Timing Generator

Rev. 1.00

2

February 24, 2004

HT0610

Block

Description

This module generates the LCD waveform of the 4 annunciators and IBP signal. The

Static Icon Control Circuit four independent static icons are enabled by software command. Icon signals are also

controlled by oscillator circuit, too.

This module generates the LCD voltage needed for display output. It takes a single sup-

ply input and generates necessary bias voltages. It consists of:

·

Voltage doubler and voltage tripler

To generate the VCCA1 voltage. Either doubler or tripler can be enabled.

·

Voltage regulator

Feedback gain control for initial LCD voltage. It can also be used with external contrast

control.

·

Voltage divider

Divide the LCD display voltage (VLL2~VLL6) from the regulator output. This is low

power consumption circuit, which can save the most display current compare with tra-

ditional resistor ladder method.

LCD Driving Voltage

Generator

·

Bias Ratio Selection circuitry

Software control of 1/5 and 1/7 bias ratios to match the characteristic of LCD panel.

Self adjust temperature compensation circuitry

Provide 4 different compensation grade selections to satisfy the various liquid crystal

temperature grades. The grading can be selected by software control.

·

Contrast Control Block

Software control of 16 voltage levels of LCD voltage.

External Contrast Control

By adjusting the gain control resistors connected externally, the contrast can be var-

ied.

All blocks can be individually turned off if external voltage generator is employed.

153 bit long registers, which carry the display signal information. First 33 bits are Com-

120 Bit Latch/33 Bit Latch mon driving signals and other 120 bits are Segment driving signals. Data will be input to

the HV-buffer Cell for bumping up to the required level.

Level selector is a control of the display synchronization. Display voltage can be sepa-

rated into two sets and used with different cycles. Synchronization is important since it

Level Selector

selects the required LCD voltage level to the HV Buffer Cell for output signal voltage

pump.

HV Buffer Cell works as a level shifter that translates the low voltage output signal to the

HV Buffer Cell

(Level Shifter)

required driving voltage. The output is shifted out with an internal FRM clock, which co-

mes from the Display Timing Generator. The voltage levels are given by the level selec-

tor which is synchronized with the internal M signal.

Rev. 1.00

3

February 24, 2004

HT0610

Pin Assignment

D

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1

9

7

6

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3

0

1

2

3

4

2

1

9

5

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4

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1

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3

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2

1

2

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4

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6

7

8

9

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3

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1

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2

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4

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5

6

7

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7

8

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6

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6

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5

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6

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2

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5

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6

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Rev. 1.00

4

February 24, 2004

HT0610

Pin Description

Pin Name

I/O

Description

VDD is the positive supply to the digital control circuit and other circuitry in LCD bias voltage

generator (Must have same voltage level with VDDA)

VDD

I

RES

VSS

I

Active low reset pin; reset all internal status of circuit (Same as power on reset)

VSS is ground

If pull this pin ²High² then D0~D7 bi-direction bus is used for data transferring; If DCOM pin is

²Low² then D0~D7 bi-direction bus is used for command transferring.

DCOM

RW

I

If pull this pin high: Indicate we want to read the display data RAM or the internal state. If we

force this to Low: Indicate we want to write data to display data RAM or write some internal

state to registers.

This pin is normal low clock input. Data on D0~D7 bi-direction data bus are latched at the fall-

ing edge of CS

CS

D0~D7

CE

B

I

Those bi-direction pins are used for DATA or command transferring.

High input to this pin to enable the control pins on the driver.

Oscillator input pin.

For internal oscillator mode, this is an input for the internal low power RC oscillator circuit. In

this mode, an external resistor of certain value is placed between the OSC1 and OSC2 pins.

For external oscillator mode, OSC1 pin should be left open

OSC1

OSC2

I

Oscillator output pin

For internal oscillator mode, this is an output for the internal low power RC oscillator circuit.

O

External Oscillator input

For external oscillator mode, OSC2 will be an input pin for external clock and no external resis-

tor is needed.

C1P, C1N

C2P, C2N

If internal DC/DC converter is enabled, a capacitor is required to connect these two pins.

¾

If internal tripler is enabled, a capacitor is required to connect these two pins. Otherwise, leave

these pin open.

Group of voltage level pins for driving the LCD panel. They can either be connected to external

driving circuit for external bias supply or connected internally to built-in divider circuit. For in-

ternal voltage divider enable, a 0.1mF capacitor to VSS is required on each pin.

VLL2~VLL6

O

If internal voltage divider is enable with 1/7 bias selected, a capacitor to VSS is required on

each pin. Otherwise, pull these two pin to VSS

DUM1, DUM2

C+, C-

O

¾

O

If internal divider circuit is enable, a capacitor is required to connect between these two pin

If internal DC/DC Converter is enabled, a 0.1mF capacitor from this pin to VSS is required. It

can also be an external bias input pin if internal DC/DC converter is not used

VCCA1

This is a feedback path for the gain control (external contrast control) of VLL1 to VLL6. For ad-

justing the LCD driving voltage, it requires a feedback resistor placed between VR and VF, a

gain control resistor placed between VF and VSS, a 10uF capacitor placed between VR and

VSS.

VF, VR

¾

COM0~COM32

VDDA

O

I

These pins provide the row driving signal to LCD panel

VDDA is the positive supply to the noise sensitive circuitry and must have same voltage level

with VDD

ICON1~ICON4

IBP

O

There are four independent annunciator driving outputs

This pin combines with ICON1~ICON4 pins to form annunciator driving part.

These 120 pins provide LCD column driving signal to LCD panel.

SEG0~SEG119

Rev. 1.00

5

February 24, 2004

HT0610

Absolute Maximum Ratings

Supply Voltage ........................................-0.3V to 4.0V

Input Voltage .............................V_SS-0_.3V to V_DD+0.3V

LCD Input Voltage..................................-0.3V to 10.5V

Storage Temperature ...........................-65°C to 150°C

Operating Temperature ..........................-30°C to 85°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

HT0610 contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it

is advised that normal precaution to be taken to avoid application of any voltage higher than maximum rated voltages to

this high impedance circuit . For proper operation it is recommended that V_INand Vout be constrained to the range VSS

< or = (V_INor V_OUT) < or = VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate

logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive?

caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not

radiation protected.

Electrical Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min. Typ.

Max. Unit

V_DD

Supply voltage

2.4V~

3.5V

V_DD

Operating Voltage

VDDA=VDD

2.4

3.15

3.5

V

Supply Current

Measure with VDD fixed at

3.15V

Read/write Mode

Internal DC/DC converter on,

display on, tripler enable,

read/write accessing,

2.4V~

3.5V

I_RW

Supply Current Drain from Pin VDDA

and VDD

120

170

200

mA

t_CYC=1MHz, Osc freq.=50kHz,

1/33 duty, 1/7 bias

Internal DC/DC converter on,

display on, tripler enable,

read/write HALT,

Display on Mode

2.4V~

3.5V

I_ON1

Supply Current Drain from Pin VDDA

and VDD

130

140

110

100

140

120

mA

Osc freq.=50kHz, 1/33 duty,

1/7 bias

Internal DC/DC converter on,

display on, tripler enable,

read/write HALT,

Display on Mode

2.4V~

3.5V

I_ON2

Supply Current Drain from Pin VDDA

and VDD

Osc freq.=38.4kHz, 1/33 duty,

1/7 bias

Standby Mode Supply Current Drain 2.4V~ Display off, oscillator disabled,

from Pin VDDA and VDD 3.5V read/write HALT

I_STB1

300

0.6

500

1

nA

¾

Display off, oscillator enabled,

read/write HALT, external os-

cillator and frequency=50kHz

Standby Mode Supply Current Drain 2.4V~

from Pin VDDA and VDD 3.5V

I_STB2

mA

Display off, oscillator enabled,

read/write HALT, internal oscil-

lator and frequency=50kHz

Standby Mode Supply Current Drain 2.4V~

from Pin VDDA and VDD 3.5V

I_STB3

23

25

30

¾

mA

Low power I_CONmode, oscilla-

Standby Mode Supply Current Drain 2.4V~ tor enable, read/write HALT,

I_ICON

from Pin VDDA and VDD

3.5V internal oscillator and fre-

quency=50kHz

Rev. 1.00

6

February 24, 2004

HT0610

Test Conditions

Conditions

Symbol

Parameter

Min. Typ.

Max. Unit

V_DD

VLCD voltage (Absolute value referenced to VSS)

Display on, internal DC/DC

converter enable, tripler en-

able, oscillator and fre-

quency=50kHz, regulator

enable, divider enable

I_OUT£100mA

LCD Driving Voltage

2.4V~

V_LCC1

Generator Output Voltage at Pin

VCCA1

10.5

V

¾

3´VDD

2´VDD

3.5V

Display on, internal DC/DC

converter enable, doubler en-

able, oscillator and fre-

quency=50kHz, regulator

enable, divider enable

I_OUT£100mA

LCD Driving Voltage

Generator Output Voltage at Pin

VCCA1

2.4V~

3.5V

V_LCC2

7

V

¾

LCD Driving Voltage Input at Pin 2.4V~ Internal DC/DC converter dis-

VCCA1 3.5V able

V_LCD

5

10.5

VDD

¾

Output voltage

Output High Voltage at Pin D0~D7, 2.4V~

0.8´

VDD

V_OH1

V_OL1

V_R1

I_OUT=100mA

V

ICON1~ICON4, IBP and OSC2

3.5V

Output Low Voltage at Pin D0~D7, 2.4V~

0.2´

VDD

I_OUT=100mA

0

¾

ICON1~ICON4, IBP and OSC2

3.5V

LCD Driving Voltage Source at Pin 2.4V~

Regulator enable, I_OUT=50mA

VCCA1

VR

3.5V

LCD Driving Voltage Source at Pin 2.4V~

V_R2

Regulator disable

Floating

¾

VR

3.5V

Input voltage

Input High Voltage at Pin RES, CE,

2.4V~

3.5V

0.8´

VDD

V_IH1

CS, D0~D7, RW, DCOM, OSC1 and

OSC2

VDD

V

¾

Input Low Voltage at Pin RES, CE,

CS, D0~D7, RW, DCOM, OSC1 and

OSC2

2.4V~

3.5V

0.2´

VDD

V_IL1

0

LCD display voltage

2.4V~

3.5V

V_LL6

VR

V

¾

2.4V~

3.5V

V_LL5

0.8´VR

0.6´VR

0.4´VR

0.2´VR

LCD Driving Voltage Output from Pin 2.4V~ 1/5 bias ratio, voltage divider

V_LL4

V_LL3

V_LL2

VLL6~VLL2

3.5V enable, regulator enable

2.4V~

3.5V

2.4V~

3.5V

Rev. 1.00

7

February 24, 2004

HT0610

Test Conditions

Conditions

Symbol

Parameter

Min. Typ.

Max. Unit

V_DD

2.4V~

3.5V

V_LL6

V_LL5

V_LL4

D_UM2

D_UM1

V_LL3

V_LL2

V_LL6

V_LL5

V_LL4

V_LL3

VR

6/7´VR

5/7´VR

4/7´VR

3/7´VR

2/7´VR

1/7´VR

¾

V

¾

2.4V~

3.5V

2.4V~

3.5V

¾

2.4V~ 1/7 bias ratio, voltage divider

3.5V enable, regulator enable

¾

2.4V~

3.5V

¾

2.4V~

3.5V

¾

2.4V~

3.5V

¾

2.4V~

3.5V

0.5´

VCCA1

2.4V~

3.5V

0.5´

¾

VCCA1

2.4V~ External voltage generator,

0.5´

¾

3.5V internal voltage divider disable VCCA1

2.4V~

0.5´

vss

¾

3.5V

VCCA1

2.4V~

0.5´

V_LL2

vss

¾

3.5V

VCCA1

Output Current

Output High Current Source from

Pins D0~D7, ICON1~ICON4, IBP

and OSC2

2.4V~

I_OH

V_OUT=VDD-0.1V

1.5

mA

¾

3.5V

Output Low Current Drain by Pins

D0~D7, ICON1~ICON4, IBP and

OSC2

2.4V~

3.5V

I_OL

V_OUT=0.1V

5

mA

¾

-1

¾

1

Output Tri-state Current Drain 2.4V~

I_OZ

¾

Source at Pins D0~D7 and OSC2

3.5V

Input Current at Pins RES, CE, CS,

D0~D7, RW, DCOM, OSC1 and

OSC2

2.4V~

3.5V

I_IL/I_IH

1

On resistance

Channel Resistance between LCD

During display on, 0.1V apply

Driving Signal Pins (Segment and 2.4V~ between two terminals,

Common) and Driving Voltage Input 3.5V VCCA1 within operating volt-

R_ON

5

¾

kW

Pins (VLL2 to VLL6)

age range

Memory Retention Voltage (VDD)

Standby Mode, Retained All Internal

Configuration and BGDRAM Data

2.4V~

3.5V

V_MR

1.8

V

¾

2.4V~

3.5V

C_IN

Input Capacitance All Control Pins

5

7.5

pF

¾

Rev. 1.00

8

February 24, 2004

HT0610

Test Conditions

Conditions

Symbol

Parameter

Min. Typ.

Max. Unit

V_DD

Temperature coefficient compensation

2.4V~ TC1=0, TC2=0,

3.5V regulator disable

PTC0

PTC1

PTC2

PTC3

Flat Temperature

Coefficient

0

%

¾

2.4V~ TC1=0, TC2=1,

3.5V regulator enable

-0.18

-0.22

-0.35

2.4V~ TC1=1, TC2=0,

3.5V regulator enable

Temperature Coefficient 1*

Temperature Coefficient 2*

Temperature Coefficient 3*

2.4V~ TC1=1, TC2=1,

3.5V regulator enable

Internal Contrast Control VR Output

Voltage with Internal Contrast Con-

trol Selected

Internal regulator enabled,

2.4V~

3.5V

V_CON

16 Voltage Levels Controlled by Soft-

ware

internal contrast control en-

abled

%

¾

±18

¾

Each Level is Typical of 2.25% of the

Regulator Output Voltage

Oscillator frequency

Oscillator Frequency of Display Tim-

2.4V~

3.5V

F_OSC1

F_OSC2

F_ICON1

F_ICON2

ing Generator with 60Hz Frame Fre-

quency

Set clock frequency to slow

Set clock frequency to normal

¾

38.4

50

kHz

Hz

¾

Oscillator Frequency of Display Tim-

ing Generator with 60Hz Frame Fre-

quency

2.4V~

3.5V

Four Static ICON Display (50% Duty

Cycle) from Pins ICON1~ICON4 and

IBP

2.4V~

3.5V

18.75

24.4

Four Static ICON Display (50% Duty

Cycle) from Pins ICON1~ICON4 and

IBP

2.4V~

3.5V

Hz

¾

Either external clock input or

LCD Driving Signal Frame

Frequency

2.4V~ internal oscillator enable, ei-

3.5V ther 1/32 or 1/16 duty cycle,

graphic display mode

F_FRAME1

F_FRAME2

F_CON1

66

65

64

63

Hz

¾

Either external clock input or

2.4V~

LCD Driving Signal Frame

Frequency

internal oscillator enable, ei-

3.5V

ther 1/32 or 1/16 duty cycle

Either external clock input or

2.4V~ internal oscillator enable, 1/33

3.5V duty cycle, graphic display

mode

LCD Driving Signal Frame

Frequency

Either external clock input or

LCD Driving Signal Frame

Frequency

2.4V~

F_CON2

internal oscillator enable, 1/33

3.5V

duty cycle

Internal oscillation frequency

Internal OSC Oscillation Frequency

O_SC

2.4V~ Internal oscillator enable

3.5V within operation range

with Different Value of Feedback Re-

sistor

See the figure as follow

Note:

o

VR at 50 C- VR at 0 C

1

* The formula for the temperature coefficient is: TC (%)=

´

´100%

o

VR at 25 C

50 C- 0 C

Rev. 1.00

9

February 24, 2004

HT0610

Total variation of VR D V_RTis affected by the following factors:

Process variation of regulator D V_R

External VDD variation contributed to regulator D V_VDD

External resistor pair Ra/Rf contributed to regulator D V_RES

2

Where D V_RT

=

DV_R

DV_VDD

DV_RES

Assume external VDD variation is ±6% at 3.15V and 1% variation resistor used at application

TC Level

TC0

D V_VDD(%)

±6.0

D V_R(%)

D V_RES(%)

D V_RT(%)

±6.652

±4.924

±3.805

±3.195

TC1

±4.0

Reference Generator

±2.5

±1.414

TC2

±2.5

TC3

±1.4

Parallel timing characteristics (Write cycle)

Ta=30°C~85°C, DV_DD=2.4V~3.5V, V_SS=0V

Symbol

t_CYCLE

Parameter

Enable Cycle Time

Min.

620

300

10

Typ.

¾

Max.

¾

Unit

ns

t_EH

t_AS

t_DS

t_DH

t_AH

Enable Pulse Width

Address Setup Time

Data Setup Time

Data Hold Time

ns

¾

ns

¾

300

30

ns

¾

ns

¾

Address Hold Time

30

ns

¾

C

E

t

C

Y

C

L

E

C

S

(

C

L

K

)

t

E

H

R

W

t

A

S

t

A H

D

C

O

M

t

D

S

t

D H

D

0

~

D

7

V

a

l

i

d

D

a

t

a

Timing characteristics (Write cycle)

Rev. 1.00

10

February 24, 2004

HT0610

Parallel timing characteristics (Read cycle)

Ta=30°C~85°C, DV_DD=2.4V~3.5V, V_SS=0V

Symbol

t_CYCLE

Parameter

Enable Cycle Time

Min.

620

300

10

Typ.

¾

Max.

¾

Unit

ns

t_EH

t_AS

t_DS

t_DH

t_AH

Enable Pulse Width

Address Setup Time

Data Setup Time

Data Hold Time

ns

¾

ns

¾

300

¾

ns

¾

10

ns

¾

Address Hold Time

30

ns

¾

C

E

t

C

Y

C

L

E

C

S

(

C

L

K

)

t

E

H

R

W

t

A

S

t

A H

D

C

O

M

t

D

S

t

D H

D

0

~

D

7

V

a

l

i

d

D

a

t

a

Timing characteristics (Read cycle)

Rev. 1.00

11

February 24, 2004

HT0610

Functional Description

3

2

1

0

5

0

5

0

5

0

1

0

K

1

5

0

K

2

0

K

2

4

0

K

3

0

K

3

6

0

K

4

3

0

K

5

1

0

K

5

6

0

K

6

2

0

K

6

8

0

K

7

5

0

K

8

2

0

K

9

1

0

K

1

M

1

.

5

M

2

.

0

M

R

e

s

i

s

t

o

r

v

a

l

u

e

o

n

O

S

C

1

&

O

S

C

2

(

Internal oscillator frequency relationship with different external resistor value

·

Set clock frequency to slow: F_FRAME1=F_OSC1/576

Set clock frequency to normal: F_FRAME2=F_OSC2/768

C

o

l

u

m

n

a

d

r

e

s

0

H

C

o

l

u

m

n

a

d

r

e

s

7

H

(

o

r

c

l

o

u

m

n

a

d

r

e

s

7

H

)

(

o

r

c

l

o

u

m

n

a

d

r

e

s

0

H

)

C

(

O

M

0

L

S

B

P

a

g

e

1

C

O

M

3

1

)

M

S

B

P

a

g

e

2

P

a

g

e

3

P

a

g

e

4

C

(

C

O

M

0

3

C

O

M

3

1

)

P

a

g

e

5

2

S

E

G

0

S

E

G

1

9

Built-in graphic display data RAM (BGDRAM) address map

Rev. 1.00

12

February 24, 2004

HT0610

Command

Description

The display on command turns the LCD common and segment outputs on and has

no effect to the static icons output. This command causes the conversion of data in

BGDRAM to necessary waveforms on the common and segment driving outputs.

The on-chip bias generator is also turned on by this command.

(Note: ²oscillator on² command should be sent before ²display on² is selected.)

The display off command turns the display off and the states of the LCD driver are

as follow during display off:

Set Display On/Off

(Display Mode/Standby Mode)

·

The common and segment outputs are fixed at VLL1(VSS)

The bias voltage generator is turned off.

·

The RAM and content of all register are retained.

IC will accept new commands and data.

The status of the static Icons and oscillator are not affected by display off com-

mand.

Set BGDRAM Page Address

Master Clear BGDRAM

This command positions the row address to 1 of 5 possible positions in BGDRAM.

This command is to clear the 480 byte BGDRAM by setting the RAM data to zero.

Issue this command followed by a dummy writes command. The RAM for icon line

will not be affected by this command.

This command is used to clear the data in page 5 of BGDRAM, which stores the

icon line data. Before using this command, set the page address to page 5 by the

command ²set BGDRAM page address². A dummy write data is also needed after

this ²master clear Icons² command to make the clear icon action effective.

Master Clear Icons

If 1/32 Mux selected, use this command change to 1/33 Mux for using the Icon line.

This command can also change Icon display mode to normal display mode (1/32 or

1/33 MUX).

Set Display with Icon Line

Set Icon Display Mode

This command forces the output to the icon display mode. Display on row 0 to row

31 will be disabled.

Set Icon Line/Static Icon

Contrast Level

The contrast of the icon line and static icon in icon mode can be set by this com-

mand. There are four levels to select from.

This command is used to scroll the screen vertically with scroll value 0 to 31. With

scroll value equals to 0, row 0 of BGDRAM is mapped to com 0 and row 1 through

row 31 are mapped to com 1 through com 31 respectively. With scroll value equal

to 1, row 1 of BGDRAM is mapped to com 0, then row 2 through row 31 will be

mapped to com 1 through com 30 respectively and row 0 will be mapped to com 31.

Com 32 is not affected by this command.

Set Vertical Scroll Value

With bit option=1 in this command, the save/restore column address command

saves a copy of the column address of BGDRAM. With a bit option=0, this com-

mand restores the copy obtained from the previous execution of saving column ad-

dress.

Save/Restore BGDRAM

Column Address

This instruction is very useful for writing full graphics characters that are larger than

8 pixels vertically.

This instruction selects the mapping of BGDRAM to segment drivers for mechani-

cal flexibility. There are 2 mappings to select:

·

Column 0~column 119 of BGDRAM mapped to SEG0~SEG119 respectively

Column 0~column 119 of BGDRAM mapped to SEG119~SEG0 respectively

Set Column Mapping

·

COM 32 will not be affected by this command. Detailed information please refer to

section ²display output description².

This instruction selects the mapping of BGDRAM to common drivers for mechani-

cal flexibility. There are 2 mappings to select:

·

Row 0~Row 31 of BGDRAM mapped to COM 0~COM 31 respectively.

Row 0~Row 31 of BGDRAM mapped to COM 31~COM 0 respectively.

Set Row Mapping

·

COM 32 will not be affected by this command. Detail information please refer to

section ²display output description².

Rev. 1.00

13

February 24, 2004

HT0610

Command

Description

This command is used to control the active states of the 4 stand-alone icons driv-

ers.

Set Static Icon Control Signal

This command is used to either disable or enable the oscillator. For using internal

or external oscillator, this command should be executed. The setting for this com-

mand is not affected by command ²set display on/off² and ²set static Icon control

signal². Refer to command ²set internal/external oscillator² for more information.

Set Oscillator Disable/Enable

This command is used to select either internal or external oscillator. When internal

Set Internal/External Oscillator oscillator is selected, feedback resistor between OSC1 and OSC2 is needed. For

external oscillation circuit, feed clock input signal to OSC2 and leaves OSC1 open.

Use this command to choose from two different oscillation frequency (50kHz or

38.4kHz) to get the 60Hz frame frequency.

Set Clock Frequency

With frequency high, 50kHz clock frequency is preferred. 38.4kHz clock frequency

(low frequency) enable for power saving purpose.

Use this command selects the internal DC/DC converter to generate the VDDA1

Set DC/DC Converter On/Off

from VDD. Disable the internal DC/DC converter if external VCCA1 is provided.

Use this command to choose doubler or tripler when the internal DC/DC converter

Set Voltage Doubler/Tripler

is enabled.

Choose bit option 0 to disable the internal regulator. Choose bit option 1 to enable

Set Internal Regulator On/Off

internal regulator, which consists of the internal contrast control and temperature

compensation circuits.

If the internal voltage divider is disabled, external bias can be used for VLL6 to

VLL2. If the internal voltage divider is enabled, the internal circuit will automatically

select the correct bias level according to the number of multiplex. Refer to com-

mand ²bias ratio select².

Set Internal Voltage Divider

On/Off

This command is to select 16 mux or 32 mux display. When 16 mux is enabled, the

unused 16 common outputs will be swinging between VLL2 and VLL5 for dummy

scan purpose and doubler will be used.

Set Duty Cycle

Set Bias Ratio

This command sets the 1/5 bias or 1/7 bias for the divider output.

The selection should match the characteristic of LCD panel.

This command is used to turn on or off the internal control of delta voltage of the

bias voltages. With bit option=1, the software selection for delta bias voltage con-

trol is enabled. With bit option=0, internal contrast control is disabled.

Set Internal Contrast Control

On/Off

If the internal contrast control is enabled, this command is used to increase or de-

crease the contrast level within the 16 contrast levels. The contrast level starts from

lowest value after power on reset.

Increase/Decrease Contrast

Level

This command is to select one of the 16 contrast levels when internal contrast con-

trol circuitry is in use.

Set Contrast Level

This command allows the user to read the current contrast level value. With RW in-

put HIGH (READ), DCOM input LOW (Command) and D7, D6, D5 and D4 are

equal to 0001, the value if the internal contrast value can be read on D0~D3 at the

falling edge of CS.

Read Contrast Value

This command can select 4 different LCD driving voltage temperature coefficients

to match various liquid crystal temperature grades. Those temperature coefficients

are specified in electrical characteristics table.

Set Temperature Coefficient

Set IDD Reduction Mode By using this command to reduce the display clock frequency by HALT. Use in Icon

On/Off

mode to reduce standby current

Rev. 1.00

14

February 24, 2004

HT0610

Command table

Bit Pattern

(D7~D0)

Command

Comment

Set BGDRAM page address using X₂X₁X₀as address bits.

X₂X₁X₀=000: page 1 (POR; initial state)

X₂X₁X₀=001: page 2

00000X₂X₁X₀

Set BGDRAM Page Address

X₂X₁X₀=010: page 3

X₂X₁X₀=011: page 4

X₂X₁X₀=100: page 5

Set one of the 4 available values to the icon and annunciator con-

trast, using X₁X₀as data bits.

Set Icon Line/Annunciator

Contrast Level

X₁X₀=00 (Von=0.87VDD)

000011X₁X₀

X₁X₀=01 (Von=0.71VDD)

X₁X₀=10 (Von=0.61VDD) (POR initial state)

X₁X₀=11 (Von=0.55VDD)

Set one of the 16 available values to the internal contrast register,

using X₃X₂X₁X₀as data bits. The contrast register is reset to 0000

during POR

0001X₃X₂X₁X₀

Set Contrast Level

With DCOM pin input low, RW pin input high, and D7~d4 pins

equal to 0001 at the rising edge of CS, the value of the internal con-

trast register will be latched out at D3, D2, D1 and D0 pins, i.e.

X₃X₂X₁X₀at the rising edge of CS.

Read Contrast Value

X₀=0: Select voltage tripler (POR initial state)

X₀=1: Select voltage doubler

0010000X₀

0010001X₀

Set Voltage Doubler/Tripler

Set Column Mapping

X₀=0: COL0 to SEG0 (POR initial state)

X₀=1: COL0 to SEG119

X₀=0: ROW0 to COM0 (POR initial state)

X₀=1: ROW0 to COM31

0010010X₀

0010011X₀

0010100X₀

Set Row Mapping

Reserved

X₀=0: Display off (POR initial state)

X₀=1: Display on

Set Display On/Off

X₀=0: DC/DC converter off (POR initial state)

X₀=1: DC/DC converter on

0010101X₀

0010110X₀

Set DC/DC Converter On/Off

X₀=0: Internal regulator off (POR initial state)

X₀=1: Internal regulator on

Set Internal Regulator On/Off When the application employs external contrast control, the inter-

nal contrast control, temperature compensation and the regulator

must be enabled.

X₀=0: Internal voltage divider off (POR initial state)

Set Internal Voltage Divider X₀=1: Internal voltage divider on

0010111X₀

0011000X₀

On/Off

When an external bias network is preferred, the voltage divider

should be disabled.

X₀=0: Internal contrast control off (POR initial state)

Set Internal Contrast Control X₀=1: Internal contrast control on

On/Off

Internal contrast circuits can be disabled if external contrast circuit

is preferred.

X₀=0: Low frequency (38.4kHz) (POR initial state)

X₀=1: High frequency (50kHz)

0011001X₀

0011010X₀

Set Clock Frequency

Save/Restore RAM Column X₀=0: Restore address

Address

X₀=1: Save address

00110110

00110111

Master Clear RAM

Master Clear Icons

Master clear BGDRAM page 1 to 4

Master clear of BGDRAM page 5

Rev. 1.00

15

February 24, 2004

HT0610

Bit Pattern

(D7~D0)

Command

Comment

X₀=0: Set 1/7 bias (POR initial state)

X₀=1: Set 1/5 bias

0011100X₀

Set Bias Ratio

X₀=0: Normal operation (POR initial state)

X₀=1: Test mode

0011101X₀

Reserved

(Note: make sure to set X₀=0: during application)

X₀=0: Set display mode without Icon line (POR initial state)

X₀=1: Set display mode with Icon line

0011110X₀

00111110

Set Display with Icon Line

Set Icon Display Mode

Set Vertical Scroll Value

Power saving icon display mode, COM 0 to COM 31 will be dis-

abled.

Use X₄X₃X₂X₁as number for lines to scroll.

Scroll value=0 upon POR

010X₄X₃X₂X₁X₀

A₁A₀=00: Select Icon 1 (POR initial state)

A₁A₀=01: Select Icon 2

Set Static Icon Control Sig- A₁A₀=10: Select Icon 3

01100A₁A₀X₀

nals

A₁A₀=11: Select Icon 4

X₀=0: Turned selected Icon off (POR state)

X₀=1: Turned selected Icon on

X₀=0: 1/32 duty and triple enabled (POR initial state)

X₀=1: 1/16 duty and doubler enabled

0110100X₀

0110101X₀

Set Duty Cycle

X₀=0: Normal mode

Set IDD Reduction Mode

X₀=1: I_DDreduction mode

X₀=00: 0.00% (POR initial state)

X₀=01: -0.18%

X₀=10: -0.22%

011011X₁X₀

0111000X₀

Set Temperature Coefficient

X₀=11: -0.35%

X₀=0: Decrease by one level (POR initial state)

Increase/Decrease Contrast X₀=1: Increase by one level

Value

(Note: increment/decrement wraps round among the 16 contrast

levels. Start at the lowest level when POR.

0111001X₀

0111010X₀

Reserved

X₀=0: Normal operation (POR initial state)

X₀=1: Test mode select

0111011X₀

0111100X₀

Reserved

(Note: make sure to set X₀=0 during application)

X₀=0: Internal oscillator (POR initial state)

X₀=1: External oscillator

Set Internal/External

Oscillator

0111101X₀

0111110X₀

If resistors are placed at OSC1 and OSC2. For external oscillator,

simply feed clock in OSC2.

Reserved

X₀=0: Oscillator disable (POR initial state)

X₀=1: Oscillator enable

This is the master control for oscillator circuitry.

This command should be issued after the ²external/internal oscilla-

tor² command.

0111111X₀

Set Oscillator Disable/Enable

Set BGDRAM column address.

1X₆X₅X₄X₃X₂X₁X₀

Set BGDRAM Address

Use X₆X₅X₄X₃X₂X₁X₀as address bits

Rev. 1.00

16

February 24, 2004

HT0610

Data read write

·

To read data from the BGDRAM, input high to RW pin and DCOM pin. Data is valid at the falling edge of CS. And the

BGDRAM column address pointer will be increased by one automatically.

To write data to the BGDRAM, input low to RW pin and high to DCOM pin. Data is latched at the falling edge of CS.

And the BGDRAM column address pointer will be increased by one automatically.

No auto address pointer increment will be performed for the dummy write data after ²master clear BGDRAM²

Address increment table (Automatic)

DCOM

RW

0

Comment

Write command

Read command

Write data

Address Increment

Note

0

1

*1

*2

0

Ö

1

Read data

Address increment is done automatically data read write. The column address pointer of BGDRAM*3 is affected.

Note:

²*1² Refer to the command read contrast value

²*2² If write data is issued after command clear RAM, address increase is not applied

²*3² Column address will be wrapped around when overflow

Power up sequence (Command required)

Command Required

Set Clock Frequency

POR Status

Note

Low

*1

Set Oscillator Enable

Disable

*1

Set Static Icon Control Signals

Set Duty Cycle

Static Icon off

1/32 duty

1/7 bias

*1

Set Bias Ratio

*1

Set Internal DC/DC Converter On

Set Internal Regulator On

Set Temperature Coefficient

Set Internal Contrast Control On

Increase Contrast Level

Set Internal Voltage Divider On

Set Segment Mapping

Set Common Mapping

Set Vertical Scroll Value

Set Display On

Off

*1

Off

*1

TC=0%

*1, *3

*1, *2, *3

*1

Off

Contrast level=0

Off

SEG0=COLUMN0

COM0=ROW0

Scroll value=0

Off

Note:

²*1² Required only if desired status differ from power on reset

²*2² Effective only if internal contrast control is enabled.

²*3² Effective only if the regulator is enabled.

Rev. 1.00

17

February 24, 2004

HT0610

Command Required for Display Mode Setup

Display Mode

Command Required

Set external/internal oscillator*

Set oscillator enable*

Display Mode

Set display on*

Set external/internal oscillator*

Set oscillator enable*

Static Icon Display

Standby Mode 1

Set static Icon control signal*

Set display off*

Set oscillator disable*

Set external oscillator*

Set static Icon control signal*

Set display off*

Standby Mode 2

Standby Mode 3

Set oscillator enable*

Set internal oscillator*

Set static Icon control signal*

Set display off*

Set oscillator enable*

Other related command with display mode: set duty cycle, set column mapping, set row mapping, set vertical scroll

value.

Command Related to Internal DC/DC Converter

Set oscillator disable/enable, set internal regulator on/off, set duty cycle, set temperature coefficient, set internal con-

trast control on/off, increase contrast level, set internal voltage divider on/off, set bias ratio, set display on/off, set inter-

nal/external oscillator, set contrast level, set voltage doubler/tripler, set 33 mux display mode, set Icon display mode.

* You do not need to resend the command again if it is set previously.

Command Required for R/W Actions on RAM

R/W Actions on RAM

Command Required

Set BGDRAM page address*

Read data from BGDRAM

Set BGDRAM column address*

Read/write data

Write data to BGDRAM

Save or restore BGDRAM column address

Increase BGDRAM address by one

Save or restore BGDRAM column address

Dummy read data

Master clear BGDRAM

Dummy write data

Master clear BGDRAM

* You do not need to resend the command again if it is set previously.

Rev. 1.00

18

February 24, 2004

HT0610

Note:

Film: UPILEX-S 75±5mm thickness

Copper: FQ-VLP 25±5mm thickness

Adhesive: Toray #7100, 12±2mm thickness

Solder resist: AE-70-M11, 26±14mm thickness

Flex coating: FS-100L Min. 10mm

Plating: Sn 0.21±0.05mm thickness

All corner radii of base film are less than 0.2mm unless otherwise noted

Other specs than display in this drawing are based on the standard spec lists

All dimensional tolerances of ²SR² & ²Flex² are ±0.2mm & 0.3mm unless otherwise noted

All dimensional tolerances of ²base film² are ±0.05mm unless otherwise noted

Inner lead accumulative pitch:

Output side: 9.359±0.008mm

Input side: 9.077±0.008mm

Reel size: F405mm

Rev. 1.00

19

February 24, 2004

HT0610

Application Circuits

32/33 MUX display with analog circuitry enabled, tripler enabled and 1/7 bias

T

o

L

C

D

P

a

n

e

l

C

S

A

O

M

0

~

C

O

M

3

2

V

D

V

D

E

G

0

~

S

E

G

1

9

0

.

1

m

F

N

1

~

A

N

4

,

B

P

R

C

R

D

E

S

E

W

C

S

V

S

V

D

A

M

P

U

/

M

C

U

w

i

t

h

m

0 . 1 F

V

L

2

P

a

r

a

l

e

l

O

M

0

.

1

m

F

I

n

t

e

r

f

a

c

e

3

0

.

1

m

F

D

0

~

D

7

D

U

M

2

H

T

0

6

1

0

.

1

m

F

1

V

L

4

0

.

1

m

F

5

R

A

M

E

P

R

O

M

0

.

1

m

F

6

1

V

C

A

1

5

0

k

m

0 . 1 F

9

1

0

k

W

0

.

1

m

F

m

0 . 1 F

5

6

0

p

F

m

4 . 7 F

3

0

k

N

o

t

e

:

V

R

a

n

d

V

F

c

a

n

b

e

l

e

f

t

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p

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n

w

h

e

n

R

e

g

u

l

a

t

o

r

i

s

d

i

s

a

b

l

e

d

.

16 MUX display with analog circuitry enabled, tripler enabled and 1/5 bias

T

o

L

C

D

P

a

n

e

l

C

S

A

O

M

0

~

C

O

M

3

2

V

D

V

D

E

G

0

~

S

E

G

1

9

0

.

1

m

F

N

1

~

A

N

4

,

B

P

R

E

S

V

S

C

R

D

S

E

W

C

V

D

A

M

P

U

/

M

C

U

w

i

t

h

m

0 . 1 F

V

L

2

P

a

r

a

l

e

l

O

M

0

.

1

m

F

I

n

t

e

r

f

a

c

e

3

D

0

~

D

7

D

U

M

2

H

T

0

6

1

0

1

m

0 . 1 F

V

L

4

0

.

1

m

F

V

L

5

R

A

M

E

P

R

O

M

0

.

1

m

F

6

1

.

1

m

F

V

C

A

1

5

0

k

0

.

1

m

F

m

0 . 1 F

E

x

t

e

r

n

a

l

5

6

0

p

F

C

l

o

c

k

m

4 . 7 F

3

0

k

N

o

t

e

:

V

R

a

n

d

V

F

c

a

n

b

e

l

e

f

t

o

p

e

n

w

h

e

n

R

e

g

u

l

a

t

o

r

i

s

d

i

s

a

b

l

e

d

.

Rev. 1.00

20

February 24, 2004

HT0610

16/32/33 MUX display with analog circuitry disabled

T

o

L

C

D

P

a

n

e

l

C

O

M

0

~

C

O

M

3

2

V

D

V

D

0

.

1

m

F

S

A

E

G

0

~

S

E

G

1

9

V

S

N

1

~

A

N

4

,

B

P

R

E

S

C

R

D

S

E

W

C

V

D

A

M

P

U

/

M

C

U

w

i

t

h

V

L

2

P

a

r

a

l

e

l

O

M

I

n

t

e

r

f

a

c

e

V

L

3

D

0

~

D

7

H

T

0

6

1

0

D

U

M

2

1

4

U

M

V

L

V

L

5

R

A

M

E

P

R

O

M

V

L

6

V

C

A

1

V

C

E

x

t

e

r

n

a

l

C

l

o

c

k

N

o

t

e

:

V

R

a

n

d

V

F

c

a

n

b

e

l

e

f

t

o

p

e

n

w

h

e

n

R

e

g

u

l

a

t

o

r

i

s

d

i

s

a

b

l

e

d

.

Rev. 1.00

21

February 24, 2004

HT0610

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor (Shanghai) Inc.

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China

Tel: 021-6485-5560

Fax: 021-6485-0313

http://www.holtek.com.cn

Holtek Semiconductor (Hong Kong) Ltd.

Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong

Tel: 852-2-745-8288

Fax: 852-2-742-8657

Holmate Semiconductor, Inc.

46712 Fremont Blvd., Fremont, CA 94538

Tel: 510-252-9880

Fax: 510-252-9885

http://www.holmate.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 1.00

22

February 24, 2004


型号：	HT0610
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	33 x 120 LCD Driver 33 ×120的LCD驱动器显示驱动器驱动程序和接口接口集成电路 CD
文件：	总22页 (文件大小：462K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT0610 [HOLTEK]

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