HT48R062(16SOP-A) [HOLTEK]
Microcontroller;
| 型号： | HT48R062(16SOP-A) |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Microcontroller 微控制器 |
| 文件： | 总32页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT48R062/HT48C062
Cost-Effective I/O Type 8-Bit MCU
Technical Document
·
Tools Information
·
FAQs
·
Application Note
-
HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
HA0013E HT48 & HT46 LCM Interface Design
-
-
-
-
HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
HA0049E Read and Write Control of the HT1380
Features
·
·
·
·
·
·
·
·
·
Operating voltage:
63 powerful instructions
fSYS=4MHz: 2.2V~5.5V
Up to 0.5ms instruction cycle with 8MHz system clock
All instructions in 1 or 2 machine cycles
14-bit table read instructions
fSYS=8MHz: 3.3V~5.5V
·
·
·
·
·
·
11 bidirectional I/O lines
On-chip crystal and RC oscillator
Watchdog Timer
One-level subroutine nesting
Bit manipulation instructions
1K´14 program memory
32´8 data RAM
Low voltage reset function
16-pin DIP/SOP/SSOP package
HALT function and wake-up feature reduce power
consumption
General Description
The HT48R062/HT48C062 are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for cost-effective multiple I/O control product
applications. The mask version HT48C062 is fully pin
and functionally compatible with the OTP version
HT48R062 devices.
The advantages of low power consumption, I/O flexibil-
ity, oscillator options, HALT and wake-up functions,
watchdog timer, as well as low cost, enhance the versa-
tility of these devices to suit a wide range of application
possibilities such as industrial control, consumer prod-
ucts, subsystem controllers, etc.
The HT48C062 is under development and will be avail-
able soon.
Block Diagram
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Rev. 1.00
1
July 13, 2006
HT48R062/HT48C062
Pin Assignment
P
A
3
P
A
4
1
2
3
4
5
6
7
8
1
1
1
1
1
1
1
6
5
4
3
2
1
0
9
P
A
2
P
A
5
P
A
1
P
A
A
6
7
P
P
A
B
0
0
P
O
O
V
R
S
S
C
C
2
1
V
S
S
P
P
B
B
1
2
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0
6
2
/
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0
6
2
1
6
D
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P
-
A
/
S
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P
-
A
/
S
S
O
P
-
A
Pin Description
Code
Pin Name
I/O
Description
Option
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up in-
put by options. Software instructions determine the CMOS output or Schmitt
trigger input with a pull-high resistor (determined by pull-high options).
Pull-high
Wake-up
PA0~PA7
I/O
Bidirectional 3-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with a pull-high resistor (determined by
pull-high options).
PB0~PB2
I/O
Pull-high
VDD
VSS
Positive power supply
¾
¾
¾
¾
Negative power supply, ground
OSC1, OSC2 are connected to an RC network or a crystal (determined by
code option) for the internal system clock. In the case of RC operation, OSC2
is the output terminal for 1/4 system clock (NMOS open drain output).
OSC2
OSC1
O
I
Crystal
or RC
RES
I
Schmitt trigger reset input. Active low.
¾
Absolute Maximum Ratings
Supply Voltage...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
fSYS=4MHz
2.2
3.3
¾
5.5
5.5
1.5
4
V
¾
¾
VDD
Operating Voltage
f
SYS=8MHz
V
¾
3V
5V
3V
5V
0.6
2
mA
mA
mA
mA
IDD1
No load, fSYS=4MHz
No load, fSYS=4MHz
Operating Current (Crystal OSC)
Operating Current (RC OSC)
¾
0.8
2.5
1.5
4
¾
IDD2
¾
Rev. 1.00
2
July 13, 2006
HT48R062/HT48C062
Test Conditions
Conditions
Symbol
Parameter
Operating Current
Min.
Typ.
Max.
Unit
VDD
IDD3
No load, fSYS=8MHz
5V
4
8
mA
¾
(Crystal OSC, RC OSC)
3V
5V
3V
5V
¾
5
10
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
3
mA
mA
mA
mA
V
ISTB1
Standby Current (WDT Enabled)
No load, system HALT
1
¾
ISTB2
Standby Current (WDT Disabled)
No load, system HALT
2
¾
VIL1
VIH1
VIL2
VIH2
VLVR
0.3VDD
VDD
0.4VDD
VDD
3.3
¾
Input Low Voltage for I/O Port
Input High Voltage for I/O Port
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset
0
¾
0.7VDD
0
V
¾
¾
V
¾
¾
¾
0.9VDD
2.7
4
V
¾
LVRenabled
V
¾
3V
5V
3V
5V
3V
5V
8
mA
mA
mA
mA
kW
kW
IOL
V
OL=0.1VDD
OH=0.9VDD
I/O Port Sink Current
I/O Port Source Current
Pull-high Resistance
10
20
-4
-10
60
30
¾
-2
¾
IOH
V
-5
¾
20
100
50
RPH
¾
10
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
2.2V~5.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
400
400
400
400
22
4000
8000
4000
8000
90
kHz
kHz
kHz
kHz
ms
¾
¾
¾
¾
45
32
¾
fSYS1
System Clock (Crystal OSC)
System Clock (RC OSC)
Watchdog Oscillator Period
3.3V~5.5V
¾
2.2V~5.5V
¾
fSYS2
3.3V~5.5V
¾
3V
5V
¾
tWDTOSC
¾
¾
16
64
ms
tRES
tSST
tLVR
External Reset Low Pulse Width
System Start-up Timer Period
Low Voltage Width to Reset
1
¾
ms
Power-up or wake-up
from HALT
tSYS
ms
1024
1
¾
¾
¾
¾
0.25
2
¾
Note: tSYS=1/fSYS
Rev. 1.00
3
July 13, 2006
HT48R062/HT48C062
Functional Description
Execution Flow
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The HT48R062/HT48C062 system clock can be derived
from a crystal/ceramic resonator oscillator or an RC. It is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set or return from subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
Program Counter - PC
The 10-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted and its contents specify a maximum of 1024 ad-
dresses.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
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(
P
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(
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(
P
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Execution Flow
Program Counter
Mode
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
Skip
0
0
0
0
0
0
0
0
0
0
Program Counter+2
Loading PCL
*9
*8
@7
#7
@6
#6
@5
#5
@4
#4
@3
#3
@2
#2
@1
#1
@0
#0
Jump, Call Branch
Return from Subroutine
#9
S9
#8
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *9~*0: Program counter bits
#9~#0: Instruction code bits
S9~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.00
4
July 13, 2006
HT48R062/HT48C062
Program Memory - ROM
Stack Register - STACK
The program memory is used to store the program in-
structions which are to be executed. It also contains
data and table and is organized into 1024´14 bits, ad-
dressed by the program counter and table pointer.
This is a special part of the memory used to save the
contents of the Program Counter only. The stack is orga-
nized into one level and is neither part of the data nor
part of the program space, and is neither readable nor
writeable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call the contents of the program counter are
pushed onto the stack. At the end of a subroutine sig-
naled by a return instruction (RET), the program counter
is restored to its previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
Certain locations in the program memory are reserved
for special usage:
·
Location 000H
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H.
·
Table location
Any location in the EPROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, one page=256 words) and ²TABRDL
[m]² (the last page) transfer the contents of the
lower-order byte to the specified data memory, and
the higher-order byte to TBLH (08H). Only the desti-
nation of the lower-order byte in the table is
well-defined, the other bits of the table word are trans-
ferred to the lower portion of TBLH, the remaining 2
bits are read as ²0². The Table Higher-order byte reg-
ister (TBLH) is read only. The table pointer (TBLP) is a
read/write register (07H), where P indicates the table
location. Before accessing the table, the location must
be placed in TBLP. The TBLH is read only and cannot
be restored. All table related instructions need 2 cy-
cles to complete the operation. These areas may
function as normal program memory depending upon
the requirements.
If the stack is full and a ²CALL² is subsequently exe-
cuted, stack overflow occurs and the first entry will be
lost (only the most recent return address is stored).
Data Memory - RAM
The data memory is designed with 44´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(32´8). Most of them are read/write, but some are read
only.
The special function registers include the Indirect Ad-
dressing Register (00H), the Memory Pointer register
(MP;01H), the Accumulator (ACC;05H) the Program
Counter Lower-order byte register (PCL;06H), the Table
Pointer (TBLP;07H), the table higher-order byte register
(TBLH;08H), the Watchdog Timer option setting register
(WDTS;09H), the STATUS register (STATUS;0AH), the
I/O registers (PA;12H, PB;14H) and I/O control registers
(PAC;13H, PBC;15H). The remaining space before the
20H is reserved for future expanded usage and reading
these locations will return the result 00H. The general
purpose data memory, addressed from 20H to 3FH, is
used for data and control information under instruction
command.
0
0
0
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H
All data memory areas can handle arithmetic, logic, in-
crement, decrement and rotate operations directly. Ex-
cept for some dedicated bits, each bit in the data
memory can be set and reset by the ²SET [m].i² and
²CLR [m].i² instructions, respectively. They are also indi-
rectly accessible through memory pointer register
(MP;01H).
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(
2
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6
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3
Program Memory
Table Location
Instruction(s)
*9
P9
1
*8
P8
1
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
@7
@7
@6
@6
@5
@5
@4
@4
@3
@3
@2
@2
@1
@1
@0
@0
Table Location
@7~@0: Table pointer bits
Note: *9~*0: Table location bits
P9~P8: Current program counter bits
Rev. 1.00
5
July 13, 2006
HT48R062/HT48C062
result ²1². Any writing operation to MP will only transfer
the lower 7-bit data to MP.
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
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P
Accumulator
The accumulator closely relates to ALU operations. It is
also mapped to location 05H of the data memory and is
capable of carrying out immediate data operations. Data
movement between two data memory locations has to
pass through the accumulator.
A
C
C
P
C
L
T
B
L
P
T
B
L
H
W
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S
0
0
A
B
H
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Arithmetic and Logic Unit - ALU
D
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This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions.
0
0
C
D
·
·
·
·
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
0
E
0
F
1
1
1
1
1
0
1
2
3
4
H
H
H
H
H
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
P
A
P
A
C
The ALU not only saves the results of a data operation but
also changes the contents of the status register.
P
B
1
1
5
6
H
H
P
B
C
:
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,
Status Register - STATUS
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0
0
"
1
F
H
H
2
0
This 8-bit status register (0AH) contains the zero flag
(Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF) and watchdog time-out
flag (TO). It also records the status information and con-
trols the operation sequence.
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3
F
H
RAM Mapping
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other register. Any data written into the status register
will not change the TO or PDF flags. In addition it should
be noted that operations related to the status register
may give different results from those intended. The TO
and PDF flags can only be changed by the Watchdog
Timer overflow, chip power-up, clearing the Watchdog
Timer and executing the ²HALT² instruction.
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H).
Reading location 00H itself indirectly will return the re-
sult 00H. Writing indirectly results in no operation.
The memory pointer register MP (01H) is a 7-bit register.
The bit 7 of MP is undefined and reading will return the
Bit No.
Label
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
0
C
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PDF is cleared when either a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
4
PDF
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
5
TO
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.00
6
July 13, 2006
HT48R062/HT48C062
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
tem clock divided by 4), decided by options. This timer is
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The Watchdog Timer can be disabled by an op-
tion. If the Watchdog Timer is disabled, all the execu-
tions related to the WDT result in no operation.
In addition, on executing the subroutine call, the status
register will not be automatically pushed onto the stack.
If the contents of the status are important and if the sub-
routine can corrupt the status register, precautions must
be taken to save it properly.
Once the internal WDT oscillator (RC oscillator with a
period of 32ms at 5V normally) is selected, it is first di-
vided by 512 (9-stage) to get the nominal time-out pe-
riod of approximately 17ms at 5V. This time-out period
may vary with temperatures, VDD and process varia-
tions. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 (bit 2,1,0 of the WDTS) can give different time-out
periods. If WS2, WS1, and WS0 are all equal to 1, the di-
vision ratio is up to 1:128, and the maximum time-out
period is 2.1s at 5V seconds. If the WDT oscillator is dis-
abled, the WDT clock may still come from the instruction
clock and operate in the same manner except that in the
HALT state the WDT may stop counting and lose its pro-
tecting purpose. In this situation the logic can only be re-
started by external logic. The high nibble and bit 3 of the
WDTS are reserved for user¢s defined flags, which can
be used to indicate some specified status.
Oscillator Configuration
There are two oscillator circuits implemented in the
microcontroller.
V
D
D
4
7
0
p
F
C
1
O
S
C
1
O
S
C
1
R
O
S
C
C
2
O
S
C
2
O
S
C
2
S
Y
S
R
1
N
M
O
S
o
p
e
n
d
r
a
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n
C
r
y
s
t
a
l
O
s
c
i
l
l
a
t
o
r
R
C
O
s
c
i
l
l
a
t
o
r
System Oscillator
Both are designed for system clocks; the RC oscillator
and the Crystal oscillator, which are determined by code
options. No matter what oscillator type is selected, the
signal provides the system clock. The HALT mode stops
the system oscillator and ignores the external signal to
conserve power.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
If an RC oscillator is used, an external resistor between
OSC1 and VSS in needed and the resistance must
range from 24kW to 1MW. The system clock, divided by
4, is available on OSC2, which can be used to synchro-
nize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of the
oscillation may vary with VDD, temperature and the chip
itself due to process variations. It is, therefore, not suit-
able for timing sensitive operations where accurate os-
cillator frequency is desired.
WS2
WS1
WS0
Division Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift for the oscillator. No other external components are
needed. Instead of a crystal, the resonator can also be
connected between OSC1 and OSC2 to get a frequency
reference, but two external capacitors in OSC1 and
OSC2 are required.
WDTS (09H) Register
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset², and
only the Program Counter and SP are reset to zero. To
clear the contents of WDT (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a ²HALT² in-
Watchdog Timer - WDT
The clock source of WDT is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
W
D
T
P
r
e
s
c
a
l
e
r
S
y
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m
C
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k
/
4
8
-
b
i
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C
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r
7
-
b
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O
p
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S
e
l
e
c
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W
D
T
O
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C
¸
2
W
S
0
~
W
S
2
(
2
4
k
H
z
)
8
-
t
o
-
1
M
U
X
W
D
T
T
i
m
e
-
o
u
t
Watchdog Timer
Rev. 1.00
7
July 13, 2006
HT48R062/HT48C062
struction. The software instruction include ²CLR WDT²
and the other set - ²CLR WDT1² and ²CLR WDT2². Of
these two types of instruction, only one can be active de-
pending on the option - ²CLR WDT times selection op-
tion². If the ²CLR WDT² is selected (i.e. CLRWDT times
equal one), any execution of the ²CLR WDT² instruction
will clear the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. CLRWDT times equal
two), these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip as a
result of time-out.
TO PDF
RESET Conditions
0
u
0
1
1
0
u
1
u
1
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
Note: ²u² means unchanged.
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem powers up or when the system awakes from a HALT
state.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
When a system power up occurs, an SST delay is added
during the reset period. But when the reset comes from
the RES pin, the SST delay is disabled. Any wake-up
from HALT will enable the SST delay.
·
·
The system oscillator turns off and the WDT stops.
The contents of the on-chip RAM and registers remain
unchanged.
·
·
·
WDT prescaler are cleared.
The functional unit chip reset status is shown below.
All I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
Program Counter
WDT Prescaler
Input/Output ports
Stack Pointer
000H
Clear
The system can quit the HALT mode by means of an ex-
ternal reset or an external falling edge signal on port B.
An external reset causes a device initialization. Exam-
ining the TO and PDF flags, the reason for chip reset
can be determined. The PDF flag is cleared when the
system powers up or execute the ²CLR WDT² instruc-
tion and is set when the ²HALT² instruction is executed.
The TO flag is set if the WDT time-out occurs, and
causes a wake-up that only resets the program counter
and SP, the others keep their original status.
Input mode
Points to the top of the stack
V
D
D
R
E
S
t
S S T
S
S
T
T
i
m
e
-
o
u
t
C
h
i
p
R
e
s
e
t
The Port A wake-up can be considered as a continua-
tion of normal execution. Each bit in Port A can be inde-
pendently selected to wake up the device by the code
option. Awakening from an I/O port stimulus, the pro-
gram will resume execution of the next instruction.
Reset Timing Chart
V
D
D
Once a wake-up event(s) occurs, it takes 1024 tSYS
(system clock period) to resume normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up.
R
E
S
Reset Circuit
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
H
A
L
T
W
D
T
W
D
T
Reset
T
i
m
e
-
o
u
t
R
e
s
e
t
There are three ways in which a reset can occur:
·
R
e
s
e
t
RES reset during normal operation
R
E
S
·
·
RES reset during HALT
WDT time-out reset during normal operation
S
S
T
O
S
C
1
1
0
-
s
t
a
g
e
R
i
p
p
l
e
C
o
u
n
t
e
r
Some registers remain unchanged during reset condi-
tions. Most registers are reset to the ²initial condition²
when the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish between
different ²chip resets².
P
o
w
e
r
-
o
n
D
e
t
e
c
t
i
o
n
Reset Configuration
Rev. 1.00
8
July 13, 2006
HT48R062/HT48C062
The chip reset status of the registers is summarized in the following table:
Reset
WDT Time-out
RES Reset
RES Reset
(HALT)
WDT Time-out
(HALT)*
Register
(Power-on) (Normal Operation) (Normal Operation)
Program Counter
MP
000H
000H
000H
000H
000H
-xxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
0000 0111
--00 xxxx
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0111
--1u uuuu
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0111
--uu uuuu
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0111
--01 uuuu
1111 1111
1111 1111
---- -111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
--11 uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
ACC
TBLP
TBLH
WDTS
STATUS
PA
PAC
PB
PBC
---- -111
---- -111
---- -111
---- -111
---- -uuu
Note:
²*² means ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²
Input/Output Ports
without pull-high resistor structures can be reconfigured
dynamically (i.e. on-the-fly) under software control. To
function as an input, the corresponding latch of the con-
trol register must write ²1². The input source also de-
pends on the control register. If the control register bit is
²1², the input will read the pad state. If the control regis-
ter bit is ²0², the contents of the latches will move to the
internal bus. The latter is possible in the ²read-modify-
write² instruction.
There are up to 11 bidirectional input/output lines in the
microcontroller labeled with port names PA and PB,
which are mapped to the data memory of [12H] and
[14H] respectively. All of these I/O ports can be used for
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction ²MOV A,[m]² (m=12H
or 14H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC) to
control the input/output configuration. With this control
register, CMOS output or Schmitt trigger input with or
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H
and 15H.
V
D
D
C
o
n
t
r
o
l
B
i
t
P
u
l
l
-
h
i
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h
D
a
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a
B
u
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D
C
Q
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K
Q
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h
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p
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P
A
0
~
P
A
7
R
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a
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C
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l
R
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s
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r
P
B
0
~
P
B
2
D
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a
B
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C
Q
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e
-
u
p
O
p
t
i
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n
(
P
A
o
n
l
y
)
Input/Output Ports
Rev. 1.00
9
July 13, 2006
HT48R062/HT48C062
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H or 14H)
instructions.
Low Voltage Reset - LVR
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will au-
tomatically reset the device internally.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
The LVR includes the following specifications:
·
The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
·
Each line of Port A has the capability of waking-up the
device. The highest 5-bit of Port B are not physically im-
plemented; on reading them a ²0² is returned whereas
writing then results in a no-operation. See Application
note.
The LVR uses the ²OR² function with the external
RES signal to perform chip reset.
The relationship between VDD and VLVR is shown below.
V
D
D
V
O P R
5
.
5
V
5
.
5
V
There are pull-high options available for PA and PB.
Once the pull-high option is selected, I/O lines have
pull-high resistors. Otherwise, the pull-high resistors are
absent. It should be noted that a non-pull-high I/O line
operating in input mode will cause a floating state.
V
L
V
R
3
.
0
V
2
.
2
V
0
.
9
V
Note:
V
OPR is the voltage range for proper chip opera-
tion at 4MHz system clock.
V
D
D
5
.
5
V
L
V
R
D
e
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e
c
t
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V
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0
.
9
0
V
V
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N
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O
p
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a
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n
R
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s
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t
*
1
*
2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters
the reset mode.
Rev. 1.00
10
July 13, 2006
HT48R062/HT48C062
Options
The following table shows eight kinds of code option in the HT48R062/HT48C062. All the code options must be defined
to ensure proper system functioning.
No.
1
Options
WDT clock source: WDTOSC or fSYS/4
WDT function: enable or disable
LVR function: enable or disable
2
3
4
CLRWDT instruction(s): one or two clear WDT instruction(s)
System oscillator: RC or crystal
5
6
PA and PB pull-high resistors: none or pull-high
PA0~PA7 wake-up: enable or disable
7
Application Circuits
V
D
D
m
0 . 0 1 F *
V
R
D
D
S
P
A
0
~
P
A
7
1
0
0
k
V
D
D
E
P
B
0
~
P
B
2
4
7
0
p
F
m
0 . 1 F
R
C
S
y
s
t
e
m
O
s
c
i
l
l
a
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r
1
0
k
O
S
C
1
2
4
k
W
O
S
C
W
R
O
S
C
m
0 . 1 F *
S
Y
S
O
S
C
2
V
S
S
N
M
O
S
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p
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n
d
r
a
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n
C
1
O
O
S
S
C
C
1
2
O
O
S
S
C
C
1
2
C
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y
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F
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v
a
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,
C
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2
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t
a
b
l
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b
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o
w
S
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R
i
g
h
t
S
i
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e
R
1
H
T
4
8
R
0
6
2
/
H
T
4
8
C
0
6
2
O
S
C
C
i
r
c
u
i
t
Note: The resistance and capacitance for reset circuit should be designed to ensure that the VDD is stable and re-
mains in a valid range of the operating voltage before bringing RES high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For refer-
ence only)
Crystal or Resonator
4MHz Crystal
C1, C2
0pF
R1
10kW
12kW
10kW
10kW
12kW
10kW
9.1kW
10kW
10kW
4MHz Resonator
10pF
0pF
3.58MHz Crystal
3.58MHz Resonator
2MHz Crystal & Resonator
1MHz Crystal
25pF
25pF
35pF
300pF
300pF
300pF
480kHz Resonator
455kHz Resonator
429kHz Resonator
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage condi-
tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Rev. 1.00
11
July 13, 2006
HT48R062/HT48C062
Instruction Set Summary
Instruction
Cycle
Flag
Mnemonic
Arithmetic
Description
Affected
ADD A,[m]
ADDM A,[m]
ADD A,x
Add data memory to ACC
1
1(1)
1
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
Add ACC to data memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add data memory to ACC with carry
1
1(1)
Add ACC to data memory with carry
Subtract immediate data from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Subtract data memory from ACC
1
1(1)
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1(1)
Logic Operation
AND A,[m]
OR A,[m]
AND data memory to ACC
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
OR data memory to ACC
XOR A,[m]
ANDM A,[m]
ORM A,[m]
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
1
1(1)
1(1)
1(1)
1
XORM A,[m] Exclusive-OR ACC to data memory
AND A,x
OR A,x
AND immediate data to ACC
OR immediate data to ACC
1
XOR A,x
CPL [m]
CPLA [m]
Exclusive-OR immediate data to ACC
Complement data memory
1
1(1)
Complement data memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment data memory with result in ACC
1
Z
Z
Z
Z
Increment data memory
1(1)
DECA [m]
DEC [m]
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
Rotate
RRA [m]
RR [m]
Rotate data memory right with result in ACC
Rotate data memory right
1
1(1)
1
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
1(1)
C
1
None
None
C
1(1)
1
RLCA [m]
RLC [m]
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1(1)
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Rev. 1.00
12
July 13, 2006
HT48R062/HT48C062
Instruction
Cycle
Flag
Mnemonic
Branch
Description
Affected
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if data memory is zero
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRDC [m] Read ROM code (current page) to data memory and TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
Miscellaneous
NOP
No operation
1
1(1)
1(1)
1
None
None
CLR [m]
Clear data memory
SET [m]
Set data memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter Power Down Mode
1
1
1(1)
1
None
1
TO,PDF
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1): If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2): If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(1) and (2)
(3)
:
(4): The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
Rev. 1.00
13
July 13, 2006
HT48R062/HT48C062
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
Rev. 1.00
14
July 13, 2006
HT48R062/HT48C062
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND op-
eration. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND op-
eration. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
Operation
The contents of the specified data memory are cleared to 0.
[m] ¬ 00H
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.00
15
July 13, 2006
HT48R062/HT48C062
CLR [m].i
Clear bit of data memory
Description
Operation
The bit i of the specified data memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
0
PDF
0
OV
Z
AC
C
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
0*
PDF
0*
OV
Z
AC
C
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
0*
PDF
0*
OV
Z
AC
C
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.00
16
July 13, 2006
HT48R062/HT48C062
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-
lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Operation
Data in the specified data memory is decremented by 1.
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.00
17
July 13, 2006
HT48R062/HT48C062
HALT
Enter Power Down Mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
0
PDF
1
OV
Z
AC
C
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Operation
Data in the specified data memory is incremented by 1
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Description
Operation
Move data memory to the accumulator
The contents of the specified data memory are copied to the accumulator.
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.00
18
July 13, 2006
HT48R062/HT48C062
MOV A,x
Move immediate data to the accumulator
Description
Operation
The 8-bit data specified by the code is loaded into the accumulator.
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
Program Counter ¬ Program Counter+1
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) per-
form a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.00
19
July 13, 2006
HT48R062/HT48C062
RET
Return from subroutine
Description
Operation
Affected flag(s)
The program counter is restored from the stack. This is a 2-cycle instruction.
Program Counter ¬ Stack
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the speci-
fied 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
Operation
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.00
20
July 13, 2006
HT48R062/HT48C062
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-
places the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
Operation
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
Rev. 1.00
21
July 13, 2006
HT48R062/HT48C062
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.00
22
July 13, 2006
HT48R062/HT48C062
SET [m]
Set data memory
Description
Operation
Each bit of the specified data memory is set to 1.
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Operation
Bit i of the specified data memory is set to 1.
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the fol-
lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-
wise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.00
23
July 13, 2006
HT48R062/HT48C062
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memo-
ries) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.00
24
July 13, 2006
HT48R062/HT48C062
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.00
25
July 13, 2006
HT48R062/HT48C062
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-
sive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-
sive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-
eration. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.00
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July 13, 2006
HT48R062/HT48C062
Package Information
16-pin DIP (300mil) Outline Dimensions
A
1
6
9
8
B
1
H
C
D
a
G
E
I
F
Dimensions in mil
Symbol
Min.
745
240
125
125
16
Nom.
¾
Max.
775
260
135
145
20
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
50
70
¾
100
¾
¾
295
335
0°
315
375
15°
¾
¾
¾
a
Rev. 1.00
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July 13, 2006
HT48R062/HT48C062
16-pin SOP (300mil) Outline Dimensions
1
6
9
A
B
1
8
C
C
'
G
H
D
a
E
F
Dimensions in mil
Symbol
Min.
394
290
14
390
92
¾
Nom.
¾
Max.
419
300
20
A
B
C
C¢
D
E
F
¾
¾
413
104
¾
¾
¾
50
4
¾
¾
¾
¾
¾
G
H
a
32
4
38
12
0°
10°
Rev. 1.00
28
July 13, 2006
HT48R062/HT48C062
16-pin SSOP (150mil) Outline Dimensions
1
6
9
A
B
1
8
C
C
'
G
H
D
a
E
F
Dimensions in mil
Symbol
Min.
228
150
8
Nom.
¾
Max.
244
157
12
A
B
C
C¢
D
E
F
¾
¾
189
54
¾
197
60
¾
¾
25
¾
4
10
¾
¾
¾
¾
G
H
a
22
7
28
10
0°
8°
Rev. 1.00
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July 13, 2006
HT48R062/HT48C062
Product Tape and Reel Specifications
Reel Dimensions
D
T
2
C
A
B
T
1
SOP 16W (300mil)
Symbol
Description
Dimensions in mm
330±1
A
B
Reel Outer Diameter
Reel Inner Diameter
62±1.5
13±0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2±0.5
16.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
22.2±0.2
SSOP 16S
Symbol
Description
Dimensions in mm
330±1
A
B
Reel Outer Diameter
Reel Inner Diameter
62±1.5
13+0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2±0.5
12.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
18.2±0.2
Rev. 1.00
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July 13, 2006
HT48R062/HT48C062
Carrier Tape Dimensions
P
0
P
1
t
D
E
F
W
B
0
C
D
1
P
K
0
A
0
SOP 16W (300mil)
Symbol
Description
Dimensions in mm
16±0.2
W
P
Carrier Tape Width
Cavity Pitch
12±0.1
E
Perforation Position
1.75±0.1
7.5±0.1
1.5+0.1
1.5+0.25
4±0.1
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
D
D1
P0
P1
A0
B0
K0
t
Cavity to Perforation (Length Direction)
Cavity Length
2±0.1
10.9±0.1
10.8±0.1
3±0.1
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
0.3±0.05
13.3
C
SSOP 16S
Symbol
Description
Dimensions in mm
12+0.3
-0.1
W
Carrier Tape Width
P
E
Cavity Pitch
8±0.1
1.75±0.1
5.5±0.1
1.55±0.1
1.5+0.25
4±0.1
Perforation Position
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
F
D
D1
P0
P1
A0
B0
K0
t
Cavity to Perforation (Length Direction)
Cavity Length
2±0.1
6.4±0.1
5.2±0.1
2.1±0.1
0.3±0.05
9.3
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
Rev. 1.00
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July 13, 2006
HT48R062/HT48C062
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Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
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Tel: 886-2-2655-7070
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Fax: 510-252-9885
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Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
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July 13, 2006
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