HT49R30A-1(48SSOP)_技术文档

HT49R30A-1/HT49C30-1/HT49C30L

LCD Type 8-Bit MCU

Features

·

Operating voltage:

_SYS= 4MHz: 2.2V~5.5V for HT49R30A-1/HT49C30-1

_SYS= 8MHz: 3.3V~5.5V for HT49R30A-1/HT49C30-1

_SYS= 500kHz: 1.2V~2.2V for HT49C30L

On-chip crystal, RC and 32768Hz crystal oscillator

f

HALT function and wake-up feature reduce power

consumption

f

·

4-level subroutine nesting

Bit manipulation instruction

14-bit table read instruction

·

6 input lines

8 bidirectional I/O lines

Two external interrupt input

Up to 0.5ms instruction cycle with 8MHz system clock

for HT49R30A-1/HT49C30-1

One 8-bit programmable timer/event counter with

PFD (programmable frequency divider) function

·

Up to 8ms instruction cycle with 500kHz system clock

for HT49C30L

·

LCD driver with 19´2, 19´3 or 18´4 segments

2K´14 program memory

96´8 data memory RAM

Real Time Clock (RTC)

8-bit prescaler for RTC

Watchdog Timer

·

63 powerful instructions

All instructions in 1 or 2 machine cycles

Low voltage reset/detector for

HT49R30A-1/HT49C30-1

·

48-pin SSOP package

Buzzer output

General Description

The HT49R30A-1/HT49C30-1/HT49C30L are 8-bit,

high performance, RISC architecture microcontroller

devices specifically designed for a wide range of LCD

applications. The mask version HT49C30-1 and

HT49C30L are fully pin and functionally compatible with

the OTP version HT49R30A-1 device. The HT49C30L

is a low voltage version, with the ability to operate at a

minimum power supply of 1.2V, making it suitable for

single cell battery applications.

The advantages of low power consumption, I/O flexibil-

ity, programmable frequency divider, timer functions,

oscillator options, HALT and wake-up functions and

buzzer driver in addition to a flexible and configurable

LCD interface, enhance the versatility of these devices

to control a wide range of LCD-based application possi-

bilities such as measuring scales, electronic multi-

meters, gas meters, timers, calculators, remote

controllers and many other LCD-based industrial and

home appliance applications.

Rev. 1.70

1

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Block Diagram

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7

Rev. 1.70

2

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Pin Assignment

P

A

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1

/

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3

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7

6

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A

Rev. 1.70

3

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Pad Assignment

HT49R30A-1

4

5

1

5

0

4

9

4

8

4

7

4

6

4

2

4

1

4

0

4

3

T

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3

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2

1

2

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4

5

6

7

8

9

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6

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7

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0

1

3

9

8

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1

(

0

,

0

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3

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2

3

4

5

6

7

8

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3

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5

1

0

1

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S

1

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3

2

1

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L

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1

3

4

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1

8

2

0

2

1

2

3

2

4

2

5

2

6

2

7

2

8

2

9

3

0

1

9

1

5

1

6

1

7

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.70

4

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

HT49C30-1

1

5

1

4

9

4

7

4

6

4

5

4

2

4

0

4

3

9

4

1

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2

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2

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8

1

9

2

0

2

3

2

6

2

5

1

3

1

4

1

6

1

5

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.70

5

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

HT49C30L

4

7

4

6

4

5

4

1

4

8

4

3

4

2

4

0

3

8

4

1

3

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3

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6

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6

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C

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1

2

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3

1

4

1

5

1

6

1

7

1

8

1

9

2

1

2

3

2

4

2

5

2

0

* The IC substrate should be connected to VSS in the PCB layout artwork.

Pad Description

Pad Name

I/O

Options

Description

PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trig-

ger input capability. Each bit on port can be configured as a wake-up input by

options. PA0~PA3 can be configured as a CMOS output or NMOS input/out-

put with or without pull-high resistor by options. PA4~PA7 are always

pull-high NMOS input/output. Of the eight bits, PA0~PA1 can be set as I/O

pins or buzzer outputs by options. PA3 can be set as an I/O pin or as a PFD

output also by options.

PA0/BZ

Wake-up

Pull-high

or None

CMOS or

NMOS

PA1/BZ

PA2

I/O

PA3/PFD

PA4~PA7

PB0~PB5 constitute a 6-bit Schmitt trigger input port. Each bit on port are

with pull-high resistor. Of the six bits, PB0 and PB1 can be set as input pins or

as external interrupt control pins (INT0) and (INT1) respectively, by software

application. PB2 can be set as an input pin or as a timer/event counter input

pin TMR also by software application.

PB0/INT0

PB1/INT1

PB2/TMR

PB3~PB5

I

¾

LCD power supply for HT49R30A-1/HT49C30-1.

Voltage pump for HT49C30L.

VLCD

Voltage pump for HT49R30A-1/HT49C30-1.

LCD power supply for HT49C30L.

V2

I

¾

V1,C1,C2

Voltage pump

COM0~COM2

COM3/SEG18

1/2, 1/3 or 1/4 SEG18 can be set as a segment or as a common output driver for LCD panel

Duty by options. COM0~COM2 are outputs for LCD panel plate.

O

Rev. 1.70

6

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Pad Name

I/O

Options

Description

SEG0~SEG17

O

LCD driver outputs for LCD panel segments

¾

OSC1 and OSC2 are connected to an RC network or a crystal (by options)

for the internal system clock. In the case of RC operation, OSC2 is the output

OSC1

OSC2

I

Crystal or RC terminal for 1/4 system clock.

The system clock may come from the RTC oscillator. If the system clock co-

O

mes from RTC OSC, these two pins can be floating.

Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz

crystal oscillator for timing purposes or to a system clock source (depending

on the options).

OSC3

OSC4

I

RTC or

O

System Clock

VSS

VDD

RES

Negative power supply, ground

Positive power supply

¾

I

¾

Schmitt trigger reset input, active low

Absolute Maximum Ratings

Supply Voltage..........................V_SS-0.3V to V_SS+6.0V*

Storage Temperature ............................-50°C to 125°C

Operating Temperature...........................-40°C to 85°C

Supply Voltage ........................V_SS-0.3V to V_SS+2.5V**

Input Voltage..............................V_SS-0.3V to V_DD+0.3V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

²*² For HT49R30A-1/HT49C30-1

²**² For HT49C30L

D.C. Characteristics

V_DD=1.5V for HT49C30L, V_DD=3V & V_DD=5V for HT49R30A-1 and HT49C30-1

Ta=25°C

Test Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

V_DD

Conditions

For HT49C30L

1.2

2.2

5.5

V

¾

LVR disable, f_SYS=4MHz

V_DD

Operating Voltage

¾

(for HT49R30A-1/HT49C30-1)

f

_SYS=8MHz

3.3

2.2

5.5

V

¾

(for HT49R30A-1/HT49C30-1)

For HT49R30A-1/HT49C30-1,

V_LCD

LCD Power Supply (Note *)

¾

VA£5.5V

No load, f_SYS=455kHz

No load, f_SYS=4MHz

No load, f_SYS=400kHz

No load, f_SYS=4MHz

1.5V

3V

60

1

100

2

¾

mA

Operating Current

(Crystal OSC)

I_DD1

5V

3

5

1.5V

3V

50

1

100

2

Operating Current

(RC OSC)

I_DD2

mA

5V

3

5

Operating Current

I_DD3

No load, f_SYS=8MHz

5V

4

8

mA

¾

(Crystal OSC, RC OSC)

Rev. 1.70

7

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

V_DD

1.5V

2.5

0.3

0.6

0.1

¾

5

0.6

1

¾

mA

Operating Current

(f_SYS=32768Hz)

I_DD4

3V No load

5V

1.5V

0.5

1

Standby Current

(*f_S=T1)

No load, system HALT,

I_STB1

I_STB2

I_STB3

3V

5V

LCD Off at HALT

2

¾

1.5V

3V

1

2

Standby Current

No load, system HALT,

LCD On at HALT, C type

2.5

10

0.5

2

5

(*f_S=32.768kHz OSC)

5V

20

1

1.5V

3V

Standby Current

No load, system HALT

5

(*f_S=WDT RC OSC)

LCD On at HALT, C type

5V

6

10

30

60

25

50

25

50

20

40

3V

17

34

13

28

14

26

10

19

Standby Current

No load, system HALT,

I_STB4

I_STB5

I_STB6

(*f_S=32.768kHz OSC)

LCD On at HALT, R type, 1/2 bias

5V

3V

Standby Current

No load, system HALT,

(*f_S=32.768kHz OSC)

LCD On at HALT, R type, 1/3 bias

5V

3V

Standby Current

No load, system HALT,

(*f_S=WDT RC OSC)

LCD On at HALT, R type, 1/2 bias

5V

3V

Standby Current

No load, system HALT,

I_STB7

(*f_S=WDT RC OSC)

LCD On at HALT, R type, 1/3 bias

5V

Input Low Voltage for I/O

Ports, TMR and INT

V_IL1

0.3V_DD

0

V

¾

0.8V_DD

0.7V_DD

0

V_DD

0.4V_DD

V_DD

¾

1.5V

3V

V

¾

Input High Voltage for I/O

Ports, TMR and INT

V_IH1

5V

V

¾

V_IL2

V_IH2

Input Low Voltage (RES)

Input High Voltage (RES)

V

¾

0.9V_DD

0.4

V

¾

1.5V

3V

0.8

12

mA

I_OL1

V

_OL=0.1V_DD

I/O Port Sink Current

6

¾

5V

10

25

¾

1.5V

3V

-0.3

-2

-0.6

-4

¾

I_OH1

_OH=0.9V_DD

I/O Port Source Current

¾

5V

-5

-8

¾

3V

210

350

-80

420

700

-160

¾

LCD Common and Segment

Current

I_OL2

V

_OL=0.1V_DD

_OH=0.9V_DD

5V

¾

3V

¾

LCD Common and Segment

Current

I_OH2

V

5V

-180 -360

¾

Rev. 1.70

8

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

V_DD

1.5V

3V

75

20

150

60

300

100

50

kW

V

Pull-high Resistance of I/O

Ports and INT0, INT1

R_PH

¾

5V

10

30

V_LVR

V_LVD

Low Voltage Reset Voltage

Low Voltage Detector Voltage

2.7

3.0

3.2

3.3

3.6

¾

V

¾

Note:

²*² for the value of VA refer to the LCD driver section.

t_SYS=1/f_SYS

²*f_S² please refer to the WDT clock option

A.C. Characteristics

V_DD=1.5V for HT49C30L, V_DD=3V & V_DD=5V for HT49R30A-1 and HT49C30-1

Ta=25°C

Test Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

V_DD

¾

Conditions

1.2V~2.2V (for HT49C30L)

2.2V~5.5V

400

500

4000

8000

500

kHz

¾

f_SYS1

System Clock (Crystal OSC)

¾

3.3V~5.5V

¾

1.2V~2.2V (for HT49C30L)

2.2V~5.5V

¾

f_SYS2

System Clock (RC OSC)

4000

8000

¾

3.3V~5.5V

¾

System Clock

f_SYS3

32768

Hz

¾

(32768Hz Crystal OSC)

f_RTCOSC

RTC Frequency

32768

¾

Hz

¾

1.2V~2.2V (for HT49C30L)

2.2V~5.5V

¾

0

¾

500

4000

8000

140

180

130

¾

kHz

f_TIMER

Timer I/P Frequency

0

¾

3.3V~5.5V

0

¾

1.5V

3V

5V

35

45

32

10

1

70

ms

t_WDTOSC

Watchdog Oscillator Period

90

¾

65

ms

For HT49C30L

¾

ms

t_RES

t_SST

t_INT

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

¾

For HT49R30A-1/HT49C30-1

Wake-up from HALT

For HT49C30L

¾

ms

*t_SYS

1024

¾

10

1

¾

ms

For HT49R30A-1/HT49C30-1

¾

Note: *t_SYS=1/f_SYS

Rev. 1.70

9

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Functional Description

Execution Flow

After accessing a program memory word to fetch an in-

struction code, the value of the PC is incremented by

one. The PC then points to the memory word containing

the next instruction code.

The system clock is derived from either a crystal or an

RC oscillator or a 32768Hz crystal oscillator. It is inter-

nally divided into four non-overlapping clocks. One in-

struction cycle consists of four system clock cycles.

When executing a jump instruction, conditional skip ex-

ecution, loading a PCL register, a subroutine call, an ini-

tial reset, an internal interrupt, an external interrupt, or

returning from a subroutine, the PC manipulates the

program transfer by loading the address corresponding

to each instruction.

Instruction fetching and execution are pipelined in such

a way that a fetch takes one instruction cycle while de-

coding and execution takes the next instruction cycle.

The pipelining scheme causes each instruction to effec-

tively execute in a cycle. If an instruction changes the

value of the program counter, two cycles are required to

complete the instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get a proper instruction; oth-

erwise proceed with the next instruction.

Program Counter - PC

The program counter (PC) is of 11 bits wide and controls

the sequence in which the instructions stored in the pro-

gram ROM are executed. The contents of the PC can

specify a maximum of 2048 addresses.

The lower byte of the PC (PCL) is a readable and

writeable register (06H). Moving data into the PCL per-

forms a short jump. The destination is within 256 loca-

tions.

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

S

y

s

t

e

m

C

l

o

c

k

O

S

C

2

(

R

C

o

n

l

y

)

P

C

P

C

+

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Execution Flow

Program Counter

Mode

*10

0

*9

0

*8

0

*7

0

*6

0

*5

0

*4

0

1

*3

0

1

0

*2

0

1

0

1

0

1

*1

0

*0

0

Initial Reset

External Interrupt 0

External Interrupt 1

0

Timer/Event Counter Overflow

Time Base Interrupt

RTC Interrupt

0

Skip

PC+2

@5

#5

S5

Loading PCL

*10

*9

#9

S9

*8

#8

S8

@7

#7

@6

#6

@4

#4

@3

#3

@2

#2

@1

#1

@0

#0

Jump, Call Branch

Return From Subroutine

#10

S10

S7

S6

S4

S3

S2

S1

S0

Program Counter

Note: *10~*0: Program counter bits

#10~#0: Instruction code bits

S10~S0: Stack register bits

@7~@0: PCL bits

Rev. 1.70

10

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

0

4

H

When a control transfer takes place, an additional

dummy cycle is required.

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Program Memory - ROM

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The program memory is used to store the program in-

structions which are to be executed. It also contains

data, table, and interrupt entries, and is organized into

2048´14 bits which are addressed by the PC and table

pointer.

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Certain locations in the ROM are reserved for special

usage:

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·

Location 000H

Location 000H is reserved for program initialization.

After chip reset, the program always begins execution

at this location.

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·

Location 004H

Location 004H is reserved for the external interrupt

service program. If the INT0 input pin is activated, and

the interrupt is enabled, and the stack is not full, the

program begins execution at location 004H.

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Program Memory

·

Location 008H

higher-order byte to TBLH (Table Higher-order byte

register) (08H). Only the destination of the lower-order

byte in the table is well-defined; the other bits of the ta-

ble word are all transferred to the lower portion of

TBLH, and the remaining 2 bit is read as ²0². The

TBLH is read only, and the table pointer (TBLP) is a

read/write register (07H), indicating the table location.

Before accessing the table, the location should be

placed in TBLP. All the table related instructions re-

quire 2 cycles to complete the operation. These areas

may function as a normal ROM depending upon the

user¢s requirements.

Location 008H is reserved for the external interrupt

service program also. If the INT1 input pin is activated,

and the interrupt is enabled, and the stack is not full,

the program begins execution at location 008H.

Location 00CH

Location 00CH is reserved for the timer/event counter

interrupt service program. If a timer interrupt results

from a timer/event counter overflow, and if the inter-

rupt is enabled and the stack is not full, the program

begins execution at location 00CH.

·

Location 010H

Location 010H is reserved for the Time Base interrupt

service program. If a Time Base interrupt occurs, and

the interrupt is enabled, and the stack is not full, the

program begins execution at location 010H.

Stack Register - STACK

The stack register is a special part of the memory used

to save the contents of the PC. The stack is organized

into 4 levels and is neither part of the data nor part of the

program, and is neither readable nor writeable. Its acti-

vated level is indexed by a stack pointer (SP) and is nei-

ther readable nor writeable. At a commencement of a

subroutine call or an interrupt acknowledgment, the

contents of the PC is pushed onto the stack. At the end

of the subroutine or interrupt routine, signaled by a re-

turn instruction (RET or RETI), the contents of the PC is

restored to its previous value from the stack. After chip

reset, the SP will point to the top of the stack.

Location 014H

Location 014H is reserved for the real time clock inter-

rupt service program. If a real time clock interrupt oc-

curs, and the interrupt is enabled, and the stack is not

full, the program begins execution at location 014H.

Table location

Any location in the ROM can be used as a look-up ta-

ble. The instructions ²TABRDC [m]² (the current page,

1 page=256 words) and ²TABRDL [m]² (the last page)

transfer the contents of the lower-order byte to the

specified data memory, and the contents of the

Table Location

Instruction(s)

*10

P10

1

*9

P9

1

*8

P8

1

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

@7

@6

@5

@4

@3

@2

@1

@0

Table Location

P10~P8: Current program counter bits

Note: *10~*0: Table location bits

@7~@0: Table pointer bits

Rev. 1.70

11

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag is recorded but the ac-

knowledgment is still inhibited. Once the SP is decre-

mented (by RET or RETI), the interrupt is serviced. This

feature prevents stack overflow, allowing the program-

mer to use the structure easily. Likewise, if the stack is

full, and a ²CALL² is subsequently executed, a stack

overflow occurs and the first entry is lost (only the most

recent four return addresses are stored).

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Data Memory - RAM

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The data memory (RAM) is designed with 113´8 bits,

and is divided into two functional groups, namely special

function registers and general purpose data memory,

most of which are readable/writeable, although some

are read only.

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Of the two types of functional groups, the special func-

tion registers consist of an Indirect addressing register 0

(00H), a Memory pointer register 0 (MP0;01H), an Indi-

rect addressing register 1 (02H), a Memory pointer reg-

ister 1 (MP1;03H), a Bank pointer (BP;04H), an

Accumulator (ACC;05H), a Program counter

lower-order byte register (PCL;06H), a Table pointer

(TBLP;07H), a Table higher-order byte register

(TBLH;08H), a Real time clock control register

(RTCC;09H), a Status register (STATUS;0AH), an Inter-

rupt control register 0 (INTC0;0BH), a timer/event coun-

ter (TMR;0DH), a timer/event counter control register

(TMRC;0EH), I/O registers (PA;12H, PB;14H), and In-

terrupt control register 1 (INTC1;1EH). On the other

hand, the general purpose data memory, addressed

from 20H to 7FH, is used for data and control informa-

tion under instruction commands.

1

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The areas in the RAM can directly handle arithmetic,

logic, increment, decrement, and rotate operations. Ex-

cept some dedicated bits, each bit in the RAM can be

set and reset by ²SET [m].i² and ²CLR [m].i² They are

also indirectly accessible through the Memory pointer

register 0 (MP0;01H) or the Memory pointer register 1

(MP1;03H).

7

F

H

RAM Mapping

Accumulator - ACC

The accumulator (ACC) is related to the ALU opera-

tions. It is also mapped to location 05H of the RAM and

is capable of operating with immediate data. The data

movement between two data memory locations must

pass through the ACC.

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] and [02H] accesses the RAM pointed to

by MP0 (01H) and MP1(03H) respectively. Reading lo-

cation 00H or 02H indirectly returns the result 00H.

While, writing it indirectly leads to no operation.

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic opera-

tions and provides the following functions:

The function of data movement between two indirect ad-

dressing registers is not supported. The memory pointer

registers, MP0 (7-bit) and MP1 (7-bit), used to access

the RAM by combining corresponding indirect address-

ing registers. MP0 can only be applied to data memory,

while MP1 can be applied to data memory and LCD dis-

play memory.

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ etc.)

Rev. 1.70

12

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

The ALU not only saves the results of a data operation

but also changes the status register.

scheme may prevent any further interrupt nesting. Other

interrupt requests may take place during this interval,

but only the interrupt request flag will be recorded. If a

certain interrupt requires servicing within the service

routine, the EMI bit and the corresponding bit of the

INTC0 or of INTC1 may be set in order to allow interrupt

nesting. Once the stack is full, the interrupt request will

not be acknowledged, even if the related interrupt is en-

abled, until the SP is decremented. If immediate service

is desired, the stack should be prevented from becom-

ing full.

Status Register - STATUS

The status register (0AH) is of 8 bits wide and contains,

a carry flag (C), an auxiliary carry flag (AC), a zero flag

(Z), an overflow flag (OV), a power down flag (PDF), and

a watchdog time-out flag (TO). It also records the status

information and controls the operation sequence.

Except the TO and PDF flags, bits in the status regis-

ter can be altered by instructions similar to other regis-

ters. Data written into the status register does not alter

the TO or PDF flags. Operations related to the status

register, however, may yield different results from those

intended. The TO and PDF flags can only be changed

by a Watchdog Timer overflow, chip power-up, or clear-

ing the Watchdog Timer and executing the ²HALT² in-

struction. The Z, OV, AC, and C flags reflect the status of

the latest operations.

All these interrupts can support a wake-up function. As

an interrupt is serviced, a control transfer occurs by

pushing the contents of the PC onto the stack followed

by a branch to a subroutine at the specified location in

the ROM. Only the contents of the PC is pushed onto

the stack. If the contents of the register or of the status

register (STATUS) is altered by the interrupt service pro-

gram which corrupts the desired control sequence, the

contents should be saved in advance.

On entering the interrupt sequence or executing the

subroutine call, the status register will not be automati-

cally pushed onto the stack. If the contents of the status

is important, and if the subroutine is likely to corrupt the

status register, the programmer should take precautions

and save it properly.

External interrupts are triggered by a high to low transi-

tion of INT0 or INT1, and the related interrupt request

flag (EIF0;bit 4 of INTC0, EIF1;bit 5 of INTC0) is set as

well. After the interrupt is enabled, the stack is not full,

and the external interrupt is active, a subroutine call to

location 04H or 08H occurs. The interrupt request flag

(EIF0 or EIF1) and EMI bits are all cleared to disable

other interrupts.

Interrupts

The device provides two external interrupts, an internal

timer/event counter interrupt, an internal time base in-

terrupt, and an internal real time clock interrupt. The in-

terrupt control register 0 (INTC0;0BH) and interrupt

control register 1 (INTC1;1EH) both contain the interrupt

control bits that are used to set the enable/disable status

and interrupt request flags.

The internal timer/event counter interrupt is initialized by

setting the timer/event counter interrupt request flag

(TF;bit 6 of INTC0), which is normally caused by a timer

overflow. After the interrupt is enabled, and the stack is

not full, and the TF bit is set, a subroutine call to location

0CH occurs. The related interrupt request flag (TF) is re-

set, and the EMI bit is cleared to disable further inter-

rupts.

Once an interrupt subroutine is serviced, other inter-

rupts are all blocked (by clearing the EMI bit). This

Labels

Bits

Function

C is set if the operation results in a carry during an addition operation or if a borrow does not take

place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

C

0

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the

high nibble into the low nibble in subtraction; otherwise AC is cleared.

AC

Z

1

2

3

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

OV

PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is set

by executing the ²HALT² instruction.

PDF

4

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

TO

5

6, 7

¾

Unused bit, read as ²0²

Status Register

Rev. 1.70

13

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Register

Bit No.

Label

EMI

EEI0

EEI1

ETI

Function

0

1

Control the master (global) interrupt (1=enabled; 0=disabled)

Control the external interrupt 0 (1=enabled; 0=disabled)

Control the external interrupt 1 (1=enabled; 0=disabled)

Control the timer/event counter interrupt (1=enabled; 0=disabled)

External interrupt 0 request flag (1=active; 0=inactive)

External interrupt 1 request flag (1=active; 0=inactive)

Internal timer/event counter request flag (1=active; 0=inactive)

Unused bit, read as ²0²

2

3

INTC0

(0BH)

4

EIF0

EIF1

TF

5

6

7

¾

0

ETBI

ERTI

¾

Control the time base interrupt (1=enabled; 0:disabled)

Control the real time clock interrupt (1=enabled; 0:disabled)

Unused bit, read as ²0²

1

2, 3

4

INTC1

(1EH)

TBF

RTF

¾

Time base request flag (1=active; 0=inactive)

Real time clock request flag (1=active; 0=inactive)

Unused bit, read as ²0²

5

6, 7

INTC Register

The time base interrupt is initialized by setting the time

base interrupt request flag (TBF;bit 4 of INTC1), that is

caused by a regular time base signal. After the interrupt

is enabled, and the stack is not full, and the TBF bit is

set, a subroutine call to location 10H occurs. The related

interrupt request flag (TBF) is reset and the EMI bit is

cleared to disable further interrupts.

Interrupt Source

External interrupt 0

Priority

Vector

04H

1

2

3

4

5

External interrupt 1

08H

Timer/event counter overflow

Time base interrupt

0CH

10H

Real time clock interrupt

14H

The real time clock interrupt is initialized by setting the

real time clock interrupt request flag (RTF;bit 5 of

INTC1), that is caused by a regular real time clock sig-

nal. After the interrupt is enabled, and the stack is not

full, and the RTF bit is set, a subroutine call to location

14H occurs. The related interrupt request flag (RTF) is

reset and the EMI bit is cleared to disable further inter-

rupts.

The timer/event counter interrupt request flag (TF), ex-

ternal interrupt 1 request flag (EIF1), external interrupt 0

request flag (EIF0), enable timer/event counter interrupt

bit (ETI), enable external interrupt 1 bit (EEI1), enable

external interrupt 0 bit (EEI0), and enable master inter-

rupt bit (EMI) make up of the Interrupt Control register 0

(INTC0) which is located at 0BH in the RAM. The real

time clock interrupt request flag (RTF), time base inter-

rupt request flag (TBF), enable real time clock interrupt

bit (ERTI), and enable time base interrupt bit (ETBI),

constitute the Interrupt Control register 1 (INTC1) which

is located at 1EH in the RAM. EMI, EEI0, EEI1, ETI,

ETBI, and ERTI are all used to control the enable/dis-

able status of interrupts. These bits prevent the re-

quested interrupt from being serviced. Once the

interrupt request flags (RTF, TBF, TF, EIF1, EIF0) are all

set, they remain in the INTC1 or INTC0 respectively until

the interrupts are serviced or cleared by a software in-

struction.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are all held until the ²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set both to 1 (if the stack is not

full). To return from the interrupt subroutine, ²RET² or

²RETI² may be invoked. RETI sets the EMI bit and en-

ables an interrupt service, but RET does not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts

are enabled. In the case of simultaneous requests, the

priorities in the following table apply. These can be

masked by resetting the EMI bit.

It is recommended that a program not use the ²CALL

subroutine² within the interrupt subroutine. It¢s because

interrupts often occur in an unpredictable manner or re-

quire to be serviced immediately in some applications.

At this time, if only one stack is left, and enabling the in-

terrupt is not well controlled, operation of the ²call² in the

interrupt subroutine may damage the original control se-

quence.

Rev. 1.70

14

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Oscillator Configuration

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Although

the system enters the power down mode, the system

clock stops, and the WDT oscillator still works with a pe-

riod of approximately 65ms@5V. The WDT oscillator can

be disabled by options to conserve power.

The device provides three oscillator circuits for system

clocks, i.e., RC oscillator, crystal oscillator and 32768Hz

crystal oscillator, determined by options. No matter what

type of oscillator is selected, the signal is used for the

system clock. The HALT mode stops the system oscilla-

tor (RC and crystal oscillator only) and ignores external

signal to conserve power. The 32768Hz crystal oscillator

(system oscillator) still runs at HALT mode. If the

32768Hz crystal oscillator is selected as the system oscil-

lator, the system oscillator is not stopped; but the instruc-

tion execution is stopped. Since the (used as system

oscillator or oscillator) is also designed for timing pur-

poses, the internal timing (RTC, time base, WDT) opera-

tion still runs even if the system enters the HALT mode.

Watchdog Timer - WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or an instruction clock

(system clock/4) or a real time clock oscillator (RTC os-

cillator). The timer is designed to prevent a software

malfunction or sequence from jumping to an unknown

location with unpredictable results. The WDT can be

disabled by options. But if the WDT is disabled, all exe-

cutions related to the WDT lead to no operation.

Of the three oscillators, if the RC oscillator is used, an

external resistor between OSC1 and VSS is required,

and the range of the resistance should be from 30kW to

750kW for HT49R30A-1/HT49C30-1 and from 560kW to

1MW for HT49C30L. The system clock, divided by 4, is

available on OSC2 with pull-high resistor, which can be

used to synchronize external logic. The RC oscillator

provides the most cost effective solution. However, the

frequency of the oscillation may vary with VDD, temper-

ature, and the chip itself due to process variations. It is

therefore, not suitable for timing sensitive operations

where accurate oscillator frequency is desired.

The WDT time-out period is f_S/2¹⁵~f_S/2¹⁶. If the WDT

clock source chooses the internal WDT oscillator, the

time-out period may vary with temperature, VDD, and

process variations. On the other hand, if the clock

source selects the instruction clock and the ²HALT²

instruction is executed, WDT may stop counting and

lose its protecting purpose, and the logic can only be re-

started by an external logic.

When the device operates in a noisy environment, using

the on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT can stop the system clock.

The WDT overflow under normal operation initializes a

²chip reset² and sets the status bit ²TO². In the HALT

mode, the overflow initializes a ²warm reset², and only

the PC and SP are reset to zero. To clear the contents of

the WDT, there are three methods to be adopted, i.e.,

external reset (a low level to RES), software instruction,

and a ²HALT² instruction. There are two types of soft-

ware instructions; ²CLR WDT² and the other set - ²CLR

WDT1² and ²CLR WDT2². Of these two types of instruc-

tion, only one type of instruction can be active at a time

depending on the options - ²CLR WDT² times selection

option. If the ²CLR WDT² is selected (i.e., CLR WDT

times equal one), any execution of the ²CLR WDT² in-

struction clears the WDT. In the case that ²CLR WDT1²

and ²CLR WDT2² are chosen (i.e., CLR WDT times

equal two), these two instructions have to be executed

to clear the WDT; otherwise, the WDT may reset the

chip due to time-out.

On the other hand, if the crystal oscillator is selected, a

crystal across OSC1 and OSC2 is needed to provide the

feedback and phase shift required for the oscillator, and

no other external components are required. A resonator

may be connected between OSC1 and OSC2 to replace

the crystal and to get a frequency reference, but two ex-

ternal capacitors in OSC1 and OSC2 are required.

There is another oscillator circuit designed for the real

time clock. In this case, only the 32.768kHz crystal oscil-

lator can be applied. The crystal should be connected

between OSC3 and OSC4.

The RTC oscillator circuit can be controlled to oscillate

quickly by setting the ²QOSC² bit (bit 4 of RTCC). It is

recommended to turn on the quick oscillating function

upon power on, and then turn it off after 2 seconds.

V

D

4

7

0

p

F

O

S

C

1

O

S

C

1

O

S

C

3

V

D

O

S

C

4

S

Y

S

O

S

C

2

O

S

C

2

C

r

y

s

t

a

l

O

s

c

i

l

a

t

o

r

R

C

O

s

c

i

l

a

t

o

r

3

2

7

6

8

H

z

C

r

y

s

t

a

l

/

R

T

C

O

s

c

i

l

a

t

o

r

System Oscillator

Rev. 1.70

15

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Multi-function Timer

Real Time Clock - RTC

The device provides a multi-function timer for the WDT,

time base and RTC but with different time-out periods.

The multi-function timer consists of a 8-stage divider

and an 7-bit prescaler, with the clock source coming

from the WDT OSC or RTC OSC or the instruction clock

(i.e., system clock divided by 4). The multi-function timer

also provides a selectable frequency signal (ranges

from f_S/2²to f_S/2⁸) for LCD driver circuits, and a

selectable frequency signal (ranges from f_S/2²to f_S/2⁹)

for the buzzer output by options. It is recommended to

select a near 4kHz signal to LCD driver circuits for

proper display.

The real time clock (RTC) is operated in the same man-

ner as the time base that is used to supply a regular in-

ternal interrupt. Its time-out period ranges from f_S/2⁸to

f_S/2¹⁵by software programming . Writing data to RT2,

RT1 and RT0 (bit2, 1, 0 of RTCC;09H) yields various

time-out periods. If the RTC time-out occurs, the related

interrupt request flag (RTF;bit 5 of INTC1) is set. But if

the interrupt is enabled, and the stack is not full, a sub-

routine call to location 14H occurs. The real time clock

time-out signal also can be applied to be a clock source

of timer/event counter for getting a longer time-out pe-

riod.

RT2

0

RT1

0

RT0 RTC Clock Divided Factor

Time Base

0

1

0

1

0

1

0

1

2⁸*

2⁹*

The time base offers a periodic time-out period to gener-

ate a regular internal interrupt. Its time-out period

ranges from f_S/2¹²to f_S/2¹⁵selected by options. If time

base time-out occurs, the related interrupt request flag

(TBF; bit 4 of INTC1) is set. But if the interrupt is en-

abled, and the stack is not full, a subroutine call to loca-

tion 10H occurs.

0

1

2¹⁰

2¹¹

*

0

1

*

1

0

2¹²

2¹³

2¹⁴

2¹⁵

1

0

1

Note:

²*² not recommended for use

S

y

s

t

e

m

C

l

o

c

k

/

4

R

T

C

f

S

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D

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3

2

7

6

8

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1

5

1

6

1

2

k

H

z

T

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e

s

e

t

f

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~ f / 2

S

O

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C

R

W

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T

C

l

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a

r

Watchdog Timer

f

s

D

i

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P

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c

a

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e

r

O

p

t

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2

8

S S

D r i v e r ( f / 2 ~ f / 2 )

T

i

m

e

B

a

s

e

I

n

t

e

r

u

p

t

L

B

C

D

1

2

1

5

f

S

/

2

S

~ f / 2

2

9

S S

z z e r ( f / 2 ~ f / 2 )

u

Time Base

f

S

D

i

v

i

d

e

r

P

r

e

s

c

a

l

e

r

8

S S

f / 2 ~ f / 2

1

5

R

T

2

8

t

o

1

R

T

1

0

M

u

x

.

R

T

C

I

n

t

e

r

u

p

t

Real Time Clock

Rev. 1.70

16

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Reset

Power Down Operation - HALT

There are three ways in which reset may occur.

The HALT mode is initialized by the ²HALT² instruction

and results in the following.

·

RES is reset during normal operation

·

The system oscillator turns off but the WDT or RTC

RES is reset during HALT

oscillator keeps running (if the WDT oscillator or the

real time clock is selected).

·

WDT time-out is reset during normal operation

The WDT time-out during HALT differs from other chip

reset conditions, for it can perform a ²warm reset² that

resets only the PC and SP and leaves the other circuits

at their original state. Some registers remain unaffected

during any other reset conditions. Most registers are re-

set to the ²initial condition² once the reset conditions are

met. Examining the PDF and TO flags, the program can

distinguish between different ²chip resets².

·

The contents of the on-chip RAM and of the registers

remain unchanged.

The WDT is cleared and start recounting (if the WDT

clock source is from the WDT oscillator or the real time

clock oscillator).

·

All I/O ports maintain their original status.

The PDF flag is set but the TO flag is cleared.

LCD driver is still running (if the WDT OSC or RTC

OSC is selected).

V

D

The system quits the HALT mode by an external reset,

an interrupt, an external falling edge signal on port A, or

a WDT overflow. An external reset causes device initial-

ization, and the WDT overflow performs a ²warm reset².

After examining the TO and PDF flags, the reason for

chip reset can be determined. The PDF flag is cleared

by system power-up or by executing the ²CLR WDT²

instruction, and is set by executing the ²HALT²

instruction. On the other hand, the TO flag is set if WDT

time-out occurs, and causes a wake-up that only resets

the PC (Program Counter) and SP, and leaves the oth-

ers at their original state.

m

0 . 0 1 F *

1

0

k

R

E

S

1

0

k

m

0 . 1 F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by options. Awakening from an I/O port stimulus,

the program resumes execution of the next instruction.

On the other hand, awakening from an interrupt, two se-

quences may occur. If the related interrupt is disabled or

the interrupt is enabled but the stack is full, the program

resumes execution at the next instruction. But if the in-

terrupt is enabled, and the stack is not full, the regular in-

terrupt response takes place.

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES Wake-up HALT

0

u

0

1

0

u

1

u

1

WDT time-out during normal operation

WDT Wake-up HALT

Note:

²u² stands for unchanged

When an interrupt request flag is set before entering the

²HALT² status, the system cannot be awaken using that

interrupt.

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem awakes from the HALT state. Awaking from the

HALT state, the SST delay is added.

If wake-up events occur, it takes 1024 t_SYS(system

clock period) to resume normal operation. In other

words, a dummy period is inserted after the wake-up. If

the wake-up results from an interrupt acknowledgment,

the actual interrupt subroutine execution is delayed by

more than one cycle. However, if the Wake-up results in

the next instruction execution, the execution will be per-

formed immediately after the dummy period is finished.

An extra option load time delay is added during reset

and power on.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

Rev. 1.70

17

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

The functional unit chip reset status is shown below.

V

D

PC

000H

R

E

S

t

S S T

Interrupt

Disabled

Cleared

S

T

i

m

e

-

o

u

t

Prescaler, Divider

C

h

i

p

R

e

s

e

t

WDT, RTC,

Time Base

Cleared. After master reset,

WDT starts counting

Reset Timing Chart

Timer/Event Counter Off

H

A

L

T

Input/output Ports

SP

Input mode

Points to the top of the stack

W

a

r

m

R

e

s

e

t

W

D

T

W

D

T

i

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-

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E

x

t

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n

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S

C

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d

S

T

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e

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1

0

-

b

i

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R

i

p

l

e

O

S

C

1

C

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t

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r

P

o

w

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r

-

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n

D

e

t

e

c

t

i

o

n

Reset Configuration

The states of the registers are summarized below:

WDT Time-out

RES Reset

RES Reset WDT Time-out

Register

TMR

Reset (Power On)

(Norma Operation) (Normal Operation)

(HALT)

xxxx xxxx

0000 1---

0000H

(HALT)*

uuuu uuuu

uuuu u---

0000H

xxxx xxxx

0000 1---

0000H

xxxx xxxx

0000 1---

0000H

xxxx xxxx

0000 1---

0000H

TMRC

Program Counter

MP0

-xxx xxxx

---- ---0

-uuu uuuu

---- ---0

-uuu uuuu

---- ---0

-uuu uuuu

---- ---0

-uuu uuuu

---- ---u

MP1

BP

ACC

xxxx xxxx

--xx xxxx

--00 xxxx

-000 0000

--00 --00

--00 0111

1111 1111

uuuu uuuu

--uu uuuu

--1u uuuu

-000 0000

--00 --00

uuuu uuuu

--uu uuuu

-000 0000

--00 --00

uuuu uuuu

--uu uuuu

--01 uuuu

-000 0000

--00 --00

--00 0111

1111 1111

uuuu uuuu

--uu uuuu

--11 uuuu

-uuu uuuu

--uu --uu

TBLP

TBLH

STATUS

INTC0

INTC1

RTCC

PA

--00 0111

1111 1111

--00 0111

1111 1111

--uu uuuu

uuuu uuuu

Note:

²*² stands for warm reset

²u² stands for unchanged

²x² stands for unknown

Rev. 1.70

18

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Timer/Event Counter

low if the TE bit is ²0²), it will start counting until the

TMR returns to the original level and resets the TON.

The measured result remains in the timer/event counter

even if the activated transient occurs again. In other

words, only one cycle measurement can be made until

the TON is set. The cycle measurement will re-function

as long as it receives further transient pulse. In this oper-

ation mode, the timer/event counter begins counting ac-

cording not to the logic level but to the transient edges.

In the case of counter overflows, the counter is reloaded

from the timer/event counter preload register and issues

an interrupt request, as in the other two modes, i.e.,

event and timer modes.

One timer/event counters is implemented in the device.

It contains an 8-bit programmable count-up counter.

The timer/event counter clock source may come from

the system clock or system clock/4 or RTC time-out sig-

nal or external source. System clock source or system

clock/4 is selected by options. Using external clock input

allows the user to count external events, measure time

internals or pulse widths, or generate an accurate time

base. While using the internal clock allows the user to

generate an accurate time base.

There are two registers related to the timer/event coun-

ter, i.e., TMR ([0DH]) and TMRC ([0EH]). There are also

two physical registers which are mapped to TMR loca-

tion; writing TMR places the starting value in the

timer/event counter preload register, while reading it

yields the contents of the timer/event counter. TMRC is

a timer/event counter control register used to define

some options.

To enable the counting operation, the Timer ON bit

(TON;bit 4 of TMRC) should be set to 1. In the pulse

width measurement mode, the TON is automatically

cleared after the measurement cycle is completed. But

in the other two modes, the TON can only be reset by in-

structions. The overflow of the Timer/Event Counter is

one of the wake-up sources and can also be applied to a

PFD (Programmable Frequency Divider) output at PA3

by options. No matter what the operation mode is, writing

a 0 to ETI disables the related interrupt service. When the

PFD function is selected, executing ²CLR [PA].3² instruc-

tion to enable PFD output and executing ²SET [PA].3² in-

struction to disable PFD output.

The TM0 and TM1 bits define the operation mode. The

event count mode is used to count external events,

which means that the clock source is from an external

TMR pin. The timer mode functions as a normal timer

with the clock source coming from the internal selected

clock source. Finally, the pulse width measurement

mode can be used to count the high or low level duration

of the external signal TMR, and the counting is based on

the internal selected clock source.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter is turn on, data written to the

timer/event counter is kept only in the timer/event coun-

ter preload register. The timer/event counter still contin-

ues its operation until an overflow occurs.

In the event count or timer mode, the timer/event coun-

ter starts counting at the current contents in the

timer/event counter and ends at FFH. Once an overflow

occurs, the counter is reloaded from the timer/event

counter preload register, and generates an interrupt re-

quest flag (TF; bit 6 of INTC0).

When the timer/event counter (reading TMR) is read,

the clock is blocked to avoid errors. As this may results

in a counting error, blocking of the clock should be taken

into account by the programmer.

In the pulse width measurement mode with the values

of the TON and TE bits equal to one, after the TMR

has received a transient from low to high (or high to

S

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C

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M

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X

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I N T

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D

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0

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F

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Q

P

A

3

D

a

t

a

C

T

R

L

Timer/Event Counter

Rev. 1.70

19

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Label

Bits

0~2

3

Function

(TMRC)

¾

Unused bit, read as ²0²

To define the TMR0 active edge of timer/event counter

(0=active on low to high; 1=active on high to low)

TE

To enable/disable timer counting

(0=disabled; 1=enabled)

TON

TS

4

5

2 to 1 multiplexer control inputs to select the timer/event counter clock source

(0=RTC outputs; 1= system clock or system clock/4)

To define the operating mode (TM1, TM0)

01= Event count mode (External clock)

10= Timer mode (Internal clock)

TM0

TM1

6

7

11= Pulse Width measurement mode (External clock)

00= Unused

TMRC Register

It is strongly recommended to load a desired value into

the TMR register first, then turn on the related

timer/event counter for proper operation, because the

initial value of TMR is unknown.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR

[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or to the accumulator. When a PA line is used as

an I/O line, the related PA line options should be config-

ured as NMOS with or without pull-high resistor. Once a

PA line is selected as a CMOS output, the I/O function

cannot be used.

Due to the timer/event scheme, the programmer should

pay special attention on the instruction to enable then

disable the timer for the first time, whenever there is a

need to use the timer/event function, to avoid unpredict-

able result. After this procedure, the timer/event function

can be operated normally.

The input state of a PA line is read from the related PA

pad. When the PA is configured as NMOS with or with-

out pull-high resistor, one should be careful when apply-

ing a read-modify-write instruction to PA. Since the

read-modify-write will read the entire port state (pads

state) firstly, execute the specified instruction and then

write the result to the port data register. When the read

operation is executed, a fault pad state (caused by the

load effect or floating state) may be read. Errors will then

occur.

Input/Output Ports

There are a 8-bit bidirectional input/output port, an 6-bit

input port in the device, labeled PA, PB which are

mapped to [12H], [14H] of the RAM, respectively.

PA0~PA3 can be configured as CMOS (output) or

NMOS (input/output) with or without pull-high resistor by

options. PA4~PA7 are always pull-high and NMOS (in-

put/output).

If you choose NMOS (input), each bit on the port

(PA0~PA7) can be configured as a wake-up input. PB

can only be used for input operation. All the ports for the

input operation (PA, PB), are non-latched, that is, the in-

puts should be ready at the T2 rising edge of the instruc-

tion ²MOV A, [m]² (m=12H or 14H).

There are three function pins that share with the PA port:

PA0/BZ, PA1/BZ and PA3/PFD.

The BZ and BZ are buzzer driving output pair and the

PFD is a programmable frequency divider output. If the

user wants to use the BZ/BZ or PFD function, the related

PA port should be set as a CMOS output. The buzzer

output signals are controlled by PA0 and PA1 data regis-

ters and defined in the following table.

For PA output operation, all data are latched and remain

unchanged until the output latch is rewritten.

When the PA structures are open drain NMOS type, it

should be noted that, before reading data from the pads,

a ²1² should be written to the related bits to disable the

NMOS device. That is executing first the instruction

²SET [m].i² (i=0~7 for PA) to disable related NMOS de-

vice, and then ²MOV A, [m]² to get stable data.

PA1 Data

Register

PA0 Data

Register

PA0/PA1 Pad State

0

1

X

0

1

PA0=BZ, PA1=BZ

PA0=BZ, PA1=0

PA0=0, PA1=0

After chip reset, these input lines remain at the high level

or are left floating (by options). Each bit of these output

latches can be set or cleared by the ²MOV [m], A²

(m=12H) instruction.

Note: ²X² stands for unused

Rev. 1.70

20

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

The PFD output signal function is controlled by the PA3 data register and the timer/event counter state. The PFD output

signal frequency is also dependent on the timer/event counter overflow period. The definitions of PFD control signal

and PFD output frequency are listed in the following table.

Timer

OFF

ON

Timer Preload Value

PA3 Data Register

PA3 Pad State

PFD Frequency

X

N

0

1

0

1

U

0

X

PFD

0

f_INT/[2´(256-N)]

ON

X

Note:

²X² stands for unused

²U² stands for unknown

V

D

V

D

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P

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-

u

p

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p

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M

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(

P

A

0

~

P

A

3

)

O

p

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i

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V

D

(

P

A

0

~

P

A

3

)

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P

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0

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P

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7

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PA Input/Output Ports

PB Input Ports

LCD Display Memory

memory. The LCD display memory can be read and

written to only by indirect addressing mode using MP1.

When data is written into the display data area, it is auto-

matically read by the LCD driver which then generates

the corresponding LCD driving signals. To turn the dis-

play on or off, a ²1² or a ²0² is written to the correspond-

ing bit of the display memory, respectively. The figure

illustrates the mapping between the display memory

and LCD pattern for the device.

The device provides an area of embedded data memory

for LCD display. This area is located from 40H to 52H of

the RAM at Bank 1. Bank pointer (BP; located at 04H of

the RAM) is the switch between the RAM and the LCD

display memory. When the BP is set as ²01H², any data

written into 40H~52H will effect the LCD display. When

the BP is cleared to ²00H², any data written into

40H~52H means to access the general purpose data

4

0

H

4

1

H

4

2

H

4

3

H

5

0

5

1

5

2

B

i

t

C

O

M

0

1

2

3

0

1

2

3

0

1

2

3

1

6

1

7

1

8

S

E

G

M

E

N

T

Display Memory

Rev. 1.70

21

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

LCD Driver Output

voltage for HT49C30L can only be 1/2 bias. If 1/2 bias is

selected, a capacitor mounted between V2 pin and

ground is required. If 1/3 bias is selected, two capacitors

are needed for V1 and V2 pins.

The output number of the LCD driver device can be

19´2, 19´3 or 18´4 by option (i.e., 1/2 duty, 1/3 duty or

1/4 duty). The bias type LCD driver can be ²R² type or

²C² type for HT49R30A-1/HT49C30-1 while the bias

type LCD driver can only be ²C² type for HT49C30L. If

the ²R² bias type is selected, no external capacitor is re-

quired. If the ²C² bias type is selected, a capacitor

mounted between C1 and C2 pins is needed. The LCD

driver bias voltage for HT49R30A-1/HT49C30-1 can be

1/2 bias or 1/3 bias by option, while the LCD driver bias

LCD bias power supply selection for HT49R30A-1/

HT49C30-1: There are two types of selections: 1/2 bias

or 1/3 bias.

LCD bias type selection for HT49R30A-1/HT49C30-1:

This option is to determine what kind of bias is selected,

R type or C type.

D

u

r

i

n

g

a

r

e

s

e

t

p

u

l

s

e

V

A

B

C

A

O

M

0

,

C

O

M

1

,

C

O

M

2

V

S

V

A

B

l

L

C

D

d

r

i

v

e

r

o

u

t

p

u

t

s

V

S

N

o

r

m

a

l

o

p

e

r

a

t

i

o

n

m

o

d

e

V

A

B

*

C

O

M

0

1

2

V

S

V

A

B

V

S

V

A

B

*

V

S

V

A

B

L

C

D

s

e

g

m

e

n

t

s

O

N

O

M

0

,

1

,

2

s

i

d

e

s

a

r

e

u

n

l

i

g

h

t

e

d

V

S

V

A

B

O

C

n

l

y

L

C

D

s

e

g

m

e

n

t

s

O

N

O

M

0

s

i

d

e

a

r

e

l

i

g

h

t

e

d

V

S

V

A

B

O

C

n

l

y

L

C

D

s

e

g

m

e

n

t

s

O

M

1

s

i

d

e

a

r

e

l

i

g

h

t

e

d

V

S

V

A

B

O

C

n

l

y

L

C

D

s

e

g

m

e

n

t

s

O

N

O

M

2

s

i

d

e

a

r

e

l

i

g

h

t

e

d

V

S

V

A

B

L

C

D

s

e

g

m

e

d

n

e

t

s

O

N

O

M

0

,

1

s

i

a

r

e

l

i

g

h

t

e

d

V

S

V

A

B

L

C

D

s

e

g

m

e

n

t

s

O

N

O

M

0

,

2

s

i

d

e

s

a

r

e

l

i

g

h

t

e

d

V

S

V

A

B

L

C

D

s

e

g

m

e

d

n

e

t

s

O

N

O

M

1

,

2

s

i

a

r

e

l

i

g

h

t

e

d

V

S

V

A

B

L

C

D

s

e

g

m

e

n

t

s

O

N

O

M

0

,

1

,

2

s

i

d

e

s

a

r

e

l

i

g

h

t

e

d

V

S

H

A

L

T

M

o

d

e

V

A

B

C

A

O

M

0

,

C

O

M

1

,

C

O

M

2

*

V

S

V

A

B

l

L

C

D

d

r

i

v

e

r

o

u

t

p

u

t

s

V

S

N

o

t

e

:

*

" " O m i t t h e C O M 2 s i g n a l , i f t h e 1 / 2 d u t y L C D i s u s e d .

V

A

=

V

L

C

D

,

V

B

=

1

/

2

V

L

C

D

f

o

r

H

T

4

9

R

3

0

A

-

1

/

H

T

4

9

C

3

0

-

1

V

A

=

2

V

2

,

V

B

=

V

2

,

C

t

y

p

e

f

o

r

H

T

4

9

C

3

0

L

LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type)

Rev. 1.70

22

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

V

A

B

C

O

M

0

V

S

A

S

V

B

C

O

M

1

V

S

A

V

B

C

O

M

2

V

S

A

V

B

C

O

M

3

V

S

A

V

B

L

C

D

s

e

g

m

e

n

t

s

O

N

C

O

M

2

s

i

d

e

l

i

g

h

t

e

d

V

C

S

N

o

t

e

:

1

/

4

d

u

t

y

,

1

/

3

b

i

a

s

,

C

t

y

p

e

:

"

V

A

"

3

/

2

V

L

C

D

,

"

V

B

"

V

L

C

D

,

"

V

C

"

1

/

2

V

L

C

D

1

/

4

d

b

u

t

y

,

1

/

3

b

i

a

s

,

R

t

y

p

e

:

"

V

A

"

V

L

C

D

,

"

V

B

"

2

/

3

V

L

C

D

,

"

V

C

"

1

/

3

V

L

C

D

1

/

3

i

a

s

o

n

l

y

f

o

r

H

T

4

9

R

3

0

A

-

1

/

H

T

4

9

C

3

0

-

1

LCD Driver Output

Low Voltage Reset/Detector Functions for

HT49R30A-1/HT49C30-1

The LVR has the same effect or function with the exter-

nal RES signal which performs chip reset. During HALT

state, LVR is disabled.

There is a low voltage detector (LVD) and a low voltage

reset circuit (LVR) implemented in the microcontroller.

These two functions can be enabled/disabled by op-

tions. Once the options of LVD is enabled, the user can

use the RTCC.3 to enable/disable (1/0) the LVD circuit

and read the LVD detector status (0/1) from RTCC.5;

otherwise, the LVD function is disabled.

The definitions of RTCC register are listed in the follow-

ing table.

Register

Bit No.

Label

RT0~RT2

LVDC*

Read/Write

R/W

Reset

111B

0

Function

8 to 1 multiplexer control inputs to select the real

clock prescaler output

0~2

3

R/W

LVD enable/disable (1/0)

32768Hz OSC quick start-up oscillating

0/1: quickly/slowly start

RTCC

(09H)

4

QOSC

R/W

0

LVD detection output (1/0)

1: low voltage detected

5

LVDO*

R

0

6~7

¾

Unused bit, read as ²0²

Note: ²*² For HT49R30A-1/HT49C30-1

Rev. 1.70

23

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Options

The following shows the options in the device. All these options should be defined in order to ensure proper functioning

system.

Options

OSC type selection.

This option is to determine whether an RC or crystal or 32768Hz crystal oscillator is chosen as system clock.

WDT Clock source selection.

RTC and Time Base. There are three types of selection: system clock/4 or RTC OSC or WDT OSC.

WDT enable/disable selection.

WDT can be enabled or disabled by options.

CLR WDT times selection.

This option defines how to clear the WDT by instruction. ²One time² means that the ²CLR WDT² can clear the WDT.

²Two times² means that if both of the ²CLR WDT1² and ²CLR WDT2² have been executed, only then will the WDT be

cleared.

Time Base time-out period selection.

The Time Base time-out period ranges from clock/2¹²to clock/2¹⁵²Clock² means the clock source selected by op-

tions.

Buzzer output frequency selection.

There are eight types of frequency signals for buzzer output: Clock/2²~Clock/2⁹. ²Clock² means the clock source se-

lected by options.

Wake-up selection.

This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip

from a HALT by a falling edge.

Pull-high selection.

This option is to decide whether the pull-high resistance is visible or not on the PA0~PA3. (PB and PA4~PA7 are al-

ways pull-high)

PA0~PA3 CMOS or NMOS selection.

The structure of PA0~PA3 4 bits can be selected as CMOS or NMOS individually. When the CMOS is selected, the

related pins only can be used for output operations. When the NMOS is selected, the related pins can be used for in-

put or output operations. (PA4~PA7 are always NMOS)

Clock source selection of timer/event counter.

There are two types of selection: system clock or system clock/4.

I/O pins share with other functions selection.

PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.

PA3/PFD: PA3 can be set as I/O pins or PFD output.

LCD common selection.

There are three types of selection: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 com-

mon is selected, the segment output pin ²SEG18² will be set as a common output.

LCD bias power supply selection.

There are two types of selection: 1/2 bias or 1/3 bias for HT49R30A-1/HT49C30-1.

LCD bias type selection.

This option is to determine what kind of bias is selected, R type or C type for HT49R30A-1/HT49C30-1, C type for

HT49C30L.

LCD driver clock selection.

There are seven types of frequency signals for the LCD driver circuits: f_S/2²~f_S/2⁸.

²f_S² means the clock source selection by options.

LCD ON/OFF at HALT selection

LVR selection.

LVR has enable or disable options for HT49R30A-1/HT49C30-1

LVD selection.

LVD has enable or disable options for HT49R30A-1/HT49C30-1

Rev. 1.70

24

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Application Circuits

V

D

C

O

M

0

~

C

O

M

3

7

L

C

D

m

0 . 0 1 F *

S

E

G

0

~

S

E

G

1

V

R

D

P

A

N

E

L

1

0

k

m

0 . 1 F

E

S

V

L

C

D

L

C

D

P

o

w

e

r

S

u

p

l

y

1

0

k

m

0 . 1 F *

C

1

2

V

S

V

D

m

0 . 1 F

R

C

S

y

s

t

e

m

O

s

c

i

l

a

t

o

r

3

0

k

W

O

S

C

W

4

7

0

p

F

O

S

C

1

2

V

1

O

S

C

1

2

O

S

C

m

0 . 1 F

R

O

S

C

S

Y

S

C

i

r

c

u

i

t

V

2

S

e

r

i

g

h

t

s

i

d

e

C

1

m

0 . 1 F

O

S

C

1

2

C

F

r

y

s

t

a

l

S

y

s

t

e

m

O

s

c

i

l

a

t

o

r

o

r

t

h

e

v

a

l

u

e

s

,

3

2

7

6

8

H

z

s

e

t

a

b

l

e

b

e

l

o

w

C

2

O

S

C

3

P

A

0

~

P

A

7

R

1

0

p

F

P

B

0

~

P

B

5

O

S

C

4

O

S

C

1

2

3

O

u

2

7

6

8

H

z

C

r

y

s

t

a

l

S

y

s

t

e

m

I

N

T

0

1

s

c

i

l

a

t

o

r

S

C

1

a

n

d

O

S

C

2

l

e

f

t

n

c

o

n

e

c

t

e

d

T

M

R

H

T

4

9

R

3

0

A

-

1

/

H

T

4

9

C

3

0

-

1

O

S

C

i

r

c

u

i

t

The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)

Crystal or Resonator

4MHz Crystal

C1, C2

0pF

R1

10kW

12kW

10kW

27kW

9.1kW

10kW

4MHz Resonator

10pF

0pF

3.58MHz Crystal

3.58MHz Resonator

2MHz Crystal & Resonator

1MHz Crystal

25pF

35pF

300pF

480kHz Resonator

455kHz Resonator

429kHz Resonator

The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage condi-

tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the

MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.

Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is

stable and remains within a valid operating voltage range before bringing RES to high.

²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise

interference.

Rev. 1.70

25

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

C

O

M

0

~

C

O

M

3

7

L

C

D

O

S

C

3

S

E

G

0

~

S

E

G

1

P

A

N

E

L

V

D

R

C

S

y

s

t

e

m

O

s

c

i

l

a

t

o

r

O

S

C

4

7

0

p

F

V

L

C

D

5

6

0

k

W

O

S

C

W

O

S

C

1

0

.

1

m

F

V

D

R

O

S

C

V

D

S

Y

S

O

S

C

2

C

1

2

1

0

k

2

0

p

F

C

r

y

s

t

a

l

S

y

s

t

e

m

O

s

c

i

l

a

t

o

r

O

S

C

1

R

E

S

V

1

m

0 . 1 F

2

0

p

F

O

S

C

2

V

2

V

D D

I

N

T

0

1

O

S

C

1

3

2

7

6

8

H

z

C

r

y

s

t

a

l

S

y

s

t

e

m

O

u

s

c

i

l

a

t

o

r

P

A

0

~

P

A

7

S

C

1

a

n

d

O

S

C

2

l

e

f

t

T

M

R

P

B

0

~

P

B

5

n

c

o

n

e

c

t

e

d

O

S

C

2

H

T

4

9

C

3

0

L

O

S

C

i

r

c

u

i

t

Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is

stable and remains within a valid operating voltage range before bringing RES to high.

Rev. 1.70

26

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Instruction Set Summary

Instruction

Cycle

Flag

Mnemonic

Arithmetic

Description

Affected

ADD A,[m]

ADDM A,[m]

ADD A,x

Add data memory to ACC

1

1⁽¹⁾

1

Z,C,AC,OV

C

Add ACC to data memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add data memory to ACC with carry

1

1⁽¹⁾

Add ACC to data memory with carry

Subtract immediate data from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

Subtract data memory from ACC

1

1⁽¹⁾

Subtract data memory from ACC with result in data memory

Subtract data memory from ACC with carry

Subtract data memory from ACC with carry and result in data memory

Decimal adjust ACC for addition with result in data memory

1

1⁽¹⁾

Logic Operation

AND A,[m]

OR A,[m]

AND data memory to ACC

1

Z

OR data memory to ACC

XOR A,[m]

ANDM A,[m]

ORM A,[m]

Exclusive-OR data memory to ACC

AND ACC to data memory

OR ACC to data memory

1

1⁽¹⁾

1

XORM A,[m] Exclusive-OR ACC to data memory

AND A,x

OR A,x

AND immediate data to ACC

OR immediate data to ACC

1

XOR A,x

CPL [m]

CPLA [m]

Exclusive-OR immediate data to ACC

Complement data memory

1

1⁽¹⁾

Complement data memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment data memory with result in ACC

1

Z

Increment data memory

1⁽¹⁾

DECA [m]

DEC [m]

Decrement data memory with result in ACC

Decrement data memory

1

1⁽¹⁾

Rotate

RRA [m]

RR [m]

Rotate data memory right with result in ACC

Rotate data memory right

1

1⁽¹⁾

1

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate data memory right through carry with result in ACC

Rotate data memory right through carry

Rotate data memory left with result in ACC

Rotate data memory left

1⁽¹⁾

C

1

None

C

1⁽¹⁾

1

RLCA [m]

RLC [m]

Rotate data memory left through carry with result in ACC

Rotate data memory left through carry

1⁽¹⁾

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move data memory to ACC

Move ACC to data memory

Move immediate data to ACC

1

1⁽¹⁾

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of data memory

Set bit of data memory

1⁽¹⁾

None

Rev. 1.70

27

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Instruction

Cycle

Flag

Mnemonic

Branch

Description

Affected

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if data memory is zero

1⁽²⁾

1⁽³⁾

1⁽²⁾

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if data memory is zero with data movement to ACC

Skip if bit i of data memory is zero

Skip if bit i of data memory is not zero

Skip if increment data memory is zero

Skip if decrement data memory is zero

Skip if increment data memory is zero with result in ACC

Skip if decrement data memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC [m] Read ROM code (current page) to data memory and TBLH

TABRDL [m] Read ROM code (last page) to data memory and TBLH

2⁽¹⁾

None

Miscellaneous

NOP

No operation

1

1⁽¹⁾

1

None

CLR [m]

Clear data memory

SET [m]

Set data memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO,PDF

TO⁽⁴⁾,PDF⁽⁴⁾

None

Pre-clear Watchdog Timer

Swap nibbles of data memory

Swap nibbles of data memory with result in ACC

Enter power down mode

1

1⁽¹⁾

1

None

1

TO,PDF

Note: x: Immediate data

m: Data memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Ö: Flag is affected

-: Flag is not affected

⁽¹⁾: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle

(four system clocks).

⁽²⁾: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more

cycle (four system clocks). Otherwise the original instruction cycle is unchanged.

⁽¹⁾and ⁽²⁾

(3)

:

⁽⁴⁾: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the

CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.

Otherwise the TO and PDF flags remain unchanged.

Rev. 1.70

28

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Instruction Definition

ADC A,[m]

Add data memory and carry to the accumulator

Description

The contents of the specified data memory, accumulator and the carry flag are added si-

multaneously, leaving the result in the accumulator.

Operation

ACC ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADCM A,[m]

Add the accumulator and carry to data memory

Description

The contents of the specified data memory, accumulator and the carry flag are added si-

multaneously, leaving the result in the specified data memory.

Operation

[m] ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADD A,[m]

Add data memory to the accumulator

Description

The contents of the specified data memory and the accumulator are added. The result is

stored in the accumulator.

Operation

ACC ¬ ACC+[m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADD A,x

Add immediate data to the accumulator

Description

The contents of the accumulator and the specified data are added, leaving the result in the

accumulator.

Operation

ACC ¬ ACC+x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADDM A,[m]

Add the accumulator to the data memory

Description

The contents of the specified data memory and the accumulator are added. The result is

stored in the data memory.

Operation

[m] ¬ ACC+[m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

Rev. 1.70

29

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

AND A,[m]

Logical AND accumulator with data memory

Description

Data in the accumulator and the specified data memory perform a bitwise logical_AND op-

eration. The result is stored in the accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

AND A,x

Logical AND immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_AND operation.

The result is stored in the accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

ANDM A,[m]

Logical AND data memory with the accumulator

Description

Data in the specified data memory and the accumulator perform a bitwise logical_AND op-

eration. The result is stored in the data memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

CALL addr

Subroutine call

Description

The instruction unconditionally calls a subroutine located at the indicated address. The

program counter increments once to obtain the address of the next instruction, and pushes

this onto the stack. The indicated address is then loaded. Program execution continues

with the instruction at this address.

Operation

Stack ¬ PC+1

PC ¬ addr

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

CLR [m]

Clear data memory

Description

Operation

The contents of the specified data memory are cleared to 0.

[m] ¬ 00H

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.70

30

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

CLR [m].i

Clear bit of data memory

Description

Operation

The bit i of the specified data memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

CLR WDT

Clear Watchdog Timer

Description

The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are

cleared.

Operation

WDT ¬ 00H

PDF and TO ¬ 0

Affected flag(s)

TO

0

PDF

0

OV

Z

AC

C

¾

CLR WDT1

Preclear Watchdog Timer

Description

Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution

of this instruction without the other preclear instruction just sets the indicated flag which im-

plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT ¬ 00H*

PDF and TO ¬ 0*

Affected flag(s)

TO

0*

PDF

0*

OV

Z

AC

C

¾

CLR WDT2

Preclear Watchdog Timer

Description

Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution

of this instruction without the other preclear instruction, sets the indicated flag which im-

plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT ¬ 00H*

PDF and TO ¬ 0*

Affected flag(s)

TO

0*

PDF

0*

OV

Z

AC

C

¾

CPL [m]

Complement data memory

Description

Each bit of the specified data memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa.

Operation

[m] ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.70

31

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

CPLA [m]

Complement data memory and place result in the accumulator

Description

Each bit of the specified data memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa. The complemented result

is stored in the accumulator and the contents of the data memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

DAA [m]

Decimal-Adjust accumulator for addition

Description

The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-

lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal

carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-

justment is done by adding 6 to the original value if the original value is greater than 9 or a

carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored

in the data memory and only the carry flag (C) may be affected.

Operation

If ACC.3~ACC.0 >9 or AC=1

then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC

else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0

and

If ACC.7~ACC.4+AC1 >9 or C=1

then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1

else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

DEC [m]

Decrement data memory

Description

Operation

Data in the specified data memory is decremented by 1.

[m] ¬ [m]-1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

DECA [m]

Decrement data memory and place result in the accumulator

Description

Data in the specified data memory is decremented by 1, leaving the result in the accumula-

tor. The contents of the data memory remain unchanged.

Operation

ACC ¬ [m]-1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.70

32

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

HALT

Enter power down mode

Description

This instruction stops program execution and turns off the system clock. The contents of

the RAM and registers are retained. The WDT and prescaler are cleared. The power down

bit (PDF) is set and the WDT time-out bit (TO) is cleared.

Operation

PC ¬ PC+1

PDF ¬ 1

TO ¬ 0

Affected flag(s)

TO

0

PDF

1

OV

Z

AC

C

¾

INC [m]

Increment data memory

Description

Operation

Data in the specified data memory is incremented by 1

[m] ¬ [m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

INCA [m]

Increment data memory and place result in the accumulator

Description

Data in the specified data memory is incremented by 1, leaving the result in the accumula-

tor. The contents of the data memory remain unchanged.

Operation

ACC ¬ [m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

JMP addr

Directly jump

Description

The program counter are replaced with the directly-specified address unconditionally, and

control is passed to this destination.

Operation

PC ¬addr

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

MOV A,[m]

Description

Operation

Move data memory to the accumulator

The contents of the specified data memory are copied to the accumulator.

ACC ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.70

33

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

MOV A,x

Move immediate data to the accumulator

Description

Operation

The 8-bit data specified by the code is loaded into the accumulator.

ACC ¬ x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

MOV [m],A

Move the accumulator to data memory

Description

The contents of the accumulator are copied to the specified data memory (one of the data

memories).

Operation

[m] ¬ACC

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

PC ¬ PC+1

TO

PDF

OV

Z

AC

C

¾

OR A,[m]

Logical OR accumulator with data memory

Description

Data in the accumulator and the specified data memory (one of the data memories) per-

form a bitwise logical_OR operation. The result is stored in the accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

OR A,x

Logical OR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_OR operation.

The result is stored in the accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

ORM A,[m]

Logical OR data memory with the accumulator

Description

Data in the data memory (one of the data memories) and the accumulator perform a

bitwise logical_OR operation. The result is stored in the data memory.

Operation

[m] ¬ACC ²OR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.70

34

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

RET

Return from subroutine

Description

Operation

Affected flag(s)

The program counter is restored from the stack. This is a 2-cycle instruction.

PC ¬ Stack

TO

PDF

OV

Z

AC

C

¾

RET A,x

Return and place immediate data in the accumulator

Description

The program counter is restored from the stack and the accumulator loaded with the speci-

fied 8-bit immediate data.

Operation

PC ¬ Stack

ACC ¬ x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RETI

Return from interrupt

Description

The program counter is restored from the stack, and interrupts are enabled by setting the

EMI bit. EMI is the enable master (global) interrupt bit.

Operation

PC ¬ Stack

EMI ¬ 1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RL [m]

Rotate data memory left

Description

Operation

The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RLA [m]

Rotate data memory left and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the

rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0 ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.70

35

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

RLC [m]

Rotate data memory left through carry

Description

The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-

places the carry bit; the original carry flag is rotated into the bit 0 position.

Operation

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

RLCA [m]

Rotate left through carry and place result in the accumulator

Description

Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the

carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored

in the accumulator but the contents of the data memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

RR [m]

Rotate data memory right

Description

Operation

The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7 ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RRA [m]

Rotate right and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving

the rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7 ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RRC [m]

Rotate data memory right through carry

Description

The contents of the specified data memory and the carry flag are together rotated 1 bit

right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.

Operation

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

Rev. 1.70

36

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

RRCA [m]

Rotate right through carry and place result in the accumulator

Description

Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces

the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is

stored in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SBC A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-

tracted from the accumulator, leaving the result in the accumulator.

Operation

ACC ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SBCM A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-

tracted from the accumulator, leaving the result in the data memory.

Operation

[m] ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SDZ [m]

Skip if decrement data memory is 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next

instruction is skipped. If the result is 0, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-

tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]-1)=0, [m] ¬ ([m]-1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SDZA [m]

Decrement data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next

instruction is skipped. The result is stored in the accumulator but the data memory remains

unchanged. If the result is 0, the following instruction, fetched during the current instruction

execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-

cles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]-1)=0, ACC ¬ ([m]-1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.70

37

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

SET [m]

Set data memory

Description

Operation

Each bit of the specified data memory is set to 1.

[m] ¬ FFH

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SET [m]. i

Set bit of data memory

Description

Operation

Bit i of the specified data memory is set to 1.

[m].i ¬ 1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SIZ [m]

Skip if increment data memory is 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the fol-

lowing instruction, fetched during the current instruction execution, is discarded and a

dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with

the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, [m] ¬ ([m]+1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SIZA [m]

Increment data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the next

instruction is skipped and the result is stored in the accumulator. The data memory re-

mains unchanged. If the result is 0, the following instruction, fetched during the current in-

struction execution, is discarded and a dummy cycle is replaced to get the proper

instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, ACC ¬ ([m]+1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SNZ [m].i

Skip if bit i of the data memory is not 0

Description

If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data

memory is not 0, the following instruction, fetched during the current instruction execution,

is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-

wise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i¹0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.70

38

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

SUB A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the

result in the accumulator.

Operation

ACC ¬ ACC+[m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SUBM A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the

result in the data memory.

Operation

[m] ¬ ACC+[m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SUB A,x

Subtract immediate data from the accumulator

Description

The immediate data specified by the code is subtracted from the contents of the accumula-

tor, leaving the result in the accumulator.

Operation

ACC ¬ ACC+x+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SWAP [m]

Swap nibbles within the data memory

Description

The low-order and high-order nibbles of the specified data memory (1 of the data memo-

ries) are interchanged.

Operation

[m].3~[m].0 « [m].7~[m].4

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SWAPA [m]

Swap data memory and place result in the accumulator

Description

The low-order and high-order nibbles of the specified data memory are interchanged, writ-

ing the result to the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.3~ACC.0 ¬ [m].7~[m].4

ACC.7~ACC.4 ¬ [m].3~[m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.70

39

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

SZ [m]

Skip if data memory is 0

Description

If the contents of the specified data memory are 0, the following instruction, fetched during

the current instruction execution, is discarded and a dummy cycle is replaced to get the

proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SZA [m]

Move data memory to ACC, skip if 0

Description

The contents of the specified data memory are copied to the accumulator. If the contents is

0, the following instruction, fetched during the current instruction execution, is discarded

and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed

with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SZ [m].i

Skip if bit i of the data memory is 0

Description

If bit i of the specified data memory is 0, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-

tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

TABRDC [m]

Move the ROM code (current page) to TBLH and data memory

Description

The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved

to the specified data memory and the high byte transferred to TBLH directly.

Operation

[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

TABRDL [m]

Move the ROM code (last page) to TBLH and data memory

Description

The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to

the data memory and the high byte transferred to TBLH directly.

Operation

[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.70

40

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

XOR A,[m]

Logical XOR accumulator with data memory

Description

Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-

sive_OR operation and the result is stored in the accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

XORM A,[m]

Logical XOR data memory with the accumulator

Description

Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-

sive_OR operation. The result is stored in the data memory. The 0 flag is affected.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

XOR A,x

Logical XOR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-

eration. The result is stored in the accumulator. The 0 flag is affected.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.70

41

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Package Information

48-pin SSOP (300mil) Outline Dimensions

4

8

2

5

B

4

A

1

C

'

G

H

D

a

E

F

Dimensions in mil

Symbol

Min.

395

291

8

Nom.

¾

Max.

420

299

12

A

B

C

C¢

D

E

F

¾

613

85

¾

637

99

¾

25

¾

4

10

G

H

a

25

4

35

¾

12

¾

0°

¾

8°

Rev. 1.70

42

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Product Tape and Reel Specifications

Reel Dimensions

D

T

2

C

A

B

T

1

SSOP 48W

Symbol

Description

Dimensions in mm

330±1.0

A

B

Reel Outer Diameter

Reel Inner Diameter

100±0.1

13.0+0.5

-0.2

C

D

Spindle Hole Diameter

Key Slit Width

2.0±0.5

32.2+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

38.2±0.2

Rev. 1.70

43

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Carrier Tape Dimensions

P

0

P

1

t

D

E

F

B

0

W

C

K

1

D

1

P

K

2

A

0

SSOP 48W

Symbol

Description

Dimensions in mm

32.0±0.3

16.0±0.1

1.75±0.1

14.2±0.1

2.0 Min.

W

P

Carrier Tape Width

Cavity Pitch

E

Perforation Position

F

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

D

D1

P0

P1

A0

B0

K1

K2

t

1.5+0.25

4.0±0.1

Cavity to Perforation (Length Direction)

Cavity Length

2.0±0.1

12.0±0.1

16.20±0.1

2.4±0.1

Cavity Width

Cavity Depth

3.2±0.1

Carrier Tape Thickness

Cover Tape Width

0.35±0.05

25.5

C

Rev. 1.70

44

September 21, 2004

HT49R30A-1/HT49C30-1/HT49C30L

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233

Tel: 021-6485-5560

Fax: 021-6485-0313

http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031

Tel: 0755-8346-5589

Fax: 0755-8346-5590

ISDN: 0755-8346-5591

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031

Tel: 010-6641-0030, 6641-7751, 6641-7752

Fax: 010-6641-0125

Holmate Semiconductor, Inc. (North America Sales Office)

46712 Fremont Blvd., Fremont, CA 94538

Tel: 510-252-9880

Fax: 510-252-9885

http://www.holmate.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 1.70

45

September 21, 2004


型号：	HT49R30A-1(48SSOP)
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDSO48 可编程只读存储器微控制器光电二极管
文件：	总45页 (文件大小：309K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT49R30A-1(48SSOP) [HOLTEK]

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