HT49RA0(52QFP-A)_技术文档

HT49RA0/HT49CA0

Remote Type 8-Bit MCU with LCD

Technical Document

·

Tools Information

FAQs

Application Note

-

HA0075E MCU Reset and Oscillator Circuits Application Note

Features

·

Operating voltage: 2.0V~3.6V

8 bidirectional I/O lines and 8 input lines

Two external interrupt input

Watchdog Timer

HALT function and wake-up feature reduce power

consumption

·

4-level subroutine nesting

One 8-bit programmable timer/event counter

LCD driver with 21´2, 21´3 or 20´4 segments

2K´14 program memory

Bit manipulation instruction

14-bit table read instruction

Up to 1ms instruction cycle with 4MHz system clock

63 powerful instructions

96´8 data memory RAM

Real Time Clock (RTC)

All instructions in 1 or 2 machine cycles

Low voltage reset/detector function

52-pin QFP package

8-bit prescaler for RTC

One carrier output (1/2 or 1/3 duty)

Software LCD, RTC control

On-chip RC and 32768Hz crystal oscillator

General Description

The HT49RA0/HT49CA0 are 8-bit high performance,

RISC architecture microcontroller devices specifically

designed for multiple I/O control product applications.

The mask version HT49CA0 is fully pin and functionally

compatible with the OTP version HT49RA0 device.

timer, HALT and wake-up functions, as well as low cost,

enhance the versatility of this device to suit a wide range

of application possibilities such as industrial control,

consumer products, and particularly suitable for use in

products such as infrared LCD remote controllers and

various subsystem controllers.

The advantages of low power consumption, I/O

flexibility, timer functions, oscillator options, watchdog

Rev. 1.40

1

December 16, 2008

HT49RA0/HT49CA0

Block Diagram

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Pin Assignment

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Rev. 1.40

2

December 16, 2008

HT49RA0/HT49CA0

Pin Description

Pin Name

I/O

Options

Description

Bidirectional 8-bit input/output port with pull-high resistors. Each bit can

be determined as NMOS output or Schmitt trigger input by software in-

structions.

PA0~PA7

I/O

¾

PB0/INT0

PB1/INT1

PB2/TMR

PB3~PB7

8-bit Schmitt trigger input port with pull-high resistors. Eash bit can be

configured as a wake-up input by code option.

Pins PB0, PB1 and PB2 are pin-shared with INT0, INT1 and TMR respec-

tively.

I

Wake-up

Level or Carrier Level or carrier output pin

PC0/REM

V1, V2, C1, C2

VLCD

I/O

I

Pull-high

PC0 can be set as CMOS output pin or carrier output pin by code option.

Voltage pump

¾

LCD power supply

V_LCDshould be larger than V_DDfor correct operation i.e. V_LCD³ V_DD

.

COM0~COM2

COM3/SEG20

1/2, 1/3 or 1/4 COM3/SEG20 can be set as a segment or as a common output driver for

O

I

Duty

LCD panel by options. COM0~COM2 are output for LCD panel plate.

LCD driver outputs for LCD panel segments.

SEG0~SEG11

SEG12~SEG19

OSC1

¾

SEG12~SEG19 LCD driver outputs for LCD panel segments.

CMOS output SEG12~SEG19 can be optioned as logical outputs.

RC

OSC1 connect a resistor to GND for internal system clock.

Real time clock oscillator. OSC3 and OSC4 are connected to a 32768Hz

crystal oscillator for timing purpose. It can¢t be used as a system clock. No

capacitor is built-in. If RTC is not selected as fs. OSC3,OSC4 should be

left floating.

OSC3

OSC4

I

¾

O

RES

VSS

VDD

I

Schmitt trigger reset input, active low.

Negative power supply, ground

Positive power supply

¾

Absolute Maximum Ratings

Supply Voltage...........................V_SS-0.3V to V_SS+6.0V

Input Voltage..............................V_SS-0.3V to V_DD+0.3V

Storage Temperature............................-50°C to 125°C

Operating Temperature...........................-40°C to 85°C

I_OHTotal............................................................-100mA

I

_OLTotal ..............................................................150mA

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed

in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics

Ta=25°C

Test Conditions

Conditions

¾

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

I_DD

Operating Voltage

2.0

3.6

1.5

V

¾

Operating Current

(RC OSC)

No load, f_SYS=4MHz

3V

0.7

mA

¾

Standby Current

(*f_S=T1)

No load, system HALT,

LCD off at HALT

I_STB1

0.1

2.5

1

5

¾

mA

Standby Current

No load, system HALT,

LCD On at HALT, C type

I_STB2

(*f_S=32.768kHz OSC)

Rev. 1.40

3

December 16, 2008

HT49RA0/HT49CA0

Test Conditions

Conditions

Symbol

Parameter

Standby Current

Min.

Typ.

Max.

Unit

V_DD

No load, system HALT

LCD On at HALT, C type

I_STB3

3V

2

5

¾

0

mA

V

(*f_S=WDT RC OSC)

Input Low Voltage for I/O

V_IL1

0.3V_DD

3V

¾

Ports, TMR, INT0 and INT1

Input High Voltage for I/O

Ports, TMR, INT0 and INT1

V_IH1

0.7V_DD

V_DD

V

V_IL2

V_IH2

I_OL1

I_OH1

0.4V_DD

V_DD

¾

Input Low Voltage (RES)

3V

0

0.9V_DD

4

V

¾

8

Input High Voltage (RES)

I/O Port & REM Sink Current

I/O Port & REM Source Current

V_OL=0.1V_DD

V_OH=0.9V_DD

mA

-5

-7

¾

LCD Common and Segment

Current

I_OL2

V

_OL=0.1V_DD

_OH=0.9V_DD

3V

210

420

¾

mA

LCD Common and Segment

Current

I_OH2

-80

-160

R_PH

Pull-high Resistance of I/O Ports 3V

100

2.0

2.2

150

2.1

2.3

200

2.2

2.4

¾

kW

V

V_LVR

V_LVD

Low Voltage Reset Voltage

Low Voltage Detector Voltage

¾

V

VDD Start Voltage to Ensure

Power-on Reset

V_POR

R_POR

Note:

100

mV

¾

VDD Rise Rate to Ensure

Power-on Reset

0.035

V/ms

¾

²*² for the value of VA refer to the LCD driver section.

t_SYS=1/f_SYS

²*f_S² please refer to WDT clock option

A.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

2.0V~3.6V, 4MHz ± 3%,

Temp.= 0°C ~ 50°C

f_SYS

System Clock

4000

kHz

¾

f_RTCOSC

f_TIMER

t_WDTOSC

t_RES

RTC Frequency

32768

¾

Hz

kHz

ms

¾

3V

¾

0

¾

4000

180

¾

Timer I/P Frequency (TMR)

Watchdog Oscillator Period

External Reset Low Pulse Width

Low Voltage Width to Reset

System Start-up Timer Period

Interrupt Pulse Width

¾

45

1

90

¾

ms

t_LVR

0.25

¾

1

2

ms

¾

Wake-up from HALT

¾

t_SST

*t_SYS

1024

¾

t_INT

¾

ms

Note: *t_SYS=1/f_SYS

Rev. 1.40

4

December 16, 2008

HT49RA0/HT49CA0

Functional Description

Execution Flow

After accessing a program memory word to fetch an in-

struction code, the value of the PC is incremented by

one. The PC then points to the memory word containing

the next instruction code.

The system clock is derived from RC oscillator. It is inter-

nally divided into four non-overlapping clocks. One in-

struction cycle consists of four system clock cycles.

When executing a jump instruction, conditional skip ex-

ecution, loading a PCL register, a subroutine call, an ini-

tial reset, an internal interrupt, an external interrupt, or

returning from a subroutine, the PC manipulates the

program transfer by loading the address corresponding

to each instruction.

Instruction fetching and execution are pipelined in such

a way that a fetch takes one instruction cycle while de-

coding and execution takes the next instruction cycle.

The pipelining scheme causes each instruction to effec-

tively execute in a cycle. If an instruction changes the

value of the program counter, two cycles are required to

complete the instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get a proper instruction; oth-

erwise proceed with the next instruction.

Program Counter - PC

The program counter (PC) is of 11 bits wide and controls

the sequence in which the instructions stored in the pro-

gram ROM are executed. The contents of the PC can

specify a maximum of 2048 addresses.

The lower byte of the PC (PCL) is a readable and

writeable register (06H). Moving data into the PCL per-

forms a short jump. The destination is within 256 locations.

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Execution Flow

Program Counter

Mode

*10

0

*9

0

*8

0

*7

0

*6

0

*5

0

*4

0

1

*3

0

1

0

*2

0

1

0

1

0

1

*1

0

*0

0

Initial Reset

External Interrupt 0

External Interrupt 1

0

Timer/Event Counter overflow

Time Base Interrupt

RTC Interrupt

0

Skip

Program Counter + 2

Loading PCL

*10

#10

S10

*9

*8

#8

S8

@7

#7

@6

#6

@5

#5

@4

#4

@3

#3

@2

#2

@1

#1

@0

#0

Jump, Call Branch

Return From Subroutine

#9

S9

S7

S6

S5

S4

S3

S2

S1

S0

Program Counter

Note: *10~*0: Program counter bits

#10~#0: Instruction code bits

S10~S0: Stack register bits

@7~@0: PCL bits

Rev. 1.40

5

December 16, 2008

HT49RA0/HT49CA0

·

Location 014H

When a control transfer takes place, an additional

dummy cycle is required.

Location 014H is reserved for the real time clock inter-

rupt service program. If a real time clock interrupt oc-

curs, and the interrupt is enabled, and the stack is not

full, the program begins execution at location 014H.

Program Memory - ROM

The program memory (ROM) is used to store the pro-

gram instructions which are to be executed. It also con-

tains data, table, and interrupt entries, and is organized

into 2048 ´ 14 bits which are addressed by the program

counter and table pointer.

Table location

Any location in the ROM can be used as a look-up ta-

ble. The instructions ²TABRDC [m]² (the current page,

1 page=256 words) and ²TABRDL [m]² (the last page)

transfer the contents of the lower-order byte to the

specified data memory, and the contents of the

higher-order byte to TBLH (Table Higher-order byte

register) (08H). Only the destination of the lower-order

byte in the table is well-defined; the other bits of the ta-

ble word are all transferred to the lower portion of

TBLH, and the remaining 2 bit is read as ²0². The

TBLH is read only, and the table pointer (TBLP) is a

read/write register (07H), indicating the table location.

Before accessing the table, the location should be

placed in TBLP. All the table related instructions re-

quire 2 cycles to complete the operation. These areas

may function as a normal ROM depending upon the

user¢s requirements.

Certain locations in the ROM are reserved for special

usage:

·

Location 000H

Location 000H is reserved for program initialization.

After chip reset, the program always begins execution

at this location.

·

Location 004H

Location 004H is reserved for the external interrupt

service program. If the INT0 input pin is activated, and

the interrupt is enabled, and the stack is not full, the

program begins execution at location 004H.

·

Location 008H

0

4

8

H

Location 008H is reserved for the external interrupt

service program also. If the INT1 input pin is activated,

and the interrupt is enabled, and the stack is not full,

the program begins execution at location 008H.

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Location 00CH

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Location 00CH is reserved for the Timer/Event Coun-

ter interrupt service program. If a timer interrupt re-

sults from a Timer/Event Counter overflow, and if the

interrupt is enabled and the stack is not full, the pro-

gram begins execution at location 00CH.

0

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4

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·

Location 010H

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(

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6

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7

F

H

Location 010H is reserved for the Time Base interrupt

service program. If a Time Base interrupt occurs, and

the interrupt is enabled, and the stack is not full, the

program begins execution at location 010H.

7

0

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6

Program Memory

Table Location

Instruction(s)

*10

P10

1

*9

P9

1

*8

P8

1

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

@7

@6

@5

@4

@3

@2

@1

@0

Table Location

P10~P8: Current program Counter bits

Note: *10~*0: Table location bits

@7~@0: Table pointer bits

Rev. 1.40

6

December 16, 2008

HT49RA0/HT49CA0

Stack Register - STACK

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9

H

M

P

0

The stack register is a special part of the memory used

to save the contents of the program counter. The stack

is organized into 4 levels and is neither part of the data

nor part of the program, and is neither readable nor

writeable. Its activated level is indexed by a stack

pointer (SP) and is neither readable nor writeable. At a

commencement of a subroutine call or an interrupt ac-

knowledgment, the contents of the program counter is

pushed onto the stack. At the end of the subroutine or in-

terrupt routine, signaled by a return instruction (RET or

RETI), the contents of the program counter is restored

to its previous value from the stack. After chip reset, the

SP will point to the top of the stack.

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If the stack is full and a non-masked interrupt takes

place, the interrupt request flag is recorded but the ac-

knowledgment is still inhibited. Once the SP is decre-

mented (by RET or RETI), the interrupt is serviced. This

feature prevents stack overflow, allowing the program-

mer to use the structure easily. Likewise, if the stack is

full, and a ²CALL² is subsequently executed, a stack

overflow occurs and the first entry is lost (only the most

recent 4 return addresses are stored).

0

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P

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B

P

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P

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1

8

9

H

Data Memory - RAM

1

A

B

H

The data memory is divided into two functional group :

special function registers (20´8) and general purpose

data memory (96´8). Most of them are read/write, but

some are read only.

1

C

D

H

:

U

n

u

s

e

d

.

I

N

T

C

1

E

H

1

F

H

L

C

D

C

The unused space before 20H is reserved for future ex-

panded usage and reading these locations will return

the result 00H. The general purpose data memory, ad-

dressed from 20H to 7FH, is used for data and control

information under instruction command. The areas in

the RAM can directly handle arithmetic, logic, incre-

ment, decrement, and rotate operations. Except some

dedicated bits, each bit in the RAM can be set and reset

by ²SET [m].i² and ²CLR [m].i². They are also indirectly

accessible through the Memory pointer register 0

(MP0;01H) or the Memory pointer register 1 (MP1;03H).

R

²

2

0

H

G

e

n

e

r

a

l

P

u

r

p

o

s

e

D

a

t

a

M

e

m

o

r

y

(

9

6

B

y

t

e

s

)

7

F

H

RAM Mapping

Accumulator - ACC

The accumulator (ACC) is related to the ALU opera-

tions. It is also mapped to location 05H of the RAM and

is capable of operating with immediate data. The data

movement between two data memory locations must

pass through the ACC.

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] and [02H] accesses the RAM pointed to

by MP0 (01H) and MP1(03H) respectively. Reading lo-

cation 00H or 02H indirectly returns the result 00H.

While, writing it indirectly leads to no operation.

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic opera-

tions and provides the following functions:

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

The function of data movement between two indirect ad-

dressing registers is not supported. The memory pointer

registers, MP0 and MP1, are both 7-bit registers used to

access the RAM by combining corresponding indirect

addressing registers. MP0 can only be applied to data

memory, while MP1 can be applied to data memory and

LCD display memory.

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ etc.)

The ALU not only saves the results of a data operation but

also changes the status register.

Rev. 1.40

7

December 16, 2008

HT49RA0/HT49CA0

Status Register - STATUS

Once an interrupt subroutine is serviced, other inter-

rupts are all blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may take place during this interval,

but only the interrupt request flag will be recorded. If a

certain interrupt requires servicing within the service

routine, the EMI bit and the corresponding bit of the

INTC0 or of INTC1 may be set in order to allow interrupt

nesting. Once the stack is full, the interrupt request will

not be acknowledged, even if the related interrupt is en-

abled, until the Stack Pointer is decremented. If immedi-

ate service is desired, the stack should be prevented

from becoming full.

The status register (0AH) is of 8 bits wide and contains,

a carry flag (C), an auxiliary carry flag (AC), a zero flag

(Z), an overflow flag (OV), a power down flag (PDF), and

a watchdog time-out flag (TO). It also records the status

information and controls the operation sequence.

Except the TO and PDF flags, bits in the status register

can be altered by instructions similar to other registers.

Data written into the status register does not alter the TO

or PDF flags. Operations related to the status register,

however, may yield different results from those in-

tended. The TO and PDF flags can only be changed by

a Watchdog Timer overflow, chip power-up, or clearing

the Watchdog Timer and executing the ²HALT² instruc-

tion. The Z, OV, AC, and C flags reflect the status of the

latest operations.

All these interrupts can support a wake-up function. As

an interrupt is serviced, a control transfer occurs by

pushing the contents of the program counter onto the

stack followed by a branch to a subroutine at the speci-

fied location in the ROM. Only the contents of the pro-

gram counter is pushed onto the stack. If the contents of

the register or of the status register (STATUS) is altered

by the interrupt service program which corrupts the de-

sired control sequence, the contents should be saved in

advance.

On entering the interrupt sequence or executing the

subroutine call, the status register will not be automati-

cally pushed onto the stack. If the contents of the status

is important, and if the subroutine is likely to corrupt the

status register, the programmer should take precautions

and save it properly.

External interrupts are triggered by a high to low or low

to high or both transition of INT0 or INT1, and the related

interrupt request flag (EIF0;bit 4 of INTC0, EIF1;bit 5 of

INTC0) is set as well. After the interrupt is enabled, the

stack is not full, and the external interrupt is active, a

subroutine call to location 04H or 08H occurs. The inter-

rupt request flag (EIF0 or EIF1) and EMI bits are all

cleared to disable other interrupts.

Interrupts

The devices provides two external interrupts, one inter-

nal timer/event counter interrupts, an internal time base

interrupt, and an internal real time clock interrupt. The

interrupt control register 0 (INTC0;0BH) and interrupt

control register 1 (INTC1;1EH) both contain the interrupt

control bits that are used to set the enable/disable status

and interrupt request flags.

Bit No.

Label

Function

C is set if the operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-

tate through carry instruction.

0

C

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

1

2

3

AC

Z

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

OV

PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is

set by executing the ²HALT² instruction.

4

PDF

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO

is set by a WDT time-out.

5

TO

6, 7

¾

Unused bit, read as ²0²

Status (0AH) Register

Rev. 1.40

8

December 16, 2008

HT49RA0/HT49CA0

The internal Timer/Event Counter interrupt is initialized

by setting the Timer/Event Counter interrupt request flag

(TF;bit 6 of INTC0), which is normally caused by a timer

overflow. After the interrupt is enabled, and the stack is

not full, and the TF bit is set, a subroutine call to location

0CH occurs. The related interrupt request flag (TF) is re-

set, and the EMI bit is cleared to disable further interrupts.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts

are enabled. In the case of simultaneous requests, the

priorities in the following table apply. These can be

masked by resetting the EMI bit.

Interrupt Source

External interrupt 0

Priority

Vector

04H

The time base interrupt is initialized by setting the time

base interrupt request flag (TBF;bit 4 of INTC1), that is

caused by a regular time base signal. After the interrupt

is enabled, and the stack is not full, and the TBF bit is

set, a subroutine call to location 10H occurs. The related

interrupt request flag (TBF) is reset and the EMI bit is

cleared to disable further interrupts.

1

2

3

4

5

External interrupt 1

08H

Timer/Event Counter overflow

Time base interrupt

0CH

10H

Real time clock interrupt

14H

The real time clock interrupt is initialized by setting the

real time clock interrupt request flag (RTF; bit 5 of

INTC1), that is caused by a regular real time clock signal.

After the interrupt is enabled, and the stack is not full, and

the RTF bit is set, a subroutine call to location 14H oc-

curs. The related interrupt request flag (RTF) is reset and

the EMI bit is cleared to disable further interrupts.

The EMI, EEI0, EEI1, ETI, ETBI and ERTI are all used to

control the enable/disable status of interrupts. These

bits prevent the requested interrupt from being serviced.

Once the interrupt request flags (RTF, TBF, TF, EIF1,

EIF0) are all set, they remain in the INTC1 or INTC0 re-

spectively until the interrupts are serviced or cleared by

a software instruction.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are all held until the ²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set both to 1 (if the stack is not

full). To return from the interrupt subroutine, ²RET² or

²RETI² may be invoked. RETI sets the EMI bit and en-

ables an interrupt service, but RET does not.

Bit No.

Label

EMI

EEI0

EEI1

ETI

Function

0

1

2

3

4

5

6

7

Controls the master (global) interrupt (1=enabled; 0=disabled)

Controls the external interrupt 0 (1=enabled; 0=disabled)

Controls the external interrupt 1 (1=enabled; 0=disabled)

Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)

External interrupt 0 request flag (1=active; 0=inactive)

External interrupt 1 request flag (1=active; 0=inactive)

Internal Timer/Event Counter request flag (1=active; 0=inactive)

Unused bit, read as ²0²

EIF0

EIF1

TF

¾

INTC0 (0BH) Register

Bit No.

Label

ETBI

ERTI

¾

Function

Controls the time base interrupt (1=enabled; 0:disabled)

Controls the real time clock interrupt (1=enabled; 0:disabled)

Unused bit, read as ²0²

0

1

2, 3

4

TBF

RTF

¾

Time base request flag (1=active; 0=inactive)

Real time clock request flag (1=active; 0=inactive)

Unused bit, read as ²0²

5

6, 7

INTC1 (1EH) Register

Rev. 1.40

9

December 16, 2008

HT49RA0/HT49CA0

Oscillator Configuration

It is recommended that a program not use the ²CALL

subroutine² within the interrupt subroutine. It¢s because

interrupts often occur in an unpredictable manner or re-

quire to be serviced immediately in some applications.

At this time, if only one stack is left, and enabling the in-

terrupt is not well controlled, operation of the ²call² in the

interrupt subroutine may damage the original control se-

quence.

An external resistor between OSC1 and VSS in needed

and the resistance is about 12kW. The RC oscillator

provides a ±3% accuracy, the conditions are:

·

V_DD=2.0V~3.6V

Temp.= 0°C ~ 50°C

f_SYS=4MHz

O

S

C

1

R

C

O

s

c

i

l

a

t

o

r

System Oscillator

LCD/RTC OSC Control Register

Two bit in (1FH) are for controlling LCD and RTC OSC.

Bit No.

Label

RTCEN

LCDEN

¾

Function

0

1

Controls RTC OSC enable (1=enabled; 0=disabled)

Controls LCD enable (1=enabled; 0=disabled)

Unused bit, read as ²0²

2~7

LCDC (1FH) Register

LCDEN and RTCEN may decide LCD and RTC On/Off condition on normal operation.

LCD/WDT Control Bits

f_SClock

Source

LCDEN, RTCEN=0, 0 LCDEN, RTCEN=0, 1 LCDEN, RTCEN=1, 0 LCDEN, RTCEN=1, 1

f_SYS/4

LCD off, RTC off

LCD on, RTC off

WDT OSC

RTC OSC

LCD off, RTC on

LCD off, RTC off

LCD off, RTC on

LCD on, RTC on

(WDT enable)

RTC OSC

(WDT disable)

Rev. 1.40

10

December 16, 2008

HT49RA0/HT49CA0

Watchdog Timer - WDT

(TBF; bit 4 of INTC1) is set. But if the interrupt is en-

abled, and the stack is not full, a subroutine call to loca-

tion 10H occurs.

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or an instruction clock

(system clock/4) or a real time clock oscillator (RTC os-

cillator). The timer is designed to prevent a software

malfunction or sequence from jumping to an unknown

location with unpredictable results. The WDT can be

disabled by option. But if the WDT is disabled, all execu-

tions related to the WDT lead to no operation.

f

S

D

i

v

i

d

e

r

P

r

e

s

c

a

l

e

r

O

p

t

i

o

n

O

p

t

i

o

n

2

8

The WDT time-out period is as f_S/2¹⁶~f_S/2¹⁵

.

T

i

m

e

B

a

s

e

I

n

t

e

r

u

p

t

L

B

C

D

r

i

v

e

r

(

f

S

/

2

~

f

S

/

2

)

1

2

1

5

2

9

(

f

S

/

2

~

f

S

/

2

)

u

z

e

r

(

f

S

/

2

~

f

S

/

2

)

If the WDT clock source chooses the internal WDT oscilla-

tor, the time-out period may vary with temperature, VDD,

and process variations. On the other hand, if the clock

source selects the instruction clock and the ²HALT² in-

struction is executed, WDT may stop counting and lose its

protecting purpose, and the logic can only be restarted by

an external logic.

Time Base

Real Time Clock - RTC

The real time clock (RTC) is operated in the same man-

ner as the time base that is used to supply a regular inter-

nal interrupt. Its time-out period ranges from f_S/2⁸to

f_S/2¹⁵by software programming . Writing data to RT2,

RT1 and RT0 (bit2, 1, 0 of RTCC;09H) yields various

time-out periods. If the RTC time-out occurs, the related

interrupt request flag (RTF; bit 5 of INTC1) is set. But if

the interrupt is enabled, and the stack is not full, a subrou-

tine call to location 14H occurs. The real time clock

time-out signal also can be applied to be a clock source of

Timer/Event Counter for getting a longer time-out period.

When the device operates in a noisy environment, using

the on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT can stop the system clock.

The WDT overflow under normal operation initializes a

²chip reset² and sets the status bit ²TO². In the HALT

mode, the overflow initializes a ²warm reset², and only

the program counter and stack pointer are reset to zero.

To clear the contents of the WDT, there are three meth-

ods to be adopted, i.e., external reset (a low level to

RES), software instruction, and a ²HALT² instruction.

There are two types of software instructions; ²CLR

WDT² and the other set - ²CLR WDT1² and ²CLR

WDT2². Of these two types of instruction, only one type

of instruction can be active at a time depending on the

options - ²CLR WDT² times selection option. If the ²CLR

WDT² is selected (i.e., CLR WDT times equal one), any

execution of the ²CLR WDT² instruction clears the WDT.

In the case that ²CLR WDT1² and ²CLR WDT2² are

chosen (i.e., CLR WDT times equal two), these two in-

structions have to be executed to clear the WDT; other-

wise, the WDT may reset the chip due to time-out.

RT2

0

RT1

0

RT0 RTC Clock Divided Factor

0

1

0

1

0

1

0

1

2^8*

2^9*

0

1

2^10*

2^11*

2¹²

2¹³

2¹⁴

2¹⁵

0

1

0

1

0

1

Note: ²*² not recommended to be used

f

S

D

i

v

i

d

e

r

P

r

e

s

c

a

l

e

r

Time Base

8

1

5

R

T

2

8

t

o

1

f

S

/

2

S

~ f / 2

R

T

1

0

The time base offers a periodic time-out period to gener-

ate a regular internal interrupt. Its time-out period

ranges from f_S/2¹²to f_S/2¹⁵selected by options. If time

base time-out occurs, the related interrupt request flag

M

u

x

.

R

T

C

I

n

t

e

r

u

p

t

Real Time Clock

S

y

s

t

e

m

C

l

o

c

k

/

4

R

T

C

f

S

O

p

t

i

o

n

3

2

7

6

8

H

z

D

i

v

i

d

e

r

P

r

e

s

c

a

l

e

r

O

S

C

S

e

l

e

c

t

C

K

T

C

K

T

W

D

T

i

m

e

-

o

u

t

R

e

s

e

t

1

2

k

H

z

1

6

1

5

O

S

C

R

f

S

/

2

S

~ f / 2

W

D

T

C

l

e

a

r

Watchdog Timer

Rev. 1.40

11

December 16, 2008

HT49RA0/HT49CA0

Reset

Power Down Operation - HALT

There are three ways in which reset may occur.

The HALT mode is initialized by the ²HALT² instruction

and results in the following.

·

RES is reset during normal operation

·

The system oscillator turns off but the WDT OSC

RES is reset during HALT

keeps running (if the WDT oscillator or the real time

clock is selected).

·

WDT time-out is reset during normal operation

The WDT time-out during HALT differs from other chip

reset conditions, for it can perform a ²warm reset² that

resets only the program counter and stack pointer and

leaves the other circuits at their original state. Some reg-

isters remain unaffected during any other reset condi-

tions. Most registers are reset to the ²initial condition²

once the reset conditions are met. Examining the PDF

and TO flags, the program can distinguish between dif-

ferent ²chip resets².

·

The contents of the on-chip RAM and of the registers

remain unchanged.

The WDT is cleared and start recounting (if the WDT

clock source is from the WDT oscillator or the real time

clock oscillator).

·

All I/O ports maintain their original status.

The PDF flag is set but the TO flag is cleared.

The system quits the HALT mode by an external reset,

an interrupt, an external falling edge signal on port B, or

a WDT overflow. An external reset causes device initial-

ization, and the WDT overflow performs a ²warm reset².

After examining the TO and PDF flags, the reason for

chip reset can be determined. The PDF flag is cleared by

system power-up or by executing the ²CLR WDT² in-

struction, and is set by executing the ²HALT² instruction.

On the other hand, the TO flag is set if WDT time-out oc-

curs, and causes a wake-up that only resets the program

counter and Stack Pointer, and leaves the others at their

original state.

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES Wake-up HALT

0

u

0

1

0

u

1

u

1

WDT time-out during normal operation

WDT Wake-up HALT

The port B wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port B can be independently selected to wake-up the

device by option. Awakening from an I/O port stimulus,

the program resumes execution of the next instruction.

On the other hand, awakening from an interrupt, two se-

quences may occur. If the related interrupt is disabled or

the interrupt is enabled but the stack is full, the program

resumes execution at the next instruction. But if the in-

terrupt is enabled, and the stack is not full, the regular in-

terrupt response takes place.

Note:

²u² means unchanged

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem awakes from the HALT state. Awaking from the

HALT state, the SST delay is added.

An extra SST delay is added during the power-up period

and any wakeup from the HALT may enable only the

SST delay.

When an interrupt request flag is set before entering the

²HALT² status, the system cannot be awaken using that

interrupt.

The functional unit chip reset status is shown below.

Program Counter

Interrupt

000H

Disabled

Cleared

If wake-up events occur, it takes 1024 t_SYS(system

clock period) to resume normal operation. In other

words, a dummy period is inserted after the wake-up. If

the wake-up results from an interrupt acknowledgment,

the actual interrupt subroutine execution is delayed by

more than one cycle. However, if the Wake-up results in

the next instruction execution, the execution will be per-

formed immediately after the dummy period is finished.

Prescaler, Divider

WDT, RTC,

Time base

Cleared. After master reset,

WDT starts counting

Timer/Event Counter Off

Input/output ports

Stack Pointer

Input mode

Points to the top of the stack

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

When at HALT state and f_S=f_SYS/4, LCD and RTC will be

turned off no matter the bit value of (LCDEN, RTCEN).

Rev. 1.40

12

December 16, 2008

HT49RA0/HT49CA0

V

D

V

D

V

D

m

0 . 0 1 F

R

E

S

t

S S T

1

0

k

1

0

k

S

T

i

m

e

-

o

u

t

R

E

S

R

E

S

C

h

i

p

R

e

s

e

t

m

0 . 1 F

1

0

k

Reset Timing Chart

B

a

s

i

c

H

i

-

n

o

i

s

e

R

e

s

e

t

R

e

s

e

t

m

0 . 1 F

C

i

r

c

u

i

t

C

i

r

c

u

i

t

H

A

L

T

W

a

r

m

R

e

s

e

t

Reset Circuit

W

D

T

W

D

T

i

m

e

-

o

u

t

Note: Most applications can use the Basic Reset Circuit

as shown, however for applications with extensive noise,

it is recommended to use the Hi-noise Reset Circuit.

R

e

s

e

t

E

x

t

e

r

n

a

l

R

E

S

C

o

l

d

R

e

s

e

t

S

T

1

0

-

b

i

t

R

i

p

l

e

O

S

C

1

C

o

u

n

t

e

r

P

o

w

e

r

-

o

n

D

e

t

e

c

t

i

o

n

Reset Configuration

The states of the registers are summarized below:

Reset

WDT Time-out

RES Reset

(HALT)

WDT Time-out

(HALT)*

Register

(Power-on) (Normal Operation) (Normal Operation)

MP0

MP1

BP

-xxx xxxx

0000 0000

xxxx xxxx

000H

-uuu uuuu

0000 0000

uuuu uuuu

000H

-uuu uuuu

0000 0000

uuuu uuuu

000H

-uuu uuuu

0000 0000

uuuu uuuu

000H

-uuu uuuu

uuuu uuuu

000H

ACC

Program Counter

TBLP

xxxx xxxx

--xx xxxx

--00 0111

--00 xxxx

-000 0000

xxxx xxxx

0000 1---

1111 1111

---- ---1

uuuu uuuu

--uu uuuu

--00 0111

--1u uuuu

-000 0000

xxxx xxxx

0000 1---

1111 1111

---- ---1

uuuu uuuu

--uu uuuu

--00 0111

--uu uuuu

-000 0000

xxxx xxxx

0000 1---

1111 1111

---- ---1

uuuu uuuu

--uu uuuu

--00 0111

--01 uuuu

-000 0000

xxxx xxxx

0000 1---

1111 1111

---- ---1

uuuu uuuu

--uu uuuu

--11 uuuu

-uuu uuuu

uuuu uuuu

uuuu u---

uuuu uuuu

---- ---u

TBLH

RTCC

STATUS

INTC0

TMR

TMRC

PA

PB

PC

PCC

---- ---1

---- ---u

INTC1

LCDC

--00 --00

---- --11

--00 --00

---- --11

--00 --00

---- --11

--00 --00

---- --11

--uu --uu

---- --uu

Note:

²*² refers to warm reset

²u² means unchanged

²x² means unknown

²-² means unimplemented

Rev. 1.40

13

December 16, 2008

HT49RA0/HT49CA0

Timer/Event Counter

mode can be used to count the high or low level duration

of the external signal (TMR), and the counting is based

on the internal selected clock source.

One timer/event counters are implemented in the devices.

It contains an 8-bit programmable count-up counter.

In the event count or timer mode, the timer/event coun-

ter starts counting at the current contents in the

timer/event counter and ends at FFH. Once an overflow

occurs, the counter is reloaded from the timer/event

counter preload register, and generates an interrupt re-

quest flag (TF;bit 6 of INTC0).

The timer/event counter clock source may come from

the system clock or system clock/4 or RTC time-out sig-

nal or external source. System clock source or system

clock/4 is selected by option.

Using external clock input allows the user to count exter-

nal events, measure time internals or pulse widths, or

generate an accurate time base. While using the inter-

nal clock allows the user to generate an accurate time

base.

In the pulse width measurement mode with the val-

ues of the TON and TE bit equal to one, after the TMR

has received a transient from low to high (or high to

low if the TE bit is ²0²), it will start counting until the

TMR returns to the original level and resets the TON.

The measured result remains in the timer/event

counter even if the activated transient occurs again.

In other words, only one cycle measurement can be

made until the TON is set. The cycle measurement will

re-function as long as it receives further transient pulse.

In this operation mode, the timer/event counter begins

counting according not to the logic level but to the tran-

sient edges. In the case of counter overflows, the counter

is reloaded from the timer/event counter preload register

and issues an interrupt request, as in the other two

modes, i.e., event and timer modes.

There are two registers related to the timer/event coun-

ter, i.e., TMR (0DH) and TMRC (0EH). There are also

two physical registers are mapped to TMR location; writ-

ing TMR places the starting value in the timer/event

counter preload register, while reading it yields the con-

tents of the timer/event counter. TMRC is timer/event

counter control register used to define some options.

The TM0 and TM1 bits define the operation mode. The

event count mode is used to count external events,

which means that the clock source is from an external

(TMR) pin. The timer mode functions as a normal timer

with the clock source coming from the internal selected

clock source. Finally, the pulse width measurement

Bit No.

Label

Function

0~2

¾

Unused bit, read as ²0²

To define the TMR active edge of timer/event counter

(0=active on low to high; 1=active on high to low)

3

4

5

TE

TON

TS

To enable/disable timer counting

(0=disabled; 1=enabled)

2 to 1 multiplexer control inputs to select the timer/event counter clock source

(0=RTC outputs; 1= system clock or system clock/4)

To define the operating mode (TM1, TM0)

01=Event count mode (External clock)

10=Timer mode (Internal clock)

6

7

TM0

TM1

11=Pulse Width measurement mode (External clock)

00=Unused

TMRC (0EH) Register

S

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Timer/Event Counter

Rev. 1.40

14

December 16, 2008

HT49RA0/HT49CA0

Carrier Generator

To enable the counting operation, the Timer ON bit

(TON: bit 4 of TMRC) should be set to 1. In the pulse

width measurement mode, the TON is automatically

cleared after the measurement cycle is completed. But

in the other two modes, the TON can only be reset by in-

structions. The overflow of the timer/event counter is

one of the wake-up sources. No matter what the opera-

tion mode is, writing a 0 to ETI disables the related inter-

rupt service.

The HT49RA0/HT49CA0 provides a carrier output

which shares the pin with PC0. It can be selected to be a

carrier output (REM) or level output pin (PC0) by code

option. If the carrier output option is selected, setting

PC0=²1² to enable carrier output and setting PC0=²0² to

disable it at low level output.

The clock source of the carrier is implemented by in-

struction clock (system clock divided by 4) and pro-

cessed by a frequency divider to yield various carry

frequency.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter is turn on, data written to the

timer/event counter is kept only in the timer/event coun-

ter preload register. The timer/event counter still contin-

ues its operation until an overflow occurs.

Clock Source

Carry Frequency=

m ´2ⁿ

where m=2 or 3 and n=0~3, both are selected by code

option. If m=2, the duty cycle of the carrier output is 1/2

duty. If m=3, the duty cycle of the carrier output can be

1/2 duty or 1/3 duty also determined by code option (with

the exception of n=0).

When the timer/event counter (reading TMR) is read,

the clock is blocked to avoid errors. As this may results

in a counting error, blocking of the clock should be taken

into account by the programmer.

Detailed selection of the carrier duty is shown below:

m´2ⁿ

It is strongly recommended to load a desired value into

the TMR register first, then turn on the related

timer/event counter for proper operation. Because the

initial value of TMR is unknown.

Duty Cycle

2, 4, 8, 16

3

1/2

1/3

Due to the timer/event scheme, the programmer should

pay special attention on the instruction to enable then

disable the timer for the first time, whenever there is a

need to use the timer/event function, to avoid

unpredicatable result. After this procedure, the

timer/event function can be operated normally.

6, 12, 24

1/2 or 1/3

The following table shows examples of carrier fre-

quency selection.

m´2ⁿ

f_SYS

f_CARRIER

37.92kHz

56.9kHz

Duty

1/3 only

1/2 only

3

2

455kHz

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Carrier/Level Output

Rev. 1.40

15

December 16, 2008

HT49RA0/HT49CA0

Input/Output Ports

executed first to disable related NMOS device, and then

²MOV A, [m]² to get stable data.

There are an 8-bit bidirectional input/output port, a 8-bit in-

put port and one-bit input/output port in the

HT49RA0/HT49CA0, labeled as PA, PB and PC which

are mapped to [12H], [14H], [16H] of the RAM respec-

tively. Each bit of PA can be selected as NMOS output or

Schmitt trigger with pull-high resistor by software instruc-

tion. PB0~PB7 can only be used for input operation

(Schmitt trigger with pull-high resistors). PC is only one-bit

input/outputportsharesthepinwithcarrieroutput.

After chip reset, PA, PB and PC remain at a high level in-

put line.

Each bit of PA and PC output latches can be set or

cleared by the ²SET [m].i² and ²CLR [m].i² (m=12H or

16H) instructions respectively.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR [m]²,

²CPL [m]², ²CPLA [m]² read the entire port states into

the CPU, execute the defined operations (bit-operation),

and then write the results back to the latches or to the

accumulator.

When PA, PB and PC for the input operation, these

ports are non-latched, that is, the inputs should be ready

at the T2 rising edge of the instruction ²MOV A, [m]²

(m=12H or 14H). For PA and PC output operation, all

data are latched and remain unchanged until the output

latch is rewritten.

Each line of PB has a wake-up capability to the device

by code option. The highest seven bits of PC are not

physically implemented, on reading them a ²0² is re-

turned and writing results in a no-operation.

When the PA is used for input operation, it should be

noted that before reading data from pads, a ²1² should

be written to the related bits to disable the NMOS de-

vice. That is, the instruction ²SET [m].i² (i=0~7 for PA) is

V

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PA Input/Output Ports

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PB Input Ports

Rev. 1.40

16

December 16, 2008

HT49RA0/HT49CA0

V

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PC Input/Output Ports

LCD Display Memory

LCD Driver Output

The devices provides an area of embedded data mem-

ory for LCD display. This area is located from 40H to

54H of the RAM at Bank 1. Bank pointer (BP; located at

04H of the RAM) is the switch between the RAM and the

LCD display memory. When the BP is set as ²1², any

data written into 40H~54H will effect the LCD display.

When the BP is cleared to ²0², any data written into

40H~54H means to access the general purpose data

memory.

The output number of the LCD driver device can be

21´2, 21´3 or 20´4 by option. The bias type LCD driver

can be ²C² type only. A capacitor mounted between C1

and C2 pins is needed. If 1/2 bias is selected, a capaci-

tor mounted between V2 pin and ground is required. If

1/3 bias is selected, two capacitors are needed for V1

and V2 pins. All the capacitance of capacitors used for

LCD bias generator is suggested to use the 0.1mF. The

relationships between LCD bias types, bias levels and

V1 and V2 connection are listed in the table.

The LCD display memory can be read and written to

only by indirect addressing mode using MP1. When

data is written into the display data area, it is automati-

cally read by the LCD driver which then generates the

corresponding LCD driving signals. To turn the display

on or off, a ²1² or a ²0² is written to the corresponding bit

of the display memory, respectively. The figure illus-

trates the mapping between the display memory and

LCD pattern for the devices.

Bias

Type

C1/C2

V1

V2

VLCD

Level

1/2

1/3

C

x

VLCD

0.1mF

0.1mF 0.1mF 0.1mF

There is a clock source needed for LCD driver. The LCD

clock source comes from the general purpose prescaler

and is decided by code options. The LCD clock fre-

quency should be selected as near to 4kHz either from

32768 RTC or WDT or f_SYS/4 clock source.

C

O

M

4

0

H

4

1

H

4

2

H

4

3

H

5

2

H

5

3

H

5

4

H

B

i

t

0

1

2

3

0

The options of LCD clock frequency are listed in the fol-

lowing table.

1

2

3

f_SClock Source

WDT Oscillator

LCD Clock Selection

WDT/2²

S

E

G

M

E

N

T

0

1

2

3

1

8

1

9

2

0

RTC Oscillator

f_SYS/4

RTC/2³

f_SYS/2⁴~f_SYS/2¹⁰

Display Memory

Rev. 1.40

17

December 16, 2008

HT49RA0/HT49CA0

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"

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" O m i t t h e C O M 2 s i g n a l , i f t h e 1 / 2 d u t y L C D i s u s e d .

V

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V

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D

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x

1

/

2

LCD Driver Output (1/3 Duty, 1/2 Bias, C Type)

Rev. 1.40

18

December 16, 2008

HT49RA0/HT49CA0

V

A

V

B

C

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0

V

C

V

S

A

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1

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5

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1

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2

LCD Driver Output (1/4 Duty, 1/3 Bias, C Type)

Rev. 1.40

19

December 16, 2008

HT49RA0/HT49CA0

Low Voltage Reset/Detector Functions

There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These

two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the RTCC.3 to

enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is

disabled.

The RTCC register definitions are listed below.

Bit No.

0~2

3

Label

Function

RT0~RT2 8 to 1 multiplexer control inputs to select the real clock prescaler output

LVDC*

QOSC

LVD enable/disable (1/0)

32768Hz OSC quick start-up oscillating

0/1: quickly/slowly start

4

LVD detection output (1/0)

5

LVDO

1: low voltage detected, read only

6, 7

¾

Unused bit, read as ²0²

RTCC (09H) Register

Once the LVD function is enabled the reference generator should be enabled; otherwise the reference generator is

controlled by LVR code option. The relationship among LVR and LVD options and LVDC are as shown.

LVDC can read/write, LVDO is read only.

LVD

LVR

LVDC

On

Off

On

Off

X

VREF Generator

Enable

LVR Comparator

Enable

LVD Comparator

Enable

Disable

Enable

Disable

Enable

Disable

Enable

Disable

Enable

Disable

Enable

Disable

Enable

Disable

X

Disable

Rev. 1.40

20

December 16, 2008

HT49RA0/HT49CA0

The microcontroller provides a low voltage reset circuit

in order to monitor the supply voltage of the device. If the

supply voltage of the device is within the range

0.9V~V_LVR, such as might happen when changing a bat-

tery, the LVR will automatically reset the device inter-

nally. During a HALT state, LVR is disabled.

The relationship between V_DDand V_LVRis shown below.

V

D

3

.

6

V

The LVR includes the following specifications:

V

L

V

R

·

The low voltage (0.9V~V_LVR) state must exists for

more than 1ms, while the other circuits remain in their

original state. If the low voltage state does not exceed

1ms, the LVR will ignore it and do not perform a reset

function.

2

.

0

V

0

.

9

V

·

The LVR uses the ²OR² function with the power-on re-

set signal to perform a chip reset.

Note: V_OPRis the voltage range for proper chip

operation at 4MHz system clock.

V

D

3

.

6

V

L

V

R

D

e

t

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c

t

V

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t

a

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e

V

L

V

R

0

.

9

0

V

R

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t

S

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p

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R

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s

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t

*

1

*

2

Low Voltage Reset

Note:

²*1² To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system

clock pulses before entering the normal operation.

²*2² Low voltage state has to be maintained for over 1ms, then after a 1ms delay the device enters the reset

mode.

Rev. 1.40

21

December 16, 2008

HT49RA0/HT49CA0

Options

The following shows the options in the devices. All these options should be defined in order to ensure proper system

functioning.

Item

Options

I/O Options

1

2

3

PB0~PB7: wake-up enable or disable (bit option)

PC0: CMOS output or carrier output (bit option)

PC0: Pull-high enable or disable (bit option)

LCD Options

4

5

6

7

8

LCD clock: f_S/2², f_S/2³, f_S/2⁴, f_S/2⁵, f_S/2⁶, f_S/2⁷, f_S/2⁸

LCD duty: 1/2, 1/3, 1/4

LCD bias: 1/2, 1/3

LCD segment 12~15 output or CMOS output(Nibble Option)

LCD segment 16~19 output or CMOS output(Nibble Option)

Interrupt Options

9

INT0 function: enable or disable

10

11

12

Triggering edge: rising, falling or both

INT1 function: enable or disable

Triggering edge: rising, falling or both

Oscillator Options

13 _Sinternal clock source: RTC oscillator, WDT oscillator or f_SYS/4

Timer Options

f

14

Timer/Event Counter clock source: f_SYSor f_SYS/4

Time Base Options

15

Time Base division ratio: f_S/2¹², f_S/2¹³, f_S/2¹⁴, f_S/2¹⁵

Watchdog Options

16

17

WDT enable or disable

CLRWDT instructions: 1 or 2 instructions

LVD/LVR Options

18

19

Low Voltage Detect: enable or disable

LVR function: enable or disable

Carrier Options

20

21

22

23

Carrier duty: 1/2 duty or 1/3 duty

Carrier frequency: f_SYS/8, f_SYS/16, f_SYS/32, f_SYS/64 for 1/2 duty cycle

Carrier frequency: f_SYS/12, 1/3 duty cycle

Carrier frequency: f_SYS/24, f_SYS/48, f_SYS/96 for 1/2 duty or 1/3 duty cycle

Rev. 1.40

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HT49RA0/HT49CA0

Application Circuits

V

D

V

D

R

e

s

e

t

1

0

k

C

i

r

c

u

i

t

m

0 . 1 F

R

E

S

P

A

0

~

P

A

7

m

0 . 1 F

P

B

0

/

I

N

T

0

P

B

1

/

I

N

T

1

V

S

P

B

2

/

T

M

R

P

B

3

~

P

B

7

O

S

C

O

S

C

1

P

C

0

/

R

E

M

C

i

r

c

u

i

t

V

D

O

S

C

3

4

7

0

p

F

R

C

S

y

s

t

e

m

O

s

c

i

l

a

t

o

r

O

S

C

1

R

O

S

C

R

O

S

C

O

S

C

4

H

T

4

9

R

A

0

/

H

T

4

9

C

A

0

O

S

C

i

r

c

u

i

t

Note: 1. Reset circuit

The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and re-

mains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of

the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.

2. For applications where noise may interfere with the reset circuit and for details on the oscillator external

components, refer to Application Note HA0075E for more information.

Rev. 1.40

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December 16, 2008

HT49RA0/HT49CA0

Example

P

A

B

2

3

4

5

7

6

5

4

P

A

B

1

0

3

2

1

0

V

D

V

D

R

e

s

e

t

1

0

k

C

i

r

c

u

i

t

V

L

C

D

L

C

D

P

o

w

e

r

S

u

p

l

y

0

m

. 1 F

R

E

S

m

0 . 1 F

C

O

M

0

~

C

O

M

2

9

L

C

D

C

O

M

3

/

S

E

G

2

0

P

A

N

E

L

S

E

G

0

~

S

E

G

1

V

S

3

W

C

1

2

V

D

m

0 . 1 F

1

m

0 0 F

1

W

V

b

a

t

V

1

2

W

m

0 . 1 F

P

C

0

/

R

E

M

V

2

m

0 . 1 F

O

S

C

O

S

C

1

C

i

r

c

u

i

t

H

T

4

9

R

A

0

/

H

T

4

9

C

A

0

Rev. 1.40

24

December 16, 2008

HT49RA0/HT49CA0

Instruction Set

Introduction

subtract instruction mnemonics to enable the necessary

arithmetic to be carried out. Care must be taken to en-

sure correct handling of carry and borrow data when re-

sults exceed 255 for addition and less than 0 for

subtraction. The increment and decrement instructions

INC, INCA, DEC and DECA provide a simple means of

increasing or decreasing by a value of one of the values

in the destination specified.

Central to the successful operation of any

microcontroller is its instruction set, which is a set of pro-

gram instruction codes that directs the microcontroller to

perform certain operations. In the case of Holtek

microcontrollers, a comprehensive and flexible set of

over 60 instructions is provided to enable programmers

to implement their application with the minimum of pro-

gramming overheads.

Logical and Rotate Operations

For easier understanding of the various instruction

codes, they have been subdivided into several func-

tional groupings.

The standard logical operations such as AND, OR, XOR

and CPL all have their own instruction within the Holtek

microcontroller instruction set. As with the case of most

instructions involving data manipulation, data must pass

through the Accumulator which may involve additional

programming steps. In all logical data operations, the

zero flag may be set if the result of the operation is zero.

Another form of logical data manipulation comes from

the rotate instructions such as RR, RL, RRC and RLC

which provide a simple means of rotating one bit right or

left. Different rotate instructions exist depending on pro-

gram requirements. Rotate instructions are useful for

serial port programming applications where data can be

rotated from an internal register into the Carry bit from

where it can be examined and the necessary serial bit

set high or low. Another application where rotate data

operations are used is to implement multiplication and

division calculations.

Instruction Timing

Most instructions are implemented within one instruc-

tion cycle. The exceptions to this are branch, call, or ta-

ble read instructions where two instruction cycles are

required. One instruction cycle is equal to 4 system

clock cycles, therefore in the case of an 8MHz system

oscillator, most instructions would be implemented

within 0.5ms and branch or call instructions would be im-

plemented within 1ms. Although instructions which re-

quire one more cycle to implement are generally limited

to the JMP, CALL, RET, RETI and table read instruc-

tions, it is important to realize that any other instructions

which involve manipulation of the Program Counter Low

register or PCL will also take one more cycle to imple-

ment. As instructions which change the contents of the

PCL will imply a direct jump to that new address, one

more cycle will be required. Examples of such instruc-

tions would be ²CLR PCL² or ²MOV PCL, A². For the

case of skip instructions, it must be noted that if the re-

sult of the comparison involves a skip operation then

this will also take one more cycle, if no skip is involved

then only one cycle is required.

Branches and Control Transfer

Program branching takes the form of either jumps to

specified locations using the JMP instruction or to a sub-

routine using the CALL instruction. They differ in the

sense that in the case of a subroutine call, the program

must return to the instruction immediately when the sub-

routine has been carried out. This is done by placing a

return instruction RET in the subroutine which will cause

the program to jump back to the address right after the

CALL instruction. In the case of a JMP instruction, the

program simply jumps to the desired location. There is

no requirement to jump back to the original jumping off

point as in the case of the CALL instruction. One special

and extremely useful set of branch instructions are the

conditional branches. Here a decision is first made re-

garding the condition of a certain data memory or indi-

vidual bits. Depending upon the conditions, the program

will continue with the next instruction or skip over it and

jump to the following instruction. These instructions are

the key to decision making and branching within the pro-

gram perhaps determined by the condition of certain in-

put switches or by the condition of internal data bits.

Moving and Transferring Data

The transfer of data within the microcontroller program

is one of the most frequently used operations. Making

use of three kinds of MOV instructions, data can be

transferred from registers to the Accumulator and

vice-versa as well as being able to move specific imme-

diate data directly into the Accumulator. One of the most

important data transfer applications is to receive data

from the input ports and transfer data to the output ports.

Arithmetic Operations

The ability to perform certain arithmetic operations and

data manipulation is a necessary feature of most

microcontroller applications. Within the Holtek

microcontroller instruction set are a range of add and

Rev. 1.40

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HT49RA0/HT49CA0

Bit Operations

Other Operations

The ability to provide single bit operations on Data Mem-

ory is an extremely flexible feature of all Holtek

microcontrollers. This feature is especially useful for

output port bit programming where individual bits or port

pins can be directly set high or low using either the ²SET

[m].i² or ²CLR [m].i² instructions respectively. The fea-

ture removes the need for programmers to first read the

8-bit output port, manipulate the input data to ensure

that other bits are not changed and then output the port

with the correct new data. This read-modify-write pro-

cess is taken care of automatically when these bit oper-

ation instructions are used.

In addition to the above functional instructions, a range

of other instructions also exist such as the ²HALT² in-

struction for Power-down operations and instructions to

control the operation of the Watchdog Timer for reliable

program operations under extreme electric or electro-

magnetic environments. For their relevant operations,

refer to the functional related sections.

Instruction Set Summary

The following table depicts a summary of the instruction

set categorised according to function and can be con-

sulted as a basic instruction reference using the follow-

ing listed conventions.

Table Read Operations

Table conventions:

Data storage is normally implemented by using regis-

ters. However, when working with large amounts of

fixed data, the volume involved often makes it inconve-

nient to store the fixed data in the Data Memory. To over-

come this problem, Holtek microcontrollers allow an

area of Program Memory to be setup as a table where

data can be directly stored. A set of easy to use instruc-

tions provides the means by which this fixed data can be

referenced and retrieved from the Program Memory.

x: Bits immediate data

m: Data Memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Mnemonic

Arithmetic

Description

Cycles Flag Affected

ADD A,[m]

ADDM A,[m]

ADD A,x

Add Data Memory to ACC

1

1^Note

1

Z, C, AC, OV

C

Add ACC to Data Memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add Data Memory to ACC with Carry

1

1^Note

Add ACC to Data memory with Carry

Subtract immediate data from the ACC

Subtract Data Memory from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

1

1^Note

Subtract Data Memory from ACC with result in Data Memory

Subtract Data Memory from ACC with Carry

Subtract Data Memory from ACC with Carry, result in Data Memory

Decimal adjust ACC for Addition with result in Data Memory

1

1^Note

Logic Operation

AND A,[m]

OR A,[m]

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

Logical AND Data Memory to ACC

Logical OR Data Memory to ACC

Logical XOR Data Memory to ACC

Logical AND ACC to Data Memory

Logical OR ACC to Data Memory

Logical XOR ACC to Data Memory

Logical AND immediate Data to ACC

Logical OR immediate Data to ACC

Logical XOR immediate Data to ACC

Complement Data Memory

1

Z

1

1^Note

1

OR A,x

1

XOR A,x

1

1^Note

CPL [m]

CPLA [m]

Complement Data Memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment Data Memory with result in ACC

1

Z

Increment Data Memory

1^Note

DECA [m]

DEC [m]

Decrement Data Memory with result in ACC

Decrement Data Memory

1

1^Note

Rev. 1.40

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December 16, 2008

HT49RA0/HT49CA0

Mnemonic

Rotate

Description

Cycles Flag Affected

RRA [m]

RR [m]

Rotate Data Memory right with result in ACC

Rotate Data Memory right

1

1^Note

1

1^Note

1

1^Note

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate Data Memory right through Carry with result in ACC

Rotate Data Memory right through Carry

Rotate Data Memory left with result in ACC

Rotate Data Memory left

C

None

C

RLCA [m]

RLC [m]

Rotate Data Memory left through Carry with result in ACC

Rotate Data Memory left through Carry

1

1^Note

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move Data Memory to ACC

Move ACC to Data Memory

Move immediate data to ACC

1

1^Note

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of Data Memory

Set bit of Data Memory

1^Note

None

Branch

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if Data Memory is zero

1^Note

1^note

1^Note

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if Data Memory is zero with data movement to ACC

Skip if bit i of Data Memory is zero

Skip if bit i of Data Memory is not zero

Skip if increment Data Memory is zero

Skip if decrement Data Memory is zero

Skip if increment Data Memory is zero with result in ACC

Skip if decrement Data Memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC [m]

TABRDL [m]

Read table (current page) to TBLH and Data Memory

Read table (last page) to TBLH and Data Memory

2^Note

None

Miscellaneous

NOP

No operation

1

1^Note

1

None

CLR [m]

Clear Data Memory

SET [m]

Set Data Memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO, PDF

None

Pre-clear Watchdog Timer

Swap nibbles of Data Memory

Swap nibbles of Data Memory with result in ACC

Enter power down mode

1

1^Note

1

None

1

TO, PDF

Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,

if no skip takes place only one cycle is required.

2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.

3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by

the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and

²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags

remain unchanged.

Rev. 1.40

27

December 16, 2008

HT49RA0/HT49CA0

Instruction Definition

ADC A,[m]

Add Data Memory to ACC with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the Accumulator.

Operation

ACC ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADCM A,[m]

Add ACC to Data Memory with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADD A,[m]

Add Data Memory to ACC

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

ADD A,x

Add immediate data to ACC

Description

The contents of the Accumulator and the specified immediate data are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + x

Affected flag(s)

OV, Z, AC, C

ADDM A,[m]

Add ACC to Data Memory

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

AND A,[m]

Logical AND Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

Z

AND A,x

Logical AND immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical AND

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

Z

ANDM A,[m]

Logical AND ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

Z

Rev. 1.40

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HT49RA0/HT49CA0

CALL addr

Subroutine call

Description

Unconditionally calls a subroutine at the specified address. The Program Counter then in-

crements by 1 to obtain the address of the next instruction which is then pushed onto the

stack. The specified address is then loaded and the program continues execution from this

new address. As this instruction requires an additional operation, it is a two cycle instruc-

tion.

Operation

Stack ¬ Program Counter + 1

Program Counter ¬ addr

Affected flag(s)

None

CLR [m]

Clear Data Memory

Description

Operation

Each bit of the specified Data Memory is cleared to 0.

[m] ¬ 00H

Affected flag(s)

None

CLR [m].i

Clear bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

None

CLR WDT

Description

Operation

Clear Watchdog Timer

The TO, PDF flags and the WDT are all cleared.

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT1

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT2 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT2

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT1 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

Rev. 1.40

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December 16, 2008

HT49RA0/HT49CA0

CPL [m]

Complement Data Memory

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa.

Operation

[m] ¬ [m]

Affected flag(s)

Z

CPLA [m]

Complement Data Memory with result in ACC

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa. The complemented result

is stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

Z

DAA [m]

Decimal-Adjust ACC for addition with result in Data Memory

Description

Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-

sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or

if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble

remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of

6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-

ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C

flag may be affected by this instruction which indicates that if the original BCD sum is

greater than 100, it allows multiple precision decimal addition.

Operation

[m] ¬ ACC + 00H or

[m] ¬ ACC + 06H or

[m] ¬ ACC + 60H or

[m] ¬ ACC + 66H

Affected flag(s)

C

DEC [m]

Decrement Data Memory

Description

Operation

Data in the specified Data Memory is decremented by 1.

[m] ¬ [m] - 1

Affected flag(s)

Z

DECA [m]

Decrement Data Memory with result in ACC

Description

Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-

mulator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] - 1

Affected flag(s)

Z

HALT

Enter power down mode

Description

This instruction stops the program execution and turns off the system clock. The contents

of the Data Memory and registers are retained. The WDT and prescaler are cleared. The

power down flag PDF is set and the WDT time-out flag TO is cleared.

Operation

TO ¬ 0

PDF ¬ 1

Affected flag(s)

TO, PDF

Rev. 1.40

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HT49RA0/HT49CA0

INC [m]

Increment Data Memory

Description

Operation

Data in the specified Data Memory is incremented by 1.

[m] ¬ [m] + 1

Affected flag(s)

Z

INCA [m]

Increment Data Memory with result in ACC

Description

Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-

lator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] + 1

Affected flag(s)

Z

JMP addr

Jump unconditionally

Description

The contents of the Program Counter are replaced with the specified address. Program

execution then continues from this new address. As this requires the insertion of a dummy

instruction while the new address is loaded, it is a two cycle instruction.

Operation

Program Counter ¬ addr

Affected flag(s)

None

MOV A,[m]

Description

Operation

Move Data Memory to ACC

The contents of the specified Data Memory are copied to the Accumulator.

ACC ¬ [m]

Affected flag(s)

None

MOV A,x

Move immediate data to ACC

Description

Operation

The immediate data specified is loaded into the Accumulator.

ACC ¬ x

Affected flag(s)

None

MOV [m],A

Description

Operation

Move ACC to Data Memory

The contents of the Accumulator are copied to the specified Data Memory.

[m] ¬ ACC

Affected flag(s)

None

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

No operation

None

OR A,[m]

Logical OR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-

ation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

Z

Rev. 1.40

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HT49RA0/HT49CA0

OR A,x

Logical OR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

Z

ORM A,[m]

Logical OR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-

ation. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²OR² [m]

Affected flag(s)

Z

RET

Return from subroutine

Description

The Program Counter is restored from the stack. Program execution continues at the re-

stored address.

Operation

Program Counter ¬ Stack

Affected flag(s)

None

RET A,x

Return from subroutine and load immediate data to ACC

Description

The Program Counter is restored from the stack and the Accumulator loaded with the

specified immediate data. Program execution continues at the restored address.

Operation

Program Counter ¬ Stack

ACC ¬ x

Affected flag(s)

None

RETI

Return from interrupt

Description

The Program Counter is restored from the stack and the interrupts are re-enabled by set-

ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending

when the RETI instruction is executed, the pending Interrupt routine will be processed be-

fore returning to the main program.

Operation

Program Counter ¬ Stack

EMI ¬ 1

Affected flag(s)

None

RL [m]

Rotate Data Memory left

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ [m].7

Affected flag(s)

None

RLA [m]

Rotate Data Memory left with result in ACC

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-

main unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ [m].7

Affected flag(s)

None

Rev. 1.40

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HT49RA0/HT49CA0

RLC [m]

Rotate Data Memory left through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7

replaces the Carry bit and the original carry flag is rotated into bit 0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RLCA [m]

Rotate Data Memory left through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces

the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in

the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RR [m]

Rotate Data Memory right

Description

The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into

bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ [m].0

Affected flag(s)

None

RRA [m]

Rotate Data Memory right with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-

tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data

Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ [m].0

Affected flag(s)

None

RRC [m]

Rotate Data Memory right through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0

replaces the Carry bit and the original carry flag is rotated into bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

C

RRCA [m]

Rotate Data Memory right through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-

places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is

stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

C

Rev. 1.40

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December 16, 2008

HT49RA0/HT49CA0

SBC A,[m]

Subtract Data Memory from ACC with Carry

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result

of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or

zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SBCM A,[m]

Subtract Data Memory from ACC with Carry and result in Data Memory

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-

sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is

positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SDZ [m]

Skip if decrement Data Memory is 0

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0 the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] - 1

Skip if [m] = 0

Affected flag(s)

None

SDZA [m]

Skip if decrement Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0, the program proceeds with the following instruction.

Operation

ACC ¬ [m] - 1

Skip if ACC = 0

Affected flag(s)

None

SET [m]

Set Data Memory

Description

Operation

Each bit of the specified Data Memory is set to 1.

[m] ¬ FFH

Affected flag(s)

None

SET [m].i

Set bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is set to 1.

[m].i ¬ 1

Affected flag(s)

None

Rev. 1.40

34

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HT49RA0/HT49CA0

SIZ [m]

Skip if increment Data Memory is 0

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] + 1

Skip if [m] = 0

Affected flag(s)

None

SIZA [m]

Skip if increment Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0 the program proceeds with the following instruction.

Operation

ACC ¬ [m] + 1

Skip if ACC = 0

Affected flag(s)

None

SNZ [m].i

Skip if bit i of Data Memory is not 0

Description

If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is 0 the program proceeds with the following instruction.

Operation

Skip if [m].i ¹ 0

Affected flag(s)

None

SUB A,[m]

Subtract Data Memory from ACC

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUBM A,[m]

Subtract Data Memory from ACC with result in Data Memory

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUB A,x

Subtract immediate data from ACC

Description

The immediate data specified by the code is subtracted from the contents of the Accumu-

lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-

tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will

be set to 1.

Operation

ACC ¬ ACC - x

Affected flag(s)

OV, Z, AC, C

Rev. 1.40

35

December 16, 2008

HT49RA0/HT49CA0

SWAP [m]

Description

Operation

Swap nibbles of Data Memory

The low-order and high-order nibbles of the specified Data Memory are interchanged.

[m].3~[m].0 « [m].7 ~ [m].4

Affected flag(s)

None

SWAPA [m]

Swap nibbles of Data Memory with result in ACC

Description

The low-order and high-order nibbles of the specified Data Memory are interchanged. The

result is stored in the Accumulator. The contents of the Data Memory remain unchanged.

Operation

ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4

ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0

Affected flag(s)

None

SZ [m]

Skip if Data Memory is 0

Description

If the contents of the specified Data Memory is 0, the following instruction is skipped. As

this requires the insertion of a dummy instruction while the next instruction is fetched, it is a

two cycle instruction. If the result is not 0 the program proceeds with the following instruc-

tion.

Operation

Skip if [m] = 0

None

Affected flag(s)

SZA [m]

Skip if Data Memory is 0 with data movement to ACC

Description

The contents of the specified Data Memory are copied to the Accumulator. If the value is

zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-

tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the

program proceeds with the following instruction.

Operation

ACC ¬ [m]

Skip if [m] = 0

Affected flag(s)

None

SZ [m].i

Skip if bit i of Data Memory is 0

Description

If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is not 0, the program proceeds with the following instruction.

Operation

Skip if [m].i = 0

None

Affected flag(s)

TABRDC [m]

Read table (current page) to TBLH and Data Memory

Description

The low byte of the program code (current page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

TABRDL [m]

Read table (last page) to TBLH and Data Memory

Description

The low byte of the program code (last page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

Rev. 1.40

36

December 16, 2008

HT49RA0/HT49CA0

XOR A,[m]

Logical XOR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XORM A,[m]

Logical XOR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XOR A,x

Logical XOR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical XOR

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

Z

Rev. 1.40

37

December 16, 2008

HT49RA0/HT49CA0

Package Information

52-pin QFP (14mm´14mm) Outline Dimensions

C

H

D

G

3

9

2

7

I

4

0

2

6

F

A

B

E

1

4

5

2

K

J

1

3

Dimensions in mm

Symbol

Min.

17.3

13.9

17.3

13.9

¾

Nom.

¾

Max.

17.5

14.1

17.5

14.1

¾

A

B

C

D

E

F

G

H

I

¾

1

0.4

¾

2.5

¾

3.1

¾

0.1

¾

3.4

¾

J

0.73

0.1

0°

1.03

0.2

K

a

7°

Rev. 1.40

38

December 16, 2008

HT49RA0/HT49CA0

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103

Tel: 86-21-5422-4590

Fax: 86-21-5422-4705

http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5F, Unit A, Productivity Building, Gaoxin M 2nd, Middle Zone Of High-Tech Industrial Park, ShenZhen, China 518057

Tel: 86-755-8616-9908, 86-755-8616-9308

Fax: 86-755-8616-9722

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031

Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752

Fax: 86-10-6641-0125

Holtek Semiconductor Inc. (Chengdu Sales Office)

709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016

Tel: 86-28-6653-6590

Fax: 86-28-6653-6591

Holtek Semiconductor (USA), Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538

Tel: 1-510-252-9880

Fax: 1-510-252-9885

http://www.holtek.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 1.40

39

December 16, 2008


型号：	HT49RA0(52QFP-A)
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	Microcontroller, 8-Bit, UVPROM, CMOS, PQFP52, 可编程只读存储器微控制器
文件：	总39页 (文件大小：290K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT49RA0(52QFP-A) [HOLTEK]

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