HT6230 [HOLTEK]
Infrared Remote Encoder; 红外遥控编码器
| 型号： | HT6230 |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Infrared Remote Encoder |
| 文件： | 总8页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT6230
Infrared Remote Encoder
Features
·
·
Operating voltage: 2.4V~5.2V
32 system codes, each system with
64 command codes
(1/2 system frequency and 1/4 duty cycle)
Single pin oscillator
·
·
·
·
429kHz resonator system clock
Test pins available
28-pin SOP package
·
·
·
Programmable transmission codes
Biphase transmission method
Generated modulation output data
Applications
·
Televisions and video cassette recorder
controllers
Garage door controllers
·
·
·
Car door controllers
Security systems
Other remote control systems
·
General Description
The HT6230 is designed as infrared remote en-
coder, usually applied to TV systems. A total of
2048 different commands can be generated and
arranged into 32 systems where each system
contains 64 different commands. There are 96
keys and to each key is assigned one program-
mable code. The code is programmable by mask
option. Legal and illegal key operation can be
distinguished.
Block Diagram
P
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1
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2
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Z
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3
0
Z
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X
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0
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L
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P
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V
S
V
S
D
D
1
April 19, 2000
HT6230
Pin Assignment
Pad Assignment
X
I
N
1
2
3
4
5
6
7
8
9
1
1
1
1
1
7
2
2
2
2
2
2
2
2
2
1
1
1
1
1
8
7
6
5
4
3
2
1
0
9
8
7
6
5
V
X
X
X
X
X
X
X
T
T
O
D
D
D
D
I
I
I
I
I
I
I
D
M
S
N
N
N
N
N
N
N
6
5
4
3
2
1
0
1
2
8
2
7
2
2
1
2
6
2
5
2
4
2
3
2
Z
Z
Z
Z
I
I
I
I
N
N
N
N
0
1
2
3
2
1
0
9
X
X
I
I
N
N
2
1
Z
Z
I
I
N
N
2
3
2
3
M
C
O
D
E
C
O
D
E
1
8
X
T
T
I
N
0
D
D
D
D
D
R
R
R
R
R
S
S
S
S
S
7
6
5
4
3
T
T
1
2
4
5
M
C
O
D
E
1
1
7
6
T
T
1
2
(
0
,
0
)
0
1
2
3
4
S
C
C
O
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E
R
R
R
S
S
S
0
1
2
V
S
S
6
7
D
D
R
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S
7
6
H
T
6
2
3
0
2
8
S
O
P
D
R
S
5
8
9
1
0
1
1
1
2
1
3
1
4
5
1
Chip size: 1605 ´ 1910 (mm)2
* The IC substrate should be connected to VDD in the
layout artwork.
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
2
817.68
442.16
300.74
120.29
15
16
17
18
19
20
21
22
23
24
25
26
27
28
605.12
653.07
653.07
653.07
653.07
653.07
561.23
419.80
278.37
136.94
-4.48
-570.19
-662.85
-662.85
-662.85
-662.85
-662.85
-662.85
-644.16
-429.58
-288.15
-98.77
-817.68
-75.59
65.84
3
4
207.26
437.29
578.71
817.68
817.68
817.68
817.68
817.68
817.68
817.68
817.68
5
-147.93
-395.02
-536.45
-817.68
-817.68
-817.68
-817.68
-817.68
-817.68
-817.68
6
7
8
9
10
11
12
13
14
107.68
-145.91
-287.34
-428.76
249.11
463.69
2
April 19, 2000
HT6230
Pad Description
Internal
Connection
Pad No.
Pad Name I/O
Description
1~3
28
ZIN1~ZIN3
ZIN0
CMOS with
PMOS Pull-high
I
Detect inputs from Z-key matrix
Tri-state
CMOS
Generate modulation output data code with
1/12 system frequency and 1/4 duty cycle
4
5
MCODE
CODE
O
O
Tri-state
CMOS
Generates output data code
Open Drain
NMOS
6~10
11
DRS7~DRS3
VSS
O
¾
O
I
Drive for key scanning
Negative power supply, ground
Drive for key scanning
Oscillator input
¾
Open Drain
NMOS
12~14
15
DRS2~DRS0
OSC
CMOS
Switch to four operating modes:
0 0 normal mode
0 1 test mode 1
16~17
TT2~TT1
I
CMOS
1 0 test mode 2
1 1 Reset
CMOS with
PMOS Pull-high
18~24
25
XIN0~XIN6
VDD
I
¾
I
Detect inputs from X-key matrix
Positive power supply
¾
CMOS with
PMOS Pull-high
26
XIN7
Detect input from X-key matrix
Select system mode (Two modes provided:
One-key system mode and Two-key system
mode)
27
MS
I
CMOS
Approximate internal connection circuits
·
Input terminal
P
i
n
:
X
I
N
0
~
X
I
N
7
,
Z
I
N
0
~
Z
I
N
3
P
i
n
:
M
S
,
T
T
1
,
T
T
2
,
O
S
C
(
w
i
t
h
p
u
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l
-
h
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h
r
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s
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)
V
D
D
V
D
D
V
D
D
3
April 19, 2000
HT6230
·
Output terminal
P
i
n
:
D
R
S
0
~
D
R
P
S
i
7
n
:
C
O
D
E
,
M
C
O
D
E
V
D
D
E
N
B
D
A
T
A
I
N
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V
Input Voltage.................VSS-0.3V to VDD+0.3V
Storage Temperature.................-50°C to 125°C
Operating Temperature ..............-25°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-
mum Ratings² may cause substantial damage to the device. Functional operation of this de-
vice at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
Electrical Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ. Max. Unit
VDD
Conditions
VDD
Supply Voltage
2.4
5.2
0.3
V
V
¾
¾
¾
¾
DRS0~DRS7 Output
Voltage Low
VOL1
IOL1=0.3mA
3V
¾
CODE, MCODE Output
Voltage Low
VOL2
VOH
RPH
IOL2=0.6mA
3V
3V
3V
0.3
¾
¾
¾
V
V
¾
¾
¾
27
CODE, MCODE Output
Voltage High
IOH=-0.4mA
V
DD-0.3
XIN0~XIN7 and
ZIN0~ZIN3 Pull-high
TT1=TT2=MS=Low
VI=0V
¾
¾
30
kW
kHz
Oscillator Frequency
Operational
429
50
¾
¾
fOSC
3V
Free-running
100 kHz
4
April 19, 2000
HT6230
Functional Description
cent state both CODE and MCODE are high
impedance.
Key operation
When MS is low, the legal key operation is that
only one ZIN or XIN can be connected to one
DRS driver and if more than one XIN, ZIN or
both are pressed at the same time then the key
operation is recognized as illegal; hence, the os-
cillator will not start. When MS is high, the le-
gal key operation is that exactly one ZIN and
one XIN are connected to two DRS drivers and
other cases of key operation are all considered
as illegal.
Key scan drivers
The key scan drivers DRS0 to DRS7 are open
drain NMOS and the outputs of these are all
low in quiescent state. When a legal key opera-
tion is detected, the debounce cycle starts and
at the end of the debounce cycle, the DRS out-
puts are high impedance. Furthermore, the
scanning cycle starts and DRS outputs take
turns to switch to low state.
However, when one XIN or ZIN is connected to
more than one DRS, the last key scan driver is
to generate output data code.
Programmable output data code
The output data code corresponding to each key
is programmable by hardware mask option.
The PAL circuit is necessary for this purpose.
Format of transmission code
The output pin CODE transmits the data code
as a code format, as shown at the bottom figure.
Operation mode
The method of transmitting one code bit is called
biphase transmission and is represented by the
following fig:
·
One-key system mode
The device enters this mode by switching the
MS input pin to low state. The pull-high resis-
tors are connected to all XIN and ZIN inputs
so that all sense inputs are at high state, until
pulled to low state by key operation. In this
mode the legal key operation is that only one
ZIN or XIN can be connected to one DRS.
When a sense input detects a low level, an en-
able signal is generated to latch the system or
command latches. If the sense input belongs
to ZIN, the corresponding system code is gen-
erated and the command code is defined as all
l
o
g
i
c
0
l
o
g
i
c
1
Where one code bit time is 3´28´TOSC. The out-
put signal of the MCODE pin is the signal of the
generated output code modulated by 1/12 of the
system frequency with 1/4 duty cycle. In quies-
o
n
e
c
o
d
e
1
1
L
S
M
B
S
B
L
S
B
M
S
B
D
e
b
o
c
u
y
n
c
c
l
e
S
c
e
c
a
n
S
t
a
r
t
5
s
y
s
t
e
m
b
i
t
s
6
c
o
m
m
a
n
d
b
i
t
s
(
1
6
b
i
t
-
t
y
i
c
m
l
e
e
b
)
i
t
s
C
o
n
t
r
o
l
s
t
a
r
t
b
i
t
C
o
d
e
1
C
o
d
e
2
1
6
b
i
t
-
t
i
m
e
4
8
b
i
t
-
t
i
m
e
1
6
b
i
t
-
t
i
m
e
s
t
a
r
t
R
e
p
e
t
i
t
i
o
n
t
i
m
e
(
6
4
b
i
t
-
t
i
m
e
)
Transmission code format
5
April 19, 2000
HT6230
·
·
logic 1. If the sense input comes from XIN, the
corresponding command code together with
the system code stored in the system latches
are generated.
During Tsep and debounce time, the device
will reset immediately if a key is released.
During Scan cycle in Tcode, a reset will occur
if a key is released in three cases described be-
low:
·
Two-key system mode
¨
The device goes into this mode by switching
the MS input pin to high state. The pull-high
resistors are only connected to XIN inputs ex-
cept the first scan cycle. In the first scan cycle,
there only exists pull-high resistors in ZIN in-
puts. In this mode, the legal key operation is
that exactly one XIN and one ZIN are con-
nected to two DRS drivers. In the first scan
duration, it detects which key in Z-key matrix
is pressed and generates an enable signal to
latch the system latches. While in the second
scan duration, it detects which key in the
X-key matrix is pressed and generates an en-
abled signal to latch the command latches. Af-
ter being latched, the system and command
codes are transmitted.
When one of the key scan drivers is in the
low state
¨
Before that key has been detected
¨
When MS is high and there is no wired con-
nection in Z-key matrix
Test pins (TT1 and TT2)
There are four modes by the combination of TT1
and TT2.
TT1 TT2
Mode
Normal mode
0
1
1
0
0
1
0
1
Reset
Test mode 1
Test mode 2
Control bit
A control bit is added after two start bits and
will be complemented if one key is released. The
decoder can decide whether the next code is a
new command or not.
Oscillator
The embedded part of the oscillator is an
RC-oscillation circuit. The OSC pin is the input
terminal of the RC-oscillation circuit and is con-
nected to an external ceramic resonator (429kHz).
A resistor of 6.8kW must be in series with the
resonator. The resonator and resistor are
grounded at one side.
Reset (after key release)
In a complete code repetition time, as shown in
the figure below, the following situation of key
release results in a reset action.
D
e
b
o
u
n
c
e
C
o
d
e
1
C
o
d
e
2
t
i
m
e
T
c
o
d
e
T
s
e
p
T
c
o
d
e
R
e
p
e
t
i
t
i
o
n
t
i
m
e
6
April 19, 2000
HT6230
Application Circuits
V
D
D
1
2
3
4
5
6
7
8
9
2
8
X
M
Z
Z
Z
Z
M
C
D
D
D
D
D
V
I
N
7
V
D
D
2
2
2
2
2
2
2
2
1
1
1
1
1
7
6
5
4
3
2
1
0
9
8
7
6
5
X
X
X
X
X
X
X
I
I
I
I
I
I
I
N
N
N
N
N
N
N
6
5
4
3
2
1
0
S
V
D
D
I
I
I
I
N
N
N
N
0
1
2
3
I
n
f
r
a
-
R
e
d
4
W
7
C
O
D
E
1
W
k
O
D
E
T
T
T
T
1
2
R
R
R
R
R
S
S
S
S
S
7
6
5
4
3
1
1
1
1
1
0
1
2
3
4
O
S
C
D
D
D
R
R
R
S
S
S
0
1
2
S
S
R
e
s
o
n
a
t
o
r
(
4
2
9
k
H
z
)
H
T
6
2
3
0
2
8
S
O
P
6 .
W
8
k
w
h
e
r
e
p
u
s
h
-
b
u
t
t
o
n
s
w
i
t
c
h
7
April 19, 2000
HT6230
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres-
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
8
April 19, 2000
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