HT66F70A [HOLTEK]
Enhanced A/D Flash Type 8-Bit MCU with EEPROM; 增强A / D型闪存的8位微控制器与EEPROM
| 型号： | HT66F70A |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Enhanced A/D Flash Type 8-Bit MCU with EEPROM |
| 文件： | 总237页 (文件大小：8743K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
HT66F60A
HT66F70A
Revision: V1.00 Date: �aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Table of Contents
Features............................................................................................................ 7
CPU Featuꢀes ........................................................................................................................ 7
Peꢀipꢂeꢀal Featuꢀes ................................................................................................................ 7
General Description......................................................................................... 8
Selection Table................................................................................................. 8
Block Diagram.................................................................................................. 9
Pin Assignment.............................................................................................. 10
Pin Description .............................................................................................. 12
Absolute Maximum Ratings.......................................................................... 18
D.C. Characteristics....................................................................................... 18
A.C. Characteristics....................................................................................... 21
A/D Converter Characteristics...................................................................... 22
LVD & LVR Electrical Characteristics .......................................................... 22
Comparator Electrical Characteristics ........................................................ 23
Power on Reset Electrical Characteristics ................................................. 23
System Architecture...................................................................................... 24
Cloꢁking and Pipelining......................................................................................................... ꢃ4
Pꢀogꢀam Counteꢀ................................................................................................................... ꢃ5
Staꢁk ..................................................................................................................................... ꢃ6
Aꢀitꢂmetiꢁ and Logiꢁ Unit – ALU ........................................................................................... ꢃ6
Flash Program Memory................................................................................. 27
Stꢀuꢁtuꢀe................................................................................................................................ ꢃ7
Speꢁial Veꢁtoꢀs ..................................................................................................................... ꢃ8
Look-up Table........................................................................................................................ ꢃ8
Table Pꢀogꢀam Example........................................................................................................ ꢃ9
In Ciꢀꢁuit Pꢀogꢀamming – ICP ............................................................................................... ꢅ0
On-Cꢂip Debug Suppoꢀt – OCDS ......................................................................................... ꢅ1
In Appliꢁation Pꢀogꢀamming – IAP ........................................................................................ ꢅ1
Data Memory .................................................................................................. 39
Stꢀuꢁtuꢀe................................................................................................................................ ꢅ9
Geneꢀal Puꢀpose Data �emoꢀy ............................................................................................ 40
Speꢁial Puꢀpose Data �emoꢀy ............................................................................................. 40
Special Function Register Description........................................................ 42
Indiꢀeꢁt Addꢀessing Registeꢀs – IAR0ꢄ IAR1 ......................................................................... 4ꢃ
�emoꢀy Pointeꢀs – �P0ꢄ �P1 .............................................................................................. 4ꢃ
Bank Pointeꢀ – BP................................................................................................................. 4ꢅ
Aꢁꢁumulatoꢀ – ACC............................................................................................................... 4ꢅ
Pꢀogꢀam Counteꢀ Low Registeꢀ – PCL.................................................................................. 44
Look-up Table Registeꢀs – TBLPꢄ TBHPꢄ TBLH..................................................................... 44
Status Registeꢀ – STATUS.................................................................................................... 44
Rev. 1.00
ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
EEPROM Data Memory.................................................................................. 46
EEPRO� Data �emoꢀy Stꢀuꢁtuꢀe ........................................................................................ 46
EEPRO� Registeꢀs .............................................................................................................. 46
Reading Data fꢀom tꢂe EEPRO� ......................................................................................... 47
Wꢀiting Data to tꢂe EEPRO�................................................................................................ 48
Wꢀite Pꢀoteꢁtion..................................................................................................................... 48
EEPRO� Inteꢀꢀupt ................................................................................................................ 48
Pꢀogꢀamming Consideꢀations................................................................................................ 48
Pꢀogꢀamming Examples........................................................................................................ 49
Oscillator ........................................................................................................ 50
Osꢁillatoꢀ Oveꢀview ............................................................................................................... 50
System Clock Configurations................................................................................................ 50
Exteꢀnal Cꢀystal/Ceꢀamiꢁ Osꢁillatoꢀ – HXT ........................................................................... 51
Exteꢀnal RC Osꢁillatoꢀ – ERC ............................................................................................... 5ꢃ
Inteꢀnal Higꢂ Speed RC Osꢁillatoꢀ – HIRC ........................................................................... 5ꢃ
Exteꢀnal ꢅꢃ.768kHz Cꢀystal Osꢁillatoꢀ – LXT........................................................................ 5ꢅ
Inteꢀnal Low Speed Osꢁillatoꢀ – LIRC................................................................................... 54
Supplementaꢀy Osꢁillatoꢀs .................................................................................................... 54
Operating Modes and System Clocks ......................................................... 55
System Cloꢁk ........................................................................................................................ 55
System Opeꢀation �odes...................................................................................................... 56
Contꢀol Registeꢀ .................................................................................................................... 57
Fast Wake-up........................................................................................................................ 60
Opeꢀating �ode Switꢁꢂing.................................................................................................... 61
NOR�AL �ode to SLOW �ode Switꢁꢂing........................................................................... 6ꢃ
SLOW �ode to NOR�AL �ode Switꢁꢂing........................................................................... 6ꢅ
Enteꢀing tꢂe SLEEP0 �ode .................................................................................................. 64
Enteꢀing tꢂe SLEEP1 �ode .................................................................................................. 64
Enteꢀing tꢂe IDLE0 �ode...................................................................................................... 64
Enteꢀing tꢂe IDLE1 �ode...................................................................................................... 65
Standby Cuꢀꢀent Consideꢀations........................................................................................... 65
Wake-up................................................................................................................................ 66
Pꢀogꢀamming Consideꢀations................................................................................................ 66
Watchdog Timer............................................................................................. 67
Watꢁꢂdog Timeꢀ Cloꢁk Souꢀꢁe.............................................................................................. 67
Watꢁꢂdog Timeꢀ Contꢀol Registeꢀ......................................................................................... 67
Watꢁꢂdog Timeꢀ Opeꢀation ................................................................................................... 68
Reset and Initialisation.................................................................................. 70
Reset Funꢁtions .................................................................................................................... 70
Reset Initial Conditions ......................................................................................................... 74
Rev. 1.00
ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Input/Output Ports......................................................................................... 78
Pull-ꢂigꢂ Resistoꢀs ................................................................................................................ 80
Poꢀt A Wake-up ..................................................................................................................... 80
I/O Poꢀt Contꢀol Registeꢀs..................................................................................................... 80
Pin-sꢂaꢀed Funꢁtions ............................................................................................................ 80
I/O Pin Stꢀuꢁtuꢀes.................................................................................................................. 9ꢅ
Pꢀogꢀamming Consideꢀations................................................................................................ 94
Timer Modules – TM ...................................................................................... 94
Intꢀoduꢁtion ........................................................................................................................... 94
T� Opeꢀation ........................................................................................................................ 95
T� Cloꢁk Souꢀꢁe................................................................................................................... 95
T� Inteꢀꢀupts......................................................................................................................... 95
T� Exteꢀnal Pins................................................................................................................... 96
T� Input/Output Pin Contꢀol ................................................................................................. 97
Pꢀogꢀamming Consideꢀations................................................................................................ 98
Compact Type TM – CTM .............................................................................. 99
Compaꢁt T� Opeꢀation......................................................................................................... 99
Compaꢁt Type T� Registeꢀ Desꢁꢀiption.............................................................................. 100
Compaꢁt Type T� Opeꢀating �odes .................................................................................. 104
Compaꢀe �atꢁꢂ Output �ode............................................................................................. 104
Timeꢀ/Counteꢀ �ode ........................................................................................................... 107
PW� Output �ode.............................................................................................................. 107
Standard Type TM – STM .............................................................................110
Standaꢀd T� Opeꢀation........................................................................................................110
Standaꢀd Type T� Registeꢀ Desꢁꢀiption ..............................................................................111
Standaꢀd Type T� Opeꢀating �odes...................................................................................115
Compaꢀe �atꢁꢂ Output �ode..............................................................................................115
Timeꢀ/Counteꢀ �ode ............................................................................................................118
PW� Output �ode...............................................................................................................118
Single Pulse �ode .............................................................................................................. 1ꢃ1
Captuꢀe Input �ode ............................................................................................................ 1ꢃꢅ
Enhanced Type TM – ETM........................................................................... 125
Enꢂanꢁed T� Opeꢀation..................................................................................................... 1ꢃ5
Enꢂanꢁed Type T� Registeꢀ Desꢁꢀiption............................................................................ 1ꢃ6
Enꢂanꢁed Type T� Opeꢀating �odes................................................................................. 1ꢅꢃ
Compaꢀe Output �ode........................................................................................................ 1ꢅꢅ
Timeꢀ/Counteꢀ �ode ........................................................................................................... 1ꢅ8
PW� Output �ode.............................................................................................................. 1ꢅ8
Single Pulse �ode .............................................................................................................. 144
Captuꢀe Input �ode ............................................................................................................ 146
Rev. 1.00
4
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Aanlog to Digital Converter ........................................................................ 149
A/D Oveꢀview ...................................................................................................................... 149
A/D Conveꢀteꢀ Registeꢀ Desꢁꢀiption.................................................................................... 149
A/D Opeꢀation ..................................................................................................................... 15ꢅ
A/D Input Pins ..................................................................................................................... 154
Summaꢀy of A/D Conveꢀsion Steps..................................................................................... 154
Pꢀogꢀamming Consideꢀations.............................................................................................. 156
A/D Tꢀansfeꢀ Funꢁtion ......................................................................................................... 156
A/D Pꢀogꢀamming Example................................................................................................. 157
Comparators ................................................................................................ 159
Compaꢀatoꢀ Opeꢀation ........................................................................................................ 159
Compaꢀatoꢀ Registeꢀs......................................................................................................... 160
Compaꢀatoꢀ Inteꢀꢀupt........................................................................................................... 16ꢃ
Pꢀogꢀamming Consideꢀations.............................................................................................. 16ꢃ
Serial Interface Module – SIM..................................................................... 162
SPI Inteꢀfaꢁe ....................................................................................................................... 16ꢃ
SPI Registeꢀs ...................................................................................................................... 164
SPI Communiꢁation ............................................................................................................ 167
IꢃC Inteꢀfaꢁe ........................................................................................................................ 169
IꢃC Inteꢀfaꢁe Opeꢀation........................................................................................................ 169
IꢃC Registeꢀs ....................................................................................................................... 170
IꢃC Bus Communiꢁation ...................................................................................................... 174
IꢃC Bus Staꢀt Signal............................................................................................................. 175
Slave Addꢀess ..................................................................................................................... 175
IꢃC Bus Read/Wꢀite Signal .................................................................................................. 176
IꢃC Bus Slave Addꢀess Aꢁknowledge Signal....................................................................... 176
IꢃC Bus Data and Aꢁknowledge Signal ............................................................................... 176
Peripheral Clock Output.............................................................................. 179
Peꢀipꢂeꢀal Cloꢁk Opeꢀation................................................................................................. 179
Peꢀipꢂeꢀal Cloꢁk Registeꢀs.................................................................................................. 180
Serial Interface – SPIA................................................................................. 181
SPIA Inteꢀfaꢁe Opeꢀation .................................................................................................... 181
SPIA ꢀegisteꢀs ..................................................................................................................... 18ꢃ
SPIA Communiꢁation .......................................................................................................... 185
SPIA Bus Enable/Disable.................................................................................................... 187
SPIA Opeꢀation ................................................................................................................... 187
Eꢀꢀoꢀ Deteꢁtion.................................................................................................................... 188
Rev. 1.00
5
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Interrupts...................................................................................................... 189
Inteꢀꢀupt Registeꢀs............................................................................................................... 189
Inteꢀꢀupt Opeꢀation.............................................................................................................. ꢃ00
Exteꢀnal Inteꢀꢀupt................................................................................................................. ꢃ01
Compaꢀatoꢀ Inteꢀꢀupt........................................................................................................... ꢃ01
�ulti-funꢁtion Inteꢀꢀupt ........................................................................................................ ꢃ01
A/D Conveꢀteꢀ Inteꢀꢀupt....................................................................................................... ꢃ0ꢃ
Time Base Inteꢀꢀupt............................................................................................................. ꢃ0ꢃ
Seꢀial Inteꢀfaꢁe �odule Inteꢀꢀupts....................................................................................... ꢃ04
SPIA Inteꢀfaꢁe Inteꢀꢀupt....................................................................................................... ꢃ04
Exteꢀnal Peꢀipꢂeꢀal Inteꢀꢀupt ............................................................................................... ꢃ04
EEPRO� Inteꢀꢀupt .............................................................................................................. ꢃ05
LVD Inteꢀꢀupt....................................................................................................................... ꢃ05
T� Inteꢀꢀupts....................................................................................................................... ꢃ05
Inteꢀꢀupt Wake-up Funꢁtion................................................................................................. ꢃ06
Pꢀogꢀamming Consideꢀations.............................................................................................. ꢃ06
Low Voltage Detector – LVD ....................................................................... 207
LVD Registeꢀ....................................................................................................................... ꢃ07
LVD Opeꢀation..................................................................................................................... ꢃ08
SCOM Function for LCD.............................................................................. 209
LCD Opeꢀation .................................................................................................................... ꢃ09
LCD Bias Contꢀol ................................................................................................................ ꢃ09
Configuration Options................................................................................. 210
Application Circuits..................................................................................... 210
Instruction Set...............................................................................................211
Intꢀoduꢁtion ..........................................................................................................................ꢃ11
Instꢀuꢁtion Timing.................................................................................................................ꢃ11
�oving and Tꢀansfeꢀꢀing Data..............................................................................................ꢃ11
Aꢀitꢂmetiꢁ Opeꢀations...........................................................................................................ꢃ11
Logiꢁal and Rotate Opeꢀation ............................................................................................. ꢃ1ꢃ
Bꢀanꢁꢂes and Contꢀol Tꢀansfeꢀ ........................................................................................... ꢃ1ꢃ
Bit Opeꢀations ..................................................................................................................... ꢃ1ꢃ
Table Read Opeꢀations ....................................................................................................... ꢃ1ꢃ
Otꢂeꢀ Opeꢀations................................................................................................................. ꢃ1ꢃ
Instruction Set Summary ............................................................................ 213
Table Conventions............................................................................................................... ꢃ1ꢅ
Extended Instꢀuꢁtion Set..................................................................................................... ꢃ15
Instruction Definition................................................................................... 217
Extended Instruction Definition ........................................................................................... ꢃꢃ7
Package Information ................................................................................... 234
48-pin LQFP (7mm×7mm) Outline Dimensions .................................................................. ꢃꢅ5
64-pin LQFP (7mm×7mm) Outline Dimensions .................................................................. ꢃꢅ6
Rev. 1.00
6
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Features
CPU Features
•ꢀ OperatingꢀVoltage:
ꢀ
♦
ꢀ
♦
ꢀ
♦
fSYS=8MHz:ꢀ2.2V~5.5V
fSYS=12MHz:ꢀ2.7V~5.5V
fSYS=16MHz:ꢀ4.5V~5.5V
•ꢀ Upꢀtoꢀ0.25μsꢀinstructionꢀcycleꢀwithꢀ16MHzꢀsystemꢀclockꢀatꢀVDD=5V
•ꢀ Powerꢀdownꢀandꢀwake-upꢀfunctionsꢀtoꢀreduceꢀpowerꢀconsumption
•ꢀ Fiveꢀoscillators:
ꢀ
♦
ꢀ
♦
ꢀ
♦
ꢀ
♦
ꢀ
♦
ExternalꢀCrystalꢀ--ꢀHXT
Externalꢀ32.768kHzꢀCrystalꢀ--ꢀLXT
ExternalꢀRCꢀ--ꢀERC
InternalꢀRCꢀ--ꢀHIRC
Internalꢀ32kHzꢀRCꢀ--ꢀLIRC
•ꢀ Multi-modeꢀoperation:ꢀNORMAL,ꢀSLOW,ꢀIDLEꢀandꢀSLEEP
•ꢀ Fullyꢀintegratedꢀinternalꢀ8MHzꢀocilllatorꢀrequiresꢀnoꢀexternalꢀcomponents
•ꢀ Allꢀinstructionsꢀexecutedꢀinꢀ1~3ꢀinstructionꢀcycles
•ꢀ Tableꢀreadꢀinstructions
•ꢀ 114ꢀpowerfulꢀinstructions
•ꢀ Upꢀtoꢀ16-levelꢀsubroutineꢀnesting
•ꢀ Bitꢀmanipulationꢀinstruction
Peripheral Features
•ꢀ FlashꢀProgramꢀMemory:ꢀ16k×16~32k×16
•ꢀ DataꢀMemory:ꢀ1024×8~2048×8
•ꢀ EEPROMꢀMemory:ꢀ128×8
•ꢀ InꢀApplicationꢀProgrammingꢀfunction
•ꢀ WatchdogꢀTimerꢀfunction
•ꢀ Upꢀtoꢀ61ꢀbidirectionalꢀI/Oꢀlines
•ꢀ Softwareꢀcontrolledꢀ4-SCOMꢀlinesꢀLCDꢀdriverꢀwithꢀ1/2ꢀbias
•ꢀ Multipleꢀpin-sharedꢀexternalꢀinterrupts
•ꢀ MultipleꢀTimerꢀModuleꢀforꢀtimeꢀmeasure,ꢀinputꢀcapture,ꢀcompareꢀmatchꢀoutput,ꢀPWMꢀoutputꢀorꢀ
singleꢀpulseꢀoutputꢀfunction
•ꢀ SerialꢀInterfacesꢀModuleꢀ–ꢀSIMꢀforꢀSPIꢀorꢀI2C
•ꢀ SingleꢀsefialꢀSPIꢀinterfaceꢀ–ꢀSPIA
•ꢀ DualꢀComparatorꢀfunctions
•ꢀ DualꢀTime-Baseꢀfunctionsꢀforꢀgenerationꢀofꢀfixedꢀtimeꢀinterruptꢀsignals
•ꢀ Multi-channelꢀ12-bitꢀresolutionꢀA/Dꢀconverter
•ꢀ Lowꢀvoltageꢀresetꢀfunction
•ꢀ Lowꢀvoltageꢀdetectꢀfunction
•ꢀ Wideꢀrangeꢀofꢀavailableꢀpackageꢀtypes
•ꢀ Flashꢀprogramꢀmemoryꢀcanꢀbeꢀre-programmedꢀupꢀtoꢀ100,000ꢀtimes
•ꢀ Flashꢀprogramꢀmemoryꢀdataꢀretentionꢀ>ꢀ10ꢀyears
•ꢀ EEPROMꢀdataꢀmemoryꢀcanꢀbeꢀre-programmedꢀupꢀtoꢀ1,000,000ꢀtimes
•ꢀ EEPROMꢀdataꢀmemoryꢀdataꢀretentionꢀ>ꢀ10ꢀyears
Rev. 1.00
7
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
General Description
TheꢀHT66Fx0AꢀseriesꢀofꢀdevicesꢀareꢀFlashꢀMemoryꢀA/Dꢀtypeꢀ8-bitꢀhighꢀperformanceꢀRISCꢀ
architectureꢀmicrocontrollers,ꢀdesignedꢀforꢀaꢀwideꢀrangeꢀofꢀapplications.ꢀOfferingꢀusersꢀtheꢀ
convenienceꢀofꢀFlashꢀMemoryꢀmulti-programmingꢀfeatures,ꢀtheseꢀdevicesꢀalsoꢀincludeꢀaꢀwideꢀrangeꢀ
ofꢀfunctionsꢀandꢀfeatures.ꢀOtherꢀmemoryꢀincludesꢀanꢀareaꢀofꢀRAMꢀDataꢀMemoryꢀasꢀwellꢀasꢀanꢀareaꢀ
ofꢀEEPROMꢀmemoryꢀforꢀstorageꢀofꢀnon-volatileꢀdataꢀsuchꢀasꢀserialꢀnumbers,ꢀcalibrationꢀdataꢀetc.
Analogꢀfeaturesꢀincludeꢀaꢀmulti-channelꢀ12-bitꢀA/Dꢀconverterꢀandꢀdualꢀcomparatorꢀfunctions.ꢀ
MultipleꢀandꢀextremelyꢀflexibleꢀTimerꢀModulesꢀprovideꢀtiming,ꢀpulseꢀgenerationꢀandꢀPWMꢀ
generationꢀfunctions.ꢀCommunicationꢀwithꢀtheꢀoutsideꢀworldꢀisꢀcateredꢀforꢀbyꢀincludingꢀfullyꢀ
integratedꢀSPIꢀorꢀI2Cꢀinterfaceꢀfunctions,ꢀtwoꢀpopularꢀinterfacesꢀwhichꢀprovideꢀdesignersꢀwithꢀaꢀ
meansꢀofꢀeasyꢀcommunicationꢀwithꢀexternalꢀperipheralꢀhardware.ꢀProtectiveꢀfeaturesꢀsuchꢀasꢀanꢀ
internalꢀWatchdogꢀTimer,ꢀLowꢀVoltageꢀResetꢀandꢀLowꢀVoltageꢀDetectorꢀcoupledꢀwithꢀꢀexcellentꢀ
noiseꢀimmunityꢀandꢀESDꢀprotectionꢀensureꢀthatꢀreliableꢀoperationꢀisꢀmaintainedꢀinꢀhostileꢀelectricalꢀ
environments.ꢀAꢀfullꢀchoiceꢀofꢀHXT,ꢀLXT,ꢀERC,ꢀHIRCꢀandꢀLIRCꢀoscillatorꢀfunctionsꢀareꢀprovidedꢀ
includingꢀaꢀfullyꢀintegratedꢀsystemꢀoscillatorꢀwhichꢀrequiresꢀnoꢀexternalꢀcomponentsꢀforꢀitsꢀ
implementation.ꢀTheꢀabilityꢀtoꢀoperateꢀandꢀswitchꢀdynamicallyꢀbetweenꢀaꢀrangeꢀofꢀoperatingꢀmodesꢀ
usingꢀdifferentꢀclockꢀsourcesꢀgivesꢀusersꢀtheꢀabilityꢀtoꢀoptimiseꢀmicrocontrollerꢀoperationꢀandꢀ
minimiseꢀpowerꢀconsumption.
TheꢀinclusionꢀofꢀflexibleꢀI/Oꢀprogrammingꢀfeatures,ꢀTime-Baseꢀfunctionsꢀalongꢀwithꢀmanyꢀotherꢀ
featuresꢀensureꢀthatꢀtheꢀdevicesꢀwillꢀfindꢀexcellentꢀuseꢀinꢀapplicationsꢀsuchꢀasꢀelectronicꢀmetering,ꢀ
environmentalꢀmonitoring,ꢀhandheldꢀinstruments,ꢀhouseholdꢀappliances,ꢀelectronicallyꢀcontrolledꢀ
tools,ꢀmotorꢀdrivingꢀinꢀadditionꢀtoꢀmanyꢀothers.
Selection Table
Mostꢀfeaturesꢀareꢀcommonꢀtoꢀallꢀdevices.ꢀTheꢀmainꢀfeaturesꢀdistinguishingꢀthemꢀareꢀProgramꢀ
MemoryꢀandꢀDataꢀMemoryꢀcapacity.ꢀTheꢀfollowingꢀtableꢀsummarisesꢀtheꢀmainꢀfeaturesꢀofꢀeachꢀ
device.
Program
Memory Memory EEPROM
Data
Data
External
Interrupt Converter
A/D
Time
Base
Part No.
I/O
Timer Module SIM SPIA
Comparators Stacks package
10-bit CT� × ꢃ
1ꢃ-bit × 1ꢃ 16-bit ST� × ꢅ
48/64
LQFP
HT66F60A 16k × 16 10ꢃ4 × 8
HT66F70A ꢅꢃk × 16 ꢃ048 × 8
1ꢃ8 × 8
1ꢃ8 × 8
61
4
4
√
√
√
√
ꢃ
ꢃ
ꢃ
ꢃ
16
16
10-bit ET� × 1
10-bit CT� × ꢃ
1ꢃ-bit × 1ꢃ 16-bit ST� × ꢅ
10-bit ET� × 1
48/64
LQFP
61
Note:ꢀAsꢀdevicesꢀexistꢀinꢀmoreꢀthanꢀoneꢀpackageꢀformat,ꢀtheꢀtableꢀreflectsꢀtheꢀsituationꢀforꢀtheꢀpackageꢀwithꢀtheꢀ
mostꢀpins.
Rev. 1.00
8
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Block Diagram
L
w
o
W
t
a
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c
d
o
g
V
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o
a
t
e
g
T
m
i
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e
D
t
e
c
e
t
R
s
e
t
e
L
w
o
C
r
i
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c
t
i
V
l
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Rev. 1.00
9
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Pin Assignment
48 47 46 45 44 4ꢅ 4ꢃ 41 40 ꢅ9 ꢅ8 ꢅ7
1
ꢅ6
ꢅ5
ꢅ4
ꢅꢅ
ꢅꢃ
ꢅ1
ꢅ0
ꢃ9
ꢃ8
ꢃ7
ꢃ6
ꢃ5
PF1/AN11/C1P
PB7/SDI/SDA
ꢃ
PF0/AN10/C1N
PE7/AN9/INT1
PE6/AN8/INT0
VSS
PD6/SCK/SCL
ꢅ
PD7/SCS
4
PCꢃ/PCK/TCKꢃ/C0X
5
PCꢅ/PINT/TPꢃ/TPꢃB/TPꢃI/C1X
PC4/INTꢃ/TCKꢅ/TPꢃ/TPꢃB/TPꢃI/INT0/PINT
PC5/INTꢅ/TP0/TP0B/TP1B/TP1BB/TP1IB/INT1/PCK
PD0/TPꢅ/TPꢅB/SCS/TCKꢃ
PD1/TPꢃ/TPꢃB/TPꢃI/SDO/SCK/SCL
PDꢃ/SDI/SDA/TCK0
6
VDD
HT66F60A/HT66F70A
48 LQFP-A
7
PB4/XTꢃ
8
PBꢅ/XT1
9
VSSꢃ
10
11
1ꢃ
PB1/OSC1
PBꢃ/OSCꢃ
PE5/TPꢅ/TPꢅB
PDꢅ/TPꢅ/TPꢅB/SDO/SCK/SCL/TCK1
PD4/TPꢃ/TPꢃB/TPꢃI
1ꢅ 14 15 16 17 18 19 ꢃ0 ꢃ1 ꢃꢃ ꢃꢅ ꢃ4
64 6ꢅ 6ꢃ 61 60 59 58 57 56 55 54 5ꢅ 5ꢃ 51 50 49
48
1
PH0/TP0/TP0B/AN0/VREF/C0X
PF1/AN11/C1P
PF0/AN10/C1N
PE7/AN9/INT1
PE6/AN8/INT0
PF6
PH5/SDOA
ꢃ
47
46
45
44
4ꢅ
4ꢃ
41
40
ꢅ9
ꢅ8
ꢅ7
ꢅ6
ꢅ5
ꢅ4
ꢅꢅ
PB6/SDO
ꢅ
PB7/SDI/SDA
4
PD6/SCK/SCL
5
PD7/SCS
6
PCꢃ/PCK/TCKꢃ/C0X
7
VSS
PCꢅ/PINT/TPꢃ/TPꢃB/TPꢃI/C1X
PC4/INTꢃ/TCKꢅ/TPꢃ/TPꢃB/TPꢃI/INT0/PINT
PC5/INTꢅ/TP0/TP0B/TP1B/TP1BB/TP1IB/INT1/PCK
PD0/TPꢅ/TPꢅB/SCS/TCKꢃ
PD1/TPꢃ/TPꢃB/TPꢃI/SDO/SCK/SCL
PDꢃ/SDI/SDA/TCK0
8
VDD
HT66F60A/HT66F70A
64 LQFP-A
9
PB4/XTꢃ
10
11
1ꢃ
1ꢅ
14
15
16
PBꢅ/XT1
VSSꢃ
PB1/OSC1
PBꢃ/OSCꢃ
PF4
PDꢅ/TPꢅ/TPꢅB/SDO/SCK/SCL/TCK1
PGꢃ/TCK4
PFꢅ
PGꢅ/TP4/TP4B/TP4I
PE5/TPꢅ/TPꢅB
PG4/TP4/TP4B/TP4I
17 18 19 ꢃ0 ꢃ1 ꢃꢃ ꢃꢅ ꢃ4 ꢃ5 ꢃ6 ꢃ7 ꢃ8 ꢃ9 ꢅ0 ꢅ1 ꢅꢃ
Rev. 1.00
10
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
48 47 46 45 44 4ꢅ 4ꢃ 41 40 ꢅ9 ꢅ8 ꢅ7
1
ꢅ6
ꢅ5
ꢅ4
ꢅꢅ
ꢅꢃ
ꢅ1
ꢅ0
ꢃ9
ꢃ8
ꢃ7
ꢃ6
ꢃ5
PF1/AN11/C1P
PF0/AN10/C1N
PE7/AN9/INT1
PE6/AN8/INT0
VSS
PB7/SDI/SDA
ꢃ
PD6/SCK/SCL
ꢅ
PD7/SCS
4
PCꢃ/PCK/TCKꢃ/C0X
5
PCꢅ/PINT/TPꢃ/TPꢃB/TPꢃI/C1X
PC4/INTꢃ/TCKꢅ/TPꢃ/TPꢃB/TPꢃI/INT0/PINT
PC5/INTꢅ/TP0/TP0B/TP1B/TP1BB/TP1IB/INT1/PCK
PD0/TPꢅ/TPꢅB/SCS/TCKꢃ
PD1/TPꢃ/TPꢃB/TPꢃI/SDO/SCK/SCL
PDꢃ/SDI/SDA/TCK0
6
VDD
HT66V70A
48 LQFP-A
7
PB4/XTꢃ
8
PBꢅ/XT1
9
VSSꢃ
10
11
1ꢃ
PB1/OSC1
PBꢃ/OSCꢃ
PE5/TPꢅ/TPꢅB
PDꢅ/TPꢅ/TPꢅB/SDO/SCK/SCL/TCK1
PD4/TPꢃ/TPꢃB/TPꢃI
1ꢅ 14 15 16 17 18 19 ꢃ0 ꢃ1 ꢃꢃ ꢃꢅ ꢃ4
64 6ꢅ 6ꢃ 61 60 59 58 57 56 55 54 5ꢅ 5ꢃ 51 50 49
48
1
PH0/TP0/TP0B/AN0/VREF/C0X
PF1/AN11/C1P
PF0/AN10/C1N
PE7/AN9/INT1
PE6/AN8/INT0
PF6
PH5/SDOA
ꢃ
47
46
45
44
4ꢅ
4ꢃ
41
40
ꢅ9
ꢅ8
ꢅ7
ꢅ6
ꢅ5
ꢅ4
ꢅꢅ
PB6/SDO
ꢅ
PB7/SDI/SDA
4
PD6/SCK/SCL
5
PD7/SCS
6
PCꢃ/PCK/TCKꢃ/C0X
7
VSS
PCꢅ/PINT/TPꢃ/TPꢃB/TPꢃI/C1X
PC4/INTꢃ/TCKꢅ/TPꢃ/TPꢃB/TPꢃI/INT0/PINT
PC5/INTꢅ/TP0/TP0B/TP1B/TP1BB/TP1IB/INT1/PCK
PD0/TPꢅ/TPꢅB/SCS/TCKꢃ
PD1/TPꢃ/TPꢃB/TPꢃI/SDO/SCK/SCL
PDꢃ/SDI/SDA/TCK0
HT66V70A
64 LQFP-A
8
VDD
9
PB4/XTꢃ
10
11
1ꢃ
1ꢅ
14
15
16
PBꢅ/XT1
VSSꢃ
PB1/OSC1
PBꢃ/OSCꢃ
PF4
PDꢅ/TPꢅ/TPꢅB/SDO/SCK/SCL/TCK1
PGꢃ/TCK4
PFꢅ
PGꢅ/TP4/TP4B/TP4I
PE5/TPꢅ/TPꢅB
PG4/TP4/TP4B/TP4I
17 18 19 ꢃ0 ꢃ1 ꢃꢃ ꢃꢅ ꢃ4 ꢃ5 ꢃ6 ꢃ7 ꢃ8 ꢃ9 ꢅ0 ꢅ1 ꢅꢃ
Note:ꢀ1.ꢀIfꢀtheꢀpin-sharedꢀpinꢀfunctionsꢀhaveꢀmultipleꢀoutputsꢀsimultaneously,ꢀtheꢀpin-sharedꢀfunctionꢀisꢀ
determinedꢀbyꢀtheꢀcorrespondingꢀsoftwareꢀcontrolꢀbitsꢀexceptꢀtheꢀfunctionsꢀdeterminedꢀbyꢀtheꢀ
configurationꢀoptions.
2.ꢀTheꢀHT66Vx0AꢀdeviceꢀisꢀtheꢀEVꢀchipꢀofꢀtheꢀHT66Fx0Aꢀseriesꢀofꢀdevices.ꢀItꢀsupportsꢀtheꢀ“On-Chipꢀ
Debug”ꢀfunctionꢀforꢀdebuggingꢀduringꢀdevelopmentꢀusingꢀtheꢀOCDSDAꢀandꢀOCDSCKꢀpinsꢀconnectedꢀ
toꢀtheꢀHoltekꢀHT-IDEꢀdevelopmentꢀtools.
Rev. 1.00
11
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Pin Description
Pad Name
Function OPT
I/T
O/T
Description
PAWU
PAPU
PA0
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up and wake-up
PA0/ICPDA/
OCDSDA
ICPDA
—
—
ST C�OS ICP Data/Addꢀess
OCDSDA
ST C�OS OCDS Data/Addꢀessꢄ foꢀ EV ꢁꢂip only
PAWU
PA1
PAPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up and wake-up
PAS0
PA1/TP1A/
TP1IA/AN1
TP1A
TP1IA
AN1
PAS0
IFSꢃ
—
C�OS T�1 A output
ST
—
—
T�1 A input
PAS0 AN
PAWU
PAPU
A/D Conveꢀteꢀ analog input
PAꢃ
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up and wake-up
PAꢃ/ICPCK/
OCDSCK
ICPCK
—
ST C�OS ICP Cloꢁk pin
OCDSCK
—
ST
—
OCDS Cloꢁk pinꢄ foꢀ EV ꢁꢂip only
PAWU
PAꢅ
PAPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up and wake-up
PAS1
INTEG
INTC0 ST
IFS0
PAꢅ/INT0/
ANꢅ/C0N
INT0
—
Exteꢀnal Inteꢀꢀupt 0
ANꢅ
C0N
PAS1 AN
PAS1 AN
PAPU
—
—
A/D Conveꢀteꢀ analog input
Compaꢀatoꢀ 0 inveꢀting input
PA4
PAWU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up and wake-up
PASꢃ
INTEG
INTC0 ST
IFS0
PA4/INT1/
TCK1/AN4
INT1
—
Exteꢀnal Inteꢀꢀupt 1
TCK1
AN4
IFS1
ST
—
—
T�1 input
PAS1 AN
PAWU
A/D Conveꢀteꢀ analog input
PA5
PAPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up and wake-up
PASꢃ
PA5/SDO/
AN5/C1X
SDO
AN5
C1X
PASꢃ
—
C�OS SPI data output
PASꢃ AN
—
A/D Conveꢀteꢀ analog input
PASꢃ
—
C�OS Compaꢀatoꢀ 1 output
PAWU
PA6
SDI
PAPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up and wake-up
PASꢅ
PASꢅ
PA6/SDI/
SDA/AN6
ST
—
SPI data input
IFS4
PASꢅ
IFS4
SDA
AN6
ST N�OS IꢃC data line
PASꢅ AN
PAWU
—
A/D Conveꢀteꢀ analog input
PA7
PAPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up and wake-up
PASꢅ
PASꢅ
PA7/SCK/
SCL/AN7
SCK
ST C�OS SPI seꢀial ꢁloꢁk
IFS4
PASꢅ
IFS4
SCL
AN7
ST N�OS IꢃC ꢁloꢁk line
PASꢅ AN
—
A/D Conveꢀteꢀ analog input
1ꢃ
Rev. 1.00
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Pad Name
PB0/RES
Function OPT
I/T
PBPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
CO ST Reset pin
PBPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
CO HXT HXT/ERC osꢁillatoꢀ pin & EC mode input pin
PBPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
CO HXT HXT osꢁillatoꢀ pin
PBPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
CO LXT LXT osꢁillatoꢀ pin
PBPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
O/T
Description
PB0
RES
PB1
—
PB1/OSC1
PBꢃ/OSCꢃ
PBꢅ/XT1
OSC1
PBꢃ
—
OSCꢃ
PBꢅ
—
XT1
—
PB4
PB4/XTꢃ
XTꢃ
CO
—
LXT LXT osꢁillatoꢀ pin
PBPU
PBSꢃ
PB5
SCS
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
ST C�OS SPI slave seleꢁt
PB5/SCS
PB6/SDO
PBSꢃ
IFS4
PBPU
PBSꢅ
PB6
SDO
PB7
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up and wake-up
PBSꢅ
—
C�OS SPI data output
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up and wake-up
ST SPI data input
PBPU
PBSꢅ
PBSꢅ
IFS4
PB7/SDI/SDA
SDI
—
PBSꢅ
IFS4
SDA
ST N�OS IꢃC data line
PCPU
PCS0
PC0
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PC0/TP1B/
TP1BB/TP1IB/
SCO�0
TP1B
PCS0
—
—
C�OS T�1 B output
TP1BB PCS0
TP1IB IFSꢃ
C�OS T�1 inveꢀted B output
ST
—
—
T�1 B input
SCO�0 PCS0
SCO� LCD ꢁommon output
PCPU
PC1
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PCS0
PC1/TP1B/
TP1BB/TP1IB/
SCO�1
TP1B
TP1BB PCS0
TP1IB IFSꢃ
PCS0
—
—
C�OS T�1 B output
C�OS T�1 inveꢀted B output
ST
—
—
T�1 B input
SCO�1 PCS0
SCO� LCD ꢁommon output
PCPU
PCꢃ
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PCS1
PCꢃ/PCK/
TCKꢃ/C0X
PCK
TCKꢃ
C0X
PCS1
IFS1
—
ST
—
C�OS Peꢀipꢂeꢀal ꢁloꢁk output
T�ꢃ input
C�OS Compaꢀatoꢀ 0 output
—
PCS1
PCPU
PCS1
PCꢅ
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PINT
TPꢃ
IFS0
PCS1
PCS1
IFSꢃ
ST
—
—
Peꢀipꢂeꢀal inteꢀꢀupt
PCꢅ/PINT/TPꢃ/
TPꢃB/TPꢃI/C1X
C�OS T�ꢃ output
TPꢃB
TPꢃI
C1X
—
C�OS T�ꢃ inveꢀted output
ST
—
—
T�ꢃ input
PCS1
C�OS Compaꢀatoꢀ 1 output
Rev. 1.00
1ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Pad Name
Function OPT
I/T
O/T
Description
PCPU
PC4
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PCSꢃ
INTEG
INTꢃ
INTCꢅ ST
IFS0
—
—
Exteꢀnal Inteꢀꢀupt ꢃ
T�ꢅ input
TCKꢅ
TPꢃ
IFS1
ST
—
PC4/INTꢃ/TCKꢅ/
TPꢃ/TPꢃB/TPꢃI/
INT0/PINT
PCS1
PCS1
IFSꢃ
C�OS T�ꢃ output
TPꢃB
TPꢃI
—
C�OS T�ꢃ inveꢀted output
ST
—
—
—
T�ꢃ input
INTEG
INTC0 ST
IFS0
INT0
Exteꢀnal Inteꢀꢀupt 0
Peꢀipꢂeꢀal inteꢀꢀupt
PINT
PC5
IFS0
ST
PCPU
PCSꢃ
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
INTEG
INTCꢅ
INTꢅ
ST
—
Exteꢀnal Inteꢀꢀupt ꢅ
TP0
PCSꢃ
PCSꢃ
PCSꢃ
—
—
—
—
ST
C�OS T�0 output
PC5/INTꢅ/TP0/
TP0B/TP1B/
TP1BB/TP1IB/
INT1/PCK
TP0B
TP1B
C�OS T�0 inveꢀted output
C�OS T�1 B output
TP1BB PCSꢃ
C�OS T�1 inveꢀted B output
TP1IB
IFSꢃ
—
T�1 B input
INTEG
INT1
INTC0 ST
IFS0
—
Exteꢀnal Inteꢀꢀupt 1
PCK
PC6
PCSꢃ
—
C�OS Peꢀipꢂeꢀal ꢁloꢁk output
PCPU
PCSꢅ
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PC6/SCO�ꢃ/
TP0/TP0B
SCO�ꢃ PCSꢅ
—
—
—
SCO� LCD ꢁommon output
C�OS T�0 output
TP0
PCSꢅ
PCSꢅ
TP0B
C�OS T�0 inveꢀted output
PCPU
PCSꢅ
PC7
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PC7/SCO�ꢅ/
TP1A/TP1IA
SCO�ꢅ PCSꢅ
—
—
SCO� LCD ꢁommon output
C�OS T�1 A output
TP1A
PCSꢅ
IFSꢃ
TP1IA
ST
—
T�1 A input
PDPU
PDS0
PD0
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
TPꢅ
PDS0
PDS0
—
—
C�OS T�ꢅ output
PD0/TPꢅ/TPꢅB/
SCS/TCKꢃ
TPꢅB
C�OS T�ꢅ inveꢀted output
PDS0
IFS4
SCS
ST C�OS SPI slave seleꢁt
ST T�ꢃ input
TCKꢃ
IFS1
—
Rev. 1.00
14
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Pad Name
Function OPT
I/T
O/T
Description
PDPU
PD1
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PDS0
TPꢃ
TPꢃB
TPꢃI
SDO
PDS0
PDS0
IFSꢃ
—
—
C�OS T�ꢃ output
C�OS T�ꢃ inveꢀted output
PD1/TPꢃ/TPꢃB/
TPꢃI/SDO/SCK/
SCL
ST
—
—
T�ꢃ input
PDS0
C�OS SPI slave seleꢁt
PDS0
IFS4
SCK
SCL
PDꢃ
SDI
ST C�OS SPI seꢀial ꢁloꢁk
PDS0
IFS4
ST N�OS IꢃC ꢁloꢁk line
PDPU
PDS1
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PDS1
IFS4
ST
ST N�OS IꢃC data line
ST T�0 input
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
—
SPI data input
PDꢃ/SDI/
SDA/TCK0
PDS1
IFS4
SDA
TCK0
PDꢅ
IFS1
—
PDPU
PDS1
TPꢅ
TPꢅB
SDO
PDS1
PDS1
PDS1
—
—
—
C�OS T�ꢅ output
C�OS T�ꢃ inveꢀted output
C�OS SPI slave seleꢁt
PDꢅ/TPꢅ/TPꢅB/
SDO/SCK/SCL/
TCK1
PDS1
IFS4
SCK
ST C�OS SPI seꢀial ꢁloꢁk
ST N�OS IꢃC ꢁloꢁk line
PDS1
IFS4
SCL
TCK1
PD4
IFS1
ST
—
T�1 input
PDPU
PDSꢃ
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PD4/TPꢃ/TPꢃB/
TPꢃI
TPꢃ
TPꢃB
TPꢃI
PDSꢃ
PDSꢃ
IFSꢃ
—
—
C�OS T�ꢃ output
C�OS T�ꢃ inveꢀted output
ST
—
T�ꢃ input
PDPU
PDSꢃ
PD5
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PD5/TP0/TP0B
TP0
PDSꢃ
PDSꢃ
—
—
C�OS T�0 output
TP0B
C�OS T�0 inveꢀted output
PDPU
PDSꢅ
PD6
SCK
SCL
PD7
SCS
PE0
SCSA
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
ST C�OS SPI seꢀial ꢁloꢁk
PDSꢅ
IFS4
PD6/SCK/SCL
PD7/SCS
PDSꢅ
IFS4
ST N�OS IꢃC ꢁloꢁk line
PDPU
PDSꢅ
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
ST C�OS SPI slave seleꢁt
PDSꢅ
IFS4
PEPU
PES0
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
ST C�OS SPIA slave seleꢁt
PES0
IFS5
PE0/SCSA/INT0
Rev. 1.00
INTEG
INTC0 ST
IFS0
INT0
—
Exteꢀnal Inteꢀꢀupt 0
15
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Pad Name
Function OPT
I/T
O/T
Description
PEPU
PE1
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
ST C�OS SPIA seꢀial ꢁloꢁk
PES0
PES0
SCKA
PE1/SCKA/INT1
IFS5
INTEG
INT1
INTC0 ST
—
Exteꢀnal Inteꢀꢀupt 1
IFS0
PEPU
PES1
PEꢃ
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
ST C�OS SPI seꢀial ꢁloꢁk
SDIA
IFS5
PEꢃ/SDIA/INTꢃ
INTEG
INTꢃ
INTCꢅ ST
IFS0
—
Exteꢀnal Inteꢀꢀupt ꢃ
PEPU
PEꢃ
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PES1
PES1
IFS1
PEꢅ/SDOA/TCKꢅ
SDOA
TCKꢅ
ST C�OS SPIA seꢀial ꢁloꢁk
ST
—
T�ꢅ input
PEPU
PESꢃ
PE4
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PE4/TP1B/
TP1BB/TP1IB
TP1B
PESꢃ
—
—
C�OS T�1 B output
TP1BB PESꢃ
C�OS T�1 inveꢀted B output
TP1IB
IFSꢃ
ST
—
T�1 B input
PEPU
PESꢃ
PE5
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PE5/TPꢅ/TPꢅB
PE6/AN8/INT0
TPꢅ
PESꢃ
PESꢃ
—
—
C�OS T�ꢅ output
TPꢅB
C�OS T�ꢅ inveꢀted output
PEPU
PESꢅ
PE6
AN8
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PESꢅ AN
—
—
A/D Conveꢀteꢀ analog input
Exteꢀnal Inteꢀꢀupt 0
INTEG
INTC0 ST
IFS0
INT0
PEPU
PESꢅ
PE7
AN9
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PESꢅ AN
—
—
A/D Conveꢀteꢀ analog input
Exteꢀnal Inteꢀꢀupt 1
PE7/AN9/INT1
INTEG
INTC0 ST
IFS0
INT1
PFPU
PFS0
PF0
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PF0/AN10/C1N
PF1/AN11/C1P
AN10
C1N
PFS0 AN
PFS0 AN
PFPU
—
—
A/D Conveꢀteꢀ analog input
Compaꢀatoꢀ 1 inteꢀting input
PF1
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PFS0
AN11
C1P
PFn
PFS0 AN
PFS0 AN
—
—
A/D Conveꢀteꢀ analog input
Compaꢀatoꢀ 1 non-inteꢀting input
PFꢃ~PF6
PG0/C0X
PFPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PGPU
PG0
C0X
PG1
C1X
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PGS0
PGS0
—
C�OS Compaꢀatoꢀ 0 output
PGPU
PGS0
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PG1/C1X
Rev. 1.00
PGS0
—
C�OS Compaꢀatoꢀ 1 output
16
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Pad Name
PGꢃ/TCK4
Function OPT
I/T
O/T
Description
PGꢃ
PGPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
TCK4
—
ST
—
T�4 input
PGPU
PGS1
PGꢅ
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PGꢅ/TP4/
TP4B/TP4I
TP4
TP4B
TP4I
PGS1
PGS1
IFSꢅ
—
—
C�OS T�4 output
C�OS T�4 inveꢀted output
ST
—
T�4 input
PGPU
PGSꢃ
PG4
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PG4/TP4/
TP4B/TP4I
TP4
TP4B
TP4I
PG5
PGSꢃ
PGSꢃ
IFSꢅ
—
—
C�OS T�4 output
C�OS T�4 inveꢀted output
ST
—
T�4 input
PGPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PG5/TCK5
TCK5
—
ST
—
T�5 input
PGPU
PGSꢅ
PG6
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PG6/TP5/
TP5B/TP5I
TP5
TP5B
TP5I
PGSꢅ
PGSꢅ
IFSꢅ
—
—
C�OS T�5 output
C�OS T�5 inveꢀted output
ST
—
T�5 input
PGPU
PGSꢅ
PG7
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PG7/TP5/
TP5B/TP5I
TP5
TP5B
TP5I
PGSꢅ
PGSꢅ
IFSꢅ
—
—
C�OS T�5 output
C�OS T�5 inveꢀted output
ST
—
T�5 input
PHPU
PHS0
PH0
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
TP0
TP0B
AN0
PHS0
PHS0
—
—
C�OS T�0 output
PH0/TP0/TP0B/
AN0/VREF/C0X
C�OS T�0 inveꢀted output
PHS0 AN
PHS0 AN
—
—
A/D Conveꢀteꢀ analog input
A/D Conveꢀteꢀ ꢀefeꢀenꢁe input
VREF
C0X
PHS0
—
C�OS Compaꢀatoꢀ 0 output
PHPU
PHS0
PH0
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PH1/TCK0/
ANꢃ/C0P
TCK0
ANꢃ
IFS1
ST
—
—
—
T�0 input
PHS0 AN
PHS0 AN
PHPU
A/D Conveꢀteꢀ analog input
Compaꢀatoꢀ 0 non-inveꢀting input
C0P
PHꢃ
SCSA
PHꢅ
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
ST C�OS SPIA slave seleꢁt
PHS1
PHꢃ/SCSA
PHꢅ/SCKA
PHS1
IFS5
PHPU
PHS1
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
ST C�OS SPIA seꢀial ꢁloꢁk
PHS1
IFS5
SCKA
PH4
PHPU ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PH4/SDIA
SDIA
IFS5
ST C�OS SPIA seꢀial data input
PHPU
PHSꢃ
PH5
ST C�OS Geneꢀal puꢀpose I/O. Registeꢀ enabled pull-up
PH5/SDOA
SDOA
VDD
VSS
PHSꢃ ST C�OS SPIA seꢀial data output
VDD
VSS
—
—
PWR
PWR
—
—
Positive Poweꢀ supply
Negative Poweꢀ supply. Gꢀound
Rev. 1.00
17
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
OperatingꢀTemperature
StorageꢀTemperature
....................................................................................................-50˚Cꢀtoꢀ125˚Cꢀ
..................................................................................................-40˚Cꢀtoꢀ85˚Cꢀ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Pad Name
VSSꢃ
Function OPT
VSSꢃ
I/T
O/T
Description
I/O Pad Poweꢀ supply. Gꢀound
—
PWR
—
Note:ꢀI/T:ꢀInputꢀtype;ꢀꢀ
ꢀ
O/T:ꢀOutputꢀtype
OPT:ꢀOptionalꢀbyꢀconfigurationꢀoptionꢀ(CO)ꢀorꢀregisterꢀoption
PWR:ꢀPower;ꢀꢀ
ꢀ
CO:ꢀConfigurationꢀoption
ST:ꢀSchmittꢀTriggerꢀinput;
CMOS:ꢀCMOSꢀoutput;ꢀꢀ
NMOS:ꢀNMOSꢀoutput
HXT:ꢀHighꢀfrequencyꢀcrystalꢀoscillator
LXT:ꢀLowꢀfrequencyꢀcrystalꢀoscillator
Absolute Maximum Ratings
SupplyꢀVoltageꢀ................................................................................................VSS−0.3VꢀtoꢀVSS+6.0Vꢀ
InputꢀVoltageꢀ..................................................................................................VSS−0.3VꢀtoꢀVDD+0.3Vꢀ
IOHꢀTotalꢀ....................................................................................................................................-80mAꢀ
IOLꢀTotalꢀ..................................................................................................................................... 80mAꢀ
TotalꢀPowerꢀDissipationꢀꢀ........................................................................................................ 500mWꢀ
Note:ꢀTheseꢀareꢀstressꢀratingsꢀonly.ꢀStressesꢀexceedingꢀtheꢀrangeꢀspecifiedꢀunderꢀ"AbsoluteꢀMaximumꢀ
Ratings"ꢀmayꢀcauseꢀsubstantialꢀdamageꢀtoꢀtheseꢀdevices.ꢀFunctionalꢀoperationꢀofꢀtheseꢀdevicesꢀatꢀ
otherꢀconditionsꢀbeyondꢀthoseꢀlistedꢀinꢀtheꢀspecificationꢀisꢀnotꢀimpliedꢀandꢀprolongedꢀexposureꢀtoꢀ
extremeꢀconditionsꢀmayꢀaffectꢀdevicesꢀreliability.
D.C. Characteristics
Ta=ꢃ5°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Conditions
fSYS=8�Hz
ꢃ.ꢃ
ꢃ.7
4.5
ꢃ.ꢃ
ꢃ.7
4.5
ꢃ.ꢃ
—
—
—
5.5
5.5
5.5
5.5
5.5
5.5
5.5
1.5
4.0
ꢃ.0
4.5
ꢃ.5
5.5
V
V
VDD1
Opeꢀating Voltage (HXT)
—
fSYS=1ꢃ�Hz
fSYS=16�Hz
fSYS=6�Hz
fSYS=8�Hz
fSYS=1ꢃ�Hz
fSYS=4/8 �Hz
—
V
—
V
VDDꢃ
Opeꢀating Voltage (ERC)
Opeꢀating Voltage (HIRC)
—
—
V
—
V
VDDꢅ
—
ꢅV
5V
ꢅV
5V
ꢅV
5V
—
V
1.0
ꢃ.5
1.ꢃ
ꢃ.8
1.5
ꢅ.5
mA
mA
mA
mA
mA
mA
No loadꢄ fH=8�Hzꢄ ADC offꢄ
WDT enable
—
—
No loadꢄ fH=10�Hzꢄ ADC offꢄ
WDT enable
Opeꢀating Cuꢀꢀent
(HXTꢄ fSYS=fHꢄ
—
IDD1
—
No loadꢄ fH=1ꢃ�Hzꢄ ADC offꢄ
WDT enable
fS=fSUB=fRTC oꢀ fLIRC
)
—
No loadꢄ fH=16�Hzꢄ ADC offꢄ
WDT enable
5V
—
4.5
7.0
mA
Rev. 1.00
18
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
ꢅV
5V
ꢅV
5V
Conditions
—
—
—
—
0.9
ꢃ.0
1.ꢃ
ꢃ.8
1.5
ꢅ.0
ꢃ.0
4.5
mA
mA
mA
mA
No loadꢄ fH=6�Hzꢄ ADC offꢄ
WDT enable
Opeꢀating Cuꢀꢀent
(ERCꢄ fSYS=fHꢄ
No loadꢄ fH=8�Hzꢄ ADC offꢄ
WDT enable
IDDꢃ
fS=fSUB=fRTC oꢀ fLIRC
)
No loadꢄ fH=1ꢃ�Hzꢄ ADC offꢄ
WDT enable
5V
—
4.0
6.0
mA
ꢅV
5V
ꢅV
5V
ꢅV
5V
ꢅV
5V
ꢅV
5V
ꢅV
5V
ꢅV
5V
ꢅV
5V
ꢅV
5V
ꢅV
5V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.7
1.5
1.ꢃ
ꢃ.8
0.9
ꢃ.1
0.6
1.6
0.48
1.ꢃ
0.4ꢃ
1.1
0.ꢅ8
1.0
0.ꢅ6
1.0
10
1.ꢃ
ꢃ.5
ꢃ.0
4.5
1.5
ꢅ.ꢅ
1.0
ꢃ.5
0.8
ꢃ.0
0.7
1.7
0.6
1.5
0.55
1.5
ꢃ0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
No loadꢄ fH=4�Hzꢄ ADC offꢄ
WDT enable
Opeꢀating Cuꢀꢀent
(HIRC OSCꢄ fSYS=fHꢄ
IDDꢅ
IDD4
IDD5
No loadꢄ fH=8�Hzꢄ ADC offꢄ
WDT enable
fS=fSUB=fRTC oꢀ fLIRC
)
No loadꢄ fH=1ꢃ�Hzꢄ fL=fH/ꢃꢄ
ADC offꢄ WDT enable
No loadꢄ fH=1ꢃ�Hzꢄ fL=fH/4ꢄ
ADC offꢄ WDT enable
No loadꢄ fH=1ꢃ�Hzꢄ fL=fH/8ꢄ
ADC offꢄ WDT enable
Opeꢀating Cuꢀꢀent
(HXTꢄ fSYS=fLꢄ
No loadꢄ fH=1ꢃ�Hzꢄ fL=fH/16ꢄ
ADC offꢄ WDT enable
fS=fSUB=fRTC oꢀ fLIRC
)
No loadꢄ fH=1ꢃ�Hzꢄ fL=fH/ꢅꢃꢄ
ADC offꢄ WDT enable
No loadꢄ fH=1ꢃ�Hzꢄ fL=fH/64ꢄ
ADC offꢄ WDT enable
No loadꢄ ADC offꢄ WDT enableꢄ
LXTLP=0ꢄ LVD&LVR disable
Opeꢀating Cuꢀꢀent
(LXTꢄ fSYS=fL=fRTC
fS=fSUB=fRTC
ꢅ0
50
μA
ꢄ
10
ꢃ0
μA
No loadꢄ ADC offꢄ WDT enableꢄ
LXTLP=1ꢄ LVD & LVR disable
)
ꢅ0
50
μA
Opeꢀating Cuꢀꢀent
(LIRCꢄ fSYS=fL=fLIRC
ꢅV
5V
ꢅV
5V
ꢅV
5V
—
—
—
—
—
—
10
ꢅ0
ꢃ0
50
μA
μA
mA
mA
μA
μA
No loadꢄ ADC offꢄ WDT enableꢄ
LVD&LVR disable
IDD6
ꢄ
fS=fSUB=fLIRC
)
Standby Cuꢀꢀent (IDLE1)
(HXTꢄ fSYS=fHꢄ
0.6
1.ꢃ
1.ꢅ
ꢃ.ꢃ
1.0
ꢃ.0
ꢅ.0
5.0
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=1ꢃ�Hz
ISTB1
fS=fSUB=fRTC oꢀ fLIRC
)
Standby Cuꢀꢀent (IDLE0)
(HXTꢄ fSYS=offꢄ
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=1ꢃ�Hz
ISTBꢃ
ISTBꢅ
ISTB4
fS=fSUB=fRTC oꢀ fLIRC
)
ꢅV
5V
—
—
1.ꢅ
ꢃ.ꢃ
ꢅ.0
5.0
μA
μA
Standby Cuꢀꢀent (IDLE0)
(ERCꢄ fSYS=offꢄ fS=fSUB=fRTC
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=1ꢃ�Hz
)
Standby Cuꢀꢀent (IDLE0)
(HIRCꢄ fSYS=offꢄ
ꢅV
5V
ꢅV
5V
ꢅV
5V
ꢅV
5V
—
—
—
—
—
—
—
—
1.ꢅ
ꢃ.ꢃ
ꢅ.0
5.0
0.6
1.ꢃ
ꢅ.0
5.0
4.0
7.0
μA
μA
mA
mA
μA
μA
μA
μA
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=8�Hz
fS=fSUB=fLIRC
)
Standby Cuꢀꢀent (IDLE1)
(HXTꢄ fSYS=fLꢄ
0.ꢅ4
0.85
1.ꢅ
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=1ꢃ�Hz/64
ISTB5
ISTB6
ISTB7
fS=fSUB=fRTC oꢀ fLIRC
)
Standby Cuꢀꢀent (IDLE0)
(HXTꢄ fSYS=offꢄ
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=1ꢃ�Hz/64
ꢃ.ꢃ
fS=fSUB=fRTC oꢀ fLIRC
)
Standby Cuꢀꢀent (IDLE1)
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=ꢅꢃ768Hzꢄ
LXTLP=1
1.9
(LXTꢄ fSYS=fL=fRTC
ꢄ
ꢅ.ꢅ
fS=fSUB=fRTC
)
Rev. 1.00
19
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Conditions
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=ꢅꢃ768Hzꢄ
LXTLP=1
ꢅV
─
1.ꢅ
ꢃ.ꢃ
ꢅ.0
5.0
μA
μA
Standby Cuꢀꢀent (IDLE0)
(LXTꢄ fSYS=offꢄ fS=fSUB=fRTC
ISTB8
ISTB9
ISTB10
)
5V
—
ꢅV
5V
—
—
1.ꢅ
ꢃ.ꢃ
ꢅ.0
5.0
μA
μA
Standby Cuꢀꢀent (IDLE0)
(LIRCꢄ fSYS=offꢄ fS=fSUB=fLIRC
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=ꢅꢃkHz
)
Standby Cuꢀꢀent (SLEEP0)
(HXTꢄ fSYS=offꢄ
ꢅV
5V
—
—
0.1
0.ꢅ
1
ꢃ
μA
μA
No loadꢄ system HALTꢄ ADC offꢄ
WDT disableꢄ fSYS=1ꢃ�Hz
fS=fSUB=fRTC oꢀ fLIRC
)
ꢅV
5V
ꢅV
5V
—
—
—
—
1.ꢅ
ꢃ.ꢃ
1.ꢅ
ꢃ.ꢃ
5.0
10.0
5.0
μA
μA
μA
μA
Standby Cuꢀꢀent (SLEEP1)
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=1ꢃ�Hz
ISTB11
(HXTꢄ fSYS=offꢄ fS=fSUB=fRTC
)
Standby Cuꢀꢀent (SLEEP1)
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=1ꢃ�Hz
ISTB1ꢃ
(HXTꢄ fSYS=offꢄ fS=fSUB=fLIRC
)
10.0
Standby Cuꢀꢀent (SLEEP0)
(LXTꢄ fSYS=offꢄ
ꢅV
5V
—
—
0.1
0.ꢅ
1
ꢃ
μA
μA
No loadꢄ system HALTꢄ ADC offꢄ
WDT disableꢄ fSYS=ꢅꢃ768Hz
ISTB1ꢅ
ISTB14
ISTB15
fS=fSUB=fLIRC oꢀ fRTC
)
ꢅV
5V
—
—
1.ꢅ
ꢃ.ꢃ
5.0
μA
μA
Standby Cuꢀꢀent (SLEEP1)
No loadꢄ system HALTꢄ ADC offꢄ
WDT enableꢄ fSYS=ꢅꢃ768Hz
(LXTꢄ fSYS=offꢄ fS=fSUB=fRTC
)
10.0
Stanby Cuꢀꢀent (SLEEP)
(HXTꢄ fSYS=offꢄ
No loadꢄ system HALTꢄ ADC offꢄ
WDT disableꢄ fSYS=1ꢃ�Hzꢄ
LVR enable and LVDEN=1
—
—
60
90
μA
fS=fSUB=fRTC oꢀ fLIRC
)
5
0
0
—
—
—
—
—
—
1.5
0.ꢃVDD
5
V
V
V
V
V
V
Input Low Voltage foꢀ I/O
poꢀt exꢁept RES pin
VIL1
VIH1
—
—
—
5
ꢅ.5
Input Higꢂ Voltage foꢀ I/O
poꢀt exꢁept RES pin
—
—
—
0.8VDD
0
VDD
VILꢃ
VIHꢃ
Input Low Voltage (RES)
Input Higꢂ Voltage (RES)
—
—
0.4VDD
VDD
0.9VDD
VDD/ꢃ voltage foꢀ LCD
CO�n
VSCO�
IOL
ꢃ.5V~5.5V No load
0.475 0.500 0.5ꢃ5
VDD
ꢅV
5V
ꢅV
5V
ꢅV
5V
VOL=0.1VDD
4
8
—
—
mA
mA
mA
mA
kΩ
I/O Poꢀt Sink Cuꢀꢀent
VOL=0.1VDD
VOH=0.9VDD
VOH=0.9VDD
10
-ꢃ
ꢃ0
-4
—
IOH
I/O Poꢀt Souꢀꢁe Cuꢀꢀent
-5
-10
60
ꢅ0
—
—
—
ꢃ0
10
100
50
Pull-ꢂigꢂ Resistanꢁe of I/O
Poꢀts
RPH
kΩ
Rev. 1.00
ꢃ0
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
A.C. Characteristics
Ta=ꢃ5°C
Test Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VDD
Condition
ꢃ.ꢃ~5.5V
ꢃ.7~5.5V
4.5~5.5V
0.4
0.4
0.4
-ꢃ%
-ꢃ%
—
—
—
8
�Hz
fSYS1
System ꢁloꢁk (HXT)
—
1ꢃ �Hz
16 �Hz
+ꢃ% �Hz
+ꢃ% �Hz
—
fSYSꢃ
fSYSꢅ
fSYS4
fSYS5
System ꢁloꢁk (ERC)
System ꢁloꢁk (HIRC)
System Cloꢁk (LXT)
System Cloꢁk (LIRC)
5V Ta=ꢃ5°Cꢄ Exteꢀnal RERC=1ꢃ0kΩ
8
5V Ta=ꢃ5°C
8
—
—
ꢅꢃ768
ꢅꢃ
—
Hz
5V Ta=ꢃ5°C
-ꢅ%
+ꢅ% kHz
TCKn and timeꢀ ꢁaptuꢀe Input Pulse
Widtꢂ
tTI�ER
—
—
0.ꢅ
—
—
μs
tRES
tINT
Exteꢀnal Reset Low Pulse Widtꢂ
Inteꢀꢀupt Pulse Widtꢂ
—
—
—
—
10
10
—
—
—
—
μs
μs
fSYS=HXT oꢀ LXT
→
(Slow �ode Noꢀmal �ode(HXT)ꢄ 10ꢃ4
—
—
—
—
tSYS
System Staꢀt-up Timeꢀ Peꢀiod
(Wake-up fꢀom HALTꢄ
→
Noꢀmal �ode Slow �ode(LXT))
—
fSYS=HXT oꢀ LXT
(Wake-up fꢀom HALTꢄ
fSYS off at HALT state)
fSYS off at HALT stateꢄ
10ꢃ4
tSYS
→ꢀ
Slow �ode
Noꢀmal �odeꢄ
→
Noꢀmal �ode
Slow �ode)
tSST
—
—
fSYS=ERC oꢀ HIRC
fSYS=LIRC
16
ꢃ
—
—
—
—
tSYS
tSYS
System Staꢀt-up Timeꢀ Peꢀiod
(Wake-up fꢀom HALTꢄ
fSYS on at HALT state)
—
—
—
—
—
—
ꢃ
—
—
50
—
—
tSYS
tSYS
System Staꢀt-up Timeꢀ Peꢀiod (Reset)
10ꢃ4
ꢃ5
System Reset Delay Time
(Poweꢀ On Resetꢄ LVR ꢀesetꢄ LVRC
softwaꢀe ꢀesetꢄ WDTC softwaꢀe ꢀeset)
100 ms
tRSTD
System Reset Delay Time
(RES ꢀesetꢄ WDT noꢀmal ꢀeset)
—
—
8.ꢅ
16.7 ꢅꢅ.ꢅ ms
tEERD
tEEWR
EEPRO� Read Time
EEPRO� Wꢀite Timet
—
—
—
—
1
1
ꢃ
ꢃ
4
4
tSYS
ms
Note: tSYS=1/fSYS
Rev. 1.00
ꢃ1
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
A/D Converter Characteristics
Ta=25˚C
Test Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VDD
—
Condition
VADI
A/D Conveꢀteꢀ Input Voltage
A/D Conveꢀteꢀ Refeꢀenꢁe Voltage
Diffeꢀential non-lineaꢀity
—
—
0
ꢃ
—
—
VREF
AVDD
+ꢅ
V
V
VREF
DNL
INL
—
5V
5V
ꢅV
5V
—
tADCK=0.5μs
tADCK=0.5μs
No load (tADCK=0.5μs )
No load (tADCK=0.5μs )
—
-ꢅ
-4
—
—
0.5
—
LSB
LSB
mA
mA
μs
Integꢀal non-lineaꢀity
—
+4
1.0
1.5
—
ꢃ.0
Additional Poweꢀ Consumption if A/D
Conveꢀteꢀ is used
IADC
ꢅ.0
tADCK
tADC
A/D Conveꢀteꢀ Cloꢁk Peꢀiod
100
A/D Conveꢀsion Time
(Inꢁlude Sample and Hold Time)
—
1ꢃ bit A/D Conveꢀteꢀ
—
16
—
tADCK
tADS
A/D Conveꢀteꢀ Sampling Time
A/D Conveꢀteꢀ On-to-Staꢀt Time
—
—
—
—
—
ꢃ
4
—
—
tADCK
tONꢃST
—
μs
LVD & LVR Electrical Characteristics
Ta=ꢃ5°C
Test Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VDD
Conditions
LVR Enableꢄ ꢃ.1V option
LVR Enableꢄ ꢃ.55V option
LVR Enableꢄ ꢅ.15V option
LVR Enableꢄ ꢅ.8V option
LVDEN=1ꢄ VLVD=ꢃ.0V
LVDEN=1ꢄ VLVD=ꢃ.ꢃV
LVDEN=1ꢄ VLVD=ꢃ.4V
LVDEN=1ꢄ VLVD=ꢃ.7V
LVDEN=1ꢄ VLVD=ꢅ.0V
LVDEN=1ꢄ VLVD=ꢅ.ꢅV
LVDEN=1ꢄ VLVD=ꢅ.6V
LVDEN=1ꢄ VLVD=4.0V
—
VLVR1
VLVRꢃ
VLVRꢅ
VLVR4
VLVD1
VLVDꢃ
VLVDꢅ
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VBG
ꢃ.1
ꢃ.55
Low Voltage Reset Voltage
—
—
-5%
+5%
+5%
V
ꢅ.15
ꢅ.8
ꢃ.0
ꢃ.ꢃ
ꢃ.4
ꢃ.7
ꢅ.0
ꢅ.ꢅ
ꢅ.6
4.0
V
V
V
V
V
V
V
V
V
Low Voltage Deteꢁtoꢀ Voltage
-5%
Bandgap ꢀefeꢀenꢁe witꢂ buffeꢀ voltage
—
-ꢅ% 1.ꢃ5 +ꢅ%
Additional Poweꢀ Consumption if bandgap
ꢀefeꢀenꢁe witꢂ buffeꢀ is used
IBG
─
─
—
ꢃ00 ꢅ00 μA
ꢅV
5V
ꢅV
5V
ꢅV
5V
─
—
—
ꢅ0
60
40
45
90
60
μA
μA
μA
ILVR
Additional Poweꢀ Consumption if LVR is used
LVR disable→LVR enable
—
LVD disable→LVD enable
(LVR disable)
—
75 115 μA
ILVD
Additional Poweꢀ Consumption if LVD is used
—
ꢅ0
60
─
45
90
─
μA
μA
ms
LVD disable→LVD enable
(LVR enable)
—
tBGS
tLVR
tLVD
VBG tuꢀn on stable time
─
10
1ꢃ0
ꢃ0
Low Voltage Widtꢂ to Reset
Low Voltage Widtꢂ to Inteꢀꢀupt
—
—
—
—
—
—
—
—
45
—
—
480 μs
90
—
—
μs
μs
μs
For LVR enable, LVD off→on 15
For LVR disable, LVD off→on 15
tLVDS
LVDO stable time
tSRESET
Softwaꢀe Reset Widtꢂ to Reset
—
45
90 1ꢃ0 μs
Rev. 1.00
ꢃꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Comparator Electrical Characteristics
Ta=25˚C
Test Conditions
Symbol
Parameter
Min. Typ.
Max.
Unit
VDD
—
Condition
VC�P
IC�P
Compaꢀatoꢀ opeꢀating voltage
Compaꢀatoꢀ opeꢀating ꢁuꢀꢀent
—
—
—
—
ꢃ.ꢃ
—
—
50
85
—
40
—
80
5.5
75
V
ꢅV
5V
—
μA
μA
mV
mV
—
1ꢅ0
+10
60
VC�POS Compaꢀatoꢀ input offset voltage
-10
ꢃ0
VHYS
VC�
AOL
Hysteꢀesis widtꢂ
—
Compaꢀatoꢀ ꢁommon mode voltage ꢀange
Compaꢀatoꢀ open loop gain
—
—
—
VSS
60
VDD-1.4V
—
V
—
dB
ꢅV
5V
tPD
Compaꢀatoꢀ ꢀesponse time
Witꢂ 100mV oveꢀdꢀive(Note)
—
ꢃ00
400
ns
Note:ꢀMeasuredꢀwithꢀcomparatorꢀoneꢀinputꢀpinꢀatꢀVCM=(VDD-1.4)/2ꢀwhileꢀtheꢀotherꢀpinꢀinputꢀtransitionꢀfromꢀVSSꢀtoꢀ
(VCM+100mV)ꢀorꢀfromꢀVDDꢀtoꢀ(VCM-100mV).
Power on Reset Electrical Characteristics
Ta=25˚C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
—
Condition
VPOR
VDD Staꢀt Voltage to ensuꢀe Poweꢀ-on Reset
—
—
—
—
—
100
—
mV
RRVDD VDD Rise Rate to ensuꢀe Poweꢀ-on Reset
—
0.0ꢅ5
V/ms
�inimum Time foꢀ VDD to ꢀemain at VPOR to
ensuꢀe Poweꢀ-on Reset
tPOR
—
—
1
—
—
ms
V
D
D
t
P
R
O
R
V
R
D
D
V
P
R
O
T
m
i
Rev. 1.00
ꢃꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
System Architecture
Aꢀkeyꢀfactorꢀinꢀtheꢀhigh-performanceꢀfeaturesꢀofꢀtheꢀHoltekꢀrangeꢀofꢀmicrocontrollersꢀisꢀattributedꢀ
toꢀtheirꢀinternalꢀsystemꢀarchitecture.ꢀTheꢀrangeꢀofꢀdevicesꢀtakeꢀadvantageꢀofꢀtheꢀusualꢀfeaturesꢀfoundꢀ
withinꢀRISCꢀmicrocontrollersꢀprovidingꢀincreasedꢀspeedꢀofꢀoperationꢀandꢀenhancedꢀperformance.ꢀ
Theꢀpipeliningꢀschemeꢀisꢀimplementedꢀinꢀsuchꢀaꢀwayꢀthatꢀinstructionꢀfetchingꢀandꢀinstructionꢀ
executionꢀareꢀoverlapped,ꢀhenceꢀinstructionsꢀareꢀeffectivelyꢀexecutedꢀinꢀoneꢀcycle,ꢀwithꢀtheꢀ
exceptionꢀofꢀbranchꢀorꢀcallꢀinstructions.ꢀAnꢀ8-bitꢀwideꢀALUꢀisꢀusedꢀinꢀpracticallyꢀallꢀinstructionꢀsetꢀ
operations,ꢀwhichꢀcarriesꢀoutꢀarithmeticꢀoperations,ꢀlogicꢀoperations,ꢀrotation,ꢀincrement,ꢀdecrement,ꢀ
branchꢀdecisions,ꢀetc.ꢀTheꢀinternalꢀdataꢀpathꢀisꢀsimplifiedꢀbyꢀmovingꢀdataꢀthroughꢀtheꢀAccumulatorꢀ
andꢀtheꢀALU.ꢀCertainꢀinternalꢀregistersꢀareꢀimplementedꢀinꢀtheꢀDataꢀMemoryꢀandꢀcanꢀbeꢀdirectlyꢀ
orꢀindirectlyꢀaddressed.ꢀTheꢀsimpleꢀaddressingꢀmethodsꢀofꢀtheseꢀregistersꢀalongꢀwithꢀadditionalꢀ
architecturalꢀfeaturesꢀensureꢀthatꢀaꢀminimumꢀofꢀexternalꢀcomponentsꢀisꢀrequiredꢀtoꢀprovideꢀaꢀ
functionalꢀI/OꢀandꢀA/Dꢀcontrolꢀsystemꢀwithꢀmaximumꢀreliabilityꢀandꢀflexibility.ꢀThisꢀmakesꢀtheseꢀ
devicesꢀsuitableꢀforꢀlow-cost,ꢀhigh-volumeꢀproductionꢀforꢀcontrollerꢀapplications.
Clocking and Pipelining
Theꢀmainꢀsystemꢀclock,ꢀderivedꢀfromꢀeitherꢀaꢀHXT,ꢀLXT,ꢀHIRC,ꢀLIRCꢀorꢀERCꢀoscillatorꢀisꢀ
subdividedꢀꢀintoꢀfourꢀinternallyꢀgeneratedꢀnon-overlappingꢀclocks,ꢀT1~T4.ꢀTheꢀProgramꢀCounterꢀisꢀ
incrementedꢀatꢀtheꢀbeginningꢀofꢀtheꢀT1ꢀclockꢀduringꢀwhichꢀtimeꢀaꢀnewꢀinstructionꢀisꢀfetched.ꢀTheꢀ
remainingꢀT2~T4ꢀclocksꢀcarryꢀoutꢀtheꢀdecodingꢀandꢀexecutionꢀfunctions.ꢀInꢀthisꢀway,ꢀoneꢀT1~T4ꢀ
clockꢀcycleꢀformsꢀoneꢀinstructionꢀcycle.ꢀAlthoughꢀtheꢀfetchingꢀandꢀexecutionꢀofꢀinstructionsꢀtakesꢀ
placeꢀinꢀconsecutiveꢀinstructionꢀcycles,ꢀtheꢀpipeliningꢀstructureꢀofꢀtheꢀmicrocontrollerꢀensuresꢀthatꢀ
instructionsꢀareꢀeffectivelyꢀexecutedꢀinꢀoneꢀinstructionꢀcycle.ꢀTheꢀexceptionꢀtoꢀthisꢀareꢀinstructionsꢀ
whereꢀtheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀareꢀchanged,ꢀsuchꢀasꢀsubroutineꢀcallsꢀorꢀjumps,ꢀinꢀwhichꢀ
caseꢀtheꢀinstructionꢀwillꢀtakeꢀoneꢀmoreꢀinstructionꢀcycleꢀtoꢀexecute.
Forꢀinstructionsꢀinvolvingꢀbranches,ꢀsuchꢀasꢀjumpꢀorꢀcallꢀinstructions,ꢀtwoꢀmachineꢀcyclesꢀareꢀ
requiredꢀtoꢀcompleteꢀinstructionꢀexecution.ꢀAnꢀextraꢀcycleꢀisꢀrequiredꢀasꢀtheꢀprogramꢀtakesꢀoneꢀ
cycleꢀtoꢀfirstꢀobtainꢀtheꢀactualꢀjumpꢀorꢀcallꢀaddressꢀandꢀthenꢀanotherꢀcycleꢀtoꢀactuallyꢀexecuteꢀtheꢀ
branch.ꢀTheꢀrequirementꢀforꢀthisꢀextraꢀcycleꢀshouldꢀbeꢀtakenꢀintoꢀaccountꢀbyꢀprogrammersꢀinꢀtimingꢀ
sensitiveꢀapplications.
f
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Y
(
y
S
e
s
t
m
C
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c
o
k
)
P
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a
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C
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T
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1
P
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a
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C
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c
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T
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2
P
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a
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C
s
o
c
l
T
k
3
P
h
a
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C
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o
c
l
T
k
4
P
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g
a
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m
C
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+
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1
P
+
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2
F
t
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h
c
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t
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)
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p
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(
C
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-
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F
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P
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E
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(
C
P
1
+
)
System Clocking and Pipelining
Rev. 1.00
ꢃ4
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
F
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Instruction Fetching
Program Counter
Duringꢀprogramꢀexecution,ꢀtheꢀProgramꢀCounterꢀisꢀusedꢀtoꢀkeepꢀtrackꢀofꢀtheꢀaddressꢀofꢀtheꢀ
nextꢀinstructionꢀtoꢀbeꢀexecuted.ꢀItꢀisꢀautomaticallyꢀincrementedꢀbyꢀoneꢀeachꢀtimeꢀanꢀinstructionꢀ
isꢀexecutedꢀexceptꢀforꢀinstructions,ꢀsuchꢀasꢀ“JMP”ꢀorꢀ“CALL”ꢀthatꢀdemandꢀaꢀjumpꢀtoꢀaꢀ
non-consecutiveꢀProgramꢀMemoryꢀaddress.ꢀOnlyꢀtheꢀlowerꢀ8ꢀbits,ꢀknownꢀasꢀtheꢀProgramꢀCounterꢀ
LowꢀRegister,ꢀareꢀdirectlyꢀaddressableꢀbyꢀtheꢀapplicationꢀprogram.
Whenꢀexecutingꢀinstructionsꢀrequiringꢀjumpsꢀtoꢀnon-consecutiveꢀaddressesꢀsuchꢀasꢀaꢀjumpꢀ
instruction,ꢀaꢀsubroutineꢀcall,ꢀinterruptꢀorꢀreset,ꢀetc.,ꢀtheꢀmicrocontrollerꢀmanagesꢀprogramꢀcontrolꢀ
byꢀloadingꢀtheꢀrequiredꢀaddressꢀintoꢀtheꢀProgramꢀCounter.ꢀForꢀconditionalꢀskipꢀinstructions,ꢀonceꢀ
theꢀconditionꢀhasꢀbeenꢀmet,ꢀtheꢀnextꢀinstruction,ꢀwhichꢀhasꢀalreadyꢀbeenꢀfetchedꢀduringꢀtheꢀpresentꢀ
instructionꢀexecution,ꢀisꢀdiscardedꢀandꢀaꢀdummyꢀcycleꢀtakesꢀitsꢀplaceꢀwhileꢀtheꢀcorrectꢀinstructionꢀisꢀ
obtained.
Program Counter
Device
Porgram Counter High Byte
Porgram Counter Low Byte
HT66F60A
HT66F70A
PC1ꢅ~PC8
PCL7~PCL0
PC14~PC8
Program Counter
TheꢀlowerꢀbyteꢀofꢀtheꢀProgramꢀCounter,ꢀknownꢀasꢀtheꢀProgramꢀCounterꢀLowꢀregisterꢀorꢀPCL,ꢀisꢀ
availableꢀforꢀprogramꢀcontrolꢀandꢀisꢀaꢀreadableꢀandꢀwriteableꢀregister.ꢀByꢀtransferringꢀdataꢀdirectlyꢀ
intoꢀthisꢀregister,ꢀaꢀshortꢀprogramꢀjumpꢀcanꢀbeꢀexecutedꢀdirectly;ꢀhowever,ꢀasꢀonlyꢀthisꢀlowꢀbyteꢀ
isꢀavailableꢀforꢀmanipulation,ꢀtheꢀjumpsꢀareꢀlimitedꢀtoꢀtheꢀpresentꢀpageꢀofꢀmemory,ꢀthatꢀisꢀ256ꢀ
locations.ꢀWhenꢀsuchꢀprogramꢀjumpsꢀareꢀexecutedꢀitꢀshouldꢀalsoꢀbeꢀnotedꢀthatꢀaꢀdummyꢀcycleꢀ
willꢀbeꢀinserted.ꢀManipulatingꢀtheꢀPCLꢀregisterꢀmayꢀcauseꢀprogramꢀbranching,ꢀsoꢀanꢀextraꢀcycleꢀisꢀ
neededꢀtoꢀpre-fetch.
Rev. 1.00
ꢃ5
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Stack
ThisꢀisꢀaꢀspecialꢀpartꢀofꢀtheꢀmemoryꢀwhichꢀisꢀusedꢀtoꢀsaveꢀtheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀ
only.ꢀTheꢀstackꢀhasꢀmultipleꢀlevelsꢀandꢀisꢀneitherꢀpartꢀofꢀtheꢀdataꢀnorꢀpartꢀofꢀtheꢀprogramꢀspace,ꢀ
andꢀisꢀneitherꢀreadableꢀnorꢀwriteable.ꢀTheꢀactivatedꢀlevelꢀisꢀindexedꢀbyꢀtheꢀStackꢀPointer,ꢀandꢀisꢀ
neitherꢀreadableꢀnorꢀwriteable.ꢀAtꢀaꢀsubroutineꢀcallꢀorꢀinterruptꢀacknowledgeꢀsignal,ꢀtheꢀcontentsꢀofꢀ
theꢀProgramꢀCounterꢀareꢀpushedꢀontoꢀtheꢀstack.ꢀAtꢀtheꢀendꢀofꢀaꢀsubroutineꢀorꢀanꢀinterruptꢀroutine,ꢀ
signaledꢀbyꢀaꢀreturnꢀinstruction,ꢀRETꢀorꢀRETI,ꢀtheꢀProgramꢀCounterꢀisꢀrestoredꢀtoꢀitsꢀpreviousꢀvalueꢀ
fromꢀtheꢀstack.ꢀAfterꢀaꢀdeviceꢀreset,ꢀtheꢀStackꢀPointerꢀwillꢀpointꢀtoꢀtheꢀtopꢀofꢀtheꢀstack.
Ifꢀtheꢀstackꢀisꢀfullꢀandꢀanꢀenabledꢀinterruptꢀtakesꢀplace,ꢀtheꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀrecordedꢀbutꢀ
theꢀacknowledgeꢀsignalꢀwillꢀbeꢀinhibited.ꢀWhenꢀtheꢀStackꢀPointerꢀisꢀdecremented,ꢀbyꢀRETꢀorꢀRETI,ꢀ
theꢀinterruptꢀwillꢀbeꢀserviced.ꢀThisꢀfeatureꢀpreventsꢀstackꢀoverflowꢀallowingꢀtheꢀprogrammerꢀtoꢀuseꢀ
theꢀstructureꢀmoreꢀeasily.ꢀHowever,ꢀwhenꢀtheꢀstackꢀisꢀfull,ꢀaꢀCALLꢀsubroutineꢀinstructionꢀcanꢀstillꢀ
beꢀexecutedꢀwhichꢀwillꢀresultꢀinꢀaꢀstackꢀoverflow.ꢀPrecautionsꢀshouldꢀbeꢀtakenꢀtoꢀavoidꢀsuchꢀcasesꢀ
whichꢀmightꢀcauseꢀunpredictableꢀprogramꢀbranching.
Ifꢀtheꢀstackꢀisꢀoverflow,ꢀtheꢀfirstꢀProgramꢀCounterꢀsaveꢀinꢀtheꢀstackꢀwillꢀbeꢀlost.
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6
Arithmetic and Logic Unit – ALU
Theꢀarithmetic-logicꢀunitꢀorꢀALUꢀisꢀaꢀcriticalꢀareaꢀofꢀtheꢀmicrocontrollerꢀthatꢀcarriesꢀoutꢀarithmeticꢀ
andꢀlogicꢀoperationsꢀofꢀtheꢀinstructionꢀset.ꢀConnectedꢀtoꢀtheꢀmainꢀmicrocontrollerꢀdataꢀbus,ꢀtheꢀALUꢀ
receivesꢀrelatedꢀinstructionꢀcodesꢀandꢀperformsꢀtheꢀrequiredꢀarithmeticꢀorꢀlogicalꢀoperationsꢀafterꢀ
whichꢀtheꢀresultꢀwillꢀbeꢀplacedꢀinꢀtheꢀspecifiedꢀregister.ꢀAsꢀtheseꢀALUꢀcalculationꢀorꢀoperationsꢀmayꢀ
resultꢀinꢀcarry,ꢀborrowꢀorꢀotherꢀstatusꢀchanges,ꢀtheꢀstatusꢀregisterꢀwillꢀbeꢀcorrespondinglyꢀupdatedꢀtoꢀ
reflectꢀtheseꢀchanges.ꢀTheꢀALUꢀsupportsꢀtheꢀfollowingꢀfunctions:
•ꢀ Arithmeticꢀoperations:ꢀ
ADD,ꢀADDM,ꢀADC,ꢀADCM,ꢀSUB,ꢀSUBM,ꢀSBC,ꢀSBCM,ꢀDAA,
LADD,ꢀLADDM,ꢀLADC,ꢀLADCM,ꢀLSUB,ꢀLSUBM,ꢀLSBC,ꢀLSBCM,ꢀLDAA
•ꢀ Logicꢀoperations:
AND,ꢀOR,ꢀXOR,ꢀANDM,ꢀORM,ꢀXORM,ꢀCPL,ꢀCPLA,
LAND,ꢀLOR,ꢀLXOR,ꢀLANDM,ꢀLORM,ꢀLXORM,ꢀLCPL,ꢀLCPLA
•ꢀ Rotation:
RRA,ꢀRR,ꢀRRCA,ꢀRRC,ꢀRLA,ꢀRL,ꢀRLCA,ꢀRLC,
LRRA,ꢀLRR,ꢀLRRCA,ꢀLRRC,ꢀLRLA,ꢀLRL,ꢀLRLCA,ꢀLRLC
•ꢀ IncrementꢀandꢀDecrement:ꢀ
INCA,ꢀINC,ꢀDECA,ꢀDEC,ꢀLINCA,ꢀLINC,ꢀLDECA,ꢀLDEC
•ꢀ Branchꢀdecision:
JMP,ꢀCALL,ꢀRET,ꢀRETI,ꢀSZ,ꢀSZA,ꢀSNZ,ꢀSIZ,ꢀSDZ,ꢀSIZA,ꢀSDZA,
LSZ,ꢀLSZA,ꢀLSNZ,ꢀLSIZ,ꢀLSDZ,ꢀLSIZA,ꢀLSDZA
Rev. 1.00
ꢃ6
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Flash Program Memory
TheꢀProgramꢀMemoryꢀisꢀtheꢀlocationꢀwhereꢀtheꢀuserꢀcodeꢀorꢀprogramꢀisꢀstored.ꢀForꢀtheseꢀdevicesꢀ
seriesꢀtheꢀProgramꢀMemoryꢀareꢀFlashꢀtype,ꢀwhichꢀmeansꢀitꢀcanꢀbeꢀprogrammedꢀandꢀre-programmedꢀ
aꢀlargeꢀnumberꢀofꢀtimes,ꢀallowingꢀtheꢀuserꢀtheꢀconvenienceꢀofꢀcodeꢀmodificationꢀonꢀtheꢀsameꢀ
device.ꢀByꢀusingꢀtheꢀappropriateꢀprogrammingꢀtools,ꢀtheseꢀFlashꢀdevicesꢀofferꢀusersꢀtheꢀflexibilityꢀtoꢀ
convenientlyꢀdebugꢀandꢀdevelopꢀtheirꢀapplicationsꢀwhileꢀalsoꢀofferingꢀaꢀmeansꢀofꢀfieldꢀprogrammingꢀ
andꢀupdating.
Structure
TheꢀProgramꢀMemoryꢀhasꢀaꢀcapacityꢀofꢀ16K×16ꢀbitsꢀtoꢀ32K×16ꢀbits.ꢀTheꢀProgramꢀMemoryꢀisꢀ
addressedꢀbyꢀtheꢀProgramꢀCounterꢀandꢀalsoꢀcontainsꢀdata,ꢀtableꢀinformationꢀandꢀinterruptꢀentriesꢀ
information.ꢀTableꢀdata,ꢀwhichꢀcanꢀbeꢀsetupꢀinꢀanyꢀlocationꢀwithinꢀtheꢀProgramꢀMemory,ꢀisꢀ
addressedꢀbyꢀseparateꢀtableꢀpointerꢀregisters.
Device
Capacity
16K × 16
ꢅꢃK × 16
Banks
0~1
HT66F60A
HT66F70A
0~ꢅ
TheꢀseriesꢀofꢀdevicesꢀhasꢀitsꢀProgramꢀMemoryꢀdividedꢀintoꢀtwoꢀorꢀfourꢀBanks,ꢀBankꢀ0~Bankꢀ1ꢀorꢀ
Bankꢀ0~Bankꢀ3ꢀrespectively.ꢀTheꢀrequiredꢀBankꢀisꢀselectedꢀusingꢀBitꢀ0ꢀorꢀBitꢀ0~1ꢀofꢀtheꢀBPꢀRegisterꢀ
dependentꢀuponꢀwhichꢀdeviceꢀisꢀselected.
HT66F60A HT66F70A
0000H
0004H
Reset
Reset
Inteꢀꢀupt
Veꢁtoꢀ
Inteꢀꢀupt
Veꢁtoꢀ
00ꢅ8H
16 bits
Bank 1
16 bits
Bank 1
1FFFH
ꢃ000H
ꢅFFFH
4000H
Bank ꢃ
Bank ꢅ
5FFFH
6000H
7FFFH
Program Memory Structure
Rev. 1.00
ꢃ7
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Special Vectors
WithinꢀtheꢀProgramꢀMemory,ꢀcertainꢀlocationsꢀareꢀreservedꢀforꢀtheꢀresetꢀandꢀinterrupts.ꢀTheꢀlocationꢀ
0000Hꢀisꢀreservedꢀforꢀuseꢀbyꢀtheseꢀdevicesꢀresetꢀforꢀprogramꢀinitialisation.ꢀAfterꢀaꢀdeviceꢀresetꢀisꢀ
initiated,ꢀtheꢀprogramꢀwillꢀjumpꢀtoꢀthisꢀlocationꢀandꢀbeginꢀexecution.
Look-up Table
AnyꢀlocationꢀwithinꢀtheꢀProgramꢀMemoryꢀcanꢀbeꢀdefinedꢀasꢀaꢀlook-upꢀtableꢀwhereꢀprogrammersꢀcanꢀ
storeꢀfixedꢀdata.ꢀToꢀuseꢀtheꢀlook-upꢀtable,ꢀtheꢀtableꢀpointerꢀmustꢀfirstꢀbeꢀsetupꢀbyꢀplacingꢀtheꢀaddressꢀ
ofꢀtheꢀlookꢀupꢀdataꢀtoꢀbeꢀretrievedꢀinꢀtheꢀtableꢀpointerꢀregister,ꢀTBLPꢀandꢀTBHP.ꢀTheseꢀregistersꢀ
defineꢀtheꢀtotalꢀaddressꢀofꢀtheꢀlook-upꢀtable.
Afterꢀsettingꢀupꢀtheꢀtableꢀpointer,ꢀtheꢀtableꢀdataꢀcanꢀbeꢀretrievedꢀfromꢀtheꢀProgramꢀMemoryꢀusingꢀ
theꢀ“TABRD[m]”ꢀorꢀ“TABRDL[m]”ꢀinstructionsꢀrespectivelyꢀwhenꢀtheꢀmemoryꢀ[m]ꢀisꢀlocatedꢀ
inꢀcurrentꢀpage.ꢀIfꢀtheꢀmemoryꢀ[m]ꢀisꢀlocatedꢀinꢀotherꢀpages,ꢀtheꢀdataꢀcanꢀbeꢀretrievedꢀfromꢀtheꢀ
programꢀmemoryꢀusingꢀtheꢀ“LTABRD[m]”ꢀorꢀ“LTABRDL[m]”ꢀinstructionsꢀrespectively.ꢀWhenꢀtheꢀ
instructionꢀisꢀexecuted,ꢀtheꢀlowerꢀorderꢀtableꢀbyteꢀfromꢀtheꢀProgramꢀMemoryꢀwillꢀbeꢀtransferredꢀtoꢀ
theꢀuserꢀdefinedꢀDataꢀMemoryꢀregisterꢀ[m]ꢀasꢀspecifiedꢀinꢀtheꢀinstruction.ꢀTheꢀhigherꢀorderꢀtableꢀdataꢀ
byteꢀfromꢀtheꢀProgramꢀMemoryꢀwillꢀbeꢀtransferredꢀtoꢀtheꢀTBLHꢀspecialꢀregister.
Theꢀaccompanyingꢀdiagramꢀillustratesꢀtheꢀaddressingꢀdataꢀflowꢀofꢀtheꢀlook-upꢀtable.
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Rev. 1.00
ꢃ8
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Table Program Example
Theꢀaccompanyingꢀexampleꢀshowsꢀhowꢀtheꢀtableꢀpointerꢀandꢀtableꢀdataꢀisꢀdefinedꢀandꢀretrievedꢀfromꢀ
theꢀdevice.ꢀThisꢀexampleꢀusesꢀrawꢀtableꢀdataꢀlocatedꢀinꢀtheꢀlastꢀpageꢀwhichꢀisꢀstoredꢀthereꢀusingꢀtheꢀ
ORGꢀstatement.ꢀTheꢀvalueꢀatꢀthisꢀORGꢀstatementꢀisꢀ“3F00H”ꢀwhichꢀrefersꢀtoꢀtheꢀstartꢀaddressꢀofꢀtheꢀ
lastꢀpageꢀwithinꢀtheꢀ16KꢀProgramꢀMemoryꢀofꢀtheꢀHT66F60Aꢀdevice.ꢀTheꢀtableꢀpointerꢀisꢀsetupꢀhereꢀ
toꢀhaveꢀanꢀinitialꢀvalueꢀofꢀ“06H”.ꢀThisꢀwillꢀensureꢀthatꢀtheꢀfirstꢀdataꢀreadꢀfromꢀtheꢀdataꢀtableꢀwillꢀbeꢀ
atꢀtheꢀProgramꢀMemoryꢀaddressꢀ“3F06H”ꢀorꢀ6ꢀlocationsꢀafterꢀtheꢀstartꢀofꢀtheꢀlastꢀpage.ꢀNoteꢀthatꢀtheꢀ
valueꢀforꢀtheꢀtableꢀpointerꢀisꢀreferencedꢀtoꢀtheꢀfirstꢀaddressꢀofꢀtheꢀpresentꢀpageꢀifꢀtheꢀ“TABRDꢀ[m]”ꢀ
instructionꢀisꢀbeingꢀused.ꢀTheꢀhighꢀbyteꢀofꢀtheꢀtableꢀdataꢀwhichꢀinꢀthisꢀcaseꢀisꢀequalꢀtoꢀzeroꢀwillꢀbeꢀ
transferredꢀtoꢀtheꢀTBLHꢀregisterꢀautomaticallyꢀwhenꢀtheꢀ“TABRDꢀ[m]ꢀinstructionꢀisꢀexecuted.
BecauseꢀtheꢀTBLHꢀregisterꢀisꢀaꢀread-onlyꢀregisterꢀandꢀcannotꢀbeꢀrestored,ꢀcareꢀshouldꢀbeꢀtakenꢀ
toꢀensureꢀitsꢀprotectionꢀifꢀbothꢀtheꢀmainꢀroutineꢀandꢀInterruptꢀServiceꢀRoutineꢀuseꢀtableꢀreadꢀ
instructions.ꢀIfꢀusingꢀtheꢀtableꢀreadꢀinstructions,ꢀtheꢀInterruptꢀServiceꢀRoutinesꢀmayꢀchangeꢀtheꢀ
valueꢀofꢀtheꢀTBLHꢀandꢀsubsequentlyꢀcauseꢀerrorsꢀifꢀusedꢀagainꢀbyꢀtheꢀmainꢀroutine.ꢀAsꢀaꢀruleꢀitꢀisꢀ
recommendedꢀthatꢀsimultaneousꢀuseꢀofꢀtheꢀtableꢀreadꢀinstructionsꢀshouldꢀbeꢀavoided.ꢀHowever,ꢀinꢀ
situationsꢀwhereꢀsimultaneousꢀuseꢀcannotꢀbeꢀavoided,ꢀtheꢀinterruptsꢀshouldꢀbeꢀdisabledꢀpriorꢀtoꢀtheꢀ
executionꢀofꢀanyꢀmainꢀroutineꢀtable-readꢀinstructions.ꢀNoteꢀthatꢀallꢀtableꢀrelatedꢀinstructionsꢀrequireꢀ
twoꢀinstructionꢀcyclesꢀtoꢀcompleteꢀtheirꢀoperation.
Table Read Program Example:
tempreg1 db ?
tempreg2 db ?
; temporary register #1 in current page
; temporary register #2 in current page
:
:
mov a,06h
; initialise low byte table pointer - note that this address
; is referenced
mov tblp, a
; to the last page or present page
:
:
tabrdl tempreg1
; transfers value in table referenced by table pointer to tempreg1
; Data at program memory address “3F06H” transferred to tempreg1
; and TBLH
dec tblp
; reduce value of table pointer by one
tabrdl tempreg2
; transfers value in table referenced by table pointer to tempreg2
; Data at program memory address “3F05H” transferred to tempreg2
; and TBLH. In this example the data “1AH” is transferred to
; tempreg1 and data “0FH” to register tempreg2 while the value “00H”
; will be transferred to the high byte register TBLH
:
:
org 3F00h
; sets initial address of last page
dc 000Ah, 000Bh, 000Ch, 000Dh, 000Eh, 000Fh, 001Ah, 001Bh
:
:
Rev. 1.00
ꢃ9
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
In Circuit Programming – ICP
TheꢀprovisionꢀofꢀFlashꢀtypeꢀProgramꢀMemoryꢀprovidesꢀtheꢀuserꢀwithꢀaꢀmeansꢀofꢀconvenientꢀandꢀ
easyꢀupgradesꢀandꢀmodificationsꢀtoꢀtheirꢀprogramsꢀonꢀtheꢀsameꢀdevice.
Asꢀanꢀadditionalꢀconvenience,ꢀHoltekꢀhasꢀprovidedꢀaꢀmeansꢀofꢀprogrammingꢀtheꢀmicrocontrollerꢀ
in-circuitꢀusingꢀaꢀ4-pinꢀinterface.ꢀThisꢀprovidesꢀmanufacturersꢀwithꢀtheꢀpossibilityꢀofꢀmanufacturingꢀ
theirꢀcircuitꢀboardsꢀcompleteꢀwithꢀaꢀprogrammedꢀorꢀun-programmedꢀmicrocontroller,ꢀandꢀthenꢀ
programmingꢀorꢀupgradingꢀtheꢀprogramꢀatꢀaꢀlaterꢀstage.ꢀThisꢀenablesꢀproductꢀmanufacturersꢀtoꢀeasilyꢀ
keepꢀtheirꢀmanufacturedꢀproductsꢀsuppliedꢀwithꢀtheꢀlatestꢀprogramꢀreleasesꢀwithoutꢀremovalꢀandꢀ
re-insertionꢀofꢀtheꢀdevice.
Holtek Writer Pins
MCU Programming Pins
Pin Description
Pꢀogꢀamming Seꢀial Data
Pꢀogꢀamming Cloꢁk
Poweꢀ Supply
ICPDA
ICPCK
VDD
PA0
PAꢃ
VDD
VSS
VSS
Gꢀound
TheꢀProgramꢀMemoryꢀcanꢀbeꢀprogrammedꢀseriallyꢀin-circuitꢀusingꢀthisꢀ4-wireꢀinterface.ꢀDataꢀ
isꢀdownloadedꢀandꢀuploadedꢀseriallyꢀonꢀaꢀsingleꢀpinꢀwithꢀanꢀadditionalꢀlineꢀforꢀtheꢀclock.ꢀTwoꢀ
additionalꢀlinesꢀareꢀrequiredꢀforꢀtheꢀpowerꢀsupplyꢀandꢀoneꢀlineꢀforꢀtheꢀreset.ꢀTheꢀtechnicalꢀdetailsꢀ
regardingꢀtheꢀin-circuitꢀprogrammingꢀofꢀtheꢀdevicesꢀareꢀbeyondꢀtheꢀscopeꢀofꢀthisꢀdocumentꢀandꢀwillꢀ
beꢀsuppliedꢀinꢀsupplementaryꢀliterature.
Duringꢀtheꢀprogrammingꢀprocess,ꢀtheꢀuserꢀmustꢀtakeꢀcareꢀofꢀtheꢀICPDAꢀandꢀICPCKꢀpinsꢀforꢀdataꢀ
andꢀclockꢀprogrammingꢀpurposesꢀtoꢀensureꢀthatꢀnoꢀotherꢀoutputsꢀareꢀconnectedꢀtoꢀtheseꢀtwoꢀpins.
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A
2
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e
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S
V
S
S
*
*
T
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t
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Note:ꢀ*ꢀmayꢀbeꢀresistorꢀorꢀcapacitor.ꢀTheꢀresistanceꢀofꢀ*ꢀmustꢀbeꢀgreaterꢀ
thanꢀ1kꢀorꢀtheꢀcapacitanceꢀofꢀ*ꢀmustꢀbeꢀlessꢀthanꢀ1nF.
Rev. 1.00
ꢅ0
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
On-Chip Debug Support – OCDS
ThereꢀisꢀanꢀEVꢀchipꢀnamedꢀHT66V70AꢀwhichꢀisꢀusedꢀtoꢀemulateꢀtheꢀHT66Fx0Aꢀseriesꢀofꢀdevices.ꢀ
TheꢀHT66V70Aꢀdeviceꢀalsoꢀprovidesꢀtheꢀ“On-ChipꢀDebug”ꢀfunctionꢀtoꢀdebugꢀtheꢀHT66Fx0Aꢀ
seriesꢀofꢀdevicesꢀduringꢀdevelopmentꢀprocess.ꢀTheꢀdevices,ꢀHT66Fx0AꢀandꢀHT66V70A,ꢀareꢀalmostꢀ
functionalꢀcompatibleꢀexceptꢀtheꢀ“On-ChipꢀDebug”ꢀfunctionꢀandꢀpackageꢀtypes.ꢀUsersꢀcanꢀuseꢀ
theꢀHT66V70AꢀdeviceꢀtoꢀemulateꢀtheꢀHT66Fx0Aꢀseriesꢀofꢀdevicesꢀbehaviorsꢀbyꢀconnectingꢀtheꢀ
OCDSDAꢀandꢀOCDSCKꢀpinsꢀtoꢀtheꢀHoltekꢀHT-IDEꢀdevelopmentꢀtools.ꢀTheꢀOCDSDAꢀpinꢀisꢀtheꢀ
OCDSꢀData/Addressꢀinput/outputꢀpinꢀwhileꢀtheꢀOCDSCKꢀpinꢀisꢀtheꢀOCDSꢀclockꢀinputꢀpin.ꢀWhenꢀ
usersꢀuseꢀtheꢀHT66V70AꢀEVꢀchipꢀforꢀdebugging,ꢀtheꢀcorrespondingꢀpinꢀfunctionsꢀsharedꢀwithꢀ
theꢀOCDSDAꢀandꢀOCDSCKꢀpinsꢀinꢀtheꢀHT66Fx0Aꢀseriesꢀofꢀdevicesꢀwillꢀhaveꢀnoꢀeffectꢀinꢀtheꢀ
HT66V70AꢀEVꢀchip.ꢀHowever,ꢀtheꢀtwoꢀOCDSꢀpinsꢀwhichꢀareꢀpin-sharedꢀwithꢀtheꢀICPꢀprogrammingꢀ
pinsꢀareꢀstillꢀusedꢀasꢀtheꢀFlashꢀMemoryꢀprogrammingꢀpinsꢀforꢀICP.ꢀForꢀmoreꢀdetailedꢀOCDSꢀ
information,ꢀreferꢀtoꢀtheꢀcorrespondingꢀdocumentꢀnamedꢀ“Holtekꢀe-Linkꢀforꢀ8-bitꢀMCUꢀOCDSꢀ
User’sꢀGuide”.
Holtek e-Link Pins
OCDSDA
OCDSCK
VDD
EV Chip Pins
OCDSDA
OCDSCK
VDD
Pin Description
On-Cꢂip Debug Suppoꢀt Data/Addꢀess input/output
On-Cꢂip Debug Suppoꢀt Cloꢁk input
Poweꢀ Supply
GND
VSS
Gꢀound
In Application Programming – IAP
ThisꢀdeviceꢀoffersꢀIAPꢀfunctionꢀtoꢀupdateꢀdataꢀorꢀapplicationꢀprogramꢀtoꢀflashꢀROM.ꢀUsersꢀcanꢀ
defineꢀanyꢀROMꢀlocationꢀforꢀIAP,ꢀbutꢀthereꢀareꢀsomeꢀfeaturesꢀwhichꢀuserꢀmustꢀnoticeꢀinꢀusingꢀIAPꢀ
function.
•ꢀ Eraseꢀpage:ꢀ64ꢀwords/page
•ꢀ Writing:ꢀ64ꢀwords/time
•ꢀ Reading:ꢀ1ꢀword/time
In Application Programming Control Register
TheꢀAddressꢀregister,ꢀFARLꢀandꢀFARH,ꢀandꢀtheꢀDataꢀregisters,ꢀFD0L/FD0H,ꢀFD1L/FD1H,ꢀ
FD2L/FD2HꢀandꢀFD3L/FD3H,ꢀlocatedꢀinꢀDataꢀMemoryꢀsection0,ꢀtogetherꢀwithꢀtheꢀControlꢀ
registersr,ꢀFC0,ꢀFC1ꢀandꢀFC2,ꢀlocatedꢀinꢀDataꢀMemoryꢀsection1ꢀareꢀtheꢀcorrespondingꢀFlashꢀaccessꢀ
registersꢀforꢀIAP.ꢀAsꢀindirectꢀaddressingꢀisꢀtheꢀonlyꢀwayꢀtoꢀaccessꢀtheꢀFC0,ꢀFC1ꢀandꢀFC2ꢀregisters,ꢀ
allꢀreadꢀandꢀwriteꢀoperationsꢀtoꢀtheꢀregistersꢀmustꢀbeꢀperformedꢀusingꢀtheꢀIndirectꢀAddressingꢀ
Register,ꢀIAR1,ꢀandꢀtheꢀMemoryꢀPointerꢀpair,ꢀMP1LꢀandꢀMP1H.ꢀBecauseꢀtheꢀFC0,ꢀFC1ꢀandꢀFC2ꢀ
controlꢀregistersꢀareꢀlocatedꢀatꢀtheꢀaddressꢀofꢀ43H~45HꢀinꢀDataꢀMemoryꢀsection1,ꢀtheꢀdesiredꢀvalueꢀ
rangedꢀfromꢀ43Hꢀtoꢀ45HꢀmustꢀfirstꢀbeꢀwrittenꢀintoꢀtheꢀMP1LꢀMemoryꢀPointerꢀlowꢀbyteꢀandꢀtheꢀvalueꢀ
“01H”ꢀmustꢀalsoꢀbeꢀwrittenꢀintoꢀtheꢀMP1HꢀMemoryꢀPointerꢀhighꢀbyte.
Rev. 1.00
ꢅ1
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• FC0 Register
Bit
7
6
5
F�OD1
R/W
1
4
3
2
1
FRDEN
R/W
0
0
Name
R/W
CFWEN F�ODꢃ
F�OD0 FWPEN
FWT
R/W
0
FRD
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
POR
Bitꢀ7
CFWEN:ꢀFlashꢀMemoryꢀWriteꢀenableꢀcontrol
0:ꢀFlashꢀmemoryꢀwriteꢀfunctionꢀisꢀdisabled
1:ꢀFlashꢀmemoryꢀwriteꢀfunctionꢀhasꢀbeenꢀsuccessfullyꢀenabled
Whenꢀthisꢀbitꢀisꢀclearedꢀtoꢀ0ꢀbyꢀapplicationꢀprogram,ꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀ
isꢀdisabled.ꢀNoteꢀthatꢀwritingꢀaꢀ“1”ꢀintoꢀthisꢀbitꢀresultsꢀinꢀnoꢀaction.ꢀThisꢀbitꢀisꢀusedꢀ
toꢀindicateꢀthatꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀstatus.ꢀWhenꢀthisꢀbitꢀisꢀsetꢀtoꢀ1ꢀbyꢀ
hardware,ꢀitꢀmeansꢀthatꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀisꢀenabledꢀsuccessfully.ꢀ
Otherwise,ꢀtheꢀFlashꢀmemoryꢀwriteꢀfunctionꢀisꢀdisabledꢀasꢀtheꢀbitꢀcontentꢀisꢀzero.
Bitꢀ6~4
FMOD2~FMOD0:ꢀModeꢀselection
000:ꢀWriteꢀprogramꢀmemory
001:ꢀPageꢀeraseꢀprogramꢀmemory
010:ꢀReserved
011:ꢀReadꢀprogramꢀmemory
101:ꢀReserved
110:ꢀFWENꢀmodeꢀ–ꢀFlashꢀmemoryꢀWriteꢀfunctionꢀEnableꢀmode
111:ꢀReserved
Bitꢀ3
Bitꢀ2
FWPEN:ꢀFlashꢀmemoryꢀwriteꢀprocedureꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
Whenꢀthisꢀbitꢀisꢀsetꢀtoꢀ1ꢀandꢀtheꢀFMODꢀfieldꢀisꢀsetꢀtoꢀ“110”,ꢀtheꢀIAPꢀcontrollerꢀwillꢀ
executeꢀtheꢀ“Flashꢀmemoryꢀwriteꢀfunctionꢀenable”ꢀprocedure.ꢀOnceꢀtheꢀFlashꢀmemoryꢀ
writeꢀfunctionꢀisꢀsuccessfullyꢀenabled,ꢀitꢀisꢀnotꢀnecessaryꢀtoꢀsetꢀtheꢀFWPENꢀbitꢀanyꢀ
more.
FWT:ꢀFlashꢀROMꢀwriteꢀcontrolꢀbit
0:ꢀDoꢀnotꢀinitiateꢀFlashꢀmemoryꢀwriteꢀorꢀFlashꢀmemoryꢀWriteꢀprocessꢀisꢀcompleted
1:ꢀInitiateꢀFlashꢀmemoryꢀwriteꢀprocess
ThisꢀbitꢀisꢀsetꢀbyꢀsoftwareꢀandꢀclearedꢀbyꢀhardwareꢀwhenꢀtheꢀFlashꢀmemoryꢀwriteꢀ
processꢀisꢀcompleted.
Bitꢀ1
Bitꢀ0
FRDEN:ꢀFlashꢀmemoryꢀreadꢀenableꢀbit
0:ꢀFlashꢀmemoryꢀreadꢀdisable
1:ꢀFlashꢀmemoryꢀreadꢀenable
FRD:ꢀFlashꢀmemoryꢀreadꢀcontrolꢀbit
0:ꢀDoꢀnotꢀinitiateꢀFlashꢀmemoryꢀreadꢀorꢀFlashꢀmemoryꢀreadꢀprocessꢀisꢀcompleted
1:ꢀInitiateꢀFlashꢀmemoryꢀreadꢀprocess
ThisꢀbitꢀisꢀsetꢀbyꢀsoftwareꢀandꢀclearedꢀbyꢀhardwareꢀwhenꢀtheꢀFlashꢀmemoryꢀreadꢀ
processꢀisꢀcompleted.
Rev. 1.00
ꢅꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• FC1 Register
Bit
Name
R/W
7
D7
R
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
0
Bitꢀ7~0
55H:ꢀwholeꢀchipꢀreset
Whenꢀuserꢀwritesꢀ55Hꢀtoꢀthisꢀregister,ꢀitꢀwillꢀgenerateꢀaꢀresetꢀsignalꢀtoꢀresetꢀwholeꢀ
chip.
• FC2 Register
Bit
7
6
5
4
3
2
1
0
CLWB
R/W
0
Name
R/W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ“0”
CLWB:ꢀFlashꢀMemoryꢀWriteꢀbufferꢀclearꢀcontrol
0:ꢀDoꢀnotꢀinitiateꢀWirteꢀBufferꢀClearꢀorꢀWirteꢀBufferꢀClearꢀprocessꢀisꢀcompleted
1:ꢀInitiateꢀWirteꢀBufferꢀClearꢀprocess
ThisꢀbitꢀisꢀsetꢀbyꢀsoftwareꢀandꢀclearedꢀbyꢀhardwareꢀwhenꢀtheꢀWirteꢀBufferꢀClearꢀ
processꢀisꢀcompleted.
• FARL Register
Bit
Name
R/W
7
A7
R/W
0
6
A6
R/W
0
5
A5
R/W
0
4
A4
R/W
0
3
Aꢅ
R/W
0
2
Aꢃ
R/W
0
1
A1
R/W
0
0
A0
R/W
0
POR
Bitꢀ7~0ꢀ
FlashꢀMemoryꢀAddressꢀ[7:0]
• FARH Register
Bit
Name
R/W
7
6
5
4
3
A11
R/W
0
2
1
A9
R/W
0
0
A8
R/W
0
—
—
—
A14
R/W
0
A1ꢅ
R/W
0
A1ꢃ
R/W
0
A10
R/W
0
POR
Bitꢀ7ꢀ
Bitꢀ6~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
FlashꢀMemoryꢀAddressꢀ[14:8]
• FD0L Register
Bit
Name
R/W
7
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
D7
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀfirstꢀFlashꢀMemoryꢀdataꢀ[7:0]
• FD0H Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
D15
R/W
0
D14
R/W
0
D1ꢅ
R/W
0
D1ꢃ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀfirstꢀFlashꢀMemoryꢀdataꢀ[15:8]
Rev. 1.00
ꢅꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• FD1L Register
Bit
Name
R/W
7
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
D7
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀsecondꢀFlashꢀMemoryꢀdataꢀ[7:0]
• FD1H Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
D15
R/W
0
D14
R/W
0
D1ꢅ
R/W
0
D1ꢃ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀsecondꢀFlashꢀMemoryꢀdataꢀ[15:8]
• FD2L Register
Bit
Name
R/W
7
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
D7
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀthirdꢀFlashꢀMemoryꢀdataꢀ[7:0]
• FD2H Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
D15
R/W
0
D14
R/W
0
D1ꢅ
R/W
0
D1ꢃ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀthirdꢀFlashꢀMemoryꢀdataꢀ[15:8]
• FD3L Register
Bit
Name
R/W
7
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
D7
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀfourthꢀFlashꢀMemoryꢀdataꢀ[7:0]
• FD3H Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
D15
R/W
0
D14
R/W
0
D1ꢅ
R/W
0
D1ꢃ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0ꢀ
TheꢀfourthꢀFlashꢀMemoryꢀdataꢀ[15:8]
Rev. 1.00
ꢅ4
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Flash Memory Write Function Enable Procedure
InꢀorderꢀtoꢀallowꢀusersꢀtoꢀchangeꢀtheꢀFlashꢀmemoryꢀdataꢀthroughꢀtheꢀIAPꢀcontrolꢀregisters,ꢀusersꢀ
mustꢀfirstꢀenableꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀbyꢀtheꢀfollowingꢀprocedurce:
•ꢀ Writeꢀ“110”ꢀintoꢀtheꢀFMOD2~FMOD0ꢀbitsꢀtoꢀselectꢀtheꢀFWENꢀmode.
•ꢀ SetꢀtheꢀFWPENꢀbitꢀtoꢀ“1”.ꢀTheꢀstepꢀ1ꢀandꢀstepꢀ2ꢀcanꢀbeꢀexecutedꢀsimultaneously.
•ꢀ Theꢀpatternꢀdataꢀwithꢀaꢀsequenceꢀofꢀ00H,ꢀ04H,ꢀ0DH,ꢀ09H,ꢀC3Hꢀandꢀ40Hꢀmustꢀbeꢀwrittenꢀintoꢀtheꢀ
FD1L,ꢀFD1H,ꢀFD2L,ꢀFD2H,ꢀFD3LꢀandꢀFD3Hꢀregistersꢀrespectively.
•ꢀ Aꢀcounterꢀwithꢀaꢀtime-outꢀperiodꢀofꢀ300μsꢀwillꢀbeꢀactivatedꢀtoꢀallowꢀusersꢀwritingꢀtheꢀcorrectꢀ
patternꢀdataꢀintoꢀtheꢀFD1L/FD1H~FD3L/FD3Hꢀregisterꢀpairs.ꢀTheꢀcounterꢀclockꢀisꢀderivedꢀfromꢀ
LIRCꢀoscillator.
•ꢀ Ifꢀtheꢀcounterꢀoverflowsꢀorꢀtheꢀpatternꢀdataꢀisꢀincorrect,ꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀwillꢀ
notꢀbeꢀenabledꢀandꢀusersꢀmustꢀagainꢀrepeatꢀtheꢀaboveꢀprocedure.ꢀThenꢀtheꢀFWPENꢀbitꢀwillꢀ
automaticallyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀhardware.
•ꢀ Ifꢀtheꢀpatternꢀdataꢀisꢀcorrectꢀbeforeꢀtheꢀcounterꢀoverflows,ꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀwillꢀ
beꢀenabledꢀandꢀtheꢀFPWENꢀbitꢀwillꢀautomaticallyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀhardware.ꢀTheꢀCFWENꢀbitꢀ
willꢀalsoꢀbeꢀsetꢀtoꢀ1ꢀbyꢀhardwareꢀtoꢀindicateꢀthatꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀisꢀsuccessfullyꢀ
enabled.
•ꢀ OnceꢀtheꢀFlashꢀmemoryꢀwriteꢀoperationꢀisꢀenabled,ꢀtheꢀuserꢀcanꢀchangeꢀtheꢀFlashꢀROMꢀdataꢀ
throughꢀtheꢀFlashꢀcontrolꢀregister.
•ꢀ ToꢀdisableꢀtheꢀFlashꢀmermoyꢀwriteꢀoperation,ꢀtheꢀuserꢀcanꢀclearꢀtheꢀCFWENꢀbitꢀtoꢀ0.
no
Is patteꢀn is
ꢁoꢀꢀeꢁt ?
yes
Flasꢂ �emoꢀy
Wꢀite Funꢁtion
Enable Pꢀoꢁeduꢀe
FWPEN=0
&
CFWEN=0
Is ꢁounteꢀ
oveꢀflow ?
yes
Set F�OD [ꢃ:0] =110 & FWPEN=1
→Seleꢁt FWEN mode & Staꢀt Flasꢂ wꢀite
Haꢀdwaꢀe aꢁtivate a ꢁounteꢀ
no
no
Failed
FWPEN=0 ?
Wꢀtie tꢂe following patteꢀn to Flasꢂ Data ꢀegisteꢀs
FD1L= 00ꢂ ꢄ FD1H = 04ꢂ
yes
FDꢃL= 0Dꢂ ꢄ FDꢃH = 09ꢂ
FDꢅL= Cꢅꢂ ꢄ FDꢅH = 40ꢂ
CFWEN = 1
Suꢁꢁess
END
Flash Memory Write Function Enable Procedure
Rev. 1.00
ꢅ5
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Wꢀite
Flasꢂ �emoꢀy
Flasꢂ �emoꢀy
Wꢀite Funꢁtion
Enable Pꢀoꢁeduꢀe
Set Page Eꢀase addꢀess: FARH/FARL
Set F�OD [ꢃ:0]=001 & FWT=1
→ Seleꢁt “Page Eꢀase mode”
& Initiate wꢀite opeꢀation
no
FWT=0 ?
yes
Set F�OD [ꢃ:0]=000
→ Seleꢁt “Wꢀite Flasꢂ �ode”
Set Page Eꢀase addꢀess: FARH/FARL
Wꢀite data to data ꢀegisteꢀ: FD0L/FD0H
no
Page data
wꢀite finisꢂ ?
yes
Set FWT=1
no
FWT=0 ?
yes
no
Wꢀite Finisꢂ ?
yes
Cleaꢀ CFWEN=0
END
Write Flash Memory Procedure
Rev. 1.00
ꢅ6
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
ERASE PAGE
FARH
FARL[7:6]
Note
0
1
ꢃ
ꢅ
4
5
6
7
8
9
0000 0000
0000 0000
0000 0000
0000 0000
0000 0001
0000 0001
0000 0001
0000 0001
0000 0010
0000 0010
00
01
10
11
00
01
10
11
00
01
:
:
:
:
:
:
FARL [5:0]: don’t ꢁaꢀe
ꢃ5ꢃ
ꢃ5ꢅ
ꢃ54
ꢃ55
0011 1111
0011 1111
0011 1111
0011 1111
00
01
10
11
:
:
:
:
:
:
508
509
510
511
0111 1111
0111 1111
0111 1111
0111 1111
00
01
10
11
Note: Thereꢀareꢀ256ꢀIAPꢀeraseꢀpagesꢀinꢀtheꢀHT66F60Aꢀdeviceꢀwhileꢀthereꢀareꢀ512ꢀIAPꢀeraseꢀpagesꢀ
inꢀtheꢀHT66F70Aꢀdevice.
Rev. 1.00
ꢅ7
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Read
Flasꢂ �emoꢀy
Set F�OD [ꢃ:0]=011
& FRDEN=1
Set Flasꢂ Addꢀess ꢀegisteꢀs
FAH=xxꢂꢄ FAL=xxꢂ
Set FRD=1
no
FRD=0 ?
yes
Read data value:
FD0L=xxꢂꢄ FD0H=xxꢂ
no
Read Finisꢂ ?
yes
Cleaꢀ FWEN bit
END
Read Flash Memory Procedure
Note:ꢀWhenꢀtheꢀFWTꢀorꢀFRDꢀbitꢀisꢀsetꢀtoꢀ1,ꢀtheꢀMCUꢀisꢀstopped.
Rev. 1.00
ꢅ8
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Data Memory
TheꢀDataꢀMemoryꢀisꢀanꢀ8-bitꢀwideꢀRAMꢀinternalꢀmemoryꢀandꢀisꢀtheꢀlocationꢀwhereꢀtemporaryꢀ
informationꢀisꢀstored.
Dividedꢀintoꢀtwoꢀtypes,ꢀtheꢀfirstꢀofꢀDataꢀMemoryꢀisꢀanꢀareaꢀofꢀRAMꢀwhereꢀspecialꢀfunctionꢀregistersꢀ
areꢀlocated.ꢀTheseꢀregistersꢀhaveꢀfixedꢀlocationsꢀandꢀareꢀnecessaryꢀforꢀcorrectꢀoperationꢀofꢀtheꢀ
device.ꢀManyꢀofꢀtheseꢀregistersꢀcanꢀbeꢀreadꢀfromꢀandꢀwrittenꢀtoꢀdirectlyꢀunderꢀprogramꢀcontrol,ꢀ
however,ꢀsomeꢀremainꢀprotectedꢀfromꢀuserꢀmanipulation.ꢀTheꢀsecondꢀareaꢀofꢀDataꢀMemoryꢀisꢀ
reservedꢀforꢀgeneralꢀpurposeꢀuse.ꢀAllꢀlocationsꢀwithinꢀthisꢀareaꢀareꢀreadꢀandꢀwriteꢀaccessibleꢀunderꢀ
programꢀcontrol.
Structure
TheꢀDataꢀMemoryꢀisꢀdividedꢀintoꢀseveralꢀsections,ꢀallꢀofꢀwhichꢀareꢀimplementedꢀinꢀ8-bitꢀwideꢀ
Memory.ꢀEachꢀofꢀtheꢀDataꢀMemoryꢀsectionsꢀisꢀcategorizedꢀintoꢀtwoꢀtypes,ꢀtheꢀSpecialꢀPurposeꢀDataꢀ
MemoryꢀandꢀtheꢀGeneralꢀPurposeꢀDataꢀMemory.
TheꢀstartꢀaddressꢀofꢀtheꢀSpecialꢀPurposeꢀDataꢀMemoryꢀforꢀallꢀdevicesꢀisꢀtheꢀaddressꢀ00Hꢀwhileꢀ
theꢀstartꢀaddressꢀofꢀtheꢀGeneralꢀPurposeꢀDataꢀMemoryꢀisꢀtheꢀaddressꢀ80H.ꢀTheꢀspecialꢀpurposeꢀ
registersꢀwhichꢀareꢀaddressedꢀfromꢀ00Hꢀtoꢀ3FHꢀinꢀDataꢀMemoryꢀareꢀcommonꢀtoꢀallꢀsectionsꢀandꢀareꢀ
accessibleꢀinꢀallꢀsections.ꢀHowever,ꢀtheꢀspecialꢀpurposeꢀregistersꢀlocatedꢀinꢀtheꢀsectionꢀ1ꢀcanꢀonlyꢀbeꢀ
accessedꢀwithꢀtheꢀaddressꢀfromꢀ40HꢀtoꢀFFH.
Device
Capacity
Sections
0: 80H~FFH
1: 80H~FFH
HT66F60A
Geneꢀal Puꢀpose: 10ꢃ4×8
:
:
7: 80H~FFH
0: 80H~FFH
1: 80H~FFH
HT66F70A
Geneꢀal Puꢀpose: ꢃ048×8
:
:
15: 80H~FFH
Rev. 1.00
ꢅ9
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Seꢁtion 0
00H
Speꢁial Puꢀpose
Data �emoꢀy
40H in seꢁtion 1
7FH
FFH in seꢁtion 1
80H
Geneꢀal Puꢀpose
Data �emoꢀy
FFH
Seꢁtion 0
Seꢁtion 1
Seꢁtion ꢃ
Seꢁtion N
N=7 foꢀ HT66F60A; N=15 foꢀ HT66F70A
Data Memory Structure
General Purpose Data Memory
Allꢀmicrocontrollerꢀprogramsꢀrequireꢀanꢀareaꢀofꢀread/writeꢀmemoryꢀwhereꢀtemporaryꢀdataꢀcanꢀbeꢀ
storedꢀandꢀretrievedꢀforꢀuseꢀlater.ꢀItꢀisꢀthisꢀareaꢀofꢀRAMꢀmemoryꢀthatꢀisꢀknownꢀasꢀGeneralꢀPurposeꢀ
DataꢀMemory.ꢀThisꢀareaꢀofꢀDataꢀMemoryꢀisꢀfullyꢀaccessibleꢀbyꢀtheꢀuserꢀprogramingꢀforꢀbothꢀreadingꢀ
andꢀwritingꢀoperations.ꢀByꢀusingꢀtheꢀbitꢀoperationꢀinstructionsꢀindividualꢀbitsꢀcanꢀbeꢀsetꢀorꢀresetꢀ
underꢀprogramꢀcontrolꢀgivingꢀtheꢀuserꢀaꢀlargeꢀrangeꢀofꢀflexibilityꢀforꢀbitꢀmanipulationꢀinꢀtheꢀDataꢀ
Memory.
Special Purpose Data Memory
ThisꢀareaꢀofꢀDataꢀMemoryꢀisꢀwhereꢀregisters,ꢀnecessaryꢀforꢀtheꢀcorrectꢀoperationꢀofꢀtheꢀ
microcontroller,ꢀareꢀstored.ꢀMostꢀofꢀtheꢀregistersꢀareꢀbothꢀreadableꢀandꢀwriteableꢀbutꢀsomeꢀareꢀ
protectedꢀandꢀareꢀreadableꢀonly,ꢀtheꢀdetailsꢀofꢀwhichꢀareꢀlocatedꢀunderꢀtheꢀrelevantꢀSpecialꢀFunctionꢀ
Registerꢀsection.ꢀNoteꢀthatꢀforꢀlocationsꢀthatꢀareꢀunused,ꢀanyꢀreadꢀinstructionꢀtoꢀtheseꢀaddressesꢀwillꢀ
returnꢀtheꢀvalueꢀ“00H”.
Rev. 1.00
40
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Seꢁtion 0~7
IAR0
Seꢁtion 0ꢄ ꢃ~7
Unused
EEA
Seꢁtion 1
EEC
Seꢁtion 0~15
IAR0
Seꢁtion 0ꢄ ꢃ~15 Seꢁtion 1
00H
01H
0ꢃH
0ꢅH
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
1ꢃH
1ꢅH
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
ꢃ0H
ꢃ1H
ꢃꢃH
ꢃꢅH
ꢃ4H
ꢃ5H
ꢃ6H
ꢃ7H
ꢃ8H
ꢃ9H
ꢃAH
ꢃBH
ꢃCH
ꢃDH
ꢃEH
ꢃFH
ꢅ0H
ꢅ1H
ꢅꢃH
ꢅꢅH
ꢅ4H
ꢅ5H
ꢅ6H
ꢅ7H
ꢅ8H
ꢅ9H
ꢅAH
ꢅBH
ꢅCH
ꢅDH
ꢅEH
ꢅFH
40H
41H
4ꢃH
4ꢅH
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
5ꢃH
5ꢅH
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
6ꢃH
6ꢅH
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
00H
01H
0ꢃH
0ꢅH
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
1ꢃH
1ꢅH
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
ꢃ0H
ꢃ1H
ꢃꢃH
ꢃꢅH
ꢃ4H
ꢃ5H
ꢃ6H
ꢃ7H
ꢃ8H
ꢃ9H
ꢃAH
ꢃBH
ꢃCH
ꢃDH
ꢃEH
ꢃFH
ꢅ0H
ꢅ1H
ꢅꢃH
ꢅꢅH
ꢅ4H
ꢅ5H
ꢅ6H
ꢅ7H
ꢅ8H
ꢅ9H
ꢅAH
ꢅBH
ꢅCH
ꢅDH
ꢅEH
ꢅFH
40H
41H
4ꢃH
4ꢅH
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
5ꢃH
5ꢅH
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
6ꢃH
6ꢅH
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
Unused
EEA
EEC
Unused
Unused
FC0
�P0
Unused
Unused
FC0
�P0
IAR1
EED
IAR1
EED
�P1L
�P1H
ACC
Unused
Unused
Unused
CP0C
�P1L
�P1H
ACC
Unused
Unused
Unused
CP0C
FC1
FC1
FCꢃ
FCꢃ
PCL
Unused
Unused
IFS0
PCL
Unused
Unused
IFS0
TBLP
TBLH
TBHP
STATUS
BP
CP1C
TBLP
TBLH
TBHP
STATUS
BP
CP1C
T�1C0
T�1C1
T�1Cꢃ
T�1DL
T�1DH
T�1AL
T�1AH
T�1BL
T�1BH
T�ꢃC0
T�ꢃC1
T�ꢃDL
T�ꢃDH
T�ꢃAL
T�ꢃAH
T�ꢃRP
T�ꢅC0
T�ꢅC1
T�ꢅDL
T�ꢅDH
T�ꢅAL
T�ꢅAH
T�0C0
T�0C1
T�0DL
T�0DH
T�0AL
T�0AH
PSC0
T�1C0
T�1C1
T�1Cꢃ
T�1DL
T�1DH
T�1AL
T�1AH
T�1BL
T�1BH
T�ꢃC0
T�ꢃC1
T�ꢃDL
T�ꢃDH
T�ꢃAL
T�ꢃAH
T�ꢃRP
T�ꢅC0
T�ꢅC1
T�ꢅDL
T�ꢅDH
T�ꢅAL
T�ꢅAH
T�0C0
T�0C1
T�0DL
T�0DH
T�0AL
T�0AH
PSC0
IFS1
IFS1
IFSꢃ
IFSꢃ
IFSꢅ
IFSꢅ
IARꢃ
IFS4
IARꢃ
IFS4
�PꢃL
�PꢃH
Unused
PAWU
PAPU
PA
IFS5
�PꢃL
�PꢃH
Unused
PAWU
PAPU
PA
IFS5
Unused
Unused
T�4C0
T�4C1
T�4DL
T�4DH
T�4AL
T�4AH
T�4RP
T�5C0
T�5C1
T�5DL
T�5DH
T�5AL
T�5AH
T�5RP
Unused
Unused
PAS0
Unused
Unused
T�4C0
T�4C1
T�4DL
T�4DH
T�4AL
T�4AH
T�4RP
T�5C0
T�5C1
T�5DL
T�5DH
T�5AL
T�5AH
T�5RP
Unused
Unused
PAS0
PAC
PAC
Unused
PBPU
PB
Unused
PBPU
PB
PBC
PBC
Unused
PCPU
PC
Unused
PCPU
PC
PCC
PCC
Unused
PDPU
PD
Unused
PDPU
PD
PDC
PDC
Unused
PEPU
PE
Unused
PEPU
PE
PAS1
PAS1
PASꢃ
PASꢃ
PEC
PASꢅ
PEC
PASꢅ
Unused
PFPU
PF
Unused
Unused
PBSꢃ
Unused
PFPU
PF
Unused
Unused
PBSꢃ
TBC0
TBC0
TBC1
TBC1
PFC
PSC1
PBSꢅ
PFC
PSC1
PBSꢅ
Unused
PGPU
PG
ADCR0
ADCR1
ADRL
PCS0
Unused
PGPU
PG
ADCR0
ADCR1
ADRL
PCS0
PCS1
PCSꢃ
PCSꢅ
PDS0
PDS1
PDSꢃ
PDSꢅ
PES0
PCS1
PCSꢃ
PGC
ADRH
PCSꢅ
PGC
ADRH
Unused
PHPU
PH
SI�C0
SI�C1
SI�D
PDS0
Unused
PHPU
PH
SI�C0
SI�C1
SI�D
PDS1
PDSꢃ
PHC
6FH SI�Cꢃ/SI�A
PDSꢅ
PHC
6FH SI�Cꢃ/SI�A
INTC0
INTC1
INTCꢃ
INTCꢅ
�FI0
70H
71H
7ꢃH
7ꢅH
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
IꢃCTOC
SPIAC0
SPIAC1
SPIAD
FARL
PES0
INTC0
INTC1
INTCꢃ
INTCꢅ
�FI0
70H
71H
7ꢃH
7ꢅH
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
IꢃCTOC
SPIAC0
SPIAC1
SPIAD
FARL
PES1
PES1
PESꢃ
PESꢃ
PESꢅ
PESꢅ
PFS0
PFS0
�FI1
FARH
FD0L
Unused
Unused
Unused
PGS0
PGS1
PGSꢃ
PGSꢅ
PHS0
�FI1
FARH
FD0L
Unused
Unused
Unused
PGS0
PGS1
PGSꢃ
PGSꢅ
PHS0
PHS1
PHSꢃ
Unused
�FIꢃ
�FIꢃ
�FIꢅ
FD0H
FD1L
�FIꢅ
FD0H
FD1L
�FI4
�FI4
INTEG
S�OD
S�OD1
LVRC
LVDC
WDTC
S�ODꢃ
FD1H
FDꢃL
INTEG
S�OD
S�OD1
LVRC
LVDC
WDTC
S�ODꢃ
FD1H
FDꢃL
FDꢃH
FDꢅL
FDꢃH
FDꢅL
FDꢅH
TBCꢃ
PHS1
FDꢅH
TBCꢃ
PHSꢃ
SCO�C
Unused
SCO�C
: Unusedꢄ ꢀead as 00H
: Unusedꢄ ꢀead as 00H
HT66F60A Special Purpose Data Memory
HT66F70A Special Purpose Data Memory
Rev. 1.00
41
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Special Function Register Description
MostꢀofꢀtheꢀSpecialꢀFunctionꢀRegisterꢀdetailsꢀwillꢀbeꢀdescribedꢀinꢀtheꢀrelevantꢀfunctionalꢀsection,ꢀ
howeverꢀseveralꢀregistersꢀrequireꢀaꢀseparateꢀdescriptionꢀinꢀthisꢀsection.
Indirect Addressing Registers – IAR0, IAR1
TheꢀIndirectꢀAddressingꢀRegisters,ꢀIAR0,ꢀIAR1ꢀandꢀIAR2,ꢀalthoughꢀhavingꢀtheirꢀlocationsꢀinꢀnormalꢀ
RAMꢀregisterꢀspace,ꢀdoꢀnotꢀactuallyꢀphysicallyꢀexistꢀasꢀnormalꢀregisters.ꢀTheꢀmethodꢀofꢀindirectꢀ
addressingꢀforꢀRAMꢀdataꢀmanipulationꢀusesꢀtheseꢀIndirectꢀAddressingꢀRegistersꢀandꢀMemoryꢀ
Pointers,ꢀinꢀcontrastꢀtoꢀdirectꢀmemoryꢀaddressing,ꢀwhereꢀtheꢀactualꢀmemoryꢀaddressꢀisꢀspecified.ꢀ
ActionsꢀonꢀtheꢀIAR0,ꢀIAR1ꢀandꢀIAR2ꢀregistersꢀwillꢀresultꢀinꢀnoꢀactualꢀreadꢀorꢀwriteꢀoperationꢀtoꢀ
theseꢀregistersꢀbutꢀratherꢀtoꢀtheꢀmemoryꢀlocationꢀspecifiedꢀbyꢀtheirꢀcorrespondingꢀMemoryꢀPointers,ꢀ
MP0,ꢀMP1L/MP1HꢀorꢀMP2L/MP2H.ꢀActingꢀasꢀaꢀpair,ꢀIAR0ꢀandꢀMP0ꢀcanꢀtogetherꢀaccessꢀdataꢀ
onlyꢀfromꢀSectionꢀ0ꢀwhileꢀtheꢀIAR1ꢀregisterꢀtogetherꢀwithꢀMP1L/MP1HꢀregisterꢀpairꢀandꢀIAR2ꢀ
registerꢀtogetherꢀwithꢀMP2L/MP2HꢀregisterꢀpairꢀcanꢀaccessꢀdataꢀfromꢀanyꢀDataꢀMemoryꢀsection.ꢀAsꢀ
theꢀIndirectꢀAddressingꢀRegistersꢀareꢀnotꢀphysicallyꢀimplemented,ꢀreadingꢀtheꢀIndirectꢀAddressingꢀ
Registersꢀindirectlyꢀwillꢀreturnꢀaꢀresultꢀofꢀ“00H”ꢀandꢀwritingꢀtoꢀtheꢀregistersꢀindirectlyꢀwillꢀresultꢀinꢀ
noꢀoperation.
Memory Pointers – MP0, MP1
FiveꢀMemoryꢀPointers,ꢀknownꢀasꢀMP0,ꢀMP1L,ꢀMP1H,ꢀMP2LꢀandꢀMP2H,ꢀareꢀprovided.ꢀTheseꢀ
MemoryꢀPointersꢀareꢀphysicallyꢀimplementedꢀinꢀtheꢀDataꢀMemoryꢀandꢀcanꢀbeꢀmanipulatedꢀinꢀtheꢀ
sameꢀwayꢀasꢀnormalꢀregistersꢀprovidingꢀaꢀconvenientꢀwayꢀwithꢀwhichꢀtoꢀaddressꢀandꢀtrackꢀdata.ꢀ
WhenꢀanyꢀoperationꢀtoꢀtheꢀrelevantꢀIndirectꢀAddressingꢀRegistersꢀisꢀcarriedꢀout,ꢀtheꢀactualꢀaddressꢀ
thatꢀtheꢀmicrocontrollerꢀisꢀdirectedꢀtoꢀisꢀtheꢀaddressꢀspecifiedꢀbyꢀtheꢀrelatedꢀMemoryꢀPointer.ꢀMP0,ꢀ
togetherꢀwithꢀIndirectꢀAddressingꢀRegister,ꢀIAR0,ꢀareꢀusedꢀtoꢀaccessꢀdataꢀfromꢀSectionꢀ0,ꢀwhileꢀ
MP1L/MP1HꢀtogetherꢀwithꢀIAR1ꢀandꢀMP2L/MP2HꢀtogetherꢀwithꢀIAR2ꢀareꢀusedꢀtoꢀaccessꢀdataꢀ
fromꢀallꢀdataꢀsectionsꢀaccordingꢀtoꢀtheꢀcorrespondingꢀMP1HꢀorꢀMP2Hꢀregister.ꢀDirectꢀAddressingꢀ
canꢀbeꢀusedꢀinꢀallꢀdataꢀsectionsꢀusingꢀtheꢀcorrespondingꢀinstructionꢀwhichꢀcanꢀaddressꢀallꢀavailableꢀ
dataꢀmemoryꢀspace.
Indirect Addressing Program Example
data .section data
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block
db ?
code .section at 0 code
org 00h
start:
mov a,04h
; setup size of block
mov block,a
ꢀ
ꢀ
movꢀa,offsetꢀadres1ꢀ
ꢀ
ꢀ
;ꢀAccumulatorꢀloadedꢀwithꢀfirstꢀRAMꢀaddress
;ꢀsetupꢀmemoryꢀpointerꢀwithꢀfirstꢀRAMꢀaddress
movꢀmp0,aꢀ ꢀ
ꢀ
ꢀ
loop:
ꢀ
clrꢀIAR0ꢀ
inc mp0
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀclearꢀtheꢀdataꢀatꢀaddressꢀdefinedꢀbyꢀMP0
; increment memory pointer
sdz block
jmp loop
; check if last memory location has been cleared
continue:
Theꢀimportantꢀpointꢀtoꢀnoteꢀhereꢀisꢀthatꢀinꢀtheꢀexampleꢀshownꢀabove,ꢀnoꢀreferenceꢀisꢀmadeꢀtoꢀspecificꢀ
RAMꢀaddresses.
Rev. 1.00
4ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Bank Pointer – BP
Dependingꢀuponꢀwhichꢀdeviceꢀisꢀused,ꢀtheꢀProgramꢀMemoryꢀisꢀdividedꢀintoꢀseveralꢀbanks.ꢀSelectingꢀ
theꢀrequiredꢀProgramꢀMemoryꢀareaꢀisꢀachievedꢀusingꢀtheꢀBankꢀPointer.
TheꢀDataꢀMemoryꢀisꢀinitialisedꢀtoꢀBankꢀ0ꢀafterꢀaꢀreset,ꢀexceptꢀforꢀaꢀWDTꢀtime-outꢀresetꢀinꢀtheꢀ
PowerꢀDownꢀMode,ꢀinꢀwhichꢀcase,ꢀtheꢀDataꢀMemoryꢀbankꢀremainsꢀunaffected.ꢀDirectlyꢀaddressingꢀ
theꢀDataꢀMemoryꢀwillꢀalwaysꢀresultꢀinꢀBankꢀ0ꢀbeingꢀaccessedꢀirrespectiveꢀofꢀtheꢀvalueꢀofꢀtheꢀ
BankꢀPointer.ꢀAccessingꢀdataꢀfromꢀbanksꢀotherꢀthanꢀBankꢀ0ꢀmustꢀbeꢀimplementedꢀusingꢀIndirectꢀ
addressing.
AsꢀbothꢀtheꢀProgramꢀMemoryꢀandꢀDataꢀMemoryꢀshareꢀtheꢀsameꢀBankꢀPointerꢀRegister,ꢀcareꢀmustꢀbeꢀ
takenꢀduringꢀprogramming.
Bit
Device
7
6
5
4
3
2
1
0
HT66F60A
HT66F70A
—
—
—
—
—
—
—
—
—
—
—
—
—
BP0
BP0
BP1
BP Register List
BP Register – HT66F60A
Bit
Name
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BP0
R/W
0
POR
Bitꢀ7~1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ"0"
BP0:ꢀProgramꢀmemoryꢀbankꢀpoint
0:ꢀBankꢀ0
1:ꢀBankꢀ1
BP Register – HT66F70A
Bit
Name
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BP1
R/W
0
BP0
R/W
0
POR
Bitꢀ7~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ"0"
BP1~BP0:ꢀProgramꢀmemoryꢀbankꢀpoint
00:ꢀBankꢀ0
01:ꢀBankꢀ1
10:ꢀBankꢀ2
11:ꢀBankꢀ3
Accumulator – ACC
TheꢀAccumulatorꢀisꢀcentralꢀtoꢀtheꢀoperationꢀofꢀanyꢀmicrocontrollerꢀandꢀisꢀcloselyꢀrelatedꢀwithꢀ
operationsꢀcarriedꢀoutꢀbyꢀtheꢀALU.ꢀTheꢀAccumulatorꢀisꢀtheꢀplaceꢀwhereꢀallꢀintermediateꢀresultsꢀ
fromꢀtheꢀALUꢀareꢀstored.ꢀWithoutꢀtheꢀAccumulatorꢀitꢀwouldꢀbeꢀnecessaryꢀtoꢀwriteꢀtheꢀresultꢀofꢀ
eachꢀcalculationꢀorꢀlogicalꢀoperationꢀsuchꢀasꢀaddition,ꢀsubtraction,ꢀshift,ꢀetc.,ꢀtoꢀtheꢀDataꢀMemoryꢀ
resultingꢀinꢀhigherꢀprogrammingꢀandꢀtimingꢀoverheads.ꢀDataꢀtransferꢀoperationsꢀusuallyꢀinvolveꢀ
theꢀtemporaryꢀstorageꢀfunctionꢀofꢀtheꢀAccumulator;ꢀforꢀexample,ꢀwhenꢀtransferringꢀdataꢀbetweenꢀ
oneꢀuserꢀdefinedꢀregisterꢀandꢀanother,ꢀitꢀisꢀnecessaryꢀtoꢀdoꢀthisꢀbyꢀpassingꢀtheꢀdataꢀthroughꢀtheꢀ
Accumulatorꢀasꢀnoꢀdirectꢀtransferꢀbetweenꢀtwoꢀregistersꢀisꢀpermitted.
Rev. 1.00
4ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Program Counter Low Register – PCL
Toꢀprovideꢀadditionalꢀprogramꢀcontrolꢀfunctions,ꢀtheꢀlowꢀbyteꢀofꢀtheꢀProgramꢀCounterꢀisꢀmadeꢀ
accessibleꢀtoꢀprogrammersꢀbyꢀlocatingꢀitꢀwithinꢀtheꢀSpecialꢀPurposeꢀareaꢀofꢀtheꢀDataꢀMemory.ꢀByꢀ
manipulatingꢀthisꢀregister,ꢀdirectꢀjumpsꢀtoꢀotherꢀprogramꢀlocationsꢀareꢀeasilyꢀimplemented.ꢀLoadingꢀ
aꢀvalueꢀdirectlyꢀintoꢀthisꢀPCLꢀregisterꢀwillꢀcauseꢀaꢀjumpꢀtoꢀtheꢀspecifiedꢀProgramꢀMemoryꢀlocation,ꢀ
however,ꢀasꢀtheꢀregisterꢀisꢀonlyꢀ8-bitꢀwide,ꢀonlyꢀjumpsꢀwithinꢀtheꢀcurrentꢀProgramꢀMemoryꢀpageꢀareꢀ
permitted.ꢀWhenꢀsuchꢀoperationsꢀareꢀused,ꢀnoteꢀthatꢀaꢀdummyꢀcycleꢀwillꢀbeꢀinserted.
Look-up Table Registers – TBLP, TBHP, TBLH
Theseꢀthreeꢀspecialꢀfunctionꢀregistersꢀareꢀusedꢀtoꢀcontrolꢀoperationꢀofꢀtheꢀlook-upꢀtableꢀwhichꢀisꢀ
storedꢀinꢀtheꢀProgramꢀMemory.ꢀTBLPꢀandꢀTBHPꢀareꢀtheꢀtableꢀpointerꢀandꢀindicatesꢀtheꢀlocationꢀ
whereꢀtheꢀtableꢀdataꢀisꢀlocated.ꢀTheirꢀvalueꢀmustꢀbeꢀsetupꢀbeforeꢀanyꢀtableꢀreadꢀcommandsꢀareꢀ
executed.ꢀTheirꢀvalueꢀcanꢀbeꢀchanged,ꢀforꢀexampleꢀusingꢀtheꢀ“INC”ꢀorꢀ“DEC”ꢀinstructions,ꢀallowingꢀ
forꢀeasyꢀtableꢀdataꢀpointingꢀandꢀreading.ꢀTBLHꢀisꢀtheꢀlocationꢀwhereꢀtheꢀhighꢀorderꢀbyteꢀofꢀtheꢀtableꢀ
dataꢀisꢀstoredꢀafterꢀaꢀtableꢀreadꢀdataꢀinstructionꢀhasꢀbeenꢀexecuted.ꢀNoteꢀthatꢀtheꢀlowerꢀorderꢀtableꢀ
dataꢀbyteꢀisꢀtransferredꢀtoꢀaꢀuserꢀdefinedꢀlocation.
Status Register – STATUS
Thisꢀ8-bitꢀregisterꢀcontainsꢀtheꢀzeroꢀflagꢀ(Z),ꢀcarryꢀflagꢀ(C),ꢀauxiliaryꢀcarryꢀflagꢀ(AC),ꢀoverflowꢀ
flagꢀ(OV),ꢀSCꢀflag,ꢀCZꢀflag,ꢀpowerꢀdownꢀflagꢀ(PDF),ꢀandꢀwatchdogꢀtime-outꢀflagꢀ(TO).ꢀTheseꢀ
arithmetic/logicalꢀoperationꢀandꢀsystemꢀmanagementꢀflagsꢀareꢀusedꢀtoꢀrecordꢀtheꢀstatusꢀandꢀoperationꢀ
ofꢀtheꢀmicrocontroller.
WithꢀtheꢀexceptionꢀofꢀtheꢀTOꢀandꢀPDFꢀflags,ꢀbitsꢀinꢀtheꢀstatusꢀregisterꢀcanꢀbeꢀalteredꢀbyꢀinstructionsꢀ
likeꢀmostꢀotherꢀregisters.ꢀAnyꢀdataꢀwrittenꢀintoꢀtheꢀstatusꢀregisterꢀwillꢀnotꢀchangeꢀtheꢀTOꢀorꢀPDFꢀflag.ꢀ
Inꢀaddition,ꢀoperationsꢀrelatedꢀtoꢀtheꢀstatusꢀregisterꢀmayꢀgiveꢀdifferentꢀresultsꢀdueꢀtoꢀtheꢀdifferentꢀ
instructionꢀoperations.ꢀTheꢀTOꢀflagꢀcanꢀbeꢀaffectedꢀonlyꢀbyꢀaꢀsystemꢀpower-up,ꢀaꢀWDTꢀtime-outꢀorꢀ
byꢀexecutingꢀtheꢀ"CLRꢀWDT"ꢀorꢀ"HALT"ꢀinstruction.ꢀTheꢀPDFꢀflagꢀisꢀaffectedꢀonlyꢀbyꢀexecutingꢀ
theꢀ"HALT"ꢀorꢀ"CLRꢀWDT"ꢀinstructionꢀorꢀduringꢀaꢀsystemꢀpower-up.
TheꢀZ,ꢀOV,ꢀAC,ꢀC,ꢀSCꢀandꢀCZꢀflagsꢀgenerallyꢀreflectꢀtheꢀstatusꢀofꢀtheꢀlatestꢀoperations.
•ꢀ Cꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀduringꢀanꢀadditionꢀoperationꢀorꢀifꢀaꢀborrowꢀdoesꢀnotꢀtakeꢀ
placeꢀduringꢀaꢀsubtractionꢀoperation;ꢀotherwiseꢀCꢀisꢀcleared.ꢀCꢀisꢀalsoꢀaffectedꢀbyꢀaꢀrotateꢀthroughꢀ
carryꢀinstruction.
•ꢀ ACꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀoutꢀofꢀtheꢀlowꢀnibblesꢀinꢀaddition,ꢀorꢀnoꢀborrowꢀfromꢀ
theꢀhighꢀnibbleꢀintoꢀtheꢀlowꢀnibbleꢀinꢀsubtraction;ꢀotherwiseꢀACꢀisꢀcleared.
•ꢀ Zꢀisꢀsetꢀifꢀtheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀzero;ꢀotherwiseꢀZꢀisꢀcleared.
•ꢀ OVꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀintoꢀtheꢀhighest-orderꢀbitꢀbutꢀnotꢀaꢀcarryꢀoutꢀofꢀtheꢀ
highest-orderꢀbit,ꢀorꢀviceꢀversa;ꢀotherwiseꢀOVꢀisꢀcleared.
•ꢀ PDFꢀisꢀclearedꢀbyꢀaꢀsystemꢀpower-upꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀinstruction.ꢀPDFꢀisꢀsetꢀbyꢀ
executingꢀtheꢀ“HALT”ꢀinstruction.
•ꢀ TOꢀisꢀclearedꢀbyꢀaꢀsystemꢀpower-upꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀorꢀ“HALT”ꢀinstruction.ꢀTOꢀisꢀ
setꢀbyꢀaꢀWDTꢀtime-out.
•ꢀ SCꢀisꢀtheꢀresultꢀofꢀtheꢀ“XOR”ꢀoperationꢀwhichꢀisꢀperformedꢀbyꢀtheꢀOVꢀflagꢀandꢀtheꢀMSBꢀofꢀtheꢀ
currentꢀinstructionꢀoperationꢀresult.
•ꢀ CZꢀisꢀtheꢀoperationalꢀresultꢀofꢀdifferentꢀflagsꢀforꢀdifferentꢀinstuctions.ꢀReferꢀtoꢀregisterꢀdefinitionsꢀ
forꢀmoreꢀdetails.
Inꢀaddition,ꢀonꢀenteringꢀanꢀinterruptꢀsequenceꢀorꢀexecutingꢀaꢀsubroutineꢀcall,ꢀtheꢀstatusꢀregisterꢀwillꢀ
notꢀbeꢀpushedꢀontoꢀtheꢀstackꢀautomatically.ꢀIfꢀtheꢀcontentsꢀofꢀtheꢀstatusꢀregistersꢀareꢀimportantꢀandꢀifꢀ
theꢀsubroutineꢀcanꢀcorruptꢀtheꢀstatusꢀregister,ꢀprecautionsꢀmustꢀbeꢀtakenꢀtoꢀcorrectlyꢀsaveꢀit.
Rev. 1.00
44
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
STATUS Register
Bit
Name
R/W
7
SC
R
6
CZ
R
5
TO
R
4
PDF
R
3
OV
R/W
x
2
Z
1
AC
R/W
x
0
C
R/W
x
R/W
x
POR
x
x
0
0
“x”: unknown
Bitꢀ7
SC:ꢀTheꢀresultꢀofꢀtheꢀ“XOR”ꢀoperationꢀwhichꢀisꢀperformedꢀbyꢀtheꢀOVꢀflagꢀandꢀtheꢀꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀMSBꢀofꢀtheꢀinstructionꢀoperationꢀresult.
Bitꢀ6
CZ:ꢀTheꢀtheꢀoperationalꢀresultꢀofꢀdifferentꢀflagsꢀforꢀdifferentꢀinstuctions.
ForꢀSUB/SUBM/LSUB/LSUBMꢀinstructions,ꢀtheꢀCZꢀflagꢀisꢀequalꢀtoꢀtheꢀZꢀflag.ꢀ
ForꢀSBC/ꢀSBCM/ꢀLSBC/ꢀLSBCMꢀinstructions,ꢀtheꢀCZꢀflagꢀisꢀtheꢀ“AND”ꢀoperationꢀ
resultꢀwhichꢀisꢀperformedꢀbyꢀtheꢀpreviousꢀoperationꢀCZꢀflagꢀandꢀcurrentꢀoperationꢀ
zeroꢀflag.ꢀForꢀotherꢀinstructions,ꢀtheꢀCZꢀflagꢀwilllꢀnotꢀbeꢀaffected.
Bitꢀ5
Bitꢀ4
Bitꢀ3
TO:ꢀWatchdogꢀTime-Outꢀflag
0:ꢀAfterꢀpowerꢀupꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀorꢀ“HALT”ꢀinstruction
1:ꢀAꢀwatchdogꢀtime-outꢀoccurred.
PDF:ꢀPowerꢀdownꢀflag
0:ꢀAfterꢀpowerꢀupꢀorꢀexecutingꢀtheꢀ“CLRꢀWDT”ꢀinstruction
1:ꢀByꢀexecutingꢀtheꢀ“HALT”ꢀinstruction
OV:ꢀOverflowꢀflag
0:ꢀNoꢀoverflow
1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀintoꢀtheꢀhighest-orderꢀbitꢀbutꢀnotꢀaꢀcarryꢀoutꢀofꢀtheꢀ
highest-orderꢀbitꢀorꢀviceꢀversa.
Bitꢀ2
Bitꢀ1
Z:ꢀZeroꢀflag
0:ꢀTheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀnotꢀzero
1:ꢀTheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀzero
AC:ꢀAuxiliaryꢀflag
0:ꢀNoꢀauxiliaryꢀcarry
1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀoutꢀofꢀtheꢀlowꢀnibblesꢀinꢀaddition,ꢀorꢀnoꢀborrowꢀ
fromꢀtheꢀhighꢀnibbleꢀintoꢀtheꢀlowꢀnibbleꢀinꢀsubtraction
Bitꢀ0
C:ꢀCarryꢀflag
0:ꢀNoꢀcarry-out
1:ꢀAnꢀoperationꢀresultsꢀinꢀaꢀcarryꢀduringꢀanꢀadditionꢀoperationꢀorꢀifꢀaꢀborrowꢀdoesꢀ
notꢀtakeꢀplaceꢀduringꢀaꢀsubtractionꢀoperation
Cꢀisꢀalsoꢀaffectedꢀbyꢀaꢀrotateꢀthroughꢀcarryꢀinstruction.
Rev. 1.00
45
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
EEPROM Data Memory
TheseꢀdevicesꢀcontainꢀanꢀareaꢀofꢀinternalꢀEEPROMꢀDataꢀMemory.ꢀEEPROM,ꢀwhichꢀstandsꢀforꢀ
ElectricallyꢀErasableꢀProgrammableꢀReadꢀOnlyꢀMemory,ꢀisꢀbyꢀitsꢀnatureꢀaꢀnon-volatileꢀformꢀ
ofꢀre-programmableꢀmemory,ꢀwithꢀdataꢀretentionꢀevenꢀwhenꢀitsꢀpowerꢀsupplyꢀisꢀremoved.ꢀByꢀ
incorporatingꢀthisꢀkindꢀofꢀdataꢀmemory,ꢀaꢀwholeꢀnewꢀhostꢀofꢀapplicationꢀpossibilitiesꢀareꢀmadeꢀ
availableꢀtoꢀtheꢀdesigner.ꢀTheꢀavailabilityꢀofꢀEEPROMꢀstorageꢀallowsꢀinformationꢀsuchꢀasꢀproductꢀ
identificationꢀnumbers,ꢀcalibrationꢀvalues,ꢀspecificꢀuserꢀdata,ꢀsystemꢀsetupꢀdataꢀorꢀotherꢀproductꢀ
informationꢀtoꢀbeꢀstoredꢀdirectlyꢀwithinꢀtheꢀproductꢀmicrocontroller.ꢀTheꢀprocessꢀofꢀreadingꢀandꢀ
writingꢀdataꢀtoꢀtheꢀEEPROMꢀmemoryꢀhasꢀbeenꢀreducedꢀtoꢀaꢀveryꢀtrivialꢀaffair.
Device
Capacity
Address
HT66F60A
HT66F70A
1ꢃ8×8
00H~7FH
EEPROM Data Memory Structure
TheꢀEEPROMꢀDataꢀMemoryꢀcapacityꢀisꢀ128×8ꢀbitsꢀforꢀthisꢀseriesꢀofꢀdevices.ꢀUnlikeꢀtheꢀProgramꢀ
MemoryꢀandꢀRAMꢀDataꢀMemory,ꢀtheꢀEEPROMꢀDataꢀMemoryꢀisꢀnotꢀdirectlyꢀmappedꢀintoꢀmemoryꢀ
spaceꢀandꢀisꢀthereforeꢀnotꢀdirectlyꢀaddressableꢀinꢀtheꢀsameꢀwayꢀasꢀtheꢀotherꢀtypesꢀofꢀmemory.ꢀReadꢀ
andWriteꢀoperationsꢀtoꢀtheꢀEEPROMꢀareꢀcarriedꢀoutꢀinꢀsingleꢀbyteꢀoperationsꢀusingꢀanꢀaddressꢀandꢀ
dataꢀregisterꢀinꢀSectionꢀ0ꢀandꢀaꢀsingleꢀcontrolꢀregisterꢀinꢀSectionꢀ1.
EEPROM Registers
ThreeꢀregistersꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀinternalꢀEEPROMꢀDataꢀMemory.ꢀTheseꢀareꢀtheꢀ
addressꢀregister,ꢀEEA,ꢀtheꢀdataꢀregister,ꢀEEDꢀandꢀaꢀsingleꢀcontrolꢀregister,ꢀEEC.ꢀAsꢀbothꢀtheꢀEEAꢀ
andꢀEEDꢀregistersꢀareꢀlocatedꢀinꢀSectionꢀ0,ꢀtheyꢀcanꢀbeꢀdirectlyꢀaccessedꢀinꢀtheꢀsameꢀwasꢀasꢀanyꢀ
otherꢀSpecialꢀFunctionꢀRegister.ꢀTheꢀEECꢀregisterꢀhowever,ꢀbeingꢀlocatedꢀinꢀBank1,ꢀcannotꢀbeꢀ
addressedꢀdirectlyꢀandꢀcanꢀonlyꢀbeꢀreadꢀfromꢀorꢀwrittenꢀtoꢀindirectlyꢀusingꢀtheꢀMP1ꢀMemoryꢀPointerꢀ
andꢀIndirectꢀAddressingꢀRegister,ꢀIAR1.ꢀBecauseꢀtheꢀEECꢀcontrolꢀregisterꢀisꢀlocatedꢀatꢀaddressꢀ
40HꢀinꢀSectionꢀ1,ꢀtheꢀMP1LꢀMemoryꢀPointerꢀlowꢀbyteꢀmustꢀfirstꢀbeꢀsetꢀtoꢀtheꢀvalueꢀ40Hꢀandꢀtheꢀ
MP1HꢀMemoryꢀPointerꢀhighꢀbyteꢀsetꢀtoꢀtheꢀvalueꢀ01HꢀbeforeꢀanyꢀoperationsꢀonꢀtheꢀEECꢀregisterꢀareꢀ
executed.
EEA Register
Bit
7
6
EEA6
R/W
x
5
EEA5
R/W
x
4
EEA4
R/W
x
3
EEAꢅ
R/W
x
2
EEAꢃ
R/W
x
1
EEA1
R/W
x
0
EEA0
Name
R/W
—
—
—
R/W
POR
x
“x”: unknown
Bitꢀ7ꢀ
Unimplemented,ꢀreadꢀasꢀ"0"
EEA6~EEA0:ꢀDataꢀEEPROMꢀaddressꢀbitꢀ6~bitꢀ0
Bitꢀ6~0
EED Register
Bit
Name
R/W
7
EED7
R/W
x
6
EED6
R/W
x
5
EED5
R/W
x
4
EED4
R/W
x
3
EEDꢅ
R/W
x
2
EEDꢃ
R/W
x
1
EED1
R/W
x
0
EED0
R/W
POR
x
“x”: unknown
Bitꢀ7~0
EED7~EED0:ꢀDataꢀEEPROMꢀdataꢀbitꢀ7~bitꢀ0
Rev. 1.00
46
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
EEC Register
Bit
Name
R/W
7
6
5
4
3
WREN
R/W
0
2
WR
R/W
0
1
RDEN
R/W
0
0
RD
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~4ꢀ
Bitꢀ3
Unimplemented,ꢀreadꢀasꢀ“0”
WREN:ꢀDataꢀEEPROMꢀwriteꢀoperationꢀenable
0:ꢀDisable
1:ꢀEnable
ThisꢀisꢀtheꢀDataꢀEEPROMꢀWriteꢀOperationꢀEnableꢀbitꢀwhichꢀmustꢀbeꢀsetꢀhighꢀbeforeꢀ
DatatꢀEEPROMꢀwriteꢀoperationsꢀareꢀcarriedꢀout.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀinhibitꢀ
DataꢀEEPROMꢀwriteꢀoperations.
Bitꢀ2
WR:ꢀDataꢀEEPROMꢀwriteꢀcontrol
0:ꢀWriteꢀcycleꢀhasꢀfinished
1:ꢀActivateꢀaꢀwriteꢀcycle
ThisꢀisꢀtheꢀDataꢀEEPROMꢀWriteꢀControlꢀbitꢀandꢀwhenꢀsetꢀhighꢀbyꢀtheꢀapplicationꢀ
programꢀwillꢀactivateꢀaꢀwriteꢀcycle.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀresetꢀtoꢀzeroꢀbyꢀtheꢀ
hardwareꢀafterꢀtheꢀwriteꢀcycleꢀhasꢀfinished.ꢀSettingꢀthisꢀbitꢀhighꢀwillꢀhaveꢀnoꢀeffectꢀifꢀ
theꢀWRENꢀbitꢀhasꢀnotꢀfirstꢀbeenꢀsetꢀhigh.
Bitꢀ1
Bitꢀ0
RDEN:ꢀDataꢀEEPROMꢀreadꢀoperationꢀenable
0:ꢀDisable
1:ꢀEnable
ThisꢀisꢀtheꢀDataꢀEEPROMꢀReadꢀOperationꢀEnableꢀbitꢀwhichꢀmustꢀbeꢀsetꢀhighꢀbeforeꢀ
DatatꢀEEPROMꢀreadꢀoperationsꢀareꢀcarriedꢀout.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀinhibitꢀ
DataꢀEEPROMꢀreadꢀoperations.
RD:ꢀDataꢀEEPROMꢀreadꢀcontrol
0:ꢀReadꢀcycleꢀhasꢀfinished
1:ꢀActivateꢀaꢀreadꢀcycle
ThisꢀisꢀtheꢀDataꢀEEPROMꢀReadꢀControlꢀbitꢀandꢀwhenꢀsetꢀhighꢀbyꢀtheꢀapplicationꢀ
programꢀwillꢀactivateꢀaꢀreadꢀcycle.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀresetꢀtoꢀzeroꢀbyꢀtheꢀ
hardwareꢀafterꢀtheꢀreadꢀcycleꢀhasꢀfinished.ꢀSettingꢀthisꢀbitꢀhighꢀwillꢀhaveꢀnoꢀeffectꢀifꢀ
theꢀRDENꢀbitꢀhasꢀnotꢀfirstꢀbeenꢀsetꢀhigh.
Note:ꢀTheꢀWREN,ꢀWR,ꢀRDENꢀandꢀRDꢀbitsꢀcanꢀnotꢀbeꢀsetꢀtoꢀ“1”ꢀatꢀtheꢀsameꢀtimeꢀinꢀoneꢀinstruction.ꢀ
TheꢀWRꢀandꢀRDꢀbitsꢀcanꢀnotꢀbeꢀsetꢀtoꢀ“1”ꢀatꢀtheꢀsameꢀtime.
Reading Data from the EEPROM
ToꢀreadꢀdataꢀfromꢀtheꢀEEPROM,ꢀtheꢀreadꢀenableꢀbit,ꢀRDEN,ꢀinꢀtheꢀEECꢀregisterꢀmustꢀfirstꢀbeꢀsetꢀ
highꢀtoꢀenableꢀtheꢀreadꢀfunction.ꢀTheꢀEEPROMꢀaddressꢀofꢀtheꢀdataꢀtoꢀbeꢀreadꢀmustꢀthenꢀbeꢀplacedꢀ
inꢀtheꢀEEAꢀregister.ꢀIfꢀtheꢀRDꢀbitꢀinꢀtheꢀEECꢀregisterꢀisꢀnowꢀsetꢀhigh,ꢀaꢀreadꢀcycleꢀwillꢀbeꢀinitiated.ꢀ
SettingꢀtheꢀRDꢀbitꢀhighꢀwillꢀnotꢀinitiateꢀaꢀreadꢀoperationꢀifꢀtheꢀRDENꢀbitꢀhasꢀnotꢀbeenꢀset.ꢀWhenꢀ
theꢀreadꢀcycleꢀterminates,ꢀtheꢀRDꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀzero,ꢀafterꢀwhichꢀtheꢀdataꢀcanꢀ
beꢀreadꢀfromꢀtheꢀEEDꢀregister.ꢀTheꢀdataꢀwillꢀremainꢀinꢀtheꢀEEDꢀregisterꢀuntilꢀanotherꢀreadꢀorꢀwriteꢀ
operationꢀisꢀexecuted.ꢀTheꢀapplicationꢀprogramꢀcanꢀpollꢀtheꢀRDꢀbitꢀtoꢀdetermineꢀwhenꢀtheꢀdataꢀisꢀ
validꢀforꢀreading.
Rev. 1.00
47
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Writing Data to the EEPROM
TheꢀEEPROMꢀaddressꢀofꢀtheꢀdataꢀtoꢀbeꢀwrittenꢀmustꢀfirstꢀbeꢀplacedꢀinꢀtheꢀEEAꢀregisterꢀandꢀtheꢀdataꢀ
placedꢀinꢀtheꢀEEDꢀregister.ꢀToꢀwriteꢀdataꢀtoꢀtheꢀEEPROM,ꢀtheꢀwriteꢀenableꢀbit,ꢀWREN,ꢀinꢀtheꢀEECꢀ
registerꢀmustꢀfirstꢀbeꢀsetꢀhighꢀtoꢀenableꢀtheꢀwriteꢀfunction.ꢀAfterꢀthis,ꢀtheꢀWRꢀbitꢀinꢀtheꢀEECꢀregisterꢀ
mustꢀbeꢀimmediatelyꢀsetꢀhighꢀtoꢀinitiateꢀaꢀwriteꢀcycle.ꢀTheseꢀtwoꢀinstructionsꢀmustꢀbeꢀexecutedꢀ
consecutively.ꢀTheꢀglobalꢀinterruptꢀbitꢀEMIꢀshouldꢀalsoꢀfirstꢀbeꢀclearedꢀbeforeꢀimplementingꢀanyꢀ
writeꢀoperations,ꢀandꢀthenꢀsetꢀagainꢀafterꢀtheꢀwriteꢀcycleꢀhasꢀstarted.ꢀNoteꢀthatꢀsettingꢀtheꢀWRꢀbitꢀ
highꢀwillꢀnotꢀinitiateꢀaꢀwriteꢀcycleꢀifꢀtheꢀWRENꢀbitꢀhasꢀnotꢀbeenꢀset.ꢀAsꢀtheꢀEEPROMꢀwriteꢀcycleꢀisꢀ
controlledꢀusingꢀanꢀinternalꢀtimerꢀwhoseꢀoperationꢀisꢀasynchronousꢀtoꢀmicrocontrollerꢀsystemꢀclock,ꢀ
aꢀcertainꢀtimeꢀwillꢀelapseꢀbeforeꢀtheꢀdataꢀwillꢀhaveꢀbeenꢀwrittenꢀintoꢀtheꢀEEPROM.ꢀDetectingꢀwhenꢀ
theꢀwriteꢀcycleꢀhasꢀfinishedꢀcanꢀbeꢀimplementedꢀeitherꢀbyꢀpollingꢀtheꢀWRꢀbitꢀinꢀtheꢀEECꢀregisterꢀorꢀ
byꢀusingꢀtheꢀEEPROMꢀinterrupt.ꢀWhenꢀtheꢀwriteꢀcycleꢀterminates,ꢀtheꢀWRꢀbitꢀwillꢀbeꢀautomaticallyꢀ
clearedꢀtoꢀzeroꢀbyꢀtheꢀmicrocontroller,ꢀinformingꢀtheꢀuserꢀthatꢀtheꢀdataꢀhasꢀbeenꢀwrittenꢀtoꢀtheꢀ
EEPROM.ꢀTheꢀapplicationꢀprogramꢀcanꢀthereforeꢀpollꢀtheꢀWRꢀbitꢀtoꢀdetermineꢀwhenꢀtheꢀwriteꢀcycleꢀ
hasꢀended.
Write Protection
Protectionꢀagainstꢀinadvertentꢀwriteꢀoperationꢀisꢀprovidedꢀinꢀseveralꢀways.ꢀAfterꢀtheꢀdeviceꢀisꢀ
powered-onꢀtheꢀWriteꢀEnableꢀbitꢀinꢀtheꢀcontrolꢀregisterꢀwillꢀbeꢀclearedꢀpreventingꢀanyꢀwriteꢀ
operations.ꢀAlsoꢀatꢀpower-onꢀtheꢀMemoryꢀPointerꢀpairs,ꢀMP1L/MP1HꢀandꢀMP2L/MP2H,ꢀwillꢀbeꢀ
resetꢀtoꢀzero,ꢀwhichꢀmeansꢀthatꢀDataꢀMemoryꢀSectionꢀ0ꢀwillꢀbeꢀselected.ꢀAsꢀtheꢀEEPROMꢀcontrolꢀ
registerꢀisꢀlocatedꢀinꢀSectionꢀ1,ꢀthisꢀaddsꢀaꢀfurtherꢀmeasureꢀofꢀprotectionꢀagainstꢀspuriousꢀwriteꢀ
operations.ꢀDuringꢀnormalꢀprogramꢀoperation,ꢀensuringꢀthatꢀtheꢀWriteꢀEnableꢀbitꢀinꢀtheꢀcontrolꢀ
registerꢀisꢀclearedꢀwillꢀsafeguardꢀagainstꢀincorrectꢀwriteꢀoperations.
EEPROM Interrupt
TheꢀEEPROMꢀwriteꢀinterruptꢀisꢀgeneratedꢀwhenꢀanꢀEEPROMꢀwriteꢀcycleꢀhasꢀended.ꢀTheꢀEEPROMꢀ
interruptꢀmustꢀfirstꢀbeꢀenabledꢀbyꢀsettingꢀtheꢀDEEꢀbitꢀinꢀtheꢀrelevantꢀinterruptꢀregister.ꢀHoweverꢀasꢀ
theꢀEEPROMꢀisꢀcontainedꢀwithinꢀaꢀMulti-functionꢀInterrupt,ꢀtheꢀassociatedꢀmulti-functionꢀinterruptꢀ
enableꢀbitꢀmustꢀalsoꢀbeꢀset.ꢀWhenꢀanꢀEEPROMꢀwriteꢀcycleꢀends,ꢀtheꢀDEFꢀrequestꢀflagꢀandꢀitsꢀ
associatedꢀmulti-functionꢀinterruptꢀrequestꢀflagꢀwillꢀbothꢀbeꢀset.ꢀIfꢀtheꢀglobal,ꢀEEPROMꢀandꢀMulti-
functionꢀinterruptsꢀareꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀaꢀjumpꢀtoꢀtheꢀassociatedꢀMulti-functionꢀ
Interruptꢀvectorꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀservicedꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀflagꢀ
willꢀbeꢀautomaticallyꢀreset,ꢀtheꢀEEPROMꢀinterruptꢀflagꢀmustꢀbeꢀmanuallyꢀresetꢀbyꢀtheꢀapplicationꢀ
program.ꢀMoreꢀdetailsꢀcanꢀbeꢀobtainedꢀinꢀtheꢀInterruptꢀsection.
Programming Considerations
CareꢀmustꢀbeꢀtakenꢀthatꢀdataꢀisꢀnotꢀinadvertentlyꢀwrittenꢀtoꢀtheꢀEEPROM.ꢀProtectionꢀcanꢀbeꢀ
enhancedꢀbyꢀensuringꢀthatꢀtheꢀWriteꢀEnableꢀbitꢀisꢀnormallyꢀclearedꢀtoꢀzeroꢀwhenꢀnotꢀwriting.ꢀAlsoꢀ
theꢀMemoryꢀPointerꢀhighꢀbyte,ꢀMP1HꢀorꢀMP2H,ꢀcouldꢀbeꢀnormallyꢀclearedꢀtoꢀzeroꢀasꢀthisꢀwouldꢀ
inhibitꢀaccessꢀtoꢀDataꢀMemoryꢀSectionꢀ1ꢀwhereꢀtheꢀEEPROMꢀcontrolꢀregisterꢀexist.ꢀAlthoughꢀ
certainlyꢀnotꢀnecessary,ꢀconsiderationꢀmightꢀbeꢀgivenꢀinꢀtheꢀapplicationꢀprogramꢀtoꢀtheꢀcheckingꢀofꢀ
theꢀvalidityꢀofꢀnewꢀwriteꢀdataꢀbyꢀaꢀsimpleꢀreadꢀbackꢀprocess.
WhenꢀwritingꢀdataꢀtheꢀWRꢀbitꢀmustꢀbeꢀsetꢀhighꢀimmediatelyꢀafterꢀtheꢀWRENꢀbitꢀhasꢀbeenꢀsetꢀhigh,ꢀ
toꢀensureꢀtheꢀwriteꢀcycleꢀexecutesꢀcorrectly.ꢀTheꢀglobalꢀinterruptꢀbitꢀEMIꢀshouldꢀalsoꢀbeꢀclearedꢀ
beforeꢀaꢀwriteꢀcycleꢀisꢀexecutedꢀandꢀthenꢀre-enabledꢀafterꢀtheꢀwriteꢀcycleꢀstarts.
Rev. 1.00
48
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Programming Examples
Reading Data from the EEPROM – Polling Mothod
MOVꢀ A,ꢀEEPROM_ADRESꢀ
MOVꢀ EEA,ꢀA
ꢀ
;ꢀuserꢀdefinedꢀaddress
MOVꢀ A,ꢀ040Hꢀꢀ
MOVꢀ MP1L,ꢀAꢀ
MOVꢀ A,ꢀ01Hꢀꢀ
MOVꢀ MP1H,ꢀA
SETꢀ IAR1.1ꢀ ꢀ
SETꢀ IAR1.0ꢀ ꢀ
BACK:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀsetupꢀmemoryꢀpointerꢀMP1L
;ꢀMP1ꢀpointsꢀtoꢀEECꢀregister
;ꢀsetupꢀmemoryꢀpointerꢀMP1H
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀsetꢀRDENꢀbit,ꢀenableꢀreadꢀoperations
;ꢀstartꢀReadꢀCycleꢀ-ꢀsetꢀRDꢀbit
SZꢀ
ꢀ
IAR1.0ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀcheckꢀforꢀreadꢀcycleꢀend
;ꢀdisableꢀEEPROMꢀread/write
;ꢀmoveꢀreadꢀdataꢀtoꢀregister
JMPꢀ BACK
CLRꢀ IAR1ꢀ
CLRꢀ MP1H
ꢀ
ꢀ
ꢀ
MOVꢀ A,ꢀEEDꢀꢀ
MOVꢀ READ_DATA,ꢀA
Writing Data to the EEPROM – Polling Mothod
CLRꢀ EMI
MOVꢀ A,ꢀEEPROM_ADRESꢀ
MOVꢀ EEA,ꢀA
MOVꢀ A,ꢀEEPROM_DATAꢀ
MOVꢀ EED,ꢀA
ꢀ
ꢀ
;ꢀuserꢀdefinedꢀaddress
;ꢀuserꢀdefinedꢀdata
MOVꢀ A,ꢀ040Hꢀꢀ
MOVꢀ MP1L,ꢀAꢀ
MOVꢀ A,ꢀ01Hꢀꢀ
MOVꢀ MP1H,ꢀA
SETꢀ IAR1.3ꢀ ꢀ
SETꢀ IAR1.2ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀsetupꢀmemoryꢀpointerꢀMP1L
;ꢀMP1ꢀpointsꢀtoꢀEECꢀregister
;ꢀsetupꢀmemoryꢀpointerꢀMP1H
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀsetꢀWRENꢀbit,ꢀenableꢀwriteꢀoperations
;ꢀStartꢀWriteꢀCycleꢀ-ꢀsetꢀWRꢀbitꢀ-ꢀexecutedꢀimmediately
;ꢀafterꢀsetꢀWRENꢀbit
ꢀ
ꢀ
ꢀ
ꢀ
SETꢀ EMI
BACK:
SZꢀ
ꢀ
IAR1.2ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀcheckꢀforꢀwriteꢀcycleꢀend
;ꢀdisableꢀEEPROMꢀread/write
JMPꢀ BACK
CLRꢀ IAR1ꢀ
CLRꢀ MP1H
ꢀ
ꢀ
Rev. 1.00
49
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Oscillator
Variousꢀoscillatorꢀoptionsꢀofferꢀtheꢀuserꢀaꢀwideꢀrangeꢀofꢀfunctionsꢀaccordingꢀtoꢀtheirꢀvariousꢀ
applicationꢀrequirements.ꢀTheꢀflexibleꢀfeaturesꢀofꢀtheꢀoscillatorꢀfunctionsꢀensureꢀthatꢀtheꢀbestꢀ
optimisationꢀcanꢀbeꢀachievedꢀinꢀtermsꢀofꢀspeedꢀandꢀpowerꢀsaving.ꢀOscillatorꢀselectionsꢀandꢀoperationꢀ
areꢀselectedꢀthroughꢀaꢀcombinationꢀofꢀconfigurationꢀoptionsꢀandꢀregisters.
Oscillator Overview
Inꢀadditionꢀtoꢀbeingꢀtheꢀsourceꢀofꢀtheꢀmainꢀsystemꢀclockꢀtheꢀoscillatorsꢀalsoꢀprovideꢀclockꢀsourcesꢀ
forꢀtheꢀWatchdogꢀTimerꢀandꢀTimeꢀBaseꢀInterrupts.ꢀExternalꢀoscillatorsꢀrequiringꢀsomeꢀexternalꢀ
componentsꢀasꢀwellꢀasꢀfullyꢀintegratedꢀinternalꢀoscillators,ꢀrequiringꢀnoꢀexternalꢀcomponents,ꢀ
areꢀprovidedꢀtoꢀformꢀaꢀwideꢀrangeꢀofꢀbothꢀfastꢀandꢀslowꢀsystemꢀoscillators.ꢀAllꢀoscillatorꢀ
optionsꢀareꢀselectedꢀthroughꢀtheꢀconfigurationꢀoptions.ꢀTheꢀhigherꢀfrequencyꢀoscillatorsꢀprovideꢀ
higherꢀperformanceꢀbutꢀcarryꢀwithꢀitꢀtheꢀdisadvantageꢀofꢀhigherꢀpowerꢀrequirements,ꢀwhileꢀtheꢀ
oppositeꢀisꢀofꢀcourseꢀtrueꢀforꢀtheꢀlowerꢀfrequencyꢀoscillators.ꢀWithꢀtheꢀcapabilityꢀofꢀdynamicallyꢀ
switchingꢀbetweenꢀfastꢀandꢀslowꢀsystemꢀclock,ꢀtheseꢀdevicesꢀhaveꢀtheꢀflexibilityꢀtoꢀoptimizeꢀtheꢀ
performance/powerꢀratio,ꢀaꢀfeatureꢀespeciallyꢀimportantꢀinꢀpowerꢀsensitiveꢀportableꢀapplications.
Type
Exteꢀnal Cꢀystal
Name
HXT
Frequency
400kHz~16�Hz
400kHz~16�Hz
8�Hz
Pins
OSC1/OSCꢃ
OSC1
Exteꢀnal RC
ERC
HIRC
LXT
Inteꢀnal Higꢂ Speed RC
Exteꢀnal Low Speed Cꢀystal
Inteꢀnal Low Speed RC
—
ꢅꢃ.768kHz
ꢅꢃkHz
XT1/XTꢃ
—
LIRC
Oscillator Types
System Clock Configurations
Thereꢀareꢀfiveꢀmethodsꢀofꢀgeneratingꢀtheꢀsystemꢀclock,ꢀthreeꢀhighꢀspeedꢀoscillatorsꢀandꢀtwoꢀlowꢀ
speedꢀoscillators.ꢀTheꢀhighꢀspeedꢀoscillatorsꢀareꢀisꢀtheꢀexternalꢀcrystal/ceramicꢀoscillator,ꢀexternalꢀ
RCꢀnetworkꢀoscillatorꢀandꢀtheꢀinternalꢀ8MHzꢀRCꢀoscillator.ꢀTheꢀtwoꢀlowꢀspeedꢀoscillatorsꢀareꢀtheꢀ
internalꢀ32kHzꢀRCꢀoscillatorꢀandꢀtheꢀexternalꢀ32.768kHzꢀcrystalꢀoscillator.ꢀSelectingꢀwhetherꢀtheꢀ
lowꢀorꢀhighꢀspeedꢀoscillatorꢀisꢀusedꢀasꢀtheꢀsystemꢀoscillatorꢀisꢀimplementedꢀusingꢀtheꢀHLCLKꢀbitꢀ
andꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSMODꢀregisterꢀandꢀasꢀtheꢀsystemꢀclockꢀcanꢀbeꢀdynamicallyꢀselected.
Theꢀactualꢀsourceꢀclockꢀusedꢀforꢀeachꢀofꢀtheꢀhighꢀspeedꢀandꢀlowꢀspeedꢀoscillatorsꢀisꢀchosenꢀ
viaꢀconfigurationꢀoptions.ꢀTheꢀfrequencyꢀofꢀtheꢀslowꢀspeedꢀorꢀhighꢀspeedꢀsystemꢀclockꢀisꢀalsoꢀ
determinedꢀusingꢀtheꢀHLCLKꢀbitꢀandꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSMODꢀregister.ꢀNoteꢀthatꢀtwoꢀ
oscillatorꢀselectionsꢀmustꢀbeꢀmadeꢀnamelyꢀoneꢀhighꢀspeedꢀandꢀoneꢀlowꢀspeedꢀsystemꢀoscillators.ꢀItꢀisꢀ
notꢀpossibleꢀtoꢀchooseꢀaꢀno-oscillatorꢀselectionꢀforꢀeitherꢀtheꢀhighꢀorꢀlowꢀspeedꢀoscillator.
Rev. 1.00
50
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Higꢂ Speed
Osꢁillation (HOSC)
fH/ꢃ
HXT
fH/4
fH/8
fH
ERC
Pꢀesꢁaleꢀ
fH/16
fSYS
fH/ꢅꢃ
HIRC
fH/64
Fast Wake-up fꢀom SLEEP �ode oꢀ
IDLE �ode Contꢀol (foꢀ HXT only)
Higꢂ Speed Osꢁillation
Configuꢀation Option
CKS[ꢃ:0]ꢄ HLCLK
LIRC
LXT
fSUB
fSUB
WDT
fSYS
fSYS/4
fSUB
fTB
Low Speed
Osꢁillation (LOSC)
Pꢀesꢁaleꢀ
Time Base
Low Speed Osꢁillation
Configuꢀation Option
fH
TB0 [ꢃ:0] TB1 [ꢃ:0]
CLKS0[1:0]
fSYS
fSYS/4
fSUB
fP
Peꢀipꢂeꢀal Cloꢁk
Output (PCK)
Pꢀesꢁaleꢀ
TBꢃ [ꢃ:0]
fH
CLKS1[1:0]
External Crystal/Ceramic Oscillator – HXT
TheꢀExternalꢀCrystal/CeramicꢀSystemꢀOscillatorꢀisꢀoneꢀofꢀtheꢀhighꢀfrequencyꢀoscillatorꢀchoices,ꢀ
whichꢀisꢀselectedꢀviaꢀconfigurationꢀoption.ꢀForꢀmostꢀcrystalꢀoscillatorꢀconfigurations,ꢀtheꢀsimpleꢀ
connectionꢀofꢀaꢀcrystalꢀacrossꢀOSC1ꢀandꢀOSC2ꢀwillꢀcreateꢀtheꢀnecessaryꢀphaseꢀshiftꢀandꢀfeedbackꢀforꢀ
oscillation,ꢀwithoutꢀrequiringꢀexternalꢀcapacitors.ꢀHowever,ꢀforꢀsomeꢀcrystalꢀtypesꢀandꢀfrequencies,ꢀ
toꢀensureꢀoscillation,ꢀitꢀmayꢀbeꢀnecessaryꢀtoꢀaddꢀtwoꢀsmallꢀvalueꢀcapacitors,ꢀC1ꢀandꢀC2.ꢀUsingꢀaꢀ
ceramicꢀresonatorꢀwillꢀusuallyꢀrequireꢀtwoꢀsmallꢀvalueꢀcapacitors,ꢀC1ꢀandꢀC2,ꢀtoꢀbeꢀconnectedꢀasꢀ
shownꢀforꢀoscillationꢀtoꢀoccur.ꢀTheꢀvaluesꢀofꢀC1ꢀandꢀC2ꢀshouldꢀbeꢀselectedꢀinꢀconsultationꢀwithꢀtheꢀ
crystalꢀorꢀresonatorꢀmanufacturer'sꢀspecification.
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2
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F
Crystal/Resonator Oscillator – HXT
Crystal Oscillator C1 and C2 Values
Crystal Frequency
1ꢃ�Hz
C1
0pF
C2
0pF
0pF
0pF
8�Hz
0pF
4�Hz
0pF
1�Hz
100pF
100pF
Note: C1 and Cꢃ values aꢀe foꢀ guidanꢁe only.
Crystal Recommended Capacitor Values
Rev. 1.00
51
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
External RC Oscillator – ERC
Ω
Ω
UsingꢀtheꢀERCꢀoscillatorꢀonlyꢀrequiresꢀthatꢀaꢀresistor,ꢀwithꢀaꢀvalueꢀbetweenꢀ56k ꢀandꢀ2.4M ,ꢀisꢀ
connectedꢀbetweenꢀOSC1ꢀandꢀVDD,ꢀandꢀaꢀcapacitorꢀisꢀconnectedꢀbetweenꢀOSC1ꢀandꢀground,ꢀ
providingꢀaꢀlowꢀcostꢀoscillatorꢀconfiguration.ꢀItꢀisꢀonlyꢀtheꢀexternalꢀresistorꢀthatꢀdeterminesꢀtheꢀ
oscillationꢀfrequency;ꢀtheꢀexternalꢀcapacitorꢀhasꢀnoꢀinfluenceꢀoverꢀtheꢀfrequencyꢀandꢀisꢀconnectedꢀ
forꢀstabilityꢀpurposesꢀonly.ꢀDeviceꢀtrimmingꢀduringꢀtheꢀmanufacturingꢀprocessꢀandꢀtheꢀinclusionꢀ
ofꢀinternalꢀfrequencyꢀcompensationꢀcircuitsꢀareꢀusedꢀtoꢀensureꢀthatꢀtheꢀinfluenceꢀofꢀtheꢀpowerꢀ
supplyꢀvoltage,ꢀtemperatureꢀandꢀprocessꢀvariationsꢀonꢀtheꢀoscillationꢀfrequencyꢀareꢀminimised.ꢀAsꢀaꢀ
Ω
resistance/frequencyꢀreferenceꢀpoint,ꢀitꢀcanꢀbeꢀnotedꢀthatꢀwithꢀanꢀexternalꢀ120k ꢀresistorꢀconnectedꢀ
andꢀwithꢀaꢀ5Vꢀvoltageꢀpowerꢀsupplyꢀandꢀtemperatureꢀofꢀ25 Cꢀdegrees,ꢀtheꢀoscillatorꢀwillꢀhaveꢀaꢀ
°
frequencyꢀofꢀ8MHzꢀwithinꢀaꢀtoleranceꢀofꢀ2%.ꢀHereꢀonlyꢀtheꢀOSC1ꢀpinꢀisꢀused,ꢀwhichꢀisꢀsharedꢀwithꢀ
I/OꢀpinꢀPB1,ꢀleavingꢀpinꢀPB2ꢀfreeꢀforꢀuseꢀasꢀaꢀnormalꢀI/Oꢀpin.
V
D
D
R
O
C
S
O
C
S
1
2
0
p
F
External RC Oscillator – ERC
Internal High Speed RC Oscillator – HIRC
TheꢀinternalꢀRCꢀoscillatorꢀisꢀaꢀfullyꢀintegratedꢀsystemꢀoscillatorꢀrequiringꢀnoꢀexternalꢀcomponents.ꢀ
TheꢀinternalꢀRCꢀoscillatorꢀhasꢀaꢀfixedꢀfrequencyꢀofꢀ8MHz.ꢀDeviceꢀtrimmingꢀduringꢀtheꢀ
manufacturingꢀprocessꢀandꢀtheꢀinclusionꢀofꢀinternalꢀfrequencyꢀcompensationꢀcircuitsꢀareꢀusedꢀtoꢀ
ensureꢀthatꢀtheꢀinfluenceꢀofꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀtemperatureꢀandꢀprocessꢀvariationsꢀonꢀtheꢀ
oscillationꢀfrequencyꢀareꢀminimised.ꢀAsꢀaꢀresult,ꢀatꢀaꢀpowerꢀsupplyꢀofꢀ5Vꢀandꢀatꢀaꢀtemperatureꢀofꢀ
25 Cꢀdegrees,ꢀtheꢀfixedꢀoscillationꢀfrequencyꢀofꢀ8MHzꢀwillꢀhaveꢀaꢀtoleranceꢀwithinꢀ2%.ꢀNoteꢀthatꢀifꢀ
°
thisꢀinternalꢀsystemꢀclockꢀoptionꢀisꢀselected,ꢀasꢀitꢀrequiresꢀnoꢀexternalꢀpinsꢀforꢀitsꢀoperation,ꢀI/Oꢀpinsꢀ
PB1ꢀandꢀPB2ꢀareꢀfreeꢀforꢀuseꢀasꢀnormalꢀI/Oꢀpins.
Rev. 1.00
5ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
External 32.768kHz Crystal Oscillator – LXT
TheꢀExternalꢀ32.768kHzꢀCrystalꢀSystemꢀOscillatorꢀisꢀoneꢀofꢀtheꢀlowꢀfrequencyꢀoscillatorꢀchoices,ꢀ
whichꢀisꢀselectedꢀviaꢀconfigurationꢀoption.ꢀThisꢀclockꢀsourceꢀhasꢀaꢀfixedꢀfrequencyꢀofꢀ32.768kHzꢀ
andꢀrequiresꢀaꢀ32.768kHzꢀcrystalꢀtoꢀbeꢀconnectedꢀbetweenꢀpinsꢀXT1ꢀandꢀXT2.ꢀTheꢀexternalꢀresistorꢀ
andꢀcapacitorꢀcomponentsꢀconnectedꢀtoꢀtheꢀ32.768kHzꢀcrystalꢀareꢀnecessaryꢀtoꢀprovideꢀoscillation.ꢀ
Forꢀapplicationsꢀwhereꢀpreciseꢀfrequenciesꢀareꢀessential,ꢀtheseꢀcomponentsꢀmayꢀbeꢀrequiredꢀtoꢀ
provideꢀfrequencyꢀcompensationꢀdueꢀtoꢀdifferentꢀcrystalꢀmanufacturingꢀtolerances.ꢀDuringꢀpower-upꢀ
thereꢀisꢀaꢀtimeꢀdelayꢀassociatedꢀwithꢀtheꢀLXTꢀoscillatorꢀwaitingꢀforꢀitꢀtoꢀstart-up.
WhenꢀtheꢀmicrocontrollerꢀentersꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀtheꢀsystemꢀclockꢀisꢀswitchedꢀoffꢀtoꢀstopꢀ
microcontrollerꢀactivityꢀandꢀtoꢀconserveꢀpower.ꢀHowever,ꢀinꢀmanyꢀmicrocontrollerꢀapplicationsꢀ
itꢀmayꢀbeꢀnecessaryꢀtoꢀkeepꢀtheꢀinternalꢀtimersꢀoperationalꢀevenꢀwhenꢀtheꢀmicrocontrollerꢀisꢀinꢀ
theꢀSLEEPꢀorꢀIDLEꢀMode.ꢀToꢀdoꢀthis,ꢀanotherꢀclock,ꢀindependentꢀofꢀtheꢀsystemꢀclock,ꢀmustꢀbeꢀ
provided.
However,ꢀforꢀsomeꢀcrystals,ꢀtoꢀensureꢀoscillationꢀandꢀaccurateꢀfrequencyꢀgeneration,ꢀitꢀisꢀnecessaryꢀ
toꢀaddꢀtwoꢀsmallꢀvalueꢀexternalꢀcapacitors,ꢀC1ꢀandꢀC2.ꢀTheꢀexactꢀvaluesꢀofꢀC1ꢀandꢀC2ꢀshouldꢀbeꢀ
selectedꢀinꢀconsultationꢀwithꢀtheꢀcrystalꢀorꢀresonatorꢀmanufacturer’sꢀspecification.ꢀTheꢀexternalꢀ
parallelꢀfeedbackꢀresistor,ꢀRp,ꢀisꢀrequired.
SomeꢀconfigurationꢀoptionsꢀdetermineꢀifꢀtheꢀXT1/XT2ꢀpinsꢀareꢀusedꢀforꢀtheꢀLXTꢀoscillatorꢀorꢀasꢀI/Oꢀ
pins.
•ꢀ IfꢀtheꢀLXTꢀoscillatorꢀisꢀnotꢀusedꢀforꢀanyꢀclockꢀsource,ꢀtheꢀXT1/XT2ꢀpinsꢀcanꢀbeꢀusedꢀasꢀnormalꢀ
I/Oꢀpins.
•ꢀ IfꢀtheꢀLXTꢀoscillatorꢀisꢀusedꢀforꢀanyꢀclockꢀsource,ꢀtheꢀ32.768kHzꢀcrystalꢀshouldꢀbeꢀconnectedꢀtoꢀ
theꢀXT1/XT2ꢀpins.
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1
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External LXT Oscillator
LXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
10pF
ꢅꢃ.768kHz
10pF
Note: 1. C1 and Cꢃ values aꢀe foꢀ guidanꢁe only.
ꢃ. RP=5MΩ~10MΩ is recommended.
32.768kHz Crystal Recommended Capacitor Values
Rev. 1.00
5ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
LXT Oscillator Low Power Function
TheꢀLXTꢀoscillatorꢀcanꢀfunctionꢀinꢀoneꢀofꢀtwoꢀmodes,ꢀtheꢀQuickꢀStartꢀModeꢀandꢀtheꢀLowꢀPowerꢀ
Mode.ꢀTheꢀmodeꢀselectionꢀisꢀexecutedꢀusingꢀtheꢀLXTLPꢀbitꢀinꢀtheꢀSMOD2ꢀregister.
• SMOD2 Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
LXTLP
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ"0"
LXPLP:ꢀLXTꢀLowꢀPowerꢀControl
0:ꢀQuickꢀStartꢀmode
1:ꢀLowꢀPowerꢀmode
AfterꢀpowerꢀonꢀtheꢀLXTLPꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀzeroꢀensuringꢀthatꢀtheꢀLXTꢀoscillatorꢀ
isꢀinꢀtheꢀQuickꢀStartꢀoperatingꢀmode.ꢀInꢀtheꢀQuickꢀStartꢀModeꢀtheꢀLXTꢀoscillatorꢀwillꢀpowerꢀupꢀ
andꢀstabiliseꢀquickly.ꢀHowever,ꢀafterꢀtheꢀLXTꢀoscillatorꢀhasꢀfullyꢀpoweredꢀupꢀitꢀcanꢀbeꢀplacedꢀ
intoꢀtheꢀLow-powerꢀmodeꢀbyꢀsettingꢀtheꢀLXTLPꢀbitꢀhigh.ꢀTheꢀoscillatorꢀwillꢀcontinueꢀtoꢀrunꢀbutꢀ
withꢀreducedꢀcurrentꢀconsumption,ꢀasꢀtheꢀhigherꢀcurrentꢀconsumptionꢀisꢀonlyꢀrequiredꢀduringꢀtheꢀ
LXTꢀoscillatorꢀstart-up.ꢀInꢀpowerꢀsensitiveꢀapplications,ꢀsuchꢀasꢀbatteryꢀapplications,ꢀwhereꢀpowerꢀ
consumptionꢀmustꢀbeꢀkeptꢀtoꢀaꢀminimum,ꢀitꢀisꢀthereforeꢀrecommendedꢀthatꢀtheꢀapplicationꢀprogramꢀ
setsꢀtheꢀLXTLPꢀbitꢀhighꢀaboutꢀ2ꢀsecondsꢀafterꢀpower-on.
Itꢀshouldꢀbeꢀnotedꢀthat,ꢀnoꢀmatterꢀwhatꢀconditionꢀtheꢀLXTLPꢀbitꢀisꢀsetꢀto,ꢀtheꢀLXTꢀoscillatorꢀwillꢀ
alwaysꢀfunctionꢀnormally,ꢀtheꢀonlyꢀdifferenceꢀisꢀthatꢀitꢀwillꢀtakeꢀmoreꢀtimeꢀtoꢀstartꢀupꢀifꢀinꢀtheꢀ
Low-powerꢀmode.
Internal Low Speed Oscillator – LIRC
TheꢀInternalꢀ32kHzꢀSystemꢀOscillatorꢀisꢀoneꢀofꢀtheꢀlowꢀfrequencyꢀoscillatorꢀchoices,ꢀwhichꢀisꢀ
selectedꢀviaꢀconfigurationꢀoption.ꢀItꢀisꢀaꢀfullyꢀintegratedꢀRCꢀoscillatorꢀwithꢀaꢀtypicalꢀfrequencyꢀofꢀ
32kHzꢀatꢀ5V,ꢀrequiringꢀnoꢀexternalꢀcomponentsꢀforꢀitsꢀimplementation.ꢀDeviceꢀtrimmingꢀduringꢀ
theꢀmanufacturingꢀprocessꢀandꢀtheꢀinclusionꢀofꢀinternalꢀfrequencyꢀcompensationꢀcircuitsꢀareꢀusedꢀ
toꢀensureꢀthatꢀtheꢀinfluenceꢀofꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀtemperatureꢀandꢀprocessꢀvariationsꢀonꢀtheꢀ
oscillationꢀfrequencyꢀareꢀminimised.ꢀAsꢀaꢀresult,ꢀatꢀaꢀpowerꢀsupplyꢀofꢀ5Vꢀandꢀatꢀaꢀtemperatureꢀofꢀ
25 Cꢀdegrees,ꢀtheꢀfixedꢀoscillationꢀfrequencyꢀofꢀ32kHzꢀwillꢀhaveꢀaꢀtoleranceꢀwithinꢀ3%.
°
Supplementary Oscillators
Theꢀlowꢀspeedꢀoscillators,ꢀinꢀadditionꢀtoꢀprovidingꢀaꢀsystemꢀclockꢀsourceꢀareꢀalsoꢀusedꢀtoꢀprovideꢀ
aꢀclockꢀsourceꢀtoꢀtwoꢀotherꢀdevicesꢀfunctions.ꢀTheseꢀareꢀtheꢀWatchdogꢀTimerꢀandꢀtheꢀTimeꢀBaseꢀ
Interrupts.
Rev. 1.00
54
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Operating Modes and System Clocks
Presentꢀdayꢀapplicationsꢀrequireꢀthatꢀtheirꢀmicrocontrollersꢀhaveꢀhighꢀperformanceꢀbutꢀoftenꢀstillꢀ
demandꢀthatꢀtheyꢀconsumeꢀasꢀlittleꢀpowerꢀasꢀpossible,ꢀconflictingꢀrequirementsꢀthatꢀareꢀespeciallyꢀ
trueꢀinꢀbatteryꢀpoweredꢀportableꢀapplications.ꢀTheꢀfastꢀclocksꢀrequiredꢀforꢀhighꢀperformanceꢀwillꢀ
byꢀtheirꢀnatureꢀincreaseꢀcurrentꢀconsumptionꢀandꢀofꢀcourseꢀviceꢀversa,ꢀlowerꢀspeedꢀclocksꢀreduceꢀ
currentꢀconsumption.ꢀAsꢀHoltekꢀhasꢀprovidedꢀtheseꢀdevicesꢀwithꢀbothꢀhighꢀandꢀlowꢀspeedꢀclockꢀ
sourcesꢀandꢀtheꢀmeansꢀtoꢀswitchꢀbetweenꢀthemꢀdynamically,ꢀtheꢀuserꢀcanꢀoptimiseꢀtheꢀoperationꢀofꢀ
theirꢀmicrocontrollerꢀtoꢀachieveꢀtheꢀbestꢀperformance/powerꢀratio.
System Clock
TheꢀdeviceꢀhasꢀmanyꢀdifferentꢀclockꢀsourcesꢀforꢀbothꢀtheꢀCPUꢀandꢀperipheralꢀfunctionꢀoperation.ꢀ
Byꢀprovidingꢀtheꢀuserꢀwithꢀaꢀwideꢀrangeꢀofꢀclockꢀoptionsꢀusingꢀconfigurationꢀoptionsꢀandꢀregisterꢀ
programming,ꢀaꢀclockꢀsystemꢀcanꢀbeꢀconfiguredꢀtoꢀobtainꢀmaximumꢀapplicationꢀperformance.
Theꢀmainꢀsystemꢀclock,ꢀcanꢀcomeꢀfromꢀeitherꢀaꢀhighꢀfrequency,ꢀfH,ꢀorꢀlowꢀfrequency,ꢀfSUB,ꢀsource,ꢀ
andꢀisꢀselectedꢀusingꢀtheꢀHLCLKꢀbitꢀandꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSMODꢀregister.ꢀTheꢀhighꢀspeedꢀ
systemꢀclockꢀcanꢀbeꢀsourcedꢀfromꢀanꢀHXT,ꢀERCꢀorꢀHIRCꢀoscillator,ꢀselectedꢀviaꢀaꢀconfigurationꢀ
option.ꢀTheꢀlowꢀspeedꢀsystemꢀclockꢀsourceꢀcanꢀbeꢀsourcedꢀfromꢀtheꢀclock,ꢀfSUB.ꢀIfꢀfSUBꢀisꢀselectedꢀ
thenꢀitꢀcanꢀbeꢀsourcedꢀbyꢀeitherꢀtheꢀLXTꢀorꢀLIRCꢀoscillators,ꢀselectedꢀviaꢀaꢀconfigurationꢀoption.ꢀ
Theꢀotherꢀchoice,ꢀwhichꢀisꢀaꢀdividedꢀversionꢀofꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀhasꢀaꢀrangeꢀofꢀ
fH/2~fH/64.
TheꢀfSUBꢀclockꢀisꢀusedꢀtoꢀprovideꢀaꢀsubstituteꢀclockꢀforꢀtheꢀmicrocontrollerꢀjustꢀafterꢀaꢀwake-upꢀhasꢀ
occurredꢀtoꢀenableꢀfasterꢀwake-upꢀtimes.ꢀTheꢀfSUBꢀclockꢀisꢀalsoꢀusedꢀtoꢀprovideꢀtheꢀclockꢀsourceꢀforꢀ
timeꢀbaseꢀandꢀwatchdogꢀtimerꢀfunctions.
Higꢂ Speed Osꢁillation
(HOSC)
fH/ꢃ
HXT
fH/4
fH/8
fH
ERC
Pꢀesꢁaleꢀ
fH/16
fSYS
f
H/ꢅꢃ
HIRC
fH/64
Fast Wake-up fꢀom SLEEP �ode oꢀ IDLE
�ode Contꢀol (foꢀ HXT only)
Higꢂ Speed Osꢁillation
Configuꢀation Option
CKS[ꢃ:0]ꢄ HLCLK
LIRC
LXT
fSUB
fSUB
WDT
fSUB
Low Speed Osꢁillation
(LOSC)
fH
fTP
Pꢀesꢁaleꢀ
Time Base
Low Speed Osꢁillation
Configuꢀation Option
fSYS
fSYS/4
CLKS0[1:0]
System Clock Configurations
Note:ꢀWhenꢀtheꢀsystemꢀclockꢀsourceꢀfSYSꢀisꢀswitchedꢀtoꢀfSUBꢀfromꢀfH,ꢀtheꢀhighꢀspeedꢀoscillationꢀwillꢀ
stopꢀtoꢀconserveꢀtheꢀpower.ꢀThusꢀthereꢀisꢀnoꢀfH~fH/64ꢀforꢀperipheralꢀcircuitꢀtoꢀuse.
Rev. 1.00
55
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
System Operation Modes
Thereꢀareꢀsixꢀdifferentꢀmodesꢀofꢀoperationꢀforꢀtheꢀmicrocontroller,ꢀeachꢀoneꢀwithꢀitsꢀownꢀ
specialꢀcharacteristicsꢀandꢀwhichꢀcanꢀbeꢀchosenꢀaccordingꢀtoꢀtheꢀspecificꢀperformanceꢀandꢀ
powerꢀrequirementsꢀofꢀtheꢀapplication.ꢀThereꢀareꢀtwoꢀmodesꢀallowingꢀnormalꢀoperationꢀofꢀtheꢀ
microcontroller,ꢀtheꢀNORMALꢀModeꢀandꢀSLOWꢀMode.ꢀTheꢀremainingꢀfourꢀmodes,ꢀtheꢀSLEEP0,ꢀ
SLEEP1,ꢀIDLE0ꢀandꢀIDLE1ꢀModeꢀareꢀusedꢀwhenꢀtheꢀmicrocontrollerꢀCPUꢀisꢀswitchedꢀoffꢀtoꢀ
conserveꢀpower.
Description
Operating Mode
CPU
On
On
Off
Off
Off
Off
fSYS
fH~fH/64
fSUB
fSUB
On
On
On
On
Off
On
NOR�AL �ode
SLOW �ode
IDLE0 �ode
Off
IDLE1 �ode
On
SLEEP0 �ode
SLEEP1 �ode
Off
Off
NORMAL Mode
Asꢀtheꢀnameꢀsuggestsꢀthisꢀisꢀoneꢀofꢀtheꢀmainꢀoperatingꢀmodesꢀwhereꢀtheꢀmicrocontrollerꢀhasꢀallꢀofꢀ
itsꢀfunctionsꢀoperationalꢀandꢀwhereꢀtheꢀsystemꢀclockꢀisꢀprovidedꢀbyꢀoneꢀofꢀtheꢀhighꢀspeedꢀoscillators.ꢀ
Thisꢀmodeꢀoperatesꢀallowingꢀtheꢀmicrocontrollerꢀtoꢀoperateꢀnormallyꢀwithꢀaꢀclockꢀsourceꢀwillꢀcomeꢀ
fromꢀoneꢀofꢀtheꢀhighꢀspeedꢀoscillators,ꢀeitherꢀtheꢀHXT,ꢀERCꢀorꢀHIRCꢀoscillators.ꢀTheꢀhighꢀspeedꢀ
oscillatorꢀwillꢀhoweverꢀfirstꢀbeꢀdividedꢀbyꢀaꢀratioꢀrangingꢀfromꢀ1ꢀtoꢀ64,ꢀtheꢀactualꢀratioꢀbeingꢀselectedꢀ
byꢀtheꢀCKS2~CKS0ꢀandꢀHLCLKꢀbitsꢀinꢀtheꢀSMODꢀregister.ꢀAlthoughꢀaꢀhighꢀspeedꢀoscillatorꢀisꢀ
used,ꢀrunningꢀtheꢀmicrocontrollerꢀatꢀaꢀdividedꢀclockꢀratioꢀreducesꢀtheꢀoperatingꢀcurrent.
SLOW Mode
Thisꢀisꢀalsoꢀaꢀmodeꢀwhereꢀtheꢀmicrocontrollerꢀoperatesꢀnormallyꢀalthoughꢀnowꢀwithꢀaꢀslowerꢀspeedꢀ
clockꢀsource.ꢀTheꢀclockꢀsourceꢀusedꢀwillꢀbeꢀfromꢀoneꢀofꢀtheꢀlowꢀspeedꢀoscillators,ꢀeitherꢀtheꢀLXTꢀ
orꢀtheꢀLIRC.ꢀRunningꢀtheꢀmicrocontrollerꢀinꢀthisꢀmodeꢀallowsꢀitꢀtoꢀrunꢀwithꢀmuchꢀlowerꢀoperatingꢀ
currents.ꢀInꢀtheꢀSLOWꢀMode,ꢀtheꢀfHꢀisꢀoff.
SLEEP0 Mode
TheꢀSLEEP0ꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀtheꢀIDLENꢀbitꢀinꢀtheꢀ
SMODꢀregisterꢀisꢀlow.ꢀInꢀtheꢀSLEEP0ꢀmodeꢀtheꢀCPUꢀwillꢀbeꢀstoppedꢀandꢀtheꢀfSUBꢀclockꢀwillꢀbeꢀ
stoppedꢀtoo,ꢀandꢀtheꢀWatchdogꢀTimerꢀfunctionꢀisꢀdisabled.ꢀInꢀthisꢀmode,ꢀtheꢀLVDENꢀisꢀmustꢀsetꢀtoꢀ“0”.ꢀ
IfꢀtheꢀLVDENꢀisꢀsetꢀtoꢀ“1”,ꢀitꢀwon’tꢀenterꢀtheꢀSLEEP0ꢀMode.
SLEEP1 Mode
TheꢀSLEEP1ꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀtheꢀIDLENꢀbitꢀinꢀtheꢀ
SMODꢀregisterꢀisꢀlow.ꢀInꢀtheꢀSLEEP1ꢀmodeꢀtheꢀCPUꢀwillꢀbeꢀstopped.ꢀHoweverꢀtheꢀfSUBꢀwillꢀ
continueꢀtoꢀoperateꢀifꢀtheꢀLVDENꢀisꢀ“1”ꢀorꢀtheꢀWatchdogꢀTimerꢀfunctionꢀisꢀenabled.
IDLE0 Mode
TheꢀIDLE0ꢀModeꢀisꢀenteredꢀwhenꢀaꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀIDLENꢀbitꢀinꢀtheꢀ
SMODꢀregisterꢀisꢀhighꢀandꢀtheꢀFSYSONꢀbitꢀinꢀtheꢀSMOD1ꢀregisterꢀisꢀlow.ꢀInꢀtheꢀIDLE0ꢀModeꢀtheꢀ
systemꢀoscillatorꢀwillꢀbeꢀinhibitedꢀfromꢀdrivingꢀtheꢀCPUꢀbutꢀsomeꢀperipheralꢀfunctionsꢀwillꢀremainꢀ
operationalꢀsuchꢀasꢀtheꢀWatchdogꢀTimerꢀandꢀTMs.ꢀInꢀtheꢀIDLE0ꢀMode,ꢀtheꢀsystemꢀoscillatorꢀwillꢀbeꢀ
stoppedꢀwhileꢀtheꢀfSUBꢀclockꢀwillꢀbeꢀon.
Rev. 1.00
56
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
IDLE1 Mode
TheꢀIDLE1ꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀIDLENꢀbitꢀinꢀtheꢀ
SMODꢀregisterꢀisꢀhighꢀandꢀtheꢀFSYSONꢀbitꢀinꢀtheꢀSMOD1ꢀregisterꢀisꢀhigh.ꢀInꢀtheꢀIDLE1ꢀModeꢀtheꢀ
systemꢀoscillatorꢀwillꢀbeꢀinhibitedꢀfromꢀdrivingꢀtheꢀCPUꢀbutꢀmayꢀcontinueꢀtoꢀprovideꢀaꢀclockꢀsourceꢀ
toꢀkeepꢀsomeꢀperipheralꢀfunctionsꢀoperationalꢀsuchꢀasꢀtheꢀWatchdogꢀTimerꢀandꢀTMs.ꢀInꢀtheꢀIDLE1ꢀ
Mode,ꢀtheꢀsystemꢀoscillatorꢀwillꢀcontinueꢀtoꢀrun,ꢀandꢀthisꢀsystemꢀoscillatorꢀmayꢀbeꢀhighꢀspeedꢀorꢀlowꢀ
speedꢀsystemꢀoscillator.ꢀInꢀtheꢀIDLE1ꢀModeꢀtheꢀfSUBꢀclockꢀwillꢀalsoꢀbeꢀon.
Control Register
Aꢀregisterꢀpair,ꢀSMODꢀandꢀSMOD1,ꢀisꢀusedꢀforꢀoverallꢀcontrolꢀofꢀtheꢀinternalꢀclocksꢀwithinꢀtheꢀ
device.
SMOD Register
Bit
Name
R/W
7
CKSꢃ
R/W
0
6
CKS1
R/W
0
5
CKS0
R/W
0
4
FSTEN
R/W
0
3
LTO
R
2
HTO
R
1
IDLEN
R/W
1
0
HLCLK
R/W
1
POR
0
0
Bitꢀ7~5ꢀ
CKS2~CKS0:ꢀTheꢀsystemꢀclockꢀselectionꢀwhenꢀHLCLKꢀisꢀ"0"
000:ꢀfSUBꢀ(fLXTꢀorꢀfLIRC
)
001:ꢀfSUBꢀ(fLXTꢀorꢀfLIRC
010:ꢀfH/64
011:ꢀfH/32
)
100:ꢀfH/16
101:ꢀfH/8
110:ꢀfH/4
111:ꢀfH/2
Theseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀwhichꢀclockꢀisꢀusedꢀasꢀtheꢀsystemꢀclockꢀsource.ꢀ
Inꢀadditionꢀtoꢀtheꢀsystemꢀclockꢀsource,ꢀwhichꢀcanꢀbeꢀeitherꢀtheꢀLXTꢀorꢀtheꢀLIRC,ꢀaꢀ
dividedꢀversionꢀofꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀcanꢀalsoꢀbeꢀchosenꢀasꢀtheꢀsystemꢀ
clockꢀsource.
Bitꢀ4
Bitꢀ3
FSTEN:ꢀFastꢀWake-upꢀControlꢀ(onlyꢀforꢀHXT)
0:ꢀDisable
1:ꢀEnable
ThisꢀisꢀtheꢀFastꢀWake-upꢀControlꢀbitꢀwhichꢀdeterminesꢀifꢀtheꢀfSUBꢀclockꢀsourceꢀisꢀ
initiallyꢀusedꢀafterꢀtheꢀdeviceꢀwakesꢀup.ꢀWhenꢀtheꢀbitꢀisꢀhigh,ꢀtheꢀfSUBꢀclockꢀsourceꢀcanꢀ
beꢀusedꢀasꢀaꢀtemporaryꢀsystemꢀclockꢀtoꢀprovideꢀaꢀfasterꢀwakeꢀupꢀtimeꢀasꢀtheꢀfSUBꢀclockꢀ
isꢀavailable.
LTO:ꢀLowꢀspeedꢀsystemꢀoscillatorꢀreadyꢀflag
0:ꢀNotꢀready
1:ꢀReady
Thisꢀisꢀtheꢀlowꢀspeedꢀsystemꢀoscillatorꢀreadyꢀflagꢀwhichꢀindicatesꢀwhenꢀtheꢀlowꢀspeedꢀ
systemꢀoscillatorꢀisꢀstableꢀafterꢀpowerꢀonꢀresetꢀorꢀaꢀwake-upꢀhasꢀoccurred.ꢀTheꢀflagꢀ
willꢀbeꢀlowꢀwhenꢀinꢀtheꢀSLEEP0ꢀModeꢀbutꢀafterꢀaꢀwake-upꢀhasꢀoccurred,ꢀtheꢀflagꢀwillꢀ
changeꢀtoꢀaꢀhighꢀlevelꢀafterꢀ1024ꢀclockꢀcyclesꢀifꢀtheꢀLXTꢀoscillatorꢀisꢀusedꢀorꢀ1~2ꢀ
clockꢀcyclesꢀisꢀtheꢀLIRCꢀoscillatorꢀisꢀused.
Rev. 1.00
57
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Bitꢀ2
HTO:ꢀHighꢀspeedꢀsystemꢀoscillatorꢀreadyꢀflagꢀ
0:ꢀNotꢀready
1:ꢀReady
Thisꢀisꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀreadyꢀflagꢀwhichꢀindicatesꢀwhenꢀtheꢀhighꢀspeedꢀ
systemꢀoscillatorꢀisꢀstable.ꢀThisꢀflagꢀisꢀclearedꢀtoꢀ“0”ꢀbyꢀhardwareꢀwhenꢀtheꢀdeviceꢀisꢀ
poweredꢀonꢀandꢀthenꢀchangesꢀtoꢀaꢀhighꢀlevelꢀafterꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀisꢀ
stable.ꢀThereforeꢀthisꢀflagꢀwillꢀalwaysꢀbeꢀreadꢀasꢀ“1”ꢀbyꢀtheꢀapplicationꢀprogramꢀafterꢀ
deviceꢀpower-on.ꢀTheꢀflagꢀwillꢀbeꢀlowꢀwhenꢀinꢀtheꢀSLEEPꢀorꢀIDLE0ꢀModeꢀbutꢀafterꢀ
aꢀwake-upꢀhasꢀoccurred,ꢀtheꢀflagꢀwillꢀchangeꢀtoꢀaꢀhighꢀlevelꢀafterꢀ1024ꢀclockꢀcyclesꢀ
ifꢀtheꢀHXTꢀoscillatorꢀisꢀusedꢀorꢀ15~16ꢀclockꢀcyclesꢀifꢀtheꢀERCꢀorꢀHIRCꢀoscillatorꢀisꢀ
used.
bitꢀ1
IDLEN:ꢀIDLEꢀModeꢀcontrol
0:ꢀDisable
1:ꢀEnable
ThisꢀisꢀtheꢀIDLEꢀModeꢀControlꢀbitꢀandꢀdeterminesꢀwhatꢀhappensꢀwhenꢀtheꢀHALTꢀ
instructionꢀisꢀexecuted.ꢀIfꢀthisꢀbitꢀisꢀhigh,ꢀwhenꢀaꢀHALTꢀinstructionꢀisꢀexecutedꢀtheꢀ
deviceꢀwillꢀenterꢀtheꢀIDLEꢀMode.ꢀInꢀtheꢀIDLE1ꢀModeꢀtheꢀCPUꢀwillꢀstopꢀrunningꢀ
butꢀtheꢀsystemꢀclockꢀwillꢀcontinueꢀtoꢀkeepꢀtheꢀperipheralꢀfunctionsꢀoperational,ꢀifꢀ
FSYSONꢀbitꢀisꢀhigh.ꢀIfꢀFSYSONꢀbitꢀisꢀlow,ꢀtheꢀCPUꢀandꢀtheꢀsystemꢀclockꢀwillꢀallꢀstopꢀ
inꢀIDLE0ꢀmode.ꢀIfꢀtheꢀbitꢀisꢀlowꢀtheꢀdeviceꢀwillꢀenterꢀtheꢀSLEEPꢀModeꢀwhenꢀaꢀHALTꢀ
instructionꢀisꢀexecuted.
bitꢀ0
HLCLK:ꢀsystemꢀclockꢀselection
0:ꢀfH/2~fH/64ꢀorꢀfSUB
1:ꢀfH
ThisꢀbitꢀisꢀusedꢀtoꢀselectꢀifꢀtheꢀfHꢀclockꢀorꢀtheꢀfH/2~fH/64ꢀorꢀfSUBꢀclockꢀisꢀusedꢀasꢀ
theꢀsystemꢀclock.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀfHꢀclockꢀwillꢀbeꢀselectedꢀandꢀifꢀlowꢀtheꢀ
fH/2~fH/64ꢀorꢀfSUBꢀclockꢀwillꢀbeꢀselected.ꢀWhenꢀsystemꢀclockꢀswitchesꢀfromꢀtheꢀfHꢀ
clockꢀtoꢀtheꢀfSUBꢀclockꢀandꢀtheꢀfHꢀclockꢀwillꢀbeꢀautomaticallyꢀswitchedꢀoffꢀtoꢀconserveꢀ
power.
Rev. 1.00
58
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SMOD1 Register
Bit
Name
R/W
7
FSYSON
R/W
6
5
4
3
2
LVRF
R/W
x
1
0
WRF
—
—
—
—
—
—
—
—
—
—
—
—
LRF
R/W
0
R/W
POR
0
0
“x”: unknown
Bitꢀ7ꢀ
FSYSON:ꢀfSYSꢀControlꢀinꢀIDLEꢀMode
0:ꢀDisable
1:ꢀEnable
Bitꢀ6~3ꢀ
Bitꢀ2
Unimplemented,ꢀreadꢀasꢀ"0"
LVRF:ꢀLVRꢀfunctionꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀwhenꢀaꢀspecificꢀLowꢀVoltageꢀResetꢀsituationꢀoccurs.ꢀThisꢀbitꢀcanꢀ
onlyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀtheꢀapplicationꢀprogram.
Bitꢀ1
bitꢀ0
LRF:ꢀLVRꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀifꢀtheꢀLVRCꢀregisterꢀcontainsꢀanyꢀnonꢀdefinedꢀLVRꢀvoltageꢀregisterꢀ
values.ꢀThisꢀinꢀeffectꢀactsꢀlikeꢀaꢀsoftware-resetꢀfunction.ꢀThisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ
0ꢀbyꢀtheꢀapplicationꢀprogram.
WRF:ꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀbyꢀtheꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ
applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀtheꢀapplicationꢀ
program.
Rev. 1.00
59
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Fast Wake-up
ToꢀminimiseꢀpowerꢀconsumptionꢀtheꢀdeviceꢀcanꢀenterꢀtheꢀSLEEPꢀorꢀIDLE0ꢀMode,ꢀwhereꢀtheꢀsystemꢀ
clockꢀsourceꢀtoꢀtheꢀdeviceꢀwillꢀbeꢀstopped.ꢀHoweverꢀwhenꢀtheꢀdeviceꢀisꢀwokenꢀupꢀagain,ꢀitꢀcanꢀtakeꢀ
aꢀconsiderableꢀtimeꢀforꢀtheꢀoriginalꢀsystemꢀoscillatorꢀtoꢀrestart,ꢀstabilizeꢀandꢀallowꢀnormalꢀoperationꢀ
toꢀresume.ꢀToꢀensureꢀtheꢀdeviceꢀisꢀupꢀandꢀrunningꢀasꢀfastꢀasꢀpossibleꢀaꢀFastꢀWake-upꢀfunctionꢀisꢀ
provided,ꢀwhichꢀallowsꢀfSUB,ꢀnamelyꢀeitherꢀtheꢀLXTꢀorꢀLIRCꢀoscillator,ꢀtoꢀactꢀasꢀaꢀtemporaryꢀclockꢀ
toꢀfirstꢀdriveꢀtheꢀsystemꢀuntilꢀtheꢀoriginalꢀsystemꢀoscillatorꢀhasꢀstabilised.ꢀAsꢀtheꢀclockꢀsourceꢀforꢀ
theꢀFastꢀWake-upꢀfunctionꢀisꢀfSUB,ꢀtheꢀFastꢀWake-upꢀfunctionꢀisꢀonlyꢀavailableꢀinꢀtheꢀSLEEP1ꢀandꢀ
IDLE0ꢀmodes.ꢀWhenꢀtheꢀdeviceꢀisꢀwokenꢀupꢀfromꢀtheꢀSLEEP0ꢀmode,ꢀtheꢀFastWake-upꢀfunctionꢀhasꢀ
noꢀeffectꢀbecauseꢀtheꢀfSUBꢀclockꢀisꢀstopped.ꢀTheꢀFastWake-upꢀenable/disableꢀfunctionꢀisꢀcontrolledꢀ
usingꢀtheꢀFSTENꢀbitꢀinꢀtheꢀSMOD1ꢀregister.
IfꢀtheꢀHXTꢀoscillatorꢀisꢀselectedꢀasꢀtheꢀNORMALꢀModeꢀsystemꢀclockꢀandꢀifꢀtheꢀFastꢀWake-upꢀ
functionꢀisꢀenabled,ꢀthenꢀitꢀwillꢀtakeꢀoneꢀtoꢀtwoꢀtSUBꢀclockꢀcyclesꢀofꢀtheꢀLXTꢀorꢀLIRCꢀoscillatorꢀforꢀ
theꢀsystemꢀtoꢀwake-up.ꢀTheꢀsystemꢀwillꢀthenꢀinitiallyꢀrunꢀunderꢀtheꢀfSUBꢀclockꢀsourceꢀuntilꢀ1024ꢀ
HXTꢀclockꢀcyclesꢀhaveꢀelapsed,ꢀatꢀwhichꢀpointꢀtheꢀHTOꢀflagꢀwillꢀswitchꢀhighꢀandꢀtheꢀsystemꢀwillꢀ
switchꢀoverꢀtoꢀoperatingꢀfromꢀtheꢀHXTꢀoscillator.ꢀ
IfꢀtheꢀERC/HIRCꢀorꢀLIRCꢀoscillatorꢀisꢀusedꢀasꢀtheꢀsystemꢀoscillator,ꢀthenꢀitꢀwillꢀtake15~16ꢀclockꢀ
cyclesꢀofꢀtheꢀERC/HIRCꢀoscillatorꢀorꢀ1~2ꢀclockꢀcyclesꢀofꢀtheꢀLIRCꢀosrillatorꢀrespectivelyꢀtoꢀwakeꢀ
upꢀtheꢀsystemꢀfromꢀtheꢀSLEEPꢀorꢀIDLE0ꢀMode.ꢀTheꢀFastꢀWake-upꢀbit,ꢀFSTENꢀwillꢀhaveꢀnoꢀeffectꢀ
inꢀtheseꢀcases.
System
Oscillator
FSTEN
Bit
Wake-up Time
(SLEEP0 Mode)
Wake-up Time
(SLEEP1 Mode)
Wake-up Time
(IDLE0 Mode)
Wake-up Time
(IDLE1 Mode)
0
10ꢃ4 HXT ꢁyꢁles 10ꢃ4 HXT ꢁyꢁles
1~ꢃ fSUB ꢁyꢁles
1~ꢃ HXT ꢁyꢁles
HXT
1
10ꢃ4 HXT ꢁyꢁles (System ꢀuns witꢂ fSUB first for 1024 HXT cycles and 1~ꢃ HXT ꢁyꢁles
tꢂen switꢁꢂes oveꢀ to ꢀun witꢂ tꢂe HXT ꢁloꢁk )
ERC
HIRC
LIRC
LXT
x
x
x
x
15~16 ERC ꢁyꢁles 15~16 ERC ꢁyꢁles
15~16 HIRC ꢁyꢁles 15~16 HIRC ꢁyꢁles
1~ꢃ LIRC ꢁyꢁles 1~ꢃ LIRC ꢁyꢁles
10ꢃ4 LXT ꢁyꢁles 10ꢃ4 LXT ꢁyꢁles
1~ꢃ ERC ꢁyꢁles
1~ꢃ HIRC ꢁyꢁles
1~ꢃ LIRC ꢁyꢁles
1~ꢃ LXT ꢁyꢁles
Wake-up Times
NoteꢀthatꢀifꢀtheꢀWatchdogꢀTimerꢀisꢀdisabled,ꢀwhichꢀmeansꢀthatꢀtheꢀfSUBꢀclockꢀderivedꢀfromꢀtheꢀLXTꢀ
orꢀLIRCꢀoscillatorꢀisꢀoff,ꢀthenꢀthereꢀwillꢀbeꢀnoꢀFastꢀWake-upꢀfunctionꢀavailableꢀwhenꢀtheꢀdeviceꢀ
wakesꢀupꢀfromꢀtheꢀSLEEP0ꢀMode.
Rev. 1.00
60
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Operating Mode Switching
Theꢀdeviceꢀcanꢀswitchꢀbetweenꢀoperatingꢀmodesꢀdynamicallyꢀallowingꢀtheꢀuserꢀtoꢀselectꢀtheꢀbestꢀ
performance/powerꢀratioꢀforꢀtheꢀpresentꢀtaskꢀinꢀhand.ꢀInꢀthisꢀwayꢀmicrocontrollerꢀoperationsꢀthatꢀ
doꢀnotꢀrequireꢀhighꢀperformanceꢀcanꢀbeꢀexecutedꢀusingꢀslowerꢀclocksꢀthusꢀrequiringꢀlessꢀoperatingꢀ
currentꢀandꢀprolongingꢀbatteryꢀlifeꢀinꢀportableꢀapplications.
Inꢀsimpleꢀterms,ꢀModeꢀSwitchingꢀbetweenꢀtheꢀNORMALꢀModeꢀandꢀSLOWꢀModeꢀisꢀexecutedꢀ
usingꢀtheꢀHLCLKꢀbitꢀandꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSMODꢀregisterꢀwhileꢀModeꢀSwitchingꢀfromꢀtheꢀ
NORMAL/SLOWꢀModesꢀtoꢀtheꢀSLEEP/IDLEꢀModesꢀisꢀexecutedꢀviaꢀtheꢀHALTꢀinstruction.ꢀWhenꢀ
aꢀHALTꢀinstructionꢀisꢀexecuted,ꢀwhetherꢀtheꢀdeviceꢀentersꢀtheꢀIDLEꢀModeꢀorꢀtheꢀSLEEPꢀModeꢀisꢀ
determinedꢀbyꢀtheꢀconditionꢀofꢀtheꢀIDLENꢀbitꢀinꢀtheꢀSMODꢀregisterꢀandꢀFSYSONꢀinꢀtheꢀSMOD1ꢀ
register.
WhenꢀtheꢀHLCLKꢀbitꢀswitchesꢀtoꢀaꢀlowꢀlevel,ꢀwhichꢀimpliesꢀthatꢀclockꢀsourceꢀisꢀswitchedꢀfromꢀtheꢀ
highꢀspeedꢀclockꢀsource,ꢀfH,ꢀtoꢀtheꢀclockꢀsource,ꢀfH/2~fH/64ꢀorꢀfSUB.ꢀIfꢀtheꢀclockꢀisꢀfromꢀtheꢀfSUB,ꢀtheꢀ
highꢀspeedꢀclockꢀsourceꢀwillꢀstopꢀrunningꢀtoꢀconserveꢀpower.ꢀWhenꢀthisꢀhappensꢀitꢀmustꢀbeꢀnotedꢀ
thatꢀtheꢀfH/16ꢀandꢀfH/64ꢀinternalꢀclockꢀsourcesꢀwillꢀalsoꢀstopꢀrunning,ꢀwhichꢀmayꢀaffectꢀtheꢀoperationꢀ
ofꢀotherꢀinternalꢀfunctionsꢀsuchꢀasꢀtheꢀTMs.ꢀTheꢀaccompanyingꢀflowchartꢀshowsꢀwhatꢀhappensꢀwhenꢀ
theꢀdeviceꢀmovesꢀbetweenꢀtheꢀvariousꢀoperatingꢀmodes.
I
L
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1
E
N
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A
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=
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H
~
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/
f
4
6
C
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P
s
o
t
p
f
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o
n
I
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1
=
C
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P
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n
u
F
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S
O
S
=
N
1
f
S
Y
S
o
n
f
S
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S
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f
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B
U
o
n
f
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P
0
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0
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f
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1
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f
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=
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p
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f
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L
V
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n
Rev. 1.00
61
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
NORMAL Mode to SLOW Mode Switching
WhenꢀrunningꢀinꢀtheꢀNORMALꢀMode,ꢀwhichꢀusesꢀtheꢀhighꢀspeedꢀsystemꢀoscillator,ꢀandꢀthereforeꢀ
consumesꢀmoreꢀpower,ꢀtheꢀsystemꢀclockꢀcanꢀswitchꢀtoꢀrunꢀinꢀtheꢀSLOWꢀModeꢀbyꢀsetꢀtheꢀHLCLKꢀbitꢀ
toꢀ“0”ꢀandꢀsetꢀtheꢀCKS2~CKS0ꢀbitsꢀtoꢀ“000”ꢀorꢀ“001”ꢀinꢀtheꢀSMODꢀregister.ꢀThisꢀwillꢀthenꢀuseꢀtheꢀ
lowꢀspeedꢀsystemꢀoscillatorꢀwhichꢀwillꢀconsumeꢀlessꢀpower.ꢀUsersꢀmayꢀdecideꢀtoꢀdoꢀthisꢀforꢀcertainꢀ
operationsꢀwhichꢀdoꢀnotꢀrequireꢀhighꢀperformanceꢀandꢀcanꢀsubsequentlyꢀreduceꢀpowerꢀconsumption.
TheꢀSLOWꢀModeꢀisꢀsourcedꢀfromꢀtheꢀLXTꢀorꢀtheꢀLIRCꢀoscillatorsꢀandꢀthereforeꢀrequiresꢀtheseꢀ
oscillatorsꢀtoꢀbeꢀstableꢀbeforeꢀfullꢀmodeꢀswitchingꢀoccurs.ꢀThisꢀisꢀmonitoredꢀusingꢀtheꢀLTOꢀbitꢀinꢀtheꢀ
SMODꢀregister.
N
R
O
M
A
L
M
o
e
d
C
H
S
K
2
~
C
K
S
=
0
0
0
B
&
x
C
L
K
L
=
0
S
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W
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W
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r
a
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f
f
I
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L
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=
0
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0
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W
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=
0
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S
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P
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1
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I
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=
1
,
F
S
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O
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=
N
0
H
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n
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M
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=
1
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F
S
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N
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1
=
O
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Rev. 1.00
6ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SLOW Mode to NORMAL Mode Switching
InꢀSLOWꢀModeꢀtheꢀsystemꢀusesꢀeitherꢀtheꢀLXTꢀorꢀLIRCꢀlowꢀspeedꢀsystemꢀoscillator.ꢀToꢀswitchꢀ
backꢀtoꢀtheꢀNORMALꢀMode,ꢀwhereꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀisꢀused,ꢀtheꢀHLCLKꢀbitꢀshouldꢀ
beꢀsetꢀtoꢀ“1”ꢀorꢀHLCLKꢀbitꢀisꢀ“0”,ꢀbutꢀCKS2~CKS0ꢀisꢀsetꢀtoꢀ“010”,ꢀ“011”,ꢀ“100”,ꢀ“101”,ꢀ“110”ꢀ
orꢀ“111”.ꢀAsꢀaꢀcertainꢀamountꢀofꢀtimeꢀwillꢀbeꢀrequiredꢀforꢀtheꢀhighꢀfrequencyꢀclockꢀtoꢀstabilise,ꢀ
theꢀstatusꢀofꢀtheꢀHTOꢀbitꢀisꢀchecked.ꢀTheꢀamountꢀofꢀtimeꢀrequiredꢀforꢀhighꢀspeedꢀsystemꢀoscillatorꢀ
stabilizationꢀdependsꢀuponꢀwhichꢀhighꢀspeedꢀsystemꢀoscillatorꢀtypeꢀisꢀused.
S
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1
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H
B
C
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L
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H
L
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C
=
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1
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f
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1
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I
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F
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O
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=
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0
H
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Rev. 1.00
6ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Entering the SLEEP0 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdeviceꢀtoꢀenterꢀtheꢀSLEEP0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ“0”ꢀandꢀtheꢀ
WDTꢀandꢀLVDꢀbothꢀoff.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀ
followingꢀwillꢀoccur:ꢀ
•ꢀ TheꢀsystemꢀclockꢀandꢀtheꢀfSUBꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ
“HALT”ꢀinstruction.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstoppedꢀasꢀtheꢀWDTꢀisꢀdisabled.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀflag,ꢀTO,ꢀ
willꢀbeꢀcleared.
Entering the SLEEP1 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdeviceꢀtoꢀenterꢀtheꢀSLEEP1ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ“0”ꢀandꢀtheꢀ
WDTꢀorꢀLVDꢀon.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀ
followingꢀwillꢀoccur:
•ꢀ Theꢀsystemꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ“HALT”ꢀ
instruction,ꢀbutꢀtheꢀWDTꢀorꢀLVDꢀwillꢀremainꢀwithꢀtheꢀclockꢀsourceꢀcomingꢀfromꢀtheꢀfSUBꢀclock.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀasꢀtheꢀWDTꢀisꢀenabledꢀandꢀitsꢀclockꢀsourceꢀisꢀ
derivedꢀfromꢀtheꢀfSUBꢀclock.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀflag,ꢀTO,ꢀ
willꢀbeꢀcleared.
Entering the IDLE0 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdeviceꢀtoꢀenterꢀtheꢀIDLE0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ“1”ꢀandꢀtheꢀ
FSYSONꢀbitꢀinꢀSMOD1ꢀregisterꢀequalꢀtoꢀ“0”.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀ
describedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:
•ꢀ Theꢀsystemꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ“HALT”ꢀ
instruction,ꢀbutꢀtheꢀfSUBꢀclockꢀwillꢀbeꢀon.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀasꢀtheꢀWDTꢀclockꢀsourceꢀisꢀderivedꢀfromꢀtheꢀfSUBꢀ
clock.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀflag,ꢀTO,ꢀ
willꢀbeꢀcleared.
Rev. 1.00
64
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Entering the IDLE1 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdeviceꢀtoꢀenterꢀtheꢀIDLE1ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ“1”ꢀandꢀtheꢀ
FSYSONꢀbitꢀinꢀSMOD1ꢀregisterꢀequalꢀtoꢀ“1”.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀ
describedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:
•ꢀ TheꢀsystemꢀclockꢀandꢀfSUBꢀclockꢀwillꢀbeꢀonꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ“HALT”ꢀ
instruction.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀasꢀtheꢀWDTꢀclockꢀsourceꢀisꢀderivedꢀfromꢀtheꢀfSUBꢀ
clock.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀflag,ꢀTO,ꢀ
willꢀbeꢀcleared.
Standby Current Considerations
AsꢀtheꢀmainꢀreasonꢀforꢀenteringꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀtoꢀkeepꢀtheꢀcurrentꢀconsumptionꢀofꢀ
theseꢀdevicesꢀtoꢀasꢀlowꢀaꢀvalueꢀasꢀpossible,ꢀperhapsꢀonlyꢀinꢀtheꢀorderꢀofꢀseveralꢀmicro-ampsꢀexceptꢀ
inꢀtheꢀIDLE1ꢀMode,ꢀthereꢀareꢀotherꢀconsiderationsꢀwhichꢀmustꢀalsoꢀbeꢀtakenꢀintoꢀaccountꢀbyꢀtheꢀ
circuitꢀdesignerꢀifꢀtheꢀpowerꢀconsumptionꢀisꢀtoꢀbeꢀminimised.ꢀSpecialꢀattentionꢀmustꢀbeꢀmadeꢀtoꢀ
theꢀI/Oꢀpinsꢀonꢀtheseꢀdevices.ꢀAllꢀhigh-impedanceꢀinputꢀpinsꢀmustꢀbeꢀconnectedꢀtoꢀeitherꢀaꢀfixedꢀ
highꢀorꢀlowꢀlevelꢀasꢀanyꢀfloatingꢀinputꢀpinsꢀcouldꢀcreateꢀinternalꢀoscillationsꢀandꢀresultꢀinꢀincreasedꢀ
currentꢀconsumption.ꢀThisꢀalsoꢀappliesꢀtoꢀdevicesꢀwhichꢀhaveꢀdifferentꢀpackageꢀtypes,ꢀasꢀthereꢀmayꢀ
beꢀunbondedꢀpins.ꢀTheseꢀmustꢀeitherꢀbeꢀsetupꢀasꢀoutputsꢀorꢀifꢀsetupꢀasꢀinputsꢀmustꢀhaveꢀpull-highꢀ
resistorsꢀconnected.
Careꢀmustꢀalsoꢀbeꢀtakenꢀwithꢀtheꢀloads,ꢀwhichꢀareꢀconnectedꢀtoꢀI/Oꢀpins,ꢀwhichꢀareꢀsetupꢀasꢀoutputs.ꢀ
Theseꢀshouldꢀbeꢀplacedꢀinꢀaꢀconditionꢀinꢀwhichꢀminimumꢀcurrentꢀisꢀdrawnꢀorꢀconnectedꢀonlyꢀtoꢀ
externalꢀcircuitsꢀthatꢀdoꢀnotꢀdrawꢀcurrent,ꢀsuchꢀasꢀotherꢀCMOSꢀinputs.ꢀAlsoꢀnoteꢀthatꢀadditionalꢀ
standbyꢀcurrentꢀwillꢀalsoꢀbeꢀrequiredꢀifꢀtheꢀconfigurationꢀoptionsꢀhaveꢀenabledꢀtheꢀLXTꢀorꢀLIRCꢀ
oscillator.
InꢀtheꢀIDLE1ꢀModeꢀtheꢀsystemꢀoscillatorꢀisꢀon,ꢀifꢀtheꢀsystemꢀoscillatorꢀisꢀfromꢀtheꢀhighꢀspeedꢀ
systemꢀoscillator,ꢀtheꢀadditionalꢀstandbyꢀcurrentꢀwillꢀalsoꢀbeꢀperhapsꢀinꢀtheꢀorderꢀofꢀseveralꢀhundredꢀ
micro-amps.
Rev. 1.00
65
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Wake-up
AfterꢀtheꢀsystemꢀentersꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀitꢀcanꢀbeꢀwokenꢀupꢀfromꢀoneꢀofꢀvariousꢀsourcesꢀ
listedꢀasꢀfollows:
•ꢀ Anꢀexternalꢀreset
•ꢀ AnꢀexternalꢀfallingꢀedgeꢀonꢀPortꢀA
•ꢀ Aꢀsystemꢀinterrupt
•ꢀ AꢀWDTꢀoverflow
Ifꢀtheꢀsystemꢀisꢀwokenꢀupꢀbyꢀanꢀexternalꢀreset,ꢀtheseꢀdevicesꢀwillꢀexperienceꢀaꢀfullꢀsystemꢀreset,ꢀ
however,ꢀifꢀtheseꢀdevicesꢀareꢀwokenꢀupꢀbyꢀaꢀWDTꢀoverflow,ꢀaꢀWatchdogꢀTimerꢀresetꢀwillꢀbeꢀ
initiated.ꢀAlthoughꢀbothꢀofꢀtheseꢀwake-upꢀmethodsꢀwillꢀinitiateꢀaꢀresetꢀoperation,ꢀtheꢀactualꢀsourceꢀ
ofꢀtheꢀwake-upꢀcanꢀbeꢀdeterminedꢀbyꢀexaminingꢀtheꢀTOꢀandꢀPDFꢀflags.ꢀTheꢀPDFꢀflagꢀisꢀclearedꢀbyꢀaꢀ
systemꢀpower-upꢀorꢀexecutingꢀtheꢀclearꢀWatchdogꢀTimerꢀinstructionsꢀandꢀisꢀsetꢀwhenꢀexecutingꢀtheꢀ
“HALT”ꢀinstruction.ꢀTheꢀTOꢀflagꢀisꢀsetꢀifꢀaꢀWDTꢀtime-outꢀoccurs,ꢀandꢀcausesꢀaꢀwake-upꢀthatꢀonlyꢀ
resetsꢀtheꢀProgramꢀCounterꢀandꢀStackꢀPointer,ꢀtheꢀotherꢀflagsꢀremainꢀinꢀtheirꢀoriginalꢀstatus.
EachꢀpinꢀonꢀPortꢀAꢀcanꢀbeꢀsetupꢀusingꢀtheꢀPAWUꢀregisterꢀtoꢀpermitꢀaꢀnegativeꢀtransitionꢀonꢀtheꢀpinꢀ
toꢀwake-upꢀtheꢀsystem.ꢀWhenꢀaꢀPortꢀAꢀpinꢀwake-upꢀoccurs,ꢀtheꢀprogramꢀwillꢀresumeꢀexecutionꢀatꢀ
theꢀinstructionꢀfollowingꢀtheꢀ“HALT”ꢀinstruction.ꢀIfꢀtheꢀsystemꢀisꢀwokenꢀupꢀbyꢀanꢀinterrupt,ꢀthenꢀ
twoꢀpossibleꢀsituationsꢀmayꢀoccur.ꢀTheꢀfirstꢀisꢀwhereꢀtheꢀrelatedꢀinterruptꢀisꢀdisabledꢀorꢀtheꢀinterruptꢀ
isꢀenabledꢀbutꢀtheꢀstackꢀisꢀfull,ꢀinꢀwhichꢀcaseꢀtheꢀprogramꢀwillꢀresumeꢀexecutionꢀatꢀtheꢀinstructionꢀ
followingꢀtheꢀ“HALT”ꢀinstruction.ꢀInꢀthisꢀsituation,ꢀtheꢀinterruptꢀwhichꢀwoke-upꢀtheseꢀdevicesꢀwillꢀ
notꢀbeꢀimmediatelyꢀserviced,ꢀbutꢀwillꢀratherꢀbeꢀservicedꢀlaterꢀwhenꢀtheꢀrelatedꢀinterruptꢀisꢀfinallyꢀ
enabledꢀorꢀwhenꢀaꢀstackꢀlevelꢀbecomesꢀfree.ꢀTheꢀotherꢀsituationꢀisꢀwhereꢀtheꢀrelatedꢀinterruptꢀisꢀ
enabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀinꢀwhichꢀcaseꢀtheꢀregularꢀinterruptꢀresponseꢀtakesꢀplace.ꢀIfꢀanꢀ
interruptꢀrequestꢀflagꢀisꢀsetꢀhighꢀbeforeꢀenteringꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀtheꢀwake-upꢀfunctionꢀofꢀ
theꢀrelatedꢀinterruptꢀwillꢀbeꢀdisabled.
Programming Considerations
TheꢀHXTꢀandꢀLXTꢀoscillatorsꢀbothꢀuseꢀtheꢀsameꢀSSTꢀcounter.ꢀForꢀexample,ꢀifꢀtheꢀsystemꢀisꢀwokenꢀ
upꢀfromꢀtheꢀSLEEP0ꢀModeꢀandꢀbothꢀtheꢀHXTꢀandꢀLXTꢀoscillatorsꢀneedꢀtoꢀstart-upꢀfromꢀanꢀoffꢀstate.ꢀ
TheꢀLXTꢀoscillatorꢀusesꢀtheꢀSSTꢀcounterꢀafterꢀHXTꢀoscillatorꢀhasꢀfinishedꢀitsꢀSSTꢀperiod.
•ꢀ IfꢀtheꢀdeviceꢀisꢀwokenꢀupꢀfromꢀtheꢀSLEEP0ꢀModeꢀtoꢀtheꢀNORMALꢀMode,ꢀtheꢀhighꢀspeedꢀsystemꢀ
oscillatorꢀneedsꢀanꢀSSTꢀperiod.ꢀTheꢀdeviceꢀwillꢀexecuteꢀfirstꢀinstructionꢀafterꢀHTOꢀisꢀ"1".ꢀAtꢀ
thisꢀtime,ꢀtheꢀLXTꢀoscillatorꢀmayꢀnotꢀbeꢀstableꢀifꢀfSUBꢀisꢀfromꢀLXTꢀoscillator.ꢀTheꢀsameꢀsituationꢀ
occursꢀinꢀtheꢀpower-onꢀstate.ꢀTheꢀLXTꢀoscillatorꢀisꢀnotꢀreadyꢀyetꢀwhenꢀtheꢀfirstꢀinstructionꢀisꢀ
executed.
•ꢀ IfꢀtheꢀdeviceꢀisꢀwokenꢀupꢀfromꢀtheꢀSLEEP1ꢀModeꢀtoꢀNORMALꢀMode,ꢀandꢀtheꢀsystemꢀclockꢀ
sourceꢀisꢀfromꢀHXTꢀoscillatorꢀandꢀFSTENꢀisꢀ“1”,ꢀtheꢀsystemꢀclockꢀcanꢀbeꢀswitchedꢀtoꢀtheꢀLXTꢀ
orꢀLIRCꢀoscillatorꢀafterꢀwakeꢀup.ꢀ
•ꢀ Thereꢀareꢀperipheralꢀfunctions,ꢀsuchꢀasꢀWDTꢀandꢀTMs,ꢀforꢀwhichꢀtheꢀfSYSꢀisꢀused.ꢀIfꢀtheꢀsystemꢀ
clockꢀsourceꢀisꢀswitchedꢀfromꢀfHꢀtoꢀfSUB,ꢀtheꢀclockꢀsourceꢀtoꢀtheꢀperipheralꢀfunctionsꢀmentionedꢀ
aboveꢀwillꢀchangeꢀaccordingly.
•ꢀ Theꢀon/offꢀconditionꢀofꢀfSUBꢀdependsꢀuponꢀwhetherꢀtheꢀWDTꢀisꢀenabledꢀorꢀdisabledꢀasꢀtheꢀWDTꢀ
clockꢀsourceꢀisꢀselectedꢀfromꢀfSUB
.
Rev. 1.00
66
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Watchdog Timer
TheꢀWatchdogꢀTimerꢀisꢀprovidedꢀtoꢀpreventꢀprogramꢀmalfunctionsꢀorꢀsequencesꢀfromꢀjumpingꢀtoꢀ
unknownꢀlocations,ꢀdueꢀtoꢀcertainꢀuncontrollableꢀexternalꢀeventsꢀsuchꢀasꢀelectricalꢀnoise.
Watchdog Timer Clock Source
TheꢀWatchdogꢀTimerꢀclockꢀsourceꢀisꢀprovidedꢀbyꢀtheꢀfSUBꢀclock.ꢀTheꢀfSUBꢀclockꢀcanꢀbeꢀsourcedꢀfromꢀ
eitherꢀtheꢀLXTꢀorꢀLIRCꢀoscillatorꢀselectedꢀbyꢀaꢀconfigurationꢀoption.ꢀTheꢀLIRCꢀinternalꢀoscillatorꢀ
hasꢀanꢀapproximateꢀfrequencyꢀofꢀ32kHzꢀandꢀthisꢀspecifiedꢀinternalꢀclockꢀperiodꢀcanꢀvaryꢀwithꢀVDD,ꢀ
temperatureꢀandꢀprocessꢀvariations.ꢀTheꢀLXTꢀoscillatorꢀisꢀsuppliedꢀbyꢀanꢀexternalꢀ32.768kHzꢀcrystal.ꢀ
TheꢀWatchdogꢀTimerꢀsourceꢀclockꢀisꢀthenꢀsubdividedꢀbyꢀaꢀratioꢀofꢀ28ꢀtoꢀ218ꢀtoꢀgiveꢀlongerꢀtimeouts,ꢀ
theꢀactualꢀvalueꢀbeingꢀchosenꢀusingꢀtheꢀWS2~WS0ꢀbitsꢀinꢀtheꢀWDTCꢀregister.
Watchdog Timer Control Register
Aꢀsingleꢀregister,ꢀWDTC,ꢀcontrolsꢀtheꢀrequiredꢀtimeoutꢀperiodꢀasꢀwellꢀasꢀtheꢀenable/disableꢀ
operation.ꢀThisꢀregisterꢀcontrolsꢀtheꢀoverallꢀoperationꢀofꢀtheꢀWatchdogꢀTimer.
WDTC Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
WE4
R/W
0
WEꢅ
R/W
1
WEꢃ
R/W
0
WE1
R/W
1
WE0
R/W
0
WSꢃ
R/W
0
WS1
R/W
1
WS0
R/W
1
POR
Bitꢀ7~3ꢀ
WE4~WE0:ꢀWDTꢀfunctionꢀenableꢀcontrol
10101:ꢀDisabled
01010:ꢀEnabled
OtherꢀValues:ꢀResetꢀMCU
Ifꢀtheseꢀbitsꢀareꢀchangedꢀdueꢀtoꢀadverseꢀenvironmentalꢀconditions,ꢀtheꢀmicrocontrollerꢀ
willꢀbeꢀreset.ꢀTheꢀresetꢀoperationꢀwillꢀbeꢀactivatedꢀafterꢀ2~3ꢀLIRCꢀclockꢀcyclesꢀandꢀtheꢀ
WRFꢀbitꢀinꢀtheꢀSMOD1ꢀregisterꢀwillꢀbeꢀsetꢀtoꢀ1.
Bitꢀ2~0
WS2~WS0:ꢀSelectꢀWDTꢀTimeoutꢀPeriod
000:ꢀ28/fSUB
001:ꢀ210/fSUB
010:ꢀ212/fSUB
011:ꢀ214/fSUB
100:ꢀ215/fSUB
101:ꢀ216/fSUB
110:ꢀ217/fSUB
111:ꢀ218/fSUB
TheseꢀthreeꢀbitsꢀdetermineꢀtheꢀdivisionꢀratioꢀofꢀtheꢀWatchdogꢀTimerꢀsourceꢀclock,ꢀ
whichꢀinꢀturnꢀdeterminesꢀtheꢀtimeoutꢀperiod.
Rev. 1.00
67
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SMOD1 Register
Bit
7
6
5
4
3
2
LVRF
R/W
x
1
0
WRF
Name
R/W
FSYSON
—
—
—
—
—
—
—
—
—
—
—
—
LRF
R/W
0
R/W
0
R/W
POR
0
“x”: unknown
Bitꢀ7ꢀ
FSYSON:ꢀfSYSꢀControlꢀinꢀIDLEꢀMode
Describedꢀelsewhere
Bitꢀ6~3ꢀ
Bitꢀ2
Unimplemented,ꢀreadꢀasꢀ"0"
LVRF:ꢀLVRꢀfunctionꢀresetꢀflag
Describedꢀelsewhere
Bitꢀ1
bitꢀ0
LRF:ꢀLVRꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
Describedꢀelsewhere
WRF:ꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀbyꢀtheꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ
applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀtheꢀapplicationꢀ
program.
Watchdog Timer Operation
TheꢀWatchdogꢀTimerꢀoperatesꢀbyꢀprovidingꢀaꢀdeviceꢀresetꢀwhenꢀitsꢀtimerꢀoverflows.ꢀThisꢀmeansꢀ
thatꢀinꢀtheꢀapplicationꢀprogramꢀandꢀduringꢀnormalꢀoperationꢀtheꢀuserꢀhasꢀtoꢀstrategicallyꢀclearꢀtheꢀ
WatchdogꢀTimerꢀbeforeꢀitꢀoverflowsꢀtoꢀpreventꢀtheꢀWatchdogꢀTimerꢀfromꢀexecutingꢀaꢀreset.ꢀThisꢀisꢀ
doneꢀusingꢀtheꢀclearꢀwatchdogꢀinstructions.ꢀIfꢀtheꢀprogramꢀmalfunctionsꢀforꢀwhateverꢀreason,ꢀjumpsꢀ
toꢀanꢀunknownꢀlocation,ꢀorꢀentersꢀanꢀendlessꢀloop,ꢀtheseꢀclearꢀinstructionsꢀwillꢀnotꢀbeꢀexecutedꢀinꢀtheꢀ
correctꢀmanner,ꢀinꢀwhichꢀcaseꢀtheꢀWatchdogꢀTimerꢀwillꢀoverflowꢀandꢀresetꢀtheꢀdevice.ꢀWithꢀregardꢀtoꢀ
theꢀWatchdogꢀTimerꢀenable/disableꢀfunction,ꢀthereꢀareꢀfiveꢀbits,ꢀWE4~WE0,ꢀinꢀtheꢀWDTCꢀregisterꢀ
toꢀofferꢀtheꢀenable/disableꢀcontrolꢀandꢀresetꢀcontrolꢀofꢀtheꢀWatchdogꢀTimer.ꢀTheꢀWDTꢀfunctionꢀwillꢀ
beꢀdisabledꢀwhenꢀtheꢀWE4~WE0ꢀbitsꢀareꢀsetꢀtoꢀaꢀvalueꢀofꢀ10101BꢀwhileꢀtheꢀWDTꢀfunctionꢀwillꢀ
beꢀenabledꢀifꢀtheꢀWE4~WE0ꢀbitsꢀareꢀequalꢀtoꢀ01010B.ꢀIfꢀtheꢀWE4~WE0ꢀbitsꢀareꢀsetꢀtoꢀanyꢀotherꢀ
values,ꢀotherꢀthanꢀ01010Bꢀandꢀ10101B,ꢀitꢀwillꢀresetꢀtheꢀdeviceꢀafterꢀ2~3ꢀfSUBꢀclockꢀcycles.ꢀAfterꢀ
powerꢀonꢀtheseꢀbitsꢀwillꢀhaveꢀaꢀvalueꢀofꢀ01010B.
WDT Function Control
WE4~WE0 Bits
10101B
WDT Function
Disable
Appliꢁation Pꢀogꢀam Enabled
01010B
Enable
Any otꢂeꢀ value
Reset �CU
Watchdog Timer Enable/Disable Control
Rev. 1.00
68
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Underꢀnormalꢀprogramꢀoperation,ꢀaꢀWatchdogꢀTimerꢀtime-outꢀwillꢀinitialiseꢀaꢀdeviceꢀresetꢀandꢀsetꢀ
theꢀstatusꢀbitꢀTO.ꢀHowever,ꢀifꢀtheꢀsystemꢀisꢀinꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀwhenꢀaꢀWatchdogꢀTimerꢀ
time-outꢀoccurs,ꢀtheꢀTOꢀbitꢀinꢀtheꢀstatusꢀregisterꢀwillꢀbeꢀsetꢀandꢀonlyꢀtheꢀProgramꢀCounterꢀandꢀStackꢀ
Pointerꢀwillꢀbeꢀreset.ꢀThreeꢀmethodsꢀcanꢀbeꢀadoptedꢀtoꢀclearꢀtheꢀcontentsꢀofꢀtheꢀWatchdogꢀTimer.ꢀ
TheꢀfirstꢀisꢀaꢀWDTꢀreset,ꢀwhichꢀmeansꢀaꢀcertainꢀvalueꢀexceptꢀ01010Bꢀandꢀ10101Bꢀwrittenꢀintoꢀtheꢀ
WE4~WE0ꢀfield,ꢀtheꢀsecondꢀisꢀusingꢀtheꢀWatchdogꢀTimerꢀsoftwareꢀclearꢀinstructionꢀandꢀtheꢀthirdꢀisꢀ
viaꢀaꢀHALTꢀinstruction.
ThereꢀisꢀonlyꢀoneꢀmethodꢀofꢀusingꢀsoftwareꢀinstructionꢀtoꢀclearꢀtheꢀWatchdogꢀTimer.ꢀThatꢀisꢀtoꢀuseꢀ
theꢀsingleꢀ“CLRꢀWDT”ꢀinstructionꢀtoꢀclearꢀtheꢀWDTꢀcontents.
Theꢀmaximumꢀtimeꢀoutꢀperiodꢀisꢀwhenꢀtheꢀ218ꢀdivisionꢀratioꢀisꢀselected.ꢀAsꢀanꢀexample,ꢀwithꢀaꢀ
32kHzꢀLIRCꢀoscillatorꢀasꢀitsꢀsourceꢀclock,ꢀthisꢀwillꢀgiveꢀaꢀmaximumꢀwatchdogꢀperiodꢀofꢀaroundꢀ8ꢀ
secondꢀforꢀtheꢀ218ꢀdivisionꢀratio,ꢀandꢀaꢀminimumꢀtimeoutꢀofꢀ7.8msꢀforꢀtheꢀ28ꢀdivisionꢀration.
WDTC Registeꢀ WE4~WE0 bits
Reset �CU
CLR
“CLR WDT”Instꢀuꢁtion
fS/ꢃ8
�
U
X
LXT
fSUB
8-stage Divideꢀ
WDT Pꢀesꢁaleꢀ
LIRC
Low Speed Osꢁillatoꢀ
Configuꢀation option
WSꢃ~WS0
8-to-1 �UX
WDT Time-out
(ꢃ8/fS ~ ꢃ18/fS)
(fS/ꢃ8 ~ fS/ꢃ18)
Watchdog Timer
Rev. 1.00
69
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Reset and Initialisation
Aꢀresetꢀfunctionꢀisꢀaꢀfundamentalꢀpartꢀofꢀanyꢀmicrocontrollerꢀensuringꢀthatꢀtheꢀdeviceꢀcanꢀbeꢀsetꢀ
toꢀsomeꢀpredeterminedꢀconditionꢀirrespectiveꢀofꢀoutsideꢀparameters.ꢀTheꢀmostꢀimportantꢀresetꢀ
conditionꢀisꢀafterꢀpowerꢀisꢀfirstꢀappliedꢀtoꢀtheꢀmicrocontroller.ꢀInꢀthisꢀcase,ꢀinternalꢀcircuitryꢀwillꢀ
ensureꢀthatꢀtheꢀmicrocontroller,ꢀafterꢀaꢀshortꢀdelay,ꢀwillꢀbeꢀinꢀaꢀwellꢀdefinedꢀstateꢀandꢀreadyꢀtoꢀ
executeꢀtheꢀfirstꢀprogramꢀinstruction.ꢀAfterꢀthisꢀpower-onꢀreset,ꢀcertainꢀimportantꢀinternalꢀregistersꢀ
willꢀbeꢀsetꢀtoꢀdefinedꢀstatesꢀbeforeꢀtheꢀprogramꢀcommences.ꢀOneꢀofꢀtheseꢀregistersꢀisꢀtheꢀProgramꢀ
Counter,ꢀwhichꢀwillꢀbeꢀresetꢀtoꢀzeroꢀforcingꢀtheꢀmicrocontrollerꢀtoꢀbeginꢀprogramꢀexecutionꢀfromꢀtheꢀ
lowestꢀProgramꢀMemoryꢀaddress.
Inꢀadditionꢀtoꢀtheꢀpower-onꢀreset,ꢀsituationsꢀmayꢀariseꢀwhereꢀitꢀisꢀnecessaryꢀtoꢀforcefullyꢀapplyꢀaꢀ
resetꢀconditionꢀwhenꢀtheꢀꢀisꢀrunning.ꢀOneꢀexampleꢀofꢀthisꢀisꢀwhereꢀafterꢀpowerꢀhasꢀbeenꢀappliedꢀ
andꢀtheꢀꢀisꢀalreadyꢀrunning,ꢀtheꢀRESꢀlineꢀisꢀforcefullyꢀpulledꢀlow.ꢀInꢀsuchꢀaꢀcase,ꢀknownꢀasꢀaꢀnormalꢀ
operationꢀreset,ꢀsomeꢀofꢀtheꢀꢀregistersꢀremainꢀunchangedꢀallowingꢀtheꢀꢀtoꢀproceedꢀwithꢀnormalꢀ
operationꢀafterꢀtheꢀresetꢀlineꢀisꢀallowedꢀtoꢀreturnꢀhigh.
AnotherꢀtypeꢀofꢀresetꢀisꢀwhenꢀtheꢀWatchdogꢀTimerꢀoverflowsꢀandꢀresetsꢀtheꢀmicrocontroller.ꢀAllꢀ
typesꢀofꢀresetꢀoperationsꢀresultꢀinꢀdifferentꢀregisterꢀconditionsꢀbeingꢀsetup.ꢀAnotherꢀresetꢀexistsꢀinꢀ
theꢀformꢀofꢀaꢀLowꢀVoltageꢀReset,ꢀLVR,ꢀwhereꢀaꢀfullꢀreset,ꢀsimilarꢀtoꢀtheꢀRESꢀresetꢀisꢀimplementedꢀinꢀ
situationsꢀwhereꢀtheꢀpowerꢀsupplyꢀvoltageꢀfallsꢀbelowꢀaꢀcertainꢀthreshold.
Reset Functions
Thereꢀareꢀfiveꢀwaysꢀinꢀwhichꢀaꢀmicrocontrollerꢀresetꢀcanꢀoccur,ꢀthroughꢀeventsꢀoccurringꢀbothꢀ
internallyꢀandꢀexternally:
Power-on Reset
Theꢀmostꢀfundamentalꢀandꢀunavoidableꢀresetꢀisꢀtheꢀoneꢀthatꢀoccursꢀafterꢀpowerꢀisꢀfirstꢀappliedꢀtoꢀ
theꢀmicrocontroller.ꢀAsꢀwellꢀasꢀensuringꢀthatꢀtheꢀProgramꢀMemoryꢀbeginsꢀexecutionꢀfromꢀtheꢀfirstꢀ
memoryꢀaddress,ꢀaꢀpower-onꢀresetꢀalsoꢀensuresꢀthatꢀcertainꢀotherꢀregistersꢀareꢀpresetꢀtoꢀknownꢀ
conditions.ꢀAllꢀtheꢀI/Oꢀportꢀandꢀportꢀcontrolꢀregistersꢀwillꢀpowerꢀupꢀinꢀaꢀhighꢀconditionꢀensuringꢀthatꢀ
allꢀpinsꢀwillꢀbeꢀfirstꢀsetꢀtoꢀinputs.
V
D
D
0
9
.
V
D
D
R
S
E
t
R
T
S
D
+
t
S
S
T
t
n
r
e
n
a
R
e
l
e
s
t
Note:ꢀtRSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=50ms
Power-on Reset Timing Chart
Rev. 1.00
70
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
RES Pin
AsꢀtheꢀresetꢀpinꢀisꢀsharedꢀwithꢀPB.0,ꢀtheꢀresetꢀfunctionꢀmustꢀbeꢀselectedꢀusingꢀaꢀconfigurationꢀ
option.ꢀAlthoughꢀtheꢀmicrocontrollerꢀhasꢀanꢀinternalꢀRCꢀresetꢀfunction,ꢀifꢀtheꢀVDDꢀpowerꢀsupplyꢀ
riseꢀtimeꢀisꢀnotꢀfastꢀenoughꢀorꢀdoesꢀnotꢀstabiliseꢀquicklyꢀatꢀpower-on,ꢀtheꢀinternalꢀresetꢀfunctionꢀ
mayꢀbeꢀincapableꢀofꢀprovidingꢀproperꢀresetꢀoperation.ꢀForꢀthisꢀreasonꢀitꢀisꢀrecommendedꢀthatꢀanꢀ
externalꢀRCꢀnetworkꢀisꢀconnectedꢀtoꢀtheꢀRESꢀpin,ꢀwhoseꢀadditionalꢀtimeꢀdelayꢀwillꢀensureꢀthatꢀtheꢀ
RESꢀpinꢀremainsꢀlowꢀforꢀanꢀextendedꢀperiodꢀtoꢀallowꢀtheꢀpowerꢀsupplyꢀtoꢀstabilise.ꢀDuringꢀthisꢀtimeꢀ
delay,ꢀnormalꢀoperationꢀofꢀtheꢀmicrocontrollerꢀwillꢀbeꢀinhibited.ꢀAfterꢀtheꢀRESꢀlineꢀreachesꢀaꢀcertainꢀ
voltageꢀvalue,ꢀtheꢀresetꢀdelayꢀtimeꢀtRSTDꢀisꢀinvokedꢀtoꢀprovideꢀanꢀextraꢀdelayꢀtimeꢀafterꢀwhichꢀtheꢀ
microcontrollerꢀwillꢀbeginꢀnormalꢀoperation.ꢀTheꢀabbreviationꢀSSTꢀinꢀtheꢀfiguresꢀstandsꢀforꢀSystemꢀ
Start-upꢀTimer.
ForꢀmostꢀapplicationsꢀaꢀresistorꢀconnectedꢀbetweenꢀVDDꢀandꢀtheꢀRESꢀpinꢀandꢀaꢀcapacitorꢀconnectedꢀ
betweenꢀVSSꢀandꢀtheꢀRESꢀpinꢀwillꢀprovideꢀaꢀsuitableꢀexternalꢀresetꢀcircuit.ꢀAnyꢀwiringꢀconnectedꢀtoꢀ
theꢀRESꢀpinꢀshouldꢀbeꢀkeptꢀasꢀshortꢀasꢀpossibleꢀtoꢀminimiseꢀanyꢀstrayꢀnoiseꢀinterference.
ForꢀapplicationsꢀthatꢀoperateꢀwithinꢀanꢀenvironmentꢀwhereꢀmoreꢀnoiseꢀisꢀpresentꢀtheꢀEnhancedꢀResetꢀ
Circuitꢀshownꢀisꢀrecommended.
V
D
D
0
0
.
1
F
*
*
V
D
D
1
4
N
1
*
4
8
1
k
0
W
~
1
0
W
0
k
P
B
R
0
S
E
/
3
0
0
W
*
0
1
.
1
~
F
V
S
S
Note:ꢀ*ꢀItꢀisꢀrecommendedꢀthatꢀthisꢀcomponentꢀisꢀaddedꢀforꢀaddedꢀESDꢀprotection.
**ꢀItꢀisꢀrecommendedꢀthatꢀthisꢀcomponentꢀisꢀaddedꢀinꢀenvironmentsꢀwhereꢀpowerꢀ
lineꢀnoiseꢀisꢀsignificant.
Extern RES Circuit
MoreꢀinformationꢀregardingꢀexternalꢀresetꢀcircuitsꢀisꢀlocatedꢀinꢀApplicationꢀNoteꢀHA0075Eꢀonꢀtheꢀ
Holtekꢀwebsite.
PullingꢀtheꢀRESꢀPinꢀlowꢀusingꢀexternalꢀhardwareꢀwillꢀalsoꢀexecuteꢀaꢀdeviceꢀreset.ꢀInꢀthisꢀcase,ꢀasꢀinꢀ
theꢀcaseꢀofꢀotherꢀresets,ꢀtheꢀProgramꢀCounterꢀwillꢀresetꢀtoꢀzeroꢀandꢀprogramꢀexecutionꢀinitiatedꢀfromꢀ
thisꢀpoint.
0
9
.
V
D
D
0
4
.
V
D
D
R
S
E
t
R
T
S
D
+
t
S
S
T
t
n
r
e
n
a
R
e
l
e
s
t
Note: tRSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=16.7ms
RES Reset Timing Chart
Rev. 1.00
71
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Low Voltage Reset – LVR
Theꢀmicrocontrollerꢀcontainsꢀaꢀlowꢀvoltageꢀresetꢀcircuitꢀinꢀorderꢀtoꢀmonitorꢀtheꢀsupplyꢀvoltageꢀofꢀtheꢀ
device.ꢀTheꢀLVRꢀfunctionꢀisꢀalwaysꢀenabledꢀwithꢀaꢀspecificꢀLVRꢀvoltage,ꢀVLVR.ꢀIfꢀtheꢀsupplyꢀvoltageꢀ
ofꢀtheꢀdeviceꢀdropsꢀtoꢀwithinꢀaꢀrangeꢀofꢀ0.9V~VLVRꢀsuchꢀasꢀmightꢀoccurꢀwhenꢀchangingꢀtheꢀbattery,ꢀ
theꢀLVRꢀwillꢀautomaticallyꢀresetꢀtheꢀdeviceꢀinternallyꢀandꢀtheꢀLVRFꢀbitꢀinꢀtheꢀSMOD1ꢀregisterꢀwillꢀ
alsoꢀbeꢀsetꢀtoꢀ1.ꢀForꢀaꢀvalidꢀLVRꢀsignal,ꢀaꢀlowꢀsupplyꢀvoltage,ꢀi.e.,ꢀaꢀvoltageꢀinꢀtheꢀrangeꢀbetweenꢀ
0.9V~VLVRꢀmustꢀexistꢀforꢀaꢀtimeꢀgreaterꢀthanꢀthatꢀspecifiedꢀbyꢀtLVRꢀinꢀtheꢀA.C.ꢀcharacteristics.ꢀIfꢀtheꢀ
lowꢀsupplyꢀvoltageꢀstateꢀdoesꢀnotꢀexceedꢀthisꢀvalue,ꢀtheꢀLVRꢀwillꢀignoreꢀtheꢀlowꢀsupplyꢀvoltageꢀandꢀ
willꢀnotꢀperformꢀaꢀresetꢀfunction.ꢀTheꢀactualꢀVLVRꢀvalueꢀcanꢀbeꢀselectedꢀbyꢀtheꢀLVSꢀbitsꢀinꢀtheꢀLVRCꢀ
register.ꢀIfꢀtheꢀLVS7~LVS0ꢀbitsꢀhaveꢀanyꢀotherꢀvalue,ꢀwhichꢀmayꢀperhapsꢀoccurꢀdueꢀtoꢀadverseꢀ
environmentalꢀconditionsꢀsuchꢀasꢀnoise,ꢀtheꢀLVRꢀwillꢀresetꢀtheꢀdeviceꢀafterꢀ2~3ꢀfSUBꢀclockꢀcycles.ꢀ
Whenꢀthisꢀhappens,ꢀtheꢀLRFꢀbitꢀinꢀtheꢀSMOD1ꢀregisterꢀwillꢀbeꢀsetꢀtoꢀ1.ꢀAfterꢀpowerꢀonꢀtheꢀregisterꢀ
willꢀhaveꢀtheꢀvalueꢀofꢀ01010101B.ꢀNoteꢀthatꢀtheꢀLVRꢀfunctionꢀwillꢀbeꢀautomaticallyꢀdisabledꢀwhenꢀ
theꢀdeviceꢀentersꢀtheꢀpowerꢀdownꢀmode.
L
R
V
t
R
T
S
D
+
t
S
S
T
I
t
n
r
e
n
a
R
e
l
e
s
t
Note:ꢀtRSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=50ms
Low Voltage Reset Timing Chart
• LVRC Register
Bit
Name
R/W
7
LVS7
R/W
0
6
LVS6
R/W
1
5
LVS5
R/W
0
4
LVS4
R/W
1
3
LVSꢅ
R/w
0
2
LVSꢃ
R/w
1
1
LVS1
R/W
0
0
LVS0
R/W
1
POR
Bitꢀ7~0
LVS7~LVS0:ꢀLVRꢀvoltageꢀselect
01010101:ꢀ2.1V
00110011:ꢀ2.55V
10011001:ꢀ3.15V
10101010:ꢀ3.8V
Anyꢀotherꢀvalues:ꢀGeneratesꢀMCUꢀresetꢀ–ꢀregisterꢀisꢀresetꢀtoꢀPORꢀvalue
Whenꢀanꢀactualꢀlowꢀvoltageꢀconditionꢀoccurs,ꢀasꢀspecifiedꢀbyꢀoneꢀofꢀtheꢀfourꢀdefinedꢀ
LVRꢀvoltageꢀvaluesꢀabove,ꢀanꢀMCUꢀresetꢀwillꢀbeꢀgenerated.ꢀTheꢀresetꢀoperationꢀwillꢀ
beꢀactivatedꢀafterꢀ2~3ꢀfSUBꢀclockꢀcycles.ꢀInꢀthisꢀsituationꢀtheꢀregisterꢀcontentsꢀwillꢀ
remainꢀtheꢀsameꢀafterꢀsuchꢀaꢀresetꢀoccurs.
Anyꢀregisterꢀvalue,ꢀotherꢀthanꢀtheꢀfourꢀdefinedꢀregisterꢀvaluesꢀabove,ꢀwillꢀalsoꢀresultꢀ
inꢀtheꢀgenerationꢀofꢀanꢀMCUꢀreset.ꢀTheꢀresetꢀoperationꢀwillꢀbeꢀactivatedꢀafterꢀ2~3ꢀfSUB
ꢀ
clockꢀcycles.ꢀHoweverꢀinꢀthisꢀsituationꢀtheꢀregisterꢀcontentsꢀwillꢀbeꢀresetꢀtoꢀtheꢀPORꢀ
value.
Rev. 1.00
7ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• SMOD1 Register
Bit
Name
R/W
7
FSYSON
R/W
6
5
4
3
2
LVRF
R/W
x
1
0
WRF
—
—
—
—
—
—
—
—
—
—
—
—
LRF
R/W
0
R/W
POR
0
0
“x”: unknown
Bitꢀ7ꢀ
FSYSON:ꢀfSYSꢀControlꢀinꢀIDLEꢀMode
Describedꢀelsewhere
Bitꢀ6~3ꢀ
Bitꢀ2
Unimplemented,ꢀreadꢀasꢀ"0"
LVRF:ꢀLVRꢀfunctionꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀwhenꢀaꢀspecificꢀLowꢀVoltageꢀResetꢀsituationꢀconditionꢀoccurs.ꢀThisꢀ
bitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀtheꢀapplicationꢀprogram.
Bitꢀ1
LRF:ꢀLVRꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
0:ꢀNotꢀoccurred
1:ꢀOccurred
Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀifꢀtheꢀLVRCꢀregisterꢀcontainsꢀanyꢀnonꢀdefinedꢀLVRꢀvoltageꢀregisterꢀ
values.ꢀThisꢀinꢀeffectꢀactsꢀlikeꢀaꢀsoftware-resetꢀfunction.ꢀThisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ
0ꢀbyꢀtheꢀapplicationꢀprogram.
bitꢀ0
WRF:ꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀflag
Describedꢀelsewhere
Watchdog Time-out Reset during Normal Operation
TheꢀWatchdogꢀtime-outꢀResetꢀduringꢀnormalꢀoperationꢀisꢀtheꢀsameꢀasꢀaꢀhardwareꢀRESꢀpinꢀresetꢀ
exceptꢀthatꢀtheꢀWatchdogꢀtime-outꢀflagꢀTOꢀwillꢀbeꢀsetꢀtoꢀ“1”.
W
T
D
T
m
i
-
e
o
u
t
t
R
T
S
D
+
t
S
S
T
I
t
n
r
e
n
a
R
e
l
e
s
t
Note:ꢀtRSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=16.7ms
WDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode
TheꢀWatchdogꢀtime-outꢀResetꢀduringꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀaꢀlittleꢀdifferentꢀfromꢀotherꢀkindsꢀ
ofꢀreset.ꢀMostꢀofꢀtheꢀconditionsꢀremainꢀunchangedꢀexceptꢀthatꢀtheꢀProgramꢀCounterꢀandꢀtheꢀStackꢀ
Pointerꢀwillꢀbeꢀclearedꢀtoꢀ“0”ꢀandꢀtheꢀTOꢀflagꢀwillꢀbeꢀsetꢀtoꢀ“1”.ꢀReferꢀtoꢀtheꢀA.C.ꢀCharacteristicsꢀforꢀ
tSSTꢀdetails.
W
T
D
T
m
i
-
e
o
u
t
t
S
S
T
I
t
n
r
e
n
a
R
e
l
e
s
t
Note:ꢀTheꢀtSSTꢀisꢀ15~16ꢀclockꢀcyclesꢀifꢀtheꢀsystemꢀclockꢀsourceꢀisꢀprovidedꢀbyꢀERCꢀorꢀHIRC.ꢀ
TheꢀtSSTꢀisꢀ1024ꢀclockꢀforꢀHXTꢀorꢀLXT.ꢀTheꢀtSSTꢀisꢀ1~2ꢀclockꢀforꢀLIRC.
WDT Time-out Reset during SLEEP or IDLE Timing Chart
Rev. 1.00
7ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Reset Initial Conditions
Theꢀdifferentꢀtypesꢀofꢀresetꢀdescribedꢀaffectꢀtheꢀresetꢀflagsꢀinꢀdifferentꢀways.ꢀTheseꢀflags,ꢀknownꢀ
asꢀPDFꢀandꢀTOꢀareꢀlocatedꢀinꢀtheꢀstatusꢀregisterꢀandꢀareꢀcontrolledꢀbyꢀvariousꢀmicrocontrollerꢀ
operations,ꢀsuchꢀasꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀfunctionꢀorꢀWatchdogꢀTimer.ꢀTheꢀresetꢀflagsꢀareꢀ
shownꢀinꢀtheꢀtable:
TO
0
PDF
RESET Conditions
0
u
u
1
Poweꢀ-on ꢀeset
u
RES oꢀ LVR ꢀeset duꢀing NOR�AL oꢀ SLOW �ode opeꢀation
WDT time-out ꢀeset duꢀing NOR�AL oꢀ SLOW �ode opeꢀation
WDT time-out ꢀeset duꢀing IDLE oꢀ SLEEP �ode opeꢀation
1
1
“u” stands foꢀ unꢁꢂanged
Theꢀfollowingꢀtableꢀindicatesꢀtheꢀwayꢀinꢀwhichꢀtheꢀvariousꢀcomponentsꢀofꢀtheꢀmicrocontrollerꢀareꢀ
affectedꢀafterꢀaꢀpower-onꢀresetꢀoccurs.
Item
Pꢀogꢀam Counteꢀ
Inteꢀꢀupts
Condition After RESET
Reset to zeꢀo
All inteꢀꢀupts will be disabled
WDTꢄ Time Base
Timeꢀ �odules
Input/Output Poꢀts
Staꢁk Pointeꢀ
Cleaꢀ afteꢀ ꢀesetꢄ WDT begins ꢁounting
Timeꢀ �odules will be tuꢀned off
I/O poꢀts will be setup as inputs
Staꢁk Pointeꢀ will point to tꢂe top of tꢂe staꢁk
Theꢀdifferentꢀkindsꢀofꢀresetsꢀallꢀaffectꢀtheꢀinternalꢀregistersꢀofꢀtheꢀmicrocontrollerꢀinꢀdifferentꢀways.ꢀ
Toꢀensureꢀreliableꢀcontinuationꢀofꢀnormalꢀprogramꢀexecutionꢀafterꢀaꢀresetꢀoccurs,ꢀitꢀisꢀimportantꢀtoꢀ
knowꢀwhatꢀconditionꢀtheꢀmicrocontrollerꢀisꢀinꢀafterꢀaꢀparticularꢀresetꢀoccurs.ꢀTheꢀfollowingꢀtableꢀ
describesꢀhowꢀeachꢀtypeꢀofꢀresetꢀaffectsꢀtheꢀmicrocontrollerꢀinternalꢀregisters.
Register Reset Status Table
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
Register
Power-on Reset
RES or LVR Reset
IAR0
�P0
●
●
●
●
●
●
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●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
0000 0000
0000 0000
x x x x x x x x
0000 0000
0000 0000
x x x x x x x x
0000 0000
x x x x x x x x
x x x x x x x x
- - x x x x x x
- x x x x x x x
x x 0 0 x x x x
- - - - - - - 0
- - - - - - 0 0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
- - u u u u u u
- u u u u u u u
uuuu uuuu
- - - - - - - 0
- - - - - - 0 0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
- - u u u u u u
- u u u u u u u
uu1u uuuu
- - - - - - - 0
- - - - - - 0 0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
- - u u u u u u
- u u u u u u u
u u 11 u u u u
- - - - - - - u
- - - - - - u u
IAR1
�P1L
�P1H
IARꢃ
�PꢃL
�PꢃH
ACC
PCL
TBLP
TBLH
TBHP
TBHP
STATUS
BP
●
●
●
●
BP
●
Rev. 1.00
74
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
Register
Power-on Reset
RES or LVR Reset
PAWU
PAPU
PA
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
0000 0000
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
- 0 0 0 0 0 0 0
- 111 1111
- 111 1111
0000 0000
1111 1111
1111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0000 0000
- 0 0 0 0 0 0 0
0000 0000
0000 0000
- 0 0 0 - 0 0 0
0000 0000
- 0 0 0 - 0 0 0
0000 0000
- 0 0 0 - 0 0 0
0000 0000
0 0 0 0 0 0 11
0 - - - - x 0 0
- - - - - - - 0
0101 0101
- - 0 0 - 0 0 0
0 1 0 1 0 0 11
- 0 0 0 0 0 0 0
0000 0000
- 0 0 0 - - - 1
- 0 0 0 - - - 1
0000 0000
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
- 0 0 0 0 0 0 0
- 111 1111
- 111 1111
0000 0000
1111 1111
1111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0000 0000
- 0 0 0 0 0 0 0
0000 0000
0000 0000
- 0 0 0 - 0 0 0
0000 0000
- 0 0 0 - 0 0 0
0000 0000
- 0 0 0 - 0 0 0
0000 0000
0 0 0 0 0 0 11
0 - - - - 1 u u
- - - - - - - 0
uuuu uuuu
- - 0 0 - 0 0 0
0 1 0 1 0 0 11
- 0 0 0 0 0 0 0
0000 0000
- 0 0 0 - - - 1
- 0 0 0 - - - 1
0000 0000
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
- 0 0 0 0 0 0 0
- 111 1111
- 111 1111
0000 0000
1111 1111
1111 1111
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0000 0000
- 0 0 0 0 0 0 0
0000 0000
0000 0000
- 0 0 0 - 0 0 0
0000 0000
- 0 0 0 - 0 0 0
0000 0000
- 0 0 0 - 0 0 0
0000 0000
0 0 0 0 0 0 11
0 - - - - u u u
- - - - - - - 0
0101 0101
- - 0 0 - 0 0 0
0 1 0 1 0 0 11
- 0 0 0 0 0 0 0
0000 0000
- 0 0 0 - - - 1
- 0 0 0 - - - 1
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
- u u u u u u u
- u u u u u u u
- u u u u u u u
uuuu uuuu
uuuu uuuu
uuuu uuuu
- - u u u u u u
- - u u u u u u
- - u u u u u u
uuuu uuuu
- u u u u u u u
uuuu uuuu
uuuu uuuu
- u u u - u u u
uuuu uuuu
- u u u - u u u
uuuu uuuu
- u u u - u u u
uuuu uuuu
uuuu uuuu
u - - - - u u u
- - - - - - - u
uuuu uuuu
- - u u - u u u
uuuu uuuu
- u u u u u u u
uuuu uuuu
- u u u - - - u
- u u u - - - u
PAC
PBPU
PB
PBC
PCPU
PC
PCC
PDPU
PD
PDC
PEPU
PE
PEC
PFPU
PF
PFC
PGPU
PG
PGC
PHPU
PH
PHC
INTEG
INTC0
INTC1
INTCꢃ
INTCꢅ
�FI0
�FI1
�FIꢃ
�FIꢅ
�FI4
S�OD
S�OD1
S�ODꢃ
LVRC
LVDC
WDTC
EEA
EED
CP0C
CP1C
Rev. 1.00
75
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
Register
Power-on Reset
RES or LVR Reset
T�1C0
T�1C1
T�1Cꢃ
T�1DL
T�1DH
T�1AL
T�1AH
T�1BL
T�1BH
T�ꢃC0
T�ꢃC1
T�ꢃDL
T�ꢃDH
T�ꢃAL
T�ꢃAH
T�ꢃRP
T�ꢅC0
T�ꢅC1
T�ꢅDL
T�ꢅDH
T�ꢅAL
T�ꢅAH
T�0C0
T�nC1
T�0DL
T�0DH
T�0AL
T�0AH
PSC0
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
- - - - - - 0 0
0 - - - - 0 0 0
0 - - - - 0 0 0
- - - - - - 0 0
0 11 0 0 0 0 0
- 0 0 0 - 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
- - - - - - 0 0
0 - - - - 0 0 0
0 - - - - 0 0 0
- - - - - - 0 0
0 11 0 0 0 0 0
- 0 0 0 - 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0 0 0 0 0 - - -
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
- - - - - - 0 0
0 - - - - 0 0 0
0 - - - - 0 0 0
- - - - - - 0 0
0 11 0 0 0 0 0
- 0 0 0 - 0 0 0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
- - - - - - u u
uuuu uuuu
- - - - - - u u
uuuu uuuu
- - - - - - u u
u u u u u - - -
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
- - - - - - u u
uuuu uuuu
- - - - - - u u
uuuu uuuu
uuuu uuuu
uuuu uuuu
- - - - - - u u
uuuu uuuu
- - - - - - u u
- - - - - - u u
u - - - - u u u
u - - - - u u u
- - - - - - u u
uuuu uuuu
- u u u - u u u
TBC0
TBC1
PSC1
ADCR0
ADCR1
ADRL
(ADRFS=0)
●
●
●
●
●
●
●
●
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
u u u u - - - -
uuuu uuuu
uuuu uuuu
- - - - u u u u
ADRL
(ADRFS=1)
ADRH
(ADRFS=0)
ADRH
(ADRFS=1)
SI�C0
SI�C1
SI�D
●
●
●
●
●
●
111 - 0 0 0 -
1000 0001
x x x x x x x x
111 - 0 0 0 -
1000 0001
x x x x x x x x
111 - 0 0 0 -
1000 0001
x x x x x x x x
u u u - u u u -
uuuu uuuu
uuuu uuuu
Rev. 1.00
76
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
Register
Power-on Reset
RES or LVR Reset
SI�Cꢃ/
SI�A
●
●
0000 0000
0000 0000
0000 0000
uuuu uuuu
IꢃCTOC
SPIAC0
SPIAC1
SPIAD
FARL
●
●
●
●
●
●
●
●
●
●
●
0000 0000
1 1 1 - - - 0 -
0000 0000
0000 0000
0000 0000
- - 0 0 0 0 0 0
- 0 0 0 0 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 - - - - 0 0 0
0 0 0 0 - - - -
- - - - 0 0 0 0
0000 0000
0000 0000
- - - - - - - 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
0000 0000
0000 0000
0000 0000
1 1 1 - - - 0 -
0000 0000
0000 0000
0000 0000
- - 0 0 0 0 0 0
- 0 0 0 0 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 - - - - 0 0 0
0 0 0 0 - - - -
- - - - 0 0 0 0
0000 0000
0000 0000
- - - - - - - 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
0000 0000
0000 0000
0000 0000
1 1 1 - - - 0 -
0000 0000
0000 0000
0000 0000
- - 0 0 0 0 0 0
- 0 0 0 0 0 0 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 - - - - 0 0 0
0 0 0 0 - - - -
- - - - 0 0 0 0
0000 0000
0000 0000
- - - - - - - 0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
0 0 0 0 0 - - -
0000 0000
0000 0000
- - - - - - 0 0
0000 0000
- - - - - - 0 0
0000 0000
0000 0000
0000 0000
uuuu uuuu
u u u - - - u -
uuuu uuuu
uuuu uuuu
uuuu uuuu
- - u u u u u u
- u u u u u u u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u - - - - u u u
u u u u - - - -
- - - - u u u u
uuuu uuuu
uuuu uuuu
- - - - - - - u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u u u u u - - -
uuuu uuuu
uuuu uuuu
- - - - - - u u
uuuu uuuu
- - - - - - u u
uuuu uuuu
u u u u u - - -
uuuu uuuu
uuuu uuuu
- - - - - - u u
uuuu uuuu
- - - - - - u u
uuuu uuuu
uuuu uuuu
uuuu uuuu
FARH
FARH
FD0L
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
FD0H
FD1L
FD1H
FDꢃL
FDꢃH
FDꢅL
FDꢅH
TBCꢃ
SCO�C
EEC
FC0
FC1
FCꢃ
IFS0
IFS1
IFSꢃ
IFSꢅ
IFS4
IFS5
T�4C0
T�4C1
T�4DL
T�4DH
T�4AL
T�4AH
T�4RP
T�5C0
T�5C1
T�5DL
T�5DH
T�5AL
T�5AH
T�5RP
PAS0
PAS1
Rev. 1.00
77
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
Register
Power-on Reset
RES or LVR Reset
PASꢃ
PASꢅ
PBSꢃ
PBSꢅ
PCS0
PCS1
PCSꢃ
PCSꢅ
PDS0
PDS1
PDSꢃ
PDSꢅ
PES0
PES1
PESꢃ
PESꢅ
PFS0
PGS0
PGS1
PGSꢃ
PGSꢅ
PHS0
PHS1
PHSꢃ
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note:ꢀ“-”ꢀnotꢀimplementꢀ
“u”ꢀmeansꢀ“unchanged”
“x”ꢀmeansꢀ“unknown”
Input/Output Ports
HoltekꢀmicrocontrollersꢀofferꢀconsiderableꢀflexibilityꢀonꢀtheirꢀI/Oꢀports.ꢀWithꢀtheꢀinputꢀorꢀoutputꢀ
designationꢀofꢀeveryꢀpinꢀfullyꢀunderꢀuserꢀprogramꢀcontrol,ꢀpull-highꢀselectionsꢀforꢀallꢀportsꢀandꢀ
wake-upꢀselectionsꢀonꢀcertainꢀpins,ꢀtheꢀuserꢀisꢀprovidedꢀwithꢀanꢀI/Oꢀstructureꢀtoꢀmeetꢀtheꢀneedsꢀofꢀaꢀ
wideꢀrangeꢀofꢀapplicationꢀpossibilities.
Theseꢀdevicesꢀprovideꢀbidirectionalꢀinput/outputꢀlinesꢀlabeledꢀwithꢀportꢀnamesꢀPA~PHꢀTheseꢀI/Oꢀ
portsꢀareꢀmappedꢀtoꢀtheꢀRAMꢀDataꢀMemoryꢀwithꢀspecificꢀaddressesꢀasꢀshownꢀinꢀtheꢀSpecialꢀPurposeꢀ
DataꢀMemoryꢀtable.ꢀAllꢀofꢀtheseꢀI/Oꢀportsꢀcanꢀbeꢀusedꢀforꢀinputꢀandꢀoutputꢀoperations.ꢀForꢀinputꢀ
operation,ꢀtheseꢀportsꢀareꢀnon-latching,ꢀwhichꢀmeansꢀtheꢀinputsꢀmustꢀbeꢀreadyꢀatꢀtheꢀT2ꢀrisingꢀedgeꢀ
ofꢀinstructionꢀ“MOVꢀA,ꢀ[m]”,ꢀwhereꢀmꢀdenotesꢀtheꢀportꢀaddress.ꢀForꢀoutputꢀoperation,ꢀallꢀtheꢀdataꢀisꢀ
latchedꢀandꢀremainsꢀunchangedꢀuntilꢀtheꢀoutputꢀlatchꢀisꢀrewritten.
Rev. 1.00
78
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
I/O Port Register List
Bit
Register
Name
7
6
5
4
3
2
1
0
PAWU
PAPU
PA
PAWU7
PAPU7
PA7
PAWU6
PAPU6
PA6
PAWU5
PAPU5
PA5
PAWU4
PAPU4
PA4
PAWUꢅ
PAPUꢅ
PAꢅ
PAWUꢃ
PAPUꢃ
PAꢃ
PAWU1
PAPU1
PA1
PAWU0
PAPU0
PA0
PAC
PBPU
PB
PAC7
PBPU7
PB7
PAC6
PBPU6
PB6
PAC5
PBPU5
PB5
PAC4
PBPU4
PB4
PACꢅ
PBPUꢅ
PBꢅ
PACꢃ
PBPUꢃ
PBꢃ
PAC1
PBPU1
PB1
PAC0
PBPU0
PB0
PBC
PCPU
PC
PBC7
PCPU7
PC7
PBC6
PCPU6
PC6
PBC5
PCPU5
PC5
PBC4
PCPU4
PC4
PBCꢅ
PCPUꢅ
PCꢅ
PBCꢃ
PCPUꢃ
PCꢃ
PBC1
PCPU1
PC1
PBC0
PCPU0
PC0
PCC
PDPU
PD
PCC7
PDPU7
PD7
PCC6
PDPU6
PD6
PCC5
PDPU5
PD5
PCC4
PDPU4
PD4
PCCꢅ
PDPUꢅ
PDꢅ
PCCꢃ
PDPUꢃ
PDꢃ
PCC1
PDPU1
PD1
PCC0
PDPU0
PD0
PDC
PEPU
PE
PDC7
PEPU7
PE7
PDC6
PEPU6
PE6
PDC5
PEPU5
PE5
PDC4
PEPU4
PE4
PDCꢅ
PEPUꢅ
PEꢅ
PDCꢃ
PEPUꢃ
PEꢃ
PDC1
PEPU1
PE1
PDC0
PEPU0
PE0
PEC
PFPU
PF
PEC7
—
PEC6
PFPU6
PF6
PEC5
PFPU5
PF5
PEC4
PFPU4
PF4
PECꢅ
PFPUꢅ
PFꢅ
PECꢃ
PFPUꢃ
PFꢃ
PEC1
PFPU1
PF1
PEC0
PFPU0
PF0
—
PFC
PGPU
PG
—
PFC6
PGPU6
PG6
PFC5
PGPU5
PG5
PFC4
PGPU4
PG4
PFCꢅ
PGPUꢅ
PGꢅ
PFCꢃ
PGPUꢃ
PGꢃ
PFC1
PGPU1
PG1
PFC0
PGPU0
PG0
PGPU7
PG7
PGC
PHPU
PH
PGC7
—
PGC6
—
PGC5
PHPU5
PH5
PGC4
PHPU4
PH4
PGCꢅ
PHPUꢅ
PHꢅ
PGCꢃ
PHPUꢃ
PHꢃ
PGC1
PHPU1
PH1
PGC0
PHPU0
PH0
—
—
PHC
—
—
PHC5
PHC4
PHCꢅ
PHCꢃ
PHC1
PHC0
“—”:ꢀUnimplemented,ꢀreadꢀasꢀ“0”
PAWUn:ꢀPAꢀwake-upꢀfunctionꢀcontrol
0:ꢀDisable
1:ꢀEnable
PAn/PBn/PCn/PDn/PEn/PFn/PGn/PHn:ꢀI/OꢀDataꢀbit
0:ꢀdataꢀ0
1:ꢀdataꢀ1
PACn/PBCn/PCCn/PDCn/PECn/PFCn/PGCn/PHCn:ꢀI/Oꢀtypeꢀselection
0:ꢀOutput
1:ꢀinput
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn/PGPUn/PHPUn:ꢀPull-highꢀfunctionꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.00
79
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Pull-high Resistors
Manyꢀproductꢀapplicationsꢀrequireꢀpull-highꢀresistorsꢀforꢀtheirꢀswitchꢀinputsꢀusuallyꢀrequiringꢀtheꢀ
useꢀofꢀanꢀexternalꢀresistor.ꢀToꢀeliminateꢀtheꢀneedꢀforꢀtheseꢀexternalꢀresistors,ꢀallꢀI/Oꢀpins,ꢀwhenꢀ
configuredꢀasꢀanꢀinputꢀhaveꢀtheꢀcapabilityꢀofꢀbeingꢀconnectedꢀtoꢀanꢀinternalꢀpull-highꢀresistor.ꢀTheseꢀ
pull-highꢀresistorsꢀareꢀselectedꢀusingꢀregistersꢀPAPU~PHPU,ꢀandꢀareꢀimplementedꢀusingꢀweakꢀ
PMOSꢀtransistors.
Port A Wake-up
TheꢀHALTꢀinstructionꢀforcesꢀtheꢀmicrocontrollerꢀintoꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀwhichꢀpreservesꢀ
power,ꢀaꢀfeatureꢀthatꢀisꢀimportantꢀforꢀbatteryꢀandꢀotherꢀlow-powerꢀapplications.ꢀVariousꢀmethodsꢀ
existꢀtoꢀwake-upꢀtheꢀmicrocontroller,ꢀoneꢀofꢀwhichꢀisꢀtoꢀchangeꢀtheꢀlogicꢀconditionꢀonꢀoneꢀofꢀtheꢀPortꢀ
Aꢀpinsꢀfromꢀhighꢀtoꢀlow.ꢀThisꢀfunctionꢀisꢀespeciallyꢀsuitableꢀforꢀapplicationsꢀthatꢀcanꢀbeꢀwokenꢀupꢀ
viaꢀexternalꢀswitches.ꢀEachꢀpinꢀonꢀPortꢀAꢀcanꢀbeꢀselectedꢀindividuallyꢀtoꢀhaveꢀthisꢀwake-upꢀfeatureꢀ
usingꢀtheꢀPAWUꢀregister.
PAWU Register
Bit
7
PAWU7
R/W
0
6
PAWU6
R/W
0
5
PAWU5
R/W
0
4
PAWU4
R/W
0
3
PAWUꢅ
R/W
0
2
PAWUꢃ
R/W
0
1
PAWU1
R/W
0
0
PAWU0
R/W
0
Name
R/W
POR
Bitꢀ7~0
PAWU:ꢀPortꢀAꢀbitꢀ7~bitꢀ0ꢀWake-upꢀControl
0:ꢀDisable
1:ꢀEnable
I/O Port Control Registers
EachꢀPortꢀhasꢀitsꢀownꢀcontrolꢀregister,ꢀknownꢀasꢀPAC~PHC,ꢀwhichꢀcontrolsꢀtheꢀinput/outputꢀ
configuration.ꢀWithꢀthisꢀcontrolꢀregister,ꢀeachꢀI/Oꢀpinꢀwithꢀorꢀwithoutꢀpull-highꢀresistorsꢀcanꢀbeꢀ
reconfiguredꢀdynamicallyꢀunderꢀsoftwareꢀcontrol.ꢀForꢀtheꢀI/Oꢀpinꢀtoꢀfunctionꢀasꢀanꢀinput,ꢀtheꢀ
correspondingꢀbitꢀofꢀtheꢀcontrolꢀregisterꢀmustꢀbeꢀwrittenꢀasꢀaꢀ“1”.ꢀThisꢀwillꢀthenꢀallowꢀtheꢀlogicꢀstateꢀ
ofꢀtheꢀinputꢀpinꢀtoꢀbeꢀdirectlyꢀreadꢀbyꢀinstructions.ꢀWhenꢀtheꢀcorrespondingꢀbitꢀofꢀtheꢀcontrolꢀregisterꢀ
isꢀwrittenꢀasꢀaꢀ“0”,ꢀtheꢀI/OꢀpinꢀwillꢀbeꢀsetupꢀasꢀaꢀCMOSꢀoutput.ꢀIfꢀtheꢀpinꢀisꢀcurrentlyꢀsetupꢀasꢀanꢀ
output,ꢀinstructionsꢀcanꢀstillꢀbeꢀusedꢀtoꢀreadꢀtheꢀoutputꢀregister.
However,ꢀitꢀshouldꢀbeꢀnotedꢀthatꢀtheꢀprogramꢀwillꢀinꢀfactꢀonlyꢀreadꢀtheꢀstatusꢀofꢀtheꢀoutputꢀdataꢀlatchꢀ
andꢀnotꢀtheꢀactualꢀlogicꢀstatusꢀofꢀtheꢀoutputꢀpin.
Pin-shared Functions
Theꢀflexibilityꢀofꢀtheꢀmicrocontrollerꢀrangeꢀisꢀgreatlyꢀenhancedꢀbyꢀtheꢀuseꢀofꢀpinsꢀthatꢀhaveꢀmoreꢀ
thanꢀoneꢀfunction.ꢀLimitedꢀnumbersꢀofꢀpinsꢀcanꢀforceꢀseriousꢀdesignꢀconstraintsꢀonꢀdesignersꢀbutꢀbyꢀ
supplyingꢀpinsꢀwithꢀmulti-functions,ꢀmanyꢀofꢀtheseꢀdifficultiesꢀcanꢀbeꢀovercome.ꢀForꢀtheseꢀpins,ꢀtheꢀ
chosenꢀfunctionꢀofꢀtheꢀmulti-functionꢀI/Oꢀpinsꢀisꢀselectedꢀbyꢀaꢀseriesꢀofꢀregitersꢀviaꢀtheꢀapplicationꢀ
programꢀcontrol.
Pin-shared Function Selection Register
Theꢀlimitedꢀnumberꢀofꢀsuppliedꢀpinsꢀinꢀaꢀpackageꢀcanꢀimposeꢀrestrictionsꢀonꢀtheꢀamountꢀofꢀfunctionsꢀ
aꢀcertainꢀdeviceꢀcanꢀcontain.ꢀHoweverꢀbyꢀallowingꢀtheꢀsameꢀpinsꢀtoꢀshareꢀseveralꢀdifferentꢀfunctionsꢀ
andꢀprovidingꢀaꢀmeansꢀofꢀfunctionꢀselection,ꢀaꢀwideꢀrangeꢀofꢀdifferentꢀfunctionsꢀcanꢀbeꢀincorporatedꢀ
intoꢀevenꢀrelativelyꢀsmallꢀpackageꢀsizes.ꢀTheꢀdeviceꢀincludesꢀPortꢀ“x”ꢀoutputꢀfunctionꢀslsectionꢀ
registerꢀ“n”,ꢀlabeledꢀasꢀPxSn,ꢀandꢀinputꢀfunctionꢀselectionꢀregisterꢀ“i”,ꢀlabeledꢀasꢀIFSi,ꢀwhichꢀcanꢀ
Rev. 1.00
80
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
selectꢀtheꢀfunctionsꢀofꢀtheꢀpin-sharedꢀfunctionꢀpins.
Whenꢀtheꢀpin-sharedꢀinputꢀfunctionꢀisꢀselectedꢀtoꢀbeꢀused,ꢀtheꢀcorrespondingꢀinputꢀandꢀoutputꢀ
functionsꢀselectionꢀshouldꢀbeꢀproperlyꢀmanaged.ꢀForꢀexample,ꢀifꢀtheꢀI2CꢀSDAꢀlineꢀisꢀused,ꢀtheꢀ
correspondingꢀoutputꢀpin-sharedꢀfunctionꢀshouldꢀbeꢀconfiguredꢀasꢀtheꢀSDI/SDAꢀfunctionꢀbyꢀ
configuringꢀtheꢀPxSnꢀregisterꢀandꢀtheꢀSDAꢀsignalꢀintputꢀshouldꢀbeꢀproperlyꢀselectedꢀusingꢀtheꢀ
IFSiꢀregister.ꢀHowever,ꢀifꢀtheꢀexternalꢀinterruptꢀfunctionꢀisꢀselectedꢀtoꢀbeꢀused,ꢀtheꢀrelevantꢀoutputꢀ
pin-sharedꢀfunctionꢀshouldꢀbeꢀselectedꢀasꢀanꢀI/Oꢀfunctionꢀandꢀtheꢀinterruptꢀinputꢀsignalꢀshouldꢀbeꢀ
selected.
Bit
Register
Name
7
6
5
4
3
2
1
0
PAS0
PAS1
PASꢃ
PASꢅ
PBSꢃ
PBSꢅ
PCS0
PCS1
PCSꢃ
PCSꢅ
PDS0
PDS1
PDSꢃ
PDSꢅ
PES0
PES1
PESꢃ
PESꢅ
PFS0
PGS0
PGS1
PGSꢃ
PGSꢅ
PHS0
PHS1
PHSꢃ
IFS0
PA1Sꢅ
PAꢅSꢅ
PA5Sꢅ
PA7Sꢅ
PB5Sꢅ
PB7Sꢅ
PC1Sꢅ
PCꢅSꢅ
PC5Sꢅ
PC7Sꢅ
PD1Sꢅ
PDꢅSꢅ
PD5Sꢅ
PD7Sꢅ
PE1Sꢅ
PEꢅSꢅ
PE5Sꢅ
PE7Sꢅ
PF1Sꢅ
PG1Sꢅ
PGꢅSꢅ
D7
PA1Sꢃ
PAꢅSꢃ
PA5Sꢃ
PA7Sꢃ
PB5Sꢃ
PB7Sꢃ
PC1Sꢃ
PCꢅSꢃ
PC5Sꢃ
PC7Sꢃ
PD1Sꢃ
PDꢅSꢃ
PD5Sꢃ
PD7Sꢃ
PE1Sꢃ
PEꢅSꢃ
PE5Sꢃ
PD7Sꢃ
PF1Sꢃ
PG1Sꢃ
PGꢅSꢃ
D6
PA1S1
PAꢅS1
PA5S1
PA7S1
PB5S1
PB7S1
PC1S1
PCꢅS1
PC5S1
PC7S1
PD1S1
PDꢅS1
PD5S1
PD7S1
PE1S1
PEꢅS1
PE5S1
PE7S1
PF1S1
PG1S1
PGꢅS1
D5
PA1S0
PAꢅS0
PA5S0
PA7S0
PB5S0
PB7S0
PC1S0
PCꢅS0
PC5S0
PC7S0
PD1S0
PDꢅS0
PD5S0
PD7S0
PE1S0
PEꢅS0
PE5S0
PE7S0
PF1S0
PG1S0
PGꢅS0
D4
Dꢅ
Dꢃ
D1
D0
Dꢅ
Dꢃ
D1
D0
PA4Sꢅ
PA6Sꢅ
Dꢅ
PA4Sꢃ
PA6Sꢃ
Dꢃ
PA4S1
PA6S1
D1
PA4S0
PA6S0
D0
PB6Sꢅ
PC0Sꢅ
PCꢃSꢅ
PC4Sꢅ
PC6Sꢅ
PD0Sꢅ
PDꢃSꢅ
PD4Sꢅ
PD6Sꢅ
PE0Sꢅ
Dꢅ
PB6Sꢃ
PC0Sꢃ
PCꢃSꢃ
PC4Sꢃ
PC6Sꢃ
PD0Sꢃ
PDꢃSꢃ
PD4Sꢃ
PD6Sꢃ
PE0Sꢃ
Dꢃ
PB6S1
PC0S1
PCꢃS1
PC4S1
PC6S1
PD0S1
PDꢃS1
PD4S1
PD6S1
PE0S1
D1
PB6S0
PC0S0
PCꢃS0
PC4S0
PC6S0
PD0S0
PDꢃS0
PD4S0
PD6S0
PE0S0
D0
PE4Sꢅ
PE6Sꢅ
PF0Sꢅ
PG0Sꢅ
Dꢅ
PE4Sꢃ
PE6Sꢃ
PF0Sꢃ
PG0Sꢃ
Dꢃ
PE4S1
PE6S1
PF0S1
PG0S1
D1
PE4S0
PE6S0
PF0S0
PG0S0
D0
PG4Sꢅ
PG6Sꢅ
PH0Sꢅ
PHꢃSꢅ
Dꢅ
PG4Sꢃ
PG6Sꢃ
PH0Sꢃ
PHꢃSꢃ
Dꢃ
PG4S1
PG6S1
PH0S1
PHꢃS1
D1
PG4S0
PG6S0
PH0S0
PHꢃS0
D0
PG7Sꢅ
PH1Sꢅ
PHꢅSꢅ
PH5Sꢅ
PG7Sꢃ
PH1Sꢃ
PHꢅSꢃ
PH5Sꢃ
PG7S1
PH1S1
PHꢅS1
PH5S1
PG7S0
PH1S0
PHꢅS0
PH5S0
INTꢃS0
PINTBS1 PINTBS0 INTꢃS1
INT1S1
INT1S0
INT0S1
INT0S0
TCK0S0
D0
IFS1
TCKꢅS1 TCKꢅS0 TCKꢃS1 TCKꢃS0 TCK1S1 TCK1S0 TCK0S1
IFSꢃ
TPꢃIS1
D7
TPꢃIS0 TP1IBS1 TP1IBS0 TP1IAS1 TP1IAS0
D1
D1
IFSꢅ
D6
D6
D6
TP5IS1
SDIS1
TP5IS0
SDIS0
TP4IS1
SCKS1
TP4IS0
SCKS0
D0
IFS4
D7
SCSBS1 SCSBS0
IFS5
D7
SDIAS1 SDIAS0 SCKAS1 SCKAS0 SCSABS1 SCSABS0
Rev. 1.00
81
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• PAS0
Bit
Name
R/W
7
PA1Sꢅ
R/W
0
6
PA1Sꢃ
R/W
0
5
PA1S1
R/W
0
4
PA1S0
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~4
PA1S3~PA1S0:ꢀPortꢀA1ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP1A
0011:ꢀAN1
Others:ꢀReserved
Bitꢀ3~0ꢀ
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten
• PAS1
Bit
Name
R/W
7
PAꢅSꢅ
R/W
0
6
PAꢅSꢃ
R/W
0
5
PAꢅS1
R/W
0
4
PAꢅS0
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~4
PA3S3~PA3S0:ꢀPortꢀA3ꢀFunctionꢀSelection
0000:ꢀI/O
0011:ꢀAN3
0111:ꢀC0N
1111:ꢀAN3ꢀandꢀC0N
Others:ꢀReserved
Bitꢀ3~0ꢀ
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten
• PAS2
Bit
Name
R/W
7
PA5Sꢅ
R/W
0
6
PA5Sꢃ
R/W
0
5
PA5S1
R/W
0
4
PA5S0
R/W
0
3
PA4Sꢅ
R/W
0
2
PA4Sꢃ
R/W
0
1
PA4S1
R/W
0
0
PA4S0
R/W
0
POR
Bitꢀ7~4
PA5S3~PA5S0:ꢀPortꢀA5ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀSDO
0010:ꢀC1X
0011:ꢀAN5
Others:ꢀReserved
Bitꢀ3~0
PA4S3~PA4S0:ꢀPortꢀA4ꢀFunctionꢀSelection
0000:ꢀI/O
0011:ꢀAN4
Others:ꢀReserved
Rev. 1.00
8ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• PAS3
Bit
Name
R/W
7
PA7Sꢅ
R/W
0
6
PA7Sꢃ
R/W
0
5
PA7S1
R/W
0
4
PA7S0
R/W
0
3
PA6Sꢅ
R/W
0
2
PA6Sꢃ
R/W
0
1
PA6S1
R/W
0
0
PA6S0
R/W
0
POR
Bitꢀ7~4
PA7S3~PA7S0:ꢀPortꢀA7ꢀFunctionꢀSelection
0000:ꢀI/O
0010:ꢀSCK/SCL
0011:ꢀAN7
Others:ꢀReserved
Bitꢀ3~0
PA6S3~PA6S0:ꢀPortꢀA6ꢀFunctionꢀSelection
0000:ꢀI/O
0010:ꢀSDI/SDA
0011:ꢀAN6
Others:ꢀReserved
• PBS2
Bit
Name
R/W
7
PB5Sꢅ
R/W
0
6
PB5Sꢃ
R/W
0
5
PB5S1
R/W
0
4
PB5S0
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~4
PB5S3~PB5S0:ꢀPortꢀB5ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀSCS
Others:ꢀReserved
Bitꢀ3~0ꢀ
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten
• PBS3
Bit
Name
R/W
7
PB7Sꢅ
R/W
0
6
PB7Sꢃ
R/W
0
5
PB7S1
R/W
0
4
PB7S0
R/W
0
3
PB6Sꢅ
R/W
0
2
PB6Sꢃ
R/W
0
1
PB6S1
R/W
0
0
PB6S0
R/W
0
POR
Bitꢀ7~4
PB7S3~PB7S0:ꢀPortꢀB7ꢀFunctionꢀSelection
0000:ꢀI/O
0010:ꢀSDI/SDA
Others:ꢀReserved
Bitꢀ3~0
PB6S3~PB6S0:ꢀPortꢀB6ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀSDO
Others:ꢀReserved
Rev. 1.00
8ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• PCS0
Bit
Name
R/W
7
PC1Sꢅ
R/W
0
6
PC1Sꢃ
R/W
0
5
PC1S1
R/W
0
4
PC1S0
R/W
0
3
PC0Sꢅ
R/W
0
2
PC0Sꢃ
R/W
0
1
PC0S1
R/W
0
0
PC0S0
R/W
0
POR
Bitꢀ7~4
PC1S3~PC1S0:ꢀPortꢀC1ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP1B
0010:ꢀTP1BB
0011:ꢀSCOM1
Others:ꢀReserved
Bitꢀ3~0
PC0S3~PC0S0:ꢀPortꢀC0ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP1B
0010:ꢀTP1BB
0011:ꢀSCOM0
Others:ꢀReserved
• PCS1
Bit
Name
R/W
7
PCꢅSꢅ
R/W
0
6
PCꢅSꢃ
R/W
0
5
PCꢅS1
R/W
0
4
PCꢅS0
R/W
0
3
PCꢃSꢅ
R/W
0
2
PCꢃSꢃ
R/W
0
1
PCꢃS1
R/W
0
0
PCꢃS0
R/W
0
POR
Bitꢀ7~4
PC3S3~PC3S0:ꢀPortꢀC3ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP2
0010:ꢀC1X
0100:ꢀTP1B
Others:ꢀReserved
Bitꢀ3~0
PC2S3~PC2S0:ꢀPortꢀC2ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀPCK
0010:ꢀC0X
Others:ꢀReserved
• PCS2
Bit
Name
R/W
7
PC5Sꢅ
R/W
0
6
PC5Sꢃ
R/W
0
5
PC5S1
R/W
0
4
PC5S0
R/W
0
3
PC4Sꢅ
R/W
0
2
PC4Sꢃ
R/W
0
1
PC4S1
R/W
0
0
PC4S0
R/W
0
POR
Bitꢀ7~4
PC5S3~PC5S0:ꢀPortꢀC5ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀPCK
0010:ꢀTP0
0100:ꢀTP1B
0101:ꢀTP0B
0110:ꢀTP1BB
Others:ꢀReserved
Bitꢀ3~0
PC4S3~PC4S0:ꢀPortꢀC4ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP2
0010:ꢀTP2B
Others:ꢀReserved
Rev. 1.00
84
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• PCS3
Bit
Name
R/W
7
PC7Sꢅ
R/W
0
6
PC7Sꢃ
R/W
0
5
PC7S1
R/W
0
4
PC7S0
R/W
0
3
PC6Sꢅ
R/W
0
2
PC6Sꢃ
R/W
0
1
PC6S1
R/W
0
0
PC6S0
R/W
0
POR
Bitꢀ7~4
PC7S3~PC7S0:ꢀPortꢀC7ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP1A
0011:ꢀSCOM3
Others:ꢀReserved
Bitꢀ3~0
PC6S3~PC6S0:ꢀPortꢀC6ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP0
0010:ꢀTP0B
0011:ꢀSCOM2
Others:ꢀReserved
• PDS0
Bit
Name
R/W
7
PD1Sꢅ
R/W
0
6
PD1Sꢃ
R/W
0
5
PD1S1
R/W
0
4
PD1S0
R/W
0
3
PD0Sꢅ
R/W
0
2
PD0Sꢃ
R/W
0
1
PD0S1
R/W
0
0
PD0S0
R/W
0
POR
Bitꢀ7~4
PD1S3~PD1S0:ꢀPortꢀD1ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP2
0010:ꢀSCK/SCL
0100:ꢀSDO
0101:ꢀTP2B
Others:ꢀReserved
Bitꢀ3~0
PD0S3~PD0S0:ꢀPortꢀD0ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP3
0010:ꢀSCS
0100:ꢀTP3B
Others:ꢀReserved
• PDS1
Bit
Name
R/W
7
PDꢅSꢅ
R/W
0
6
PDꢅSꢃ
R/W
0
5
PDꢅS1
R/W
0
4
PDꢅS0
R/W
0
3
PDꢃSꢅ
R/W
0
2
PDꢃSꢃ
R/W
0
1
PDꢃS1
R/W
0
0
PDꢃS0
R/W
0
POR
Bitꢀ7~4
PD3S3~PD3S0:ꢀPortꢀD3ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP3
0010:ꢀSCK/SCL
0100:ꢀSDO
0101:ꢀTP3B
Others:ꢀReserved
Bitꢀ3~0
PD2S3~PD2S0:ꢀPortꢀD2ꢀFunctionꢀSelection
0000:ꢀI/O
0010:ꢀSDI/SDA
Others:ꢀReserved
Rev. 1.00
85
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• PDS2
Bit
Name
R/W
7
PD5Sꢅ
R/W
0
6
PD5Sꢃ
R/W
0
5
PD5S1
R/W
0
4
PD5S0
R/W
0
3
PD4Sꢅ
R/W
0
2
PD4Sꢃ
R/W
0
1
PD4S1
R/W
0
0
PD4S0
R/W
0
POR
Bitꢀ7~4
PD5S3~PD5S0:ꢀPortꢀD5ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP0
0010:ꢀTP0B
Others:ꢀReserved
Bitꢀ3~0
PD4S3~PD4S0:ꢀPortꢀD4ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP2
0010:ꢀTP2B
Others:ꢀReserved
• PDS3
Bit
Name
R/W
7
PD7Sꢅ
R/W
0
6
PD7Sꢃ
R/W
0
5
PD7S1
R/W
0
4
PD7S0
R/W
0
3
PD6Sꢅ
R/W
0
2
PD6Sꢃ
R/W
0
1
PD6S1
R/W
0
0
PD6S0
R/W
0
POR
Bitꢀ7~4
PD7S3~PD7S0:ꢀPortꢀD7ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀSCS
Others:ꢀReserved
Bitꢀ3~0
PD6S3~PD6S0:ꢀPortꢀD6ꢀFunctionꢀSelection
0000:ꢀI/O
0010:ꢀSCK/SCL
Others:ꢀReserved
• PES0
Bit
Name
R/W
7
PE1Sꢅ
R/W
0
6
PE1Sꢃ
R/W
0
5
PE1S1
R/W
0
4
PE1S0
R/W
0
3
PE0Sꢅ
R/W
0
2
PE0Sꢃ
R/W
0
1
PE0S1
R/W
0
0
PE0S0
R/W
0
POR
Bitꢀ7~4
PE1S3~PE1S0:ꢀPortꢀE1ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀSCKA
Others:ꢀReserved
Bitꢀ3~0
PE0S3~PE0S0:ꢀPortꢀE0ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀSCSA
Others:ꢀReserved
Rev. 1.00
86
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• PES1
Bit
Name
R/W
7
PEꢅSꢅ
R/W
0
6
PEꢅSꢃ
R/W
0
5
PEꢅS1
R/W
0
4
PEꢅS0
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~4
PE3S3~PE3S0:ꢀPortꢀE3ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀSDOA
Others:ꢀReserved
Bitꢀ3~0ꢀ
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten.
• PES2
Bit
Name
R/W
7
PE5Sꢅ
R/W
0
6
PE5Sꢃ
R/W
0
5
PE5S1
R/W
0
4
PE5S0
R/W
0
3
PE4Sꢅ
R/W
0
2
PE4Sꢃ
R/W
0
1
PE4S1
R/W
0
0
PE4S0
R/W
0
POR
Bitꢀ7~4
PE5S3~PE5S0:ꢀPortꢀE5ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP3
0010:ꢀTP3B
Others:ꢀReserved
Bitꢀ3~0
PE4S3~PE4S0:ꢀPortꢀE4ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP1B
0010:ꢀTP1BB
Others:ꢀReserved
• PES3
Bit
Name
R/W
7
PE7Sꢅ
R/W
0
6
PE7Sꢃ
R/W
0
5
PE7S1
R/W
0
4
PE7S0
R/W
0
3
PE6Sꢅ
R/W
0
2
PE6Sꢃ
R/W
0
1
PE6S1
R/W
0
0
PE6S0
R/W
0
POR
Bitꢀ7~4
PE7S3~PE7S0:ꢀPortꢀE7ꢀFunctionꢀSelection
0000:ꢀI/O
0011:ꢀAN9
Others:ꢀReserved
Bitꢀ3~0
PE6S3~PE6S0:ꢀPortꢀE6ꢀFunctionꢀSelection
0000:ꢀI/O
0011:ꢀAN8
Others:ꢀReserved
Rev. 1.00
87
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• PFS0
Bit
Name
R/W
7
PF1Sꢅ
R/W
0
6
PF1Sꢃ
R/W
0
5
PF1S1
R/W
0
4
PF1S0
R/W
0
3
PF0Sꢅ
R/W
0
2
PF0Sꢃ
R/W
0
1
PF0S1
R/W
0
0
PF0S0
R/W
0
POR
Bitꢀ7~4
PF1S3~PF1S0:ꢀPortꢀF1ꢀFunctionꢀSelection
0000:ꢀI/O
0011:ꢀAN11
0111:ꢀC1P
1111:ꢀAN11ꢀandꢀC1P
Others:ꢀReserved
Bitꢀ3~0
PF0S3~PF0S0:ꢀPortꢀF0ꢀFunctionꢀSelection
0000:ꢀI/O
0011:ꢀAN10
0111:C1N
1111:ꢀAN10ꢀandꢀC1N
Others:ꢀReserved
• PGS0
Bit
Name
R/W
7
PG1Sꢅ
R/W
0
6
PG1Sꢃ
R/W
0
5
PG1S1
R/W
0
4
PG1S0
R/W
0
3
PG0Sꢅ
R/W
0
2
PG0Sꢃ
R/W
0
1
PG0S1
R/W
0
0
PG0S0
R/W
0
POR
Bitꢀ7~4
PG1S3~PG1S0:ꢀPortꢀG1ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀC1X
Others:ꢀReserved
Bitꢀ3~0
PG0S3~PG0S0:ꢀPortꢀG0ꢀFunctionꢀSelection
0000:ꢀI/O
0001:C0X
Others:ꢀReserved
• PGS1
Bit
Name
R/W
7
PGꢅSꢅ
R/W
0
6
PGꢅSꢃ
R/W
0
5
PGꢅS1
R/W
0
4
PGꢅS0
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~4
PG3S3~PG3S0:ꢀPortꢀG3ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP4
0010:ꢀTP4B
Others:ꢀReserved
Bitꢀ3~0ꢀ
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten.
Rev. 1.00
88
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• PGS2
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
PG4Sꢅ
R/W
0
2
PG4Sꢃ
R/W
0
1
PG4S1
R/W
0
0
PG4S0
R/W
0
POR
Bitꢀ7~4ꢀ
Bitꢀ3~0
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten.
PG4S3~PG4S0:ꢀPortꢀG4ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP4
0010:ꢀTP4B
Others:ꢀReserved
• PGS3
Bit
Name
R/W
7
PG7Sꢅ
R/W
0
6
PG7Sꢃ
R/W
0
5
PG7S1
R/W
0
4
PG7S0
R/W
0
3
PG6Sꢅ
R/W
0
2
PG6Sꢃ
R/W
0
1
PG6S1
R/W
0
0
PG6S0
R/W
0
POR
Bitꢀ7~4
PG7S3~PG7S0:ꢀPortꢀG7ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP5
0010:ꢀTP5B
Others:ꢀReserved
Bitꢀ3~0
PG6S3~PG6S0:ꢀPortꢀG6ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP5
0010:ꢀTP5B
Others:ꢀReserved
• PHS0
Bit
Name
R/W
7
PH1Sꢅ
R/W
0
6
PH1Sꢃ
R/W
0
5
PH1S1
R/W
0
4
PH1S0
R/W
0
3
PH0Sꢅ
R/W
0
2
PH0Sꢃ
R/W
0
1
PH0S1
R/W
0
0
PH0S0
R/W
0
POR
Bitꢀ7~4
PH1S3~PH1S0:ꢀPortꢀH1ꢀFunctionꢀSelection
0000:ꢀI/O
0011:ꢀAN2
0111:ꢀC0P
1111:ꢀAN2ꢀandꢀC0P
Others:ꢀReserved
Bitꢀ3~0
PH0S3~PH0S0:ꢀPortꢀH0ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀTP0
0010:ꢀC0X
0011:ꢀAN0/VREF
0100:ꢀTP0B
Others:ꢀReserved
Rev. 1.00
89
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• PHS1
Bit
Name
R/W
7
PHꢅSꢅ
R/W
0
6
PHꢅSꢃ
R/W
0
5
PHꢅS1
R/W
0
4
PHꢅS0
R/W
0
3
PHꢃSꢅ
R/W
0
2
PHꢃSꢃ
R/W
0
1
PHꢃS1
R/W
0
0
PHꢃS0
R/W
0
POR
Bitꢀ7~4
PH3S3~PH3S0:ꢀPortꢀH3ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀSCKA
Others:ꢀReserved
Bitꢀ3~0
PH2S3~PH2S0:ꢀPortꢀH2ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀSCSA
Others:ꢀReserved
• PHS2
Bit
Name
R/W
7
PH5Sꢅ
R/W
0
6
PH5Sꢃ
R/W
0
5
PH5S1
R/W
0
4
PH5S0
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~4
PH5S3~PH5S0:ꢀPortꢀH5ꢀFunctionꢀSelection
0000:ꢀI/O
0001:ꢀSDOA
Others:ꢀReserved
Bitꢀ3~0ꢀ
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten.
• IFS0
Bit
Name
R/W
7
6
5
4
INTꢃS0
R/W
0
3
INT1S1
R/W
0
2
INT1S0
R/W
0
1
INT0S1
R/W
0
0
INT0S0
R/W
0
PINTBS1 PINTBS0 INTꢃS1
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6
Bitꢀ5~4
Bitꢀ3~2
PINTBS1~PINTBS0:ꢀPINTꢀinputꢀsourceꢀpinꢀselection
00:ꢀPC3
Others:ꢀPC4
INT2S1~INT2S0:ꢀINT2ꢀinputꢀsourceꢀpinꢀselection
00:ꢀPC4
Others:ꢀPE2
INT1S1~INT1S0:ꢀINT1ꢀinputꢀsourceꢀpinꢀselection
00:ꢀPA4
01:ꢀPC5
10:ꢀPE1
11:ꢀPE7
Bitꢀ1~0
INT0S1~INT0S0:ꢀINT0ꢀinputꢀsourceꢀpinꢀselection
00:ꢀPA3
01:ꢀPC4
10:ꢀPE0
11:ꢀPE6
Rev. 1.00
90
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• IFS1
Bit
Name
R/W
7
6
5
4
3
2
1
0
TCKꢅS1 TCKꢅS0 TCKꢃS1 TCKꢃS0 TCK1S1 TCK1S0 TCK0S1 TCK0S0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6
Bitꢀ5~4
Bitꢀ3~2
Bitꢀ1~0
TCK3S1~TCK3S0:ꢀTCK3ꢀinputꢀsourceꢀpinꢀselection
00:ꢀPC4
Others:ꢀPE3
TCK2S1~TCK2S0:ꢀTCK2ꢀinputꢀsourceꢀpinꢀselection
00:ꢀPC2
Others:ꢀPD0
TCK1S1~TCK1S0:ꢀTCK1ꢀinputꢀsourceꢀpinꢀselection
00:ꢀPA4
Others:ꢀPD3
TCK0S1~TCK0S0:ꢀTCK0ꢀinputꢀsourceꢀpinꢀselection
00:ꢀPH1
Others:ꢀPD2
• IFS2
Bit
Name
R/W
7
TPꢃIS1
R/W
0
6
5
4
3
2
1
D1
R/W
0
0
D0
R/W
0
TPꢃIS0 TP1IBS1 TP1IBS0 TP1IAS1 TP1IAS0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6
Bitꢀ5~4
Bitꢀ3~2
TP2IS1~TP2IS0:ꢀTP2Iꢀinputꢀsourceꢀpinꢀselection
00:ꢀPC3
01:ꢀPC4
10:ꢀPD1
11:ꢀPD4
TP1IBS1~TP1IBS0:ꢀTP1IBꢀinputꢀsourceꢀpinꢀselection
00:ꢀPC0
01:ꢀPC1
10:ꢀPC5
11:ꢀPE4
TP1IAS1~TP1IAS0:ꢀTP1IAꢀinputꢀsourceꢀpinꢀselection
00:ꢀPA1
Others:ꢀPC7
Bitꢀ1~0ꢀ
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten.
• IFS3
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
TP5IS1
R/W
0
4
TP5IS0
R/W
0
3
TP4IS1
R/W
0
2
TP4IS0
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~4
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten.
TP5IS1~TP5IS0:ꢀTP5Iꢀinputꢀsourceꢀpinꢀselection
00:ꢀPG6
Others:ꢀPG7
Bitꢀ3~2
Bitꢀ1~0ꢀ
TP4IS1~TP4IS0:ꢀTP4Iꢀinputꢀsourceꢀpinꢀselection
00:ꢀPG3
Others:ꢀPG4
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten.
Rev. 1.00
91
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• IFS4
Bit
7
D7
R/W
0
6
D6
R/W
0
5
SDIS1
R/W
0
4
SDIS0
R/W
0
3
SCKS1
R/W
0
2
1
0
Name
SCKS0 SCSBS1 SCSBS0
R/W
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~4
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten.
SDIS1~SDIS0:ꢀSDI/SDAꢀinputꢀsourceꢀpinꢀselection
00:ꢀPA6
01:ꢀPB7
Others:ꢀPD2
Bitꢀ3~2
SCKS1~SCKS0:ꢀSCK/SCLꢀinputꢀsourceꢀpinꢀselection
00:ꢀPA7
01:ꢀPD3
10:ꢀPD1
11:ꢀPD6
Bitꢀ1~0
SCSBS1~SCSBS0:ꢀSCSꢀinputꢀsourceꢀpinꢀselection
00:ꢀPB5
01:ꢀPD0
Others:ꢀPD7
• IFS5
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
4
3
2
1
0
SDIAS1 SDIAS0 SCKAS1 SCKAS0 SCSABS1 SCSABS0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~4
Reservedꢀbits,ꢀcanꢀbeꢀreadꢀandꢀwritten.
SDIAS1~SDIAS0:ꢀSDIAꢀinputꢀsourceꢀpinꢀselection
00:ꢀPE2
Others:ꢀPH4
Bitꢀ3~2
Bitꢀ1~0
SCKAS1~SCKAS0:ꢀSCKAꢀinputꢀsourceꢀpinꢀselection
00:ꢀPE1
Others:ꢀPH3
SCSABS1~SCSABS0:ꢀSCSAꢀinputꢀsourceꢀpinꢀselection
00:ꢀPE0
Others:ꢀPH2
Rev. 1.00
9ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
I/O Pin Structures
TheꢀaccompanyingꢀdiagramsꢀillustrateꢀtheꢀinternalꢀstructuresꢀofꢀsomeꢀgenericꢀI/Oꢀpinꢀtypes.ꢀAsꢀ
theꢀexactꢀlogicalꢀconstructionꢀofꢀtheꢀI/Oꢀpinꢀwillꢀdifferꢀfromꢀtheseꢀdrawings,ꢀtheyꢀareꢀsuppliedꢀasꢀaꢀ
guideꢀonlyꢀtoꢀassistꢀwithꢀtheꢀfunctionalꢀunderstandingꢀofꢀtheꢀI/Oꢀpins.ꢀTheꢀwideꢀrangeꢀofꢀpin-sharedꢀ
structuresꢀdoesꢀnotꢀpermitꢀallꢀtypesꢀtoꢀbeꢀshown.
V
D
D
P
l
u
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Generic Input/Output Structure
V
D
D
P
l
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g
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C
A
0
S
A/D Input/Output Structure
Rev. 1.00
9ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Programming Considerations
Withinꢀtheꢀuserꢀprogram,ꢀoneꢀofꢀtheꢀthingsꢀfirstꢀtoꢀconsiderꢀisꢀportꢀinitialisation.ꢀAfterꢀaꢀreset,ꢀallꢀ
ofꢀtheꢀI/Oꢀdataꢀandꢀportꢀcontrolꢀregistersꢀwillꢀbeꢀsetꢀtoꢀhigh.ꢀThisꢀmeansꢀthatꢀallꢀI/Oꢀpinsꢀwillꢀbeꢀ
defaultedꢀtoꢀanꢀinputꢀstate,ꢀtheꢀlevelꢀofꢀwhichꢀdependsꢀonꢀtheꢀotherꢀconnectedꢀcircuitryꢀandꢀwhetherꢀ
pull-highꢀselectionsꢀhaveꢀbeenꢀchosen.ꢀIfꢀtheꢀportꢀcontrolꢀregistersꢀareꢀthenꢀprogrammedꢀtoꢀsetupꢀ
someꢀpinsꢀasꢀoutputs,ꢀtheseꢀoutputꢀpinsꢀwillꢀhaveꢀanꢀinitialꢀhighꢀoutputꢀvalueꢀunlessꢀtheꢀassociatedꢀ
portꢀdataꢀregistersꢀareꢀfirstꢀprogrammed.ꢀSelectingꢀwhichꢀpinsꢀareꢀinputsꢀandꢀwhichꢀareꢀoutputsꢀcanꢀ
beꢀachievedꢀbyte-wideꢀbyꢀloadingꢀtheꢀcorrectꢀvaluesꢀintoꢀtheꢀappropriateꢀportꢀcontrolꢀregisterꢀorꢀ
byꢀprogrammingꢀindividualꢀbitsꢀinꢀtheꢀportꢀcontrolꢀregisterꢀusingꢀtheꢀ“SETꢀ[m].i”ꢀandꢀ“CLRꢀ[m].i”ꢀ
instructions.ꢀNoteꢀthatꢀwhenꢀusingꢀtheseꢀbitꢀcontrolꢀinstructions,ꢀaꢀread-modify-writeꢀoperationꢀtakesꢀ
place.ꢀTheꢀmicrocontrollerꢀmustꢀfirstꢀreadꢀinꢀtheꢀdataꢀonꢀtheꢀentireꢀport,ꢀmodifyꢀitꢀtoꢀtheꢀrequiredꢀnewꢀ
bitꢀvaluesꢀandꢀthenꢀrewriteꢀthisꢀdataꢀbackꢀtoꢀtheꢀoutputꢀports.
PortꢀAꢀhasꢀtheꢀadditionalꢀcapabilityꢀofꢀprovidingꢀwake-upꢀfunctions.ꢀWhenꢀtheꢀdeviceꢀisꢀinꢀtheꢀ
SLEEPꢀorꢀIDLEꢀMode,ꢀvariousꢀmethodsꢀareꢀavailableꢀtoꢀwakeꢀtheꢀdeviceꢀup.ꢀOneꢀofꢀtheseꢀisꢀaꢀhighꢀ
toꢀlowꢀtransitionꢀofꢀanyꢀofꢀtheꢀPortꢀAꢀpins.ꢀSingleꢀorꢀmultipleꢀpinsꢀonꢀPortꢀAꢀcanꢀbeꢀsetupꢀtoꢀhaveꢀthisꢀ
function.
Timer Modules – TM
Oneꢀofꢀtheꢀmostꢀfundamentalꢀfunctionsꢀinꢀanyꢀmicrocontrollerꢀdevicesꢀisꢀtheꢀabilityꢀtoꢀcontrolꢀandꢀ
measureꢀtime.ꢀToꢀimplementꢀtimeꢀrelatedꢀfunctionsꢀeachꢀdeviceꢀincludesꢀseveralꢀTimerꢀModules,ꢀ
abbreviatedꢀtoꢀtheꢀnameꢀTM.ꢀTheꢀTMsꢀareꢀmulti-purposeꢀtimingꢀunitsꢀandꢀserveꢀtoꢀprovideꢀ
operationsꢀsuchꢀasꢀTimer/Counter,ꢀInputꢀCapture,ꢀCompareꢀMatchꢀOutputꢀandꢀSingleꢀPulseꢀOutputꢀ
asꢀwellꢀasꢀbeingꢀtheꢀfunctionalꢀunitꢀforꢀtheꢀgenerationꢀofꢀPWMꢀsignals.ꢀEachꢀofꢀtheꢀTMsꢀhasꢀ
eitherꢀmultipleꢀinterrupts.ꢀTheꢀadditionꢀofꢀinputꢀandꢀoutputꢀpinsꢀforꢀeachꢀTMꢀensuresꢀthatꢀusersꢀareꢀ
providedꢀwithꢀtimingꢀunitsꢀwithꢀaꢀwideꢀandꢀflexibleꢀrangeꢀofꢀfeatures.
TheꢀcommonꢀfeaturesꢀofꢀtheꢀdifferentꢀTMꢀtypesꢀareꢀdescribedꢀhereꢀwithꢀmoreꢀdetailedꢀinformationꢀ
providedꢀinꢀtheꢀindividualꢀCompactꢀandꢀStandardꢀTMꢀsections.
Introduction
TheꢀdevicesꢀcontainꢀfromꢀtwoꢀtoꢀsixꢀTMsꢀdependingꢀuponꢀwhichꢀdeviceꢀisꢀselectedꢀwithꢀeachꢀTMꢀ
havingꢀaꢀreferenceꢀnameꢀofꢀTM0~TM5.ꢀEachꢀindividualꢀTMꢀcanꢀbeꢀcategorisedꢀasꢀaꢀcertainꢀtype,ꢀ
namelyꢀCompactꢀTypeꢀTM,ꢀStandardꢀTypeꢀTMꢀorꢀEnhancedꢀTypeꢀTM.ꢀAlthoughꢀsimilarꢀinꢀnature,ꢀ
theꢀdifferentꢀTMꢀtypesꢀvaryꢀinꢀtheirꢀfeatureꢀcomplexity.ꢀTheꢀcommonꢀfeaturesꢀtoꢀallꢀofꢀtheꢀCompact,ꢀ
StandardꢀandꢀEnhancedꢀTMsꢀwillꢀbeꢀdescribedꢀinꢀthisꢀsection,ꢀtheꢀdetailedꢀoperationꢀregardingꢀeachꢀ
ofꢀtheꢀTMꢀtypesꢀwillꢀbeꢀdescribedꢀinꢀseparateꢀsections.ꢀTheꢀmainꢀfeaturesꢀandꢀdifferencesꢀbetweenꢀ
theꢀthreeꢀtypesꢀofꢀTMsꢀareꢀsummarisedꢀinꢀtheꢀaccompanyingꢀtable.
TM Function
Timeꢀ/Counteꢀ
CTM
STM
ETM
√
√
√
I/P Captuꢀe
—
√
√
Compaꢀe �atꢁꢂ Output
PW� Cꢂannels
√
√
√
1
—
1
ꢃ
Single Pulse Output
PW� Alignment
1
ꢃ
Edge
Edge
Edge & Centꢀe
Duty oꢀ Peꢀiod
PW� Adjustment Peꢀiod & Duty
Duty oꢀ Peꢀiod
Duty oꢀ Peꢀiod
TM Function Summary
Rev. 1.00
94
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
EachꢀdeviceꢀinꢀtheꢀseriesꢀcontainsꢀaꢀspecificꢀnumberꢀofꢀeitherꢀCompactꢀType,ꢀStandardꢀTypeꢀandꢀ
EnhancedꢀTypeꢀTMꢀunitꢀwhichꢀareꢀshownꢀinꢀtheꢀtableꢀtogetherꢀwithꢀtheirꢀindividualꢀreferenceꢀname,ꢀ
TM0~TM5.
Device
TM0
TM1
TM2
TM3
TM4
TM5
HT66F60A
HT66F70A
10-bit CT�
10-bit ET�
16-bit ST�
10-bit CT�
16-bit ST�
16-bit ST�
TM Name/Type Reference
TM Operation
TheꢀdifferentꢀtypesꢀofꢀTMꢀofferꢀaꢀdiverseꢀrangeꢀofꢀfunctions,ꢀfromꢀsimpleꢀtimingꢀoperationsꢀtoꢀ
PWMꢀsignalꢀgeneration.ꢀTheꢀkeyꢀtoꢀunderstandingꢀhowꢀtheꢀTMꢀoperatesꢀisꢀtoꢀseeꢀitꢀinꢀtermsꢀofꢀ
aꢀfreeꢀrunningꢀcounterꢀwhoseꢀvalueꢀisꢀthenꢀcomparedꢀwithꢀtheꢀvalueꢀofꢀpre-programmedꢀinternalꢀ
comparators.ꢀWhenꢀtheꢀfreeꢀrunningꢀcounterꢀhasꢀtheꢀsameꢀvalueꢀasꢀtheꢀpre-programmedꢀcomparator,ꢀ
knownꢀasꢀaꢀcompareꢀmatchꢀsituation,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀbeꢀgeneratedꢀwhichꢀcanꢀclearꢀtheꢀ
counterꢀandꢀperhapsꢀalsoꢀchangeꢀtheꢀconditionꢀofꢀtheꢀTMꢀoutputꢀpin.ꢀTheꢀinternalꢀTMꢀcounterꢀisꢀ
drivenꢀbyꢀaꢀuserꢀselectableꢀclockꢀsource,ꢀwhichꢀcanꢀbeꢀanꢀinternalꢀclockꢀorꢀanꢀexternalꢀpin.
TM Clock Source
TheꢀclockꢀsourceꢀwhichꢀdrivesꢀtheꢀmainꢀcounterꢀinꢀeachꢀTMꢀcanꢀoriginateꢀfromꢀvariousꢀsources.ꢀTheꢀ
selectionꢀofꢀtheꢀrequiredꢀclockꢀsourceꢀisꢀimplementedꢀusingꢀtheꢀTnCK2~TnCK0ꢀbitsꢀinꢀtheꢀTMnꢀ
controlꢀregisters.ꢀTheꢀclockꢀsourceꢀcanꢀbeꢀaꢀratioꢀofꢀeitherꢀtheꢀsystemꢀclockꢀfSYSꢀorꢀtheꢀinternalꢀhighꢀ
clockꢀfH,ꢀtheꢀfSUBꢀclockꢀsourceꢀorꢀtheꢀexternalꢀTCKnꢀpin.ꢀNoteꢀthatꢀsettingꢀtheseꢀbitsꢀtoꢀtheꢀvalueꢀ101ꢀ
willꢀselectꢀaꢀreservedꢀclockꢀinput,ꢀinꢀeffectꢀdisconnectingꢀtheꢀTMꢀclockꢀsource.ꢀTheꢀTCKnꢀpinꢀclockꢀ
sourceꢀisꢀusedꢀtoꢀallowꢀanꢀexternalꢀsignalꢀtoꢀdriveꢀtheꢀTMꢀasꢀanꢀexternalꢀclockꢀsourceꢀorꢀforꢀeventꢀ
counting.
TM Interrupts
TheꢀCompactꢀtypeꢀTMꢀhasꢀtwoꢀinternalꢀinterrupts,ꢀoneꢀforꢀeachꢀofꢀtheꢀinternalꢀcomparatorꢀAꢀ
orꢀcomparatorꢀP,ꢀwhichꢀgenerateꢀaꢀTMꢀinterruptꢀwhenꢀaꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀAsꢀ
theꢀEnhancedꢀtypeꢀTMꢀhasꢀthreeꢀinternalꢀcomparatorsꢀandꢀcomparatorꢀAꢀorꢀcomparatorꢀBꢀorꢀ
comparatorꢀPꢀcompareꢀmatchꢀfunctions,ꢀitꢀconsequentlyꢀhasꢀthreeꢀinternalꢀinterrupts.ꢀWhenꢀaꢀTMꢀ
interruptꢀisꢀgeneratedꢀitꢀcanꢀbeꢀusedꢀtoꢀclearꢀtheꢀcounterꢀandꢀalsoꢀtoꢀchangeꢀtheꢀstateꢀofꢀtheꢀTMꢀ
outputꢀpin.
Rev. 1.00
95
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
TM External Pins
EachꢀofꢀtheꢀTMs,ꢀirrespectiveꢀofꢀwhatꢀtype,ꢀhasꢀtwoꢀTMꢀinputꢀpins,ꢀwithꢀtheꢀlabelꢀTCKnꢀandꢀTPnIꢀ
respectively.ꢀTheꢀTMꢀinputꢀpin,ꢀTCKn,ꢀisꢀessentiallyꢀaꢀclockꢀsourceꢀforꢀtheꢀTMꢀandꢀisꢀselectedꢀusingꢀ
theꢀTnCK2~TnCK0ꢀbitsꢀinꢀtheꢀTMnC0ꢀregister.ꢀThisꢀexternalꢀTMꢀinputꢀpinꢀallowsꢀanꢀexternalꢀclockꢀ
sourceꢀtoꢀdriveꢀtheꢀinternalꢀTM.ꢀThisꢀexternalꢀTMꢀinputꢀpinꢀisꢀsharedꢀwithꢀotherꢀfunctionsꢀbutꢀwillꢀ
beꢀconnectedꢀtoꢀtheꢀinternalꢀTMꢀifꢀselectedꢀusingꢀtheꢀTnCK2~TnCK0ꢀbits.ꢀTheꢀTMꢀinputꢀpinꢀcanꢀ
beꢀchosenꢀtoꢀhaveꢀeitherꢀaꢀrisingꢀorꢀfallingꢀactiveꢀedge.ꢀTheꢀTCKnꢀpinꢀisꢀalsoꢀusedꢀasꢀtheꢀexternalꢀ
triggerꢀinputꢀpinꢀinꢀsingleꢀpulseꢀmodeꢀforꢀtheꢀSTMꢀandꢀETM.
TheꢀotherꢀTMꢀinputꢀpin,ꢀTPnI,ꢀisꢀtheꢀcaptureꢀinputꢀwhoseꢀactiveꢀedgeꢀcanꢀbeꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀ
edgeꢀorꢀbothꢀrisingꢀandꢀfallingꢀedgesꢀandꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀusingꢀtheꢀTnIO1ꢀ
andꢀTnIO0ꢀbitsꢀinꢀtheꢀTMnC1ꢀregister.
TheꢀTMsꢀeachꢀhaveꢀoneꢀorꢀmoreꢀoutputꢀpinsꢀwithꢀtheꢀlabelꢀTPnꢀandꢀTPnBꢀrespectively.ꢀWhenꢀtheꢀ
TMꢀisꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀbyꢀtheꢀTMꢀtoꢀswitchꢀtoꢀ
aꢀhighꢀorꢀlowꢀlevelꢀorꢀtoꢀtoggleꢀwhenꢀaꢀcompareꢀmatchꢀsituationꢀoccurs.ꢀTheꢀexternalꢀTPnꢀoutputꢀ
pinꢀisꢀalsoꢀtheꢀpinꢀwhereꢀtheꢀTMꢀgeneratesꢀtheꢀPWMꢀoutputꢀwaveform.ꢀAsꢀtheꢀTMꢀoutputꢀpinsꢀ
areꢀpin-sharedꢀwithꢀotherꢀfunction,ꢀtheꢀTMꢀoutputꢀfunctionꢀmustꢀfirstꢀbeꢀsetupꢀusingꢀregisters.ꢀTheꢀ
correspondingꢀselectionꢀbitsꢀinꢀtheꢀpin-sharedꢀfunctionꢀregistersꢀdeterminesꢀifꢀitsꢀassociatedꢀpinꢀisꢀtoꢀ
beꢀusedꢀasꢀanꢀexternalꢀTMꢀoutputꢀpinꢀorꢀifꢀitꢀisꢀtoꢀhaveꢀanotherꢀfunction.ꢀTheꢀnumberꢀofꢀoutputꢀpinsꢀ
forꢀeachꢀTMꢀtypeꢀandꢀdeviceꢀisꢀdifferent,ꢀtheꢀdetailsꢀareꢀprovidedꢀinꢀtheꢀaccompanyingꢀtable.
Device
CTM
ETM
STM
Registers
TPꢃꢄ TPꢃBꢄ TPꢃIꢄ TCKꢃ
TP4ꢄ TP4Bꢄ TP4Iꢄ TCK4
TP5ꢄ TP5Bꢄ TP5Iꢄ TCK5
HT66F60A
HT66F70A
TP0ꢄ TP0Bꢄ TCK0
TPꢅꢄ TPꢅBꢄ TCKꢅ
TP1Aꢄ TP1IAꢄ TCK1
TP1Bꢄ TP1BBꢄ TP1IB
IFSi
TM Input/Output Pins
Rev. 1.00
96
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
TM Input/Output Pin Control
SelectingꢀtoꢀhaveꢀaꢀTMꢀinput/outputꢀorꢀwhetherꢀtoꢀretainꢀitsꢀotherꢀsharedꢀfunctionꢀisꢀimplementedꢀ
usingꢀoneꢀorꢀtwoꢀregisters,ꢀwithꢀtheꢀcorrespondingꢀselectionꢀbitsꢀinꢀeachꢀpin-sharedꢀfunctionꢀ
registerꢀcorrespondingꢀtoꢀaꢀTMꢀinput/outputꢀpin.ꢀConfiguringꢀtheꢀselectionꢀbitsꢀcorrectlyꢀwillꢀsetupꢀ
theꢀcorrespondingꢀpinꢀasꢀaꢀTMꢀinput/output.ꢀTheꢀdetailsꢀofꢀtheꢀpin-sharedꢀfunctionꢀselectionꢀareꢀ
describedꢀinꢀtheꢀpin-sharedꢀfunctionꢀsection.ꢀ
TCKn
CTM
(TMn)
CCR output
TPn
TPnB
CCR inveꢀted output
CTM Function Pin Control Block Diagram (n=0 or 3)
TCKn
STM
(TMn)
CCR ꢁaptuꢀe input
CCR output
TPnI
TPn
TPnB
CCR inveꢀted output
STM Function Pin Control Block Diagram (n=2, 4, 5)
TCK1
ETM
(TM1)
CCRA ꢁaptuꢀe input
CCRA output
TP1IA
TP1A
CCRB ꢁaptuꢀe input
CCRB output
TP1IB
TP1B
TP1BB
CCRB inveꢀted output
ETM Function Pin Control Block Diagram
Rev. 1.00
97
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Programming Considerations
TheꢀTMꢀCounterꢀRegistersꢀandꢀtheꢀCapture/CompareꢀCCRAꢀandꢀCCRBꢀregisters,ꢀallꢀhaveꢀaꢀlowꢀ
andꢀhighꢀbyteꢀstructure.ꢀTheꢀhighꢀbytesꢀcanꢀbeꢀdirectlyꢀaccessed,ꢀbutꢀasꢀtheꢀlowꢀbytesꢀcanꢀonlyꢀbeꢀ
accessedꢀviaꢀanꢀinternalꢀ8-bitꢀbuffer,ꢀreadingꢀorꢀwritingꢀtoꢀtheseꢀregisterꢀpairsꢀmustꢀbeꢀcarriedꢀoutꢀinꢀ
aꢀspecificꢀway.ꢀTheꢀimportantꢀpointꢀtoꢀnoteꢀisꢀthatꢀdataꢀtransferꢀtoꢀandꢀfromꢀtheꢀ8-bitꢀbufferꢀandꢀitsꢀ
relatedꢀlowꢀbyteꢀonlyꢀtakesꢀplaceꢀwhenꢀaꢀwriteꢀorꢀreadꢀoperationꢀtoꢀitsꢀcorrespondingꢀhighꢀbyteꢀisꢀ
executed.
T� Counteꢀ Registeꢀ (Read only)
T�xDL T�xDH
8-bit
Buffeꢀ
T�xAL T�xAH
T� CCRA Registeꢀ (Read/Wꢀite)
T�xBL T�xBH
T� CCRB Registeꢀ (Read/Wꢀite)
Data
Bus
AsꢀtheꢀCCRAꢀandꢀCCRBꢀregistersꢀareꢀimplementedꢀinꢀtheꢀwayꢀshownꢀinꢀtheꢀfollowingꢀdiagramꢀandꢀ
accessingꢀtheseꢀregisterꢀpairsꢀisꢀcarriedꢀoutꢀinꢀaꢀspecificꢀwayꢀasꢀdescribedꢀabove,ꢀitꢀisꢀrecommendedꢀ
toꢀuseꢀtheꢀ"MOV"ꢀinstructionꢀtoꢀaccessꢀtheꢀCCRAꢀandꢀCCRBꢀlowꢀbyteꢀregisters,ꢀnamedꢀTMxALꢀandꢀ
TMxBL,ꢀusingꢀtheꢀfollowingꢀaccessꢀprocedures.ꢀAccessingꢀtheꢀCCRAꢀorꢀCCRBꢀlowꢀbyteꢀregistersꢀ
withoutꢀfollowingꢀtheseꢀaccessꢀproceduresꢀwillꢀresultꢀinꢀunpredictableꢀvalues.
Theꢀfollowingꢀstepsꢀshowꢀtheꢀreadꢀandꢀwriteꢀprocedures:
•ꢀ WritingꢀDataꢀtoꢀCCRBꢀorꢀCCRA
ꢀ
♦
Stepꢀ1.ꢀWriteꢀdataꢀtoꢀLowꢀByteꢀTMxALꢀorꢀTMxBL
–ꢀnoteꢀthatꢀhereꢀdataꢀisꢀonlyꢀwrittenꢀtoꢀtheꢀ8-bitꢀbuffer.
ꢀ
♦
Stepꢀ2.ꢀWriteꢀdataꢀtoꢀHighꢀByteꢀTMxAHꢀorꢀTMxBH
–ꢀhereꢀdataꢀisꢀwrittenꢀdirectlyꢀtoꢀtheꢀhighꢀbyteꢀregistersꢀandꢀsimultaneouslyꢀdataꢀisꢀlatchedꢀ
fromꢀtheꢀ8-bitꢀbufferꢀtoꢀtheꢀLowꢀByteꢀregisters.
•ꢀ ReadingꢀDataꢀfromꢀtheꢀCounterꢀRegistersꢀandꢀCCRBꢀorꢀCCRA
ꢀ
♦
Stepꢀ1.ꢀReadꢀdataꢀfromꢀtheꢀHighꢀByteꢀTMxDH,ꢀTMxAHꢀorꢀTMxBH
–ꢀhereꢀdataꢀisꢀreadꢀdirectlyꢀfromꢀꢀtheꢀHighꢀByteꢀregistersꢀandꢀsimultaneouslyꢀdataꢀisꢀlatchedꢀ
fromꢀtheꢀLowꢀByteꢀregisterꢀintoꢀtheꢀ8-bitꢀbuffer.
ꢀ
♦
Stepꢀ2.ꢀReadꢀdataꢀfromꢀtheꢀLowꢀByteꢀTMxDL,ꢀTMxALꢀorꢀTMxBL
–ꢀthisꢀstepꢀreadsꢀdataꢀfromꢀtheꢀ8-bitꢀbuffer.
Rev. 1.00
98
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Compact Type TM – CTM
AlthoughꢀtheꢀsimplestꢀformꢀofꢀtheꢀtwoꢀTMꢀtypes,ꢀtheꢀCompactꢀTMꢀtypeꢀstillꢀcontainsꢀthreeꢀoperatingꢀ
modes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀTimer/EventꢀCounterꢀandꢀPWMꢀOutputꢀmodes.ꢀTheꢀ
CompactꢀTMꢀcanꢀalsoꢀbeꢀcontrolledꢀwithꢀanꢀexternalꢀinputꢀpinꢀandꢀcanꢀdriveꢀtwoꢀexternalꢀoutputꢀ
pins.ꢀTheseꢀtwoꢀexternalꢀoutputꢀpinsꢀcanꢀbeꢀtheꢀsameꢀsignalꢀorꢀtheꢀinverseꢀsignal.
Device
TM Type
TM Name
TM Input Pin
TM Output Pin
HT66F60A
HT66F70A
10-bit CT�
T�0ꢄ T�ꢅ
TCK0ꢄ TP0I; TCKꢅꢄ TPꢅI
TP0ꢄ TP0B; TPꢅꢄ TPꢅB
C
C
P
R
C
m
o
p
a
a
o
r
t
r
P
M
a
c
t
h
3
-
i
b
t
C
o
m
p
a
a
o
r
t
r
P
T
P
n
F
I
t
n
r
e
r
p
u
t
f
S
Y
/
S
4
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
b
7
b
~
9
f
S
Y
S
T
O
n
C
f
/
6
1
f
/
4
6
T
n
P
f
S
B
U
O
t
u
u
p
t
P
l
o
r
a
t
i
y
O
t
u
u
p
t
C
u
o
n
e
t
r
C
l
e
a
r
0
1
C
o
n
r
l
o
t
C
o
n
r
l
o
t
C
m
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l
p
m
e
e
n
a
y
t
r
R
s
e
r
e
e
v
d
1
0
b
t
-
C
i
u
o
n
-
p
u
t
C
u
o
n
e
t
r
T
n
P
B
T
K
C
n
1
1
1
T
M
n
,
1
T
M
n
0
T
P
n
L
O
T
C
n
C
R
L
T
O
n
N
T
I
n
1
O
,
T
n
O
I
0
b
0
b
~
9
T
P
n
U
A
C
m
o
p
a
a
o
r
t
r
A
M
t
a
h
c
1
0
-
i
b
t
C
o
m
p
a
a
o
r
t
r
A
T
A
n
F
I
t
n
r
e
r
p
u
t
T
C
n
2
K
T
~
C
n
0
K
C
C
A
R
Compact Type TM Block Diagram (n=0 or 3)
Compact TM Operation
Atꢀitsꢀcoreꢀisꢀaꢀ10-bitꢀcount-upꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀaꢀuserꢀselectableꢀinternalꢀorꢀexternalꢀclockꢀ
source.ꢀThereꢀareꢀalsoꢀtwoꢀinternalꢀcomparatorsꢀwithꢀtheꢀnames,ꢀComparatorꢀAꢀandꢀComparatorꢀP.ꢀ
TheseꢀcomparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀwithꢀCCRPꢀandꢀCCRAꢀregisters.ꢀTheꢀ
CCRPꢀisꢀthreeꢀbitsꢀwideꢀwhoseꢀvalueꢀisꢀcomparedꢀwithꢀtheꢀhighestꢀthreeꢀbitsꢀinꢀtheꢀcounterꢀwhileꢀtheꢀ
CCRAꢀisꢀtheꢀtenꢀbitsꢀandꢀthereforeꢀcomparesꢀwithꢀallꢀcounterꢀbits.
Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ10-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ
clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ
automaticallyꢀbyꢀaꢀcounterꢀoverflowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ
Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀCompactꢀ
TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ
sourcesꢀincludingꢀanꢀinputꢀpinꢀandꢀcanꢀalsoꢀcontrolꢀanꢀoutputꢀpin.ꢀAllꢀoperatingꢀsetupꢀconditionsꢀareꢀ
selectedꢀusingꢀrelevantꢀinternalꢀregisters.
Rev. 1.00
99
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Compact Type TM Register Description
OverallꢀoperationꢀofꢀtheꢀCompactꢀTMꢀisꢀcontrolledꢀusingꢀsixꢀregisters.ꢀAꢀreadꢀonlyꢀregisterꢀpairꢀ
existsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ10-bitꢀvalue,ꢀwhileꢀaꢀread/writeꢀregisterꢀpairꢀexistsꢀtoꢀstoreꢀtheꢀ
internalꢀ10-bitꢀCCRAꢀvalue.ꢀTheꢀremainingꢀtwoꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀsetupꢀtheꢀ
differentꢀoperatingꢀandꢀcontrolꢀmodesꢀasꢀwellꢀasꢀtheꢀthreeꢀCCRPꢀbits.
Name
T�nC0
T�nC1
T�nDL
T�nDH
T�nAL
T�nAH
Bit7
TnPAU
Tn�1
D7
Bit6
TnCKꢃ
Tn�0
D6
Bit5
TnCK1
TnIO1
D5
Bit4
TnCK0
TnIO0
D4
Bit3
TnON
TnOC
Dꢅ
Bit2
TnRPꢃ
TnPOL
Dꢃ
Bit1
Bit0
TnRP1
TnRP0
TnDPX TnCCLR
D1
D9
D1
D9
D0
D8
D0
D8
—
—
—
—
—
—
D7
D6
D5
D4
Dꢅ
Dꢃ
—
—
—
—
—
—
Compact TM Register List (n=0 or 3)
TMnDL Register
Bit
Name
R/W
7
D7
R
6
D6
R
5
D5
R
4
D4
R
3
Dꢅ
R
2
Dꢃ
R
1
D1
R
0
D0
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0ꢀ
TMnDL:ꢀTMnꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7ꢀ~ꢀbitꢀ0ꢀ
TMnꢀ10-bitꢀCounterꢀbitꢀ7ꢀ~ꢀbitꢀ0
TMnDH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R
0
D8
R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
0
0
Bitꢀ7~2ꢀ
Bitꢀ1~0ꢀ
Unimplemented,ꢀreadꢀasꢀ"0"
TMnDH:ꢀTMnꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ1ꢀ~ꢀbitꢀ0ꢀ
TMnꢀ10-bitꢀCounterꢀbitꢀ9ꢀ~ꢀbitꢀ8
TMnAL Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0ꢀ
TMnAL:ꢀTMnꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7ꢀ~ꢀbitꢀ0ꢀ
TMnꢀ10-bitꢀCCRAꢀbitꢀ7ꢀ~ꢀbitꢀ0
TMnAH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~2ꢀ
Bitꢀ1~0ꢀ
Unimplemented,ꢀreadꢀasꢀ"0"
TMnAH:ꢀTMnꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ1ꢀ~ꢀbitꢀ0ꢀ
TMnꢀ10-bitꢀCCRAꢀbitꢀ9ꢀ~ꢀbitꢀ8
Rev. 1.00
100
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
TMnC0 Register
Bit
Name
R/W
7
TnPAU
R/W
0
6
TnCKꢃ
R/W
0
5
TnCK1
R/W
0
4
TnCK0
R/W
0
3
TnON
R/W
0
2
TnRPꢃ
R/W
0
1
TnRP1
R/W
0
0
TnRP0
R/W
0
POR
Bitꢀ7
TnPAU:ꢀTMnꢀCounterꢀPauseꢀControl
0:ꢀRun
1:ꢀPause
Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀrestoresꢀ
normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀTMꢀwillꢀremainꢀpoweredꢀupꢀ
andꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀthisꢀbitꢀ
changesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀchangesꢀ
toꢀaꢀlowꢀvalueꢀagain.
Bitꢀ6~4ꢀ
TnCK2~TnCK0:ꢀSelectꢀTM0ꢀCounterꢀclock
000:ꢀfSYS/4
001:ꢀfSYS
010:ꢀfH/16
011:ꢀfH/64
100:ꢀfSUB
101:ꢀReserved
110:ꢀTCK0ꢀrisingꢀedgeꢀclock
111:ꢀTCK0ꢀfallingꢀedgeꢀclock
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀTM.ꢀSelectingꢀtheꢀReservedꢀ
clockꢀinputꢀwillꢀeffectivelyꢀdisableꢀtheꢀinternalꢀcounter.ꢀTheꢀexternalꢀpinꢀclockꢀsourceꢀ
canꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀfSYSꢀisꢀtheꢀ
systemꢀclock,ꢀwhileꢀfHꢀandꢀfSUBꢀareꢀotherꢀinternalꢀclocks,ꢀtheꢀdetailsꢀofꢀwhichꢀcanꢀbeꢀ
foundꢀinꢀtheꢀoscillatorꢀsection.
Bitꢀ3
TnON:ꢀTMnꢀCounterꢀOn/OffꢀControl
0:ꢀOff
1:ꢀOn
Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀTM.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀtheꢀ
counterꢀtoꢀrun,ꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀTM.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀstopꢀtheꢀ
counterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀTMꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀconsumption.ꢀ
Whenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀwillꢀbeꢀresetꢀtoꢀ
zero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀcounterꢀwillꢀretainꢀ
itsꢀresidualꢀvalue.
IfꢀtheꢀTMꢀisꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀthenꢀtheꢀTMꢀoutputꢀpinꢀwillꢀbeꢀresetꢀ
toꢀitsꢀinitialꢀcondition,ꢀasꢀspecifiedꢀbyꢀtheꢀTnOCꢀbit,ꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀ
lowꢀtoꢀhigh.
Rev. 1.00
101
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Bitꢀ2~0
TnRP2~TnRP0:ꢀTMnꢀCCRPꢀ3-bitꢀregister,ꢀcomparedꢀwithꢀtheꢀTMnꢀCounterꢀbitꢀ9~bitꢀ7
ComparatorꢀPꢀMatchꢀPeriod
000:ꢀ1024ꢀTMnꢀclocks
001:ꢀ128ꢀTMnꢀclocks
010:ꢀ256ꢀTMnꢀclocks
011:ꢀ384ꢀTMnꢀclocks
100:ꢀ512ꢀTMnꢀclocks
101:ꢀ640ꢀTMnꢀclocks
110:ꢀ768ꢀTMnꢀclocks
111:ꢀ896ꢀTMnꢀclocks
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀvalueꢀonꢀtheꢀinternalꢀCCRPꢀ3-bitꢀregister,ꢀwhichꢀ
areꢀthenꢀcomparedꢀwithꢀtheꢀinternalꢀcounter'sꢀhighestꢀthreeꢀbits.ꢀTheꢀresultꢀofꢀthisꢀ
comparisonꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀifꢀtheꢀTnCCLRꢀbitꢀisꢀsetꢀtoꢀ
zero.ꢀSettingꢀtheꢀTnCCLRꢀbitꢀtoꢀzeroꢀensuresꢀthatꢀaꢀcompareꢀmatchꢀwithꢀtheꢀCCRPꢀ
valuesꢀwillꢀresetꢀtheꢀinternalꢀcounter.ꢀAsꢀtheꢀCCRPꢀbitsꢀareꢀonlyꢀcomparedꢀwithꢀtheꢀ
highestꢀthreeꢀcounterꢀbits,ꢀtheꢀcompareꢀvaluesꢀexistꢀinꢀ128ꢀclockꢀcycleꢀmultiples.ꢀ
Clearingꢀallꢀthreeꢀbitsꢀtoꢀzeroꢀisꢀinꢀeffectꢀallowingꢀtheꢀcounterꢀtoꢀoverflowꢀatꢀitsꢀ
maximumꢀvalue.
TMnC1 Register
Bit
Name
R/W
7
Tn�1
R/W
0
6
Tn�0
R/W
0
5
TnIO1
R/W
0
4
TnIO0
R/W
0
3
TnOC
R/W
0
2
TnPOL
R/W
0
1
0
TnDPX TnCCLR
R/W
0
R/W
0
POR
Bitꢀ7~6
TnM1~TnM0:ꢀSelectꢀTMnꢀOperatingꢀMode
00:ꢀCompareꢀMatchꢀOutputꢀMode
01:ꢀUndefined
10:ꢀPWMꢀMode
11:ꢀTimer/CounterꢀMode
TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀTM.ꢀToꢀensureꢀreliableꢀoperationꢀ
theꢀTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀTnM1ꢀandꢀTnM0ꢀ
bits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀTMꢀoutputꢀpinꢀcontrolꢀmustꢀbeꢀdisabled.
Bitꢀ5~4
TnIO1~TnIO0:ꢀSelectꢀTPn,ꢀTPnBꢀoutputꢀfunction
CompareꢀMatchꢀOutputꢀMode
00:ꢀNoꢀchange
01:ꢀOutputꢀlow
10:ꢀOutputꢀhigh
11:ꢀToggleꢀoutput
PWMꢀMode
00:ꢀPWMꢀOutputꢀinactiveꢀstate
01:ꢀPWMꢀOutputꢀactiveꢀstate
10:ꢀPWMꢀoutput
11:ꢀUndefined
Timer/counterꢀMode
Unused
TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ
certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ
modeꢀtheꢀTMꢀisꢀrunning.ꢀ
Rev. 1.00
10ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀ
TMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
TheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ
stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ
zero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀTMꢀoutputꢀ
pinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀTnOCꢀbitꢀinꢀtheꢀTMnC1ꢀregister.ꢀNoteꢀthatꢀtheꢀoutputꢀ
levelꢀrequestedꢀbyꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀvalueꢀ
setupꢀusingꢀtheꢀTnOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀTMꢀoutputꢀpinꢀwhenꢀ
aꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀitꢀcanꢀbeꢀresetꢀtoꢀitsꢀ
initialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.
InꢀtheꢀPWMꢀMode,ꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀ
changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀ
functionꢀisꢀmodifiedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀonlyꢀchangeꢀtheꢀ
valuesꢀofꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMnꢀhasꢀbeenꢀswitchedꢀoff.ꢀ
UnpredictableꢀPWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀareꢀchangedꢀwhenꢀ
theꢀTMꢀisꢀrunning.
Bitꢀ3
TnOC:ꢀTPn,ꢀTPnBꢀOutputꢀcontrolꢀbit
CompareꢀMatchꢀOutputꢀMode
0:ꢀInitialꢀlow
1:ꢀInitialꢀhigh
PWMꢀMode
0:ꢀActiveꢀlow
1:ꢀActiveꢀhigh
ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ
whetherꢀTMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀMode.ꢀ
ItꢀhasꢀnoꢀeffectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀ
ModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀheꢀTMꢀoutputꢀpinꢀbeforeꢀaꢀcompareꢀmatchꢀ
occurs.ꢀInꢀtheꢀPWMꢀModeꢀitꢀdeterminesꢀifꢀtheꢀPWMꢀsignalꢀisꢀactiveꢀhighꢀorꢀactiveꢀ
low.
Bitꢀ2
TnPOL:ꢀTPn,ꢀTPnBꢀOutputꢀpolarityꢀControl
0:ꢀNon-invert
1:ꢀInvert
ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀTPnꢀorꢀTPnBꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀ
theꢀTMꢀoutputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀ
effectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.
Bitꢀ1
Bitꢀ0
TnDPX:ꢀTMnꢀPWMꢀperiod/dutyꢀControl
0:ꢀCCRPꢀ-ꢀperiod;ꢀCCRAꢀ-ꢀduty
1:ꢀCCRPꢀ-ꢀduty;ꢀCCRAꢀ-ꢀperiod
Thisꢀbit,ꢀdeterminesꢀwhichꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀforꢀperiodꢀandꢀ
dutyꢀcontrolꢀofꢀtheꢀPWMꢀwaveform.
TnCCLR:ꢀSelectꢀTMnꢀCounterꢀclearꢀcondition
0:ꢀTMnꢀComparatorꢀPꢀmatch
1:ꢀTMnꢀComparatorꢀAꢀmatch
Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀtheꢀ
CompactꢀTMꢀcontainsꢀtwoꢀcomparators,ꢀComparatorꢀAꢀandꢀComparatorꢀP,ꢀeitherꢀofꢀ
whichꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounter.ꢀWithꢀtheꢀTnCCLRꢀbitꢀsetꢀhigh,ꢀ
theꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
Whenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀ
theꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀoverflow.ꢀAꢀcounterꢀoverflowꢀclearingꢀmethodꢀcanꢀ
onlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀbitsꢀareꢀallꢀclearedꢀtoꢀzero.ꢀTheꢀTnCCLRꢀbitꢀisꢀnotꢀ
usedꢀinꢀtheꢀPWMꢀMode.
Rev. 1.00
10ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Compact Type TM Operating Modes
TheꢀCompactꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀthreeꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀMode,ꢀ
PWMꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀoperatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀTnM1ꢀandꢀTnM0ꢀ
bitsꢀinꢀtheꢀTMnC1ꢀregister.
Compare Match Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregister,ꢀshouldꢀbeꢀsetꢀtoꢀ“00”ꢀrespectively.ꢀ
Inꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀbyꢀthreeꢀmethods.ꢀTheseꢀareꢀ
aꢀcounterꢀoverflow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP.ꢀ
WhenꢀtheꢀTnCCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀcanꢀbeꢀcleared.ꢀOneꢀisꢀwhenꢀaꢀ
compareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀCCRPꢀbitsꢀareꢀallꢀzeroꢀwhichꢀallowsꢀ
theꢀcounterꢀtoꢀoverflow.ꢀHereꢀbothꢀTnAFꢀandꢀTnPFꢀinterruptꢀrequestꢀflagsꢀforꢀtheꢀComparatorꢀAꢀandꢀ
ComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.
IfꢀtheꢀTnCCLRꢀbitꢀinꢀtheꢀTMnC1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ
matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀTnAFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀ
generatedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀwhenꢀ
TnCCLRꢀisꢀhighꢀnoꢀTnPFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀgenerated.ꢀIfꢀtheꢀCCRAꢀbitsꢀareꢀallꢀzero,ꢀtheꢀ
counterꢀwillꢀoverflowꢀwhenꢀitsꢀreachesꢀitsꢀmaximumꢀ10-bit,ꢀ3FFꢀHex,ꢀvalue,ꢀhoweverꢀhereꢀtheꢀTnAFꢀ
interruptꢀrequestꢀflagꢀwillꢀnotꢀbeꢀgenerated.
Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀTMꢀoutputꢀpinꢀwillꢀchangeꢀ
state.ꢀTheꢀTMꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀaꢀTnAFꢀinterruptꢀrequestꢀflagꢀ
isꢀgeneratedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀTnPFꢀinterruptꢀrequestꢀflag,ꢀ
generatedꢀfromꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀeffectꢀonꢀtheꢀTMꢀoutputꢀ
pin.ꢀTheꢀwayꢀinꢀwhichꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀareꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀtheꢀ
TnIO1ꢀandꢀTnIO0ꢀbitsꢀinꢀtheꢀTMnC1ꢀregister.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀtheꢀTnIO1ꢀ
andꢀTnIO0ꢀbitsꢀtoꢀgoꢀhigh,ꢀtoꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀcompareꢀmatchꢀ
occursꢀfromꢀComparatorꢀA.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀTMꢀoutputꢀpin,ꢀwhichꢀisꢀsetupꢀafterꢀtheꢀ
TnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀTnOCꢀbit.ꢀNoteꢀthatꢀifꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀ
bitsꢀareꢀzeroꢀthenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.
Rev. 1.00
104
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ oveꢀflow
Counteꢀ Value
CCRP=0
TnCCLR = 0; Tn� [1:0] = 00
CCRP > 0
Counteꢀ ꢁleaꢀed by CCRP value
0xꢅFF
CCRP > 0
Counteꢀ
Restaꢀt
Resume
CCRP
CCRA
Pause
Stop
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
T� O/P Pin
Output not affeꢁted by TnAF
flag. Remains Higꢂ until ꢀeset
by TnON bit
Output Inveꢀts
wꢂen TnPOL is ꢂigꢂ
Output pin set to
initial Level Low
if TnOC=0
Output Toggle witꢂ
TnAF flag
Output Pin
Reset to Initial value
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion
Note TnIO [1:0] = 10
Aꢁtive Higꢂ Output seleꢁt
Heꢀe TnIO [1:0] = 11
Toggle Output seleꢁt
Compare Match Output Mode – TnCCLR=0
Note:ꢀ1.ꢀWithꢀTnCCLR=0,ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀn=0ꢀorꢀ3
Rev. 1.00
105
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
TnCCLR = 1; Tn� [1:0] = 00
CCRA = 0
CCRA > 0 Counteꢀ ꢁleaꢀed by CCRA value
Counteꢀ oveꢀflow
0xꢅFF
CCRA
CCRP
CCRA=0
Resume
Pause
Stop
Counteꢀ Restaꢀt
Time
TnON
TnPAU
TnPOL
No TnAF flag
geneꢀated on
CCRA oveꢀflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnPF not
geneꢀated
Output does
not ꢁꢂange
T� O/P Pin
Output not affeꢁted by
TnAF flag. Remains Higꢂ
until ꢀeset by TnON bit
Output Inveꢀts
wꢂen TnPOL is ꢂigꢂ
Output Toggle witꢂ
TnAF flag
Output pin set to
initial Level Low
if TnOC=0
Output Pin
Reset to Initial value
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion
Note TnIO [1:0] = 10
Aꢁtive Higꢂ Output seleꢁt
Heꢀe TnIO [1:0] = 11
Toggle Output seleꢁt
Compare Match Output Mode – TnCCLR=1
Note:ꢀ1.ꢀWithꢀTnCCLR=1,ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀTheꢀTnPFꢀflagꢀisꢀnotꢀgeneratedꢀwhenꢀTnCCLR=1
5.ꢀn=0ꢀorꢀ3
Rev. 1.00
106
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Timer/Counter Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ11ꢀrespectively.ꢀ
TheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀ
generatingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/CounterꢀModeꢀtheꢀTMꢀoutputꢀ
pinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀCompareꢀMatchꢀ
OutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀTMꢀoutputꢀpinꢀisꢀnotꢀusedꢀinꢀthisꢀmode,ꢀ
theꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunction.
PWM Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectively.ꢀ
TheꢀPWMꢀfunctionꢀwithinꢀtheꢀTMꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀsuchꢀasꢀmotorꢀ
control,ꢀheatingꢀcontrol,ꢀilluminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀfixedꢀfrequencyꢀbutꢀ
ofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀTMꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀgeneratedꢀwithꢀ
varyingꢀequivalentꢀDCꢀRMSꢀvalues.
AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ
waveformꢀisꢀextremelyꢀflexible.ꢀInꢀtheꢀPWMꢀmode,ꢀtheꢀTnCCLRꢀbitꢀhasꢀnoꢀeffectꢀonꢀtheꢀPWMꢀ
operation.ꢀBothꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀtoꢀgenerateꢀtheꢀPWMꢀwaveform,ꢀoneꢀ
registerꢀisꢀusedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀandꢀthusꢀcontrolꢀtheꢀPWMꢀwaveformꢀfrequency,ꢀwhileꢀ
theꢀotherꢀoneꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdutyꢀcycle.ꢀWhichꢀregisterꢀisꢀusedꢀtoꢀcontrolꢀeitherꢀfrequencyꢀ
orꢀdutyꢀcycleꢀisꢀdeterminedꢀusingꢀtheꢀTnDPXꢀbitꢀinꢀtheꢀTMnC1ꢀregister.ꢀTheꢀPWMꢀwaveformꢀ
frequencyꢀandꢀdutyꢀcycleꢀcanꢀthereforeꢀbeꢀcontrolledꢀbyꢀtheꢀvaluesꢀinꢀtheꢀCCRAꢀandꢀCCRPꢀregisters.
Anꢀinterruptꢀflag,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRAꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀmatchꢀ
occursꢀfromꢀeitherꢀComparatorꢀAꢀorꢀComparatorꢀP.ꢀTheꢀTnOCꢀbitꢀinꢀtheꢀTMnC1ꢀregisterꢀisꢀusedꢀtoꢀ
selectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀwaveformꢀwhileꢀtheꢀtwoꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀareꢀusedꢀtoꢀ
enableꢀtheꢀPWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀTMꢀoutputꢀpinꢀtoꢀaꢀfixedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀTnPOLꢀbitꢀisꢀ
usedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.
CTM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
Peꢀiod
Duty
001b
010b
011b
100b
101b
110b
111b
000b
1ꢃ8
ꢃ56
ꢅ84
51ꢃ
640
768
896
10ꢃ4
CCRA
IfꢀfSYS=16MHz,ꢀTMꢀclockꢀsourceꢀisꢀfSYS/4,ꢀCCRP=100bꢀandꢀCCRA=128,
TheꢀCTMꢀPWMꢀoutputꢀfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,ꢀduty=128/512=25%.
IfꢀtheꢀDutyꢀvalueꢀdefinedꢀbyꢀtheꢀCCRAꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀthenꢀtheꢀ
PWMꢀoutputꢀdutyꢀisꢀ100%.
CTM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
Peꢀiod
Duty
001b
010b
011b
100b
101b
110b
111b
000b
CCRA
1ꢃ8
ꢃ56
ꢅ84
51ꢃ
640
768
896
10ꢃ4
TheꢀPWMꢀoutputꢀperiodꢀisꢀdeterminedꢀbyꢀtheꢀCCRAꢀregisterꢀvalueꢀtogetherꢀwithꢀtheꢀTMꢀclockꢀ
whileꢀtheꢀPWMꢀdutyꢀcycleꢀisꢀdefinedꢀbyꢀtheꢀCCRPꢀregisterꢀvalue.
Rev. 1.00
107
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
TnDPX = 0; Tn� [1:0] = 10
Counteꢀ ꢁleaꢀed
by CCRP
Counteꢀ Reset wꢂen
TnON ꢀetuꢀns ꢂigꢂ
CCRP
CCRA
Counteꢀ Stop if
TnON bit low
Pause
Resume
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
T� O/P Pin
(TnOC=1)
T� O/P Pin
(TnOC=0)
PW� Duty Cyꢁle
set by CCRA
PW� ꢀesumes
opeꢀation
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion
Output Inveꢀts
wꢂen TnPOL = 1
PW� Peꢀiod
set by CCRP
PWM Mode – TnDPX=0
Note: 1.ꢀHereꢀTnDPX=0ꢀ–ꢀCounterꢀclearedꢀbyꢀCCRP
2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀevenꢀwhenꢀTnIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀTheꢀTnCCLRꢀbitꢀhasꢀnoꢀinfluenceꢀonꢀPWMꢀoperation
5.ꢀn=0ꢀorꢀ3
Rev. 1.00
108
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
TnDPX = 1; Tn� [1:0] = 10
Counteꢀ ꢁleaꢀed
by CCRA
Counteꢀ Reset wꢂen
TnON ꢀetuꢀns ꢂigꢂ
CCRA
CCRP
Counteꢀ Stop if
TnON bit low
Pause
Resume
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
T� O/P Pin
(TnOC=1)
T� O/P Pin
(TnOC=0)
PW� Duty Cyꢁle
set by CCRP
PW� ꢀesumes
opeꢀation
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion
Output Inveꢀts
wꢂen TnPOL = 1
PW� Peꢀiod
set by CCRA
PWM Mode – TnDPX=1
Note:ꢀ1.ꢀHereꢀTnDPX=1ꢀ–ꢀCounterꢀclearedꢀbyꢀCCRA
2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀevenꢀwhenꢀTnIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀTheꢀTnCCLRꢀbitꢀhasꢀnoꢀinfluenceꢀonꢀPWMꢀoperation
5.ꢀn=0ꢀorꢀ3
Rev. 1.00
109
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Standard Type TM – STM
TheꢀStandardꢀTypeꢀTMꢀcontainsꢀfiveꢀoperatingꢀmodes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀ
Timer/EventꢀCounter,ꢀCaptureꢀInput,ꢀSingleꢀPulseꢀOutputꢀandꢀPWMꢀOutputꢀmodes.ꢀTheꢀStandardꢀ
TMꢀcanꢀalsoꢀbeꢀcontrolledꢀwithꢀanꢀexternalꢀinputꢀpinꢀandꢀcanꢀdriveꢀoneꢀorꢀtwoꢀexternalꢀoutputꢀpins.
Device
TM Type
TM Name
TM Input Pin
TM Output Pin
TCKꢃꢄ TPꢃI;
TCK4ꢄ TP4I;
TCK5ꢄ TP5I
TPꢃꢄ TPꢃB;
TP4ꢄ TP4B;
TP5ꢄ TP5B
HT66F60A
HT66F70A
16-bit ST�
T�ꢃꢄ T�4ꢄ T�5
C
C
P
R
C
m
o
p
a
a
o
r
t
r
P
M
a
c
t
h
8
b
-
t
C
i
m
o
p
a
a
o
r
t
r
P
T
P
n
F
I
e
n
r
r
p
t
u
t
b
8
b
~
1
5
T
O
n
C
f
S
Y
/
S
4
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
f
S
Y
S
f
/
6
1
T
n
P
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t
u
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p
t
O
t
u
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p
t
P
l
o
r
a
t
i
y
f
/
4
6
0
C
u
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n
e
t
r
C
l
e
a
r
C
m
o
l
p
m
e
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n
a
y
t
r
C
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r
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C
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1
-
6
i
b
t
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p
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C
t
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f
S
B
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n
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B
1
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s
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d
T
C
n
C
R
L
T
P
n
L
O
T
M
n
,
1
T
M
n
0
T
O
n
N
T
K
C
n
1
1
1
b
0
b
~
1
5
T
I
n
1
O
,
T
n
O
I
0
T
P
n
U
A
C
m
o
p
a
a
o
r
t
r
A
M
t
a
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c
1
6
-
i
b
t
T
A
n
F
I
e
n
r
r
p
t
u
t
C
m
o
p
a
a
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r
t
r
A
T
I
n
1
O
,
T
n
O
I
0
T
C
n
2
K
T
~
C
n
0
K
C
C
A
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E
d
g
e
T
n
P
l
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t
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c
e
o
t
r
Standard Type TM Block Diagram (n=2, 4 or 5)
Standard TM Operation
TheꢀsizeꢀofꢀStandardꢀTMꢀisꢀ16-bitꢀwide.ꢀAtꢀtheꢀcoreꢀisꢀaꢀ16-bitꢀcount-upꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀ
aꢀuserꢀselectableꢀinternalꢀorꢀexternalꢀclockꢀsource.ꢀThereꢀareꢀalsoꢀtwoꢀinternalꢀcomparatorsꢀwithꢀtheꢀ
names,ꢀComparatorꢀAꢀandꢀComparatorꢀP.ꢀTheseꢀcomparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀ
withꢀCCRPꢀandꢀCCRAꢀregisters.ꢀTheꢀCCRPꢀcomparatorꢀisꢀ8-bitꢀwideꢀwhoseꢀvalueꢀisꢀcomparedꢀtheꢀ
withꢀhighestꢀ8ꢀbitsꢀinꢀtheꢀcounterꢀwhileꢀtheꢀCCRAꢀisꢀtheꢀsixteenꢀbitsꢀandꢀthereforeꢀcomparesꢀallꢀ
counterꢀbits.
Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ16-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ
clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ
automaticallyꢀbyꢀaꢀcounterꢀoverflowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ
Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀStandardꢀ
TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ
sourcesꢀincludingꢀanꢀinputꢀpinꢀandꢀcanꢀalsoꢀcontrolꢀanꢀoutputꢀpin.ꢀAllꢀoperatingꢀsetupꢀconditionsꢀareꢀ
selectedꢀusingꢀrelevantꢀinternalꢀregisters.
Rev. 1.00
110
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Standard Type TM Register Description
OverallꢀoperationꢀofꢀtheꢀStandardꢀTMꢀisꢀcontrolledꢀusingꢀaꢀseriesꢀofꢀregisters.ꢀAꢀreadꢀonlyꢀregisterꢀ
pairꢀexistsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ16-bitꢀvalue,ꢀwhileꢀaꢀread/writeꢀregisterꢀpairꢀexistsꢀtoꢀstoreꢀ
theꢀinternalꢀ16-bitꢀCCRAꢀvalue.ꢀTheꢀremainingꢀtwoꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀsetupꢀtheꢀ
differentꢀoperatingꢀandꢀcontrolꢀmodesꢀasꢀwellꢀasꢀtheꢀthreeꢀorꢀeightꢀCCRPꢀbits.
Name
T�nC0
T�nC1
T�nDL
T�nDH
T�nAL
T�nAH
T�nRP
Bit 7
TnPAU
Tn�1
D7
Bit 6
TnCKꢃ
Tn�0
D6
Bit 5
TnCK1
TnIO1
D5
Bit 4
TnCK0
TnIO0
D4
Bit 3
TnON
TnOC
Dꢅ
Bit 2
—
Bit 1
Bit 0
—
—
TnPOL
Dꢃ
TnDPX TnCCLR
D1
D9
D1
D9
D1
D0
D8
D0
D8
D0
D15
D7
D14
D6
D1ꢅ
D5
D1ꢃ
D4
D11
Dꢅ
D10
Dꢃ
D15
D7
D14
D6
D1ꢅ
D5
D1ꢃ
D4
D11
Dꢅ
D10
Dꢃ
16-bit Standard TM Register List (n=2, 4 or 5)
TMnC0 Register
Bit
7
6
TnCKꢃ
R/W
0
5
TnCK1
R/W
0
4
TnCK0
R/W
0
3
TnON
R/W
0
2
1
0
Name
R/W
TnPAU
R/W
0
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7
TnPAU:ꢀTMnꢀCounterꢀPauseꢀControl
0:ꢀRun
1:ꢀPause
Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀrestoresꢀ
normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀTMꢀwillꢀremainꢀpoweredꢀupꢀ
andꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀthisꢀbitꢀ
changesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀchangesꢀ
toꢀaꢀlowꢀvalueꢀagain.
Bitꢀ6~4
TnCK2, TnCK1, TnCK0:ꢀSelectꢀTMnꢀCounterꢀclock
000:ꢀfSYS/4
001:ꢀfSYS
010:ꢀfH/16
011:ꢀfH/64
100:ꢀfSUB
101:ꢀReserved
110:ꢀTCKnꢀrisingꢀedgeꢀclock
111:ꢀTCKnꢀfallingꢀedgeꢀclock
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀTM.ꢀSelectingꢀtheꢀReservedꢀ
clockꢀinputꢀwillꢀeffectivelyꢀdisableꢀtheꢀinternalꢀcounter.ꢀTheꢀexternalꢀpinꢀclockꢀsourceꢀ
canꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀfSYSꢀisꢀtheꢀ
systemꢀclock,ꢀwhileꢀfHꢀandꢀfSUBꢀareꢀotherꢀinternalꢀclocks,ꢀtheꢀdetailsꢀofꢀwhichꢀcanꢀbeꢀ
foundꢀinꢀtheꢀoscillatorꢀsection.
Rev. 1.00
111
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Bitꢀ3
TnON:ꢀTMnꢀCounterꢀOn/OffꢀControl
0:ꢀOff
1:ꢀOn
Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀTM.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀtheꢀ
counterꢀtoꢀrun,ꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀTM.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀstopꢀtheꢀ
counterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀTMꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀconsumption.ꢀ
Whenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀwillꢀbeꢀresetꢀtoꢀ
zero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀcounterꢀwillꢀretainꢀ
itsꢀresidualꢀvalueꢀuntilꢀtheꢀbitꢀreturnsꢀhighꢀagain.ꢀIfꢀtheꢀTMꢀisꢀinꢀtheꢀCompareꢀMatchꢀ
OutputꢀModeꢀthenꢀtheꢀTMꢀoutputꢀpinꢀwillꢀbeꢀresetꢀtoꢀitsꢀinitialꢀcondition,ꢀasꢀspecifiedꢀ
byꢀtheꢀTnOCꢀbit,ꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh.
Bitꢀ2~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
TMnC1 Register
Bit
Name
R/W
7
Tn�1
R/W
0
6
Tn�0
R/W
0
5
TnIO1
R/W
0
4
TnIO0
R/W
0
3
TnOC
R/W
0
2
TnPOL
R/W
0
1
0
TnDPX TnCCLR
R/W
0
R/W
0
POR
Bitꢀ7~6
TnM1~TnM0:ꢀSelectꢀTMnꢀOperatingꢀMode
00:ꢀCompareꢀMatchꢀOutputꢀMode
01:ꢀCaptureꢀInputꢀMode
10:ꢀPWMꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode
11:ꢀTimer/CounterꢀMode
TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀTM.ꢀToꢀensureꢀreliableꢀoperationꢀ
theꢀTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀTnM1ꢀandꢀTnM0ꢀ
bits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀTMꢀoutputꢀpinꢀcontrolꢀmustꢀbeꢀdisabled.
Bitꢀ5~4
TnIO1~TnIO0:ꢀSelectꢀTPn,ꢀTPnBꢀoutputꢀfunction
CompareꢀMatchꢀOutputꢀMode
00:ꢀNoꢀchange
01:ꢀOutputꢀlow
10:ꢀOutputꢀhigh
11:ꢀToggleꢀoutput
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
00:ꢀPWMꢀoutputꢀinactiveꢀstate
01:ꢀPWMꢀoutputꢀactiveꢀstate
10:ꢀPWMꢀoutput
11:ꢀSingleꢀpulseꢀoutput
CaptureꢀInputꢀMode
00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀTPnI
01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀTPnIꢀ
10:ꢀInputꢀcaptureꢀatꢀfalling/risingꢀedgeꢀofꢀTPnI
11:ꢀInputꢀcaptureꢀdisabled
Timer/counterꢀMode:
Unused
TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ
certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ
modeꢀtheꢀTMꢀisꢀrunning.
Rev. 1.00
11ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀ
TMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
TheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ
stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ
zero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀTMꢀoutputꢀ
pinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀTnOCꢀbitꢀinꢀtheꢀTMnC1ꢀregister.ꢀNoteꢀthatꢀtheꢀoutputꢀ
levelꢀrequestedꢀbyꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀvalueꢀ
setupꢀusingꢀtheꢀTnOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀTMꢀoutputꢀpinꢀwhenꢀ
aꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstate,ꢀitꢀcanꢀbeꢀresetꢀtoꢀitsꢀ
initialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀTnONꢀbitꢀfromꢀlowꢀtoꢀhigh.
InꢀtheꢀPWMꢀMode,ꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀ
changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀ
functionꢀisꢀmodifiedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀchangeꢀtheꢀvaluesꢀ
ofꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀUnpredictableꢀ
PWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀareꢀchangedꢀwhenꢀtheꢀTMꢀisꢀ
running.
Bitꢀ3ꢀ
TnOC:ꢀTPn,ꢀTPnBꢀOutputꢀcontrolꢀbit
CompareꢀMatchꢀOutputꢀMode
0:ꢀInitialꢀlow
1:ꢀInitialꢀhigh
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
0:ꢀActiveꢀlow
1:ꢀActiveꢀhigh
ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ
whetherꢀTMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀMode/
SingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.ꢀInꢀ
theꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀTMꢀoutputꢀpinꢀ
beforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀModeꢀitꢀdeterminesꢀifꢀtheꢀPWMꢀsignalꢀisꢀ
activeꢀhighꢀorꢀactiveꢀlow.
Bitꢀ2
TnPOL:ꢀTPn,ꢀTPnBꢀOutputꢀpolarityꢀControl
0:ꢀNon-invert
1:ꢀInvert
ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀTPnꢀorꢀTPnBꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀ
theꢀTMꢀoutputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀ
effectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.
Bitꢀ1
Bitꢀ0
TnDPX:ꢀTMnꢀPWMꢀperiod/dutyꢀControl
0:ꢀCCRPꢀ-ꢀperiod;ꢀCCRAꢀ-ꢀduty
1:ꢀCCRPꢀ-ꢀduty;ꢀCCRAꢀ-ꢀperiod
Thisꢀbit,ꢀdeterminesꢀwhichꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀforꢀperiodꢀandꢀ
dutyꢀcontrolꢀofꢀtheꢀPWMꢀwaveform.
TnCCLR:ꢀSelectꢀTMnꢀCounterꢀclearꢀcondition
0:ꢀTMnꢀComparatorꢀPꢀmatch
1:ꢀTMnꢀComparatorꢀAꢀmatch
Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀtheꢀ
StandardꢀTMꢀcontainsꢀtwoꢀcomparators,ꢀComparatorꢀAꢀandꢀComparatorꢀP,ꢀeitherꢀofꢀ
whichꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounter.ꢀWithꢀtheꢀTnCCLRꢀbitꢀsetꢀhigh,ꢀ
theꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
Whenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀ
theꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀoverflow.ꢀAꢀcounterꢀoverflowꢀclearingꢀmethodꢀcanꢀ
onlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀbitsꢀareꢀallꢀclearedꢀtoꢀzero.ꢀTheꢀTnCCLRꢀbitꢀisꢀnotꢀ
usedꢀinꢀtheꢀPWM,ꢀSingleꢀPulseꢀorꢀInputꢀCaptureꢀMode.
Rev. 1.00
11ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
TMnDL Register
Bit
Name
R/W
7
D7
R
6
D6
R
5
D5
R
4
D4
R
3
Dꢅ
R
2
Dꢃ
R
1
D1
R
0
D0
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
TMnDL:ꢀTMnꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCounterꢀbitꢀ7~bitꢀ0
TMnDH Register
Bit
Name
R/W
7
D15
R
6
D14
R
5
D1ꢅ
R
4
D1ꢃ
R
3
D11
R
2
D10
R
1
D9
R
0
D8
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
TMnDH:ꢀTMnꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCounterꢀbitꢀ15~bitꢀ8
TMnAL Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0
TMnAL:ꢀTMnꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCCRAꢀbitꢀ7~bitꢀ0
TMnAH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
D15
R/W
0
D14
R/W
0
D1ꢅ
R/W
0
D1ꢃ
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bitꢀ7~0
TMnAH:ꢀTMnꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀ16-bitꢀCCRAꢀbitꢀ15~bitꢀ8
TMnRP Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0
TMnRP:ꢀTMnꢀCCRPꢀRegisterꢀbitꢀ7~bitꢀ0
TMnꢀCCRPꢀ8-bitꢀregister,ꢀcomparedꢀwithꢀtheꢀTMnꢀCounterꢀbitꢀ15~bitꢀ8.ꢀ
ComparatorꢀPꢀMatchꢀPeriod
0:ꢀ65536ꢀTMnꢀclocks
1~255:ꢀ256×(1~255)ꢀTMnꢀclocks
TheseꢀeightꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀvalueꢀonꢀtheꢀinternalꢀCCRPꢀ8-bitꢀregister,ꢀwhichꢀ
areꢀthenꢀcomparedꢀwithꢀtheꢀinternalꢀcounter’sꢀhighestꢀeightꢀbits.ꢀTheꢀresultꢀofꢀthisꢀ
comparisonꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀifꢀtheꢀTnCCLRꢀbitꢀisꢀsetꢀtoꢀ
zero.ꢀSettingꢀtheꢀTnCCLRꢀbitꢀtoꢀzeroꢀensuresꢀthatꢀaꢀcompareꢀmatchꢀwithꢀtheꢀCCRPꢀ
valuesꢀwillꢀresetꢀtheꢀinternalꢀcounter.ꢀAsꢀtheꢀCCRPꢀbitsꢀareꢀonlyꢀcomparedꢀwithꢀtheꢀ
highestꢀeightꢀcounterꢀbits,ꢀtheꢀcompareꢀvaluesꢀexistꢀinꢀ256ꢀclockꢀcycleꢀmultiples.ꢀ
Clearingꢀallꢀeightꢀbitsꢀtoꢀzeroꢀisꢀinꢀeffectꢀallowingꢀtheꢀcounterꢀtoꢀoverflowꢀatꢀitsꢀ
maximumꢀvalue.
Rev. 1.00
114
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Standard Type TM Operating Modes
TheꢀStandardꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀfiveꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀMode,ꢀ
PWMꢀOutputꢀMode,ꢀSingleꢀPulseꢀOutputꢀMode,ꢀCaptureꢀInputꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀ
operatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀTnM1ꢀandꢀTnM0ꢀbitsꢀinꢀtheꢀTMnC1ꢀregister.
Compare Match Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregister,ꢀshouldꢀbeꢀsetꢀtoꢀ00ꢀrespectively.ꢀ
Inꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀbyꢀthreeꢀmethods.ꢀTheseꢀareꢀ
aꢀcounterꢀoverflow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP.ꢀ
WhenꢀtheꢀTnCCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀcanꢀbeꢀcleared.ꢀOneꢀisꢀwhenꢀ
aꢀcompareꢀmatchꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀCCRPꢀbitsꢀareꢀallꢀzeroꢀwhichꢀallowsꢀ
theꢀcounterꢀtoꢀoverflow.ꢀHereꢀbothꢀTnAFꢀandꢀTnPFꢀinterruptꢀrequestꢀflagsꢀforꢀComparatorꢀAꢀandꢀ
ComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.
IfꢀtheꢀTnCCLRꢀbitꢀinꢀtheꢀTMnC1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ
matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀTnAFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀ
generatedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀwhenꢀ
TnCCLRꢀisꢀhighꢀnoꢀTnPFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀgenerated.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀ
Mode,ꢀtheꢀCCRAꢀcanꢀnotꢀbeꢀsetꢀtoꢀ"0".
Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀTMꢀoutputꢀpin,ꢀwillꢀchangeꢀ
state.ꢀTheꢀTMꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀanꢀTnAFꢀinterruptꢀrequestꢀ
flagꢀisꢀgeneratedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀTnPFꢀinterruptꢀrequestꢀflag,ꢀ
generatedꢀfromꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀeffectꢀonꢀtheꢀTMꢀoutputꢀ
pin.ꢀTheꢀwayꢀinꢀwhichꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀareꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀtheꢀ
TnIO1ꢀandꢀTnIO0ꢀbitsꢀinꢀtheꢀTMnC1ꢀregister.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀtheꢀTnIO1ꢀ
andꢀTnIO0ꢀbitsꢀtoꢀgoꢀhigh,ꢀtoꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀcompareꢀmatchꢀ
occursꢀfromꢀComparatorꢀA.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀTMꢀoutputꢀpin,ꢀwhichꢀisꢀsetupꢀafterꢀtheꢀ
TnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀTnOCꢀbit.ꢀNoteꢀthatꢀifꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀ
bitsꢀareꢀzeroꢀthenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.
Rev. 1.00
115
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ
oveꢀflow
TnCCLR = 0; Tn�[1:0] = 00
Counteꢀ Value
CCRP = 0
CCRP > 0
Counteꢀ ꢁleaꢀed by CCRP value
0xFFFF
CCRP
CCRA
CCRP > 0
Pause Resume
Counteꢀ
Reset
Stop
Time
TnON bit
TnPAU bit
TnPOL bit
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
T� O/P Pin
Output inveꢀts
wꢂen TnPOL is ꢂigꢂ
Output not affeꢁted by
TnAF flag. Remains Higꢂ
until ꢀeset by TnON bit
Output Pin set
to Initial Level
Low if TnOC = 0
Output Toggle
witꢂ TnAF flag
Output Pin
Now TnIO1ꢄ TnIO0 = 10
Aꢁtive Higꢂ Output
Seleꢁt
Reset to initial value
Output ꢁontꢀolled
by otꢂeꢀ pin-sꢂaꢀed funꢁtion
Heꢀe TnIO1ꢄ TnIO0 = 11
Toggle Output Seleꢁt
Compare Match Output Mode – TnCCLR=0
Note:ꢀ1.ꢀWithꢀTnCCLR=0,ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀn=2,ꢀ4ꢀorꢀ5
Rev. 1.00
116
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
TnCCLR = 1; Tn�[1:0] = 00
Counteꢀ Value
CCRA = 0
Counteꢀ oveꢀflows
CCRA > 0 Counteꢀ ꢁleaꢀed by CCRA value
0xFFFF
CCRA
CCRA = 0
Pause Resume
Counteꢀ
Reset
Stop
CCRP
Time
TnON bit
TnPAU bit
TnPOL bit
No TnAF flag
geneꢀated on
CCRA oveꢀflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
Output does
not ꢁꢂange
TnPF not
geneꢀated
T� O/P Pin
Output not affeꢁted by
TnAF flag ꢀemains Higꢂ
until ꢀeset by TnON bit
Output Pin set
to Initial Level
Low if TnOC = 0
Output Toggle
witꢂ TnAF flag
Output inveꢀts
wꢂen TnPOL is ꢂigꢂ
Now TnIO1ꢄ TnIO0 = 10
Aꢁtive Higꢂ Output
Seleꢁt
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion
Output Pin
Reset to initial value
Heꢀe TnIO1ꢄ TnIO0 = 11
Toggle Output Seleꢁt
Compare Match Output Mode – TnCCLR=1
Note: 1.ꢀWithꢀTnCCLR=1,ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀAꢀTnPFꢀflagꢀisꢀnotꢀgeneratedꢀwhenꢀTnCCLR=1
5.ꢀn=2,ꢀ4ꢀorꢀ5
Rev. 1.00
117
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Timer/Counter Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ11ꢀrespectively.ꢀ
TheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀ
generatingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/CounterꢀModeꢀtheꢀTMꢀoutputꢀ
pinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀCompareꢀMatchꢀ
OutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀTMꢀoutputꢀpinꢀisꢀnotꢀusedꢀinꢀthisꢀmode,ꢀ
theꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunction.
PWM Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectivelyꢀ
andꢀalsoꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectively.ꢀTheꢀPWMꢀfunctionꢀwithinꢀ
theꢀTMꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀsuchꢀasꢀmotorꢀcontrol,ꢀheatingꢀcontrol,ꢀ
illuminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀfixedꢀfrequencyꢀbutꢀofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀ
TMꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀgeneratedꢀwithꢀvaryingꢀequivalentꢀDCꢀRMSꢀ
values.
AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ
waveformꢀisꢀextremelyꢀflexible.ꢀInꢀtheꢀPWMꢀmode,ꢀtheꢀTnCCLRꢀbitꢀhasꢀnoꢀeffectꢀasꢀtheꢀPWMꢀ
period.ꢀBothꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀtoꢀgenerateꢀtheꢀPWMꢀwaveform,ꢀoneꢀregisterꢀ
isꢀusedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀandꢀthusꢀcontrolꢀtheꢀPWMꢀwaveformꢀfrequency,ꢀwhileꢀtheꢀotherꢀ
oneꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdutyꢀcycle.ꢀWhichꢀregisterꢀisꢀusedꢀtoꢀcontrolꢀeitherꢀfrequencyꢀorꢀdutyꢀcycleꢀ
isꢀdeterminedꢀusingꢀtheꢀTnDPXꢀbitꢀinꢀtheꢀTMnC1ꢀregister.ꢀTheꢀPWMꢀwaveformꢀfrequencyꢀandꢀdutyꢀ
cycleꢀcanꢀthereforeꢀbeꢀcontrolledꢀbyꢀtheꢀvaluesꢀinꢀtheꢀCCRAꢀandꢀCCRPꢀregisters.
Anꢀinterruptꢀflag,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRAꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀmatchꢀ
occursꢀfromꢀeitherꢀComparatorꢀAꢀorꢀComparatorꢀP.ꢀTheꢀTnOCꢀbitꢀinꢀtheꢀTMnC1ꢀregisterꢀisꢀusedꢀtoꢀ
selectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀwaveformꢀwhileꢀtheꢀtwoꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀareꢀusedꢀtoꢀ
enableꢀtheꢀPWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀTMꢀoutputꢀpinꢀtoꢀaꢀfixedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀTnPOLꢀbitꢀisꢀ
usedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.
16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
Peꢀiod
Duty
1~255
0
CCRP×ꢃ56
655ꢅ6
CCRA
IfꢀfSYS=16MHz,ꢀTMꢀclockꢀsourceꢀselectꢀfSYS/4,ꢀCCRP=2ꢀandꢀCCRA=128,
TheꢀSTMꢀPWMꢀoutputꢀfrequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz,ꢀduty=128/(2×256)=25%.
IfꢀtheꢀDutyꢀvalueꢀdefinedꢀbyꢀtheꢀCCRAꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀthenꢀtheꢀ
PWMꢀoutputꢀdutyꢀisꢀ100%.
16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
Peꢀiod
Duty
1~255
0
CCRA
CCRP×ꢃ56
655ꢅ6
TheꢀPWMꢀoutputꢀperiodꢀisꢀdeterminedꢀbyꢀtheꢀCCRAꢀregisterꢀvalueꢀtogetherꢀwithꢀtheꢀTMꢀclockꢀ
whileꢀtheꢀPWMꢀdutyꢀcycleꢀisꢀdefinedꢀbyꢀtheꢀ(CCRP×256)ꢀexceptꢀwhenꢀtheꢀCCRPꢀvalueꢀisꢀequalꢀtoꢀ0.
Rev. 1.00
118
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
TnDPX = 0; Tn� [1:0] = 10
Counteꢀ ꢁleaꢀed
by CCRP
Counteꢀ Reset wꢂen
TnON ꢀetuꢀns ꢂigꢂ
CCRP
CCRA
Counteꢀ Stop if
TnON bit low
Pause
Resume
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
T� O/P Pin
(TnOC=1)
T� O/P Pin
(TnOC=0)
PW� Duty Cyꢁle
set by CCRA
PW� ꢀesumes
opeꢀation
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion
Output Inveꢀts
wꢂen TnPOL= 1
PW� Peꢀiod
set by CCRP
PWM Mode – TnDPX=0
Note: 1.ꢀHereꢀTnDPX=0,ꢀCounterꢀclearedꢀbyꢀCCRP
2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀTheꢀTnCCLRꢀbitꢀhasꢀnoꢀinfluenceꢀonꢀPWMꢀoperation
5.ꢀn=2,ꢀ4ꢀorꢀ5
Rev. 1.00
119
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
TnDPX = 1; Tn� [1:0] = 10
Counteꢀ ꢁleaꢀed
by CCRA
Counteꢀ Reset wꢂen
TnON ꢀetuꢀns ꢂigꢂ
CCRA
CCRP
Counteꢀ Stop if
TnON bit low
Pause
Resume
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
T� O/P Pin
(TnOC=1)
T� O/P Pin
(TnOC=0)
PW� Duty Cyꢁle
set by CCRP
PW� ꢀesumes
opeꢀation
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion
Output Inveꢀts
wꢂen TnPOL= 1
PW� Peꢀiod
set by CCRA
PWM Mode – TnDPX=1
Note:ꢀ1.ꢀHereꢀTnDPX=1ꢀ--ꢀCounterꢀclearedꢀbyꢀCCRA
2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀTheꢀTnCCLRꢀbitꢀhasꢀnoꢀinfluenceꢀonꢀPWMꢀoperation
5.ꢀn=2,ꢀ4ꢀorꢀ5
Rev. 1.00
1ꢃ0
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Single Pulse Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectivelyꢀ
andꢀalsoꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ11ꢀrespectively.ꢀTheꢀSingleꢀPulseꢀOutputꢀMode,ꢀ
asꢀtheꢀnameꢀsuggests,ꢀwillꢀgenerateꢀaꢀsingleꢀshotꢀpulseꢀonꢀtheꢀTMꢀoutputꢀpin.
TheꢀtriggerꢀforꢀtheꢀpulseꢀoutputꢀleadingꢀedgeꢀisꢀaꢀlowꢀtoꢀhighꢀtransitionꢀofꢀtheꢀTnONꢀbit,ꢀwhichꢀcanꢀ
beꢀimplementedꢀusingꢀtheꢀapplicationꢀprogram.ꢀHoweverꢀinꢀtheꢀSingleꢀPulseꢀMode,ꢀtheꢀTnONꢀbitꢀ
canꢀalsoꢀbeꢀmadeꢀtoꢀautomaticallyꢀchangeꢀfromꢀlowꢀtoꢀhighꢀusingꢀtheꢀexternalꢀTCKnꢀpin,ꢀwhichꢀwillꢀ
inꢀturnꢀinitiateꢀtheꢀSingleꢀPulseꢀoutput.ꢀWhenꢀtheꢀTnONꢀbitꢀtransitionsꢀtoꢀaꢀhighꢀlevel,ꢀtheꢀcounterꢀ
willꢀstartꢀrunningꢀandꢀtheꢀpulseꢀleadingꢀedgeꢀwillꢀbeꢀgenerated.ꢀTheꢀTnONꢀbitꢀshouldꢀremainꢀhighꢀ
whenꢀtheꢀpulseꢀisꢀinꢀitsꢀactiveꢀstate.ꢀTheꢀgeneratedꢀpulseꢀtrailingꢀedgeꢀwillꢀbeꢀgeneratedꢀwhenꢀtheꢀ
TnONꢀbitꢀisꢀclearedꢀtoꢀzero,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogramꢀorꢀwhenꢀaꢀ
compareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.
HoweverꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀautomaticallyꢀclearꢀtheꢀTnONꢀbitꢀandꢀthusꢀ
generateꢀtheꢀSingleꢀPulseꢀoutputꢀtrailingꢀedge.ꢀInꢀthisꢀwayꢀtheꢀCCRAꢀvalueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀ
theꢀpulseꢀwidth.ꢀAꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀgenerateꢀaꢀTMꢀinterrupt.ꢀTheꢀcounterꢀ
canꢀonlyꢀbeꢀresetꢀbackꢀtoꢀzeroꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhenꢀtheꢀcounterꢀ
restarts.ꢀInꢀtheꢀSingleꢀPulseꢀModeꢀCCRPꢀisꢀnotꢀused.ꢀTheꢀTnCCLRꢀandꢀTnDPXꢀbitsꢀareꢀnotꢀusedꢀinꢀ
thisꢀMode.
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Single Pulse Generation
Rev. 1.00
1ꢃ1
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
Tn� [1:0] = 10 ; TnIO [1:0] = 11
Counteꢀ stopped
by CCRA
Counteꢀ Reset wꢂen
TnON ꢀetuꢀns ꢂigꢂ
CCRA
CCRP
Counteꢀ Stops
by softwaꢀe
Resume
Pause
Time
TnON
Auto. set by
TCKn pin
Softwaꢀe Cleaꢀed by
Tꢀiggeꢀ CCRA matꢁꢂ
Softwaꢀe
Tꢀiggeꢀ
Softwaꢀe
Cleaꢀ
Softwaꢀe
Tꢀiggeꢀ
Softwaꢀe
Tꢀiggeꢀ
TCKn pin
TnPAU
TCKn pin
Tꢀiggeꢀ
TnPOL
No CCRP Inteꢀꢀupts
geneꢀated
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
T� O/P Pin
(TnOC=1)
T� O/P Pin
(TnOC=0)
Output Inveꢀts
wꢂen TnPOL = 1
Pulse Widtꢂ
set by CCRA
Single Pulse Mode
Note:ꢀ1.ꢀCounterꢀstoppedꢀbyꢀCCRA
2.ꢀCCRPꢀisꢀnotꢀused
3.ꢀTheꢀpulseꢀtriggeredꢀbyꢀtheꢀTCKnꢀpinꢀorꢀbyꢀsettingꢀtheꢀTnONꢀbitꢀhigh
4.ꢀAꢀTCKnꢀpinꢀactiveꢀedgeꢀwillꢀautomaticallyꢀsetꢀtheꢀTnONꢀbitꢀhigh.
5.ꢀInꢀtheꢀSingleꢀPulseꢀMode,ꢀTnIOꢀ[1:0]ꢀmustꢀbeꢀsetꢀtoꢀ“11”ꢀandꢀcanꢀnotꢀbeꢀchanged.
6.ꢀn=2,ꢀ4ꢀorꢀ5
Rev. 1.00
1ꢃꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Capture Input Mode
ToꢀselectꢀthisꢀmodeꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ01ꢀrespectively.ꢀ
Thisꢀmodeꢀenablesꢀexternalꢀsignalsꢀtoꢀcaptureꢀandꢀstoreꢀtheꢀpresentꢀvalueꢀofꢀtheꢀinternalꢀcounterꢀ
andꢀcanꢀthereforeꢀbeꢀusedꢀforꢀapplicationsꢀsuchꢀasꢀpulseꢀwidthꢀmeasurements.ꢀTheꢀexternalꢀsignalꢀ
isꢀsuppliedꢀonꢀtheꢀTPnIꢀpin,ꢀwhoseꢀactiveꢀedgeꢀcanꢀbeꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀrisingꢀ
andꢀfallingꢀedges;ꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀusingꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀinꢀ
theꢀTMnC1ꢀregister.ꢀTheꢀcounterꢀisꢀstartedꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhichꢀisꢀ
initiatedꢀusingꢀtheꢀapplicationꢀprogram.
WhenꢀtheꢀrequiredꢀedgeꢀtransitionꢀappearsꢀonꢀtheꢀTPnIꢀpinꢀtheꢀpresentꢀvalueꢀinꢀtheꢀcounterꢀwillꢀbeꢀ
latchedꢀintoꢀtheꢀCCRAꢀregistersꢀandꢀaꢀTMꢀinterruptꢀgenerated.ꢀIrrespectiveꢀofꢀwhatꢀeventsꢀoccurꢀ
onꢀtheꢀTPnIꢀpinꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀfreeꢀrunꢀuntilꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow.ꢀ
WhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀtheꢀcounterꢀwillꢀresetꢀbackꢀtoꢀzero;ꢀinꢀthisꢀwayꢀtheꢀCCRPꢀ
valueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀmaximumꢀcounterꢀvalue.ꢀWhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀ
fromꢀComparatorꢀP,ꢀaꢀTMꢀinterruptꢀwillꢀalsoꢀbeꢀgenerated.ꢀCountingꢀtheꢀnumberꢀofꢀoverflowꢀ
interruptꢀsignalsꢀfromꢀtheꢀCCRPꢀcanꢀbeꢀaꢀusefulꢀmethodꢀinꢀmeasuringꢀlongꢀpulseꢀwidths.ꢀTheꢀTnIO1ꢀ
andꢀTnIO0ꢀbitsꢀcanꢀselectꢀtheꢀactiveꢀtriggerꢀedgeꢀonꢀtheꢀTPnIꢀpinꢀtoꢀbeꢀaꢀrisingꢀedge,ꢀfallingꢀedgeꢀorꢀ
bothꢀedgeꢀtypes.ꢀIfꢀtheꢀTnIO1ꢀandꢀTnIO0ꢀbitsꢀareꢀbothꢀsetꢀhigh,ꢀthenꢀnoꢀcaptureꢀoperationꢀwillꢀtakeꢀ
placeꢀirrespectiveꢀofꢀwhatꢀhappensꢀonꢀtheꢀTPnIꢀpin,ꢀhoweverꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀcounterꢀwillꢀ
continueꢀtoꢀrun.
TheꢀTnCCLRꢀandꢀTnDPXꢀbitsꢀareꢀnotꢀusedꢀinꢀthisꢀMode.
Rev. 1.00
1ꢃꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counter Value
TnM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Resume
Pause
XX
Time
TnON
TnPAU
Active
edge
Active
edge
Active edge
TM capture
pin TPnI
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value
XX
YY
XX
YY
TnIO [1:0]
Value
00 – Rising edge
01 – Falling edge 10 – Both edges
11 – Disable Capture
Capture Input Mode
Note:ꢀ1.ꢀTnMꢀ[1:0]=01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀTnIOꢀ[1:0]ꢀbits
2.ꢀAꢀTMꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀtheꢀcounterꢀvalueꢀtoꢀCCRA
3.ꢀTnCCLRꢀbitꢀnotꢀused
4.ꢀNoꢀoutputꢀfunctionꢀ–ꢀTnOCꢀandꢀTnPOLꢀbitsꢀareꢀnotꢀused
5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀzero.
6.ꢀn=2,ꢀ4ꢀorꢀ5
Rev. 1.00
1ꢃ4
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Enhanced Type TM – ETM
TheꢀEnhancedꢀTypeꢀTMꢀcontainsꢀfiveꢀoperatingꢀmodes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀ
Timer/EventꢀCounter,ꢀCaptureꢀInput,ꢀSingleꢀPulseꢀOutputꢀandꢀPWMꢀOutputꢀmodes.ꢀTheꢀEnhancedꢀ
TMꢀcanꢀalsoꢀbeꢀcontrolledꢀwithꢀanꢀexternalꢀinputꢀpinꢀandꢀcanꢀdriveꢀthreeꢀorꢀfourꢀexternalꢀoutputꢀpins.
Device
TM Type
TM Name.
TM Input Pin
TM Output Pin
HT66F60A
HT66F70A
10-bit ET�
T�1
TCK1; TP1IAꢄ TP1IB
TP1A; TP1Bꢄ TP1BB
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1
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1
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1
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0
1
0
f
S
Y
S
f
/
6
1
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T
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P
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1
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1
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T
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M
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0
T
A
n
O
P
L
T
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n
N
T
C
n
C
R
L
T
K
C
n
1
1
1
T
A
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,
1
T
A
n
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0
b
0
b
~
9
T
P
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A
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T
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C
n
0
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0
C
C
A
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T
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T
B
n
M
1
,
T
n
M
B
0
T
B
n
O
P
L
C
C
B
R
T
B
n
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1
T
B
n
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0
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T
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P
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T
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1
O
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T
n
O
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0
Enhanced Type TM Block Diagram (n=1)
Enhanced TM Operation
Atꢀitsꢀcoreꢀisꢀaꢀ10-bitꢀcount-up/count-downꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀaꢀuserꢀselectableꢀinternalꢀ
orꢀexternalꢀclockꢀsource.ꢀThereꢀareꢀthreeꢀinternalꢀcomparatorsꢀwithꢀtheꢀnames,ꢀComparatorꢀA,ꢀ
ComparatorꢀBꢀandꢀComparatorꢀP.ꢀTheseꢀcomparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀwithꢀtheꢀ
CCRA,ꢀCCRBꢀandꢀCCRPꢀregisters.ꢀTheꢀCCRPꢀcomparatorꢀisꢀ3-bitsꢀwideꢀwhoseꢀvalueꢀisꢀcomparedꢀ
withꢀtheꢀhighestꢀ3-bitsꢀinꢀtheꢀcounterꢀwhileꢀCCRAꢀandꢀCCRBꢀareꢀ10-bitsꢀwideꢀandꢀthereforeꢀ
comparedꢀwithꢀallꢀcounterꢀbits.
Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ10-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ
clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀT1ONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ
automaticallyꢀbyꢀaꢀcounterꢀoverflowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ
Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀEnhancedꢀ
TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ
sourcesꢀincludingꢀanꢀinputꢀpinꢀandꢀcanꢀalsoꢀcontrolꢀoutputꢀpins.ꢀAllꢀoperatingꢀsetupꢀconditionsꢀareꢀ
selectedꢀusingꢀrelevantꢀinternalꢀregisters.
Rev. 1.00
1ꢃ5
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Enhanced Type TM Register Description
OverallꢀoperationꢀofꢀtheꢀEnhancedꢀTMꢀisꢀcontrolledꢀusingꢀaꢀseriesꢀofꢀregisters.ꢀAꢀreadꢀonlyꢀregisterꢀ
pairꢀexistsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ10-bitꢀvalue,ꢀwhileꢀtwoꢀread/writeꢀregisterꢀpairsꢀexistꢀtoꢀstoreꢀ
theꢀinternalꢀ10-bitꢀCCRAꢀandꢀCCRBꢀvalue.ꢀTheꢀremainingꢀthreeꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀ
setupꢀtheꢀdifferentꢀoperatingꢀandꢀcontrolꢀmodesꢀasꢀwellꢀasꢀtheꢀthreeꢀCCRPꢀbits.
Name
T�1C0
T�1C1
T�1Cꢃ
T�1DL
T�1DH
T�1AL
T�1AH
T�1BL
T�1BH
Bit 7
T1PAU
T1A�1
T1B�1
D7
Bit 6
TnCKꢃ
T1A�0
T1B�0
D6
Bit 5
TnCK1
T1AIO1
T1BIO1
D5
Bit 4
TnCK0
T1AIO0
T1BIO0
D4
Bit 3
Bit 2
Bit 1
Bit 0
TnON
T1RPꢃ
T1RP1
T1RP0
T1AOC T1APOL T1CDN T1CCLR
T1BOC T1BPOL T1PW�1 T1PW�0
Dꢅ
—
Dꢃ
D10
Dꢃ
—
D1
D9
D1
D9
D1
D9
D0
D8
D0
D8
D0
D8
—
—
—
—
D7
D6
D5
D4
Dꢅ
—
—
—
—
—
D7
D6
D5
D4
Dꢅ
—
Dꢃ
—
—
—
—
—
10-bit Enhanced TM Register List
TM1C0 Register
Bit
7
6
T1CKꢃ
R/W
0
5
T1CK1
R/W
0
4
T1CK0
R/W
0
3
T1ON
R/W
0
2
T1RPꢃ
R/W
0
1
T1RP1
R/W
0
0
T1RP0
R/W
0
Name
R/W
T1PAU
R/W
0
POR
Bitꢀ7
T1PAU:ꢀTM1ꢀCounterꢀPauseꢀControl
0:ꢀRun
1:ꢀPause
Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀrestoresꢀ
normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀTMꢀwillꢀremainꢀpoweredꢀupꢀ
andꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀthisꢀbitꢀ
changesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀchangesꢀ
toꢀaꢀlowꢀvalueꢀagain.
Bitꢀ6~4ꢀ
T1CK2~T1CK0:ꢀSelectꢀTM1ꢀCounterꢀclock
000:ꢀfSYS/4
001:ꢀfSYS
010:ꢀfH/16
011:ꢀfH/64
100:ꢀfSUB
101:ꢀReserved
110:ꢀTCK1ꢀrisingꢀedgeꢀclock
111:ꢀTCK1ꢀfallingꢀedgeꢀclock
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀTM.ꢀSelectingꢀtheꢀReservedꢀ
clockꢀinputꢀwillꢀeffectivelyꢀdisableꢀtheꢀinternalꢀcounter.ꢀTheꢀexternalꢀpinꢀclockꢀsourceꢀ
canꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀfSYSꢀisꢀtheꢀ
systemꢀclock,ꢀwhileꢀfHꢀandꢀfSUBꢀareꢀotherꢀinternalꢀclocks,ꢀtheꢀdetailsꢀofꢀwhichꢀcanꢀbeꢀ
foundꢀinꢀtheꢀoscillatorꢀsection.
Rev. 1.00
1ꢃ6
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Bitꢀ3
T1ON:ꢀTM1ꢀCounterꢀOn/OffꢀControl
0:ꢀOff
1:ꢀOn
Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀTM.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀ
theꢀcounterꢀtoꢀrunꢀandꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀTM.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀ
stopꢀtheꢀcounterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀTMꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀ
consumption.ꢀWhenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀ
willꢀbeꢀresetꢀtoꢀzero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀ
counterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀuntilꢀtheꢀbitꢀreturnsꢀhighꢀagain.
IfꢀtheꢀTMꢀisꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀthenꢀtheꢀTMꢀoutputꢀpinꢀwillꢀbeꢀresetꢀ
toꢀitsꢀinitialꢀcondition,ꢀasꢀspecifiedꢀbyꢀtheꢀT1OCꢀbit,ꢀwhenꢀtheꢀT1ONꢀbitꢀchangesꢀfromꢀ
lowꢀtoꢀhigh.
Bitꢀ2~0
T1RP2~T1RP0:ꢀTM1ꢀCCRPꢀ3-bitꢀregister,ꢀcomparedꢀwithꢀtheꢀTM1ꢀCounterꢀ
bitꢀ9~bitꢀ7ꢀComparatorꢀPꢀMatchꢀPeriod
000:ꢀ1024ꢀTM1clocks
001:ꢀ128ꢀTM1ꢀclocks
010:ꢀ256ꢀTM1ꢀclocks
011:ꢀ384ꢀTM1ꢀclocks
100:ꢀ512ꢀTM1ꢀclocks
101:ꢀ640ꢀTM1ꢀclocks
110:ꢀ768ꢀTM1ꢀclocks
111:ꢀ896ꢀTM1ꢀclocks
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀvalueꢀonꢀtheꢀinternalꢀCCRPꢀ3-bitꢀregister,ꢀwhichꢀ
areꢀthenꢀcomparedꢀwithꢀtheꢀinternalꢀcounter’sꢀhighestꢀthreeꢀbits.ꢀTheꢀresultꢀofꢀthisꢀ
comparisonꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀifꢀtheꢀT1CCLRꢀbitꢀisꢀsetꢀtoꢀ
zero.ꢀSettingꢀtheꢀT1CCLRꢀbitꢀtoꢀzeroꢀensuresꢀthatꢀaꢀcompareꢀmatchꢀwithꢀtheꢀCCRPꢀ
valuesꢀwillꢀresetꢀtheꢀinternalꢀcounter.ꢀAsꢀtheꢀCCRPꢀbitsꢀareꢀonlyꢀcomparedꢀwithꢀtheꢀ
highestꢀthreeꢀcounterꢀbits,ꢀtheꢀcompareꢀvaluesꢀexistꢀinꢀ128ꢀclockꢀcycleꢀmultiples.ꢀ
Clearingꢀallꢀthreeꢀbitsꢀtoꢀzeroꢀisꢀinꢀeffectꢀallowingꢀtheꢀcounterꢀtoꢀoverflowꢀatꢀitsꢀ
maximumꢀvalue.
Rev. 1.00
1ꢃ7
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
TM1C1 Register
Bit
7
6
T1A�0
R/W
0
5
T1AIO1
R/W
0
4
T1AIO0
R/W
0
3
2
1
0
Name
R/W
T1A�1
R/W
0
T1AOC T1APOL T1CDN T1CCLR
R/W
0
R/W
0
R
0
R/W
0
POR
Bitꢀ7~6
T1AM1~T1AM0:ꢀSelectꢀTM1ꢀCCRAꢀOperatingꢀMode
00:ꢀCompareꢀMatchꢀOutputꢀMode
01:ꢀCaptureꢀInputꢀMode
10:ꢀPWMꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode
11:ꢀTimer/CounterꢀMode
TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀTM.ꢀToꢀensureꢀreliableꢀoperationꢀ
theꢀTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀT1AM1ꢀandꢀ
T1AM0ꢀbits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀTMꢀoutputꢀpinꢀcontrolꢀmustꢀbeꢀdisabled.
Bitꢀ5~4
T1AIO1~T1AIO0:ꢀSelectꢀTP1Aꢀoutputꢀfunctionꢀ
CompareꢀMatchꢀOutputꢀMode
00:ꢀNoꢀchange
01:ꢀOutputꢀlow
10:ꢀOutputꢀhigh
11:ꢀToggleꢀoutput
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
00:ꢀPWMꢀOutputꢀinactiveꢀstate
01:ꢀPWMꢀOutputꢀactiveꢀstate
10:ꢀPWMꢀoutput
11:ꢀSingleꢀpulseꢀoutput
CaptureꢀInputꢀMode
00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀTP1IA
01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀTP1IA
10:ꢀInputꢀcaptureꢀatꢀfalling/risingꢀedgeꢀofꢀTP1IA
11:ꢀInputꢀcaptureꢀdisabled
Timer/counterꢀMode
Unused
TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ
certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ
modeꢀtheꢀTMꢀisꢀrunning.
InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀT1AIO1ꢀandꢀT1AIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀ
TMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ
TheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ
stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ
zero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀTMꢀoutputꢀ
pinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀT1AOCꢀbitꢀinꢀtheꢀTM1C1ꢀregister.ꢀNoteꢀthatꢀtheꢀoutputꢀ
levelꢀrequestedꢀbyꢀtheꢀT1AIO1ꢀandꢀT1AIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀ
valueꢀsetupꢀusingꢀtheꢀT1AOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀTMꢀoutputꢀpinꢀ
whenꢀaꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀitꢀcanꢀbeꢀresetꢀtoꢀ
itsꢀinitialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀT1ONꢀbitꢀfromꢀlowꢀtoꢀhigh.
InꢀtheꢀPWMꢀMode,ꢀtheꢀT1AIO1ꢀandꢀT1AIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀ
changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀfunctionꢀ
isꢀmodifiedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀchangeꢀtheꢀvaluesꢀofꢀtheꢀ
T1AIO1ꢀandꢀT1AIO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀUnpredictableꢀPWMꢀ
outputsꢀwillꢀoccurꢀifꢀtheꢀT1AIO1ꢀandꢀT1AIO0ꢀbitsꢀareꢀchangedꢀwhenꢀtheꢀTMꢀisꢀrunning.
Rev. 1.00
1ꢃ8
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Bitꢀ3
T1AOC:ꢀTP1AꢀOutputꢀcontrolꢀbit
CompareꢀMatchꢀOutputꢀMode
0:ꢀInitialꢀlow
1:ꢀInitialꢀhigh
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
0:ꢀActiveꢀlow
1:ꢀActiveꢀhigh
ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ
whetherꢀTMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀ
Mode/SingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/Counterꢀ
Mode.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀTMꢀ
outputꢀpinꢀbeforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀModeꢀitꢀdeterminesꢀifꢀtheꢀ
PWMꢀsignalꢀisꢀactiveꢀhighꢀorꢀactiveꢀlow.
Bitꢀ2
T1APOL:ꢀTP1AꢀOutputꢀpolarityꢀControl
0:ꢀNon-invert
1:ꢀInvert
ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀTP1Aꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀTMꢀ
outputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀ
TMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.
Bitꢀ1
Bitꢀ0
T1CDN:ꢀTM1ꢀCountꢀupꢀorꢀdownꢀflag
0:ꢀCountꢀup
1:ꢀCountꢀdown
T1CCLR:ꢀSelectꢀTM1ꢀCounterꢀclearꢀcondition
0:ꢀTM1ꢀComparatrorꢀPꢀmatch
1:ꢀTM1ꢀComparatrorꢀAꢀmatch
Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀ
theꢀEnhancedꢀTMꢀcontainsꢀthreeꢀcomparators,ꢀComparatorꢀA,ꢀComparatorꢀBꢀandꢀ
ComparatorꢀP,ꢀbutꢀonlyꢀComparatorꢀAꢀorꢀComparatorꢀPꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀ
internalꢀcounter.ꢀWithꢀtheꢀT1CCLRꢀbitꢀsetꢀhigh,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀ
compareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀ
beꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀ
overflow.ꢀAꢀcounterꢀoverflowꢀclearingꢀmethodꢀcanꢀonlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀ
bitsꢀareꢀallꢀclearedꢀtoꢀzero.ꢀTheꢀT1CCLRꢀbitꢀisꢀnotꢀusedꢀinꢀtheꢀPWM,ꢀSingleꢀPulseꢀorꢀ
InputꢀCaptureꢀMode.
Rev. 1.00
1ꢃ9
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
TM1C2 Register
Bit
7
6
T1B�0
R/W
0
5
T1BIO1
R/W
0
4
T1BIO0
R/W
0
3
2
1
0
Name
R/W
T1B�1
R/W
0
T1BOC T1BPOL T1PW�1 T1PW�0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6
T1BM1~T1BM0:ꢀSelectꢀTM1ꢀCCRBꢀOperatingꢀMode
00:ꢀCompareꢀMatchꢀOutputꢀMode
01:ꢀCaptureꢀInputꢀMode
10:ꢀPWMꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode
11:ꢀTimer/CounterꢀMode
TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀTM.ꢀToꢀensureꢀreliableꢀoperationꢀ
theꢀTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀT1BM1ꢀandꢀ
T1BM0ꢀbits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀTMꢀoutputꢀpinꢀcontrolꢀmustꢀbeꢀdisabled.
Bitꢀ5~4
T1BIO1~T1BIO0:ꢀSelectꢀTP1B,ꢀTP1BBꢀoutputꢀfunctionꢀ
CompareꢀMatchꢀOutputꢀMode
00:ꢀNoꢀchange
01:ꢀOutputꢀlow
10:ꢀOutputꢀhigh
11:ꢀToggleꢀoutput
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
00:ꢀPWMꢀOutputꢀinactiveꢀstate
01:ꢀPWMꢀOutputꢀactiveꢀstate
10:ꢀPWMꢀoutput
11:ꢀSingleꢀpulseꢀoutput
CaptureꢀInputꢀMode
00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀTP1IB
01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀTP1IB
10:ꢀInputꢀcaptureꢀatꢀfalling/risingꢀedgeꢀofꢀTP1IB
11:ꢀinputꢀcaptureꢀdisabled
Timer/counterꢀMode
Unused
TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ
certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ
modeꢀtheꢀTMꢀisꢀrunning.ꢀ
InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀT1BIO1ꢀandꢀT1BIO0ꢀbitsꢀdetermineꢀhowꢀ
theꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀ
B.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ
stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀB.ꢀWhenꢀtheꢀbitsꢀareꢀbothꢀ
zero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀTMꢀoutputꢀ
pinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀT1BOCꢀbitꢀinꢀtheꢀTM1C2ꢀregister.ꢀNoteꢀthatꢀtheꢀoutputꢀ
levelꢀrequestedꢀbyꢀtheꢀT1BIO1ꢀandꢀT1BIO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀ
valueꢀsetupꢀusingꢀtheꢀT1BOCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀTMꢀoutputꢀpinꢀ
whenꢀaꢀcompareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀitꢀcanꢀbeꢀresetꢀtoꢀ
itsꢀinitialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀT1ONꢀbitꢀfromꢀlowꢀtoꢀhigh.
InꢀtheꢀPWMꢀMode,ꢀtheꢀT1BIO1ꢀandꢀT1BIO0ꢀbitsꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀ
changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀ
functionꢀisꢀmodifiedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀchangeꢀtheꢀvaluesꢀofꢀ
theꢀT1BIO1ꢀandꢀT1BIO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀUnpredictableꢀ
PWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀT1BIO1ꢀandꢀT1BIO0ꢀbitsꢀareꢀchangedꢀwhenꢀtheꢀTMꢀisꢀ
running.
Rev. 1.00
1ꢅ0
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Bitꢀ3
T1BOC:ꢀTP1B,ꢀTP1BBꢀOutputꢀcontrolꢀbit
CompareꢀMatchꢀOutputꢀMode
0:ꢀInitialꢀlow
1:ꢀInitialꢀhigh
PWMꢀMode/SingleꢀPulseꢀOutputꢀMode
0:ꢀActiveꢀlow
1:ꢀActiveꢀhigh
ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ
whetherꢀTMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀ
Mode/SingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/Counterꢀ
Mode.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀTMꢀ
outputꢀpinꢀbeforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀModeꢀitꢀdeterminesꢀifꢀtheꢀ
PWMꢀsignalꢀisꢀactiveꢀhighꢀorꢀactiveꢀlow.
Bitꢀ2
T1BPOL:ꢀTP1B,ꢀTP1BBꢀOutputꢀpolarityꢀControl
0:ꢀNon-invert
1:ꢀInvert
ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀTP1B,ꢀTP1BBꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀ
theꢀTMꢀoutputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀ
effectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.
Bitꢀ1~0
T1PWM1~T1PWM0:ꢀSelectꢀPWMꢀMode
00:ꢀEdgeꢀaligned
01:ꢀCentreꢀaligned,ꢀcompareꢀmatchꢀonꢀcountꢀup
10:ꢀCentreꢀaligned,ꢀcompareꢀmatchꢀonꢀcountꢀdown
11:ꢀCentreꢀaligned,ꢀcompareꢀmatchꢀonꢀcountꢀupꢀorꢀdown
TM1DL Register
Bit
Name
R/W
7
D7
R
6
D6
R
5
D5
R
4
D4
R
3
Dꢅ
R
2
Dꢃ
R
1
D1
R
0
D0
R
POR
0
0
0
0
0
0
0
0
Bitꢀ7~0
TM1DL:ꢀTM1ꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TM1ꢀ10-bitꢀCounterꢀbitꢀ7~bitꢀ0
TM1DH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R
0
D8
R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
0
0
Bitꢀ7~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ"0"
TM1DH:ꢀTM1ꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ1~bitꢀ0
TM1ꢀ10-bitꢀCounterꢀbitꢀ9~bitꢀ8
TM1AL Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0
TM1AL:ꢀTM1ꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TM1ꢀ10-bitꢀCCRAꢀbitꢀ7~bitꢀ0
Rev. 1.00
1ꢅ1
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
TM1AH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ"0"
TM1AH:ꢀTM1ꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ1~bitꢀ0
TM1ꢀ10-bitꢀCCRAꢀbitꢀ9~bitꢀ8
TM1BL Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
Dꢅ
R/W
0
2
Dꢃ
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bitꢀ7~0
TM1BL:ꢀTM1ꢀCCRBꢀLowꢀByteꢀRegisterꢀbitꢀ7~bitꢀ0
TM1ꢀ10-bitꢀCCRBꢀbitꢀ7~bitꢀ0
TM1BH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~2ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ"0"
TM1BH:ꢀTM1ꢀCCRBꢀHighꢀByteꢀRegisterꢀbitꢀ1~bitꢀ0
TM1ꢀ10-bitꢀCCRBꢀbitꢀ9~bitꢀ8
Enhanced Type TM Operating Modes
TheꢀEnhancedꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀfiveꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀMode,ꢀ
PWMꢀOutputꢀMode,ꢀSingleꢀPulseꢀOutputꢀMode,ꢀCaptureꢀInputꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀ
operatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀTnAM1ꢀandꢀTnAM0ꢀbitsꢀinꢀtheꢀTMnC1,ꢀandꢀtheꢀTnBM1ꢀandꢀ
TnBM0ꢀbitsꢀinꢀtheꢀTMnC2ꢀregister.
CCRA
Compare
Match
CCRB Single
Pulse Output
Mode
CCRA Timer/ CCRB PWM
Counter Mode Output Mode
CCRB Input
Capture Mode
ETM Operation Mode
Output Mode
CCRB Compaꢀe �atꢁꢂ Output �ode
CCRB Timeꢀ/Counteꢀ �ode
CCRB PW� Output �ode
√
—
√
—
—
√
—
—
—
√
—
—
—
—
√
—
—
—
—
—
—
—
CCRB Single Pulse Output �ode
CCRB Input Captuꢀe �ode
—
—
—
“√”: permitted; “—”: not permitted
Rev. 1.00
1ꢅꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Compare Output Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnAM1,ꢀTnAM0ꢀandꢀTnBM1,ꢀTnBM0ꢀinꢀtheꢀTMnC1/TMnC2ꢀregistersꢀ
shouldꢀbeꢀallꢀclearedꢀtoꢀzero.ꢀInꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀ
byꢀthreeꢀmethods.ꢀTheseꢀareꢀaꢀcounterꢀoverflow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀ
matchꢀfromꢀComparatorꢀP.ꢀWhenꢀtheꢀTnCCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀ
canꢀbeꢀcleared.ꢀOneꢀisꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀ
CCRPꢀbitsꢀareꢀallꢀzeroꢀwhichꢀallowsꢀtheꢀcounterꢀtoꢀoverflow.ꢀHereꢀbothꢀtheꢀTnAFꢀandꢀTnPFꢀinterruptꢀ
requestꢀflagsꢀforꢀComparatorꢀAꢀandꢀComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.
IfꢀtheꢀTnCCLRꢀbitꢀinꢀtheꢀTMnC1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ
matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀTnAFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀ
generatedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀwhenꢀ
TnCCLRꢀisꢀhighꢀnoꢀTnPFꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀgenerated.
Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀTMꢀoutputꢀpin,ꢀwillꢀchangeꢀ
state.ꢀTheꢀTMꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀaꢀTnAFꢀorꢀTnBFꢀinterruptꢀ
requestꢀflagꢀisꢀgeneratedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀAꢀorꢀComparatorꢀB.ꢀTheꢀ
TnPFꢀinterruptꢀrequestꢀflag,ꢀgeneratedꢀfromꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀ
effectꢀonꢀtheꢀTMꢀoutputꢀpin.ꢀTheꢀwayꢀinꢀwhichꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀisꢀdeterminedꢀbyꢀtheꢀ
conditionꢀofꢀtheꢀTnAIO1ꢀandꢀTnAIO0ꢀbitsꢀinꢀtheꢀTMnC1ꢀregisterꢀforꢀETMꢀCCRA,ꢀandꢀtheꢀTnBIO1ꢀ
andꢀTnBIO0ꢀbitsꢀinꢀtheꢀTMnC2ꢀregisterꢀforꢀETMꢀCCRB.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀ
theꢀTnAIO1,ꢀTnAIO0ꢀbitsꢀ(forꢀtheꢀTPnAꢀpin)ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀ(forꢀtheꢀTP1B,ꢀTP1BBꢀ
pins)ꢀtoꢀgoꢀhigh,ꢀtoꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀ
fromꢀComparatorꢀAꢀorꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀB.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀTMꢀ
outputꢀpin,ꢀwhichꢀisꢀsetupꢀafterꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀTnAOCꢀorꢀ
TnBOCꢀbitꢀforꢀTPnAꢀorꢀTP1B,ꢀTP1BBꢀoutputꢀpins.ꢀNoteꢀthatꢀifꢀtheꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀ
TnBIO0ꢀbitsꢀareꢀzeroꢀthenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.
Rev. 1.00
1ꢅꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ oveꢀflow
Counteꢀ Value
CCRP=0
TnCCLR = 0; TnA� [1:0] = 00
CCRP > 0
Counteꢀ ꢁleaꢀed by CCRP value
0xꢅFF
CCRP > 0
Counteꢀ
Restaꢀt
Resume
CCRP
CCRA
Pause
Stop
Time
TnON
TnPAU
TnAPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TPnA O/P
Pin
Output not affeꢁted by TnAF
flag. Remains Higꢂ until ꢀeset
by TnON bit
Output Inveꢀts
wꢂen TnAPOL is ꢂigꢂ
Output pin set to
initial Level Low
if TnAOC=0
Output Toggle witꢂ
TnAF flag
Output Pin
Reset to Initial value
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion
Note TnAIO [1:0] = 10
Aꢁtive Higꢂ Output seleꢁt
Heꢀe TnAIO [1:0] = 11
Toggle Output seleꢁt
ETM CCRA Compare Match Output Mode – TnCCLR=0
Note: 1.ꢀWithꢀTnCCLR=0,ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTPnAꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀn=1
Rev. 1.00
1ꢅ4
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ oveꢀflow
Counteꢀ Value
CCRP=0
TnCCLR = 0; TnB� [1:0] = 00
CCRP > 0
Counteꢀ ꢁleaꢀed by CCRP value
0xꢅFF
CCRP > 0
Counteꢀ
Restaꢀt
Resume
CCRP
CCRB
Pause
Stop
Time
TnON
TnPAU
TnBPOL
CCRP Int.
Flag TnPF
CCRB Int.
Flag TnBF
TPnB O/P
Pin
Output not affeꢁted by TnBF
flag. Remains Higꢂ until ꢀeset
by TnON bit
Output Inveꢀts
wꢂen TnBPOL is ꢂigꢂ
Output pin set to
initial Level Low
if TnBOC=0
Output Toggle witꢂ
TnBF flag
Output Pin
Reset to Initial value
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion
Note TnBIO [1:0] = 10
Aꢁtive Higꢂ Output seleꢁt
Heꢀe TnBIO [1:0] = 11
Toggle Output seleꢁt
ETM CCRB Compare Match Output Mode – TnCCLR=0
Note:ꢀ1.ꢀWithꢀTnCCLR=0,ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTPnBꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnBFꢀflag
3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀn=1
Rev. 1.00
1ꢅ5
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
TnCCLR = 1; TnA� [1:0] = 00
CCRA = 0
CCRA > 0 Counteꢀ ꢁleaꢀed by CCRA value
Counteꢀ oveꢀflow
0xꢅFF
CCRA
CCRP
CCRA=0
Resume
Pause
Stop
Counteꢀ Restaꢀt
Time
TnON
TnPAU
TnAPOL
No TnAF flag
geneꢀated on
CCRA oveꢀflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnPF not
geneꢀated
Output does
not ꢁꢂange
TPnA O/P
Pin
Output not affeꢁted by
TnAF flag. Remains Higꢂ
until ꢀeset by TnON bit
Output Inveꢀts
wꢂen TnAPOL is ꢂigꢂ
Output pin set to
initial Level Low
if TnAOC=0
Output Toggle witꢂ
TnAF flag
Output Pin
Reset to Initial value
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion
Note TnAIO [1:0] = 10
Aꢁtive Higꢂ Output seleꢁt
Heꢀe TnAIO [1:0] = 11
Toggle Output seleꢁt
ETM CCRA Compare Match Output Mode – TnCCLR=1
Note:ꢀ1.ꢀWithꢀTnCCLR=1,ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTPnAꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnAFꢀflag
3.ꢀTheꢀTPnAꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀTheꢀTnPFꢀflagꢀisꢀnotꢀgeneratedꢀwhenꢀTnCCLR=1
5.ꢀn=1
Rev. 1.00
1ꢅ6
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
TnCCLR = 1; TnB� [1:0] = 00
CCRA = 0
Counteꢀ oveꢀflow
CCRA > 0 Counteꢀ ꢁleaꢀed by CCRA value
0xꢅFF
CCRA
CCRB
CCRA=0
Resume
Pause
Stop
Counteꢀ Restaꢀt
Time
TnON
TnPAU
TnBPOL
No TnAF flag
geneꢀated on
CCRA oveꢀflow
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
TPnB O/P
Pin
Output not affeꢁted by
TnBF flag. Remains Higꢂ
until ꢀeset by TnON bit
Output Toggle witꢂ
TnBF flag
Output Inveꢀts
wꢂen TnBPOL is ꢂigꢂ
Output pin set to
initial Level Low
if TnBOC=0
Output Pin
Reset to Initial value
Note TnBIO [1:0] = 10
Aꢁtive Higꢂ Output seleꢁt
Heꢀe TnBIO [1:0] = 11
Toggle Output seleꢁt
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion
ETM CCRB Compare Match Output Mode – TnCCLR=1
Note:ꢀ1.ꢀWithꢀTnCCLR=1,ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter
2.ꢀTheꢀTPnBꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀTnBFꢀflag
3.ꢀTheꢀTPnBꢀoutputꢀpinꢀisꢀresetꢀtoꢀitsꢀinitialꢀstateꢀbyꢀaꢀTnONꢀbitꢀrisingꢀedge
4.ꢀTheꢀTnPFꢀflagꢀisꢀnotꢀgeneratedꢀwhenꢀTnCCLR=1
5.ꢀn=1
Rev. 1.00
1ꢅ7
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Timer/Counter Mode
Toꢀselectꢀthisꢀmode,ꢀbitsꢀTnM1ꢀandꢀTnM0ꢀinꢀtheꢀTMnC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ11ꢀrespectively.ꢀ
TheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀ
generatingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/CounterꢀModeꢀtheꢀTMꢀoutputꢀ
pinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀCompareꢀMatchꢀ
OutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀTMꢀoutputꢀpinꢀisꢀnotꢀusedꢀinꢀthisꢀmode,ꢀ
theꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunction.
PWM Output Mode
Toꢀselectꢀthisꢀmode,ꢀtheꢀrequiredꢀbitꢀpairs,ꢀTnAM1,ꢀTnAM0ꢀandꢀTnBM1,ꢀTnBM0ꢀshouldꢀbeꢀsetꢀ
toꢀ10ꢀrespectivelyꢀandꢀalsoꢀtheꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀ
respectively.ꢀTheꢀPWMꢀfunctionꢀwithinꢀtheꢀTMꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀ
suchꢀasꢀmotorꢀcontrol,ꢀheatingꢀcontrol,ꢀilluminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀfixedꢀ
frequencyꢀbutꢀofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀTMꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀ
generatedꢀwithꢀvaryingꢀequivalentꢀDCꢀRMSꢀvalues.
AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ
waveformꢀisꢀextremelyꢀflexible.ꢀInꢀtheꢀPWMꢀmode,ꢀtheꢀTnCCLRꢀbitꢀisꢀusedꢀtoꢀdetermineꢀinꢀwhichꢀ
wayꢀtheꢀPWMꢀperiodꢀisꢀcontrolled.ꢀWithꢀtheꢀTnCCLRꢀbitꢀsetꢀhigh,ꢀtheꢀPWMꢀperiodꢀcanꢀbeꢀfinelyꢀ
controlledꢀusingꢀtheꢀCCRAꢀregisters.ꢀInꢀthisꢀcaseꢀtheꢀCCRBꢀregistersꢀareꢀusedꢀtoꢀsetꢀtheꢀPWMꢀ
dutyꢀvalueꢀ(forꢀTPnBꢀandꢀTPnBBꢀoutputꢀpins).ꢀTheꢀCCRPꢀbitsꢀareꢀnotꢀusedꢀandꢀTPnAꢀoutputꢀpinꢀisꢀ
notꢀused.ꢀTheꢀPWMꢀoutputꢀcanꢀonlyꢀbeꢀgeneratedꢀonꢀtheꢀTPnBꢀandꢀTPnBBꢀoutputꢀpins.ꢀWithꢀtheꢀ
TnCCLRꢀbitꢀclearedꢀtoꢀzero,ꢀtheꢀPWMꢀperiodꢀisꢀsetꢀusingꢀoneꢀofꢀtheꢀeightꢀvaluesꢀofꢀtheꢀthreeꢀCCRPꢀ
bits,ꢀinꢀmultiplesꢀofꢀ128.ꢀNowꢀbothꢀCCRAꢀandꢀCCRBꢀregistersꢀcanꢀbeꢀusedꢀtoꢀsetupꢀdifferentꢀdutyꢀ
cycleꢀvaluesꢀtoꢀprovideꢀdualꢀPWMꢀoutputsꢀonꢀtheirꢀrelativeꢀTPnA,ꢀTPnBꢀandꢀTPnBBꢀpins.
TheꢀTnPWM1ꢀandꢀTnPWM0ꢀbitsꢀdetermineꢀtheꢀPWMꢀalignmentꢀtype,ꢀwhichꢀcanꢀbeꢀeitherꢀedgeꢀ
orꢀcentreꢀtype.ꢀInꢀedgeꢀalignment,ꢀtheꢀleadingꢀedgeꢀofꢀtheꢀPWMꢀsignalsꢀwillꢀallꢀbeꢀgeneratedꢀ
concurrentlyꢀwhenꢀtheꢀcounterꢀisꢀresetꢀtoꢀzero.ꢀWithꢀallꢀpowerꢀcurrentsꢀswitchingꢀonꢀatꢀtheꢀsameꢀ
time,ꢀthisꢀmayꢀgiveꢀriseꢀtoꢀproblemsꢀinꢀhigherꢀpowerꢀapplications.ꢀInꢀcentreꢀalignmentꢀtheꢀcentreꢀ
ofꢀtheꢀPWMꢀactiveꢀsignalsꢀwillꢀoccurꢀsequentially,ꢀthusꢀreducingꢀtheꢀlevelꢀofꢀsimultaneousꢀpowerꢀ
switchingꢀcurrents.
Interruptꢀflags,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRA,ꢀCCRBꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀ
matchꢀoccursꢀfromꢀeitherꢀtheꢀComparatorꢀA,ꢀComparatorꢀBꢀorꢀComparatorꢀP.ꢀTheꢀTnAOCꢀandꢀ
TnBOCꢀbitsꢀinꢀtheꢀTMnC1ꢀandꢀTMnC2ꢀregisterꢀareꢀusedꢀtoꢀselectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀ
waveformꢀwhileꢀtheꢀtwoꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀpairsꢀareꢀusedꢀtoꢀenableꢀtheꢀ
PWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀTMꢀoutputꢀpinꢀtoꢀaꢀfixedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀTnAPOLꢀandꢀTnBPOLꢀ
bitꢀareꢀusedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.
Rev. 1.00
1ꢅ8
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0
CCRP
Peꢀiod
A Duty
B Duty
001b
010b
011b
100b
101b
110b
111b
000b
1ꢃ8
ꢃ56
ꢅ84
51ꢃ
640
768
896
10ꢃ4
CCRA
CCRB
IfꢀfSYS=12MHz,ꢀTMꢀclockꢀsourceꢀselectꢀfSYS/4,ꢀCCRP=100b,ꢀCCRA=128ꢀandꢀCCRB=256,
TheꢀTPnAꢀPWMꢀoutputꢀfrequency=(fSYS/4)/512=fSYS/2048=5.8594kHz,ꢀduty=128/512=25%.
TheꢀTPnBꢀorꢀTPnBBꢀPWMꢀoutputꢀfrequency=(fSYS/4)/512=fSYS/2048=5.8594kHz,ꢀduty=256/512=50%.
IfꢀtheꢀDutyꢀvalueꢀdefinedꢀbyꢀCCRAꢀorꢀCCRBꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀ
thenꢀtheꢀPWMꢀoutputꢀdutyꢀisꢀ100%.
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1
CCRA
Peꢀiod
B Duty
1
2
3
511
512
1021
1022
1023
1
ꢃ
ꢅ
511
51ꢃ
10ꢃ1
10ꢃꢃ
10ꢃꢅ
CCRB
ETM, PWM Mode, Center-aligned Mode, TnCCLR=0
CCRA
Peꢀiod
A Duty
B Duty
001b
010b
011b
100b
101b
110b
111b
000b
ꢃ56
51ꢃ
768
10ꢃ4
1ꢃ80
15ꢅ6
179ꢃ
ꢃ046
(CCRA×ꢃ)-1
(CCRB×ꢃ)-1
ETM, PWM Mode, Center-aligned Mode, TnCCLR=1
CCRA
Peꢀiod
B Duty
1
2
3
511
512
1021
1022
1023
ꢃ
4
6
10ꢃꢃ
10ꢃ4
ꢃ04ꢃ
ꢃ044
ꢃ046
(CCRB×ꢃ)-1
Rev. 1.00
1ꢅ9
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
TnCCLR = 0;
TnA� [1:0] = 10ꢄ TnB� [1:0] = 10;
Counteꢀ Cleaꢀed by CCRP
TnPW� [1:0] = 00
CCRP
CCRA
CCRB
Counteꢀ
Restaꢀt
Resume
Stop
Pause
Time
TnON
TnPAU
TnAPOL
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
TPnA Pin
(TnAOC=1)
Duty Cyꢁle
set by CCRA
Duty Cyꢁle
set by CCRA
Duty Cyꢁle
set by CCRA
Output Inveꢀts
wꢂen TnAPOL
is ꢂigꢂ
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Duty Cyꢁle
set by CCRB
Output ꢁontꢀolled by
otꢂeꢀ pin-sꢂaꢀed funꢁtion Reset to Initial value
Output Pin
PW� Peꢀiod set by CCRP
ETM PWM Mode – Edge Aligned
Note:ꢀ1.ꢀHereꢀTnCCLR=0ꢀthereforeꢀCCRPꢀclearsꢀtheꢀcounterꢀandꢀdeterminesꢀtheꢀPWMꢀperiod
2.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnAIOꢀ[1:0]ꢀ(orꢀTnBIOꢀ[1:0])=00ꢀorꢀ01
3.ꢀCCRAꢀcontrolsꢀtheꢀTPnAꢀPWMꢀdutyꢀandꢀCCRBꢀcontrolsꢀtheꢀTPnBꢀPWMꢀduty
4.ꢀn=1
Rev. 1.00
140
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counter Value
TnCCLR = 1; TnBM [1:0] = 10;
TnPWM [1:0] = 00
Counter Cleared by CCRA
CCRA
CCRB
Counter
Restart
Resume
Stop
Pause
Time
TnON
TnPAU
TnBPOL
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Duty Cycle
set by CCRB
Output Pin
Reset to
Initial value
Output Inverts
when TnBPOL
is high
Output controlled by
other pin-shared function
PWM Period set by CCRA
ETM PWM Mode – Edge Aligned
Note:ꢀ1.ꢀHereꢀTnCCLR=1ꢀthereforeꢀCCRAꢀclearsꢀtheꢀcounterꢀandꢀdeterminesꢀtheꢀPWMꢀperiod
2.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnBIOꢀ[1:0]=00ꢀorꢀ01
3.ꢀTheꢀCCRAꢀcontrolsꢀtheꢀTPnBꢀPWMꢀperiodꢀandꢀCCRBꢀcontrolsꢀtheꢀTPnBꢀPWMꢀduty
4.ꢀHereꢀtheꢀTMꢀpinꢀcontrolꢀregisterꢀshouldꢀnotꢀenableꢀtheꢀTPnAꢀpinꢀasꢀaꢀTMꢀoutputꢀpin
5.ꢀn=1
Rev. 1.00
141
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
TnCCLR = 0;
TnA� [1:0] = 10ꢄ TnB� [1:0] = 10;
TnPW� [1:0] = 11
CCRP
CCRA
CCRB
Counteꢀ
Restaꢀt
Stop
Resume
Pause
Time
TnON
TnPAU
TnAPOL
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
TPnA Pin
(TnAOC=1)
Duty Cyꢁle set by CCRA
Output Inveꢀts
TPnB Pin
(TnBOC=1)
wꢂen TnAPOL
is ꢂigꢂ
TPnB Pin
(TnBOC=0)
Duty Cyꢁle set by CCRB
PW� Peꢀiod set by CCRP
Output ꢁontꢀolled by
Otꢂeꢀ pin-sꢂaꢀed funꢁtion
Output Pin
Reset to Initial value
ETM PWM Mode – Centre Aligned
Note:ꢀ1.ꢀHereꢀTnCCLR=0ꢀthereforeꢀCCRPꢀclearsꢀtheꢀcounterꢀandꢀdeterminesꢀtheꢀPWMꢀperiod
2.ꢀTnPWMꢀ[1:0]=11ꢀthereforeꢀtheꢀPWMꢀisꢀcentreꢀaligned
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnAIOꢀ[1:0]ꢀ(orꢀTnBIOꢀ[1:0])=00ꢀorꢀ01
4.ꢀCCRAꢀcontrolsꢀtheꢀTPnAꢀPWMꢀdutyꢀandꢀCCRBꢀcontrolsꢀtheꢀTPnBꢀPWMꢀduty
5.ꢀCCRPꢀwillꢀgenerateꢀanꢀinterruptꢀrequestꢀwhenꢀtheꢀcounterꢀdecrementsꢀtoꢀitsꢀzeroꢀvalue
6.ꢀn=1
Rev. 1.00
14ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
CCRA
TnCCLR = 1; TnB� [1:0] = 10;
TnPW� [1:0] = 11
Counteꢀ
Restaꢀt
Stop
Resume
Pause
CCRB
Time
TnON
TnPAU
TnBPOL
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Output ꢁontꢀolled
by otꢂeꢀ pin-sꢂaꢀed
funꢁtion
Output Inveꢀts
wꢂen TnBPOL is ꢂigꢂ
Output Pin
Reset to Initial value
Duty Cyꢁle set by CCRB
PW� Peꢀiod set by CCRA
ETM PWM Mode – Centre Aligned
Note: 1.ꢀHereꢀTnCCLR=1ꢀthereforeꢀCCRAꢀclearsꢀtheꢀcounterꢀandꢀdeterminesꢀtheꢀPWMꢀperiod
2.ꢀTnPWMꢀ[1:0]=11ꢀthereforeꢀtheꢀPWMꢀisꢀcentreꢀaligned
3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀTnBIOꢀ[1:0]=00ꢀorꢀ01
4.ꢀCCRAꢀcontrolsꢀtheꢀTPnBꢀPWMꢀperiodꢀandꢀCCRBꢀcontrolsꢀtheꢀTPnBꢀPWMꢀduty
5.ꢀCCRPꢀwillꢀgenerateꢀanꢀinterruptꢀrequestꢀwhenꢀtheꢀcounterꢀdecrementsꢀtoꢀitsꢀzeroꢀvalue
6.ꢀn=1
Rev. 1.00
14ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Single Pulse Mode
Toꢀselectꢀthisꢀmode,ꢀtheꢀrequiredꢀbitꢀpairs,ꢀTnAM1,ꢀTnAM0ꢀandꢀTnBM1,ꢀTnBM0ꢀshouldꢀbeꢀsetꢀtoꢀ
10ꢀrespectivelyꢀandꢀalsoꢀtheꢀcorrespondingꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀshouldꢀbeꢀ
setꢀtoꢀ11ꢀrespectively.ꢀTheꢀSingleꢀPulseꢀOutputꢀMode,ꢀasꢀtheꢀnameꢀsuggests,ꢀwillꢀgenerateꢀaꢀsingleꢀ
shotꢀpulseꢀonꢀtheꢀTMꢀoutputꢀpin.
TheꢀtriggerꢀforꢀtheꢀpulseꢀTPnAꢀoutputꢀleadingꢀedgeꢀisꢀaꢀlowꢀtoꢀhighꢀtransitionꢀofꢀtheꢀTnONꢀbit,ꢀwhichꢀ
canꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogram.ꢀTheꢀtriggerꢀforꢀtheꢀpulseꢀTPnBꢀoutputꢀleadingꢀ
edgeꢀisꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀB,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀ
program.ꢀHoweverꢀinꢀtheꢀSingleꢀPulseꢀMode,ꢀtheꢀTnONꢀbitꢀcanꢀalsoꢀbeꢀmadeꢀtoꢀautomaticallyꢀ
changeꢀfromꢀlowꢀtoꢀhighꢀusingꢀtheꢀexternalꢀTCKnꢀpin,ꢀwhichꢀwillꢀinꢀturnꢀinitiateꢀtheꢀSingleꢀPulseꢀ
outputꢀofꢀTPnA.ꢀWhenꢀtheꢀTnONꢀbitꢀtransitionsꢀtoꢀaꢀhighꢀlevel,ꢀtheꢀcounterꢀwillꢀstartꢀrunningꢀandꢀtheꢀ
pulseꢀleadingꢀedgeꢀofꢀTPnAꢀwillꢀbeꢀgenerated.ꢀTheꢀTnONꢀbitꢀshouldꢀremainꢀhighꢀwhenꢀtheꢀpulseꢀisꢀ
inꢀitsꢀactiveꢀstate.ꢀTheꢀgeneratedꢀpulseꢀtrailingꢀedgeꢀofꢀTPnAꢀandꢀTPnBꢀorꢀTPnBBꢀwillꢀbeꢀgeneratedꢀ
whenꢀtheꢀTnONꢀbitꢀisꢀclearedꢀtoꢀzero,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogramꢀorꢀ
whenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.
HoweverꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀautomaticallyꢀclearꢀtheꢀTnONꢀbitꢀandꢀthusꢀ
generateꢀtheꢀSingleꢀPulseꢀoutputꢀtrailingꢀedgeꢀofꢀTPnAꢀandꢀTPnBꢀorꢀTPnBB.ꢀInꢀthisꢀwayꢀtheꢀCCRAꢀ
valueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀpulseꢀwidthꢀofꢀTPnA.ꢀTheꢀ(CCRA-CCRB)ꢀvalueꢀcanꢀbeꢀusedꢀtoꢀ
controlꢀtheꢀpulseꢀwidthꢀofꢀTPnBꢀandꢀTPnBB.ꢀAꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀComparatorꢀ
BꢀwillꢀalsoꢀgenerateꢀTMꢀinterrupts.ꢀTheꢀcounterꢀcanꢀonlyꢀbeꢀresetꢀbackꢀtoꢀzeroꢀwhenꢀtheꢀTnONꢀbitꢀ
changesꢀfromꢀlowꢀtoꢀhighꢀwhenꢀtheꢀcounterꢀrestarts.ꢀꢀInꢀtheꢀSingleꢀPulseꢀModeꢀCCRPꢀisꢀnotꢀused.ꢀ
TheꢀTnCCLRꢀbitꢀisꢀalsoꢀnotꢀused.
Counteꢀ Value
CCRA
CCRB
Time
0
CCRA Leading
Edge
CCRA Tꢀailing
Edge
S/W Command
S/W Command
SET“TnON”
CLR“TnON”
TnON bit
0 à 1
TnON bit
1 à 0
oꢀ
oꢀ
TCKn Pin Tꢀansition
CCRA Compaꢀe �atꢁꢂ
TPnA Output Pin
Pulse Widtꢂ = CCRA Value
TPnB Output Pin
TPnBB Output Pin
Pulse Widtꢂ = (CCRA-CCRB) Value
S/W Command
CLR“TnON”
TnON bit
1 à 0
CCRB Compaꢀe �atꢁꢂ
TnON = 1
oꢀ
CCRA Compaꢀe �atꢁꢂ
CCRB Leading
Edge
CCRB Tꢀailing
Edge
Single Pulse Generation
Rev. 1.00
144
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counteꢀ Value
TnA� [1:0] = 10ꢄ TnB� [1:0] = 10;
TnAIO [1:0] = 11ꢄ TnBIO [1:0] = 11
Counteꢀ stopped
by CCRA
Counteꢀ Reset
wꢂen TnON
ꢀetuꢀns ꢂigꢂ
CCRA
CCRB
Counteꢀ Stops
by softwaꢀe
Resume
Pause
Time
TnON
Auto. set by
TCKn pin
Softwaꢀe
Tꢀiggeꢀ
Cleaꢀed by
CCRA matꢁꢂ
Softwaꢀe
Tꢀiggeꢀ
Softwaꢀe
Cleaꢀ
Softwaꢀe
Tꢀiggeꢀ
Softwaꢀe
Tꢀiggeꢀ
TCKn pin
TnPAU
TCKn pin
Tꢀiggeꢀ
TnAPOL
TnBPOL
CCRB Int.
Flag TnBF
CCRA Int.
Flag TnAF
TPnA Pin
(TnAOC=1)
Pulse Widtꢂ
set by CCRA
TPnA Pin
(TnAOC=0)
Output Inveꢀts
wꢂen TnAPOL=1
TPnB Pin
(TnBOC=1)
TPnB Pin
Pulse Widtꢂ set
by (CCRA-CCRB)
(TnBOC=0)
Output Inveꢀts
wꢂen TnBPOL=1
ETM – Single Pulse Mode
Note:ꢀ1.ꢀCounterꢀstoppedꢀbyꢀCCRA
2.ꢀCCRPꢀisꢀnotꢀused
3.ꢀTheꢀpulseꢀtriggeredꢀbyꢀtheꢀTCKnꢀpinꢀorꢀbyꢀsettingꢀtheꢀTnONꢀbitꢀhigh
4.ꢀAꢀTCKnꢀpinꢀactiveꢀedgeꢀwillꢀautomaticallyꢀsetꢀtheꢀTnONꢀbitꢀhigh
5.ꢀInꢀtheꢀSingleꢀPulseꢀMode,ꢀTnAIOꢀ[1:0]ꢀandꢀTnBIOꢀ[1:0]ꢀmustꢀbeꢀsetꢀtoꢀ“11”ꢀandꢀcanꢀnotꢀbeꢀchanged
6.ꢀn=1
Rev. 1.00
145
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Capture Input Mode
ToꢀselectꢀthisꢀmodeꢀbitsꢀTnAM1,ꢀTnAM0ꢀandꢀTnBM1,ꢀTnBM0ꢀinꢀtheꢀTMnC1ꢀandꢀTMnC2ꢀregistersꢀ
shouldꢀbeꢀsetꢀtoꢀ01ꢀrespectively.ꢀThisꢀmodeꢀenablesꢀexternalꢀsignalsꢀtoꢀcaptureꢀandꢀstoreꢀtheꢀ
presentꢀvalueꢀofꢀtheꢀinternalꢀcounterꢀandꢀcanꢀthereforeꢀbeꢀusedꢀforꢀapplicationsꢀsuchꢀasꢀpulseꢀwidthꢀ
measurements.ꢀTheꢀexternalꢀsignalꢀisꢀsuppliedꢀonꢀtheꢀTPnIAꢀandꢀTPnIBꢀpins,ꢀwhoseꢀactiveꢀedgeꢀcanꢀ
beꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀrisingꢀandꢀfallingꢀedges;ꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀ
selectedꢀusingꢀtheꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀinꢀtheꢀTMnC1ꢀandꢀTMnC2ꢀregisters.ꢀ
TheꢀcounterꢀisꢀstartedꢀwhenꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhichꢀisꢀinitiatedꢀusingꢀtheꢀ
applicationꢀprogram.
WhenꢀtheꢀrequiredꢀedgeꢀtransitionꢀappearsꢀonꢀtheꢀTPnIAꢀandꢀTPnIBꢀpins,ꢀtheꢀpresentꢀvalueꢀinꢀ
theꢀcounterꢀwillꢀbeꢀlatchedꢀintoꢀtheꢀCCRAꢀandꢀCCRBꢀregistersꢀandꢀaꢀTMꢀinterruptꢀgenerated.ꢀ
IrrespectiveꢀofꢀwhatꢀeventsꢀoccurꢀonꢀtheꢀTPnIAꢀandꢀTPnIBꢀpinsꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀfreeꢀrunꢀ
untilꢀtheꢀTnONꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow.ꢀWhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀtheꢀcounterꢀwillꢀ
resetꢀbackꢀtoꢀzero;ꢀinꢀthisꢀwayꢀtheꢀCCRPꢀvalueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀmaximumꢀcounterꢀvalue.ꢀ
WhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀaꢀTMꢀinterruptꢀwillꢀalsoꢀbeꢀgenerated.ꢀ
CountingꢀtheꢀnumberꢀofꢀoverflowꢀinterruptꢀsignalsꢀfromꢀtheꢀCCRPꢀcanꢀbeꢀaꢀusefulꢀmethodꢀinꢀ
measuringꢀlongꢀpulseꢀwidths.ꢀTheꢀTnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀcanꢀselectꢀtheꢀactiveꢀ
triggerꢀedgeꢀonꢀtheꢀTPnIAꢀandꢀTPnIBꢀpinsꢀtoꢀbeꢀaꢀrisingꢀedge,ꢀfallingꢀedgeꢀorꢀbothꢀedgeꢀtypes.ꢀIfꢀtheꢀ
TnAIO1,ꢀTnAIO0ꢀandꢀTnBIO1,ꢀTnBIO0ꢀbitsꢀareꢀbothꢀsetꢀhigh,ꢀthenꢀnoꢀcaptureꢀoperationꢀwillꢀtakeꢀ
placeꢀirrespectiveꢀofꢀwhatꢀhappensꢀonꢀtheꢀTPnIAꢀandꢀTPnIBꢀpins,ꢀhoweverꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀ
counterꢀwillꢀcontinueꢀtoꢀrun.
AsꢀtheꢀTPnIAꢀandꢀTPnIBꢀpinsꢀareꢀpinꢀsharedꢀwithꢀotherꢀfunctions,ꢀcareꢀmustꢀbeꢀtakenꢀifꢀtheꢀTMꢀisꢀinꢀ
theꢀCaptureꢀInputꢀMode.ꢀThisꢀisꢀbecauseꢀifꢀtheꢀpinꢀisꢀsetupꢀasꢀanꢀoutput,ꢀthenꢀanyꢀtransitionsꢀonꢀthisꢀ
pinꢀmayꢀcauseꢀanꢀinputꢀcaptureꢀoperationꢀtoꢀbeꢀexecuted.ꢀTheꢀTnCCLR,ꢀTnAOC,ꢀTnBOC,ꢀTnAPOLꢀ
andꢀTnBPOLꢀbitsꢀareꢀnotꢀusedꢀinꢀthisꢀmode.
Rev. 1.00
146
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Counter Value
TnAM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop Reset
CCRP
YY
Resume
Pause
XX
Time
TnON
TnPAU
Active
edge
Active
edge
Active edge
TM capture
pin TPnIA
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value
XX
YY
XX
YY
TnAIO [1:0]
Value
00 – Rising edge
01 – Falling edge 10 – Both edges
11 – Disable Capture
ETM CCRA Capture Input Mode
Note:ꢀ1.ꢀTnAMꢀ[1:0]=01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀTnAIOꢀ[1:0]ꢀbits
2.ꢀTheꢀTMꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀtheꢀcounterꢀvalueꢀtoꢀCCRA
3.ꢀTnCCLRꢀbitꢀnotꢀused
4.ꢀNoꢀoutputꢀfunctionꢀ--ꢀTnAOCꢀandꢀTnAPOLꢀbitsꢀnotꢀused
5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀzero
6.ꢀn=1
Rev. 1.00
147
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
TnBM1, TnBM0 = 01
Counter
Value
Counter
overflow
Counter
Reset
CCRP
YY
Stop
Pause Resume
XX
Time
TnON bit
TnPAU bit
Active
edges
Active
edge
Active
edge
TM Capture
Pin TPnIB
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
CCRB
Value
XX
YY
XX
YY
TnBIO1, TnBIO0
Value
00 - Rising edge
01 - Falling edge
10 - Both edges
11 - Disable Capture
ETM CCRB Capture Input Mode
Note:ꢀ1.ꢀTnBMꢀ[1:0]=01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀTnBIOꢀ[1:0]ꢀbits
2.ꢀTheꢀTMꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀtheꢀcounterꢀvalueꢀtoꢀCCRB
3.ꢀTnCCLRꢀbitꢀnotꢀused
4.ꢀNoꢀoutputꢀfunctionꢀ--ꢀTnBOCꢀandꢀTnBPOLꢀbitsꢀnotꢀused
5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀzero
6.ꢀn=1
Rev. 1.00
148
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Aanlog to Digital Converter
Theꢀneedꢀtoꢀinterfaceꢀtoꢀrealꢀworldꢀanalogꢀsignalsꢀisꢀaꢀcommonꢀrequirementꢀforꢀmanyꢀelectronicꢀ
systems.ꢀHowever,ꢀtoꢀproperlyꢀprocessꢀtheseꢀsignalsꢀbyꢀaꢀmicrocontroller,ꢀtheyꢀmustꢀfirstꢀbeꢀ
convertedꢀintoꢀdigitalꢀsignalsꢀbyꢀA/Dꢀconverters.ꢀByꢀintegratingꢀtheꢀA/Dꢀconversionꢀelectronicꢀ
circuitryꢀintoꢀtheꢀmicrocontroller,ꢀtheꢀneedꢀforꢀexternalꢀcomponentsꢀisꢀreducedꢀsignificantlyꢀwithꢀtheꢀ
correspondingꢀfollow-onꢀbenefitsꢀofꢀlowerꢀcostsꢀandꢀreducedꢀcomponentꢀspaceꢀrequirements.
A/D Overview
Theꢀdevicesꢀcontainsꢀaꢀmulti-channelꢀanalogꢀtoꢀdigitalꢀconverterꢀwhichꢀcanꢀdirectlyꢀinterfaceꢀtoꢀ
externalꢀanalogꢀsignals,ꢀsuchꢀasꢀthatꢀfromꢀsensorsꢀorꢀotherꢀcontrolꢀsignalsꢀandꢀconvertꢀtheseꢀsignalsꢀ
directlyꢀintoꢀeitherꢀaꢀ12-bitꢀdigitalꢀvalue.
Part No.
Input Channels
A/D Channel Select Bits
Input Pins
HT66F60A
HT66F70A
1ꢃ
ACS4~ACS0
AN0~AN11
TheꢀaccompanyingꢀblockꢀdiagramꢀshowsꢀtheꢀoverallꢀinternalꢀstructureꢀofꢀtheꢀA/Dꢀconverter,ꢀtogetherꢀ
withꢀitsꢀassociatedꢀregisters.
A/D Converter Register Description
OverallꢀoperationꢀofꢀtheꢀA/Dꢀconverterꢀisꢀcontrolledꢀusingꢀfourꢀregisters.ꢀAꢀreadꢀonlyꢀregisterꢀpairꢀ
existsꢀtoꢀstoreꢀtheꢀADCꢀdataꢀ12-bitꢀvalue.ꢀTheꢀremainingꢀtwoꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀ
setupꢀtheꢀoperatingꢀandꢀcontrolꢀfunctionꢀofꢀtheꢀA/Dꢀconverter.
Name
Bit 7
Dꢅ
Bit 6
Dꢃ
Bit 5
D1
D5
D9
—
Bit 4
D0
Bit 3
—
Bit 2
—
Bit 1
—
Bit 0
—
ADRL (ADRFS=0)
ADRL (ADRFS=1)
ADRH (ADRFS=0)
ADRH (ADRFS=1)
ADCR0
D7
D6
D4
Dꢅ
Dꢃ
D1
D0
D11
—
D10
—
D8
D7
D6
D5
D4
—
D11
ACSꢅ
—
D10
ACSꢃ
D9
D8
START
—
EOCB ADOFF
ACS4
ACS1
ACS0
ADCR1
VBGEN ADRFS VREFS
ADCKꢃ ADCK1 ADCK0
A/D Converter Register List
V
D
D
f
S
S
Y
N
¸
2
A
D
C
2
K
A
~
C
D
0
K
P
0
H
V
/
E
R
F
(
=
N
~
0
)
6
P
n
i
s
-
a
h
e
r
d
e
s
e
l
t
c
o
i
n
b
i
s
t
A
O
D
F
F
B
t
i
V
E
R
S
F
A
D
/
C
o
l
k
c
B
t
i
P
P
P
P
P
0
H
H
A
E
F
A
A
/
0
N
,
,
P
A
/
N
1
A
,
1
A
D
/
R
f
e
r
e
n
e
e
c
V
l
t
o
g
a
e
1
/
2
N
P
A
/
N
3
A
,
3
A
D
R
L
/
N
4
A
~
4
P
A
/
N
7
A
,
7
A
D
/
D
t
a
a
A
D
/
C
n
o
e
v
t
r
r
e
R
g
e
s
i
e
t
s
r
A
D
R
H
/
N
6
A
~
8
P
E
/
N
7
A
,
9
0
A
/
1
N
~
0
F
P
/
1
N
A
1
1
V
S
S
A
D
R
S
F
V
B
G
b
t
i
A
S
C
~
4
C
A
0
S
V
B
E
G
N
S
A
T
T
R
E
C
O
B
A
O
D
F
F
A/D Converter Structure
Rev. 1.00
149
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
A/D Converter Data Registers – ADRL, ADRH
Asꢀtheꢀdevicesꢀcontainꢀanꢀinternalꢀ12-bitꢀA/Dꢀconverter,ꢀitꢀrequiresꢀtwoꢀdataꢀregistersꢀtoꢀstoreꢀtheꢀ
convertedꢀvalue.ꢀTheseꢀareꢀaꢀhighꢀbyteꢀregister,ꢀknownꢀasꢀADRH,ꢀandꢀaꢀlowꢀbyteꢀregister,ꢀknownꢀ
asꢀADRL.ꢀAfterꢀtheꢀconversionꢀprocessꢀtakesꢀplace,ꢀtheseꢀregistersꢀcanꢀbeꢀdirectlyꢀreadꢀbyꢀtheꢀ
microcontrollerꢀtoꢀobtainꢀtheꢀdigitisedꢀconversionꢀvalue.ꢀAsꢀonlyꢀ12ꢀbitsꢀofꢀtheꢀ16-bitꢀregisterꢀspaceꢀ
isꢀutilised,ꢀtheꢀformatꢀinꢀwhichꢀtheꢀdataꢀisꢀstoredꢀisꢀcontrolledꢀbyꢀtheꢀADRFSꢀbitꢀinꢀtheꢀADCR0ꢀ
registerꢀasꢀshownꢀinꢀtheꢀaccompanyingꢀtable.ꢀD0~D11ꢀareꢀtheꢀA/Dꢀconversionꢀresultꢀdataꢀbits.ꢀAnyꢀ
unusedꢀbitsꢀwillꢀbeꢀreadꢀasꢀzero.
ADRH
ADRL
ADRFS
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
D11 D10 D9 D8 D7 D6 D5 D4 Dꢅ Dꢃ D1 D0
0
0
0
0
0
0
0
0
D11 D10 D9 D8 D7 D6 D5 D4 Dꢅ Dꢃ D1 D0
A/D Data Registers
A/D Converter Control Registers – ADCR0, ADCR1, PAS0~PAS3, PES3, PFS0, PHS0
ToꢀcontrolꢀtheꢀfunctionꢀandꢀoperationꢀofꢀtheꢀA/Dꢀconverter,ꢀtwoꢀcontrolꢀregistersꢀknownꢀasꢀADCR0ꢀ
andꢀADCR1ꢀareꢀprovided.ꢀTheseꢀ8-bitꢀregistersꢀdefineꢀfunctionsꢀsuchꢀasꢀtheꢀselectionꢀofꢀwhichꢀ
analogꢀchannelꢀisꢀconnectedꢀtoꢀtheꢀinternalꢀA/Dꢀconverter,ꢀtheꢀdigitisedꢀdataꢀformat,ꢀtheꢀA/Dꢀclockꢀ
sourceꢀasꢀwellꢀasꢀcontrollingꢀtheꢀstartꢀfunctionꢀandꢀmonitoringꢀtheꢀA/Dꢀconverterꢀendꢀofꢀconversionꢀ
status.ꢀTheꢀACS4~ACS0ꢀbitsꢀinꢀtheꢀADCR0ꢀregisterꢀdefineꢀtheꢀADCꢀinputꢀchannelꢀnumber.ꢀAsꢀtheꢀ
deviceꢀcontainsꢀonlyꢀoneꢀactualꢀanalogꢀtoꢀdigitalꢀconverterꢀhardwareꢀcircuit,ꢀeachꢀofꢀtheꢀindividualꢀ
12ꢀanalogꢀinputsꢀmustꢀbeꢀroutedꢀtoꢀtheꢀconverter.ꢀItꢀisꢀtheꢀfunctionꢀofꢀtheꢀACS4~ACS0ꢀbitsꢀtoꢀ
determineꢀwhichꢀanalogꢀchannelꢀinputꢀpinsꢀorꢀinternalꢀ1.25Vꢀisꢀactuallyꢀconnectedꢀtoꢀtheꢀinternalꢀ
A/Dꢀconverter.
Theꢀpin-sharedꢀfunctionꢀconntrolꢀregisters,ꢀnamedꢀPAS0~PAS3,ꢀPES3,ꢀPFS0ꢀandꢀPHS0,ꢀcontainꢀtheꢀ
correspondingꢀpin-sharedꢀfunctionꢀselectionꢀbitsꢀwhichꢀdetermineꢀwhichꢀpinsꢀonꢀPortꢀA,ꢀPortꢀE,ꢀPortꢀ
FꢀandꢀPortꢀHꢀareꢀusedꢀasꢀanalogꢀinputsꢀforꢀtheꢀA/Dꢀconverterꢀinputꢀandꢀwhichꢀpinsꢀareꢀnotꢀtoꢀbeꢀusedꢀ
asꢀtheꢀA/Dꢀconverterꢀinput.ꢀConfiguringꢀtheꢀcorrespondingꢀbitꢀwillꢀselectꢀtheꢀA/Dꢀinputꢀfunctionꢀorꢀ
eitherꢀtheꢀI/Oꢀorꢀotherꢀpin-sharedꢀfunction.ꢀWhenꢀtheꢀpinꢀisꢀselectedꢀtoꢀbeꢀanꢀA/Dꢀinput,ꢀitsꢀoriginalꢀ
functionꢀwhetherꢀitꢀisꢀanꢀI/Oꢀorꢀotherꢀpin-sharedꢀfunctionꢀwillꢀbeꢀremoved.ꢀInꢀaddition,ꢀanyꢀinternalꢀ
pull-highꢀresistorsꢀconnectedꢀtoꢀtheseꢀpinsꢀwillꢀbeꢀautomaticallyꢀremovedꢀifꢀtheꢀpinꢀisꢀselectedꢀtoꢀbeꢀ
anꢀA/Dꢀinput.
Rev. 1.00
150
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• ADCR0 Register
Bit
Name
R/W
7
START
R/W
0
6
EOCB
R
5
ADOFF
R/W
1
4
ACS4
R/W
0
3
ACSꢅ
R/W
0
2
ACSꢃ
R/W
0
1
ACS1
R/W
0
0
ACS0
R/W
0
POR
1
Bitꢀ7
START:ꢀStartꢀtheꢀA/Dꢀconversion
0→1→0:ꢀStart
0→1:ꢀResetꢀtheꢀA/DꢀconverterꢀandꢀsetꢀEOCBꢀtoꢀ“1”
ThisꢀbitꢀisꢀusedꢀtoꢀinitiateꢀanꢀA/Dꢀconversionꢀprocess.ꢀTheꢀbitꢀisꢀnormallyꢀlowꢀbutꢀifꢀsetꢀ
highꢀandꢀthenꢀclearedꢀlowꢀagain,ꢀtheꢀA/Dꢀconverterꢀwillꢀinitiateꢀaꢀconversionꢀprocess.ꢀ
WhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀA/Dꢀconverterꢀwillꢀbeꢀreset.
Bitꢀ6
Bitꢀ5
EOCB:ꢀEndꢀofꢀA/Dꢀconversionꢀflag
0:ꢀA/Dꢀconversionꢀended
1:ꢀA/Dꢀconversionꢀinꢀprogress
ThisꢀreadꢀonlyꢀflagꢀisꢀusedꢀtoꢀindicateꢀwhenꢀanꢀA/Dꢀconversionꢀprocessꢀhasꢀcompleted.ꢀ
Whenꢀtheꢀconversionꢀprocessꢀisꢀrunning,ꢀtheꢀbitꢀwillꢀbeꢀhigh.
ADOFFꢀ:ꢀADCꢀmoduleꢀpowerꢀon/offꢀcontrolꢀbit
0:ꢀADCꢀmoduleꢀpowerꢀon
1:ꢀADCꢀmoduleꢀpowerꢀoff
ThisꢀbitꢀcontrolsꢀtheꢀpowerꢀtoꢀtheꢀA/Dꢀinternalꢀfunction.ꢀThisꢀbitꢀshouldꢀbeꢀclearedꢀ
toꢀzeroꢀtoꢀenableꢀtheꢀA/Dꢀconverter.ꢀIfꢀtheꢀbitꢀisꢀsetꢀhighꢀthenꢀtheꢀA/Dꢀconverterꢀwillꢀ
beꢀswitchedꢀoffꢀreducingꢀtheꢀdeviceꢀpowerꢀconsumption.ꢀAsꢀtheꢀA/Dꢀconverterꢀwillꢀ
consumeꢀaꢀlimitedꢀamountꢀofꢀpower,ꢀevenꢀwhenꢀnotꢀexecutingꢀaꢀconversion,ꢀthisꢀmayꢀ
beꢀanꢀimportantꢀconsiderationꢀinꢀpowerꢀsensitiveꢀbatteryꢀpoweredꢀapplications.
Note:ꢀ1.ꢀitꢀisꢀrecommendedꢀtoꢀsetꢀADOFF=1ꢀbeforeꢀenteringꢀIDLE/SLEEPꢀModeꢀforꢀ
savingꢀpower.
2.ꢀADOFF=1ꢀwillꢀpowerꢀdownꢀtheꢀADCꢀmodule.
Bitꢀ4~0ꢀ
ACS4~ACS0:ꢀSelectꢀA/Dꢀchannel
00000:ꢀAN0
00001:ꢀAN1
00010:ꢀAN2
00011:ꢀAN3
00100:ꢀAN4
00101:ꢀAN5
00110:ꢀAN6
00111:ꢀAN7
01000:ꢀAN8
01001:ꢀAN9
01010:ꢀAN10
01011:ꢀAN11
011xx:ꢀUndefined
1xxxx:ꢀInternalꢀBandgapꢀvoltage
TheseꢀareꢀtheꢀA/Dꢀchannelꢀselectꢀcontrolꢀbits.ꢀAsꢀthereꢀisꢀonlyꢀoneꢀinternalꢀhardwareꢀ
A/DꢀconverterꢀeachꢀofꢀtheꢀtwelveꢀA/Dꢀinputsꢀmustꢀbeꢀroutedꢀtoꢀtheꢀinternalꢀconverterꢀ
usingꢀtheseꢀbits.ꢀIfꢀtheꢀACS4ꢀbitꢀisꢀsetꢀhigh,ꢀthenꢀtheꢀinternalꢀBandgapꢀ1.25Vꢀwillꢀbeꢀ
routedꢀtoꢀtheꢀA/DꢀConverter.
Rev. 1.00
151
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
• ADCR1 Register
Bit
Name
R/W
7
6
5
ADRFS
R/W
1
4
VREFS
R/W
0
3
2
ADCKꢃ
R/W
0
1
ADCK1
R/W
0
0
ADCK0
R/W
0
—
—
—
VBGEN
—
—
—
R
1
POR
Bitꢀ7ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ6
VBGEN:ꢀInternalꢀBandgapꢀvoltageꢀcontrol
0:ꢀDisable
1:ꢀEnable
ThisꢀbitꢀcontrolsꢀtheꢀinternalꢀBandgapꢀcircuitꢀon/offꢀfunctionꢀtoꢀtheꢀA/Dꢀconverter.ꢀ
Whenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀbandgapꢀvoltageꢀ1.25VꢀcanꢀbeꢀusedꢀbyꢀtheꢀA/Dꢀconverter.ꢀ
Ifꢀ1.25VꢀisꢀnotꢀusedꢀbyꢀtheꢀA/DꢀconverterꢀandꢀtheꢀLVR/LVDꢀfunctionꢀisꢀdisabledꢀthenꢀ
theꢀbandgapꢀreferenceꢀcircuitꢀwillꢀbeꢀautomaticallyꢀswitchedꢀoffꢀtoꢀconserveꢀpower.ꢀ
Whenꢀ1.25VꢀisꢀswitchedꢀonꢀforꢀuseꢀbyꢀtheꢀA/Dꢀconverter,ꢀaꢀtimeꢀtBGꢀshouldꢀbeꢀ
allowedꢀforꢀtheꢀbandgapꢀcircuitꢀtoꢀstabiliseꢀbeforeꢀimplementingꢀanꢀA/Dꢀconversion.
Bitꢀ5
Bitꢀ4
ADRFS:ꢀADCꢀDataꢀFormatꢀControl
0:ꢀADCꢀDataꢀMSBꢀisꢀADRHꢀbitꢀ7,ꢀLSBꢀisꢀADRLꢀbitꢀ4
1:ꢀADCꢀDataꢀMSBꢀisꢀADRHꢀbitꢀ3,ꢀLSBꢀisꢀADRLꢀbitꢀ0
Thisꢀbitꢀcontrolsꢀtheꢀformatꢀofꢀtheꢀ12-bitꢀconvertedꢀA/DꢀvalueꢀinꢀtheꢀtwoꢀA/Dꢀdataꢀ
registers.ꢀDetailsꢀareꢀprovidedꢀinꢀtheꢀA/Dꢀdataꢀregisterꢀsection.
VREFS:ꢀSelectꢀADCꢀreferenceꢀvoltage
0:ꢀInternalꢀADCꢀpower
1:ꢀVREFꢀpin
ThisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀreferenceꢀvoltageꢀforꢀtheꢀA/Dꢀconverter.ꢀIfꢀtheꢀbitꢀisꢀhigh,ꢀ
thenꢀtheꢀA/DꢀconverterꢀreferenceꢀvoltageꢀisꢀsuppliedꢀonꢀtheꢀexternalꢀVREFꢀpin.ꢀIfꢀtheꢀ
pinꢀisꢀlow,ꢀthenꢀtheꢀinternalꢀreferenceꢀisꢀusedꢀwhichꢀisꢀtakenꢀfromꢀtheꢀpowerꢀsupplyꢀpinꢀ
VDD.
Bitꢀ3ꢀ
Unimplemented,ꢀreadꢀasꢀ"0"
Bitꢀ2~0
ADCK2,ꢀADCK1, ADCK0:ꢀSelectꢀADCꢀclockꢀsource
000:ꢀfSYS
001:ꢀfSYS/2
010:ꢀfSYS/4
011:ꢀfSYS/8
100:ꢀfSYS/16
101:ꢀfSYS/32
110:ꢀfSYS/64
111:ꢀUndefined
TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀA/Dꢀconverter.
Rev. 1.00
15ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
A/D Operation
TheꢀSTARTꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀisꢀusedꢀtoꢀstartꢀandꢀresetꢀtheꢀA/Dꢀconverter.ꢀWhenꢀtheꢀ
microcontrollerꢀsetsꢀthisꢀbitꢀfromꢀlowꢀtoꢀhighꢀandꢀthenꢀlowꢀagain,ꢀanꢀanalogꢀtoꢀdigitalꢀconversionꢀ
cycleꢀwillꢀbeꢀinitiated.ꢀWhenꢀtheꢀSTARTꢀbitꢀisꢀbroughtꢀfromꢀlowꢀtoꢀhighꢀbutꢀnotꢀlowꢀagain,ꢀtheꢀ
EOCBꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀwillꢀbeꢀsetꢀhighꢀandꢀtheꢀanalogꢀtoꢀdigitalꢀconverterꢀwillꢀbeꢀreset.ꢀ
ItꢀisꢀtheꢀSTARTꢀbitꢀthatꢀisꢀusedꢀtoꢀcontrolꢀtheꢀoverallꢀstartꢀoperationꢀofꢀtheꢀinternalꢀanalogꢀtoꢀdigitalꢀ
converter.
TheꢀEOCBꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀisꢀusedꢀtoꢀindicateꢀwhenꢀtheꢀanalogꢀtoꢀdigitalꢀconversionꢀ
processꢀisꢀcomplete.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀsetꢀtoꢀ“0”ꢀbyꢀtheꢀmicrocontrollerꢀafterꢀaꢀ
conversionꢀcycleꢀhasꢀended.ꢀInꢀaddition,ꢀtheꢀcorrespondingꢀA/Dꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀsetꢀ
inꢀtheꢀinterruptꢀcontrolꢀregister,ꢀandꢀifꢀtheꢀinterruptsꢀareꢀenabled,ꢀanꢀappropriateꢀinternalꢀinterruptꢀ
signalꢀwillꢀbeꢀgenerated.ꢀThisꢀA/Dꢀinternalꢀinterruptꢀsignalꢀwillꢀdirectꢀtheꢀprogramꢀflowꢀtoꢀtheꢀ
associatedꢀA/Dꢀinternalꢀinterruptꢀaddressꢀforꢀprocessing.ꢀIfꢀtheꢀA/Dꢀinternalꢀinterruptꢀisꢀdisabled,ꢀ
theꢀmicrocontrollerꢀcanꢀbeꢀusedꢀtoꢀpollꢀtheꢀEOCBꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀtoꢀcheckꢀwhetherꢀitꢀhasꢀ
beenꢀclearedꢀasꢀanꢀalternativeꢀmethodꢀofꢀdetectingꢀtheꢀendꢀofꢀanꢀA/Dꢀconversionꢀcycle.
TheꢀclockꢀsourceꢀforꢀtheꢀA/Dꢀconverter,ꢀwhichꢀoriginatesꢀfromꢀtheꢀsystemꢀclockꢀfSYS,ꢀcanꢀbeꢀchosenꢀ
toꢀbeꢀeitherꢀfSYSꢀorꢀaꢀsubdividedꢀversionꢀofꢀfSYS.ꢀTheꢀdivisionꢀratioꢀvalueꢀisꢀdeterminedꢀbyꢀtheꢀ
ADCK2~ADCK0ꢀbitsꢀinꢀtheꢀADCR1ꢀregister.
Althoughꢀ theꢀA/Dꢀ clockꢀ sourceꢀ isꢀ determinedꢀ byꢀ theꢀ systemꢀ clocky,ꢀ fSYS,ꢀ andꢀ byꢀ bitsꢀ
ADCK2~ADCK0,ꢀthereꢀareꢀsomeꢀlimitationsꢀonꢀtheꢀmaximumꢀA/Dꢀclockꢀsourceꢀspeedꢀthatꢀcanꢀ
beꢀselected.ꢀAsꢀtheꢀminimumꢀvalueꢀofꢀpermissibleꢀA/Dꢀclockꢀperiod,ꢀtADCK,ꢀisꢀ0.5μs,ꢀcareꢀmustꢀbeꢀ
takenꢀforꢀsystemꢀclockꢀfrequenciesꢀequalꢀtoꢀorꢀgreaterꢀthanꢀ4MHz.ꢀForꢀexample,ꢀifꢀtheꢀsystemꢀclockꢀ
operatesꢀatꢀaꢀfrequencyꢀofꢀ4MHz,ꢀtheꢀADCK2~ADCK0ꢀbitsꢀshouldꢀnotꢀbeꢀsetꢀtoꢀ“000”.ꢀDoingꢀsoꢀ
willꢀgiveꢀA/DꢀclockꢀperiodsꢀthatꢀareꢀlessꢀthanꢀtheꢀminimumꢀA/Dꢀclockꢀperiodꢀwhichꢀmayꢀresultꢀinꢀ
inaccurateꢀA/Dꢀconversionꢀvalues.ꢀReferꢀtoꢀtheꢀfollowingꢀtableꢀforꢀexamples,ꢀwhereꢀvaluesꢀmarkedꢀ
withꢀanꢀasteriskꢀ*ꢀshowꢀwhere,ꢀdependingꢀuponꢀtheꢀdevice,ꢀspecialꢀcareꢀmustꢀbeꢀtaken,ꢀasꢀtheꢀvaluesꢀ
mayꢀbeꢀlessꢀthanꢀtheꢀspecifiedꢀminimumꢀA/DꢀClockꢀPeriod.
A/D Clock Period (tADCK
)
ADCK2, ADCK2, ADCK2, ADCK2, ADCK2, ADCK2, ADCK2, ADCK2,
ADCK1, ADCK1, ADCK1, ADCK1, ADCK1, ADCK1, ADCK1, ADCK1,
fSYS
ADCK0
=000
ADCK0
=001
ADCK0
=010
ADCK0
=011
ADCK0
=100
ADCK0
=101
ADCK0
=110
ADCK0
=111
(fSYS
)
(fSYS/2)
(fSYS/4)
(fSYS/8)
(fSYS/16)
(fSYS/32)
(fSYS/64)
1�Hz
ꢃ�Hz
1μs
2μs
1μs
4μs
2μs
8μs
4μs
16μs
8μs
32μs
16μs
8μs
64μs
32μs
16μs
8μs
Undefined
Undefined
Undefined
Undefined
500ns
4�Hz ꢃ50ns*
8�Hz 1ꢃ5ns*
1ꢃ�Hz 8ꢅns*
500ns
ꢃ50ns*
167ns*
1μs
2μs
4μs
500ns
ꢅꢅꢅns*
1μs
2μs
4μs
667ns
1.33μs
2.67μs
5.33μs Undefined
A/D Clock Period Examples
Controllingꢀtheꢀpowerꢀon/offꢀfunctionꢀofꢀtheꢀA/Dꢀconverterꢀcircuitryꢀisꢀimplementedꢀusingꢀtheꢀ
ADOFFꢀbitꢀinꢀtheꢀADCR0ꢀregister.ꢀThisꢀbitꢀmustꢀbeꢀzeroꢀtoꢀpowerꢀonꢀtheꢀA/Dꢀconverter.ꢀWhenꢀ
theꢀADOFFꢀbitꢀisꢀclearedꢀtoꢀzeroꢀtoꢀpowerꢀonꢀtheꢀA/Dꢀconverterꢀinternalꢀcircuitryꢀaꢀcertainꢀdelay,ꢀ
asꢀindicatedꢀinꢀtheꢀtimingꢀdiagram,ꢀmustꢀbeꢀallowedꢀbeforeꢀanꢀA/Dꢀconversionꢀisꢀinitiated.ꢀEvenꢀifꢀ
noꢀpinsꢀareꢀselectedꢀforꢀuseꢀasꢀA/Dꢀinputs,ꢀifꢀtheꢀADOFFꢀbitꢀisꢀzeroꢀthenꢀsomeꢀpowerꢀwillꢀstillꢀbeꢀ
consumed.ꢀInꢀpowerꢀconsciousꢀapplicationsꢀitꢀisꢀthereforeꢀrecommendedꢀthatꢀtheꢀADOFFꢀisꢀsetꢀhighꢀ
toꢀreduceꢀpowerꢀconsumptionꢀwhenꢀtheꢀA/Dꢀconverterꢀfunctionꢀisꢀnotꢀbeingꢀused.
TheꢀreferenceꢀvoltageꢀsupplyꢀtoꢀtheꢀA/DꢀConverterꢀcanꢀbeꢀsuppliedꢀfromꢀeitherꢀtheꢀpositiveꢀpowerꢀ
supplyꢀpin,ꢀVDD,ꢀorꢀfromꢀanꢀexternalꢀreferenceꢀsourcesꢀsuppliedꢀonꢀpinꢀVREF.ꢀTheꢀdesiredꢀselectionꢀ
isꢀmadeꢀusingꢀtheꢀVREFSꢀandꢀPH0S3~PH0S0ꢀbits.ꢀAsꢀtheꢀVREFꢀpinꢀisꢀpin-sharedꢀwithꢀotherꢀ
functions,ꢀwhenꢀtheꢀVREFSꢀbitꢀisꢀsetꢀhighꢀandꢀtheꢀPH0S3~PH0S0ꢀbitsꢀareꢀsetꢀtoꢀ“0011”,ꢀtheꢀVREFꢀ
pinꢀfunctionꢀwillꢀbeꢀselectedꢀandꢀtheꢀotherꢀpinꢀfunctionsꢀwillꢀbeꢀdisabledꢀautomatically.
Rev. 1.00
15ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
A/D Input Pins
AllꢀofꢀtheꢀA/Dꢀanalogꢀinputꢀpinsꢀareꢀpin-sharedꢀwithꢀtheꢀI/OꢀpinsꢀonꢀPortꢀA,ꢀPortꢀE,ꢀPortꢀFꢀandꢀPortꢀ
Hꢀasꢀwellꢀasꢀotherꢀfunctions.ꢀTheꢀcorrespondingꢀselectionꢀbitsꢀinꢀtheꢀPAS0~PAS3,ꢀPES3,ꢀPFS0ꢀ
andꢀPHS0ꢀregisters,ꢀdetermineꢀwhetherꢀtheꢀinputꢀpinsꢀareꢀsetupꢀasꢀA/Dꢀconverterꢀanalogꢀinputsꢀorꢀ
whetherꢀtheyꢀhaveꢀotherꢀfunctions.ꢀIfꢀtheꢀcorrespondingꢀpinꢀisꢀsetupꢀtoꢀbeꢀanꢀA/Dꢀconverterꢀinput,ꢀ
theꢀoriginalꢀpinꢀfunctionsꢀdisabled.ꢀInꢀthisꢀway,ꢀpinsꢀcanꢀbeꢀchangedꢀunderꢀprogramꢀcontrolꢀtoꢀ
changeꢀtheirꢀfunctionꢀbetweenꢀA/Dꢀinputsꢀandꢀotherꢀfunctions.ꢀAllꢀpull-highꢀresistors,ꢀwhichꢀareꢀ
setupꢀthroughꢀregisterꢀprogramming,ꢀwillꢀbeꢀautomaticallyꢀdisconnectedꢀifꢀtheꢀpinsꢀareꢀsetupꢀasꢀA/Dꢀ
inputs.ꢀNoteꢀthatꢀitꢀisꢀnotꢀnecessaryꢀtoꢀfirstꢀsetupꢀtheꢀA/DꢀpinꢀasꢀanꢀinputꢀinꢀtheꢀPAC,ꢀPEC,ꢀPFCꢀorꢀ
PHCꢀportꢀcontrolꢀregisterꢀtoꢀenableꢀtheꢀA/DꢀinputꢀasꢀwhenꢀtheꢀrelevantꢀA/Dꢀinputꢀfunctionꢀselectionꢀ
bitsꢀenableꢀanꢀA/Dꢀinput,ꢀtheꢀstatusꢀofꢀtheꢀportꢀcontrolꢀregisterꢀwillꢀbeꢀoverridden.
TheꢀA/Dꢀconverterꢀhasꢀitsꢀownꢀreferenceꢀvoltageꢀpin,ꢀVREF,ꢀhoweverꢀtheꢀreferenceꢀvoltageꢀcanꢀ
alsoꢀbeꢀsuppliedꢀfromꢀtheꢀpowerꢀsupplyꢀpin,ꢀaꢀchoiceꢀwhichꢀisꢀmadeꢀthroughꢀtheꢀVREFSꢀbitꢀinꢀtheꢀ
ADCR1ꢀregister.ꢀTheꢀanalogꢀinputꢀvaluesꢀmustꢀnotꢀbeꢀallowedꢀtoꢀexceedꢀtheꢀvalueꢀofꢀVREF
.
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A/D Input Structure
Summary of A/D Conversion Steps
Theꢀfollowingꢀsummarisesꢀtheꢀindividualꢀstepsꢀthatꢀshouldꢀbeꢀexecutedꢀinꢀorderꢀtoꢀimplementꢀanꢀ
A/Dꢀconversionꢀprocess.
•ꢀ Stepꢀ1
SelectꢀtheꢀrequiredꢀA/DꢀconversionꢀclockꢀbyꢀcorrectlyꢀprogrammingꢀbitsꢀADCK2~ADCK0ꢀinꢀtheꢀ
ADCR1ꢀregister.
•ꢀ Stepꢀ2
EnableꢀtheꢀA/DꢀbyꢀclearingꢀtheꢀADOFFꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀtoꢀzero.
•ꢀ Stepꢀ3
SelectꢀwhichꢀchannelꢀisꢀtoꢀbeꢀconnectedꢀtoꢀtheꢀinternalꢀA/Dꢀconverterꢀbyꢀcorrectlyꢀprogrammingꢀ
theꢀACS4~ACS0ꢀbitsꢀwhichꢀareꢀalsoꢀcontainedꢀinꢀtheꢀADCR1ꢀandꢀADCR0ꢀregister.
•ꢀ Stepꢀ4
SelectꢀwhichꢀpinsꢀareꢀtoꢀbeꢀusedꢀasꢀA/Dꢀinputsꢀandꢀconfigureꢀthemꢀbyꢀcorrectlyꢀprogrammingꢀtheꢀ
correspondingꢀpin-sharedꢀfunctionꢀselectionꢀregisters.
•ꢀ Stepꢀ5
Ifꢀtheꢀinterruptsꢀareꢀtoꢀbeꢀused,ꢀtheꢀinterruptꢀcontrolꢀregistersꢀmustꢀbeꢀcorrectlyꢀconfiguredꢀtoꢀ
ensureꢀtheꢀA/Dꢀconverterꢀinterruptꢀfunctionꢀisꢀactive.ꢀTheꢀmasterꢀinterruptꢀcontrolꢀbit,ꢀEMI,ꢀandꢀ
theꢀA/Dꢀconverterꢀinterruptꢀbit,ꢀADE,ꢀmustꢀbothꢀbeꢀsetꢀhighꢀtoꢀdoꢀthis.
Rev. 1.00
154
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
•ꢀ Stepꢀ6
TheꢀanalogꢀtoꢀdigitalꢀconversionꢀprocessꢀcanꢀnowꢀbeꢀinitialisedꢀbyꢀsettingꢀtheꢀSTARTꢀbitꢀinꢀ
theꢀADCR0ꢀregisterꢀfromꢀlowꢀtoꢀhighꢀandꢀthenꢀlowꢀagain.ꢀNoteꢀthatꢀthisꢀbitꢀshouldꢀhaveꢀbeenꢀ
originallyꢀclearedꢀtoꢀzero.
•ꢀ Stepꢀ7
Toꢀcheckꢀwhenꢀtheꢀanalogꢀtoꢀdigitalꢀconversionꢀprocessꢀisꢀcomplete,ꢀtheꢀEOCBꢀbitꢀinꢀtheꢀADCR0ꢀ
registerꢀcanꢀbeꢀpolled.ꢀTheꢀconversionꢀprocessꢀisꢀcompleteꢀwhenꢀthisꢀbitꢀgoesꢀlow.ꢀWhenꢀthisꢀ
occursꢀtheꢀA/DꢀdataꢀregisterꢀADRLꢀandꢀADRHꢀcanꢀbeꢀreadꢀtoꢀobtainꢀtheꢀconversionꢀvalue.ꢀAsꢀanꢀ
alternativeꢀmethod,ꢀifꢀtheꢀinterruptsꢀareꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀtheꢀprogramꢀcanꢀwaitꢀforꢀ
anꢀA/Dꢀinterruptꢀtoꢀoccur.
Note:ꢀWhenꢀcheckingꢀforꢀtheꢀendꢀofꢀtheꢀconversionꢀprocess,ꢀifꢀtheꢀmethodꢀofꢀpollingꢀtheꢀEOCBꢀ
bitꢀinꢀtheꢀADCR0ꢀregisterꢀisꢀused,ꢀtheꢀinterruptꢀenableꢀstepꢀaboveꢀcanꢀbeꢀomitted.
Theꢀaccompanyingꢀdiagramꢀshowsꢀgraphicallyꢀtheꢀvariousꢀstagesꢀinvolvedꢀinꢀanꢀanalogꢀtoꢀdigitalꢀ
conversionꢀprocessꢀandꢀitsꢀassociatedꢀtiming.ꢀAfterꢀanꢀA/Dꢀconversionꢀprocessꢀhasꢀbeenꢀinitiatedꢀ
byꢀtheꢀapplicationꢀprogram,ꢀtheꢀmicrocontrollerꢀinternalꢀhardwareꢀwillꢀbeginꢀtoꢀcarryꢀoutꢀtheꢀ
conversion,ꢀduringꢀwhichꢀtimeꢀtheꢀprogramꢀcanꢀcontinueꢀwithꢀotherꢀfunctions.ꢀTheꢀtimeꢀtakenꢀforꢀtheꢀ
A/Dꢀconversionꢀisꢀ16tADCKꢀwhereꢀtADCKꢀisꢀequalꢀtoꢀtheꢀA/Dꢀclockꢀperiod.
A
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A/D Conversion Timing
Rev. 1.00
155
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Programming Considerations
DuringꢀmicrocontrollerꢀoperationsꢀwhereꢀtheꢀA/Dꢀconverterꢀisꢀnotꢀbeingꢀused,ꢀtheꢀA/Dꢀinternalꢀ
circuitryꢀcanꢀbeꢀswitchedꢀoffꢀtoꢀreduceꢀpowerꢀconsumption,ꢀbyꢀsettingꢀbitꢀADOFFꢀhighꢀinꢀtheꢀ
ADCR0ꢀregister.ꢀWhenꢀthisꢀhappens,ꢀtheꢀinternalꢀA/Dꢀconverterꢀcircuitsꢀwillꢀnotꢀconsumeꢀpowerꢀ
irrespectiveꢀofꢀwhatꢀanalogꢀvoltageꢀisꢀappliedꢀtoꢀtheirꢀinputꢀlines.ꢀIfꢀtheꢀA/Dꢀconverterꢀinputꢀlinesꢀareꢀ
usedꢀasꢀnormalꢀI/Os,ꢀthenꢀcareꢀmustꢀbeꢀtakenꢀasꢀifꢀtheꢀinputꢀvoltageꢀisꢀnotꢀatꢀaꢀvalidꢀlogicꢀlevel,ꢀthenꢀ
thisꢀmayꢀleadꢀtoꢀsomeꢀincreaseꢀinꢀpowerꢀconsumption.
A/D Transfer Function
Asꢀtheꢀdevicesꢀcontainꢀaꢀ12-bitꢀA/Dꢀconverter,ꢀitsꢀfull-scaleꢀconvertedꢀdigitisedꢀvalueꢀisꢀequalꢀtoꢀ
FFFH.ꢀSinceꢀtheꢀfull-scaleꢀanalogꢀinputꢀvalueꢀisꢀequalꢀtoꢀtheꢀVDDꢀorꢀVREFꢀvoltage,ꢀthisꢀgivesꢀaꢀsingleꢀ
bitꢀanalogꢀinputꢀvalueꢀofꢀVDDꢀorꢀVREFꢀdividedꢀbyꢀ4096.
1ꢀLSB=(VDDꢀorꢀVREF)÷4096
TheꢀA/DꢀConverterꢀinputꢀvoltageꢀvalueꢀcanꢀbeꢀcalculatedꢀusingꢀtheꢀfollowingꢀequation:
A/Dꢀinputꢀvoltage=A/Dꢀoutputꢀdigitalꢀvalueꢀ×ꢀ(VDDꢀorꢀVREF)÷4096
Theꢀdiagramꢀshowsꢀtheꢀidealꢀtransferꢀfunctionꢀbetweenꢀtheꢀanalogꢀinputꢀvalueꢀandꢀtheꢀdigitisedꢀ
outputꢀvalueꢀforꢀtheꢀA/Dꢀconverter.ꢀExceptꢀforꢀtheꢀdigitisedꢀzeroꢀvalue,ꢀtheꢀsubsequentꢀdigitisedꢀ
valuesꢀwillꢀchangeꢀatꢀaꢀpointꢀ0.5ꢀLSBꢀbelowꢀwhereꢀtheyꢀwouldꢀchangeꢀwithoutꢀtheꢀoffset,ꢀandꢀtheꢀ
lastꢀfullꢀscaleꢀdigitisedꢀvalueꢀwillꢀchangeꢀatꢀaꢀpointꢀ1.5ꢀLSBꢀbelowꢀtheꢀVDDꢀorꢀVREFꢀlevel.
1
5
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Ideal A/D Transfer Function
Rev. 1.00
156
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
A/D Programming Example
TheꢀfollowingꢀtwoꢀprogrammingꢀexamplesꢀillustrateꢀhowꢀtoꢀsetupꢀandꢀimplementꢀanꢀA/Dꢀconversion.ꢀ
Inꢀtheꢀfirstꢀexample,ꢀtheꢀmethodꢀofꢀpollingꢀtheꢀEOCBꢀbitꢀinꢀtheꢀADCR0ꢀregisterꢀisꢀusedꢀtoꢀdetectꢀ
whenꢀtheꢀconversionꢀcycleꢀisꢀcomplete,ꢀwhereasꢀinꢀtheꢀsecondꢀexample,ꢀtheꢀA/Dꢀinterruptꢀisꢀusedꢀtoꢀ
determineꢀwhenꢀtheꢀconversionꢀisꢀcomplete.
Example: using an EOCB polling method to detect the end of conversion
clr ADE
; disable ADC interrupt
mov a,03H
movꢀ ADCR1,aꢀꢀ
clrꢀ ADOFF
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀselectꢀfSYS/8ꢀasꢀA/Dꢀclockꢀandꢀswitchꢀoffꢀ1.25V
;ꢀsetupꢀPHS0ꢀtoꢀconfigureꢀpinꢀAN0
movꢀ a,03hꢀ
movꢀ PHS0,a
mov a,00h
ꢀ
movꢀ ADCR0,aꢀꢀ
ꢀ
ꢀ
;ꢀenableꢀandꢀconnectꢀAN0ꢀchannelꢀtoꢀA/Dꢀconverter
:
start_conversion:
clrꢀ STARTꢀ ꢀ
setꢀ STARTꢀ ꢀ
clrꢀ STARTꢀ ꢀ
polling_EOC:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀhighꢀpulseꢀonꢀstartꢀbitꢀtoꢀinitiateꢀconversion
;ꢀresetꢀA/D
;ꢀstartꢀA/D
szꢀ EOCBꢀ
jmpꢀ polling_EOCꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀpollꢀtheꢀADCR0ꢀregisterꢀEOCBꢀbitꢀtoꢀdetectꢀendꢀofꢀA/Dꢀconversion
;ꢀcontinueꢀpolling
movꢀ a,ADRLꢀꢀ
ꢀ
ꢀ
;ꢀreadꢀlowꢀbyteꢀconversionꢀresultꢀvalue
movꢀ ADRL_buffer,aꢀꢀ ;ꢀsaveꢀresultꢀtoꢀuserꢀdefinedꢀregister
movꢀ a,ADRHꢀꢀ ;ꢀreadꢀhighꢀbyteꢀconversionꢀresultꢀvalue
ꢀ
ꢀ
movꢀ ADRH_buffer,aꢀꢀ ;ꢀsaveꢀresultꢀtoꢀuserꢀdefinedꢀregister
:
:
jmpꢀ start_conversionꢀ ;ꢀstartꢀnextꢀa/dꢀconversion
Rev. 1.00
157
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Example: using the interrupt method to detect the end of conversion
clr ADE
; disable ADC interrupt
mov a,03H
movꢀ ADCR1,aꢀꢀ
clrꢀ ADOFF
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀselectꢀfSYS/8ꢀasꢀA/Dꢀclockꢀandꢀswitchꢀoffꢀ1.25V
;ꢀsetupꢀPHS0ꢀtoꢀconfigureꢀpinꢀAN0
movꢀ a,03hꢀ
movꢀ PHS0,a
mov a,00h
ꢀ
movꢀ ADCR0,aꢀꢀ
ꢀ
ꢀ
;ꢀenableꢀandꢀconnectꢀAN0ꢀchannelꢀtoꢀA/Dꢀconverter
Start_conversion:
clrꢀ STARTꢀ ꢀ
setꢀ STARTꢀ ꢀ
clrꢀ STARTꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
;ꢀhighꢀpulseꢀonꢀSTARTꢀbitꢀtoꢀinitiateꢀconversion
;ꢀresetꢀA/D
;ꢀstartꢀA/D
;ꢀclearꢀADCꢀinterruptꢀrequestꢀflag
; enable ADC interrupt
clrꢀ ADFꢀꢀ
ꢀ
set ADE
setꢀ EMIꢀꢀ
ꢀ
ꢀ
ꢀ
;ꢀenableꢀglobalꢀinterrupt
:
:
; ADC interrupt service routine
ADC_ISR:
movꢀ acc_stack,aꢀ
movꢀ a,STATUS
ꢀ
;ꢀsaveꢀACCꢀtoꢀuserꢀdefinedꢀmemory
movꢀ status_stack,aꢀꢀ ;ꢀsaveꢀSTATUSꢀtoꢀuserꢀdefinedꢀmemory
:
:
movꢀ a,ADRLꢀꢀ
movꢀ adrl_buffer,aꢀ ꢀ ;ꢀsaveꢀresultꢀtoꢀuserꢀdefinedꢀregister
movꢀ a,ADRHꢀꢀ ;ꢀreadꢀhighꢀbyteꢀconversionꢀresultꢀvalue
ꢀ
ꢀ
;ꢀreadꢀlowꢀbyteꢀconversionꢀresultꢀvalue
ꢀ
ꢀ
movꢀ adrh_buffer,aꢀ ꢀ ;ꢀsaveꢀresultꢀtoꢀuserꢀdefinedꢀregister
:
:
EXIT_INT_ISR:
movꢀ a,status_stack
movꢀ STATUS,aꢀ
movꢀ a,acc_stackꢀ
ꢀ
ꢀ
ꢀ
;ꢀrestoreꢀSTATUSꢀfromꢀuserꢀdefinedꢀmemory
;ꢀrestoreꢀACCꢀfromꢀuserꢀdefinedꢀmemory
reti
Rev. 1.00
158
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Comparators
Twoꢀindependentꢀanalogꢀcomparatorsꢀareꢀcontainedꢀwithinꢀtheseꢀdevices.ꢀTheseꢀfunctionsꢀofferꢀ
flexibilityꢀviaꢀtheirꢀregisterꢀcontrolledꢀfeaturesꢀsuchꢀasꢀpower-down,ꢀpolarityꢀselect,ꢀhysteresisꢀetc.ꢀ
InꢀsharingꢀtheirꢀpinsꢀwithꢀnormalꢀI/OꢀpinsꢀtheꢀcomparatorsꢀdoꢀnotꢀwasteꢀpreciousꢀI/Oꢀpinsꢀifꢀthereꢀ
functionsꢀareꢀotherwiseꢀunused.
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Comparator
Comparator Operation
Theꢀdevicesꢀcontainꢀtwoꢀcomparatorꢀfunctionsꢀwhichꢀareꢀusedꢀtoꢀcompareꢀtwoꢀanalogꢀvoltagesꢀ
andꢀprovideꢀanꢀoutputꢀbasedꢀonꢀtheirꢀdifference.ꢀFullꢀcontrolꢀoverꢀtheꢀtwoꢀinternalꢀcomparatorsꢀ
isꢀprovidedꢀviaꢀtwoꢀcontrolꢀregisters,ꢀCP0CꢀandꢀCP1C,ꢀoneꢀassignedꢀtoꢀeachꢀcomparator.ꢀTheꢀ
comparatorꢀoutputꢀisꢀrecordedꢀviaꢀaꢀbitꢀinꢀtheirꢀrespectiveꢀcontrolꢀregister,ꢀbutꢀcanꢀalsoꢀbeꢀtransferredꢀ
outꢀontoꢀaꢀsharedꢀI/Oꢀpin.ꢀAdditionalꢀcomparatorꢀfunctionsꢀinclude,ꢀoutputꢀpolarity,ꢀhysteresisꢀ
functionsꢀandꢀpowerꢀdownꢀcontrol.
Anyꢀpull-highꢀresistorsꢀconnectedꢀtoꢀtheꢀsharedꢀcomparatorꢀinputꢀpinsꢀwillꢀbeꢀautomaticallyꢀ
disconnectedꢀwhenꢀtheꢀcomparatorꢀisꢀenabled.ꢀAsꢀtheꢀcomparatorꢀinputsꢀapproachꢀtheirꢀswitchingꢀ
level,ꢀsomeꢀspuriousꢀoutputꢀsignalsꢀmayꢀbeꢀgeneratedꢀonꢀtheꢀcomparatorꢀoutputꢀdueꢀtoꢀtheꢀslowꢀ
risingꢀorꢀfallingꢀnatureꢀofꢀtheꢀinputꢀsignals.ꢀThisꢀcanꢀbeꢀminimisedꢀbyꢀselectingꢀtheꢀhysteresisꢀ
functionꢀwillꢀapplyꢀaꢀsmallꢀamountꢀofꢀpositiveꢀfeedbackꢀtoꢀtheꢀcomparator.ꢀIdeallyꢀtheꢀcomparatorꢀ
shouldꢀswitchꢀatꢀtheꢀpointꢀwhereꢀtheꢀpositiveꢀandꢀnegativeꢀinputsꢀsignalsꢀareꢀatꢀtheꢀsameꢀvoltageꢀ
level,ꢀhowever,ꢀunavoidableꢀinputꢀoffsetsꢀintroduceꢀsomeꢀuncertaintiesꢀhere.ꢀTheꢀhysteresisꢀfunction,ꢀ
ifꢀenabled,ꢀalsoꢀincreasesꢀtheꢀswitchingꢀoffsetꢀvalue.
Rev. 1.00
159
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Comparator Registers
Thereꢀareꢀtwoꢀregistersꢀforꢀoverallꢀcomparatorꢀoperation,ꢀoneꢀforꢀeachꢀcomparator.ꢀAsꢀcorrespondingꢀ
bitsꢀinꢀtheꢀtwoꢀregistersꢀhaveꢀidenticalꢀfunctions,ꢀtheyꢀfollowingꢀregisterꢀtableꢀappliesꢀtoꢀbothꢀ
registers.
Bit
Register
Name
7
6
5
4
3
2
1
0
CP0C
CP1C
—
—
C0EN
C1EN
C0POL
C1POL
C0OUT
C1OUT
—
—
—
—
—
—
C0HYEN
C1HYEN
Comparator Registers List
CP0C Register
Bit
Name
R/W
7
6
C0EN
R/W
0
5
C0POL
R/W
0
4
3
2
1
0
C0HYEN
R/W
—
—
—
C0OUT
—
—
—
—
—
—
—
—
—
R
0
POR
1
Bitꢀ7ꢀ
Bitꢀ6
Unimplemented,ꢀreadꢀasꢀ"0"
C0EN:ꢀComparatorꢀOn/Offꢀcontrol
0:ꢀOff
1:ꢀOn
ThisꢀisꢀtheꢀComparatorꢀon/offꢀcontrolꢀbit.ꢀIfꢀtheꢀbitꢀisꢀzeroꢀtheꢀcomparatorꢀwillꢀbeꢀ
switchedꢀoffꢀandꢀnoꢀpowerꢀconsumedꢀevenꢀifꢀanalogꢀvoltagesꢀareꢀappliedꢀtoꢀitsꢀinputs.ꢀ
Forꢀpowerꢀsensitiveꢀapplicationsꢀthisꢀbitꢀshouldꢀbeꢀclearedꢀtoꢀzeroꢀifꢀtheꢀcomparatorꢀisꢀ
notꢀusedꢀorꢀbeforeꢀtheꢀdevicesꢀenterꢀtheꢀSLEEPꢀorꢀIDLEꢀmode.
Bitꢀ5
Bitꢀ4
C0POL:ꢀComparatorꢀoutputꢀpolarity
0:ꢀOutputꢀnotꢀinverted
1:ꢀOutputꢀinverted
Thisꢀisꢀtheꢀcomparatorꢀpolarityꢀbit.ꢀIfꢀtheꢀbitꢀisꢀzeroꢀthenꢀtheꢀC0OUTꢀbitꢀwillꢀreflectꢀ
theꢀnon-invertedꢀoutputꢀconditionꢀofꢀtheꢀcomparator.ꢀIfꢀtheꢀbitꢀisꢀhighꢀtheꢀcomparatorꢀ
C0OUTꢀbitꢀwillꢀbeꢀinverted.
C0OUT:ꢀComparatorꢀoutputꢀbit
C0POL=0
0:ꢀC0+ꢀ<ꢀC0-
1:ꢀC0+ꢀ>ꢀC0-
C0POL=1
0:ꢀC0+ꢀ>ꢀC0-
1:ꢀC0+ꢀ<ꢀC0-
Thisꢀbitꢀstoresꢀtheꢀcomparatorꢀoutputꢀbit.ꢀTheꢀpolarityꢀofꢀtheꢀbitꢀisꢀdeterminedꢀbyꢀtheꢀ
voltagesꢀonꢀtheꢀcomparatorꢀinputsꢀandꢀbyꢀtheꢀconditionꢀofꢀtheꢀC0POLꢀbit.
Bitꢀ3~1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ"0"ꢀ
C0HYEN:ꢀHysteresisꢀControl
0:ꢀOff
1:ꢀOn
Thisꢀisꢀtheꢀhysteresisꢀcontrolꢀbitꢀandꢀifꢀsetꢀhighꢀwillꢀapplyꢀaꢀlimitedꢀamountꢀofꢀ
hysteresisꢀtoꢀtheꢀcomparator,ꢀasꢀspecifiedꢀinꢀtheꢀComparatorꢀElectricalꢀCharacteristicsꢀ
table.ꢀTheꢀpositiveꢀfeedbackꢀinducedꢀbyꢀhysteresisꢀreducesꢀtheꢀeffectꢀofꢀspuriousꢀ
switchingꢀnearꢀtheꢀcomparatorꢀthreshold.
Rev. 1.00
160
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
CP1C Register
Bit
Name
R/W
7
6
C1EN
R/W
0
5
C1POL
R/W
0
4
3
2
1
0
C1HYEN
R/W
—
—
—
C1OUT
—
—
—
—
—
—
—
—
—
R
0
POR
1
Bitꢀ7ꢀ
Unimplemented,ꢀreadꢀasꢀ"0"
Bitꢀ6
C1EN:ꢀComparatorꢀOn/Offꢀcontrol
0:ꢀOff
1:ꢀOn
ThisꢀisꢀtheꢀComparatorꢀon/offꢀcontrolꢀbit.ꢀIfꢀtheꢀbitꢀisꢀzeroꢀtheꢀcomparatorꢀwillꢀbeꢀ
switchedꢀoffꢀandꢀnoꢀpowerꢀconsumedꢀevenꢀifꢀanalogꢀvoltagesꢀareꢀappliedꢀtoꢀitsꢀinputs.ꢀ
Forꢀpowerꢀsensitiveꢀapplicationsꢀthisꢀbitꢀshouldꢀbeꢀclearedꢀtoꢀzeroꢀifꢀtheꢀcomparatorꢀisꢀ
notꢀusedꢀorꢀbeforeꢀtheꢀdevicesꢀenterꢀtheꢀSLEEPꢀorꢀIDLEꢀmode.
Bitꢀ5
Bitꢀ4
C1POL:ꢀComparatorꢀoutputꢀpolarity
0:ꢀOutputꢀnotꢀinverted
1:ꢀOutputꢀinverted
Thisꢀisꢀtheꢀcomparatorꢀpolarityꢀbit.ꢀIfꢀtheꢀbitꢀisꢀzeroꢀthenꢀtheꢀC1OUTꢀbitꢀwillꢀreflectꢀ
theꢀnon-invertedꢀoutputꢀconditionꢀofꢀtheꢀcomparator.ꢀIfꢀtheꢀbitꢀisꢀhighꢀtheꢀcomparatorꢀ
C1OUTꢀbitꢀwillꢀbeꢀinverted.
C1OUT:ꢀComparatorꢀoutputꢀbit
C1POL=0
0:ꢀC1+ꢀ<ꢀC1-
1:ꢀC1+ꢀ>ꢀC1-
C1POL=1
0:ꢀC1+ꢀ>ꢀC1-
1:ꢀC1+ꢀ<ꢀC1-
Thisꢀbitꢀstoresꢀtheꢀcomparatorꢀoutputꢀbit.ꢀTheꢀpolarityꢀofꢀtheꢀbitꢀisꢀdeterminedꢀbyꢀtheꢀ
voltagesꢀonꢀtheꢀcomparatorꢀinputsꢀandꢀbyꢀtheꢀconditionꢀofꢀtheꢀC1POLꢀbit.
Bitꢀ3~1ꢀ
Bitꢀ0
Unimplemented,ꢀreadꢀasꢀ"0"ꢀ
C1HYEN:ꢀHysteresisꢀControl
0:ꢀOff
1:ꢀOn
Thisꢀisꢀtheꢀhysteresisꢀcontrolꢀbitꢀandꢀifꢀsetꢀhighꢀwillꢀapplyꢀaꢀlimitedꢀamountꢀofꢀ
hysteresisꢀtoꢀtheꢀcomparator,ꢀasꢀspecifiedꢀinꢀtheꢀComparatorꢀElectricalꢀCharacteristicsꢀ
table.ꢀTheꢀpositiveꢀfeedbackꢀinducedꢀbyꢀhysteresisꢀreducesꢀtheꢀeffectꢀofꢀspuriousꢀ
switchingꢀnearꢀtheꢀcomparatorꢀthreshold.
Rev. 1.00
161
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Comparator Interrupt
Eachꢀalsoꢀpossessesꢀitsꢀownꢀinterruptꢀfunction.ꢀWhenꢀanyꢀoneꢀofꢀtheꢀchangesꢀstate,ꢀitsꢀrelevantꢀ
interruptꢀflagꢀwillꢀbeꢀset,ꢀandꢀifꢀtheꢀcorrespondingꢀinterruptꢀenableꢀbitꢀisꢀset,ꢀthenꢀaꢀjumpꢀtoꢀitsꢀ
relevantꢀinterruptꢀvectorꢀwillꢀbeꢀexecuted.ꢀNoteꢀthatꢀitꢀisꢀtheꢀchangingꢀstateꢀofꢀtheꢀC0OUTꢀorꢀC1OUTꢀ
bitꢀandꢀnotꢀtheꢀoutputꢀpinꢀwhichꢀgeneratesꢀanꢀinterrupt.ꢀIfꢀtheꢀmicrocontrollerꢀisꢀinꢀtheꢀSLEEPꢀorꢀ
IDLEꢀModeꢀandꢀtheꢀComparatorꢀisꢀenabled,ꢀthenꢀifꢀtheꢀexternalꢀinputꢀlinesꢀcauseꢀtheꢀComparatorꢀ
outputꢀtoꢀchangeꢀstate,ꢀtheꢀresultingꢀgeneratedꢀinterruptꢀflagꢀwillꢀalsoꢀgenerateꢀaꢀwake-up.ꢀIfꢀitꢀisꢀ
requiredꢀtoꢀdisableꢀaꢀwake-upꢀfromꢀoccurring,ꢀthenꢀtheꢀinterruptꢀflagꢀshouldꢀbeꢀfirstꢀsetꢀhighꢀbeforeꢀ
enteringꢀtheꢀSLEEPꢀorꢀIDLEꢀMode.
Programming Considerations
Ifꢀtheꢀcomparatorꢀisꢀenabled,ꢀitꢀwillꢀremainꢀactiveꢀwhenꢀtheꢀmicrocontrollerꢀentersꢀtheꢀSLEEPꢀorꢀ
IDLEꢀMode,ꢀhoweverꢀasꢀitꢀwillꢀconsumeꢀaꢀcertainꢀamountꢀofꢀpower,ꢀtheꢀuserꢀmayꢀwishꢀtoꢀconsiderꢀ
disablingꢀitꢀbeforeꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀentered.
AsꢀcomparatorꢀpinsꢀareꢀsharedꢀwithꢀnormalꢀI/OꢀpinsꢀtheꢀI/Oꢀregistersꢀforꢀtheseꢀpinsꢀwillꢀbeꢀreadꢀasꢀ
zeroꢀ(portꢀcontrolꢀregisterꢀisꢀ"1")ꢀorꢀreadꢀasꢀportꢀdataꢀregisterꢀvalueꢀ(portꢀcontrolꢀregisterꢀisꢀ"0")ꢀifꢀtheꢀ
comparatorꢀfunctionꢀisꢀenabled.
Serial Interface Module – SIM
TheseꢀdevicesꢀcontainꢀaꢀSerialꢀInterfaceꢀModule,ꢀwhichꢀincludesꢀbothꢀtheꢀfour-lineꢀSPIꢀinterfaceꢀorꢀ
two-lineꢀI2Cꢀinterfaceꢀtypes,ꢀtoꢀallowꢀanꢀeasyꢀmethodꢀofꢀcommunicationꢀwithꢀexternalꢀperipheralꢀ
hardware.ꢀHavingꢀrelativelyꢀsimpleꢀcommunicationꢀprotocols,ꢀtheseꢀserialꢀinterfaceꢀtypesꢀallowꢀ
theꢀmicrocontrollerꢀtoꢀinterfaceꢀtoꢀexternalꢀSPIꢀorꢀI2Cꢀbasedꢀhardwareꢀsuchꢀasꢀsensors,ꢀFlashꢀorꢀ
EEPROMꢀmemory,ꢀetc.ꢀTheꢀSIMꢀinterfaceꢀpinsꢀareꢀpin-sharedꢀwithꢀotherꢀI/Oꢀpinsꢀandꢀthereforeꢀtheꢀ
SIMꢀinterfaceꢀfunctionalꢀpinsꢀmustꢀfirstꢀbeꢀselectedꢀusingꢀtheꢀcorrespondingꢀpin-sharedꢀfunctionꢀ
selectionꢀbits.ꢀAsꢀbothꢀinterfaceꢀtypesꢀshareꢀtheꢀsameꢀpinsꢀandꢀregisters,ꢀtheꢀchoiceꢀofꢀwhetherꢀtheꢀ
SPIꢀorꢀI2CꢀtypeꢀisꢀusedꢀisꢀmadeꢀusingꢀtheꢀSIMꢀoperatingꢀmodeꢀcontrolꢀbits,ꢀnamedꢀSIM2~SIM0,ꢀ
inꢀtheꢀSIMC0ꢀregister.ꢀTheseꢀpull-highꢀresistorsꢀofꢀtheꢀSIMꢀpin-sharedꢀI/Oꢀpinsꢀareꢀselectedꢀusingꢀ
pull-highꢀcontrolꢀregistersꢀwhenꢀtheꢀSIMꢀfunctionꢀisꢀenabledꢀandꢀtheꢀcorrespondingꢀpinsꢀareꢀusedꢀasꢀ
SIMꢀinputꢀpins.
SPI Interface
TheꢀSPIꢀinterfaceꢀisꢀoftenꢀusedꢀtoꢀcommunicateꢀwithꢀexternalꢀperipheralꢀdevicesꢀsuchꢀasꢀsensors,ꢀ
FlashꢀorꢀEEPROMꢀmemoryꢀdevicesꢀetc.ꢀOriginallyꢀdevelopedꢀbyꢀMotorola,ꢀtheꢀfourꢀlineꢀSPIꢀ
interfaceꢀisꢀaꢀsynchronousꢀserialꢀdataꢀinterfaceꢀthatꢀhasꢀaꢀrelativelyꢀsimpleꢀcommunicationꢀprotocolꢀ
simplifyingꢀtheꢀprogrammingꢀrequirementsꢀwhenꢀcommunicatingꢀwithꢀexternalꢀhardwareꢀdevices.
Theꢀcommunicationꢀisꢀfullꢀduplexꢀandꢀoperatesꢀasꢀaꢀslave/masterꢀtype,ꢀwhereꢀtheꢀdevicesꢀcanꢀbeꢀ
eitherꢀmasterꢀorꢀslave.ꢀAlthoughꢀtheꢀSPIꢀinterfaceꢀspecificationꢀcanꢀcontrolꢀmultipleꢀslaveꢀdevicesꢀ
fromꢀaꢀsingleꢀmaster,ꢀbutꢀtheseꢀdevicesꢀprovidedꢀonlyꢀoneꢀSCSꢀpin.ꢀIfꢀtheꢀmasterꢀneedsꢀtoꢀcontrolꢀ
multipleꢀslaveꢀdevicesꢀfromꢀaꢀsingleꢀmaster,ꢀtheꢀmasterꢀcanꢀuseꢀI/Oꢀpinꢀtoꢀselectꢀtheꢀslaveꢀdevices.
Rev. 1.00
16ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SPI Interface Operation
TheꢀSPIꢀinterfaceꢀisꢀaꢀfullꢀduplexꢀsynchronousꢀserialꢀdataꢀlink.ꢀItꢀisꢀaꢀfourꢀlineꢀinterfaceꢀwithꢀpinꢀ
namesꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCSꢀPinsꢀSDIꢀandꢀSDOꢀareꢀtheꢀSerialꢀDataꢀInputꢀandꢀSerialꢀDataꢀOutputꢀ
lines,ꢀSCKꢀisꢀtheꢀSerialꢀClockꢀlineꢀandꢀSCSꢀisꢀtheꢀSlaveꢀSelectꢀline.ꢀAsꢀtheꢀSPIꢀinterfaceꢀpinsꢀareꢀ
pin-sharedꢀwithꢀnormalꢀI/OꢀpinsꢀandꢀwithꢀtheꢀI2Cꢀfunctionꢀpins,ꢀtheꢀSPIꢀinterfaceꢀpinsꢀmustꢀfirstꢀ
beꢀselectedꢀbyꢀconfiguringꢀtheꢀpin-sharedꢀfunctionꢀselectionꢀbitsꢀandꢀsettingꢀtheꢀcorrectꢀbitsꢀinꢀtheꢀ
SIMC0ꢀandꢀSIMC2ꢀregisters.ꢀAfterꢀtheꢀdesiredꢀSPIꢀconfigurationꢀhasꢀbeenꢀsetꢀitꢀcanꢀbeꢀdisabledꢀorꢀ
enabledꢀusingꢀtheꢀSIMENꢀbitꢀinꢀtheꢀSIMC0ꢀregister.ꢀCommunicationꢀbetweenꢀdevicesꢀconnectedꢀ
toꢀtheꢀSPIꢀinterfaceꢀisꢀcarriedꢀoutꢀinꢀaꢀslave/masterꢀmodeꢀwithꢀallꢀdataꢀtransferꢀinitiationsꢀbeingꢀ
implementedꢀbyꢀtheꢀmaster.ꢀTheꢀMasterꢀalsoꢀcontrolsꢀtheꢀclockꢀsignal.ꢀAsꢀtheꢀdeviceꢀonlyꢀcontainsꢀ
aꢀsingleꢀSCSꢀpinꢀonlyꢀoneꢀslaveꢀdeviceꢀcanꢀbeꢀutilized.ꢀTheꢀSCSꢀpinꢀisꢀcontrolledꢀbyꢀsoftware,ꢀsetꢀ
CSENꢀbitꢀtoꢀ1ꢀtoꢀenableꢀSCSꢀpinꢀfunction,ꢀsetꢀCSENꢀbitꢀtoꢀ0ꢀtheꢀSCSꢀpinꢀwillꢀbeꢀfloatingꢀstate.
TheꢀSPIꢀfunctionꢀinꢀthisꢀdeviceꢀoffersꢀtheꢀfollowingꢀfeatures:
•ꢀ Fullꢀduplexꢀsynchronousꢀdataꢀtransfer
•ꢀ BothꢀMasterꢀandꢀSlaveꢀmodes
•ꢀ LSBꢀfirstꢀorꢀMSBꢀfirstꢀdataꢀtransmissionꢀmodes
•ꢀ Transmissionꢀcompleteꢀflag
•ꢀ Risingꢀorꢀfallingꢀactiveꢀclockꢀedge
TheꢀstatusꢀofꢀtheꢀSPIꢀinterfaceꢀpinsꢀisꢀdeterminedꢀbyꢀaꢀnumberꢀofꢀfactorsꢀsuchꢀasꢀwhetherꢀtheꢀdeviceꢀ
isꢀinꢀtheꢀmasterꢀorꢀslaveꢀmodeꢀandꢀuponꢀtheꢀconditionꢀofꢀcertainꢀcontrolꢀbitsꢀsuchꢀasꢀCSENꢀandꢀ
SIMEN.
S
I
P
a
M
s
e
t
r
S
I
P
S
a
l
e
v
S
K
C
S
S
S
S
K
I
O
S
C
D
D
C
S
O
D
S
I
D
S
S
C
SPI Master/Slave Connection
D
t
a
a
B
u
s
S
M
I
D
S
I
D
P
n
i
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/
x
x
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SPI Bolck Diagram
Rev. 1.00
16ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SPI Registers
ThereꢀareꢀthreeꢀinternalꢀregistersꢀwhichꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀSPIꢀinterface.ꢀTheseꢀareꢀ
theꢀSIMDꢀdataꢀregisterꢀandꢀtwoꢀregistersꢀSIMC0ꢀandꢀSIMC2.ꢀNoteꢀthatꢀtheꢀSIMC1ꢀregisterꢀisꢀonlyꢀ
usedꢀbyꢀtheꢀI2Cꢀinterface.
Bit
Register
Name
7
SI�ꢃ
D7
6
SI�1
D6
5
4
3
2
1
0
—
SI�C0
SI�D
SI�0
D5
—
D4
SI�DEB1 SI�DEB0 SI�EN
Dꢅ
Dꢃ
D1
D0
TRF
SI�Cꢃ
D7
D6
CKPOLB CKEG
�LS
CSEN
WCOL
SIM Registers List
TheꢀSIMDꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceived.ꢀTheꢀsameꢀregisterꢀisꢀusedꢀ
byꢀbothꢀtheꢀSPIꢀandꢀI2Cꢀfunctions.ꢀBeforeꢀtheꢀdevicesꢀwriteꢀdataꢀtoꢀtheꢀSPIꢀbus,ꢀtheꢀactualꢀdataꢀtoꢀ
beꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSIMDꢀregister.ꢀAfterꢀtheꢀdataꢀisꢀreceivedꢀfromꢀtheꢀSPIꢀbus,ꢀtheꢀ
devicesꢀcanꢀreadꢀitꢀfromꢀtheꢀSIMDꢀregister.ꢀAnyꢀtransmissionꢀorꢀreceptionꢀofꢀdataꢀfromꢀtheꢀSPIꢀbusꢀ
mustꢀbeꢀmadeꢀviaꢀtheꢀSIMDꢀregister.
SIMD Register
Bit
7
D7
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
D4
R/W
x
3
Dꢅ
R/W
x
2
Dꢃ
R/W
x
1
D1
R/W
x
0
Name
R/W
D0
R/W
x
POR
“x”: unknown
ThereꢀareꢀalsoꢀtwoꢀcontrolꢀregistersꢀforꢀtheꢀSPIꢀinterface,ꢀSIMC0ꢀandꢀSIMC2.ꢀNoteꢀthatꢀtheꢀSIMC2ꢀ
registerꢀalsoꢀhasꢀtheꢀnameꢀSIMAꢀwhichꢀisꢀusedꢀbyꢀtheꢀI2Cꢀfunction.ꢀTheꢀSIMC1ꢀregisterꢀisꢀnotꢀusedꢀ
byꢀtheꢀSPIꢀfunction,ꢀonlyꢀbyꢀtheꢀI2Cꢀfunction.ꢀRegisterꢀSIMC0ꢀisꢀusedꢀtoꢀcontrolꢀtheꢀenable/disableꢀ
functionꢀandꢀtoꢀsetꢀtheꢀdataꢀtransmissionꢀclockꢀfrequency.ꢀAlthoughꢀnotꢀconnectedꢀwithꢀtheꢀSPIꢀ
function,ꢀtheꢀSIMC0ꢀregisterꢀisꢀalsoꢀusedꢀtoꢀcontrolꢀtheꢀPeripheralꢀClockꢀPrescaler.ꢀRegisterꢀSIMC2ꢀ
isꢀusedꢀforꢀotherꢀcontrolꢀfunctionsꢀsuchꢀasꢀLSB/MSBꢀselection,ꢀwriteꢀcollisionꢀflagꢀetc.
Rev. 1.00
164
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SIMC0 Register
Bit
Name
R/W
7
SI�ꢃ
R/W
1
6
SI�1
R/W
1
5
SI�0
R/W
1
4
3
2
1
0
—
—
—
SI�DEB1 SI�DEB0 SI�EN
—
—
—
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~5
SIM2, SIM1, SIM0: SIMꢀOperatingꢀModeꢀControl
000:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/4
001:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/16
010:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/64
011:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSUB
100:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀTM0ꢀCCRPꢀmatchꢀfrequency/2
101:ꢀSPIꢀslaveꢀmode
110:ꢀI2Cꢀslaveꢀmode
111:ꢀNonꢀSIMꢀfunction
TheseꢀbitsꢀsetupꢀtheꢀoverallꢀoperatingꢀmodeꢀofꢀtheꢀSIMꢀfunction.ꢀAsꢀwellꢀasꢀselectingꢀ
ifꢀtheꢀI2CꢀorꢀSPIꢀfunction,ꢀtheyꢀareꢀusedꢀtoꢀcontrolꢀtheꢀSPIꢀMaster/Slaveꢀselectionꢀandꢀ
theꢀSPIꢀMasterꢀclockꢀfrequency.ꢀTheꢀSPIꢀclockꢀisꢀaꢀfunctionꢀofꢀtheꢀsystemꢀclockꢀbutꢀ
canꢀalsoꢀbeꢀchosenꢀtoꢀbeꢀsourcedꢀfromꢀTM0.ꢀIfꢀtheꢀSPIꢀSlaveꢀModeꢀisꢀselectedꢀthenꢀtheꢀ
clockꢀwillꢀbeꢀsuppliedꢀbyꢀanꢀexternalꢀMasterꢀdevices.
Bitꢀ4ꢀ
Unimplemented,ꢀreadꢀasꢀ"0"
Bitꢀ3~2
SIMDEB1~SIMDEB0:ꢀI2CꢀDebounceꢀTimeꢀSelection
00:ꢀNoꢀdebounce
01:ꢀ2ꢀsystemꢀclockꢀdebounce
1x:ꢀ4ꢀsystemꢀclockꢀdebounce
Bitꢀ1
SIMEN:ꢀSIMꢀControl
0:ꢀDisable
1:ꢀEnable
Theꢀbitꢀisꢀtheꢀoverallꢀon/offꢀcontrolꢀforꢀtheꢀSIMꢀinterface.ꢀWhenꢀtheꢀSIMENꢀbitꢀisꢀ
clearedꢀtoꢀzeroꢀtoꢀdisableꢀtheꢀSIMꢀinterface,ꢀtheꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCS,ꢀorꢀSDAꢀandꢀ
SCLꢀlinesꢀwillꢀloseꢀtheirꢀSPIꢀorꢀI2CꢀfunctionꢀandꢀtheꢀSIMꢀoperatingꢀcurrentꢀwillꢀbeꢀ
reducedꢀtoꢀaꢀminimumꢀvalue.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀSIMꢀinterfaceꢀisꢀenabled.ꢀTheꢀ
SIMꢀconfigurationꢀoptionꢀmustꢀhaveꢀfirstꢀenabledꢀtheꢀSIMꢀinterfaceꢀforꢀthisꢀbitꢀtoꢀbeꢀ
effective.IfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀSPIꢀinterfaceꢀviaꢀtheꢀSIM2~SIM0ꢀ
bits,ꢀtheꢀcontentsꢀofꢀtheꢀSPIꢀcontrolꢀregistersꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀwhenꢀ
theꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀshouldꢀthereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀ
theꢀapplicationꢀprogram.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀI2Cꢀinterfaceꢀviaꢀtheꢀ
SIM2~SIM0ꢀbitsꢀandꢀtheꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀtheꢀcontentsꢀofꢀtheꢀI2Cꢀ
controlꢀbitsꢀsuchꢀasꢀHTXꢀandꢀTXAKꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀandꢀshouldꢀ
thereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀtheꢀapplicationꢀprogramꢀwhileꢀtheꢀrelevantꢀI2Cꢀflagsꢀ
suchꢀasꢀHCF,ꢀHAAS,ꢀHBB,ꢀSRWꢀandꢀRXAKꢀwillꢀbeꢀsetꢀtoꢀtheirꢀdefaultꢀstates.
Bitꢀ0ꢀ
Unimplemented,ꢀreadꢀasꢀ"0"
Rev. 1.00
165
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SIMC2 Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
CKPOLB
R/W
4
CKEG
R/W
0
3
2
CSEN
R/W
0
1
WCOL
R/W
0
0
�LS
R/W
0
TRF
R/W
0
POR
0
Bitꢀ7~6ꢀ
Bitꢀ5
Undefinedꢀbit
Thisꢀbitꢀcanꢀbeꢀreadꢀorꢀwrittenꢀbyꢀtheꢀapplicationꢀprogram.
CKPOLB:ꢀDeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline
0:ꢀTheꢀSCKꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive
1:ꢀTheꢀSCKꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive
TheꢀCKPOLBꢀbitꢀdeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀ
thenꢀtheꢀSCKꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀCKPOLBꢀbitꢀisꢀ
low,ꢀthenꢀtheꢀSCKꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.
Bitꢀ4
CKEG:ꢀDeterminesꢀSPIꢀSCKꢀactiveꢀclockꢀedgeꢀtype
CKPOLB=0
0:ꢀSCKꢀisꢀhighꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀrisingꢀedge
1:ꢀSCKꢀisꢀhighꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀfallingꢀedge
CKPOLB=1
0:ꢀSCKꢀisꢀlowꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀfallingꢀedge
1:ꢀSCKꢀisꢀlowꢀbaseꢀlevelꢀandꢀdataꢀcaptureꢀatꢀSCKꢀrisingꢀedge
TheꢀCKEGꢀandꢀCKPOLBꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀwayꢀthatꢀtheꢀclockꢀsignalꢀoutputsꢀ
andꢀinputsꢀdataꢀonꢀtheꢀSPIꢀbus.ꢀTheseꢀtwoꢀbitsꢀmustꢀbeꢀconfiguredꢀbeforeꢀdataꢀtransferꢀ
isꢀexecutedꢀotherwiseꢀanꢀerroneousꢀclockꢀedgeꢀmayꢀbeꢀgenerated.ꢀTheꢀCKPOLBꢀbitꢀ
determinesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀthenꢀtheꢀSCKꢀlineꢀ
willꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀCKPOLBꢀbitꢀisꢀlow,ꢀthenꢀtheꢀSCKꢀ
lineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀTheꢀCKEGꢀbitꢀdeterminesꢀactiveꢀclockꢀ
edgeꢀtypeꢀwhichꢀdependsꢀuponꢀtheꢀconditionꢀofꢀCKPOLBꢀbit.
Bitꢀ3
Bitꢀ2
MLS:ꢀSPIꢀDataꢀshiftꢀorder
0:ꢀLSB
1:ꢀMSB
Thisꢀisꢀtheꢀdataꢀshiftꢀselectꢀbitꢀandꢀisꢀusedꢀtoꢀselectꢀhowꢀtheꢀdataꢀisꢀtransferred,ꢀeitherꢀ
MSBꢀorꢀLSBꢀfirst.ꢀSettingꢀtheꢀbitꢀhighꢀwillꢀselectꢀMSBꢀfirstꢀandꢀlowꢀforꢀLSBꢀfirst.
CSEN:ꢀSPIꢀSCSꢀpinꢀControl
0:ꢀDisable
1:ꢀEnable
TheꢀCSENꢀbitꢀisꢀusedꢀasꢀanꢀenable/disableꢀforꢀtheꢀSCSꢀpin.ꢀIfꢀthisꢀbitꢀisꢀlow,ꢀthenꢀtheꢀ
SCSꢀpinꢀwillꢀbeꢀdisabledꢀandꢀplacedꢀintoꢀI/Oꢀpinꢀorꢀtheꢀotherꢀfunctions.ꢀIfꢀtheꢀbitꢀisꢀ
highꢀtheꢀSCSꢀpinꢀwillꢀbeꢀenabledꢀandꢀusedꢀasꢀaꢀselectꢀpin.
Bitꢀ1
Bitꢀ0
WCOL:ꢀSPIꢀWriteꢀCollisionꢀflag
0:ꢀNoꢀcollision
1:ꢀCollision
TheꢀWCOLꢀflagꢀisꢀusedꢀtoꢀdetectꢀifꢀaꢀdataꢀcollisionꢀhasꢀoccurred.ꢀIfꢀthisꢀbitꢀisꢀhighꢀitꢀ
meansꢀthatꢀdataꢀhasꢀbeenꢀattemptedꢀtoꢀbeꢀwrittenꢀtoꢀtheꢀSIMDꢀregisterꢀduringꢀaꢀdataꢀ
transferꢀoperation.ꢀThisꢀwritingꢀoperationꢀwillꢀbeꢀignoredꢀifꢀdataꢀisꢀbeingꢀtransferred.ꢀ
Theꢀbitꢀcanꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.
TRF:ꢀSPIꢀTransmit/ReceiveꢀCompleteꢀflag
0:ꢀDataꢀisꢀbeingꢀtransferred
1:ꢀSPIꢀdataꢀtransmissionꢀisꢀcompleted
TheꢀTRFꢀbitꢀisꢀtheꢀTransmit/ReceiveꢀCompleteꢀflagꢀandꢀisꢀsetꢀ“1”ꢀautomaticallyꢀwhenꢀ
anꢀSPIꢀdataꢀtransmissionꢀisꢀcompleted,ꢀbutꢀmustꢀsetꢀtoꢀ“0”ꢀbyꢀtheꢀapplicationꢀprogram.ꢀ
Itꢀcanꢀbeꢀusedꢀtoꢀgenerateꢀanꢀinterrupt.
Rev. 1.00
166
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SPI Communication
AfterꢀtheꢀSPIꢀinterfaceꢀisꢀenabledꢀbyꢀsettingꢀtheꢀSIMENꢀbitꢀhigh,ꢀthenꢀinꢀtheꢀMasterꢀMode,ꢀwhenꢀ
dataꢀisꢀwrittenꢀtoꢀtheꢀSIMDꢀregister,ꢀtransmission/receptionꢀwillꢀbeginꢀsimultaneously.ꢀWhenꢀtheꢀ
dataꢀtransferꢀisꢀcomplete,ꢀtheꢀTRFꢀflagꢀwillꢀbeꢀsetꢀautomatically,ꢀbutꢀmustꢀbeꢀclearedꢀusingꢀtheꢀ
applicationꢀprogram.ꢀInꢀtheꢀSlaveꢀMode,ꢀwhenꢀtheꢀclockꢀsignalꢀfromꢀtheꢀmasterꢀhasꢀbeenꢀreceived,ꢀ
anyꢀdataꢀinꢀtheꢀSIMDꢀregisterꢀwillꢀbeꢀtransmittedꢀandꢀanyꢀdataꢀonꢀtheꢀSDIꢀpinꢀwillꢀbeꢀshiftedꢀintoꢀ
theꢀSIMDꢀregister.ꢀTheꢀmasterꢀshouldꢀoutputꢀanꢀSCSꢀsignalꢀtoꢀenableꢀtheꢀslaveꢀdevicesꢀbeforeꢀaꢀ
clockꢀsignalꢀisꢀprovided.ꢀTheꢀslaveꢀdataꢀtoꢀbeꢀtransferredꢀshouldꢀbeꢀwellꢀpreparedꢀatꢀtheꢀappropriateꢀ
momentꢀrelativeꢀtoꢀtheꢀSCSꢀsignalꢀdependingꢀuponꢀtheꢀconfigurationsꢀofꢀtheꢀCKPOLBꢀbitꢀandꢀCKEGꢀ
bit.ꢀTheꢀaccompanyingꢀtimingꢀdiagramꢀshowsꢀtheꢀrelationshipꢀbetweenꢀtheꢀslaveꢀdataꢀandꢀSCSꢀsignalꢀ
forꢀvariousꢀconfigurationsꢀofꢀtheꢀCKPOLBꢀandꢀCKEGꢀbits.
TheꢀSPIꢀwillꢀcontinueꢀtoꢀfunctionꢀevenꢀinꢀtheꢀIDLEꢀMode.
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1
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Rev. 1.00
167
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
S
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SPI Transfer Control Flowchart
Rev. 1.00
168
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
I2C Interface
TheꢀI2Cꢀinterfaceꢀisꢀusedꢀtoꢀcommunicateꢀwithꢀexternalꢀperipheralꢀdevicesꢀsuchꢀasꢀsensors,ꢀ
EEPROMꢀmemoryꢀetc.ꢀOriginallyꢀdevelopedꢀbyꢀPhilips,ꢀitꢀisꢀaꢀtwoꢀlineꢀlowꢀspeedꢀserialꢀinterfaceꢀ
forꢀsynchronousꢀserialꢀdataꢀtransfer.ꢀTheꢀadvantageꢀofꢀonlyꢀtwoꢀlinesꢀforꢀcommunication,ꢀrelativelyꢀ
simpleꢀcommunicationꢀprotocolꢀandꢀtheꢀabilityꢀtoꢀaccommodateꢀmultipleꢀdevicesꢀonꢀtheꢀsameꢀbusꢀ
hasꢀmadeꢀitꢀanꢀextremelyꢀpopularꢀinterfaceꢀtypeꢀforꢀmanyꢀapplications.
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I2C Master Slave Bus Connection
I2C Interface Operation
TheꢀI2Cꢀserialꢀinterfaceꢀisꢀaꢀtwoꢀlineꢀinterface,ꢀaꢀserialꢀdataꢀline,ꢀSDA,ꢀandꢀserialꢀclockꢀline,ꢀSCL.ꢀAsꢀ
manyꢀdevicesꢀmayꢀbeꢀconnectedꢀtogetherꢀonꢀtheꢀsameꢀbus,ꢀtheirꢀoutputsꢀareꢀbothꢀopenꢀdrainꢀtypes.ꢀ
Forꢀthisꢀreasonꢀitꢀisꢀnecessaryꢀthatꢀexternalꢀpull-highꢀresistorsꢀareꢀconnectedꢀtoꢀtheseꢀoutputs.ꢀNoteꢀ
thatꢀnoꢀchipꢀselectꢀlineꢀexists,ꢀasꢀeachꢀdeviceꢀonꢀtheꢀI2Cꢀbusꢀisꢀidentifiedꢀbyꢀaꢀuniqueꢀaddressꢀwhichꢀ
willꢀbeꢀtransmittedꢀandꢀreceivedꢀonꢀtheꢀI2Cꢀbus.
WhenꢀtwoꢀdevicesꢀcommunicateꢀwithꢀeachꢀotherꢀonꢀtheꢀbidirectionalꢀI2Cꢀbus,ꢀoneꢀisꢀknownꢀasꢀtheꢀ
masterꢀdeviceꢀandꢀoneꢀasꢀtheꢀslaveꢀdevice.ꢀBothꢀmasterꢀandꢀslaveꢀcanꢀtransmitꢀandꢀreceiveꢀdata,ꢀ
however,ꢀitꢀisꢀtheꢀmasterꢀdeviceꢀthatꢀhasꢀoverallꢀcontrolꢀofꢀtheꢀbus.ꢀForꢀtheseꢀdevices,ꢀwhichꢀonlyꢀ
operateꢀinꢀslaveꢀmode,ꢀthereꢀareꢀtwoꢀmethodsꢀofꢀtransferringꢀdataꢀonꢀtheꢀI2Cꢀbus,ꢀtheꢀslaveꢀtransmitꢀ
modeꢀandꢀtheꢀslaveꢀreceiveꢀmode.
TheꢀSIMDEB1ꢀandꢀSIMDEB0ꢀbitsꢀdetermineꢀtheꢀdebounceꢀtimeꢀofꢀtheꢀI2Cꢀinterface.ꢀThisꢀusesꢀ
theꢀsystemꢀclockꢀtoꢀinꢀeffectꢀaddꢀaꢀdebounceꢀtimeꢀtoꢀtheꢀexternalꢀclockꢀtoꢀreduceꢀtheꢀpossibilityꢀ
ofꢀglitchesꢀonꢀtheꢀclockꢀlineꢀcausingꢀerroneousꢀoperation.ꢀTheꢀdebounceꢀtime,ꢀifꢀselected,ꢀcanꢀbeꢀ
chosenꢀtoꢀbeꢀeitherꢀ2ꢀorꢀ4ꢀsystemꢀclocks.ꢀToꢀachieveꢀtheꢀrequiredꢀI2Cꢀdataꢀtransferꢀspeed,ꢀthereꢀ
existsꢀaꢀrelationshipꢀbetweenꢀtheꢀsystemꢀclock,ꢀfSYS,ꢀandꢀtheꢀI2Cꢀdebounceꢀtime.ꢀForꢀeitherꢀtheꢀI2Cꢀ
StandardꢀorꢀFastꢀmodeꢀoperation,ꢀusersꢀmustꢀtakeꢀcareꢀofꢀtheꢀselectedꢀsystemꢀclockꢀfrequencyꢀandꢀ
theꢀconfiguredꢀdebounceꢀtimeꢀtoꢀmatchꢀtheꢀcriterionꢀshownꢀinꢀtheꢀfollowingꢀtable.
I2C Debounce Time Selection
No debounꢁe
I2C Standard Mode (100kHz)
fSYS > ꢃ�Hz
I2C Fast Mode (400kHz)
fSYS > 5�Hz
ꢃ system ꢁloꢁk debounꢁe
4 system ꢁloꢁk debounꢁe
fSYS > 4�Hz
fSYS > 10�Hz
fSYS > 8�Hz
fSYS > ꢃ0�Hz
I2C Minimum fSYS Frequency
Rev. 1.00
169
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
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I2C Registers
ThereꢀareꢀthreeꢀcontrolꢀregistersꢀassociatedꢀwithꢀtheꢀI2Cꢀbus,ꢀSIMC0,ꢀSIMC1ꢀandꢀSIMA,ꢀandꢀoneꢀ
dataꢀregister,ꢀSIMD.ꢀTheꢀSIMDꢀregister,ꢀwhichꢀisꢀshownꢀinꢀtheꢀaboveꢀSPIꢀsection,ꢀisꢀusedꢀtoꢀstoreꢀ
theꢀdataꢀbeingꢀtransmittedꢀandꢀreceivedꢀonꢀtheꢀI2Cꢀbus.ꢀBeforeꢀtheꢀmicrocontrollerꢀwritesꢀdataꢀtoꢀ
theꢀI2Cꢀbus,ꢀtheꢀactualꢀdataꢀtoꢀbeꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSIMDꢀregister.ꢀAfterꢀtheꢀdataꢀisꢀ
receivedꢀfromꢀtheꢀI2Cꢀbus,ꢀtheꢀmicrocontrollerꢀcanꢀreadꢀitꢀfromꢀtheꢀSIMDꢀregister.ꢀAnyꢀtransmissionꢀ
orꢀreceptionꢀofꢀdataꢀfromꢀtheꢀI2CꢀbusꢀmustꢀbeꢀmadeꢀviaꢀtheꢀSIMDꢀregister.
NoteꢀthatꢀtheꢀSIMAꢀregisterꢀalsoꢀhasꢀtheꢀnameꢀSIMC2ꢀwhichꢀisꢀusedꢀbyꢀtheꢀSPIꢀfunction.ꢀBitꢀSIMENꢀ
andꢀbitsꢀSIM2~SIM0ꢀinꢀregisterꢀSIMC0ꢀareꢀusedꢀbyꢀtheꢀI2Cꢀinterface.
Bit
Register
Name
7
6
5
4
—
3
2
1
0
—
SI�C0
SI�C1
SI�D
SI�ꢃ
HCF
D7
SI�1
HANS
D6
SI�0
HBB
D5
SI�DEB1 SI�DEB0 SI�EN
HTX
D4
TXAK
Dꢅ
SRW
Dꢃ
IA�WU
D1
RXAK
D0
SI�A
IICA6
IICA5
IICA4
IICAꢅ
IICAꢃ
IICA1
IICA0
D0
I2C Registers List
Rev. 1.00
170
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SIMC0 Register
Bit
Name
R/W
7
SI�ꢃ
R/W
1
6
SI�1
R/W
1
5
SI�0
R/W
1
4
3
2
1
0
—
—
—
SI�DEB1 SI�DEB0 SI�EN
—
—
—
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~5
SIM2, SIM1, SIM0: SIMꢀOperatingꢀModeꢀControl
000:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/4
001:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/16
010:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSYS/64
011:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀfSUB
100:ꢀSPIꢀmasterꢀmode;ꢀSPIꢀclockꢀisꢀTM0ꢀCCRPꢀmatchꢀfrequency/2
101:ꢀSPIꢀslaveꢀmode
110:ꢀI2Cꢀslaveꢀmode
111:ꢀUnusedꢀmode
TheseꢀbitsꢀsetupꢀtheꢀoverallꢀoperatingꢀmodeꢀofꢀtheꢀSIMꢀfunction.ꢀAsꢀwellꢀasꢀselectingꢀ
ifꢀtheꢀI2CꢀorꢀSPIꢀfunction,ꢀtheyꢀareꢀusedꢀtoꢀcontrolꢀtheꢀSPIꢀMaster/Slaveꢀselectionꢀandꢀ
theꢀSPIꢀMasterꢀclockꢀfrequency.ꢀTheꢀSPIꢀclockꢀisꢀaꢀfunctionꢀofꢀtheꢀsystemꢀclockꢀbutꢀ
canꢀalsoꢀbeꢀchosenꢀtoꢀbeꢀsourcedꢀfromꢀtheꢀTM0.ꢀIfꢀtheꢀSPIꢀSlaveꢀModeꢀisꢀselectedꢀthenꢀ
theꢀclockꢀwillꢀbeꢀsuppliedꢀbyꢀanꢀexternalꢀMasterꢀdevice.
Bitꢀ4ꢀ
Unimplemented,ꢀreadꢀasꢀ"0"
Bitꢀ3~2
SIMDEB1~SIMDEB0:ꢀI2CꢀDebounceꢀTimeꢀSelection
00:ꢀNoꢀdebounce
01:ꢀ2ꢀsystemꢀclockꢀdebounce
1x:ꢀ4ꢀsystemꢀclockꢀdebounce
Bitꢀ1
SIMEN:ꢀSIMꢀControl
0:ꢀDisable
1:ꢀEnable
Theꢀbitꢀisꢀtheꢀoverallꢀon/offꢀcontrolꢀforꢀtheꢀSIMꢀinterface.ꢀWhenꢀtheꢀSIMENꢀbitꢀisꢀ
clearedꢀtoꢀzeroꢀtoꢀdisableꢀtheꢀSIMꢀinterface,ꢀtheꢀSDI,ꢀSDO,ꢀSCKꢀandꢀSCS,ꢀorꢀSDAꢀ
andꢀSCLꢀlinesꢀwillꢀbeꢀinꢀaꢀfloatingꢀconditionꢀandꢀtheꢀSIMꢀoperatingꢀcurrentꢀwillꢀbeꢀ
reducedꢀtoꢀaꢀminimumꢀvalue.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀSIMꢀinterfaceꢀisꢀenabled.ꢀTheꢀ
SIMꢀconfigurationꢀoptionꢀmustꢀhaveꢀfirstꢀenabledꢀtheꢀSIMꢀinterfaceꢀforꢀthisꢀbitꢀtoꢀbeꢀ
effective.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀSPIꢀinterfaceꢀviaꢀSIM2~SIM0ꢀbits,ꢀ
theꢀcontentsꢀofꢀtheꢀSPIꢀcontrolꢀregistersꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀwhenꢀtheꢀ
SIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀshouldꢀthereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀtheꢀ
applicationꢀprogram.ꢀIfꢀtheꢀSIMꢀisꢀconfiguredꢀtoꢀoperateꢀasꢀanꢀI2Cꢀinterfaceꢀviaꢀtheꢀ
SIM2~SIM0ꢀbitsꢀandꢀtheꢀSIMENꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀtheꢀcontentsꢀofꢀtheꢀI2Cꢀ
controlꢀbitsꢀsuchꢀasꢀHTXꢀandꢀTXAKꢀwillꢀremainꢀatꢀtheꢀpreviousꢀsettingsꢀandꢀshouldꢀ
thereforeꢀbeꢀfirstꢀinitialisedꢀbyꢀtheꢀapplicationꢀprogramꢀwhileꢀtheꢀrelevantꢀI2Cꢀflagsꢀ
suchꢀasꢀHCF,ꢀHAAS,ꢀHBB,ꢀSRWꢀandꢀRXAKꢀwillꢀbeꢀsetꢀtoꢀtheirꢀdefaultꢀstates.
Bitꢀ0ꢀ
Unimplemented,ꢀreadꢀasꢀ"0"
Rev. 1.00
171
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SIMC1 Register
Bit
Name
R/W
7
HCF
R
6
HAAS
R
5
HBB
R
4
3
TXAK
R/W
0
2
SRW
R
1
IA�WU
R/W
0
0
RXAK
R
HTX
R/W
0
POR
1
0
0
0
1
Bitꢀ7
Bitꢀ6
Bitꢀ5
HCF:ꢀI2CꢀBusꢀdataꢀtransferꢀcompletionꢀflag
0:ꢀDataꢀisꢀbeingꢀtransferred
1:ꢀCompletionꢀofꢀanꢀ8-bitꢀdataꢀtransfer
TheꢀHCFꢀflagꢀisꢀtheꢀdataꢀtransferꢀflag.ꢀThisꢀflagꢀwillꢀbeꢀzeroꢀwhenꢀdataꢀisꢀbeingꢀ
transferred.ꢀUponꢀcompletionꢀofꢀanꢀ8-bitꢀdataꢀtransferꢀtheꢀflagꢀwillꢀgoꢀhighꢀandꢀanꢀ
interruptꢀwillꢀbeꢀgenerated.
HAAS:ꢀI2CꢀBusꢀaddressꢀmatchꢀflag
0:ꢀNotꢀaddressꢀmatch
1:ꢀAddressꢀmatch
TheꢀHAASꢀflagꢀisꢀtheꢀaddressꢀmatchꢀflag.ꢀThisꢀflagꢀisꢀusedꢀtoꢀdetermineꢀifꢀtheꢀslaveꢀ
deviceꢀaddressꢀisꢀtheꢀsameꢀasꢀtheꢀmasterꢀtransmitꢀaddress.ꢀIfꢀtheꢀaddressesꢀmatchꢀthenꢀ
thisꢀbitꢀwillꢀbeꢀhigh,ꢀifꢀthereꢀisꢀnoꢀmatchꢀthenꢀtheꢀflagꢀwillꢀbeꢀlow.
HBB:ꢀI2CꢀBusꢀbusyꢀflag
0:ꢀI2CꢀBusꢀisꢀnotꢀbusy
1:ꢀI2CꢀBusꢀisꢀbusy
TheꢀHBBꢀflagꢀisꢀtheꢀI2Cꢀbusyꢀflag.ꢀThisꢀflagꢀwillꢀbeꢀ“1”ꢀwhenꢀtheꢀI2Cꢀbusꢀisꢀbusyꢀ
whichꢀwillꢀoccurꢀwhenꢀaꢀSTARTꢀsignalꢀisꢀdetected.ꢀTheꢀflagꢀwillꢀbeꢀsetꢀtoꢀ“0”ꢀwhenꢀ
theꢀbusꢀisꢀfreeꢀwhichꢀwillꢀoccurꢀwhenꢀaꢀSTOPꢀsignalꢀisꢀdetected.
Bitꢀ4
Bitꢀ3
HTX:ꢀSelectꢀI2Cꢀslaveꢀdeviceꢀisꢀtransmitterꢀorꢀreceiver
0:ꢀSlaveꢀdeviceꢀisꢀtheꢀreceiver
1:ꢀSlaveꢀdeviceꢀisꢀtheꢀtransmitter
TXAK:ꢀI2CꢀBusꢀtransmitꢀacknowledgeꢀflag
0:ꢀSlaveꢀsendꢀacknowledgeꢀflag
1:ꢀSlaveꢀdoꢀnotꢀsendꢀacknowledgeꢀflag
TheꢀTXAKꢀbitꢀisꢀtheꢀtransmitꢀacknowledgeꢀflag.ꢀAfterꢀtheꢀslaveꢀdeviceꢀreceiptꢀofꢀ8-bitsꢀ
ofꢀdata,ꢀthisꢀbitꢀwillꢀbeꢀtransmittedꢀtoꢀtheꢀbusꢀonꢀtheꢀ9thꢀclockꢀfromꢀtheꢀslaveꢀdevice.ꢀ
TheꢀslaveꢀdeviceꢀmustꢀalwaysꢀsetꢀTXAKꢀbitꢀtoꢀ“0”ꢀbeforeꢀfurtherꢀdataꢀisꢀreceived.
Bitꢀ2
SRW:ꢀI2CꢀSlaveꢀRead/Writeꢀflag
0:ꢀSlaveꢀdeviceꢀshouldꢀbeꢀinꢀreceiveꢀmode
1:ꢀSlaveꢀdeviceꢀshouldꢀbeꢀinꢀtransmitꢀmode
TheꢀSRWꢀflagꢀisꢀtheꢀI2CꢀSlaveꢀRead/Writeꢀflag.ꢀThisꢀflagꢀdeterminesꢀwhetherꢀ
theꢀmasterꢀdeviceꢀwishesꢀtoꢀtransmitꢀorꢀreceiveꢀdataꢀfromꢀtheꢀI2Cꢀbus.ꢀWhenꢀtheꢀ
transmittedꢀaddressꢀandꢀslaveꢀaddressꢀisꢀmatch,ꢀthatꢀisꢀwhenꢀtheꢀHAASꢀflagꢀisꢀsetꢀhigh,ꢀ
theꢀslaveꢀdeviceꢀwillꢀcheckꢀtheꢀSRWꢀflagꢀtoꢀdetermineꢀwhetherꢀitꢀshouldꢀbeꢀinꢀtransmitꢀ
modeꢀorꢀreceiveꢀmode.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀhigh,ꢀtheꢀmasterꢀisꢀrequestingꢀtoꢀreadꢀdataꢀ
fromꢀtheꢀbus,ꢀsoꢀtheꢀslaveꢀdeviceꢀshouldꢀbeꢀinꢀtransmitꢀmode.ꢀWhenꢀtheꢀSRWꢀflagꢀ
isꢀzero,ꢀtheꢀmasterꢀwillꢀwriteꢀdataꢀtoꢀtheꢀbus,ꢀthereforeꢀtheꢀslaveꢀdeviceꢀshouldꢀbeꢀinꢀ
receiveꢀmodeꢀtoꢀreadꢀthisꢀdata.
Bitꢀ1
IAMWU:ꢀI2CꢀAddressꢀMatchꢀWake-upꢀControl
0:ꢀDisable
1:ꢀEnableꢀ-ꢀmustꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogramꢀafterꢀwake-up
Thisꢀbitꢀshouldꢀbeꢀsetꢀtoꢀ1ꢀtoꢀenableꢀtheꢀI2CꢀaddressꢀmatchꢀwakeꢀupꢀfromꢀtheꢀSLEEPꢀ
orꢀIDLEꢀMode.ꢀIfꢀtheꢀIAMWUꢀbitꢀhasꢀbeenꢀsetꢀbeforeꢀenteringꢀeitherꢀtheꢀSLEEPꢀorꢀ
IDLEꢀmodeꢀtoꢀenableꢀtheꢀI2Cꢀaddressꢀmatchꢀwakeꢀup,ꢀthenꢀthisꢀbitꢀmustꢀbeꢀclearedꢀbyꢀ
theꢀapplicationꢀprogramꢀafterꢀwake-upꢀtoꢀensureꢀcorrectionꢀdeviceꢀoperation.
Rev. 1.00
17ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Bitꢀ0
RXAK:ꢀI2CꢀBusꢀReceiveꢀacknowledgeꢀflag
0:ꢀSlaveꢀreceiveꢀacknowledgeꢀflag
1:ꢀSlaveꢀdoesꢀnotꢀreceiveꢀacknowledgeꢀflag
TheꢀRXAKꢀflagꢀisꢀtheꢀreceiverꢀacknowledgeꢀflag.ꢀWhenꢀtheꢀRXAKꢀflagꢀisꢀ“0”,ꢀitꢀ
meansꢀthatꢀaꢀacknowledgeꢀsignalꢀhasꢀbeenꢀreceivedꢀatꢀtheꢀ9thꢀclock,ꢀafterꢀ8ꢀbitsꢀofꢀdataꢀ
haveꢀbeenꢀtransmitted.ꢀWhenꢀtheꢀslaveꢀdeviceꢀinꢀtheꢀtransmitꢀmode,ꢀtheꢀslaveꢀdeviceꢀ
checksꢀtheꢀRXAKꢀflagꢀtoꢀdetermineꢀifꢀtheꢀmasterꢀreceiverꢀwishesꢀtoꢀreceiveꢀtheꢀnextꢀ
byte.ꢀTheꢀslaveꢀtransmitterꢀwillꢀthereforeꢀcontinueꢀsendingꢀoutꢀdataꢀuntilꢀtheꢀRXAKꢀ
flagꢀisꢀ“1”.ꢀWhenꢀthisꢀoccurs,ꢀtheꢀslaveꢀtransmitterꢀwillꢀreleaseꢀtheꢀSDAꢀlineꢀtoꢀallowꢀ
theꢀmasterꢀtoꢀsendꢀaꢀSTOPꢀsignalꢀtoꢀreleaseꢀtheꢀI2CꢀBus.
TheꢀSIMDꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceived.ꢀTheꢀsameꢀregisterꢀisꢀ
usedꢀbyꢀbothꢀtheꢀSPIꢀandꢀI2Cꢀfunctions.ꢀBeforeꢀtheꢀdevicesꢀwriteꢀdataꢀtoꢀtheꢀSPIꢀbus,ꢀtheꢀactualꢀ
dataꢀtoꢀbeꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSIMDꢀregister.ꢀAfterꢀtheꢀdataꢀisꢀreceivedꢀfromꢀtheꢀ
SPIꢀbus,ꢀtheꢀdevicesꢀcanꢀreadꢀitꢀfromꢀtheꢀSIMDꢀregister.ꢀAnyꢀtransmissionꢀorꢀreceptionꢀofꢀdataꢀ
fromꢀtheꢀSPIꢀbusꢀmustꢀbeꢀmadeꢀviaꢀtheꢀSIMDꢀregister.
SIMD Register
Bit
7
D7
R/W
x
6
D6
R/W
X
5
D5
R/W
x
4
D4
R/W
x
3
Dꢅ
R/W
x
2
Dꢃ
R/W
x
1
D1
R/W
x
0
Name
R/W
D0
R/W
x
POR
“x”: unknown
SIMA Register
Bit
Name
R/W
7
IICA6
R/W
x
6
IICA5
R/W
X
5
IICA4
R/W
x
4
IICAꢅ
R/W
x
3
IICAꢃ
R/W
x
2
IICA1
R/W
x
1
IICA0
R/W
x
0
—
—
—
POR
“x”: unknown
Bitꢀ7~1
IICA6~IICA0:ꢀI2Cꢀslaveꢀaddress
IICA6~IICA0ꢀisꢀtheꢀI2Cꢀslaveꢀaddressꢀbitꢀ6~bitꢀ0
TheꢀSIMAꢀregisterꢀisꢀalsoꢀusedꢀbyꢀtheꢀSPIꢀinterfaceꢀbutꢀhasꢀtheꢀnameꢀSIMC2.ꢀTheꢀ
SIMAꢀregisterꢀisꢀtheꢀlocationꢀwhereꢀtheꢀ7-bitꢀslaveꢀaddressꢀofꢀtheꢀslaveꢀdeviceꢀisꢀ
stored.ꢀBitsꢀ7~1ꢀofꢀtheꢀSIMAꢀregisterꢀdefineꢀtheꢀdeviceꢀslaveꢀaddress.ꢀBitꢀ0ꢀisꢀnotꢀ
defined.
Whenꢀaꢀmasterꢀdevice,ꢀwhichꢀisꢀconnectedꢀtoꢀtheꢀI2Cꢀbus,ꢀsendsꢀoutꢀanꢀaddress,ꢀwhichꢀ
matchesꢀtheꢀslaveꢀaddressꢀinꢀtheꢀSIMAꢀregister,ꢀtheꢀslaveꢀdeviceꢀwillꢀbeꢀselected.ꢀNoteꢀ
thatꢀtheꢀSIMAꢀregisterꢀisꢀtheꢀsameꢀregisterꢀaddressꢀasꢀSIMC2ꢀwhichꢀisꢀusedꢀbyꢀtheꢀSPIꢀ
interface.
Bitꢀ0ꢀ
Undefinedꢀbit
Thisꢀbitꢀcanꢀbeꢀreadꢀorꢀwrittenꢀbyꢀuserꢀsoftwareꢀprogram.
Rev. 1.00
17ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
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I2C Block Diagram
I2C Bus Communication
CommunicationꢀonꢀtheꢀI2Cꢀbusꢀrequiresꢀfourꢀseparateꢀsteps,ꢀaꢀSTARTꢀsignal,ꢀaꢀslaveꢀdeviceꢀaddressꢀ
transmission,ꢀaꢀdataꢀtransmissionꢀandꢀfinallyꢀaꢀSTOPꢀsignal.ꢀWhenꢀaꢀSTARTꢀsignalꢀisꢀplacedꢀonꢀ
theꢀI2Cꢀbus,ꢀallꢀdevicesꢀonꢀtheꢀbusꢀwillꢀreceiveꢀthisꢀsignalꢀandꢀbeꢀnotifiedꢀofꢀtheꢀimminentꢀarrivalꢀofꢀ
dataꢀonꢀtheꢀbus.ꢀTheꢀfirstꢀsevenꢀbitsꢀofꢀtheꢀdataꢀwillꢀbeꢀtheꢀslaveꢀaddressꢀwithꢀtheꢀfirstꢀbitꢀbeingꢀtheꢀ
MSB.ꢀIfꢀtheꢀaddressꢀofꢀtheꢀslaveꢀdeviceꢀmatchesꢀthatꢀofꢀtheꢀtransmittedꢀaddress,ꢀtheꢀHAASꢀbitꢀinꢀtheꢀ
SIMC1ꢀregisterꢀwillꢀbeꢀsetꢀandꢀanꢀI2Cꢀinterruptꢀwillꢀbeꢀgenerated.ꢀAfterꢀenteringꢀtheꢀinterruptꢀserviceꢀ
routine,ꢀtheꢀslaveꢀdeviceꢀmustꢀfirstꢀcheckꢀtheꢀconditionꢀofꢀtheꢀHAASꢀbitꢀtoꢀdetermineꢀwhetherꢀtheꢀ
interruptꢀsourceꢀoriginatesꢀfromꢀanꢀaddressꢀmatchꢀorꢀfromꢀtheꢀcompletionꢀofꢀanꢀ8-bitꢀdataꢀtransfer.ꢀ
Duringꢀaꢀdataꢀtransfer,ꢀnoteꢀthatꢀafterꢀtheꢀ7-bitꢀslaveꢀaddressꢀhasꢀbeenꢀtransmitted,ꢀtheꢀfollowingꢀbit,ꢀ
whichꢀisꢀtheꢀ8thꢀbit,ꢀisꢀtheꢀread/writeꢀbitꢀwhoseꢀvalueꢀwillꢀbeꢀplacedꢀinꢀtheꢀSRWꢀbit.ꢀThisꢀbitꢀwillꢀbeꢀ
checkedꢀbyꢀtheꢀslaveꢀdeviceꢀtoꢀdetermineꢀwhetherꢀtoꢀgoꢀintoꢀtransmitꢀorꢀreceiveꢀmode.ꢀBeforeꢀanyꢀ
transferꢀofꢀdataꢀtoꢀorꢀfromꢀtheꢀI2Cꢀbus,ꢀtheꢀmicrocontrollerꢀmustꢀinitialiseꢀtheꢀbus,ꢀtheꢀfollowingꢀareꢀ
stepsꢀtoꢀachieveꢀthis:
•ꢀ Stepꢀ1
SetꢀtheꢀSIM2~SIM0ꢀandꢀSIMENꢀbitsꢀinꢀtheꢀSIMC0ꢀregisterꢀtoꢀ“1”ꢀtoꢀenableꢀtheꢀI2Cꢀbus.
•ꢀ Stepꢀ2
WriteꢀtheꢀslaveꢀaddressꢀofꢀtheꢀdeviceꢀtoꢀtheꢀI2CꢀbusꢀaddressꢀregisterꢀSIMA.
•ꢀ Stepꢀ3
SetꢀtheꢀSIMEꢀandꢀSIMꢀMuti-Functionꢀinterruptꢀenableꢀbitꢀofꢀtheꢀinterruptꢀcontrolꢀregisterꢀtoꢀ
enableꢀtheꢀSIMꢀinterruptꢀandꢀMulti-functionꢀinterrupt.
Rev. 1.00
174
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
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I2C Bus Initialisation Flow Chart
I2C Bus Start Signal
TheꢀSTARTꢀsignalꢀcanꢀonlyꢀbeꢀgeneratedꢀbyꢀtheꢀmasterꢀdeviceꢀconnectedꢀtoꢀtheꢀI2Cꢀbusꢀandꢀnotꢀbyꢀ
theꢀslaveꢀdevice.ꢀThisꢀSTARTꢀsignalꢀwillꢀbeꢀdetectedꢀbyꢀallꢀdevicesꢀconnectedꢀtoꢀtheꢀI2Cꢀbus.ꢀWhenꢀ
detected,ꢀthisꢀindicatesꢀthatꢀtheꢀI2CꢀbusꢀisꢀbusyꢀandꢀthereforeꢀtheꢀHBBꢀbitꢀwillꢀbeꢀset.ꢀAꢀSTARTꢀ
conditionꢀoccursꢀwhenꢀaꢀhighꢀtoꢀlowꢀtransitionꢀonꢀtheꢀSDAꢀlineꢀtakesꢀplaceꢀwhenꢀtheꢀSCLꢀlineꢀ
remainsꢀhigh.
Slave Address
TheꢀtransmissionꢀofꢀaꢀSTARTꢀsignalꢀbyꢀtheꢀmasterꢀwillꢀbeꢀdetectedꢀbyꢀallꢀdevicesꢀonꢀtheꢀI2Cꢀbus.ꢀ
Toꢀdetermineꢀwhichꢀslaveꢀdeviceꢀtheꢀmasterꢀwishesꢀtoꢀcommunicateꢀwith,ꢀtheꢀaddressꢀofꢀtheꢀslaveꢀ
deviceꢀwillꢀbeꢀsentꢀoutꢀimmediatelyꢀfollowingꢀtheꢀSTARTꢀsignal.ꢀAllꢀslaveꢀdevices,ꢀafterꢀreceivingꢀ
thisꢀ7-bitꢀaddressꢀdata,ꢀwillꢀcompareꢀitꢀwithꢀtheirꢀownꢀ7-bitꢀslaveꢀaddress.ꢀIfꢀtheꢀaddressꢀsentꢀoutꢀbyꢀ
theꢀmasterꢀmatchesꢀtheꢀinternalꢀaddressꢀofꢀtheꢀmicrocontrollerꢀslaveꢀdevice,ꢀthenꢀanꢀinternalꢀI2Cꢀbusꢀ
interruptꢀsignalꢀwillꢀbeꢀgenerated.ꢀTheꢀnextꢀbitꢀfollowingꢀtheꢀaddress,ꢀwhichꢀisꢀtheꢀ8thꢀbit,ꢀdefinesꢀ
theꢀread/writeꢀstatusꢀandꢀwillꢀbeꢀsavedꢀtoꢀtheꢀSRWꢀbitꢀofꢀtheꢀSIMC1ꢀregister.ꢀTheꢀslaveꢀdeviceꢀwillꢀ
thenꢀtransmitꢀanꢀacknowledgeꢀbit,ꢀwhichꢀisꢀaꢀlowꢀlevel,ꢀasꢀtheꢀ9thꢀbit.ꢀTheꢀslaveꢀdeviceꢀwillꢀalsoꢀsetꢀ
theꢀstatusꢀflagꢀHAASꢀwhenꢀtheꢀaddressesꢀmatch.
AsꢀanꢀI2Cꢀbusꢀinterruptꢀcanꢀcomeꢀfromꢀtwoꢀsources,ꢀwhenꢀtheꢀprogramꢀentersꢀtheꢀinterruptꢀ
subroutine,ꢀtheꢀHAASꢀbitꢀshouldꢀbeꢀexaminedꢀtoꢀseeꢀwhetherꢀtheꢀinterruptꢀsourceꢀhasꢀcomeꢀfromꢀ
aꢀmatchingꢀslaveꢀaddressꢀorꢀfromꢀtheꢀcompletionꢀofꢀaꢀdataꢀbyteꢀtransfer.ꢀWhenꢀaꢀslaveꢀaddressꢀisꢀ
matched,ꢀtheꢀdevicesꢀmustꢀbeꢀplacedꢀinꢀeitherꢀtheꢀtransmitꢀmodeꢀandꢀthenꢀwriteꢀdataꢀtoꢀtheꢀSIMDꢀ
register,ꢀorꢀinꢀtheꢀreceiveꢀmodeꢀwhereꢀitꢀmustꢀimplementꢀaꢀdummyꢀreadꢀfromꢀtheꢀSIMDꢀregisterꢀtoꢀ
releaseꢀtheꢀSCLꢀline.
Rev. 1.00
175
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
I2C Bus Read/Write Signal
TheꢀSRWꢀbitꢀinꢀtheꢀSIMC1ꢀregisterꢀdefinesꢀwhetherꢀtheꢀslaveꢀdeviceꢀwishesꢀtoꢀreadꢀdataꢀfromꢀtheꢀ
I2CꢀbusꢀorꢀwriteꢀdataꢀtoꢀtheꢀI2Cꢀbus.ꢀTheꢀslaveꢀdeviceꢀshouldꢀexamineꢀthisꢀbitꢀtoꢀdetermineꢀifꢀitꢀisꢀtoꢀ
beꢀaꢀtransmitterꢀorꢀaꢀreceiver.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀ“1”ꢀthenꢀthisꢀindicatesꢀthatꢀtheꢀmasterꢀdeviceꢀwishesꢀ
toꢀreadꢀdataꢀfromꢀtheꢀI2Cꢀbus,ꢀthereforeꢀtheꢀslaveꢀdeviceꢀmustꢀbeꢀsetupꢀtoꢀsendꢀdataꢀtoꢀtheꢀI2Cꢀbusꢀasꢀ
aꢀtransmitter.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀ“0”ꢀthenꢀthisꢀindicatesꢀthatꢀtheꢀmasterꢀwishesꢀtoꢀsendꢀdataꢀtoꢀtheꢀI2Cꢀ
bus,ꢀthereforeꢀtheꢀslaveꢀdeviceꢀmustꢀbeꢀsetupꢀtoꢀreadꢀdataꢀfromꢀtheꢀI2Cꢀbusꢀasꢀaꢀreceiver.
I2C Bus Slave Address Acknowledge Signal
Afterꢀtheꢀmasterꢀhasꢀtransmittedꢀaꢀcallingꢀaddress,ꢀanyꢀslaveꢀdeviceꢀonꢀtheꢀI2Cꢀbus,ꢀwhoseꢀ
ownꢀinternalꢀaddressꢀmatchesꢀtheꢀcallingꢀaddress,ꢀmustꢀgenerateꢀanꢀacknowledgeꢀsignal.ꢀTheꢀ
acknowledgeꢀsignalꢀwillꢀinformꢀtheꢀmasterꢀthatꢀaꢀslaveꢀdeviceꢀhasꢀacceptedꢀitsꢀcallingꢀaddress.ꢀIfꢀnoꢀ
acknowledgeꢀsignalꢀisꢀreceivedꢀbyꢀtheꢀmasterꢀthenꢀaꢀSTOPꢀsignalꢀmustꢀbeꢀtransmittedꢀbyꢀtheꢀmasterꢀ
toꢀendꢀtheꢀcommunication.ꢀWhenꢀtheꢀHAASꢀflagꢀisꢀhigh,ꢀtheꢀaddressesꢀhaveꢀmatchedꢀandꢀtheꢀslaveꢀ
deviceꢀmustꢀcheckꢀtheꢀSRWꢀflagꢀtoꢀdetermineꢀifꢀitꢀisꢀtoꢀbeꢀaꢀtransmitterꢀorꢀaꢀreceiver.ꢀIfꢀtheꢀSRWꢀflagꢀ
isꢀhigh,ꢀtheꢀslaveꢀdeviceꢀshouldꢀbeꢀsetupꢀtoꢀbeꢀaꢀtransmitterꢀsoꢀtheꢀHTXꢀbitꢀinꢀtheꢀSIMC1ꢀregisterꢀ
shouldꢀbeꢀsetꢀtoꢀ“1”.ꢀIfꢀtheꢀSRWꢀflagꢀisꢀlow,ꢀthenꢀtheꢀmicrocontrollerꢀslaveꢀdeviceꢀshouldꢀbeꢀsetupꢀasꢀ
aꢀreceiverꢀandꢀtheꢀHTXꢀbitꢀinꢀtheꢀSIMC1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ“0”.
I2C Bus Data and Acknowledge Signal
Theꢀtransmittedꢀdataꢀisꢀ8-bitsꢀwideꢀandꢀisꢀtransmittedꢀafterꢀtheꢀslaveꢀdeviceꢀhasꢀacknowledgedꢀ
receiptꢀofꢀitsꢀslaveꢀaddress.ꢀTheꢀorderꢀofꢀserialꢀbitꢀtransmissionꢀisꢀtheꢀMSBꢀfirstꢀandꢀtheꢀLSBꢀlast.ꢀ
Afterꢀreceiptꢀofꢀ8-bitsꢀofꢀdata,ꢀtheꢀreceiverꢀmustꢀtransmitꢀanꢀacknowledgeꢀsignal,ꢀlevelꢀ“0”,ꢀbeforeꢀ
itꢀcanꢀreceiveꢀtheꢀnextꢀdataꢀbyte.ꢀIfꢀtheꢀslaveꢀtransmitterꢀdoesꢀnotꢀreceiveꢀanꢀacknowledgeꢀbitꢀsignalꢀ
fromꢀtheꢀmasterꢀreceiver,ꢀthenꢀtheꢀslaveꢀtransmitterꢀwillꢀreleaseꢀtheꢀSDAꢀlineꢀtoꢀallowꢀtheꢀmasterꢀ
toꢀsendꢀaꢀSTOPꢀsignalꢀtoꢀreleaseꢀtheꢀI2CꢀBus.ꢀTheꢀcorrespondingꢀdataꢀwillꢀbeꢀstoredꢀinꢀtheꢀSIMDꢀ
register.ꢀIfꢀsetupꢀasꢀaꢀtransmitter,ꢀtheꢀslaveꢀdeviceꢀmustꢀfirstꢀwriteꢀtheꢀdataꢀtoꢀbeꢀtransmittedꢀintoꢀtheꢀ
SIMDꢀregister.ꢀIfꢀsetupꢀasꢀaꢀreceiver,ꢀtheꢀslaveꢀdeviceꢀmustꢀreadꢀtheꢀtransmittedꢀdataꢀfromꢀtheꢀSIMDꢀ
register.
Whenꢀtheꢀslaveꢀreceiverꢀreceivesꢀtheꢀdataꢀbyte,ꢀitꢀmustꢀgenerateꢀanꢀacknowledgeꢀbit,ꢀknownꢀasꢀ
TXAK,ꢀonꢀtheꢀ9thꢀclock.ꢀTheꢀslaveꢀdevice,ꢀwhichꢀisꢀsetupꢀasꢀaꢀtransmitterꢀwillꢀcheckꢀtheꢀRXAKꢀbitꢀ
inꢀtheꢀSIMC1ꢀregisterꢀtoꢀdetermineꢀifꢀitꢀisꢀtoꢀsendꢀanotherꢀdataꢀbyte,ꢀifꢀnotꢀthenꢀitꢀwillꢀreleaseꢀtheꢀ
SDAꢀlineꢀandꢀawaitꢀtheꢀreceiptꢀofꢀaꢀSTOPꢀsignalꢀfromꢀtheꢀmaster.
Rev. 1.00
176
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
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Note:ꢀ*Whenꢀaꢀslaveꢀaddressꢀisꢀmatched,ꢀtheꢀdevicesꢀmustꢀbeꢀplacedꢀinꢀeitherꢀtheꢀtransmitꢀmodeꢀ
andꢀthenꢀwriteꢀdataꢀtoꢀtheꢀSIMDꢀregister,ꢀorꢀinꢀtheꢀreceiveꢀmodeꢀwhereꢀitꢀmustꢀimplementꢀaꢀ
dummyꢀreadꢀfromꢀtheꢀSIMDꢀregisterꢀtoꢀreleaseꢀtheꢀSCLꢀline.
I2C Communication Timing Diagram
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I2C Bus ISR flow Chart
Rev. 1.00
177
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
I2C Time-out Control
InꢀorderꢀtoꢀreduceꢀtheꢀI2Cꢀlockupꢀproblemꢀdueꢀtoꢀreceptionꢀofꢀerroneousꢀclockꢀsources,ꢀaꢀtime-outꢀ
functionꢀisꢀprovided.ꢀIfꢀtheꢀclockꢀsourceꢀconnectedꢀtoꢀtheꢀI2Cꢀbusꢀisꢀnotꢀreceivedꢀforꢀaꢀwhile,ꢀthenꢀtheꢀ
I2Cꢀcircuitryꢀandꢀregistersꢀwillꢀbeꢀresetꢀafterꢀaꢀcertainꢀtime-outꢀperiod.ꢀTheꢀtime-outꢀcounterꢀstartsꢀtoꢀ
countꢀonꢀanꢀI2Cꢀbusꢀ“START”ꢀ&ꢀ“addressꢀmatch”condition,ꢀandꢀisꢀclearedꢀbyꢀanꢀSCLꢀfallingꢀedge.ꢀ
BeforeꢀtheꢀnextꢀSCLꢀfallingꢀedgeꢀarrives,ꢀifꢀtheꢀtimeꢀelapsedꢀisꢀgreaterꢀthanꢀtheꢀtime-outꢀperiodꢀ
specifiedꢀbyꢀtheꢀI2CTOCꢀregister,ꢀthenꢀaꢀtime-outꢀconditionꢀwillꢀoccur.ꢀTheꢀtime-outꢀfunctionꢀwillꢀ
stopꢀwhenꢀanꢀI2Cꢀ“STOP”ꢀconditionꢀoccurs.
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I2C Time-out
WhenꢀanꢀI2Cꢀtime-outꢀcounterꢀoverflowꢀoccurs,ꢀtheꢀcounterꢀwillꢀstopꢀandꢀtheꢀI2CTOENꢀbitꢀwillꢀbeꢀ
clearedꢀtoꢀzeroꢀandꢀtheꢀI2CTFꢀbitꢀwillꢀbeꢀsetꢀhighꢀtoꢀindicateꢀthatꢀaꢀtime-outꢀconditionꢀhasꢀoccurred.ꢀ
Theꢀtime-outꢀconditionꢀwillꢀalsoꢀgenerateꢀanꢀinterruptꢀwhichꢀusesꢀtheꢀI2Cꢀinterrruptꢀvector.ꢀWhenꢀ
anꢀI2Cꢀtime-outꢀoccurs,ꢀtheꢀI2Cꢀinternalꢀcircuitryꢀwillꢀbeꢀresetꢀandꢀtheꢀregistersꢀwillꢀbeꢀresetꢀintoꢀtheꢀ
followingꢀcondition:
Register
SI�Dꢄ SI�Aꢄ SI�C0
SI�C1
After I2C Time-out
No ꢁꢂange
Reset to POR ꢁondition
I2C Registers after Time-out
TheꢀI2CTOFꢀflagꢀcanꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.ꢀThereꢀareꢀ64ꢀtime-outꢀperiodꢀselectionsꢀ
whichꢀcanꢀbeꢀselectedꢀusingꢀtheꢀI2CTOSꢀbitsꢀinꢀtheꢀI2CTOCꢀregister.ꢀTheꢀtime-outꢀdurationꢀisꢀ
calculatedꢀbyꢀtheꢀformula:ꢀ((1~64)ꢀ×ꢀ(32/fSUB)).ꢀThisꢀgivesꢀaꢀtime-outꢀperiodꢀwhichꢀrangesꢀfromꢀ
aboutꢀ1msꢀtoꢀ64ms.
Rev. 1.00
178
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
I2CTOC Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
IꢃCTOEN IꢃCTOF IꢃCTOS5 IꢃCTOS4 IꢃCTOSꢅ IꢃCTOSꢃ IꢃCTOS1 IꢃCTOS0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7
I2CTOEN:ꢀI2CꢀTime-outꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ6
I2CTOF:ꢀI2CꢀTime-outꢀflag
0:ꢀNoꢀtime-outꢀoccurred
1:ꢀTime-outꢀoccurred
Bitꢀ5~0
I2CTOS5~I2CTOS0:ꢀI2CꢀTime-outꢀTimeꢀSelection
I2CꢀTime-outꢀclockꢀsourceꢀisꢀfSUB/32
I2CꢀTime-outꢀtimeꢀisꢀgivenꢀby:ꢀ(I2CTOSꢀ[5:0]ꢀ+1)ꢀ×ꢀ(32/fSUB
)
Peripheral Clock Output
TheꢀPeripheralꢀClockꢀOutputꢀallowsꢀtheꢀdeviceꢀtoꢀsupplyꢀexternalꢀhardwareꢀwithꢀaꢀclockꢀsignalꢀ
synchronisedꢀtoꢀtheꢀmicrocontrollerꢀclock.
Peripheral Clock Operation
Asꢀtheꢀperipheralꢀclockꢀoutputꢀpin,ꢀPCK,ꢀisꢀsharedꢀwithꢀI/Oꢀline,ꢀtheꢀrequiredꢀpinꢀfunctionꢀisꢀchosenꢀ
usingꢀtheꢀrelevantꢀpin-sharedꢀfunctionꢀselectionꢀbit.ꢀTheꢀPeripheralꢀClockꢀfunctionꢀisꢀcontrolledꢀ
usingꢀtheꢀTB2ENꢀbitꢀinꢀtheꢀTBC2ꢀregister.ꢀTheꢀclockꢀsourceꢀforꢀtheꢀPeripheralꢀClockꢀOutputꢀcanꢀ
originateꢀfromꢀtheꢀsystemꢀclockꢀfSYS,ꢀtheꢀinstructionꢀclock,ꢀtheꢀhighꢀspeedꢀoscillatorꢀclockꢀfHꢀorꢀtheꢀ
fSUBꢀclockꢀwhichꢀcanꢀbeꢀselectedꢀbyꢀtheꢀCLKS11ꢀandꢀCLKS10ꢀbitsꢀinꢀtheꢀPSC1ꢀregister.ꢀTheꢀTB2ENꢀ
bitꢀinꢀtheꢀTBC2ꢀregisterꢀisꢀtheꢀoverallꢀon/offꢀcontrol,ꢀsettingꢀTB2ENꢀbitꢀtoꢀ1ꢀenablesꢀtheꢀPeripheralꢀ
ClockꢀwhileꢀsettingꢀTB2ENꢀbitꢀtoꢀ0ꢀdisablesꢀit.ꢀTheꢀrequiredꢀdivisionꢀratioꢀofꢀtheꢀperipheralꢀclockꢀ
isꢀselectedꢀusingꢀtheꢀTB22,ꢀTB21ꢀandꢀTB20ꢀbitsꢀinꢀtheꢀTBC2ꢀregister.ꢀIfꢀtheꢀperipheralꢀclockꢀsourceꢀ
isꢀswitchedꢀoffꢀwhenꢀtheꢀdeviceꢀentersꢀtheꢀpowerꢀdownꢀmode,ꢀthisꢀwillꢀdisableꢀtheꢀPeripheralꢀClockꢀ
output.
fSUB
fH
fSYS
fP
fP/ꢃ0 ~ fP/ꢃ7
Pꢀesꢁaleꢀ
TBꢃEN
PCK
fSYS/4
CLKS1[1:0 ]
TBꢃ[ꢃ:0 ]
Peripheral Clock Output
Rev. 1.00
179
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Peripheral Clock Registers
ThereꢀareꢀtwoꢀinternalꢀregistersꢀwhichꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀPeripheralꢀClockꢀOutput.ꢀ
TheseꢀareꢀtheꢀPSC1ꢀandꢀTBC2ꢀregisters.
Bit
Name
7
—
6
5
4
3
2
1
0
PSC1
TBCꢃ
—
—
—
—
—
—
—
—
—
CLKS11 CLKS10
TBꢃEN
TBꢃꢃ
TBꢃ1
TBꢃ0
PCK Register List
PSC1 Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLKS11 CLKS10
R/W
0
R/W
0
POR
Bitꢀ7~2ꢀꢀ
Bitꢀ1~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
CLKS11,ꢀCLKS10:ꢀPeripheralꢀClockꢀSourceꢀselection
00:ꢀfSYS
01:ꢀfSYS/4
10:ꢀfSUB
11:ꢀfH
TBC2 Register
Bit
Name
R/W
7
TBꢃEN
R/W
0
6
5
4
3
2
TBꢃꢃ
R/W
0
1
TBꢃ1
R/W
0
0
TBꢃ0
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7
TB2EN:ꢀPeripheralꢀClockꢀFunctionꢀenableꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ6~3ꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ“0”
TB22,ꢀTB21, TB20: PeripheralꢀClockꢀoutputꢀdivisionꢀselection
000:ꢀfP
001:ꢀfP/2
010:ꢀfP/4
011:ꢀfP/8
100:ꢀfP/16
101:ꢀfP/32
110:ꢀfP/64
111:ꢀfP/128
Rev. 1.00
180
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Serial Interface – SPIA
TheꢀdeviceꢀcontainsꢀanꢀindependentꢀSPIꢀfunction.ꢀItꢀisꢀimportantꢀnotꢀtoꢀconfuseꢀthisꢀindependentꢀSPIꢀ
functionꢀwithꢀtheꢀadditionalꢀoneꢀcontainedꢀwithinꢀtheꢀcombinedꢀSIMꢀfunction,ꢀwhichꢀisꢀdescribedꢀ
inꢀanotherꢀsectionꢀofꢀthisꢀdatasheet.ꢀThisꢀindependentꢀSPIꢀfunctionꢀwillꢀcarryꢀtheꢀnameꢀSPIAꢀtoꢀ
distinguishꢀitꢀfromꢀtheꢀotherꢀoneꢀinꢀtheꢀSIM.
ThisꢀSPIAꢀinterfaceꢀisꢀoftenꢀusedꢀtoꢀcommunicateꢀwithꢀexternalꢀperipheralꢀdevicesꢀsuchꢀasꢀsensors,ꢀ
FlashꢀorꢀEEPROMꢀmemoryꢀdevices,ꢀetc.ꢀOriginallyꢀdevelopedꢀbyꢀMotorola,ꢀtheꢀfourꢀlineꢀSPIꢀ
interfaceꢀisꢀaꢀsynchronousꢀserialꢀdataꢀinterfaceꢀthatꢀhasꢀaꢀrelativelyꢀsimpleꢀcommunicationꢀprotocolꢀ
simplifyingꢀtheꢀprogrammingꢀrequirementsꢀwhenꢀcommunicatingꢀwithꢀexternalꢀhardwareꢀdevices.
Theꢀcommunicationꢀisꢀfullꢀduplexꢀandꢀoperatesꢀasꢀaꢀslave/masterꢀtype,ꢀwhereꢀtheꢀdeviceꢀcanꢀbeꢀ
eitherꢀmasterꢀorꢀslave.ꢀAlthoughꢀtheꢀSPIAꢀinterfaceꢀspecificationꢀcanꢀcontrolꢀmultipleꢀslaveꢀdevicesꢀ
fromꢀaꢀsingleꢀmaster,ꢀthisꢀdeviceꢀisꢀprovidedꢀonlyꢀoneꢀSCSAꢀpin.ꢀIfꢀtheꢀmasterꢀneedsꢀtoꢀcontrolꢀ
multipleꢀslaveꢀdevicesꢀfromꢀaꢀsingleꢀmaster,ꢀtheꢀmasterꢀcanꢀuseꢀI/Oꢀpinsꢀtoꢀselectꢀtheꢀslaveꢀdevices.
SPIA Interface Operation
TheꢀSPIAꢀinterfaceꢀisꢀaꢀfullꢀduplexꢀsynchronousꢀserialꢀdataꢀlink.ꢀItꢀisꢀaꢀfourꢀlineꢀinterfaceꢀwithꢀpinꢀ
namesꢀSDIA,ꢀSDOA,ꢀSCKAꢀandꢀSCSA.ꢀPinsꢀSDIAꢀandꢀSDOAꢀareꢀtheꢀSerialꢀDataꢀInputꢀandꢀSerialꢀ
DataꢀOutputꢀlines,ꢀSCKAꢀisꢀtheꢀSerialꢀClockꢀlineꢀandꢀSCSAꢀisꢀtheꢀSlaveꢀSelectꢀline.ꢀAsꢀtheꢀSPIAꢀ
interfaceꢀpinsꢀareꢀpin-sharedꢀwithꢀotherꢀfunctions,ꢀtheꢀSPIAꢀinterfaceꢀpinsꢀmustꢀfirstꢀbeꢀselectedꢀ
byꢀconfiguringꢀtheꢀcorrespondingꢀselectionꢀbitsꢀinꢀtheꢀpin-sharedꢀfunctionꢀselectionꢀregisters.ꢀ
TheꢀSPIAꢀinterfaceꢀfunctionꢀisꢀdisabledꢀorꢀenabledꢀusingꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀregister.ꢀ
CommunicationꢀbetweenꢀdevicesꢀconnectedꢀtoꢀtheꢀSPIAꢀinterfaceꢀisꢀcarriedꢀoutꢀinꢀaꢀslave/masterꢀ
modeꢀwithꢀallꢀdataꢀtransferꢀinitiationsꢀbeingꢀimplementedꢀbyꢀtheꢀmaster.ꢀTheꢀmasterꢀalsoꢀcontrolsꢀtheꢀ
clock/signal.ꢀAsꢀtheꢀdeviceꢀonlyꢀcontainsꢀaꢀsingleꢀSCSAꢀpinꢀonlyꢀoneꢀslaveꢀdeviceꢀcanꢀbeꢀutilised.ꢀ
TheꢀSCSAꢀpinꢀisꢀcontrolledꢀbyꢀtheꢀapplicationꢀprogram,ꢀsetꢀtheꢀtheꢀSACSENꢀbitꢀtoꢀ“1”ꢀtoꢀenableꢀtheꢀ
SCSAꢀpinꢀfunctionꢀandꢀclearꢀtheꢀSACSENꢀbitꢀtoꢀ“0”ꢀtoꢀplaceꢀtheꢀSCSAꢀpinꢀintoꢀanꢀI/Oꢀfunction.
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C
A
SPIA Master/Slave Connection
Rev. 1.00
181
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
D
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SPIA Block Diagram
TheꢀSPIAꢀSerialꢀInterfaceꢀfunctionꢀincludesꢀtheꢀfollowingꢀfeatures:
•ꢀ Full-duplexꢀsynchronousꢀdataꢀtransferꢀ
•ꢀ BothꢀMasterꢀandꢀSlaveꢀmode
•ꢀ LSBꢀfirstꢀorꢀMSBꢀfirstꢀdataꢀtransmissionꢀmodes
•ꢀ Transmissionꢀcompleteꢀflag
•ꢀ Risingꢀorꢀfallingꢀactiveꢀclockꢀedge
TheꢀstatusꢀofꢀtheꢀSPIAꢀinterfaceꢀpinsꢀisꢀdeterminedꢀbyꢀaꢀnumberꢀofꢀfactorsꢀsuchꢀasꢀwhetherꢀtheꢀ
deviceꢀisꢀinꢀtheꢀmasterꢀorꢀslaveꢀmodeꢀandꢀuponꢀtheꢀconditionꢀofꢀcertainꢀcontrolꢀbitsꢀsuchꢀasꢀSACSENꢀ
andꢀSPIAEN.
SPIA registers
ThereꢀareꢀthreeꢀregistersꢀwhichꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀSPIAꢀinterface.ꢀTheseꢀareꢀtheꢀ
SPIADꢀdataꢀregistersꢀandꢀtwoꢀcontrolꢀregistersꢀSPIAC0ꢀandꢀSPIAC1.
Bit
Register
Name
7
6
5
4
3
2
1
0
SPIAC0 SASPIꢃ SASPI1
SASPI0
—
—
—
SPIAEN
—
SPIAC1
SPIAD
—
—
SACKPOL SACKEG SA�LS SACSEN SAWCOL SATRF
D5 D4 Dꢅ Dꢃ D1 D0
SPIA Registers List
D7
D6
TheꢀSPIADꢀregisterꢀisꢀusedꢀtoꢀstoreꢀtheꢀdataꢀbeingꢀtransmittedꢀandꢀreceived.ꢀBeforeꢀtheꢀdeviceꢀ
writesꢀdataꢀtoꢀthisꢀSPIAꢀbus,ꢀtheꢀactualꢀdataꢀtoꢀbeꢀtransmittedꢀmustꢀbeꢀplacedꢀinꢀtheꢀSPIADꢀregister.ꢀ
AfterꢀtheꢀdataꢀisꢀreceivedꢀfromꢀtheꢀSPIAꢀbus,ꢀtheꢀdeviceꢀcanꢀreadꢀitꢀfromꢀtheꢀSPIADꢀregister.ꢀAnyꢀ
transmissionꢀorꢀreceptionꢀofꢀdataꢀfromꢀtheꢀSPIAꢀbusꢀmustꢀbeꢀmadeꢀviaꢀtheꢀSPIADꢀregisters.
Rev. 1.00
18ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SPIAD Register
Bit
Name
R/W
7
D7
R/W
×
6
D6
R/W
×
5
D5
R/W
×
4
D4
R/W
×
3
Dꢅ
R/W
×
2
Dꢃ
R/W
×
1
D1
R/W
×
0
D0
R/W
POR
×
“×” unknown
ThereꢀareꢀalsoꢀtwoꢀcontrolꢀregistersꢀforꢀtheꢀSPIAꢀinterface,ꢀSPIAC0ꢀandꢀSPIAC1.ꢀRegisterꢀSPIAC0ꢀ
isꢀusedꢀtoꢀcontrolꢀtheꢀenable/disableꢀfunctionꢀandꢀtoꢀsetꢀtheꢀdataꢀtransmissionꢀclockꢀfrequency.ꢀ
RegisterꢀSPIAC1ꢀisꢀusedꢀforꢀotherꢀcontrolꢀfunctionsꢀsuchꢀasꢀLSB/MSBꢀselection,ꢀwriteꢀcollisionꢀ
flag,ꢀetc.
SPIAC0 Register
Bit
Name
R/W
7
SASPIꢃ
R/W
1
6
SASPI1
R/W
1
5
SASPI0
R/W
1
4
3
2
1
SPIAEN
R/W
0
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7~5
SASPI2~SASPI0:ꢀSPIAꢀMaster/SlaveꢀClockꢀSelect
000:ꢀSPIAꢀmaster,ꢀfSYS/4
001:ꢀSPIAꢀmaster,ꢀfSYS/16
010:ꢀSPIAꢀmaster,ꢀfSYS/64
011:ꢀSPIAꢀmaster,ꢀfSUB
100:ꢀSPIAꢀmaster,ꢀTP0ꢀCCRPꢀmatchꢀfrequency/2ꢀ(PFD)
101:ꢀSPIAꢀslaveꢀ
110:ꢀReserved
111:ꢀReserved
Bitꢀ4~2ꢀ
Bitꢀ1
Unimplemented,ꢀreadꢀasꢀ“0”
SPIAEN:ꢀSPIAꢀenableꢀorꢀdisable
0:ꢀDisable
1:ꢀEnable
Theꢀbitꢀisꢀtheꢀoverallꢀon/offꢀcontrolꢀforꢀtheꢀSPIAꢀinterface.ꢀWhenꢀtheꢀSPIAENꢀbitꢀ
isꢀclearedꢀtoꢀzeroꢀtoꢀdisableꢀtheꢀSPIAꢀinterface,ꢀtheꢀSDIA,ꢀSDOA,ꢀSCKAꢀandꢀSCSAꢀ
linesꢀwillꢀloseꢀtheirꢀSPIꢀfunctionꢀandꢀtheꢀSPIAꢀoperatingꢀcurrentꢀwillꢀbeꢀreducedꢀtoꢀaꢀ
minimumꢀvalue.ꢀWhenꢀtheꢀbitꢀisꢀhigh,ꢀtheꢀSPIAꢀinterfaceꢀisꢀenabled.
Bitꢀ0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.00
18ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SPIAC1 Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
SACKPOL SACKEG SA�LS SACSEN SAWCOL SATRF
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5
ꢀUnimplemented,ꢀreadꢀasꢀ“0”
SACKPOL:ꢀDeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline
0:ꢀSCKAꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive
1:ꢀSCKAꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive
TheꢀSACKPOLꢀbitꢀdeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀ
thenꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀSACKPOLꢀbitꢀisꢀ
low,ꢀthenꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.
Bitꢀ4ꢀ
SACKEG:ꢀDeterminesꢀtheꢀSPIAꢀSCKAꢀactiveꢀclockꢀedgeꢀtype
SACKPOL=0:ꢀ
0:ꢀSCKAꢀhasꢀhighꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀrisingꢀedgeꢀ
1:ꢀSCKAꢀhasꢀhighꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀfallingꢀedge
SACKPOL=1:ꢀ
0:ꢀSCKAꢀhasꢀlowꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀfallingꢀedgeꢀ
1:ꢀSCKAꢀhasꢀlowꢀbaseꢀlevelꢀwithꢀdataꢀcaptureꢀonꢀSCKAꢀrisingꢀedge
TheꢀSACKEGꢀandꢀSACKPOLꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀwayꢀthatꢀtheꢀclockꢀsignalꢀ
outputsꢀandꢀinputsꢀdataꢀonꢀtheꢀSPIAꢀbus.ꢀTheseꢀtwoꢀbitsꢀmustꢀbeꢀconfiguredꢀbeforeꢀaꢀ
dataꢀtransferꢀisꢀexecutedꢀotherwiseꢀanꢀerroneousꢀclockꢀedgeꢀmayꢀbeꢀgenerated.ꢀTheꢀ
SACKPOLꢀbitꢀdeterminesꢀtheꢀbaseꢀconditionꢀofꢀtheꢀclockꢀline,ꢀifꢀtheꢀbitꢀisꢀhigh,ꢀthenꢀ
theꢀSCKAꢀlineꢀwillꢀbeꢀlowꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀWhenꢀtheꢀSACKPOLꢀbitꢀisꢀ
low,ꢀthenꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀhighꢀwhenꢀtheꢀclockꢀisꢀinactive.ꢀTheꢀSACKEGꢀbitꢀ
determinesꢀactiveꢀclockꢀedgeꢀtypeꢀwhichꢀdependsꢀuponꢀtheꢀconditionꢀofꢀtheꢀSACKPOLꢀ
bit.
Bitꢀ3
SAMLS:ꢀdataꢀshiftꢀorder
0:ꢀTheꢀLSBꢀofꢀdataꢀisꢀtransmittedꢀfirst
1:ꢀTheꢀMSBꢀofꢀdataꢀisꢀtransmittedꢀfirst
Bitꢀ2ꢀ
SACSEN:ꢀSPIAꢀSCSAꢀpinꢀControl
0:ꢀDisable
1:ꢀEnable
TheꢀSACSENꢀbitꢀisꢀusedꢀasꢀanꢀenable/disableꢀforꢀtheꢀSCSAꢀpin.ꢀIfꢀthisꢀbitꢀisꢀlow,ꢀthenꢀ
theꢀSCSAꢀpinꢀfunctionꢀwillꢀbeꢀdisabledꢀandꢀusedꢀasꢀanꢀI/Oꢀfunction.ꢀIfꢀtheꢀbitꢀisꢀhighꢀ
theꢀSCSAꢀpinꢀwillꢀbeꢀenabledꢀandꢀusedꢀasꢀaꢀselectꢀpin.
Bitꢀ1ꢀ
Bitꢀ0ꢀ
SAWCOL:ꢀSPIAꢀWriteꢀCollisionꢀflag
0:ꢀCollisionꢀfree
1:ꢀCollisionꢀdetected
TheꢀSAWCOLꢀflagꢀisꢀusedꢀtoꢀdetectꢀifꢀaꢀdataꢀcollisionꢀhasꢀoccurred.ꢀIfꢀthisꢀbitꢀisꢀhighꢀ
itꢀmeansꢀthatꢀdataꢀhasꢀbeenꢀattemptedꢀtoꢀbeꢀwrittenꢀtoꢀtheꢀSPIADꢀregisterꢀduringꢀaꢀdataꢀ
transferꢀoperation.ꢀThisꢀwritingꢀoperationꢀwillꢀbeꢀignoredꢀifꢀdataꢀisꢀbeingꢀtransferred.ꢀ
Theꢀbitꢀcanꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.
SATRF:ꢀSPIAꢀTransmit/ReceiveꢀCompleteꢀflag
0:ꢀDataꢀisꢀbeingꢀtransferred
1:ꢀSPIAꢀdataꢀtransmissionꢀisꢀcompleted
TheꢀSATRFꢀbitꢀisꢀtheꢀTransmit/ReceiveꢀCompleteꢀflagꢀandꢀisꢀsetꢀtoꢀ“1”ꢀautomaticallyꢀ
whenꢀanꢀSPIAꢀdataꢀtransmissionꢀisꢀcompleted,ꢀbutꢀmustꢀclearedꢀtoꢀ“0”ꢀbyꢀtheꢀ
applicationꢀprogram.ꢀItꢀcanꢀbeꢀusedꢀtoꢀgenerateꢀanꢀinterrupt.
Rev. 1.00
184
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SPIA Communication
AfterꢀtheꢀSPIAꢀinterfaceꢀisꢀenabledꢀbyꢀsettingꢀtheꢀSPIAENꢀbitꢀhigh,ꢀthenꢀinꢀtheꢀMasterꢀMode,ꢀwhenꢀ
dataꢀisꢀwrittenꢀtoꢀtheꢀSPIADꢀregister,ꢀtransmission/receptionꢀwillꢀbeginꢀsimultaneously.ꢀWhenꢀtheꢀ
dataꢀtransferꢀisꢀcomplete,ꢀtheꢀSATRFꢀflagꢀwillꢀbeꢀsetꢀautomatically,ꢀbutꢀmustꢀbeꢀclearedꢀusingꢀtheꢀ
applicationꢀprogram.ꢀInꢀtheꢀSlaveꢀMode,ꢀwhenꢀtheꢀclockꢀsignalꢀfromꢀtheꢀmasterꢀhasꢀbeenꢀreceived,ꢀ
anyꢀdataꢀinꢀtheꢀSPIADꢀregisterꢀwillꢀbeꢀtransmittedꢀandꢀanyꢀdataꢀonꢀtheꢀSDIAꢀpinꢀwillꢀbeꢀshiftedꢀintoꢀ
theꢀSPIADꢀregisters.
TheꢀmasterꢀshouldꢀoutputꢀaꢀSCSAꢀsignalꢀtoꢀenableꢀtheꢀslaveꢀdeviceꢀbeforeꢀaꢀclockꢀsignalꢀisꢀprovided.ꢀ
Theꢀslaveꢀdataꢀtoꢀbeꢀtransferredꢀshouldꢀbeꢀwellꢀpreparedꢀatꢀtheꢀappropriateꢀmomentꢀrelativeꢀtoꢀ
theꢀSCSAꢀsignalꢀdependingꢀuponꢀtheꢀconfigurationsꢀofꢀtheꢀSACKPOLꢀbitꢀandꢀSACKEGꢀbit.ꢀTheꢀ
accompanyingꢀtimingꢀdiagramꢀshowsꢀtheꢀrelationshipꢀbetweenꢀtheꢀslaveꢀdataꢀandꢀSCSAꢀsignalꢀforꢀ
variousꢀconfigurationsꢀofꢀtheꢀSACKPOLꢀandꢀSACKEGꢀbits.
TheꢀSPIAꢀwillꢀcontinueꢀtoꢀfunctionꢀevenꢀinꢀtheꢀIDLEꢀMode.
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SPIA Transfer Control Flowchart
Rev. 1.00
185
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SPIA masteꢀ mode
SPIAEN
= 0 ( exteꢀnal pull-ꢂigꢂ )
=1ꢄ SACSEN
SCSA
SPIAEN
= 1
=1ꢄ SACSEN
(
SCKA SACKPOL=1ꢄ SACKEG=
)
)
0
(
SACKPOL=0ꢄ SACKEG
SCKA
SCKA
=0
(
(
)
1
=1ꢄ
SACKPOL
=
SACKEG
)
1
SACKPOL 0ꢄSACKEG
=
SCKA
=
(
SDOA SACKEG=0
)
D 7/D 0 D 6/D 1 D 5/D ꢃ D 4/D ꢅ D ꢅ/D4 D ꢃ/D 5 D1/D 6 D 0/D 7
D 7/D 0 D 6/D 1 D 5/D ꢃ D 4/D ꢅ D ꢅ/D4 D ꢃ/D 5 D1/D 6 D 0/D 7
(SACKEG =1)
SDOA
SDIA Data ꢁaptuꢀe
Wꢀite to SPIAD
SPIA slave mode
SCSA
( SACKEG=0)
SCKA (SACKPOL=1)
SCKA (SACKPOL=0 )
SDOA
D 7/D 0 D 6/D 1 D 5/D ꢃ D 4/D ꢅ D ꢅ/D4 D ꢃ/D 5 D1/D 6 D 0/D 7
SDIA Data ꢁaptuꢀe
Wꢀite to SPIAD
(SDOA not ꢁꢂange until fiꢀst SCKA edge)
)
=1
SPIA slave mode
(
SACKEG
SCSA
)
=1
SCKA (
SACKPOL
SCKA (SACKPOL=0 )
SDOA
D 7/D 0 D 6/D 1 D 5/D ꢃ D 4/D ꢅ D ꢅ/D4 D ꢃ/D 5 D 1/D 6 D 0/D 7
SDIA Data ꢁaptuꢀe
Wꢀite to SPIAD
(SDOA ꢁꢂange as soon as wꢀiting oꢁꢁuꢀ; SDOA = floating if SCSA =1)
Note :
=0 ꢄ SPIA is always
Foꢀ SPIA slave modeꢄ if SPIAEN=1 and SACSEN
enabled and ignoꢀe tꢂe SCSA level.
SPIA Master/Slave ModeTiming Diagram
Rev. 1.00
186
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SPIA Bus Enable/Disable
ToꢀenableꢀtheꢀSPIAꢀbus,ꢀsetꢀSACSEN=1ꢀandꢀSCSA=0,ꢀthenꢀwaitꢀforꢀdataꢀtoꢀbeꢀwrittenꢀintoꢀtheꢀ
SPIADꢀ(TXRXꢀbuffer)ꢀregister.ꢀForꢀtheꢀMasterꢀMode,ꢀafterꢀdataꢀhasꢀbeenꢀwrittenꢀtoꢀtheꢀSPIADꢀ
(TXRXꢀbuffer)ꢀregister,ꢀthenꢀtransmissionꢀorꢀreceptionꢀwillꢀstartꢀautomatically.ꢀWhenꢀallꢀtheꢀdataꢀhasꢀ
beenꢀtransferredꢀtheꢀSATRFꢀbitꢀshouldꢀbeꢀset.ꢀForꢀtheꢀSlaveꢀMode,ꢀwhenꢀclockꢀpulsesꢀareꢀreceivedꢀ
onꢀSCKA,ꢀdataꢀinꢀtheꢀTXRXꢀbufferꢀwillꢀbeꢀshiftedꢀoutꢀorꢀdataꢀonꢀSDIAꢀwillꢀbeꢀshiftedꢀin.
ToꢀDisableꢀtheꢀSPIAꢀbusꢀSCKA,ꢀSDIA,ꢀSDOA,ꢀSCSAꢀwillꢀbecomeꢀI/Oꢀpinsꢀorꢀotherꢀpin-sharedꢀ
functions.
SPIA Operation
Allꢀcommunicationꢀisꢀcarriedꢀoutꢀusingꢀtheꢀ4-lineꢀinterfaceꢀforꢀeitherꢀMasterꢀorꢀSlaveꢀMode.
TheꢀSACSENꢀbitꢀinꢀtheꢀSPIAC1ꢀregisterꢀcontrolsꢀtheꢀoverallꢀfunctionꢀofꢀtheꢀSPIAꢀinterface.ꢀSettingꢀ
thisꢀbitꢀhighꢀwillꢀenableꢀtheꢀSPIAꢀinterfaceꢀbyꢀallowingꢀtheꢀSCSAꢀlineꢀtoꢀbeꢀactive,ꢀwhichꢀcanꢀthenꢀ
beꢀusedꢀtoꢀcontrolꢀtheꢀSPIAꢀinterface.ꢀIfꢀtheꢀSACSENꢀbitꢀisꢀlow,ꢀtheꢀSPIAꢀinterfaceꢀwillꢀbeꢀdisabledꢀ
andꢀtheꢀSCSAꢀlineꢀwillꢀbeꢀanꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunctionsꢀandꢀcanꢀthereforeꢀnotꢀbeꢀusedꢀforꢀ
controlꢀofꢀtheꢀSPIAꢀinterface.ꢀIfꢀtheꢀSACSENꢀbitꢀandꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀregisterꢀareꢀsetꢀ
high,ꢀthisꢀwillꢀplaceꢀtheꢀSDIAꢀlineꢀinꢀaꢀfloatingꢀconditionꢀandꢀtheꢀSDOAꢀlineꢀhigh.ꢀIfꢀinꢀMasterꢀModeꢀ
theꢀSCKAꢀlineꢀwillꢀbeꢀeitherꢀhighꢀorꢀlowꢀdependingꢀuponꢀtheꢀclockꢀpolarityꢀselectionꢀbitꢀSACKPOLꢀ
inꢀtheꢀSPIAC1ꢀregister.ꢀIfꢀinꢀSlaveꢀModeꢀtheꢀSCKAꢀlineꢀwillꢀbeꢀinꢀaꢀfloatingꢀcondition.ꢀIfꢀSPIAENꢀisꢀ
lowꢀthenꢀtheꢀbusꢀwillꢀbeꢀdisabledꢀandꢀSCSA,ꢀSDIA,ꢀSDOAꢀandꢀSCKAꢀpinsꢀwillꢀallꢀbecomeꢀI/Oꢀpinsꢀ
orꢀotherꢀpin-sharedꢀfunctions.ꢀInꢀtheꢀMasterꢀModeꢀtheꢀMasterꢀwillꢀalwaysꢀgenerateꢀtheꢀclockꢀsignal.ꢀ
TheꢀclockꢀandꢀdataꢀtransmissionꢀwillꢀbeꢀinitiatedꢀafterꢀdataꢀhasꢀbeenꢀwrittenꢀintoꢀtheꢀSPIADꢀregister.ꢀ
InꢀtheꢀSlaveꢀMode,ꢀtheꢀclockꢀsignalꢀwillꢀbeꢀreceivedꢀfromꢀanꢀexternalꢀmasterꢀdeviceꢀforꢀbothꢀdataꢀ
transmissionꢀandꢀreception.ꢀTheꢀfollowingꢀsequencesꢀshowꢀtheꢀorderꢀtoꢀbeꢀfollowedꢀforꢀdataꢀtransferꢀ
inꢀbothꢀMasterꢀandꢀSlaveꢀMode.
Master Mode:
•ꢀ Stepꢀ1
SelectꢀtheꢀclockꢀsourceꢀandꢀMasterꢀmodeꢀusingꢀtheꢀSASPI2~SASPI0ꢀbitsꢀinꢀtheꢀSPIAC0ꢀcontrolꢀ
register
•ꢀ Stepꢀ2
SetupꢀtheꢀSACSENꢀbitꢀandꢀsetupꢀtheꢀSAMLSꢀbitꢀtoꢀchooseꢀifꢀtheꢀdataꢀisꢀMSBꢀorꢀLSBꢀshiftedꢀ
first,ꢀthisꢀmustꢀbeꢀsameꢀasꢀtheꢀSlaveꢀdevice.
•ꢀ Stepꢀ3
SetupꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀcontrolꢀregisterꢀtoꢀenableꢀtheꢀSPIAꢀinterface.
•ꢀ Stepꢀ4
Forꢀwriteꢀoperations:ꢀwriteꢀtheꢀdataꢀtoꢀtheꢀSPIADꢀregister,ꢀwhichꢀwillꢀactuallyꢀplaceꢀtheꢀdataꢀintoꢀ
theꢀTXRXꢀbuffer.ꢀThenꢀuseꢀtheꢀSCKAꢀandꢀSCSAꢀlinesꢀtoꢀoutputꢀtheꢀdata.ꢀAfterꢀthisꢀgoꢀtoꢀstepꢀ5.
Forꢀreadꢀoperations:ꢀtheꢀdataꢀtransferredꢀinꢀonꢀtheꢀSDIAꢀlineꢀwillꢀbeꢀstoredꢀinꢀtheꢀTXRXꢀbufferꢀ
untilꢀallꢀtheꢀdataꢀhasꢀbeenꢀreceivedꢀatꢀwhichꢀpointꢀitꢀwillꢀbeꢀlatchedꢀintoꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ5
CheckꢀtheꢀSAWCOLꢀbitꢀifꢀsetꢀhighꢀthenꢀaꢀcollisionꢀerrorꢀhasꢀoccurredꢀsoꢀreturnꢀtoꢀstepꢀ4.ꢀIfꢀequalꢀ
toꢀzeroꢀthenꢀgoꢀtoꢀtheꢀfollowingꢀstep.
•ꢀ Stepꢀ6
CheckꢀtheꢀSATRFꢀbitꢀorꢀwaitꢀforꢀaꢀSPIAꢀserialꢀbusꢀinterrupt.
Rev. 1.00
187
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
•ꢀ Stepꢀ7
ReadꢀdataꢀfromꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ8
ClearꢀSATRF.
•ꢀ Stepꢀ9
Goꢀtoꢀstepꢀ4.
Slave Mode:
•ꢀ Stepꢀ1
SelectꢀtheꢀSPIꢀSlaveꢀmodeꢀusingꢀtheꢀSASPI2~SASPI0ꢀbitsꢀinꢀtheꢀSPIAC0ꢀcontrolꢀregister
•ꢀ Stepꢀ2
SetupꢀtheꢀSACSENꢀbitꢀandꢀsetupꢀtheꢀSAMLSꢀbitꢀtoꢀchooseꢀifꢀtheꢀdataꢀisꢀMSBꢀorꢀLSBꢀshiftedꢀ
first,ꢀthisꢀsettingꢀmustꢀbeꢀtheꢀsameꢀwithꢀtheꢀMasterꢀdevice.
•ꢀ Stepꢀ3
SetupꢀtheꢀSPIAENꢀbitꢀinꢀtheꢀSPIAC0ꢀcontrolꢀregisterꢀtoꢀenableꢀtheꢀSPIAꢀinterface.
•ꢀ Stepꢀ4
Forꢀwriteꢀoperations:ꢀwriteꢀtheꢀdataꢀtoꢀtheꢀSPIADꢀregister,ꢀwhichꢀwillꢀactuallyꢀplaceꢀtheꢀdataꢀintoꢀ
theꢀTXRXꢀbuffer.ꢀThenꢀwaitꢀforꢀtheꢀmasterꢀclockꢀSCKAꢀandꢀSCSAꢀsignal.ꢀAfterꢀthis,ꢀgoꢀtoꢀstepꢀ5.
Forꢀreadꢀoperations:ꢀtheꢀdataꢀtransferredꢀinꢀonꢀtheꢀSDIAꢀlineꢀwillꢀbeꢀstoredꢀinꢀtheꢀTXRXꢀbufferꢀ
untilꢀallꢀtheꢀdataꢀhasꢀbeenꢀreceivedꢀatꢀwhichꢀpointꢀitꢀwillꢀbeꢀlatchedꢀintoꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ5
CheckꢀtheꢀSAWCOLꢀbitꢀifꢀsetꢀhighꢀthenꢀaꢀcollisionꢀerrorꢀhasꢀoccurredꢀsoꢀreturnꢀtoꢀstepꢀ4.ꢀIfꢀequalꢀ
toꢀzeroꢀthenꢀgoꢀtoꢀtheꢀfollowingꢀstep.
•ꢀ Stepꢀ6
CheckꢀtheꢀSATRFꢀbitꢀorꢀwaitꢀforꢀaꢀSPIAꢀserialꢀbusꢀinterrupt.
•ꢀ Stepꢀ7
ReadꢀdataꢀfromꢀtheꢀSPIADꢀregister.
•ꢀ Stepꢀ8
ClearꢀSATRF.
•ꢀ Stepꢀ9
Goꢀtoꢀstepꢀ4.
Error Detection
TheꢀSAWCOLꢀbitꢀinꢀtheꢀSPIAC1ꢀregisterꢀisꢀprovidedꢀtoꢀindicateꢀerrorsꢀduringꢀdataꢀtransfer.ꢀTheꢀbitꢀ
isꢀsetꢀbyꢀtheꢀSPIAꢀserialꢀInterfaceꢀbutꢀmustꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.ꢀThisꢀbitꢀindicatesꢀ
aꢀdataꢀcollisionꢀhasꢀoccurredꢀwhichꢀhappensꢀifꢀaꢀwriteꢀtoꢀtheꢀSPIADꢀregisterꢀtakesꢀplaceꢀduringꢀaꢀ
dataꢀtransferꢀoperationꢀandꢀwillꢀpreventꢀtheꢀwriteꢀoperationꢀfromꢀcontinuing.
Rev. 1.00
188
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Interrupts
Interruptsꢀareꢀanꢀimportantꢀpartꢀofꢀanyꢀmicrocontrollerꢀsystem.ꢀWhenꢀanꢀexternalꢀeventꢀorꢀanꢀ
internalꢀfunctionꢀsuchꢀasꢀaꢀTimerꢀModuleꢀorꢀanꢀA/Dꢀconverterꢀrequiresꢀmicrocontrollerꢀattention,ꢀ
theirꢀcorrespondingꢀinterruptꢀwillꢀenforceꢀaꢀtemporaryꢀsuspensionꢀofꢀtheꢀmainꢀprogramꢀallowingꢀtheꢀ
microcontrollerꢀtoꢀdirectꢀattentionꢀtoꢀtheirꢀrespectiveꢀneeds.ꢀTheseꢀdevicesꢀcontainꢀseveralꢀexternalꢀ
interruptꢀandꢀinternalꢀinterruptsꢀfunctions.ꢀTheꢀexternalꢀinterruptsꢀareꢀgeneratedꢀbyꢀtheꢀactionꢀofꢀtheꢀ
externalꢀINT0~INT3ꢀandꢀPINTꢀpins,ꢀwhileꢀtheꢀinternalꢀinterruptsꢀareꢀgeneratedꢀbyꢀvariousꢀinternalꢀ
functionsꢀsuchꢀasꢀtheꢀTMs,ꢀComparators,TimeꢀBase,ꢀLVD,ꢀEEPROM,ꢀSIMꢀandꢀtheꢀA/Dꢀconverter.
Interrupt Registers
Overallꢀinterruptꢀcontrol,ꢀwhichꢀbasicallyꢀmeansꢀtheꢀsettingꢀofꢀrequestꢀflagsꢀwhenꢀcertainꢀ
microcontrollerꢀconditionsꢀoccurꢀandꢀtheꢀsettingꢀofꢀinterruptꢀenableꢀbitsꢀbyꢀtheꢀapplicationꢀprogram,ꢀ
isꢀcontrolledꢀbyꢀaꢀseriesꢀofꢀregisters,ꢀlocatedꢀinꢀtheꢀSpecialꢀPurposeꢀDataꢀMemory,ꢀasꢀshownꢀinꢀtheꢀ
accompanyingꢀtable.ꢀTheꢀnumberꢀofꢀregistersꢀdependsꢀuponꢀtheꢀdeviceꢀchosenꢀbutꢀfallꢀintoꢀthreeꢀ
categories.ꢀTheꢀfirstꢀisꢀtheꢀINTC0~INTC3ꢀregistersꢀwhichꢀsetupꢀtheꢀprimaryꢀinterrupts,ꢀtheꢀsecondꢀ
isꢀtheꢀMFI0~MFI4ꢀregistersꢀwhichꢀsetupꢀtheꢀMulti-functionꢀinterrupts.ꢀFinallyꢀthereꢀisꢀanꢀINTEGꢀ
registerꢀtoꢀsetupꢀtheꢀexternalꢀinterruptꢀtriggerꢀedgeꢀtype.
Eachꢀregisterꢀcontainsꢀaꢀnumberꢀofꢀenableꢀbitsꢀtoꢀenableꢀorꢀdisableꢀindividualꢀregistersꢀasꢀwellꢀasꢀ
interruptꢀflagsꢀtoꢀindicateꢀtheꢀpresenceꢀofꢀanꢀinterruptꢀrequest.ꢀTheꢀnamingꢀconventionꢀofꢀtheseꢀ
followsꢀaꢀspecificꢀpattern.ꢀFirstꢀisꢀlistedꢀanꢀabbreviatedꢀinterruptꢀtype,ꢀthenꢀtheꢀ(optional)ꢀnumberꢀofꢀ
thatꢀinterruptꢀfollowedꢀbyꢀeitherꢀanꢀ“E”ꢀforꢀenable/disableꢀbitꢀorꢀ“F”ꢀforꢀrequestꢀflag.
Function
Global
Enable Bit
E�I
Request Flag
—
Notes
—
INTn Pin
Compaꢀatoꢀ
A/D Conveꢀteꢀ
Time Base
�ulti-funꢁtion
SI�
INTnE
CPnE
ADE
INTnF
CPnF
ADF
n=0~ꢅ
n=0~1
—
TBnE
�FnE
SI�E
LVE
TBnF
�FnF
SI�F
LVF
n=0~1
n=0~4
—
—
—
—
—
LVD
EEPRO�
PINT
DEE
DEF
XPE
XPF
SPIA
SPIAE
TnPE
TnAE
TnBE
SPIAF
TnPF
TnAF
TnBF
n=0~5
n=0~5
n=1
T�
Interrupt Register Bit Naming Conventions
Rev. 1.00
189
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Interrupt Register Contents
Bit
Name
7
INTꢅS1
—
6
5
4
3
INT1S1
CP0E
ADE
�FꢅE
—
2
1
0
INTEG
INTC0
INTC1
INTCꢃ
INTCꢅ
�FI0
INTꢅS0
CP0F
�F1F
TB1F
�F4F
TꢃPF
T1BF
TꢅAF
SPIAF
T5PF
INTꢃS1
INT1F
�F0F
TB0F
INTꢅF
TnAF
T1AF
TꢅPF
DEF
INTꢃS0
INT0F
CP1F
�FꢃF
INTꢃF
TnPF
T1PF
XPF
INT1S0
INT1E
�F1E
TB1E
�F4E
TꢃPE
T1BE
TꢅAE
SPIAE
T5PE
INT0S1
INT0E
�F0E
TB0E
INTꢅE
T0AE
T1AE
TꢅPE
DEE
INT0S0
E�I
ADF
�FꢅF
—
CP1E
�FꢃE
INTꢃE
T0PE
T1PE
XPE
TꢃAF
—
TꢃAE
—
�FI1
�FIꢃ
SI�F
—
SI�E
—
�FIꢅ
LVF
LVE
�FI4
T5AF
T4AF
T4PF
T5AE
T4AE
T4PE
INTEG Register
Bit
Name
R/W
7
INTꢅS1
R/W
0
6
INTꢅS0
R/W
0
5
INTꢃS1
R/W
0
4
INTꢃS0
R/W
0
3
INT1S1
R/W
0
2
INT1S0
R/W
0
1
INT0S1
R/W
0
0
INT0S0
R/W
0
POR
Bitꢀ7~6ꢀ
Bitꢀ5~4ꢀ
Bitꢀ3~2ꢀ
Bitꢀ1~0ꢀ
INT3S1, INT3S0: interruptꢀedgeꢀcontrolꢀforꢀINT3ꢀpin
00:ꢀDisable
01:ꢀRisingꢀedge
10:ꢀFallingꢀedge
11:ꢀRisingꢀandꢀfallingꢀedges
INT2S1, INT2S0:ꢀinterruptꢀedgeꢀcontrolꢀforꢀINT2ꢀpin
00:ꢀDisable
01:ꢀRisingꢀedge
10:ꢀFallingꢀedge
11:ꢀRisingꢀandꢀfallingꢀedges
INT1S1, INT1S0:ꢀinterruptꢀedgeꢀcontrolꢀforꢀINT1ꢀpin
00:ꢀDisable
01:ꢀRisingꢀedge
10:ꢀFallingꢀedge
11:ꢀRisingꢀandꢀfallingꢀedges
INT0S1, INT0S0: interruptꢀedgeꢀcontrolꢀforꢀINT0ꢀpin
00:ꢀDisable
01:ꢀRisingꢀedge
10:ꢀFallingꢀedge
11:ꢀRisingꢀandꢀfallingꢀedge
Rev. 1.00
190
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
INTC0 Register
Bit
Name
R/W
7
6
CP0F
R/W
0
5
INT1F
R/W
0
4
INT0F
R/W
0
3
CP0E
R/W
0
2
INT1E
R/W
0
1
INT0E
R/W
0
0
—
—
—
E�I
R/W
0
POR
Bitꢀ7ꢀꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ6ꢀ
Bitꢀ5ꢀ
Bitꢀ4ꢀ
Bitꢀ3ꢀ
Bitꢀ2ꢀ
Bitꢀ1ꢀ
Bitꢀ0ꢀ
CP0F:ꢀComparatorꢀ0ꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
INT1F:ꢀINT1ꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
INT0F:ꢀINT0ꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
CP0E:ꢀComparatorꢀ0ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
INT1E:ꢀINT1ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
INT0E:ꢀINT0ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
EMI:ꢀGlobalꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.00
191
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
INTC1 Register
Bit
Name
R/W
7
6
�F1F
R/W
0
5
�F0F
R/W
0
4
CP1F
R/W
0
3
2
�F1E
R/W
0
1
�F0E
R/W
0
0
CP1E
R/W
0
ADF
R/W
0
ADE
R/W
0
POR
Bitꢀ7ꢀ
Bitꢀ6ꢀ
Bitꢀ5ꢀ
Bitꢀ4ꢀ
Bitꢀ3ꢀ
Bitꢀ2ꢀ
Bitꢀ1ꢀ
Bitꢀ0ꢀ
ADF:ꢀA/DꢀConverterꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
MF1F:ꢀMulti-functionꢀinterruptꢀ1ꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
MF0F:ꢀMulti-functionꢀinterruptꢀ0ꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
CP1F:ꢀComparatorꢀ1ꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
ADE:ꢀA/DꢀConverterꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
MF1E:ꢀMulti-functionꢀinterruptꢀ1ꢀcontrol
0:ꢀDisable
1:ꢀEnable
MF0E:ꢀMulti-functionꢀinterruptꢀ0ꢀcontrol
0:ꢀDisable
1:ꢀEnable
CP1E:ꢀComparatorꢀ1ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.00
19ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
INTC2 Register
Bit
Name
R/W
7
�FꢅF
R/W
0
6
TB1F
R/W
0
5
TB0F
R/W
0
4
�FꢃF
R/W
0
3
�FꢅE
R/W
0
2
TB1E
R/W
0
1
TB0E
R/W
0
0
�FꢃE
R/W
0
POR
Bitꢀ7ꢀ
MF3F:ꢀMulti-functionꢀinterruptꢀ3ꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ6ꢀ
Bitꢀ5ꢀ
Bitꢀ4ꢀ
Bitꢀ3ꢀ
Bitꢀ2ꢀ
Bitꢀ1ꢀ
Bitꢀ0ꢀ
TB1F:ꢀTimeꢀBaseꢀ1ꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
TB0F:ꢀTimeꢀBaseꢀ0ꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
MF2F:ꢀMulti-functionꢀinterruptꢀ2ꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
MF3E:ꢀMulti-functionꢀinterruptꢀ3ꢀcontrol
0:ꢀDisable
1:ꢀEnable
TB1E:ꢀTimeꢀBaseꢀ1ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
TB0E:ꢀTimeꢀBaseꢀ0ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
MF2E:ꢀMulti-functionꢀinterruptꢀ2ꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.00
19ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
INTC3 Register
Bit
Name
R/W
7
6
�F4F
R/W
0
5
INTꢅF
R/W
0
4
INTꢃF
R/W
0
3
—
2
�F4E
R/W
0
1
INTꢅE
R/W
0
0
INTꢃE
R/W
0
—
—
—
R/W
0
POR
Bitꢀ7ꢀ
Bitꢀ6ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
MF4F:ꢀMulti-functionꢀinterruptꢀ4ꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ5ꢀ
Bitꢀ4ꢀ
INT3F:ꢀINT3ꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
INT2F:ꢀINT2ꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ3ꢀ
Bitꢀ2ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
MF4E:ꢀMulti-functionꢀinterruptꢀ4ꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ1ꢀ
Bitꢀ0ꢀ
INT3E:ꢀINT3ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
INT2E:ꢀINT2ꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.00
194
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
MFI0 Register
Bit
Name
R/W
7
TꢃAF
R/W
0
6
TꢃPF
R/W
0
5
T0AF
R/W
0
4
T0PF
R/W
0
3
TꢃAE
R/W
0
2
TꢃPE
R/W
0
1
T0AE
R/W
0
0
T0PE
R/W
0
POR
Bitꢀ7ꢀ
T2AF:ꢀTM2ꢀComparatorꢀAꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ6ꢀ
Bitꢀ5ꢀ
Bitꢀ4ꢀ
Bitꢀ3ꢀ
Bitꢀ2ꢀ
Bitꢀ1ꢀ
Bitꢀ0ꢀ
T2PF:ꢀTM2ꢀComparatorꢀPꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
T0AF:ꢀTM0ꢀComparatorꢀAꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
T0PF:ꢀTM0ꢀComparatorꢀPꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
T2AE:ꢀTM2ꢀComparatorꢀAꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
T2PE:ꢀTM2ꢀComparatorꢀPꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
T0AE:ꢀTM0ꢀComparatorꢀAꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
T0PE:ꢀTM0ꢀComparatorꢀPꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.00
195
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
MFI1 Register
Bit
Name
R/W
7
6
T1BF
R/W
0
5
T1AF
R/W
0
4
T1PF
R/W
0
3
2
T1BE
R/W
0
1
T1AE
R/W
0
0
T1PE
R/W
0
—
—
—
—
—
—
POR
Bitꢀ7ꢀꢀ
Bitꢀ6ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
T1BF:ꢀTM1ꢀComparatorꢀBꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ5ꢀ
Bitꢀ4ꢀ
T1AF:ꢀTM1ꢀComparatorꢀAꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
T1PF:ꢀTM1ꢀComparatorꢀPꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ3ꢀꢀ
Bitꢀ2ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
T1BE:ꢀTM1ꢀComparatorꢀBꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Bitꢀ1ꢀ
Bitꢀ0ꢀ
T1AE:ꢀTM1ꢀComparatorꢀAꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
T1PE:ꢀTM1ꢀComparatorꢀPꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.00
196
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
MFI2 Register
Bit
Name
R/W
7
SI�F
R/W
0
6
TꢅAF
R/W
0
5
TꢅPF
R/W
0
4
3
SI�E
R/W
0
2
TꢅAE
R/W
0
1
TꢅPE
R/W
0
0
XPF
R/W
0
XPE
R/W
0
POR
Bitꢀ7ꢀ
SIMF:ꢀSIMꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ6ꢀ
Bitꢀ5ꢀ
Bitꢀ4ꢀ
Bitꢀ3ꢀ
Bitꢀ2ꢀ
Bitꢀ1ꢀ
Bitꢀ0ꢀ
T3AF:ꢀTM3ꢀComparatorꢀAꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
T3PF:ꢀTM3ꢀComparatorꢀPꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
XPF:ꢀExternalꢀperipheralꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
SIME:ꢀSIMꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
T3AE:ꢀTM3ꢀComparatorꢀAꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
T3PE:ꢀTM3ꢀComparatorꢀPꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
XPE:ꢀExternalꢀperipheralꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
Rev. 1.00
197
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
MFI3 Register
Bit
Name
R/W
7
6
SPIAF
R/W
0
5
4
3
2
SPIAE
R/W
0
1
0
—
—
—
DEF
R/W
0
LVF
R/W
0
—
—
—
DEE
R/W
0
LVE
R/W
0
POR
Bitꢀ7ꢀ
Bitꢀ6ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
SPIAF:ꢀSPIAꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ5ꢀ
Bitꢀ4ꢀ
DEF:ꢀDataꢀEEPROMꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
LVF:ꢀLVDꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ3ꢀ
Bitꢀ2ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
SPIAE:ꢀSPIAꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ1ꢀ
Bitꢀ0ꢀ
DEE:ꢀDataꢀEEPROMꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
LVE:ꢀLVDꢀInterruptꢀControl
0:ꢀDisable
1:ꢀEnable
Rev. 1.00
198
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
MFI4 Register
Bit
Name
R/W
7
T5AF
R/W
0
6
T5PF
R/W
0
5
T4AF
R/W
0
4
T4PF
R/W
0
3
T5AE
R/W
0
2
T5PE
R/W
0
1
T4AE
R/W
0
0
T4PE
R/W
0
POR
Bitꢀ7ꢀ
T5AF:ꢀTM5ꢀComparatorꢀAꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
Bitꢀ6ꢀ
Bitꢀ5ꢀ
Bitꢀ4ꢀ
Bitꢀ3ꢀ
Bitꢀ2ꢀ
Bitꢀ1ꢀ
Bitꢀ0ꢀ
T5PF:ꢀTM5ꢀComparatorꢀPꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
T4AF:ꢀTM4ꢀComparatorꢀAꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
T4PF:ꢀTM4ꢀComparatorꢀPꢀmatchꢀinterruptꢀrequestꢀflag
0:ꢀNoꢀrequest
1:ꢀInterruptꢀrequest
T5AE:ꢀTM5ꢀComparatorꢀAꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
T5PE:ꢀTM5ꢀComparatorꢀPꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
T4AE:ꢀTM4ꢀComparatorꢀAꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
T4PE:ꢀTM4ꢀComparatorꢀPꢀmatchꢀinterruptꢀcontrol
0:ꢀDisable
1:ꢀEnable
Rev. 1.00
199
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Interrupt Operation
E�I auto disabled in ISR
Legend
xxF Request Flagꢄ no auto ꢀeset in ISR
xxF Request Flagꢄ auto ꢀeset in ISR
xxE Enable Bits
Inteꢀꢀupt
Name
Request
Flags
Enable
Bits
�asteꢀ
Enable
Vector Pꢀioꢀity
Higꢂ
04H
INT0 Pin
INT0F
INT0E
INT1E
CP0E
CP1E
�F0E
�F1E
ADE
E�I
E�I
E�I
E�I
E�I
E�I
E�I
E�I
E�I
E�I
E�I
E�I
E�I
E�I
T�ꢃ P
T�ꢃ A
T�0 P
T�0 A
TꢃPF
TꢃAF
T0PF
T0AF
TꢃPE
TꢃAE
T0PE
T0AE
INT1 Pin
INT1F
08H
0CH
10H
14H
18H
1CH
ꢃ0H
ꢃ4H
ꢃ8H
ꢃCH
ꢅ0H
ꢅ4H
Compaꢀatoꢀ 0 CP0F
Compaꢀatoꢀ 1 CP1F
�. Funꢁt. 0
�. Funꢁt. 1
A/D
�F0F
�F1F
ADF
T�1 P
T�1 A
T�1 B
T1PF
T1AF
T1BF
T1PE
T1AE
T1BE
SI�
SI�F
TꢅPF
TꢅAF
XPF
SI�E
TꢅPE
TꢅAE
XPE
�. Funꢁt. ꢃ
�FꢃF
�FꢃE
TB0E
TB1E
�FꢅE
INTꢃE
INTꢅE
�F4E
T�ꢅ P
T�ꢅ A
Time Base 0 TB0F
Time Base 1 TB1F
PINT Pin
LVD
EEPRO�
SPIA
LVF
DEF
LVE
DEE
�. Funꢁt. ꢅ
INTꢃ Pin
�FꢅF
INTꢃF
INTꢅF
�F4F
SPIAF
SPIAE
INTꢅ Pin
T�4 P
T�4 A
T�5 P
T�5 A
T4PF
T4AF
T5PF
T5AF
T4PE
T4AE
T5PE
T5AE
�. Funꢁt. 4
ꢅ8H
Low
Inteꢀꢀupts ꢁontained witꢂin
�ulti-Funꢁtion Inteꢀꢀupts
Interrupt Structure
Rev. 1.00
ꢃ00
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
External Interrupt
TheꢀexternalꢀinterruptsꢀareꢀcontrolledꢀbyꢀsignalꢀtransitionsꢀonꢀtheꢀpinsꢀINT0~INT3.ꢀAnꢀexternalꢀ
interruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀexternalꢀinterruptꢀrequestꢀflags,ꢀINT0F~INT3Fꢀareꢀset,ꢀ
whichꢀwillꢀoccurꢀwhenꢀaꢀtransition,ꢀwhoseꢀtypeꢀisꢀchosenꢀbyꢀtheꢀedgeꢀselectꢀbits,ꢀappearsꢀonꢀtheꢀ
externalꢀinterruptꢀpins.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀ
globalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀrespectiveꢀexternalꢀinterruptꢀenableꢀbit,ꢀINT0E~INT3E,ꢀmustꢀ
firstꢀbeꢀset.ꢀAdditionallyꢀtheꢀcorrectꢀinterruptꢀedgeꢀtypeꢀmustꢀbeꢀselectedꢀusingꢀtheꢀINTEGꢀregisterꢀtoꢀ
enableꢀtheꢀexternalꢀinterruptꢀfunctionꢀandꢀtoꢀchooseꢀtheꢀtriggerꢀedgeꢀtype.ꢀAsꢀtheꢀexternalꢀinterruptꢀ
pinsꢀareꢀpin-sharedꢀwithꢀI/Oꢀpins,ꢀtheyꢀcanꢀonlyꢀbeꢀconfiguredꢀasꢀexternalꢀinterruptꢀpinsꢀifꢀtheirꢀ
externalꢀinterruptꢀenableꢀbitꢀinꢀtheꢀcorrespondingꢀinterruptꢀregisterꢀhasꢀbeenꢀset.ꢀTheꢀpinꢀmustꢀalsoꢀ
beꢀsetupꢀasꢀanꢀinputꢀbyꢀsettingꢀtheꢀcorrespondingꢀbitꢀinꢀtheꢀportꢀcontrolꢀregister.ꢀWhenꢀtheꢀinterruptꢀ
isꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀtheꢀcorrectꢀtransitionꢀtypeꢀappearsꢀonꢀtheꢀexternalꢀinterruptꢀpin,ꢀ
aꢀsubroutineꢀcallꢀtoꢀtheꢀexternalꢀinterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀ
externalꢀinterruptꢀrequestꢀflags,ꢀINT0F~INT3F,ꢀwillꢀbeꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀ
automaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.ꢀNoteꢀthatꢀanyꢀpull-highꢀresistorꢀselectionsꢀonꢀtheꢀ
externalꢀinterruptꢀpinsꢀwillꢀremainꢀvalidꢀevenꢀifꢀtheꢀpinꢀisꢀusedꢀasꢀanꢀexternalꢀinterruptꢀinput.
TheꢀINTEGꢀregisterꢀisꢀusedꢀtoꢀselectꢀtheꢀtypeꢀofꢀactiveꢀedgeꢀthatꢀwillꢀtriggerꢀtheꢀexternalꢀinterrupt.ꢀ
Aꢀchoiceꢀofꢀeitherꢀrisingꢀorꢀfallingꢀorꢀbothꢀedgeꢀtypesꢀcanꢀbeꢀchosenꢀtoꢀtriggerꢀanꢀexternalꢀinterrupt.ꢀ
NoteꢀthatꢀtheꢀINTEGꢀregisterꢀcanꢀalsoꢀbeꢀusedꢀtoꢀdisableꢀtheꢀexternalꢀinterruptꢀfunction.
Comparator Interrupt
Theꢀcomparatorꢀinterruptsꢀareꢀcontrolledꢀbyꢀtheꢀtwoꢀinternalꢀcomparators.ꢀAꢀcomparatorꢀinterruptꢀ
requestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀcomparatorꢀinterruptꢀrequestꢀflags,ꢀCP0FꢀorꢀCP1F,ꢀareꢀset,ꢀaꢀ
situationꢀthatꢀwillꢀoccurꢀwhenꢀtheꢀcomparatorꢀoutputꢀchangesꢀstate.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀ
toꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀcomparatorꢀ
interruptꢀenableꢀbits,ꢀCP0EꢀandꢀCP1E,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀ
notꢀfullꢀandꢀtheꢀcomparatorꢀinputsꢀgenerateꢀaꢀcomparatorꢀoutputꢀtransition,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀ
comparatorꢀinterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀexternalꢀinterruptꢀ
requestꢀflags,ꢀwillꢀbeꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀ
otherꢀinterrupts.
Multi-function Interrupt
WithinꢀtheseꢀdevicesꢀareꢀfiveꢀMulti-functionꢀinterrupts.ꢀUnlikeꢀtheꢀotherꢀindependentꢀinterrupts,ꢀ
theseꢀinterruptsꢀhaveꢀnoꢀindependentꢀsource,ꢀbutꢀratherꢀareꢀformedꢀfromꢀotherꢀexistingꢀinterruptꢀ
sources,ꢀnamelyꢀtheꢀTMꢀInterrupts,ꢀSIMꢀInterrupt,ꢀExternalꢀPeripheralꢀInterrupt,ꢀLVDꢀinterruptꢀandꢀ
EEPROMꢀInterrupt.
AꢀMulti-functionꢀinterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀanyꢀofꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀ
flags,ꢀMF0F~MF5F,ꢀareꢀset.ꢀTheꢀMulti-functionꢀinterruptꢀflagsꢀwillꢀbeꢀsetꢀwhenꢀanyꢀofꢀtheirꢀincludedꢀ
functionsꢀgenerateꢀanꢀinterruptꢀrequestꢀflag.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀ
interruptꢀvectorꢀaddress,ꢀwhenꢀtheꢀMulti-functionꢀinterruptꢀisꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀandꢀ
eitherꢀoneꢀofꢀtheꢀinterruptsꢀcontainedꢀwithinꢀeachꢀofꢀMulti-functionꢀinterruptꢀoccurs,ꢀaꢀsubroutineꢀ
callꢀtoꢀoneꢀofꢀtheꢀMulti-functionꢀinterruptꢀvectorsꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀ
relatedꢀMulti-Functionꢀrequestꢀflag,ꢀwillꢀbeꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀ
clearedꢀtoꢀdisableꢀotherꢀinterrupts.
However,ꢀitꢀmustꢀbeꢀnotedꢀthat,ꢀalthoughꢀtheꢀMulti-functionꢀInterruptꢀflagsꢀwillꢀbeꢀautomaticallyꢀ
resetꢀwhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀrequestꢀflagsꢀfromꢀtheꢀoriginalꢀsourceꢀofꢀtheꢀMulti-
functionꢀinterrupts,ꢀnamelyꢀtheꢀTMꢀInterrupts,ꢀEEPROMꢀInterruptꢀandꢀLVDꢀinterruptꢀwillꢀnotꢀbeꢀ
automaticallyꢀresetꢀandꢀmustꢀbeꢀmanuallyꢀresetꢀbyꢀtheꢀapplicationꢀprogram.
Rev. 1.00
ꢃ01
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
A/D Converter Interrupt
TheꢀA/DꢀConverterꢀInterruptꢀisꢀcontrolledꢀbyꢀtheꢀterminationꢀofꢀanꢀA/Dꢀconversionꢀprocess.ꢀAnꢀA/Dꢀ
ConverterꢀInterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀA/DꢀConverterꢀInterruptꢀrequestꢀflag,ꢀADF,ꢀisꢀ
set,ꢀwhichꢀoccursꢀwhenꢀtheꢀA/Dꢀconversionꢀprocessꢀfinishes.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀ
respectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀA/DꢀInterruptꢀenableꢀbit,ꢀ
ADE,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀtheꢀA/Dꢀconversionꢀ
processꢀhasꢀended,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀA/DꢀConverterꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀ
interruptꢀisꢀserviced,ꢀtheꢀA/DꢀConverterꢀInterruptꢀflag,ꢀADF,ꢀwillꢀbeꢀautomaticallyꢀcleared.ꢀTheꢀEMIꢀ
bitꢀwillꢀalsoꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.
Time Base Interrupt
TheꢀfunctionꢀofꢀtheꢀTimeꢀBaseꢀInterruptꢀisꢀtoꢀprovideꢀregularꢀtimeꢀsignalꢀinꢀtheꢀformꢀofꢀanꢀinternalꢀ
interrupt.ꢀItꢀisꢀcontrolledꢀbyꢀtheꢀoverflowꢀsignalꢀfromꢀitsꢀinternalꢀtimer.ꢀWhenꢀthisꢀhappensꢀitsꢀ
interruptꢀrequestꢀflag,ꢀTBnF,ꢀwillꢀbeꢀset.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀ
vectorꢀaddresses,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMIꢀandꢀTimeꢀBaseꢀenableꢀbit,ꢀTBnE,ꢀmustꢀfirstꢀbeꢀ
set.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀtheꢀTimeꢀBaseꢀoverflows,ꢀaꢀsubroutineꢀ
callꢀtoꢀitsꢀrespectiveꢀvectorꢀlocationꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀinterruptꢀ
requestꢀflag,ꢀTBnF,ꢀwillꢀbeꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀclearedꢀtoꢀdisableꢀotherꢀ
interrupts.
TheꢀpurposeꢀofꢀtheꢀTimeꢀBaseꢀInterruptꢀisꢀtoꢀprovideꢀanꢀinterruptꢀsignalꢀatꢀfixedꢀtimeꢀperiods.ꢀItsꢀ
clockꢀsource,ꢀfTB,ꢀoriginatesꢀfromꢀtheꢀinternalꢀclockꢀsourceꢀfSUB,ꢀfSYS/4,ꢀfSYSꢀorꢀfHꢀandꢀthenꢀpassesꢀ
throughꢀaꢀdivider,ꢀtheꢀdivisionꢀratioꢀofꢀwhichꢀisꢀselectedꢀbyꢀprogrammingꢀtheꢀappropriateꢀbitsꢀinꢀtheꢀ
TBC0ꢀandꢀTBC1ꢀregistersꢀtoꢀobtainꢀlongerꢀinterruptꢀperiodsꢀwhoseꢀvalueꢀranges.ꢀTheꢀclockꢀsourceꢀ
whichꢀinꢀturnꢀcontrolsꢀtheꢀTimeꢀBaseꢀinterruptꢀperiodꢀisꢀselectedꢀusingꢀtheꢀCLKS01ꢀandꢀCLKS00ꢀ
bitsꢀinꢀtheꢀPSC0ꢀregister.
Time Base 0 Inteꢀꢀupt
fSUB
fH
fSYS
fP/ꢃ8 ~ fP/ꢃ15
fTB
Pꢀesꢁaleꢀ
TB0[ꢃ:0 ]
fSYS/4
Time Base 1 Inteꢀꢀupt
TB0EN TB1EN
CLKS0[1:0 ]
TB1[ꢃ:0 ]
Time Base Interrupt
Rev. 1.00
ꢃ0ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
PSC0 Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLKS01 CLKS00
R/W
0
R/W
0
POR
Bitꢀ7~2ꢀꢀ
Bitꢀ1~0
Unimplemented,ꢀreadꢀasꢀ“0”
CLKS01~CLKS00:ꢀTimeꢀBaseꢀclockꢀsourceꢀSelection
00:ꢀfSYS
01:ꢀfSYS/4
10:ꢀfTB
11:ꢀfH
TBC0 Register
Bit
Name
R/W
7
TB0ON
R/W
0
6
5
4
3
2
TB0ꢃ
R/W
0
1
TB01
R/W
0
0
TB00
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7ꢀ
TB0ON:ꢀTimeꢀBaseꢀ0ꢀEnable/DisableꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ6~3ꢀꢀ
Bitꢀ2~0
Unimplemented,ꢀreadꢀasꢀ“0”
TB02~TB00:ꢀTimeꢀBaseꢀ0ꢀTime-outꢀPeriod
000:ꢀ28/fTB
001:ꢀ29/fTB
010:ꢀ210/fTB
011:ꢀ211/fTB
100:ꢀ212/fTB
101:ꢀ213/fTB
110:ꢀ214/fTB
111:ꢀ215/fTB
TBC1 Register
Bit
Name
R/W
7
TB1ON
R/W
0
6
5
4
3
2
TB1ꢃ
R/W
0
1
TB11
R/W
0
0
TB10
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
POR
Bitꢀ7ꢀ
TB1ON:ꢀTimeꢀBaseꢀ1ꢀEnable/DisableꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ6~3ꢀꢀ
Bitꢀ2~0
Unimplemented,ꢀreadꢀasꢀ“0”
TB12~TB10:ꢀTimeꢀBaseꢀ1ꢀTime-outꢀPeriod
000:ꢀ28/fTB
001:ꢀ29/fTB
010:ꢀ210/fTB
011:ꢀ211/fTB
100:ꢀ212/fTB
101:ꢀ213/fTB
110:ꢀ214/fTB
111:ꢀ215/fTB
Rev. 1.00
ꢃ0ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Serial Interface Module Interrupts
TheꢀSerialꢀInterfaceꢀModuleꢀInterrupt,ꢀalsoꢀknownꢀasꢀtheꢀSIMꢀinterrupt,ꢀisꢀcontainedꢀwithinꢀtheꢀ
Multi-functionꢀInterrupt.ꢀAꢀSIMꢀInterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀSIMꢀInterruptꢀrequestꢀ
flag,ꢀSIMF,ꢀisꢀset,ꢀwhichꢀoccursꢀwhenꢀaꢀbyteꢀofꢀdataꢀhasꢀbeenꢀreceivedꢀorꢀtransmittedꢀbyꢀtheꢀSIMꢀ
interface.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀ
interruptꢀenableꢀbit,ꢀEMI,ꢀandꢀtheꢀSerialꢀInterfaceꢀInterruptꢀenableꢀbit,ꢀSIME,ꢀandꢀMuti-functionꢀ
interruptꢀenableꢀbits,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀbyteꢀ
ofꢀdataꢀhasꢀbeenꢀtransmittedꢀorꢀreceivedꢀbyꢀtheꢀSIMꢀinterface,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrespectiveꢀ
Multi-functionꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀSerialꢀInterfaceꢀInterruptꢀisꢀserviced,ꢀtheꢀ
EMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts,ꢀhoweverꢀonlyꢀtheꢀMulti-functionꢀ
interruptꢀrequestꢀflagꢀwillꢀbeꢀalsoꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀSIMFꢀflagꢀwillꢀnotꢀbeꢀautomaticallyꢀ
cleared,ꢀitꢀhasꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.
SPIA Interface Interrupt
TheꢀSPIAꢀInterfaceꢀInterruptꢀisꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀInterrupt.ꢀAꢀSPIAꢀInterruptꢀ
requestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀSPIAꢀInterruptꢀrequestꢀflag,ꢀSPIAF,ꢀisꢀset,ꢀwhichꢀoccursꢀwhenꢀaꢀ
byteꢀofꢀdataꢀhasꢀbeenꢀreceivedꢀorꢀtransmittedꢀbyꢀtheꢀSPIAꢀinterface.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀ
toꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀtheꢀSPIAꢀInterfaceꢀ
Interruptꢀenableꢀbit,ꢀSPIAE,ꢀandꢀMuti-functionꢀinterruptꢀenableꢀbits,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀ
interruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀbyteꢀofꢀdataꢀhasꢀbeenꢀtransmittedꢀorꢀreceivedꢀbyꢀtheꢀ
SPIAꢀinterface,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrespectiveꢀMulti-functionꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀ
WhenꢀtheꢀSPIAꢀInterfaceꢀInterruptꢀisꢀserviced,ꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀ
otherꢀinterrupts,ꢀhoweverꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀalsoꢀautomaticallyꢀ
cleared.ꢀAsꢀtheꢀSPIAFꢀflagꢀwillꢀnotꢀbeꢀautomaticallyꢀcleared,ꢀitꢀhasꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀ
program.
External Peripheral Interrupt
TheꢀExternalꢀPeripheralꢀInterruptꢀoperatesꢀinꢀaꢀsimilarꢀwayꢀtoꢀtheꢀexternalꢀinterruptꢀandꢀisꢀcontainedꢀ
withinꢀtheꢀMulti-functionꢀInterrupt.ꢀAꢀPeripheralꢀInterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀExternalꢀ
PeripheralꢀInterruptꢀrequestꢀflag,ꢀXPF,ꢀisꢀset,ꢀwhichꢀoccursꢀwhenꢀaꢀnegativeꢀedgeꢀtransitionꢀappearsꢀ
onꢀtheꢀPINTꢀpin.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀ
globalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀexternalꢀperipheralꢀinterruptꢀenableꢀbit,ꢀXPE,ꢀandꢀassociatedꢀ
Multi-functionꢀinterruptꢀenableꢀbit,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀ
fullꢀandꢀaꢀnegativeꢀtransitionꢀappearsꢀonꢀtheꢀExternalꢀPeripheralꢀInterruptꢀpin,ꢀaꢀsubroutineꢀcallꢀtoꢀ
theꢀrespectiveꢀMulti-functionꢀInterrupt,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀExternalꢀPeripheralꢀInterruptꢀisꢀ
serviced,ꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts,ꢀhoweverꢀonlyꢀtheꢀ
Multi-functionꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀalsoꢀautomaticallyꢀcleared.
AsꢀtheꢀXPFꢀflagꢀwillꢀnotꢀbeꢀautomaticallyꢀcleared,ꢀitꢀhasꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.ꢀ
Theꢀexternalꢀperipheralꢀinterruptꢀpinꢀisꢀpin-sharedꢀwithꢀseveralꢀotherꢀpinsꢀwithꢀdifferentꢀfunctions.ꢀItꢀ
mustꢀthereforeꢀbeꢀproperlyꢀconfiguredꢀtoꢀenableꢀitꢀtoꢀoperateꢀasꢀanꢀExternalꢀPeripheralꢀInterruptꢀpin.
Rev. 1.00
ꢃ04
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
EEPROM Interrupt
TheꢀEEPROMꢀInterrupt,ꢀisꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀInterrupt.ꢀAnꢀEEPROMꢀInterruptꢀ
requestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀEEPROMꢀInterruptꢀrequestꢀflag,ꢀDEF,ꢀisꢀset,ꢀwhichꢀoccursꢀwhenꢀ
anꢀEEPROMꢀWriteꢀcycleꢀends.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀ
address,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀEEPROMꢀInterruptꢀenableꢀbit,ꢀDEE,ꢀandꢀassociatedꢀ
Multi-functionꢀinterruptꢀenableꢀbit,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀ
fullꢀandꢀanꢀEEPROMꢀWriteꢀcycleꢀends,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrespectiveꢀMulti-functionꢀInterruptꢀ
vector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀEEPROMꢀInterruptꢀisꢀserviced,ꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀ
clearedꢀtoꢀdisableꢀotherꢀinterrupts,ꢀhoweverꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀ
alsoꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀDEFꢀflagꢀwillꢀnotꢀbeꢀautomaticallyꢀcleared,ꢀitꢀhasꢀtoꢀbeꢀclearedꢀbyꢀ
theꢀapplicationꢀprogram.
LVD Interrupt
TheꢀLowꢀVoltageꢀDetectorꢀInterruptꢀisꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀInterrupt.ꢀAnꢀLVDꢀ
InterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀLVDꢀInterruptꢀrequestꢀflag,ꢀLVF,ꢀisꢀset,ꢀwhichꢀoccursꢀ
whenꢀtheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀdetectsꢀaꢀlowꢀpowerꢀsupplyꢀvoltage.ꢀToꢀallowꢀtheꢀprogramꢀ
toꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀLowꢀVoltageꢀ
Interruptꢀenableꢀbit,ꢀLVE,ꢀandꢀassociatedꢀMulti-functionꢀinterruptꢀenableꢀbit,ꢀmustꢀfirstꢀbeꢀset.ꢀWhenꢀ
theꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀlowꢀvoltageꢀconditionꢀoccurs,ꢀaꢀsubroutineꢀcallꢀtoꢀ
theꢀMulti-functionꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀLowꢀVoltageꢀInterruptꢀisꢀserviced,ꢀtheꢀ
EMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts,ꢀhoweverꢀonlyꢀtheꢀMulti-functionꢀ
interruptꢀrequestꢀflagꢀwillꢀbeꢀalsoꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀLVFꢀflagꢀwillꢀnotꢀbeꢀautomaticallyꢀ
cleared,ꢀitꢀhasꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.
TM Interrupts
TheꢀCompactꢀTMꢀhasꢀtwoꢀinterrupts,ꢀwhileꢀtheꢀEnhancedꢀTypeꢀTMꢀhasꢀthreeꢀinterrupts.ꢀAllꢀofꢀ
theꢀTMꢀinterruptsꢀareꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀInterrupts.ꢀForꢀtheꢀCompactꢀTypeꢀTMꢀ
thereꢀareꢀtwoꢀinterruptꢀrequestꢀflagsꢀTnPFꢀandꢀTnAFꢀandꢀtwoꢀenableꢀbitsꢀTnPEꢀandꢀTnAE.ꢀForꢀtheꢀ
EnhancedꢀTypeꢀTMꢀthereꢀareꢀthreeꢀinterruptꢀrequestꢀflagsꢀTnPF,ꢀTnAFꢀandꢀTnBFꢀandꢀthreeꢀenableꢀ
bitsꢀTnPE,ꢀTnAEꢀandꢀTnBE.ꢀAꢀTMꢀinterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀanyꢀofꢀtheꢀTMꢀrequestꢀ
flagsꢀareꢀset,ꢀaꢀsituationꢀwhichꢀoccursꢀwhenꢀaꢀTMꢀcomparatorꢀP,ꢀAꢀorꢀBꢀmatchꢀsituationꢀhappens.
Toꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀ
bit,ꢀEMI,ꢀrespectiveꢀTMꢀInterruptꢀenableꢀbit,ꢀandꢀrelevantꢀMulti-functionꢀInterruptꢀenableꢀbit,ꢀMFnE,ꢀ
mustꢀfirstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀTMꢀcomparatorꢀmatchꢀ
situationꢀoccurs,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrelevantꢀMulti-functionꢀInterruptꢀvectorꢀlocations,ꢀwillꢀtakeꢀ
place.ꢀWhenꢀtheꢀTMꢀinterruptꢀisꢀserviced,ꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀ
interrupts,ꢀhoweverꢀonlyꢀtheꢀrelatedꢀMFnFꢀflagꢀwillꢀbeꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀTMꢀinterruptꢀ
requestꢀflagsꢀwillꢀnotꢀbeꢀautomaticallyꢀcleared,ꢀtheyꢀhaveꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.
Rev. 1.00
ꢃ05
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Interrupt Wake-up Function
Eachꢀofꢀtheꢀinterruptꢀfunctionsꢀhasꢀtheꢀcapabilityꢀofꢀwakingꢀupꢀtheꢀmicrocontrollerꢀwhenꢀinꢀtheꢀ
SLEEPꢀorꢀIDLEꢀMode.ꢀAꢀwake-upꢀisꢀgeneratedꢀwhenꢀanꢀinterruptꢀrequestꢀflagꢀchangesꢀfromꢀlowꢀ
toꢀhighꢀandꢀisꢀindependentꢀofꢀwhetherꢀtheꢀinterruptꢀisꢀenabledꢀorꢀnot.ꢀTherefore,ꢀevenꢀthoughꢀtheseꢀ
devicesꢀareꢀinꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀandꢀitsꢀsystemꢀoscillatorꢀstopped,ꢀsituationsꢀsuchꢀasꢀ
externalꢀedgeꢀtransitionsꢀonꢀtheꢀexternalꢀinterruptꢀpins,ꢀaꢀlowꢀpowerꢀsupplyꢀvoltageꢀorꢀcomparatorꢀ
inputꢀchangeꢀmayꢀcauseꢀtheirꢀrespectiveꢀinterruptꢀflagꢀtoꢀbeꢀsetꢀhighꢀandꢀconsequentlyꢀgenerateꢀ
anꢀinterrupt.ꢀCareꢀmustꢀthereforeꢀbeꢀtakenꢀifꢀspuriousꢀwake-upꢀsituationsꢀareꢀtoꢀbeꢀavoided.ꢀIfꢀanꢀ
interruptꢀwake-upꢀfunctionꢀisꢀtoꢀbeꢀdisabledꢀthenꢀtheꢀcorrespondingꢀinterruptꢀrequestꢀflagꢀshouldꢀbeꢀ
setꢀhighꢀbeforeꢀtheꢀdeviceꢀentersꢀtheꢀSLEEPꢀorꢀIDLEꢀMode.ꢀTheꢀinterruptꢀenableꢀbitsꢀhaveꢀnoꢀeffectꢀ
onꢀtheꢀinterruptꢀwake-upꢀfunction.
Programming Considerations
Byꢀdisablingꢀtheꢀrelevantꢀinterruptꢀenableꢀbits,ꢀaꢀrequestedꢀinterruptꢀcanꢀbeꢀpreventedꢀfromꢀbeingꢀ
serviced,ꢀhowever,ꢀonceꢀanꢀinterruptꢀrequestꢀflagꢀisꢀset,ꢀitꢀwillꢀremainꢀinꢀthisꢀconditionꢀinꢀtheꢀ
interruptꢀregisterꢀuntilꢀtheꢀcorrespondingꢀinterruptꢀisꢀservicedꢀorꢀuntilꢀtheꢀrequestꢀflagꢀisꢀclearedꢀbyꢀ
theꢀapplicationꢀprogram.ꢀ
WhereꢀaꢀcertainꢀinterruptꢀisꢀcontainedꢀwithinꢀaꢀMulti-functionꢀinterrupt,ꢀthenꢀwhenꢀtheꢀinterruptꢀ
serviceꢀroutineꢀisꢀexecuted,ꢀasꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀflags,ꢀMFnF,ꢀwillꢀbeꢀ
automaticallyꢀcleared,ꢀtheꢀindividualꢀrequestꢀflagꢀforꢀtheꢀfunctionꢀneedsꢀtoꢀbeꢀclearedꢀbyꢀtheꢀ
applicationꢀprogram.
Itꢀisꢀrecommendedꢀthatꢀprogramsꢀdoꢀnotꢀuseꢀtheꢀ“CALL”ꢀinstructionꢀwithinꢀtheꢀinterruptꢀserviceꢀ
subroutine.ꢀInterruptsꢀoftenꢀoccurꢀinꢀanꢀunpredictableꢀmannerꢀorꢀneedꢀtoꢀbeꢀservicedꢀimmediately.ꢀ
Ifꢀonlyꢀoneꢀstackꢀisꢀleftꢀandꢀtheꢀinterruptꢀisꢀnotꢀwellꢀcontrolled,ꢀtheꢀoriginalꢀcontrolꢀsequenceꢀwillꢀbeꢀ
damagedꢀonceꢀaꢀCALLꢀsubroutineꢀisꢀexecutedꢀinꢀtheꢀinterruptꢀsubroutine.
EveryꢀinterruptꢀhasꢀtheꢀcapabilityꢀofꢀwakingꢀupꢀtheꢀmicrocontrollerꢀwhenꢀitꢀisꢀinꢀtheꢀSLEEPꢀorꢀIDLEꢀ
Mode,ꢀtheꢀwakeꢀupꢀbeingꢀgeneratedꢀwhenꢀtheꢀinterruptꢀrequestꢀflagꢀchangesꢀfromꢀlowꢀtoꢀhigh.ꢀIfꢀitꢀisꢀ
requiredꢀtoꢀpreventꢀaꢀcertainꢀinterruptꢀfromꢀwakingꢀupꢀtheꢀmicrocontrollerꢀthenꢀitsꢀrespectiveꢀrequestꢀ
flagꢀshouldꢀbeꢀfirstꢀsetꢀhighꢀbeforeꢀenterꢀSLEEPꢀorꢀIDLEꢀMode.
AsꢀonlyꢀtheꢀProgramꢀCounterꢀisꢀpushedꢀontoꢀtheꢀstack,ꢀthenꢀwhenꢀtheꢀinterruptꢀisꢀserviced,ꢀifꢀtheꢀ
contentsꢀofꢀtheꢀaccumulator,ꢀstatusꢀregisterꢀorꢀotherꢀregistersꢀareꢀalteredꢀbyꢀtheꢀinterruptꢀserviceꢀ
program,ꢀtheirꢀcontentsꢀshouldꢀbeꢀsavedꢀtoꢀtheꢀmemoryꢀatꢀtheꢀbeginningꢀofꢀtheꢀinterruptꢀserviceꢀ
routine.ꢀ
Toꢀreturnꢀfromꢀanꢀinterruptꢀsubroutine,ꢀeitherꢀaꢀRETꢀorꢀRETIꢀinstructionꢀmayꢀbeꢀexecuted.ꢀTheꢀRETIꢀ
instructionꢀinꢀadditionꢀtoꢀexecutingꢀaꢀreturnꢀtoꢀtheꢀmainꢀprogramꢀalsoꢀautomaticallyꢀsetsꢀtheꢀEMIꢀ
bitꢀhighꢀtoꢀallowꢀfurtherꢀinterrupts.ꢀTheꢀRETꢀinstructionꢀhoweverꢀonlyꢀexecutesꢀaꢀreturnꢀtoꢀtheꢀmainꢀ
programꢀleavingꢀtheꢀEMIꢀbitꢀinꢀitsꢀpresentꢀzeroꢀstateꢀandꢀthereforeꢀdisablingꢀtheꢀexecutionꢀofꢀfurtherꢀ
interrupts.
Rev. 1.00
ꢃ06
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Low Voltage Detector – LVD
EachꢀdeviceꢀhasꢀaꢀLowꢀVoltageꢀDetectorꢀfunction,ꢀalsoꢀknownꢀasꢀLVD.ꢀThisꢀenabledꢀtheꢀdeviceꢀtoꢀ
monitorꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀVDD,ꢀandꢀprovideꢀaꢀwarningꢀsignalꢀshouldꢀitꢀfallꢀbelowꢀaꢀcertainꢀ
level.ꢀThisꢀfunctionꢀmayꢀbeꢀespeciallyꢀusefulꢀinꢀbatteryꢀapplicationsꢀwhereꢀtheꢀsupplyꢀvoltageꢀwillꢀ
graduallyꢀreduceꢀasꢀtheꢀbatteryꢀages,ꢀasꢀitꢀallowsꢀanꢀearlyꢀwarningꢀbatteryꢀlowꢀsignalꢀtoꢀbeꢀgenerated.ꢀ
TheꢀLowꢀVoltageꢀDetectorꢀalsoꢀhasꢀtheꢀcapabilityꢀofꢀgeneratingꢀanꢀinterruptꢀsignal.
LVD Register
TheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀisꢀcontrolledꢀusingꢀaꢀsingleꢀregisterꢀwithꢀtheꢀnameꢀLVDC.ꢀThreeꢀ
bitsꢀinꢀthisꢀregister,ꢀVLVD2~VLVD0,ꢀareꢀusedꢀtoꢀselectꢀoneꢀofꢀeightꢀfixedꢀvoltagesꢀbelowꢀwhichꢀ
aꢀlowꢀvoltageꢀconditionꢀwillꢀbeꢀdetermined.ꢀAꢀlowꢀvoltageꢀconditionꢀisꢀindicatedꢀwhenꢀtheꢀLVDOꢀ
bitꢀisꢀset.ꢀIfꢀtheꢀLVDOꢀbitꢀisꢀlow,ꢀthisꢀindicatesꢀthatꢀtheꢀVDDꢀvoltageꢀisꢀaboveꢀtheꢀpresetꢀlowꢀvoltageꢀ
value.ꢀTheꢀLVDENꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀlowꢀvoltageꢀdetector.ꢀ
Settingꢀtheꢀbitꢀhighꢀwillꢀenableꢀtheꢀlowꢀvoltageꢀdetector.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀwillꢀswitchꢀoffꢀtheꢀ
internalꢀlowꢀvoltageꢀdetectorꢀcircuits.ꢀAsꢀtheꢀlowꢀvoltageꢀdetectorꢀwillꢀconsumeꢀaꢀcertainꢀamountꢀofꢀ
power,ꢀitꢀmayꢀbeꢀdesirableꢀtoꢀswitchꢀoffꢀtheꢀcircuitꢀwhenꢀnotꢀinꢀuse,ꢀanꢀimportantꢀconsiderationꢀinꢀ
powerꢀsensitiveꢀbatteryꢀpoweredꢀapplications.
LVDC Register
Bit
Name
R/W
7
6
5
LVDO
R
4
LVDEN
R/W
0
3
2
VLVDꢃ
R/W
0
1
VLVD1
R/W
0
0
VLVD0
R/W
0
—
—
—
—
—
—
—
—
—
POR
0
Bitꢀ7~6ꢀꢀ
Bitꢀ5ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
LVDO:ꢀLVDꢀOutputꢀFlag
0:ꢀNoꢀLowꢀVoltageꢀDetected
1:ꢀLowꢀVoltageꢀDetected
Bitꢀ4
LVDEN:ꢀLowꢀVoltageꢀDetectorꢀEnable/Disable
0:ꢀDisable
1:ꢀEnable
Bitꢀ3ꢀꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Bitꢀ2~0ꢀ
VLVD2~VLVD0:ꢀSelectꢀLVDꢀVoltage
000:ꢀ2.0V
001:ꢀ2.2V
010:ꢀ2.4V
011:ꢀ2.7V
100:ꢀ3.0V
101:ꢀ3.3V
110:ꢀ3.6V
111:ꢀ4.0V
Rev. 1.00
ꢃ07
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
LVD Operation
TheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀoperatesꢀbyꢀcomparingꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀVDD,ꢀwithꢀaꢀ
pre-specifiedꢀvoltageꢀlevelꢀstoredꢀinꢀtheꢀLVDCꢀregister.ꢀThisꢀhasꢀaꢀrangeꢀofꢀbetweenꢀ2.0Vꢀandꢀ4.0V.ꢀ
Whenꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀVDD,ꢀfallsꢀbelowꢀthisꢀpre-determinedꢀvalue,ꢀtheꢀLVDOꢀbitꢀwillꢀbeꢀ
setꢀhighꢀindicatingꢀaꢀlowꢀpowerꢀsupplyꢀvoltageꢀcondition.ꢀTheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀisꢀ
suppliedꢀbyꢀaꢀreferenceꢀvoltageꢀwhichꢀwillꢀbeꢀautomaticallyꢀenabled.ꢀWhenꢀtheꢀdeviceꢀisꢀpoweredꢀ
downꢀtheꢀlowꢀvoltageꢀdetectorꢀwillꢀremainꢀactiveꢀifꢀtheꢀLVDENꢀbitꢀisꢀhigh.ꢀAfterꢀenablingꢀtheꢀLowꢀ
VoltageꢀDetector,ꢀaꢀtimeꢀdelayꢀtLVDSꢀshouldꢀbeꢀallowedꢀforꢀtheꢀcircuitryꢀtoꢀstabiliseꢀbeforeꢀreadingꢀtheꢀ
LVDOꢀbit.ꢀNoteꢀalsoꢀthatꢀasꢀtheꢀVDDꢀvoltageꢀmayꢀriseꢀandꢀfallꢀratherꢀslowly,ꢀatꢀtheꢀvoltageꢀnearsꢀthatꢀ
ofꢀVLVD,ꢀthereꢀmayꢀbeꢀmultipleꢀbitꢀLVDOꢀtransitions.
V
D
D
V
L
D
V
L
D
V
N
E
L
D
V
O
t
L
D
V
S
LVD Operation
TheꢀLowꢀVoltageꢀDetectorꢀalsoꢀhasꢀitsꢀownꢀinterruptꢀwhichꢀisꢀcontainedꢀwithinꢀoneꢀofꢀtheꢀ
Multi-functionꢀinterrupts,ꢀprovidingꢀanꢀalternativeꢀmeansꢀofꢀlowꢀvoltageꢀdetection,ꢀinꢀadditionꢀtoꢀ
pollingꢀtheꢀLVDOꢀbit.ꢀTheꢀinterruptꢀwillꢀonlyꢀbeꢀgeneratedꢀafterꢀaꢀdelayꢀofꢀtLVDꢀafterꢀtheꢀLVDOꢀbitꢀ
hasꢀbeenꢀsetꢀhighꢀbyꢀaꢀlowꢀvoltageꢀcondition.ꢀWhenꢀtheꢀdeviceꢀisꢀpoweredꢀdownꢀtheꢀLowꢀVoltageꢀ
DetectorꢀwillꢀremainꢀactiveꢀifꢀtheꢀLVDENꢀbitꢀisꢀhigh.ꢀInꢀthisꢀcase,ꢀtheꢀLVFꢀinterruptꢀrequestꢀflagꢀ
willꢀbeꢀset,ꢀcausingꢀanꢀinterruptꢀtoꢀbeꢀgeneratedꢀifꢀVDDꢀfallsꢀbelowꢀtheꢀpresetꢀLVDꢀvoltage.ꢀThisꢀwillꢀ
causeꢀtheꢀdeviceꢀtoꢀwake-upꢀfromꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀhoweverꢀifꢀtheꢀLowꢀVoltageꢀDetectorꢀ
wakeꢀupꢀfunctionꢀisꢀnotꢀrequiredꢀthenꢀtheꢀLVFꢀflagꢀshouldꢀbeꢀfirstꢀsetꢀhighꢀbeforeꢀtheꢀdeviceꢀentersꢀ
theꢀSLEEPꢀorꢀIDLEꢀMode.
Rev. 1.00
ꢃ08
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SCOM Function for LCD
TheꢀdevicesꢀhaveꢀtheꢀcapabilityꢀofꢀdrivingꢀexternalꢀLCDꢀpanels.ꢀTheꢀcommonꢀpinsꢀforꢀLCDꢀdriving,ꢀ
SCOM0~SCOM3,ꢀareꢀpinꢀsharedꢀwithꢀtheꢀPC0~PC1,ꢀPC6~PC7ꢀpins.ꢀTheꢀLCDꢀsignalsꢀ(COMꢀandꢀ
SEG)ꢀareꢀgeneratedꢀusingꢀtheꢀapplicationꢀprogram.
LCD Operation
AnꢀexternalꢀLCDꢀpanelꢀcanꢀbeꢀdrivenꢀusingꢀthisꢀdeviceꢀbyꢀconfiguringꢀtheꢀPC0~PC1,ꢀPC6~PC7ꢀ
pinsꢀasꢀcommonꢀpinsꢀandꢀusingꢀotherꢀoutputꢀportsꢀlinesꢀasꢀsegmentꢀpins.ꢀTheꢀLCDꢀdriverꢀfunctionꢀ
isꢀcontrolledꢀusingꢀtheꢀSCOMCꢀregisterꢀwhichꢀinꢀadditionꢀtoꢀcontrollingꢀtheꢀoverallꢀon/offꢀfunctionꢀ
alsoꢀcontrolsꢀtheꢀbiasꢀvoltageꢀsetupꢀfunction.ꢀThisꢀenablesꢀtheꢀLCDꢀCOMꢀdriverꢀtoꢀgenerateꢀtheꢀ
necessaryꢀVDD/2ꢀvoltageꢀlevelsꢀforꢀLCDꢀ1/2ꢀbiasꢀoperation.
TheꢀSCOMENꢀbitꢀinꢀtheꢀSCOMCꢀregisterꢀisꢀtheꢀoverallꢀmasterꢀcontrolꢀforꢀtheꢀLCDꢀdriver.ꢀTheꢀ
LCDꢀSCOMnꢀpinꢀisꢀselectedꢀtoꢀbeꢀusedꢀforꢀLCDꢀdrivingꢀbyꢀtheꢀcorrespondingꢀpin-sharedꢀfunctionꢀ
selectionꢀbits.ꢀNoteꢀthatꢀtheꢀPortꢀControlꢀregisterꢀdoesꢀnotꢀneedꢀtoꢀfirstꢀsetupꢀtheꢀpinsꢀasꢀoutputsꢀtoꢀ
enableꢀtheꢀLCDꢀdriverꢀoperation.
V
D
D
S
O
C
M
o
p
r
t
e
a
n
i
g
u
c
r
e
r
n
t
V
D
/
D
2
S
O
C
M
0
~
S
O
C
M
3
P
n
i
s
-
a
h
e
r
d
s
l
e
c
e
i
o
t
n
b
t
i
s
S
O
C
M
E
N
LCD COM Bias
LCD Bias Control
TheꢀLCDꢀCOMꢀdriverꢀenablesꢀaꢀrangeꢀofꢀselectionsꢀtoꢀbeꢀprovidedꢀtoꢀsuitꢀtheꢀrequirementꢀofꢀtheꢀ
LCDꢀpanelꢀwhichꢀisꢀbeingꢀused.ꢀTheꢀbiasꢀresistorꢀchoiceꢀisꢀimplementedꢀusingꢀtheꢀISEL1ꢀandꢀISEL0ꢀ
bitsꢀinꢀtheꢀSCOMCꢀregister.
SCOMC Register
Bit
Name
R/W
7
D7
R/W
0
6
ISEL1
R/W
0
5
4
3
2
1
0
ISEL0 SCO�EN
—
—
—
—
—
—
—
—
—
—
—
—
R/W
0
R/W
0
POR
Bitꢀ7ꢀ
ReservedꢀBit
0:ꢀCorrectꢀlevelꢀ-ꢀbitꢀmustꢀbeꢀresetꢀtoꢀzeroꢀforꢀcorrectꢀoperation
1:ꢀUnpredictableꢀoperationꢀ-ꢀbitꢀmustꢀnotꢀbeꢀsetꢀhigh
Bitꢀ6~5
ISEL1, ISEL0:ꢀSelectꢀSCOMꢀtypicalꢀbiasꢀcurrentꢀ(VDD=5V)
00:ꢀ25μA
01:ꢀ50μA
10:ꢀ100μA
11:ꢀ200μA
Bitꢀ4
SCOMEN:ꢀSCOMꢀmoduleꢀControl
0:ꢀDisable
1:ꢀEnable
Bitꢀ3~0ꢀ
Unimplemented,ꢀreadꢀasꢀ“0”
Rev. 1.00
ꢃ09
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Configuration Options
ConfigurationꢀoptionsꢀreferꢀtoꢀcertainꢀoptionsꢀwithinꢀtheꢀMCUꢀthatꢀareꢀprogrammedꢀintoꢀtheꢀdevicesꢀ
duringꢀtheꢀprogrammingꢀprocess.ꢀDuringꢀtheꢀdevelopmentꢀprocess,ꢀtheseꢀoptionsꢀareꢀselectedꢀusingꢀ
theꢀHT-IDEꢀsoftwareꢀdevelopmentꢀtools.ꢀAsꢀtheseꢀoptionsꢀareꢀprogrammedꢀintoꢀtheꢀdevicesꢀusingꢀ
theꢀhardwareꢀprogrammingꢀtools,ꢀonceꢀtheyꢀareꢀselectedꢀtheyꢀcannotꢀbeꢀchangedꢀlaterꢀusingꢀtheꢀ
applicationꢀprogram.ꢀAllꢀoptionsꢀmustꢀbeꢀdefinedꢀforꢀproperꢀsystemꢀfunction,ꢀtheꢀdetailsꢀofꢀwhichꢀareꢀ
shownꢀinꢀtheꢀtable.
No.
Options
Higꢂ Speed System Osꢁillatoꢀ Seleꢁtion – fH
HXTꢄ ERC oꢀ HIRC
1
Low Speed System Osꢁillatoꢀ Seleꢁtion – fSUB
LXT oꢀ LIRC
ꢃ
ꢅ
I/O oꢀ Reset pin seleꢁtion
Reset pin oꢀ I/O pin
Application Circuits
VDD
VDD
PA0~PA7
100KΩ
PB0/RES
PB0~PB7
PC0~PC7
0.1uF
0.1uF
PD0~PD7
PE0~PE7
PF0~PF7
PG0~PG7
PH0~PH5
VSS
PB1/OSC1
PBꢃ/OSCꢃ
PBꢅ/XT1
OSC
Ciꢀꢁuit
OSC
Ciꢀꢁuit
PB4/XTꢃ
Rev. 1.00
ꢃ10
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Instruction Set
Introduction
Centralꢀtoꢀtheꢀsuccessfulꢀoperationꢀofꢀanyꢀmicrocontrollerꢀisꢀitsꢀinstructionꢀset,ꢀwhichꢀisꢀaꢀsetꢀofꢀ
programꢀinstructionꢀcodesꢀthatꢀdirectsꢀtheꢀmicrocontrollerꢀtoꢀperformꢀcertainꢀoperations.ꢀInꢀtheꢀcaseꢀ
ofꢀHoltekꢀmicrocontroller,ꢀaꢀcomprehensiveꢀandꢀflexibleꢀsetꢀofꢀoverꢀ60ꢀinstructionsꢀisꢀprovidedꢀtoꢀ
enableꢀprogrammersꢀtoꢀimplementꢀtheirꢀapplicationꢀwithꢀtheꢀminimumꢀofꢀprogrammingꢀoverheads.ꢀ
Forꢀeasierꢀunderstandingꢀofꢀtheꢀvariousꢀinstructionꢀcodes,ꢀtheyꢀhaveꢀbeenꢀsubdividedꢀintoꢀseveralꢀ
functionalꢀgroupings.
Instruction Timing
Mostꢀinstructionsꢀareꢀimplementedꢀwithinꢀoneꢀinstructionꢀcycle.ꢀTheꢀexceptionsꢀtoꢀthisꢀareꢀbranch,ꢀ
call,ꢀorꢀtableꢀreadꢀinstructionsꢀwhereꢀtwoꢀinstructionꢀcyclesꢀareꢀrequired.ꢀOneꢀinstructionꢀcycleꢀisꢀ
equalꢀtoꢀ4ꢀsystemꢀclockꢀcycles,ꢀthereforeꢀinꢀtheꢀcaseꢀofꢀanꢀ8MHzꢀsystemꢀoscillator,ꢀmostꢀinstructionsꢀ
wouldꢀbeꢀimplementedꢀwithinꢀ0.5μsꢀandꢀbranchꢀorꢀcallꢀinstructionsꢀwouldꢀbeꢀimplementedꢀwithinꢀ
1μs.ꢀAlthoughꢀinstructionsꢀwhichꢀrequireꢀoneꢀmoreꢀcycleꢀtoꢀimplementꢀareꢀgenerallyꢀlimitedꢀtoꢀ
theꢀJMP,ꢀCALL,ꢀRET,ꢀRETIꢀandꢀtableꢀreadꢀinstructions,ꢀitꢀisꢀimportantꢀtoꢀrealizeꢀthatꢀanyꢀotherꢀ
instructionsꢀwhichꢀinvolveꢀmanipulationꢀofꢀtheꢀProgramꢀCounterꢀLowꢀregisterꢀorꢀPCLꢀwillꢀalsoꢀtakeꢀ
oneꢀmoreꢀcycleꢀtoꢀimplement.ꢀAsꢀinstructionsꢀwhichꢀchangeꢀtheꢀcontentsꢀofꢀtheꢀPCLꢀwillꢀimplyꢀaꢀ
directꢀjumpꢀtoꢀthatꢀnewꢀaddress,ꢀoneꢀmoreꢀcycleꢀwillꢀbeꢀrequired.ꢀExamplesꢀofꢀsuchꢀinstructionsꢀ
wouldꢀbeꢀ“CLRꢀPCL”ꢀorꢀ“MOVꢀPCL,ꢀA”.ꢀForꢀtheꢀcaseꢀofꢀskipꢀinstructions,ꢀitꢀmustꢀbeꢀnotedꢀthatꢀifꢀ
theꢀresultꢀofꢀtheꢀcomparisonꢀinvolvesꢀaꢀskipꢀoperationꢀthenꢀthisꢀwillꢀalsoꢀtakeꢀoneꢀmoreꢀcycle,ꢀifꢀnoꢀ
skipꢀisꢀinvolvedꢀthenꢀonlyꢀoneꢀcycleꢀisꢀrequired.
Moving and Transferring Data
Theꢀtransferꢀofꢀdataꢀwithinꢀtheꢀmicrocontrollerꢀprogramꢀisꢀoneꢀofꢀtheꢀmostꢀfrequentlyꢀusedꢀ
operations.ꢀMakingꢀuseꢀofꢀseveralꢀkindsꢀofꢀMOVꢀinstructions,ꢀdataꢀcanꢀbeꢀtransferredꢀfromꢀregistersꢀ
toꢀtheꢀAccumulatorꢀandꢀvice-versaꢀasꢀwellꢀasꢀbeingꢀableꢀtoꢀmoveꢀspecificꢀimmediateꢀdataꢀdirectlyꢀ
intoꢀtheꢀAccumulator.ꢀOneꢀofꢀtheꢀmostꢀimportantꢀdataꢀtransferꢀapplicationsꢀisꢀtoꢀreceiveꢀdataꢀfromꢀ
theꢀinputꢀportsꢀandꢀtransferꢀdataꢀtoꢀtheꢀoutputꢀports.
Arithmetic Operations
Theꢀabilityꢀtoꢀperformꢀcertainꢀarithmeticꢀoperationsꢀandꢀdataꢀmanipulationꢀisꢀaꢀnecessaryꢀfeatureꢀofꢀ
mostꢀmicrocontrollerꢀapplications.ꢀWithinꢀtheꢀHoltekꢀmicrocontrollerꢀinstructionꢀsetꢀareꢀaꢀrangeꢀofꢀ
addꢀandꢀsubtractꢀinstructionꢀmnemonicsꢀtoꢀenableꢀtheꢀnecessaryꢀarithmeticꢀtoꢀbeꢀcarriedꢀout.ꢀCareꢀ
mustꢀbeꢀtakenꢀtoꢀensureꢀcorrectꢀhandlingꢀofꢀcarryꢀandꢀborrowꢀdataꢀwhenꢀresultsꢀexceedꢀ255ꢀforꢀ
additionꢀandꢀlessꢀthanꢀ0ꢀforꢀsubtraction.ꢀTheꢀincrementꢀandꢀdecrementꢀinstructionsꢀsuchꢀasꢀINC,ꢀ
INCA,ꢀDECꢀandꢀDECAꢀprovideꢀaꢀsimpleꢀmeansꢀofꢀincreasingꢀorꢀdecreasingꢀbyꢀaꢀvalueꢀofꢀoneꢀofꢀtheꢀ
valuesꢀinꢀtheꢀdestinationꢀspecified.
Rev. 1.00
ꢃ11
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Logical and Rotate Operation
TheꢀstandardꢀlogicalꢀoperationsꢀsuchꢀasꢀAND,ꢀOR,ꢀXORꢀandꢀCPLꢀallꢀhaveꢀtheirꢀownꢀinstructionꢀ
withinꢀtheꢀHoltekꢀmicrocontrollerꢀinstructionꢀset.ꢀAsꢀwithꢀtheꢀcaseꢀofꢀmostꢀinstructionsꢀinvolvingꢀ
dataꢀmanipulation,ꢀdataꢀmustꢀpassꢀthroughꢀtheꢀAccumulatorꢀwhichꢀmayꢀinvolveꢀadditionalꢀ
programmingꢀsteps.ꢀInꢀallꢀlogicalꢀdataꢀoperations,ꢀtheꢀzeroꢀflagꢀmayꢀbeꢀsetꢀifꢀtheꢀresultꢀofꢀtheꢀ
operationꢀisꢀzero.ꢀAnotherꢀformꢀofꢀlogicalꢀdataꢀmanipulationꢀcomesꢀfromꢀtheꢀrotateꢀinstructionsꢀsuchꢀ
asꢀRR,ꢀRL,ꢀRRCꢀandꢀRLCꢀwhichꢀprovideꢀaꢀsimpleꢀmeansꢀofꢀrotatingꢀoneꢀbitꢀrightꢀorꢀleft.ꢀDifferentꢀ
rotateꢀinstructionsꢀexistꢀdependingꢀonꢀprogramꢀrequirements.ꢀRotateꢀinstructionsꢀareꢀusefulꢀforꢀserialꢀ
portꢀprogrammingꢀapplicationsꢀwhereꢀdataꢀcanꢀbeꢀrotatedꢀfromꢀanꢀinternalꢀregisterꢀintoꢀtheꢀCarryꢀ
bitꢀfromꢀwhereꢀitꢀcanꢀbeꢀexaminedꢀandꢀtheꢀnecessaryꢀserialꢀbitꢀsetꢀhighꢀorꢀlow.ꢀAnotherꢀapplicationꢀ
whichꢀrotateꢀdataꢀoperationsꢀareꢀusedꢀisꢀtoꢀimplementꢀmultiplicationꢀandꢀdivisionꢀcalculations.
Branches and Control Transfer
ProgramꢀbranchingꢀtakesꢀtheꢀformꢀofꢀeitherꢀjumpsꢀtoꢀspecifiedꢀlocationsꢀusingꢀtheꢀJMPꢀinstructionꢀ
orꢀtoꢀaꢀsubroutineꢀusingꢀtheꢀCALLꢀinstruction.ꢀTheyꢀdifferꢀinꢀtheꢀsenseꢀthatꢀinꢀtheꢀcaseꢀofꢀaꢀ
subroutineꢀcall,ꢀtheꢀprogramꢀmustꢀreturnꢀtoꢀtheꢀinstructionꢀimmediatelyꢀwhenꢀtheꢀsubroutineꢀhasꢀ
beenꢀcarriedꢀout.ꢀThisꢀisꢀdoneꢀbyꢀplacingꢀaꢀreturnꢀinstructionꢀ“RET”ꢀinꢀtheꢀsubroutineꢀwhichꢀwillꢀ
causeꢀtheꢀprogramꢀtoꢀjumpꢀbackꢀtoꢀtheꢀaddressꢀrightꢀafterꢀtheꢀCALLꢀinstruction.ꢀInꢀtheꢀcaseꢀofꢀaꢀJMPꢀ
instruction,ꢀtheꢀprogramꢀsimplyꢀjumpsꢀtoꢀtheꢀdesiredꢀlocation.ꢀThereꢀisꢀnoꢀrequirementꢀtoꢀjumpꢀbackꢀ
toꢀtheꢀoriginalꢀjumpingꢀoffꢀpointꢀasꢀinꢀtheꢀcaseꢀofꢀtheꢀCALLꢀinstruction.ꢀOneꢀspecialꢀandꢀextremelyꢀ
usefulꢀsetꢀofꢀbranchꢀinstructionsꢀareꢀtheꢀconditionalꢀbranches.ꢀHereꢀaꢀdecisionꢀisꢀfirstꢀmadeꢀregardingꢀ
theꢀconditionꢀofꢀaꢀcertainꢀdataꢀmemoryꢀorꢀindividualꢀbits.ꢀDependingꢀuponꢀtheꢀconditions,ꢀtheꢀ
programꢀwillꢀcontinueꢀwithꢀtheꢀnextꢀinstructionꢀorꢀskipꢀoverꢀitꢀandꢀjumpꢀtoꢀtheꢀfollowingꢀinstruction.ꢀ
Theseꢀinstructionsꢀareꢀtheꢀkeyꢀtoꢀdecisionꢀmakingꢀandꢀbranchingꢀwithinꢀtheꢀprogramꢀperhapsꢀ
determinedꢀbyꢀtheꢀconditionꢀofꢀcertainꢀinputꢀswitchesꢀorꢀbyꢀtheꢀconditionꢀofꢀinternalꢀdataꢀbits.
Bit Operations
TheꢀabilityꢀtoꢀprovideꢀsingleꢀbitꢀoperationsꢀonꢀDataꢀMemoryꢀisꢀanꢀextremelyꢀflexibleꢀfeatureꢀofꢀallꢀ
Holtekꢀmicrocontrollers.ꢀThisꢀfeatureꢀisꢀespeciallyꢀusefulꢀforꢀoutputꢀportꢀbitꢀprogrammingꢀwhereꢀ
individualꢀbitsꢀorꢀportꢀpinsꢀcanꢀbeꢀdirectlyꢀsetꢀhighꢀorꢀlowꢀusingꢀeitherꢀtheꢀ“SETꢀ[m].i”ꢀorꢀ“CLRꢀ[m].i”ꢀ
instructionsꢀrespectively.ꢀTheꢀfeatureꢀremovesꢀtheꢀneedꢀforꢀprogrammersꢀtoꢀfirstꢀreadꢀtheꢀ8-bitꢀoutputꢀ
port,ꢀmanipulateꢀtheꢀinputꢀdataꢀtoꢀensureꢀthatꢀotherꢀbitsꢀareꢀnotꢀchangedꢀandꢀthenꢀoutputꢀtheꢀportꢀwithꢀ
theꢀcorrectꢀnewꢀdata.ꢀThisꢀread-modify-writeꢀprocessꢀisꢀtakenꢀcareꢀofꢀautomaticallyꢀwhenꢀtheseꢀbitꢀ
operationꢀinstructionsꢀareꢀused.
Table Read Operations
Dataꢀstorageꢀisꢀnormallyꢀimplementedꢀbyꢀusingꢀregisters.ꢀHowever,ꢀwhenꢀworkingꢀwithꢀlargeꢀ
amountsꢀofꢀfixedꢀdata,ꢀtheꢀvolumeꢀinvolvedꢀoftenꢀmakesꢀitꢀinconvenientꢀtoꢀstoreꢀtheꢀfixedꢀdataꢀinꢀ
theꢀDataꢀMemory.ꢀToꢀovercomeꢀthisꢀproblem,ꢀHoltekꢀmicrocontrollersꢀallowꢀanꢀareaꢀofꢀProgramꢀ
Memoryꢀtoꢀbeꢀsetupꢀasꢀaꢀtableꢀwhereꢀdataꢀcanꢀbeꢀdirectlyꢀstored.ꢀAꢀsetꢀofꢀeasyꢀtoꢀuseꢀinstructionsꢀ
providesꢀtheꢀmeansꢀbyꢀwhichꢀthisꢀfixedꢀdataꢀcanꢀbeꢀreferencedꢀandꢀretrievedꢀfromꢀtheꢀProgramꢀ
Memory.
Other Operations
Inꢀadditionꢀtoꢀtheꢀaboveꢀfunctionalꢀinstructions,ꢀaꢀrangeꢀofꢀotherꢀinstructionsꢀalsoꢀexistꢀsuchꢀasꢀ
theꢀ“HALT”ꢀinstructionꢀforꢀPower-downꢀoperationsꢀandꢀinstructionsꢀtoꢀcontrolꢀtheꢀoperationꢀofꢀ
theꢀWatchdogꢀTimerꢀforꢀreliableꢀprogramꢀoperationsꢀunderꢀextremeꢀelectricꢀorꢀelectromagneticꢀ
environments.ꢀForꢀtheirꢀrelevantꢀoperations,ꢀreferꢀtoꢀtheꢀfunctionalꢀrelatedꢀsections.
Rev. 1.00
ꢃ1ꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Instruction Set Summary
Theꢀinstructionsꢀrelatedꢀtoꢀtheꢀdataꢀmemoryꢀaccessꢀinꢀtheꢀfollowingꢀtableꢀcanꢀbeꢀusedꢀwhenꢀtheꢀ
desiredꢀdataꢀmemoryꢀisꢀlocatedꢀinꢀDataꢀMemoryꢀsectionꢀ0.
Table Conventions
x:ꢀBitsꢀimmediateꢀdataꢀ
m:ꢀDataꢀMemoryꢀaddressꢀ
A:ꢀAccumulatorꢀ
i:ꢀ0~7ꢀnumberꢀofꢀbitsꢀ
addr:ꢀProgramꢀmemoryꢀaddress
Mnemonic
Description
Cycles
Flag Affected
Arithmetic
ADD Aꢄ[m]
ADD� Aꢄ[m]
ADD Aꢄx
Add Data �emoꢀy to ACC
Add ACC to Data �emoꢀy
Add immediate data to ACC
1
1Note
1
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
ADC Aꢄ[m]
ADC� Aꢄ[m]
SUB Aꢄx
Add Data �emoꢀy to ACC witꢂ Caꢀꢀy
1
1Note
Add ACC to Data memoꢀy witꢂ Caꢀꢀy
Subtꢀaꢁt immediate data fꢀom tꢂe ACC
Subtꢀaꢁt Data �emoꢀy fꢀom ACC
1
SUB Aꢄ[m]
SUB� Aꢄ[m]
SBC Aꢄx
1
Subtꢀaꢁt Data �emoꢀy fꢀom ACC witꢂ ꢀesult in Data �emoꢀy
1Note Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
Subtꢀaꢁt immediate data fꢀom ACC witꢂ Caꢀꢀy
Subtꢀaꢁt Data �emoꢀy fꢀom ACC witꢂ Caꢀꢀyꢄ ꢀesult in Data �emoꢀy 1Note Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
1
Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
SBC� Aꢄ[m]
DAA [m]
Deꢁimal adjust ACC foꢀ Addition witꢂ ꢀesult in Data �emoꢀy
1Note
C
Logic Operation
AND Aꢄ[m]
OR Aꢄ[m]
Logiꢁal AND Data �emoꢀy to ACC
Logiꢁal OR Data �emoꢀy to ACC
Logiꢁal XOR Data �emoꢀy to ACC
Logiꢁal AND ACC to Data �emoꢀy
Logiꢁal OR ACC to Data �emoꢀy
Logiꢁal XOR ACC to Data �emoꢀy
Logiꢁal AND immediate Data to ACC
Logiꢁal OR immediate Data to ACC
Logiꢁal XOR immediate Data to ACC
Complement Data �emoꢀy
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
XOR Aꢄ[m]
AND� Aꢄ[m]
OR� Aꢄ[m]
XOR� Aꢄ[m]
AND Aꢄx
1
1Note
1Note
1Note
1
OR Aꢄx
1
XOR Aꢄx
1
1Note
CPL [m]
CPLA [m]
Complement Data �emoꢀy witꢂ ꢀesult in ACC
1
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
Inꢁꢀement Data �emoꢀy witꢂ ꢀesult in ACC
1
Z
Z
Z
Z
Inꢁꢀement Data �emoꢀy
1Note
Deꢁꢀement Data �emoꢀy witꢂ ꢀesult in ACC
Deꢁꢀement Data �emoꢀy
1
1Note
RRA [m]
RR [m]
Rotate Data �emoꢀy ꢀigꢂt witꢂ ꢀesult in ACC
Rotate Data �emoꢀy ꢀigꢂt
1
1Note
1
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate Data �emoꢀy ꢀigꢂt tꢂꢀougꢂ Caꢀꢀy witꢂ ꢀesult in ACC
Rotate Data �emoꢀy ꢀigꢂt tꢂꢀougꢂ Caꢀꢀy
Rotate Data �emoꢀy left witꢂ ꢀesult in ACC
Rotate Data �emoꢀy left
1Note
C
1
None
None
C
1Note
1
RLCA [m]
RLC [m]
Rotate Data �emoꢀy left tꢂꢀougꢂ Caꢀꢀy witꢂ ꢀesult in ACC
Rotate Data �emoꢀy left tꢂꢀougꢂ Caꢀꢀy
1Note
C
Rev. 1.00
ꢃ1ꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Mnemonic
Data Move
�OV Aꢄ[m]
Description
Cycles Flag Affected
�ove Data �emoꢀy to ACC
1
1Note
1
None
None
None
�OV [m]ꢄA �ove ACC to Data �emoꢀy
�OV Aꢄx
Bit Operation
CLR [m].i
SET [m].i
Branch
�ove immediate data to ACC
Cleaꢀ bit of Data �emoꢀy
Set bit of Data �emoꢀy
1Note
1Note
None
None
J�P addꢀ
SZ [m]
Jump unꢁonditionally
ꢃ
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if Data �emoꢀy is zeꢀo
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
ꢃ
SZA [m]
SZ [m].i
Skip if Data �emoꢀy is zeꢀo witꢂ data movement to ACC
Skip if bit i of Data �emoꢀy is zeꢀo
SNZ [m]
SIZ [m]
Skip if Data �emoꢀy is not zeꢀo
Skip if inꢁꢀement Data �emoꢀy is zeꢀo
Skip if deꢁꢀement Data �emoꢀy is zeꢀo
Skip if inꢁꢀement Data �emoꢀy is zeꢀo witꢂ ꢀesult in ACC
Skip if deꢁꢀement Data �emoꢀy is zeꢀo witꢂ ꢀesult in ACC
Subꢀoutine ꢁall
SDZ [m]
SIZA [m]
SDZA [m]
CALL addꢀ
RET
Retuꢀn fꢀom subꢀoutine
ꢃ
RET Aꢄx
RETI
Retuꢀn fꢀom subꢀoutine and load immediate data to ACC
Retuꢀn fꢀom inteꢀꢀupt
ꢃ
ꢃ
Table Read
TABRD [m] Read table to TBLH and Data �emoꢀy
ꢃNote
ꢃNote
None
None
None
TABRDL [m] Read table (last page) to TBLH and Data �emoꢀy
ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory ꢃNote
Increment table pointer TBLP first and Read table (last page) to TBLH and
Data �emoꢀy
ITABRDL [m]
ꢃNote
None
Miscellaneous
NOP
No opeꢀation
1
1Note
1Note
1
None
None
CLR [m]
SET [m]
CLR WDT
SWAP [m]
Cleaꢀ Data �emoꢀy
Set Data �emoꢀy
None
Cleaꢀ Watꢁꢂdog Timeꢀ
Swap nibbles of Data �emoꢀy
TOꢄ PDF
None
1Note
SWAPA [m] Swap nibbles of Data �emoꢀy witꢂ ꢀesult in ACC
HALT Enteꢀ poweꢀ down mode
1
None
1
TOꢄ PDF
Note:ꢀ1.ꢀForꢀskipꢀinstructions,ꢀifꢀtheꢀresultꢀofꢀtheꢀcomparisonꢀinvolvesꢀaꢀskipꢀthenꢀupꢀtoꢀthreeꢀcyclesꢀareꢀrequired,ꢀifꢀ
noꢀskipꢀtakesꢀplaceꢀonlyꢀoneꢀcycleꢀisꢀrequired.
2.ꢀAnyꢀinstructionꢀwhichꢀchangesꢀtheꢀcontentsꢀofꢀtheꢀPCLꢀwillꢀalsoꢀrequireꢀ2ꢀcyclesꢀforꢀexecution.
3.ꢀForꢀtheꢀ“CLRꢀWDT”ꢀinstructionꢀtheꢀTOꢀandꢀPDFꢀflagsꢀmayꢀbeꢀaffectedꢀbyꢀtheꢀexecutionꢀstatus.ꢀTheꢀTOꢀ
andꢀPDFꢀflagsꢀareꢀclearedꢀafterꢀtheꢀ“CLRꢀWDT”ꢀinstructionsꢀisꢀexecuted.ꢀOtherwiseꢀtheꢀTOꢀandꢀPDFꢀ
flagsꢀremainꢀunchanged.
Rev. 1.00
ꢃ14
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Extended Instruction Set
Theꢀextendedꢀinstructionsꢀareꢀusedꢀtoꢀsupportꢀtheꢀfullꢀrangeꢀaddressꢀaccessꢀforꢀtheꢀdataꢀmemory.ꢀ
Whenꢀtheꢀaccessedꢀdataꢀmemoryꢀisꢀlocatedꢀinꢀanyꢀdataꢀmemoryꢀsectionsꢀexceptꢀsectionꢀ0,ꢀtheꢀ
extendedꢀinstructionꢀcanꢀbeꢀusedꢀtoꢀaccessꢀtheꢀdataꢀmemoryꢀinsteadꢀofꢀusingꢀtheꢀindirectꢀaddressingꢀ
accessꢀtoꢀimproveꢀtheꢀCPUꢀfirmwareꢀperformance.
Mnemonic
Arithmetic
LADD Aꢄ[m]
Description
Cycles
Flag Affected
Add Data �emoꢀy to ACC
ꢃ
ꢃNote
ꢃ
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SC
Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
LADD� Aꢄ[m] Add ACC to Data �emoꢀy
LADC Aꢄ[m] Add Data �emoꢀy to ACC witꢂ Caꢀꢀy
LADC� Aꢄ[m] Add ACC to Data memoꢀy witꢂ Caꢀꢀy
LSUB Aꢄ[m] Subtꢀaꢁt Data �emoꢀy fꢀom ACC
LSUB� Aꢄ[m] Subtꢀaꢁt Data �emoꢀy fꢀom ACC witꢂ ꢀesult in Data �emoꢀy
LSBC Aꢄ[m] Subtꢀaꢁt Data �emoꢀy fꢀom ACC witꢂ Caꢀꢀy
ꢃNote
ꢃ
ꢃNote Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
ꢃ
Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
LSBC� Aꢄ[m] Subtꢀaꢁt Data �emoꢀy fꢀom ACC witꢂ Caꢀꢀyꢄ ꢀesult in Data �emoꢀy ꢃNote Zꢄ Cꢄ ACꢄ OVꢄ SCꢄ CZ
LDAA [m]
Deꢁimal adjust ACC foꢀ Addition witꢂ ꢀesult in Data �emoꢀy
ꢃNote
C
Logic Operation
LAND Aꢄ[m]
LOR Aꢄ[m]
Logiꢁal AND Data �emoꢀy to ACC
Logiꢁal OR Data �emoꢀy to ACC
Logiꢁal XOR Data �emoꢀy to ACC
ꢃ
ꢃ
Z
Z
Z
Z
Z
Z
Z
Z
LXOR Aꢄ[m]
ꢃ
LAND� Aꢄ[m] Logiꢁal AND ACC to Data �emoꢀy
LOR� Aꢄ[m] Logiꢁal OR ACC to Data �emoꢀy
LXOR� Aꢄ[m] Logiꢁal XOR ACC to Data �emoꢀy
ꢃNote
ꢃNote
ꢃNote
ꢃNote
ꢃ
LCPL [m]
Complement Data �emoꢀy
LCPLA [m]
Complement Data �emoꢀy witꢂ ꢀesult in ACC
Increment & Decrement
LINCA [m]
LINC [m]
Inꢁꢀement Data �emoꢀy witꢂ ꢀesult in ACC
ꢃ
Z
Z
Z
Z
Inꢁꢀement Data �emoꢀy
ꢃNote
LDECA [m]
LDEC [m]
Rotate
Deꢁꢀement Data �emoꢀy witꢂ ꢀesult in ACC
Deꢁꢀement Data �emoꢀy
ꢃ
ꢃNote
LRRA [m]
LRR [m]
Rotate Data �emoꢀy ꢀigꢂt witꢂ ꢀesult in ACC
Rotate Data �emoꢀy ꢀigꢂt
ꢃ
ꢃNote
ꢃ
None
None
C
LRRCA [m]
LRRC [m]
LRLA [m]
Rotate Data �emoꢀy ꢀigꢂt tꢂꢀougꢂ Caꢀꢀy witꢂ ꢀesult in ACC
Rotate Data �emoꢀy ꢀigꢂt tꢂꢀougꢂ Caꢀꢀy
Rotate Data �emoꢀy left witꢂ ꢀesult in ACC
Rotate Data �emoꢀy left
ꢃNote
C
ꢃ
None
None
C
LRL [m]
ꢃNote
ꢃ
LRLCA [m]
LRLC [m]
Data Move
L�OV Aꢄ[m]
L�OV [m]ꢄA
Bit Operation
LCLR [m].i
LSET [m].i
Rotate Data �emoꢀy left tꢂꢀougꢂ Caꢀꢀy witꢂ ꢀesult in ACC
Rotate Data �emoꢀy left tꢂꢀougꢂ Caꢀꢀy
ꢃNote
C
�ove Data �emoꢀy to ACC
�ove ACC to Data �emoꢀy
ꢃ
ꢃNote
None
None
Cleaꢀ bit of Data �emoꢀy
Set bit of Data �emoꢀy
ꢃNote
ꢃNote
None
None
Rev. 1.00
ꢃ15
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Mnemonic
Description
Cycles Flag Affected
Branch
LSZ [m]
Skip if Data �emoꢀy is zeꢀo
ꢃNote
ꢃNote
ꢃNote
ꢃNote
ꢃNote
ꢃNote
ꢃNote
ꢃNote
ꢃNote
None
None
None
None
None
None
None
None
None
LSZA [m]
LSNZ [m]
LSZ [m].i
LSNZ [m].i
LSIZ [m]
Skip if Data �emoꢀy is zeꢀo witꢂ data movement to ACC
Skip if Data �emoꢀy is not zeꢀo
Skip if bit i of Data �emoꢀy is zeꢀo
Skip if bit i of Data �emoꢀy is not zeꢀo
Skip if inꢁꢀement Data �emoꢀy is zeꢀo
LSDZ [m]
LSIZA [m]
LSDZA [m]
Table Read
Skip if deꢁꢀement Data �emoꢀy is zeꢀo
Skip if inꢁꢀement Data �emoꢀy is zeꢀo witꢂ ꢀesult in ACC
Skip if deꢁꢀement Data �emoꢀy is zeꢀo witꢂ ꢀesult in ACC
LTABRD [m] Read table to TBLH and Data �emoꢀy
ꢅNote
ꢅNote
None
None
None
LTABRDL [m] Read table (last page) to TBLH and Data �emoꢀy
LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory ꢅNote
Increment table pointer TBLP first and Read table (last page) to TBLH and
Data �emoꢀy
LITABRDL [m]
ꢅNote
None
Miscellaneous
LCLR [m]
Cleaꢀ Data �emoꢀy
ꢃNote
ꢃNote
ꢃNote
ꢃ
None
None
None
None
LSET [m]
Set Data �emoꢀy
LSWAP [m]
Swap nibbles of Data �emoꢀy
LSWAPA [m] Swap nibbles of Data �emoꢀy witꢂ ꢀesult in ACC
Note:ꢀ1.ꢀForꢀtheseꢀextendedꢀskipꢀinstructions,ꢀifꢀtheꢀresultꢀofꢀtheꢀcomparisonꢀinvolvesꢀaꢀskipꢀthenꢀupꢀtoꢀfourꢀcyclesꢀ
areꢀrequired,ꢀifꢀnoꢀskipꢀtakesꢀplaceꢀtwoꢀcyclesꢀisꢀrequired.
2.ꢀAnyꢀextendedꢀinstructionꢀwhichꢀchangesꢀtheꢀcontentsꢀofꢀtheꢀPCLꢀregisterꢀwillꢀalsoꢀrequireꢀthreeꢀcyclesꢀforꢀ
execution.
Rev. 1.00
ꢃ16
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Instruction Definition
ꢀ
AddꢀDataꢀMemoryꢀtoꢀACCꢀwithꢀCarry
ADC A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀflagꢀareꢀadded.ꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀACCꢀtoꢀDataꢀMemoryꢀwithꢀCarry
ADCM A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀflagꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspecifiedꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀDataꢀMemoryꢀtoꢀACC
ADD A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
AddꢀimmediateꢀdataꢀtoꢀACC
ADD A,x
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀx
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀACCꢀtoꢀDataꢀMemory
ADDM A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspecifiedꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀANDꢀDataꢀMemoryꢀtoꢀACC
AND A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″AND″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
LogicalꢀANDꢀimmediateꢀdataꢀtoꢀACC
AND A,x
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀperformꢀaꢀbitꢀwiseꢀlogicalꢀANDꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″AND″ꢀx
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀANDꢀACCꢀtoꢀDataꢀMemory
ANDM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″AND″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃ17
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
ꢀ
Subroutineꢀcall
CALL addr
Descriptionꢀ
Unconditionallyꢀcallsꢀaꢀsubroutineꢀatꢀtheꢀspecifiedꢀaddress.ꢀTheꢀProgramꢀCounterꢀthenꢀ
incrementsꢀbyꢀ1ꢀtoꢀobtainꢀtheꢀaddressꢀofꢀtheꢀnextꢀinstructionꢀwhichꢀisꢀthenꢀpushedꢀontoꢀtheꢀ
stack.ꢀTheꢀspecifiedꢀaddressꢀisꢀthenꢀloadedꢀandꢀtheꢀprogramꢀcontinuesꢀexecutionꢀfromꢀthisꢀ
newꢀaddress.ꢀAsꢀthisꢀinstructionꢀrequiresꢀanꢀadditionalꢀoperation,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
Stackꢀ←ꢀProgramꢀCounterꢀ+ꢀ1ꢀ
ProgramꢀCounterꢀ←ꢀaddr
Affectedꢀflag(s)ꢀ
None
ꢀ
ClearꢀDataꢀMemory
CLR [m]
Descriptionꢀ
Operationꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.
[m]ꢀ←ꢀ00H
None
Affectedꢀflag(s)ꢀ
ClearꢀbitꢀofꢀDataꢀMemory
CLR [m].i
Descriptionꢀ
Operationꢀ
BitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.
[m].iꢀ←ꢀ0
None
Affectedꢀflag(s)ꢀ
ꢀ
ClearꢀWatchdogꢀTimer
CLR WDT
Descriptionꢀ
TheꢀTO,ꢀPDFꢀflagsꢀandꢀtheꢀWDTꢀareꢀallꢀcleared.ꢀ
Operationꢀ
ꢀ
ꢀ
WDTꢀclearedꢀ
TOꢀ←ꢀ0ꢀ
PDFꢀ←ꢀ0
Affectedꢀflag(s)ꢀ
TO,ꢀPDF
ꢀ
Pre-clearꢀWatchdogꢀTimer
CLR WDT1
Descriptionꢀ
TheꢀTO,ꢀPDFꢀflagsꢀandꢀtheꢀWDTꢀareꢀallꢀcleared.ꢀNoteꢀthatꢀthisꢀinstructionꢀworksꢀinꢀ
conjunctionꢀwithꢀCLRꢀWDT2ꢀandꢀmustꢀbeꢀexecutedꢀalternatelyꢀwithꢀCLRꢀWDT2ꢀtoꢀhaveꢀ
effect.ꢀRepetitivelyꢀexecutingꢀthisꢀinstructionꢀwithoutꢀalternatelyꢀexecutingꢀCLRꢀWDT2ꢀwillꢀ
haveꢀnoꢀeffect.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ꢀ
WDTꢀclearedꢀ
TOꢀ←ꢀ0ꢀ
PDFꢀ←ꢀ0ꢀ
Affectedꢀflag(s)ꢀ
TO,ꢀPDF
ꢀ
Pre-clearꢀWatchdogꢀTimer
CLR WDT2
Descriptionꢀ
ꢀ
ꢀꢀ
ꢀ
TheꢀTO,ꢀPDFꢀflagsꢀandꢀtheꢀWDTꢀareꢀallꢀcleared.ꢀNoteꢀthatꢀthisꢀinstructionꢀworksꢀinꢀconjunctionꢀ
withꢀCLRꢀWDT1ꢀandꢀmustꢀbeꢀexecutedꢀalternatelyꢀwithꢀCLRꢀWDT1ꢀtoꢀhaveꢀeffect.ꢀ
RepetitivelyꢀexecutingꢀthisꢀinstructionꢀwithoutꢀalternatelyꢀexecutingꢀCLRꢀWDT1ꢀwillꢀhaveꢀnoꢀ
effect.
Operationꢀ
ꢀ
ꢀ
WDTꢀclearedꢀ
TOꢀ←ꢀ0ꢀ
PDFꢀ←ꢀ0
Affectedꢀflag(s)ꢀ
TO,ꢀPDF
ComplementꢀDataꢀMemory
CPL [m]
Descriptionꢀ
ꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ
previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.
Operationꢀ
[m]ꢀ←ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃ18
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
ꢀ
ComplementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
CPLA [m]
Descriptionꢀ
ꢀ
ꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ
previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.ꢀTheꢀcomplementedꢀresultꢀisꢀstoredꢀinꢀ
theꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Decimal-AdjustꢀACCꢀforꢀadditionꢀwithꢀresultꢀinꢀDataꢀMemory
DAA [m]
Descriptionꢀ
ConvertꢀtheꢀcontentsꢀofꢀtheꢀAccumulatorꢀvalueꢀtoꢀaꢀBCDꢀ(BinaryꢀCodedꢀDecimal)ꢀvalueꢀ
resultingꢀfromꢀtheꢀpreviousꢀadditionꢀofꢀtwoꢀBCDꢀvariables.ꢀIfꢀtheꢀlowꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀ
orꢀifꢀACꢀflagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀwillꢀbeꢀaddedꢀtoꢀtheꢀlowꢀnibble.ꢀOtherwiseꢀtheꢀlowꢀnibbleꢀ
remainsꢀunchanged.ꢀIfꢀtheꢀhighꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀorꢀifꢀtheꢀCꢀflagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀ
willꢀbeꢀaddedꢀtoꢀtheꢀhighꢀnibble.ꢀEssentially,ꢀtheꢀdecimalꢀconversionꢀisꢀperformedꢀbyꢀaddingꢀ
00H,ꢀ06H,ꢀ60Hꢀorꢀ66HꢀdependingꢀonꢀtheꢀAccumulatorꢀandꢀflagꢀconditions.ꢀOnlyꢀtheꢀCꢀflagꢀ
mayꢀbeꢀaffectedꢀbyꢀthisꢀinstructionꢀwhichꢀindicatesꢀthatꢀifꢀtheꢀoriginalꢀBCDꢀsumꢀisꢀgreaterꢀthanꢀ
100,ꢀitꢀallowsꢀmultipleꢀprecisionꢀdecimalꢀaddition.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ00Hꢀorꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ06Hꢀorꢀꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ60Hꢀorꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ66H
ꢀ
ꢀ
ꢀ
Affectedꢀflag(s)ꢀ
C
ꢀ
DecrementꢀDataꢀMemory
DEC [m]
Descriptionꢀ
Operationꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.
[m]ꢀ←ꢀ[m]ꢀ−ꢀ1
Z
Affectedꢀflag(s)ꢀ
DECAꢀ[m]ꢀ
DecrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀ
Accumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]ꢀ−ꢀ1
Z
Affectedꢀflag(s)ꢀ
ꢀ
Enterꢀpowerꢀdownꢀmode
HALT
Descriptionꢀ
ꢀ
ꢀ
Thisꢀinstructionꢀstopsꢀtheꢀprogramꢀexecutionꢀandꢀturnsꢀoffꢀtheꢀsystemꢀclock.ꢀTheꢀcontentsꢀofꢀꢀ
theꢀDataꢀMemoryꢀandꢀregistersꢀareꢀretained.ꢀTheꢀWDTꢀandꢀprescalerꢀareꢀcleared.ꢀTheꢀpowerꢀ
downꢀflagꢀPDFꢀisꢀsetꢀandꢀtheꢀWDTꢀtime-outꢀflagꢀTOꢀisꢀcleared.
Operationꢀ
ꢀ
TOꢀ←ꢀ0ꢀ
PDFꢀ←ꢀ1
Affectedꢀflag(s)ꢀ
TO,ꢀPDF
ꢀ
IncrementꢀDataꢀMemoryꢀ
INC [m]
Descriptionꢀ
Operationꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.
[m]ꢀ←ꢀ[m]ꢀ+ꢀ1
Z
Affectedꢀflag(s)ꢀ
IncrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
INCA [m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀ
TheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]ꢀ+ꢀ1
Z
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃ19
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Jumpꢀunconditionally
JMP addr
Descriptionꢀ
ꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀareꢀreplacedꢀwithꢀtheꢀspecifiedꢀaddress.ꢀProgramꢀ
executionꢀthenꢀcontinuesꢀfromꢀthisꢀnewꢀaddress.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnewꢀaddressꢀisꢀloaded,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.
Operationꢀ
ProgramꢀCounterꢀ←ꢀaddr
None
Affectedꢀflag(s)ꢀ
ꢀ
MoveꢀDataꢀMemoryꢀtoꢀACC
MOV A,[m]
Descriptionꢀ
Operationꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.
ACCꢀ←ꢀ[m]
None
Affectedꢀflag(s)ꢀ
MoveꢀimmediateꢀdataꢀtoꢀACC
MOV A,x
Descriptionꢀ
Operationꢀ
TheꢀimmediateꢀdataꢀspecifiedꢀisꢀloadedꢀintoꢀtheꢀAccumulator.
ACCꢀ←ꢀx
None
Affectedꢀflag(s)ꢀ
ꢀ
MoveꢀACCꢀtoꢀDataꢀMemoryꢀ
MOV [m],A
Descriptionꢀ
Operationꢀ
TheꢀcontentsꢀofꢀtheꢀAccumulatorꢀareꢀcopiedꢀtoꢀtheꢀspecifiedꢀDataꢀMemory.
[m]ꢀ←ꢀACC
None
Affectedꢀflag(s)ꢀ
ꢀ
Noꢀoperation
NOP
Descriptionꢀ
Operationꢀ
Noꢀoperationꢀisꢀperformed.ꢀExecutionꢀcontinuesꢀwithꢀtheꢀnextꢀinstruction.
Noꢀoperation
None
Affectedꢀflag(s)ꢀ
LogicalꢀORꢀDataꢀMemoryꢀtoꢀACC
OR A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀ
logicalꢀORꢀoperation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″OR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀORꢀimmediateꢀdataꢀtoꢀACC
OR A,x
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀperformꢀaꢀbitwiseꢀlogicalꢀORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″OR″ꢀx
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀORꢀACCꢀtoꢀDataꢀMemory
ORM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″OR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
Returnꢀfromꢀsubroutine
RET
Descriptionꢀ
ꢀ
TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstack.ꢀProgramꢀexecutionꢀcontinuesꢀatꢀtheꢀrestoredꢀ
address.
Operationꢀ
ProgramꢀCounterꢀ←ꢀStack
None
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃꢃ0
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
ꢀ
ReturnꢀfromꢀsubroutineꢀandꢀloadꢀimmediateꢀdataꢀtoꢀACC
RET A,x
Descriptionꢀ
ꢀ
TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstackꢀandꢀtheꢀAccumulatorꢀloadedꢀwithꢀtheꢀspecifiedꢀ
immediateꢀdata.ꢀProgramꢀexecutionꢀcontinuesꢀatꢀtheꢀrestoredꢀaddress.
Operationꢀ
ꢀ
ProgramꢀCounterꢀ←ꢀStackꢀ
ACCꢀ←ꢀx
Affectedꢀflag(s)ꢀ
None
ꢀ
Returnꢀfromꢀinterrupt
RETI
Descriptionꢀ
TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstackꢀandꢀtheꢀinterruptsꢀareꢀre-enabledꢀbyꢀsettingꢀtheꢀ
EMIꢀbit.ꢀEMIꢀisꢀtheꢀmasterꢀinterruptꢀglobalꢀenableꢀbit.ꢀIfꢀanꢀinterruptꢀwasꢀpendingꢀwhenꢀtheꢀꢀ
RETIꢀinstructionꢀisꢀexecuted,ꢀtheꢀpendingꢀInterruptꢀroutineꢀwillꢀbeꢀprocessedꢀbeforeꢀreturningꢀꢀ
toꢀtheꢀmainꢀprogram.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ProgramꢀCounterꢀ←ꢀStackꢀ
EMIꢀ←ꢀ1
Affectedꢀflag(s)ꢀ
None
ꢀ
RotateꢀDataꢀMemoryꢀleft
RL [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.
Operationꢀ
ꢀ
[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
[m].0ꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀleftꢀwithꢀresultꢀinꢀACC
RLA [m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.ꢀ
TheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀ
unchanged.
Operationꢀ
ꢀ
ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
ACC.0ꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarry
RLC [m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀ
replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ0.
Operationꢀ
ꢀ
ꢀ
[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
[m].0ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
C
ꢀ
RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC
RLCA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀreplacesꢀtheꢀ
Carryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀtheꢀbitꢀ0.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀ
AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ꢀ
ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
ACC.0ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
C
RotateꢀDataꢀMemoryꢀright
RR [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀrotatedꢀintoꢀbitꢀ7.
Operationꢀ
ꢀ
[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
[m].7ꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
None
Rev. 1.00
ꢃꢃ1
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
RotateꢀDataꢀMemoryꢀrightꢀwithꢀresultꢀinꢀACC
RRA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀ
rotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀ
DataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
ACC.7ꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarry
RRC [m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀ
replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ7.
Operationꢀ
ꢀ
ꢀ
[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
[m].7ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
C
ꢀ
RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC
RRCA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀreplacesꢀꢀ
theꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀꢀ
AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ꢀ
ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
ACC.7ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
C
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarry
SBC A,[m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀ
subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀꢀ
resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀ
positiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
SBC A, xꢀ
SubtractꢀimmediateꢀdataꢀfromꢀACCꢀwithꢀCarry
Descriptionꢀ
Theꢀimmediateꢀdataꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀsubtractedꢀfromꢀtheꢀꢀ
Accumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀꢀ
negative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀꢀ
willꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
ACCꢀ←ꢀACCꢀ-ꢀ[m]ꢀ-ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarryꢀandꢀresultꢀinꢀDataꢀMemory
SBCM A,[m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀꢀ
subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀꢀ
resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀꢀ
positiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
[m]ꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃꢃꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀ0
SDZ [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ
theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀꢀ
proceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
[m]ꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ
Skipꢀifꢀ[m]=0
Affectedꢀflag(s)ꢀ
None
ꢀ
SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC
SDZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspecifiedꢀꢀ
DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀ
theꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ
SkipꢀifꢀACC=0
Affectedꢀflag(s)ꢀ
None
ꢀ
SetꢀDataꢀMemory
SET [m]
Descriptionꢀ
Operationꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.
[m]ꢀ←ꢀFFH
None
Affectedꢀflag(s)ꢀ
SetꢀbitꢀofꢀDataꢀMemory
SET [m].i
Descriptionꢀ
Operationꢀ
BitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.
[m].iꢀ←ꢀ1
None
Affectedꢀflag(s)ꢀ
SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀ0
SIZ [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀ
followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ
theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀ
proceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
[m]ꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ
Skipꢀifꢀ[m]=0ꢀ
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC
SIZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspecifiedꢀ
DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ
0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ
SkipꢀifꢀACC=0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀDataꢀMemoryꢀisꢀnotꢀ0
SNZ [m].i
Descriptionꢀ
ꢀ
ꢀ
IfꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀnotꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀ
insertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀꢀ
instruction.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m].iꢀ≠ꢀ0
None
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃꢃꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SkipꢀifꢀDataꢀMemoryꢀisꢀnotꢀ0
SNZ [m]
Descriptionꢀ
ꢀ
ꢀ
IfꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀnotꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀ
insertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀꢀ
instruction.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m]≠ꢀ0
None
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACC
SUB A,[m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀspecifiedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ
storedꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀꢀ
clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀresultꢀinꢀDataꢀMemory
SUBM A,[m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀspecifiedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ
storedꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀꢀ
clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
[m]ꢀ←ꢀACCꢀ−ꢀ[m]
Affectedꢀflag(s)ꢀ
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
SubtractꢀimmediateꢀdataꢀfromꢀACC
SUB A,x
Descriptionꢀ
ꢀ
ꢀ
TheꢀimmediateꢀdataꢀspecifiedꢀbyꢀtheꢀcodeꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀꢀ
flagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀx
Affectedꢀflag(s)ꢀ
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
SwapꢀnibblesꢀofꢀDataꢀMemory
SWAP [m]
Descriptionꢀ
Operationꢀ
Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀinterchanged.
[m].3~[m].0ꢀ↔ꢀ[m].7~[m].4
None
Affectedꢀflag(s)ꢀ
ꢀ
SwapꢀnibblesꢀofꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
SWAPA [m]
Descriptionꢀ
ꢀ
Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀinterchanged.ꢀTheꢀꢀ
resultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ACC.3~ACC.0ꢀ←ꢀ[m].7~[m].4ꢀ
ACC.7~ACC.4ꢀ←ꢀ[m].3~[m].0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀDataꢀMemoryꢀisꢀ0
SZ [m]
Descriptionꢀ
ꢀ
ꢀ
IfꢀtheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀꢀ
requiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀꢀ
cycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m]=0
None
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃꢃ4
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SkipꢀifꢀDataꢀMemoryꢀisꢀ0ꢀwithꢀdataꢀmovementꢀtoꢀACC
SZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.ꢀIfꢀtheꢀvalueꢀisꢀzero,ꢀꢀ
theꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀꢀ
whileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀꢀ
programꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ
Skipꢀifꢀ[m]=0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀbitꢀiꢀofꢀDataꢀMemoryꢀisꢀ0
SZ [m].i
Descriptionꢀ
ꢀ
ꢀ
IfꢀbitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀ
theꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀ
instruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m].i=0
None
Affectedꢀflag(s)ꢀ
ꢀ
Readꢀtableꢀ(currentꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
TABRD [m]
Descriptionꢀ
ꢀ
Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(currentꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀꢀ
movedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
Readꢀtableꢀ(lastꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
TABRDL [m]
Descriptionꢀ
ꢀ
Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(lastꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀmovedꢀꢀ
toꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
ITABRD [m]ꢀ
IncrementꢀtableꢀpointerꢀlowꢀbyteꢀfirstꢀandꢀreadꢀtableꢀtoꢀTBLHꢀandꢀDataꢀMemory
Descriptionꢀ
ꢀ
ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyte,ꢀTBLP,ꢀfirstꢀandꢀthenꢀtheꢀprogramꢀcodeꢀaddressedꢀbyꢀtheꢀꢀ
tableꢀpointerꢀ(TBHPꢀandꢀTBLP)ꢀisꢀmovedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀꢀ
movedꢀtoꢀTBLH.
Operationꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
None
ꢀ
Affectedꢀflag(s)ꢀ
ITABRDL [m]ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyteꢀfirstꢀandꢀreadꢀtableꢀ(lastꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
Descriptionꢀ
ꢀ
ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyte,ꢀTBLP,ꢀfirstꢀandꢀthenꢀtheꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀꢀ
(lastꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀmovedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀꢀ
theꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
None
ꢀ
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀXORꢀDataꢀMemoryꢀtoꢀACC
XOR A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″XOR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃꢃ5
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
ꢀ
LogicalꢀXORꢀACCꢀtoꢀDataꢀMemory
XORM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″XOR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
LogicalꢀXORꢀimmediateꢀdataꢀtoꢀACC
XOR A,x
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀimmediateꢀdataꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″XOR″ꢀx
Z
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃꢃ6
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Extended Instruction Definition
Theꢀextendedꢀinstructionsꢀareꢀusedꢀtoꢀdirectlyꢀaccessꢀtheꢀdataꢀstoredꢀinꢀanyꢀdataꢀmemoryꢀsections.
ꢀ
AddꢀDataꢀMemoryꢀtoꢀACCꢀwithꢀCarry
LADC A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀflagꢀareꢀadded.ꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀACCꢀtoꢀDataꢀMemoryꢀwithꢀCarry
LADCM A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀflagꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspecifiedꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀDataꢀMemoryꢀtoꢀACC
LADD A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ+ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
AddꢀACCꢀtoꢀDataꢀMemory
LADDM A,[m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀꢀ
TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspecifiedꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀANDꢀDataꢀMemoryꢀtoꢀACC
LAND A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″AND″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀANDꢀACCꢀtoꢀDataꢀMemory
LANDM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″AND″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
ClearꢀDataꢀMemory
LCLR [m]
Descriptionꢀ
Operationꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.
[m]ꢀ←ꢀ00H
None
Affectedꢀflag(s)ꢀ
ClearꢀbitꢀofꢀDataꢀMemory
LCLR [m].i
Descriptionꢀ
Operationꢀ
BitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.
[m].iꢀ←ꢀ0
None
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃꢃ7
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
ComplementꢀDataꢀMemory
LCPL [m]
Descriptionꢀ
ꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ
previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.
Operationꢀ
[m]ꢀ←ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
ComplementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
LCPLA [m]
Descriptionꢀ
ꢀ
ꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ
previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.ꢀTheꢀcomplementedꢀresultꢀisꢀstoredꢀinꢀ
theꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Decimal-AdjustꢀACCꢀforꢀadditionꢀwithꢀresultꢀinꢀDataꢀMemory
LDAA [m]
Descriptionꢀ
ConvertꢀtheꢀcontentsꢀofꢀtheꢀAccumulatorꢀvalueꢀtoꢀaꢀBCDꢀ(BinaryꢀCodedꢀDecimal)ꢀvalueꢀ
resultingꢀfromꢀtheꢀpreviousꢀadditionꢀofꢀtwoꢀBCDꢀvariables.ꢀIfꢀtheꢀlowꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀ
orꢀifꢀACꢀflagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀwillꢀbeꢀaddedꢀtoꢀtheꢀlowꢀnibble.ꢀOtherwiseꢀtheꢀlowꢀnibbleꢀ
remainsꢀunchanged.ꢀIfꢀtheꢀhighꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀorꢀifꢀtheꢀCꢀflagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀ
willꢀbeꢀaddedꢀtoꢀtheꢀhighꢀnibble.ꢀEssentially,ꢀtheꢀdecimalꢀconversionꢀisꢀperformedꢀbyꢀaddingꢀ
00H,ꢀ06H,ꢀ60Hꢀorꢀ66HꢀdependingꢀonꢀtheꢀAccumulatorꢀandꢀflagꢀconditions.ꢀOnlyꢀtheꢀCꢀflagꢀ
mayꢀbeꢀaffectedꢀbyꢀthisꢀinstructionꢀwhichꢀindicatesꢀthatꢀifꢀtheꢀoriginalꢀBCDꢀsumꢀisꢀgreaterꢀthanꢀ
100,ꢀitꢀallowsꢀmultipleꢀprecisionꢀdecimalꢀaddition.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ00Hꢀorꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ06Hꢀorꢀꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ60Hꢀorꢀ
[m]ꢀ←ꢀACCꢀ+ꢀ66H
ꢀ
ꢀ
ꢀ
Affectedꢀflag(s)ꢀ
C
ꢀ
DecrementꢀDataꢀMemory
LDEC [m]
Descriptionꢀ
Operationꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.
[m]ꢀ←ꢀ[m]ꢀ−ꢀ1
Z
Affectedꢀflag(s)ꢀ
LDECA [m]ꢀ
DecrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀ
Accumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]ꢀ−ꢀ1
Z
Affectedꢀflag(s)ꢀ
ꢀ
IncrementꢀDataꢀMemoryꢀ
LINC [m]
Descriptionꢀ
Operationꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.
[m]ꢀ←ꢀ[m]ꢀ+ꢀ1
Z
Affectedꢀflag(s)ꢀ
IncrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
LINCA [m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀ
TheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ACCꢀ←ꢀ[m]ꢀ+ꢀ1
Z
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃꢃ8
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
ꢀ
MoveꢀDataꢀMemoryꢀtoꢀACC
LMOV A,[m]
Descriptionꢀ
Operationꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.
ACCꢀ←ꢀ[m]
None
Affectedꢀflag(s)ꢀ
ꢀ
MoveꢀACCꢀtoꢀDataꢀMemoryꢀ
LMOV [m],A
Descriptionꢀ
Operationꢀ
TheꢀcontentsꢀofꢀtheꢀAccumulatorꢀareꢀcopiedꢀtoꢀtheꢀspecifiedꢀDataꢀMemory.
[m]ꢀ←ꢀACC
None
Affectedꢀflag(s)ꢀ
LogicalꢀORꢀDataꢀMemoryꢀtoꢀACC
LOR A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀ
logicalꢀORꢀoperation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″OR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀORꢀACCꢀtoꢀDataꢀMemory
LORM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″OR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
RotateꢀDataꢀMemoryꢀleft
LRL [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.
Operationꢀ
ꢀ
[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
[m].0ꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀleftꢀwithꢀresultꢀinꢀACC
LRLA [m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.ꢀ
TheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀ
unchanged.
Operationꢀ
ꢀ
ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
ACC.0ꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarry
LRLC [m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀ
replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ0.
Operationꢀ
ꢀ
ꢀ
[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
[m].0ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
C
ꢀ
RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC
LRLCA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀreplacesꢀtheꢀ
Carryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀtheꢀbitꢀ0.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀ
AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ꢀ
ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ
ACC.0ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].7
Affectedꢀflag(s)ꢀ
C
Rev. 1.00
ꢃꢃ9
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
RotateꢀDataꢀMemoryꢀright
LRR [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀrotatedꢀintoꢀbitꢀ7.
Operationꢀ
ꢀ
[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
[m].7ꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀrightꢀwithꢀresultꢀinꢀACC
LRRA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀ
rotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀ
DataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
ACC.7ꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
None
RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarry
LRRC [m]
Descriptionꢀ
ꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀ
replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ7.
Operationꢀ
ꢀ
ꢀ
[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
[m].7ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
C
ꢀ
RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC
LRRCA [m]
Descriptionꢀ
ꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀflagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀreplacesꢀꢀ
theꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀflagꢀisꢀrotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀꢀ
AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ꢀ
ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ
ACC.7ꢀ←ꢀCꢀ
Cꢀ←ꢀ[m].0
Affectedꢀflag(s)ꢀ
C
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarry
LSBC A,[m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀ
subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀꢀ
resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀ
positiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarryꢀandꢀresultꢀinꢀDataꢀMemory
LSBCM A,[m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀflagꢀareꢀꢀ
subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀꢀ
resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀꢀ
positiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
ꢀ
ꢀ
ꢀ
Operationꢀ
[m]ꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀC
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃꢅ0
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀ0
LSDZ [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ
theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀꢀ
proceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
[m]ꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ
Skipꢀifꢀ[m]=0
Affectedꢀflag(s)ꢀ
None
ꢀ
SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC
LSDZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspecifiedꢀꢀ
DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀ
theꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ
SkipꢀifꢀACC=0
Affectedꢀflag(s)ꢀ
None
ꢀ
SetꢀDataꢀMemory
LSET [m]
Descriptionꢀ
Operationꢀ
EachꢀbitꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.
[m]ꢀ←ꢀFFH
None
Affectedꢀflag(s)ꢀ
SetꢀbitꢀofꢀDataꢀMemory
LSET [m].i
Descriptionꢀ
Operationꢀ
BitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.
[m].iꢀ←ꢀ1
None
Affectedꢀflag(s)ꢀ
SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀ0
LSIZ [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀ
followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ
theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀ
proceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
[m]ꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ
Skipꢀifꢀ[m]=0ꢀ
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC
LSIZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀfirstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ
followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspecifiedꢀ
DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ
instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ
0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ
SkipꢀifꢀACC=0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀDataꢀMemoryꢀisꢀnotꢀ0
LSNZ [m].i
Descriptionꢀ
ꢀ
ꢀ
IfꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀnotꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀ
insertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀꢀ
instruction.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m].iꢀ≠ꢀ0
None
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃꢅ1
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SkipꢀifꢀDataꢀMemoryꢀisꢀnotꢀ0
LSNZ [m]
Descriptionꢀ
ꢀ
ꢀ
IfꢀꢀtheꢀcontentꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀnotꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀꢀ
thisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀꢀ
twoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m]ꢀ≠ꢀ0
None
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACC
LSUB A,[m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀspecifiedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ
storedꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀꢀ
clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
ACCꢀ←ꢀACCꢀ−ꢀ[m]
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
Affectedꢀflag(s)ꢀ
ꢀ
SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀresultꢀinꢀDataꢀMemory
LSUBM A,[m]
Descriptionꢀ
ꢀ
ꢀ
TheꢀspecifiedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ
storedꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀflagꢀwillꢀbeꢀꢀ
clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀflagꢀwillꢀbeꢀsetꢀtoꢀ1.
Operationꢀ
[m]ꢀ←ꢀACCꢀ−ꢀ[m]
Affectedꢀflag(s)ꢀ
OV,ꢀZ,ꢀAC,ꢀC,ꢀSC,ꢀCZ
SwapꢀnibblesꢀofꢀDataꢀMemory
LSWAP [m]
Descriptionꢀ
Operationꢀ
Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀinterchanged.
[m].3~[m].0ꢀ↔ꢀ[m].7~[m].4
None
Affectedꢀflag(s)ꢀ
ꢀ
SwapꢀnibblesꢀofꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC
LSWAPA [m]
Descriptionꢀ
ꢀ
Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀinterchanged.ꢀTheꢀꢀ
resultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.
Operationꢀ
ꢀ
ACC.3~ACC.0ꢀ←ꢀ[m].7~[m].4ꢀ
ACC.7~ACC.4ꢀ←ꢀ[m].3~[m].0
Affectedꢀflag(s)ꢀ
None
SkipꢀifꢀDataꢀMemoryꢀisꢀ0
LSZ [m]
Descriptionꢀ
ꢀ
ꢀ
IfꢀtheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀꢀ
requiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀꢀ
cycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m]=0
None
Affectedꢀflag(s)ꢀ
SkipꢀifꢀDataꢀMemoryꢀisꢀ0ꢀwithꢀdataꢀmovementꢀtoꢀACC
LSZA [m]
Descriptionꢀ
TheꢀcontentsꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.ꢀIfꢀtheꢀvalueꢀisꢀzero,ꢀꢀ
theꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀꢀ
whileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀꢀ
programꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
ꢀ
ꢀ
ꢀ
Operationꢀ
ꢀ
ACCꢀ←ꢀ[m]ꢀ
Skipꢀifꢀ[m]=0
Affectedꢀflag(s)ꢀ
None
Rev. 1.00
ꢃꢅꢃ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
SkipꢀifꢀbitꢀiꢀofꢀDataꢀMemoryꢀisꢀ0
LSZ [m].i
Descriptionꢀ
ꢀ
ꢀ
IfꢀbitꢀiꢀofꢀtheꢀspecifiedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀ
theꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀ
instruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.
Operationꢀ
Skipꢀifꢀ[m].i=0
None
Affectedꢀflag(s)ꢀ
ꢀ
Readꢀtableꢀ(currentꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
LTABRD [m]
Descriptionꢀ
ꢀ
Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(currentꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀꢀ
movedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
Readꢀtableꢀ(lastꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
LTABRDL [m]
Descriptionꢀ
ꢀ
Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(lastꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀmovedꢀꢀ
toꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
LITABRD [m]ꢀ
IncrementꢀtableꢀpointerꢀlowꢀbyteꢀfirstꢀandꢀreadꢀtableꢀtoꢀTBLHꢀandꢀDataꢀMemory
Descriptionꢀ
ꢀ
ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyte,ꢀTBLP,ꢀfirstꢀandꢀthenꢀtheꢀprogramꢀcodeꢀaddressedꢀbyꢀtheꢀꢀ
tableꢀpointerꢀ(TBHPꢀandꢀTBLP)ꢀisꢀmovedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀꢀ
movedꢀtoꢀTBLH.
Operationꢀ
ꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
Affectedꢀflag(s)ꢀ
None
LITABRDL [m]ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyteꢀfirstꢀandꢀreadꢀtableꢀ(lastꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory
Descriptionꢀ
ꢀ
ꢀ
Incrementꢀtableꢀpointerꢀlowꢀbyte,ꢀTBLP,ꢀfirstꢀandꢀthenꢀtheꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀꢀ
(lastꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀmovedꢀtoꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀꢀ
theꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.
Operationꢀ
[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)
TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)
None
ꢀ
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀXORꢀDataꢀMemoryꢀtoꢀACC
LXOR A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspecifiedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.
Operationꢀ
ACCꢀ←ꢀACCꢀ″XOR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
ꢀ
LogicalꢀXORꢀACCꢀtoꢀDataꢀMemory
LXORM A,[m]
Descriptionꢀ
ꢀ
DataꢀinꢀtheꢀspecifiedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ
operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.
Operationꢀ
[m]ꢀ←ꢀACCꢀ″XOR″ꢀ[m]
Z
Affectedꢀflag(s)ꢀ
Rev. 1.00
ꢃꢅꢅ
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
•ꢀ Further Package Informationꢀ(includeꢀOutlineꢀDimensions,ꢀProductꢀTapeꢀandꢀReelꢀSpecifications)
•ꢀ Packing Meterials Information
•ꢀ Carton information
•ꢀ PB FREE Products
•ꢀ Green Packages Products
Rev. 1.00
234
March 20, 2013
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
48-pin LQFP (7mm×7mm) Outline Dimensions
C
H
D
G
3
6
2
5
I
3
7
2
4
F
A
B
E
4
8
1
3
=
K
J
1
1
2
Dimensions in inch
Nom.
Symbol
Min.
Max.
A
B
C
D
E
F
G
H
I
0.ꢅ50
0.ꢃ7ꢃ
0.ꢅ50
0.ꢃ7ꢃ
―
―
0.05ꢅ
―
―
―
―
0.ꢅ58
0.ꢃ80
0.ꢅ58
0.ꢃ80
―
―
0.0ꢃ0
0.008
―
―
0.004
―
―
0.057
0.06ꢅ
―
0.0ꢅ0
0.008
7°
―
J
K
α
0.018
0.004
0°
―
―
Dimensions in mm
Nom.
Symbol
Min.
Max.
A
B
C
D
E
F
G
H
I
8.90
6.90
8.90
6.90
―
―
1.ꢅ5
―
―
―
―
9.10
7.10
9.10
7.10
―
―
0.50
0.ꢃ0
―
―
0.10
―
―
1.45
1.60
―
0.75
0.ꢃ0
7°
―
J
K
α
0.45
0.10
0°
―
―
Rev. 1.00
ꢃꢅ5
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
64-pin LQFP (7mm×7mm) Outline Dimensions
C
D
H
G
4
8
3
3
I
3
2
4
9
F
A
B
E
6
4
1
7
=
K
J
1
1
6
Dimensions in inch
Symbol
Min.
0.ꢅ50
0.ꢃ7ꢃ
0.ꢅ50
0.ꢃ7ꢃ
―
Nom.
―
Max.
0.ꢅ58
0.ꢃ80
0.ꢅ58
0.ꢃ80
―
A
B
C
D
E
F
G
H
I
―
―
―
0.016
―
0.005
0.05ꢅ
―
0.009
0.057
0.06ꢅ
0.006
0.0ꢅ0
0.008
7°
―
―
0.00ꢃ
0.018
0.004
0°
―
J
―
K
α
―
―
Dimensions in mm
Symbol
Min.
8.90
6.90
8.90
6.90
―
Nom.
―
Max.
9.10
7.10
9.10
7.10
―
A
B
C
D
E
F
G
H
I
―
―
―
0.40
―
0.1ꢅ
1.ꢅ5
―
0.ꢃꢅ
1.45
1.60
0.15
0.75
0.ꢃ0
7°
―
―
0.05
0.45
0.09
0°
―
J
―
K
α
―
―
Rev. 1.00
ꢃꢅ6
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
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Howeveꢀꢄ Holtek assumes no ꢀesponsibility aꢀising fꢀom tꢂe use of tꢂe speꢁifiꢁations desꢁꢀibed.
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no waꢀꢀanty oꢀ ꢀepꢀesentation tꢂat suꢁꢂ appliꢁations will be suitable witꢂout fuꢀtꢂeꢀ modifiꢁationꢄ
noꢀ ꢀeꢁommends tꢂe use of its pꢀoduꢁts foꢀ appliꢁation tꢂat may pꢀesent a ꢀisk to ꢂuman life due to
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Rev. 1.00
ꢃꢅ7
�aꢀꢁꢂ ꢃ0ꢄ ꢃ01ꢅ
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