HT66FU60(44LQFP-A) [HOLTEK]
Microcontroller, 8-Bit, FLASH, 20MHz, CMOS, PQFP44;
| 型号： | HT66FU60(44LQFP-A) |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Microcontroller, 8-Bit, FLASH, 20MHz, CMOS, PQFP44 时钟 微控制器 |
| 文件： | 总259页 (文件大小：2955K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Enhanced A/D Flash Type MCU 8-Bit MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Revision: 1.60 Date: September 9, 2011
Contents
Table of Contents
Technical Document ...........................................................................9
Features ...............................................................................................9
CPU Features ........................................................................................................9
Peripheral Features................................................................................................9
General Description ............................................................................9
Selection Table ..................................................................................10
Block Diagram ...................................................................................10
Pin Assignment .................................................................................11
Pin Description..................................................................................15
HT66F20 ..............................................................................................................15
HT66F30 ..............................................................................................................16
HT66F40 ..............................................................................................................17
HT66F50 ..............................................................................................................19
HT66F60 ..............................................................................................................20
Absolute Maximum Ratings .............................................................22
D.C. Characteristics ..........................................................................22
A.C. Characteristics ..........................................................................24
A/D Converter Characteristics .........................................................25
Comparator Electrical Characteristics............................................26
Power-on Reset Characteristics ......................................................26
System Architecture .........................................................................27
Clocking and Pipelining ........................................................................................27
Program Counter..................................................................................................28
Stack....................................................................................................................28
Arithmetic and Logic Unit - ALU............................................................................28
Flash Program Memory ....................................................................29
Structure...............................................................................................................29
Special Vectors.....................................................................................................29
Look-up Table.......................................................................................................29
Table Program Example .......................................................................................29
In Circuit Programming.........................................................................................30
RAM Data Memory.............................................................................31
Structure...............................................................................................................31
Rev. 1.60
2
September 9, 2011
Contents
Special Function Register Description ...........................................34
Indirect Addressing Registers - IAR0, IAR1....................................34
Memory Pointers - MP0, MP1...............................................................................34
Bank Pointer - BP.................................................................................................35
Accumulator - ACC...............................................................................................36
Program Counter Low Register - PCL ..................................................................36
Look-up Table Registers - TBLP, TBHP, TBLH......................................................36
Status Register - STATUS ....................................................................................36
EEPROM Data Memory .....................................................................38
EEPROM Data Memory Structure ........................................................................38
EEPROM Registers..............................................................................................38
Reading Data from the EEPROM .........................................................................40
Writing Data to the EEPROM ...............................................................................40
Write Protection....................................................................................................41
EEPROM Interrupt ...............................................................................................41
Programming Considerations ...............................................................................41
Oscillator............................................................................................42
Oscillator Overview...............................................................................................42
System Clock Configurations................................................................................42
External Crystal/ Ceramic Oscillator - HXT ...........................................................43
External RC Oscillator - ERC................................................................................43
Internal RC Oscillator - HIRC................................................................................43
External 32.768kHz Crystal Oscillator - LXT.........................................................43
LXT Oscillator Low Power Function......................................................................44
Internal 32kHz Oscillator - LIRC ...........................................................................44
Supplementary Oscillators....................................................................................44
Operating Modes and System Clocks.............................................45
System Clocks......................................................................................................45
System Operation Modes .....................................................................................46
Control Register ...................................................................................................47
Fast Wake-up.......................................................................................................48
Operating Mode Switching and Wake-up..............................................................49
NORMAL Mode to SLOW Mode Switching...........................................................49
SLOW Mode to NORMAL Mode Switching...........................................................50
Entering the SLEEP0 Mode..................................................................................50
Entering the SLEEP1 Mode..................................................................................51
Entering the IDLE0 Mode .....................................................................................51
Entering the IDLE1 Mode .....................................................................................51
Standby Current Considerations...........................................................................51
Wake-up...............................................................................................................52
Programming Considerations ...............................................................................52
Rev. 1.60
3
September 9, 2011
Contents
Watchdog Timer ................................................................................53
Watchdog Timer Clock Source .............................................................................53
Watchdog Timer Control Register.........................................................................53
Watchdog Timer Operation...................................................................................54
Reset and Initialisation .....................................................................55
Reset Functions ...................................................................................................55
Reset Initial Conditions.........................................................................................56
Input/Output Ports.............................................................................69
Pull-high Resistors................................................................................................72
Port A Wake-up ....................................................................................................74
I/O Port Control Registers.....................................................................................74
Pin-remapping Functions......................................................................................77
Pin-remapping Registers ......................................................................................77
I/O Pin Structures .................................................................................................81
Programming Considerations ...............................................................................81
Timer Modules - TM...........................................................................84
Introduction ..........................................................................................................84
TM Operation .......................................................................................................85
TM Clock Source..................................................................................................85
TM Interrupts........................................................................................................85
TM External Pins..................................................................................................85
TM Input/Output Pin Control Registers .................................................................86
Programming Considerations ...............................................................................94
Compact Type TM - CTM...................................................................95
Compact TM Operation ........................................................................................95
Compact Type TM Register Description ...............................................................96
Compact Type TM Operating Modes....................................................................99
Compare Match Output Mode ..............................................................................99
Timer/Counter Mode.............................................................................................99
PWM Output Mode.............................................................................................102
Standard Type TM - STM.................................................................104
Standard TM Operation ......................................................................................104
Standard Type TM Register Description .............................................................104
Standard Type TM Operating Modes ..................................................................112
Compare Output Mode .......................................................................................112
Timer/Counter Mode...........................................................................................115
PWM Output Mode .............................................................................................115
Single Pulse Mode..............................................................................................118
Capture Input Mode............................................................................................119
Rev. 1.60
4
September 9, 2011
Contents
Enhanced Type TM - ETM...............................................................120
Enhanced TM Operation ....................................................................................120
Enhanced Type TM Register Description............................................................121
Enhanced Type TM Operating Modes ................................................................126
Compare Output Mode.......................................................................................126
Timer/Counter Mode...........................................................................................131
PWM Output Mode.............................................................................................131
Single Pulse Output Mode..................................................................................136
Capture Input Mode............................................................................................138
Analog to Digital Converter............................................................140
A/D Overview .....................................................................................................140
A/D Converter Register Description....................................................................140
A/D Converter Data Registers - ADRL, ADRH....................................................141
A/D Converter Control Registers - ADCR0, ADCR1, ACERL, ACERH ...............141
A/D Operation.....................................................................................................146
A/D Input Pins ....................................................................................................146
Summary of A/D Conversion Steps ....................................................................147
Programming Considerations .............................................................................148
A/D Transfer Function.........................................................................................148
A/D Programming Example ................................................................................148
Comparators....................................................................................150
Comparator Operation........................................................................................150
Comparator Registers ........................................................................................150
Comparator Interrupt ..........................................................................................150
Programming Considerations .............................................................................150
Serial Interface Module - SIM .........................................................153
SPI Interface.......................................................................................................153
SPI Registers .....................................................................................................154
SPI Communication............................................................................................157
I2C Interface .......................................................................................................159
I2C Bus Communication......................................................................................163
I2C Bus Start Signal............................................................................................163
Slave Address ....................................................................................................163
I2C Bus Read/Write Signal..................................................................................163
I2C Bus Slave Address Acknowledge Signal.......................................................163
I2C Bus Data and Acknowledge Signal ...............................................................164
Peripheral Clock Output .................................................................166
Peripheral Clock Operation.................................................................................166
Rev. 1.60
5
September 9, 2011
Contents
Interrupts..........................................................................................167
Interrupt Registers..............................................................................................167
Interrupt Operation .............................................................................................179
External Interrupt................................................................................................183
Comparator Interrupt ..........................................................................................183
Multi-function Interrupt........................................................................................183
A/D Converter Interrupt.......................................................................................183
Time Base Interrupts ..........................................................................................183
Serial Interface Module Interrupt.........................................................................185
External Peripheral Interrupt...............................................................................185
EEPROM Interrupt .............................................................................................185
LVD Interrupt ......................................................................................................185
TM Interrupts......................................................................................................186
Interrupt Wake-up Function ................................................................................186
Programming Considerations .............................................................................186
Power Down Mode and Wake-up ...................................................187
Entering the IDLE or SLEEP Mode.....................................................................187
Standby Current Considerations.........................................................................187
Wake-up.............................................................................................................187
Low Voltage Detector - LVD............................................................188
LVD Register ......................................................................................................188
LVD Operation....................................................................................................189
SCOM Function for LCD .................................................................189
LCD Operation ...................................................................................................189
LCD Bias Control................................................................................................189
Configuration Options ....................................................................192
Application Circuits ........................................................................193
UART Module Serial Interface........................................................194
UART Module Features......................................................................................194
UART Module Overview..................................................................194
UART Module Block Diagram.........................................................194
Pin Assignment ...............................................................................195
UART Module Pin Description .......................................................197
UART Module D.C. Characteristics................................................197
UART Module A.C. Characteristics................................................198
UART Module Functional Description...........................................199
UART Module Internal Signal .............................................................................199
Rev. 1.60
6
September 9, 2011
Contents
UART Module SPI Interface............................................................199
SPI Timing..........................................................................................................199
UART Module External Pin Interfacing..........................................200
UART Data Transfer Scheme .............................................................................200
UART Commands ..............................................................................................201
UART Status and Control Registers ...................................................................201
Baud Rate Generator .........................................................................................206
UART Module Setup and Control...................................................208
Managing Receiver Errors ..................................................................................211
UART Module Interrupt Structure ..................................................211
UART Module Power-down and Wake-up .....................................212
Using the UART Function...............................................................213
Application Circuit with UART Module..........................................214
Instruction Set .................................................................................215
Introduction.........................................................................................................215
Instruction Timing ...............................................................................................215
Moving and Transferring Data ............................................................................215
Arithmetic Operations .........................................................................................215
Logical and Rotate Operations ...........................................................................215
Branches and Control Transfer...........................................................................215
Bit Operations.....................................................................................................216
Table Read Operations.......................................................................................216
Other Operations................................................................................................216
Instruction Set Summary ....................................................................................216
Instruction Definition ......................................................................218
Package Information.......................................................................228
16-pin DIP (300mil) Outline Dimensions .............................................................228
16-pin NSOP (150mil) Outline Dimensions.........................................................231
16-pin SSOP (150mil) Outline Dimensions .........................................................232
20-pin DIP (300mil) Outline Dimensions .............................................................233
20-pin SOP (300mil) Outline Dimensions............................................................235
20-pin SSOP (150mil) Outline Dimensions .........................................................236
24-pin SKDIP (300mil) Outline Dimensions ........................................................237
24-pin SOP (300mil) Outline Dimensions............................................................240
24-pin SSOP (150mil) Outline Dimensions .........................................................241
28-pin SKDIP (300mil) Outline Dimensions ........................................................242
28-pin SOP (300mil) Outline Dimensions............................................................243
28-pin SSOP (150mil) Outline Dimensions .........................................................244
SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions...................................245
SAW Type 40-pin (6mm´6mm for 0.75mm) QFN Outline Dimensions...............246
44-pin QFP (10mm´10mm) Outline Dimensions ................................................247
48-pin SSOP (300mil) Outline Dimensions .........................................................248
Rev. 1.60
7
September 9, 2011
Contents
SAW Type 48-pin (7mm´7mm) QFN Outline Dimensions...................................249
52-pin QFP (14mm´14mm) Outline Dimensions ................................................250
44-pin LQFP (10mm´10mm) (FP3.2mm) Outline Dimensions............................251
Product Tape and Reel Specifications ..........................................252
Reel Dimensions ................................................................................................252
Carrier Tape Dimensions ....................................................................................254
Rev. 1.60
8
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Enhanced A/D Flash Type MCU 8-Bit MCU with EEPROM
Technical Document
·
Application Note
-
HA0075E MCU Reset and Oscillator Circuits Application Note
Features
·
CPU Features
RAM Data Memory: 64´8 ~ 576´8
·
·
EEPROM Memory: 32´8~256´8
Watchdog Timer function
Operating Voltage:
·
fSYS= 8MHz: 2.2V~5.5V
fSYS= 12MHz: 2.7V~5.5V
fSYS= 20MHz: 4.5V~5.5V
·
·
Up to 50 bidirectional I/O lines
Software controlled 4-SCOM lines LCD driver with
1/2 bias
·
·
·
Up to 0.2ms instruction cycle with 20MHz system
clock at VDD=5V
·
·
Multiple pin-shared external interrupts
Multiple Timer Module for time measure, input
capture, compare match output, PWM output or
single pulse output function
Power down and wake-up functions to reduce power
consumption
Five oscillators:
External Crystal -- HXT
Serial Interfaces Module -- SIM for SPI or I2C
·
·
·
External 32.768kHz Crystal -- LXT
External RC -- ERC
Internal RC -- HIRC
Internal 32kHz RC -- LIRC
Multi-mode operation: NORMAL, SLOW, IDLE and
SLEEP
Dual Comparator functions
Dual Time-Base functions for generation of fixed time
interrupt signals
·
·
·
·
Multi-channel 12-bit resolution A/D converter
Low voltage reset function
·
·
·
Low voltage detect function
Fully integrated internal 4MHz, 8MHz and 12MHz
oscillator requires no external components
All instructions executed in one or two instruction
cycles
Optional peripheral -- UART module for fully duplex
asynchronous communication
·
·
Wide range of available package types
·
·
·
·
Table read instructions
63 powerful instructions
Flash program memory can be re-programmed up to
100,000 times
Up to 12-level subroutine nesting
Bit manipulation instruction
·
·
Flash program memory data retention > 10 years
EEPROM data memory can be re-programmed up to
1,000,000 times
Peripheral Features
·
EEPROM data memory data retention > 10 years
·
Flash Program Memory: 1K´14 ~ 12K´16
General Description
The HT66FXX series of devices are Flash Memory A/D
type 8-bit high performance RISC architecture
microcontrollers. Offering users the convenience of Flash
Memory multi-programming features, these devices also
include a wide range of functions and features. Other
memory includes an area of RAM Data Memory as well as
an area of EEPROM memory for storage of non-volatile
data such as serial numbers, calibration data etc.
A full choice of HXT, LXT, ERC, HIRC and LIRC oscilla-
tor functions are provided including a fully integrated
system oscillator which requires no external compo-
nents for its implementation. The ability to operate and
switch dynamically between a range of operating
modes using different clock sources gives users the
ability to optimise microcontroller operation and mini-
mise power consumption.
Analog features include a multi-channel 12-bit A/D con-
verter and dual comparator functions. Multiple and ex-
tremely flexible Timer Modules provide timing, pulse
generation and PWM generation functions. Communica-
tion with the outside world is catered for by including fully
integrated SPI or I2C interface functions, two popular inter-
faces which provide designers with a means of easy com-
munication with external peripheral hardware. Protective
features such as an internal Watchdog Timer, Low Voltage
Reset and Low Voltage Detector coupled with excellent
noise immunity and ESD protection ensure that reliable
operation is maintained in hostile electrical environments.
The UART module is contained in the HT66FUx0 series of
devices. It can support the applications such as data com-
munication networks between microcontrollers, low-cost
data links between PCs and peripheral devices, portable
and battery operated device communication, etc.
The inclusion of flexible I/O programming features,
Time-Base functions along with many other features en-
sure that the devices will find excellent use in applica-
tions such as electronic metering, environmental
monitoring, handheld instruments, household appli-
ances, electronically controlled tools, motor driving in
addition to many others.
Rev. 1.60
9
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Selection Table
Most features are common to all devices, the main feature distinguishing them are Memory capacity, I/O count, TM
features, stack capacity and package types. The following table summarises the main features of each device.
Program
Data
Data
Ext.
Int.
Timer
Interface
(SPI/I2C)
Part No.
VDD
I/O
A/D
UART Stack
Package
Memory Memory EEPROM
Module
2.2V~
5.5V
10-bit CTM´1,
10-bit STM´1
16DIP/NSOP/SSOP
20DIP/SOP/SSOP
HT66F20
1K´14
2K´14
64´8
96´8
32´8
64´8
18
2
12-bit´8
Ö
¾
4
4
16DIP/NSOP/SSOP
20DIP/SOP/SSOP
24SKDIP/SOP/SSOP
HT66F30
HT66FU30
HT66F40
22
14
42
¾
Ö
2.2V~
5.5V
10-bit CTM´1,
10-bit ETM´1
2
12-bit´8
12-bit´8
Ö
24SKDIP/SOP
24/28SKDIP/SOP/SSOP
44LQFP
¾
10-bit CTM´1,
10-bit ETM´1,
16-bit STM´1
2.2V~
5.5V
32/40QFN, 48SSOP/QFN
4K´15
192´8
128´8
2
Ö
8
40QFN, 44LQFP,
48SSOP/QFN
HT66FU40
HT66F50
34
42
Ö
28SKDIP/SOP/SSOP
44LQFP, 40QFN
48SSOP/QFN
10-bit CTM´2,
10-bit ETM´1,
16-bit STM´1
¾
2.2V~
5.5V
8K´16
384´8
576´8
256´8
256´8
2
4
12-bit´8
Ö
Ö
8
HT66FU50
HT66F60
34
50
Ö
44LQFP, 48QFN
52QFP, 40QFN, 44LQFP
48SSOP/LQFP/QFN
¾
10-bit CTMx2,
10-bit ETMx1,
16-bit STMx1
2.2V~
5.5V
12K´16
12-bit´12
12
52QFP, 40QFN, 44LQFP
48LQFP/QFN
HT66FU60
42
Ö
Note: As devices exist in more than one package format, the table reflects the situation for the package with the most
pins.
There is an additional peripheral known as the UART module in HT66FU30, HT66FU40, HT66FU50 and
HT66FU60 devices. All information related to the UART Module will be described in the following UART Mod-
ule section.
Block Diagram
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Rev. 1.60
10
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Pin Assignment
P
A
0
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C
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1
1
1
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/
C
0
X
/
T
P
0
_
2
1
1
1
1
1
1
1
1
1
0
0
9
8
7
6
5
4
3
2
1
/
P
P
P
P
P
P
P
P
P
P
A
A
A
A
A
A
A
A
B
C
C
N
1
2
3
4
5
6
7
5
0
/
/
/
/
/
/
/
/
T
T
I
I
C
S
S
S
P
C
1
A
/
A
N
1
1
2
3
4
5
6
7
8
9
1
V
S
S
&
A
V
S
S
K
0
/
C
0
+
/
A
N
P
A
0
/
C
0
X
/
T
P
0
_
0
/
P
P
P
P
P
P
P
P
A
A
A
A
A
A
A
A
B
N
1
2
3
4
5
6
7
5
0
/
/
/
/
/
/
/
/
T
T
I
I
C
S
S
S
P
C
1
A
/
A
N
1
P
P
B
B
4
3
/
/
X
X
T
T
2
1
N
N
T
T
0
1
/
/
C
T
0
-
/
A
N
1
2
3
4
5
6
7
8
1
1
1
1
1
1
1
6
5
4
3
2
1
0
V
S
S
&
A
V
S
S
K
0
/
C
0
+
/
A
N
2
C
K
1
/
A
P
P
B
B
4
3
/
/
X
X
T
T
2
1
N
N
T
T
0
1
/
/
C
T
0
-
/
A
N
3
P
P
B
B
2
1
/
/
O
O
S
S
C
C
2
1
1
X
/
S
D
O
/
A
N
C
K
1
/
A
N
4
D
C
C
I
K
S
/
S
D
A
/
A
N
6
P
P
B
B
2
1
/
/
O
O
S
S
C
C
2
1
1
X
/
S
D
O
/
A
N
5
V
D
D
D
&
D
A
V
/
/
S
V
C
R
L
E
/
A
N
D
C
C
I
K
S
/
S
D
A
/
A
N
6
P
B
0
/
R
E
S
F
V
D
D
&
A
V
D
D
C
L
/
A
/
/
N
S
7
P
C
1
/
T
P
1
B
_
1
/
[
S
D
O
]
/
S
C
2
3
O
/
/
P
P
M
C
I
1
K
/
C
1
+
P
B
0
/
R
E
S
V
R
E
P
F
C
0
/
T
P
1
B
_
0
/
[
S
D
I
/
S
D
A
]
/
S
C
O
N
M
T
0
/
C
1
-
9
0
H
T
6
6
F
3
0
H
T
6
6
F
3
0
1
6
D
I
P
-
A
/
N
S
O
P
-
A
/
S
S
O
P
-
A
2
0
D
I
P
-
A
/
S
O
P
-
A
/
S
S
O
P
-
A
P
A
0
/
C
0
X
/
T
1
2
3
4
5
6
7
8
9
1
1
1
P
0
_
0
/
P
P
P
P
P
P
P
P
P
P
P
P
A
A
A
A
A
A
A
A
B
C
C
C
C
N
1
2
3
4
5
6
7
5
0
/
/
/
/
/
/
/
/
T
T
I
I
C
S
S
S
P
C
1
A
/
A
N
1
2
2
2
2
2
1
1
1
1
1
1
1
4
3
2
1
0
9
8
7
6
5
4
3
V
S
S
&
A
V
S
S
K
0
/
C
0
+
/
A
N
2
P
P
B
B
4
3
/
/
X
X
T
T
2
1
N
N
T
T
0
1
/
/
C
T
0
-
/
A
N
3
C
K
1
/
A
N
4
P
P
B
B
2
1
/
/
O
O
S
S
C
C
2
1
1
X
/
S
D
O
/
A
N
5
D
C
C
I
K
S
/
S
D
A
/
A
N
6
V
D
D
&
A
V
D
D
/
/
S
V
C
R
L
E
/
A
N
7
P
B
0
/
R
E
S
F
P
C
1
/
T
P
1
B
_
1
/
[
S
D
O
]
/
S
C
/
2
3
4
5
P
O
C
M
K
1
/
C
1
+
P
C
0
/
T
P
1
B
_
0
/
[
S
D
0
1
2
I
/
S
D
A
]
/
/
/
/
S
P
[
T
C
I
O
N
I
M
T
0
/
C
]
1
-
P
C
7
/
[
S
C
K
/
S
C
L
]
/
S
C
O
M
3
P
N
T
P
C
6
/
[
S
C
S
]
/
S
C
O
M
2
P
0
_
1
/
[
P
C
K
]
H
T
6
6
F
3
0
2
4
S
K
D
I
P
-
A
/
S
O
P
-
A
/
S
S
O
P
-
A
P
A
0
/
C
0
X
/
T
1
2
3
4
5
6
7
8
9
1
1
1
1
1
P
0
_
2
2
2
2
2
2
2
2
2
1
1
1
1
1
0
8
7
6
5
4
3
2
1
0
9
8
7
6
5
/
P
P
P
P
P
P
P
P
P
P
P
P
P
P
A
A
A
A
A
A
A
A
B
C
C
C
C
D
D
N
1
2
3
4
5
6
7
5
0
/
/
/
/
/
/
/
/
T
T
I
I
C
S
S
S
P
C
1
A
/
A
N
1
V
S
S
&
A
V
S
S
K
0
/
C
0
+
/
A
N
2
P
A
0
/
C
0
X
/
T
1
2
3
4
5
6
7
8
9
1
1
1
P
0
_
0
/
P
P
P
P
P
P
P
P
P
P
P
P
A
A
A
A
A
A
A
A
B
C
C
C
C
N
1
2
3
4
5
6
7
5
0
/
/
/
/
/
/
/
/
T
T
I
I
C
S
S
S
P
C
1
A
/
A
N
1
P
P
B
B
4
3
/
/
X
X
T
T
2
1
N
N
T
T
0
1
/
/
C
T
0
-
/
A
N
3
2
2
2
2
2
1
1
1
1
1
1
1
4
3
2
1
0
9
8
7
6
5
4
3
V
S
S
&
A
V
S
S
K
0
/
C
0
+
/
A
N
2
C
K
1
/
A
N
P
P
B
B
4
3
/
/
X
X
T
T
2
1
N
N
T
T
0
1
/
/
C
T
0
-
/
A
N
3
P
P
B
B
2
1
/
/
O
O
S
S
C
C
2
1
1
X
/
S
D
O
/
A
N
5
C
K
1
/
A
N
4
D
I
/
S
D
A
/
A
N
6
P
P
B
B
2
1
/
/
O
O
S
S
C
C
2
1
1
X
/
S
D
O
/
A
N
5
V
D
D
&
A
V
D
D
L
C
/
A
K
N
/
/
S
V
7
C
R
D
I
/
S
D
A
/
A
N
6
P
B
0
/
R
E
S
C
C
S
K
E
F
V
D
D
&
A
V
D
D
C
K
/
/
S
V
C
R
L
E
/
A
P
P
N
C
C
7
1
0
/
/
T
T
P
P
1
1
B
B
_
_
1
0
/
/
/
S
S
S
C
O
O
O
M
1
2
3
4
5
0
1
/
/
/
/
/
/
T
P
[
[
[
[
2
/
P
C
K
/
C
1
+
P
B
0
/
R
E
S
C
C
S
K
F
0
0
1
2
3
4
C
C
M
M
I
N
T
/
T
P
2
_
0
/
C
P
P
C
C
1
0
/
/
T
T
P
P
1
1
B
B
_
_
1
0
/
/
/
S
S
S
C
O
O
O
M
1
3
2
3
4
5
/
/
/
/
T
P
[
[
2
/
P
C
K
/
P
C
C
1
7
+
/
[
T
P
1
A
]
3
I
I
T
T
N
N
T
T
0
1
]
]
/
/
[
T
P
I
N
T
]
0
0
1
2
C
C
M
M
I
N
T
/
T
P
2
_
P
0
C
/
C
6
/
1
[
-
T
P
0
_
0
]
/
S
C
O
M
2
P
0
_
1
P
C
7
/
[
T
P
1
A
]
I
I
N
N
T
T
0
1
]
]
/
/
[
T
P
I
N
P
T
D
]
3
/
/
[
P
T
2
C
_
K
1
1
]
/
[
S
D
O
]
C
P
K
2
]
/
[
S
C
S
]
P
C
6
/
[
T
P
0
_
0
]
/
S
C
O
M
2
P
P
0
D
_
2
1
/
/
[
T
T
P
C
1
K
B
0
_
]
2
/
/
[
[
S
P
D
C
I
K
/
]
S
D
A
]
2
_
0
]
/
[
S
D
O
H
T
6
6
F
4
0
H
T
6
6
F
4
0
2
4
S
K
D
I
P
-
A
/
S
O
P
-
A
/
S
S
O
P
-
A
2
8
S
K
D
I
P
-
A
/
S
O
P
-
A
/
S
S
O
P
-
A
Note: 1. Bracketed pin names indicate non-default pinout remapping locations.
2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the
²/² sign can be used for higher priority.
3. VDD&AVDD means the VDD and AVDD are the double bonding.
Rev. 1.60
11
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
3
3
3
3
3
1
2
3
3
0
4
3
5
4
6
7
8
9
0
1
2
3
4
5
6
7
8
9
1
3
2
2
2
2
2
2
2
2
2
P
P
P
P
P
P
P
P
P
P
D
D
D
D
C
C
C
C
E
E
2
3
4
5
6
7
0
1
/
/
/
/
/
/
/
/
[
[
[
[
[
[
T
T
T
T
T
T
T
T
C
C
P
P
P
P
K
0
]
/
P
B
5
/
S
C
S
/
V
R
E
F
2
2
2
2
5
2
6
3
3
7
3
8
9
0
1
2
1
2
3
4
5
6
7
8
2
2
2
2
2
1
1
1
4
3
2
1
0
9
8
7
9
8
7
6
5
4
3
2
1
K
1
]
/
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
4
P
P
P
P
P
P
P
P
D
D
D
D
C
C
C
C
0
1
2
3
6
7
0
1
/
/
/
/
/
/
/
/
[
[
[
[
[
[
T
T
T
T
T
T
T
T
C
P
C
C
P
P
K
2
]
/
[
S
C
S
]
A
P
7
/
S
C
K
/
S
C
L
/
A
N
7
2
0
0
1
_
_
_
A
1
1
0
]
]
]
P
A
3
/
I
N
T
0
/
C
0
-
/
A
N
3
2
_
0
0
]
]
/
/
[
S
S
D
O
]
/
[
S
C
K
/
S
C
L
]
P
A
6
/
S
D
I
/
S
D
A
/
/
A
A
N
N
6
5
P
A
2
/
T
C
K
0
/
C
0
+
/
A
N
2
K
K
0
1
]
]
/
/
[
[
S
S
D
D
I
O
/
S
D
A
]
1
P
A
5
/
C
X
/
S
D
O
P
A
1
/
T
P
1
A
/
A
N
1
]
H
T
6
6
F 4
4
0
H
T
6
6
F
4
0
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
4
0
Q
F
3
N
-
A
]
/
P
A
0
/
C
0
X
/
T
T
P
0
3
_
2
0
/
Q
A
F
N
N
0
-
A
0
1
_
A
C
O
M
2
3 /
P
A
I
N
T
0
/
C
0
-
/
A
N
/
P
S
1
C
B
O
_
M
0
0
P
F
1
/
[
C
1
X
]
]
/
S
C
O
M
3
2
P
A
/
T
+
C
/
K
A
0
N
/
2
C
0
P
1
B
_
1
/
P
F
0
/
[
C
0
X
]
P
1
B
_
0
/
S
C
O
M
0
A
P
1
/
T
P
1
A
/
A
N
1
4
/
[
T
P
1
B
_
2
P
E
I
7
N
/
[
1
]
P
1
B
_
1
/
S
C
O
M
1
/
P
A
0
C
0
X
/
T
P
0
_
0
/
A
N
0
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
0
5
P
F
1
/
[
C
1
X
]
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
P
A
0
/
C
0
X
/
T
P
0
_
0
/
P
P
P
P
P
P
P
P
P
P
P
P
P
N
N
N
P
P
P
P
P
P
P
P
A
A
A
A
A
A
A
A
B
B
B
D
D
C
N
1
2
3
4
5
6
7
5
6
7
0
/
/
/
/
/
/
/
/
/
/
T
T
I
I
C
S
S
S
[
[
P
C
1
A
/
A
N
1
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
P
P
F
F
1
0
/
/
[
[
C
C
1
0
X
X
]
]
K
0
/
C
0
+
/
A
N
2
N
N
T
T
0
1
/
/
C
T
0
-
/
A
N
3
P
P
E
E
7
6
/
/
[
[
I
I
N
N
T
T
1
0
]
]
C
K
1
/
A
N
4
1
X
/
S
D
O
/
A
N
5
V
S
S
&
A
V
S
S
D
C
C
I
K
S
/
S
D
A
/
A
N
6
P
P
B
B
4
3
/
/
X
X
T
T
2
1
/
/
S
V
C
R
L
E
/
A
N
7
F
P
P
B
B
2
1
/
/
O
O
S
S
C
C
2
1
S
S
D
D
O
I
]
3
3
3
3
3
4
3
5
4
6
7
4
8
4
4
9
4
0
1
2
3
4
/
S
D
A
]
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
P
B
5
/
S
C
S
1
2
3
4
5
6
7
8
9
/
V
R
E
F
P
P
P
P
P
P
P
P
P
P
P
D
D
D
E
E
E
E
C
C
C
C
3
4
5
/
/
/
[
[
[
T
T
T
C
P
P
K
1
]
/
3
3
3
3
2
2
2
2
2
2
2
3
2
1
0
9
8
7
6
5
4
3
P
A
7
/
S
C
K
/
S
C
L
/
A
N
7
2
0
_
_
1
1
V
D
D
&
A
V
D
D
6
7
4
/
/
/
[
[
[
S
S
I
C
C
K
S
/
]
S
C
L
]
P
A
6
/
S
D
I
/
S
D
A
/
/
A
A
N
N
6
5
P
B
0
/
R
E
S
P
A
5
/
C
1
X
/
S
D
O
0
1
2
3
P
E
5
N
T
0
]
/
[
P
I
N
T
]
/
T
P
2
_
1
T
P
A
4
/
I
N
1
/
T
C
K
1
/
A
N
4
H
T
6
6
F
4
0
P
A
3
/
I
N
T
0
/
C
0
-
/
A
N
3
P
E
4
/
[
T
P
1
B
_
2
]
C
C
C
4
4
L
Q
F
P
-
A
P
A
2
/
T
+
C
/
K
A
0
N
/
2
C
0
P
P
C
C
1
0
/
/
T
T
P
P
1
1
B
B
_
_
1
0
/
/
S
S
C
C
O
O
M
M
1
0
P
A
1
/
T
P
1
A
/
A
N
1
6
7
0
/
/
/
[
[
T
T
T
P
P
0
1
_
A
0
P
A
0
/
C
0
X
/
T
P
0
_
0
/
A
N
0
]
/
P
F
1
/
[
1
1
C
0
1
X
X
]
]
P
1
B
_
0
N
C
C
C
C
D
D
D
D
D
2
3
5
0
1
2
3
4
/
/
/
/
/
/
/
/
T
P
[
[
[
[
[
[
C
K
2
/
P
C
K
/
C
1
+
P
F
0
/
[
C
1
0
1
/
T
P
1
B
_
1
/
S
P
C
7
/
[
T
P
1
A
]
/
S
C
O
M
3
I
N
T
/
2
T
P
2
_
0
/
C
1
-
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
P
C
6
/
[
T
P
0
_
0
]
/
S
C
O
M
2
I
T
T
T
T
T
N
T
1
]
/
T
P
0
_
1
/
T
P
1
B
_
2
/
[
P
C
K
]
P
P
P
P
E
E
E
E
3
2
1
0
C
P
C
C
P
K
]
/
[
S
C
S
]
2
_
0
]
/
[
S
D
O
]
/
[
S
C
K
/
S
C
L
]
K
K
0
1
]
]
/
/
[
[
S
S
D
D
I
O
/
S
D
A
]
]
P
D
5
/
[
T
P
0
_
1
]
2
_
1
]
H
T
6
6
F
4
0
4
8
S
S
O
P
-
A
4
4
8
4
7
6
4
4
4
5
4
4
4
2
3
4
1
0
3
3
8
9
1
2
3
4
5
6
7
8
9
3
3
3
3
3
3
3
2
2
2
2
2
6
5
4
3
2
1
0
9
8
7
6
5
P
P
P
P
P
P
P
P
P
N
P
P
D
D
D
E
E
E
E
C
C
3
4
5
/
/
/
[
[
[
T
T
T
C
P
P
K
1
]
N
C
2
0
_
_
1
1
P
B
5
/
S
C
S
/
V
R
E
F
P
A
7
/
S
C
K
/
S
C
L
/
A
N
7
0
1
2
3
P
A
6
/
S
D
I
/
S
D
A
/
/
A
A
N
N
6
5
P
A
5
/
C
1
X
/
0
S
D
O
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
4
6 F
H
T
6
4
0
4
8
Q
F
N
-
A
P
A
3
/
I
N
T
/
C
0
-
/
A
N
3
6
7
/
/
[
[
T
T
P
P
0
1
_
A
0
P
A
2
/
C
T
0
C
+
K
/
0
A
/
N
2
]
P
A
1
/
T
P
1
A
/
A
N
1
C
P
A
0
/
C
0
X
/
T
1
1
1
0
1
2
P
0
_
0
/
A
N
0
C
C
0
1
/
/
T
T
P
1
B
_
0
N
C
P
1
B
_
1
P
F
1
/
[
C
1
X
]
1
3
1
4
1
1
7
5
1
1
8
6
1
9
2
0
2
1
2
2
2
3
2
4
Note: 1. Bracketed pin names indicate non-default pinout remapping locations.
2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the
²/² sign can be used for higher priority.
3. VDD&AVDD means the VDD and AVDD are the double bonding.
Rev. 1.60
12
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
P
A
0
/
C
0
X
/
T
1
2
3
4
5
6
7
8
9
1
1
1
1
1
P
0
_
2
2
2
2
2
2
2
2
2
1
1
1
1
1
0
8
7
6
5
4
3
2
1
0
9
8
7
6
5
/
P
P
P
P
P
P
P
P
P
P
P
P
P
P
A
A
A
A
A
A
A
A
B
C
C
C
C
D
D
N
1
2
0
/
/
T
T
P
C
1
A
/
A
N
1
V
S
S
&
A
V
S
S
K
0
/
C
0
+
/
A
N
2
P
P
B
B
4
3
/
/
X
X
T
T
2
1
3
/
I
N
T
0
/
C
0
-
/
A
N
3
4
5
6
7
5
/
/
/
/
/
I
C
S
S
S
N
T
1
/
T
C
K
1
/
A
N
4
P
P
B
B
2
1
/
/
O
O
S
S
C
C
2
1
1
X
/
S
D
O
/
A
N
5
D
I
/
S
D
A
/
A
N
6
3
3
3
3
3
1
2
3
3
0
4
3
5
4
6
7
8
9
0
1
2
3
4
5
6
7
8
9
3
2
2
2
2
2
2
2
2
2
V
D
D
C
K
/
/
S
V
C
R
L
E
/
A
N
C
7
1
P
P
P
P
P
P
P
P
P
P
D
D
D
D
C
C
C
C
E
E
2
3
4
5
6
7
0
1
/
/
/
/
/
/
/
/
[
[
[
[
[
[
T
T
T
T
T
T
T
T
C
C
P
P
P
P
K
0
]
/
[
P
B
5
/
S
C
S
/
V
R
E
F
9
8
7
6
5
4
3
2
1
K
1
]
/
T
P
A
7
/
S
C
K
/
S
C
L
/
A
N
7
P
B
0
/
R
E
S
C
C
S
K
F
2
0
0
1
_
_
_
A
1
1
0
]
]
]
P
A
6
/
S
D
I
/
S
D
A
/
/
A
A
N
N
6
5
P
P
C
C
1
0
/
/
T
T
P
P
1
1
B
B
_
_
1
0
/
/
S
S
C
C
C
O
O
M
M
M
1
0
2
3
4
5
0
1
/
/
/
/
/
/
T
P
[
[
[
[
2
/
P
C
K
/
+
P
A
5
/
C
1
X
/
S
D
O
0
1
2
3
4
I
N
T
/
T
P
2
_
0
/
C
1
-
4
/
H
T
6
6
F 5
4
0
P
A
/
I
N
T
1
/
T
C
K
1
/
A
N
4 0
-
1
Q
F
3
N
-
A
]
/
S
P
A
3
/
I
N
T
0
/
C
0
/
A
N
P
C
7
/
[
T
P
1
A
]
/
S
O
3
I
I
T
T
N
N
T
T
0
1
]
]
/
/
[
T
P
I
N
T
]
/
T
C
K
3
/
T
P
2
_
P
1
B
_
0
/
S
P
A
/
2
/
T
+
C
B
/
K
A
0
N
/
2
C
0
P
C
6
/
[
T
P
0
_
0
]
/
S
C
O
M
2
P
0
_
1
T
P
1
_
2
/
[
P
C
K
]
P
1
B
_
1
/
S
P
A
1
/
T
P
1
A
/
A
N
1
P
D
3
/
[
T
C
K
1
]
/
T
P
3
_
0
/
[
S
D
O
]
C
P
K
2
]
/
T
P
3
_
1
/
[
S
C
S
]
X /
4
/
[
T
P
1
B
_
2
]
P
A
0
/
C
0
T
P
0
_
0
/
A
N
0
1
0
1
C
5
/
[
T
P
3
_
0
]
P
F
1
/
[
C
X
]
]
P
D
2
/
[
T
C
K
0
]
/
[
S
D
I
/
S
D
A
]
2
_
0
]
/
[
S
D
O
]
/
[
S
C
K
/
S
L
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
H
T
6
6
F
5
0
2
8
S
K
D
I
P
-
A
/
S
O
P
-
A
/
S
S
O
P
-
A
P
A
0
/
C
0
X
/
T
P
0
_
0
/
P
P
P
P
P
P
P
P
P
P
P
P
P
N
N
N
P
P
P
P
P
P
P
P
A
A
A
A
A
A
A
A
B
B
B
D
D
C
N
1
2
3
4
5
6
7
5
6
7
0
/
/
/
/
/
/
/
/
/
/
T
T
I
I
C
S
S
S
[
[
P
C
1
A
/
A
N
1
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
P
P
F
F
1
0
/
/
[
[
C
C
1
0
X
X
]
]
K
0
/
C
0
+
/
A
N
2
N
N
T
T
0
1
/
/
C
T
0
-
/
A
N
3
P
P
E
E
7
6
/
/
[
[
I
I
N
N
T
T
1
0
]
]
C
K
1
/
A
N
4
1
X
/
S
D
O
/
A
N
5
V
S
S
&
A
V
S
S
D
C
C
I
K
S
/
S
D
A
/
A
N
6
P
P
B
B
4
3
/
/
X
X
T
T
2
1
/
/
S
V
C
R
L
E
/
A
N
7
F
P
P
B
B
2
1
/
/
O
O
S
S
C
C
2
1
S
S
D
D
O
I
]
/
S
D
A
]
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
V
D
D
&
A
V
D
D
6
7
4
/
/
/
[
[
[
S
S
I
C
C
K
S
/
]
S
C
L
]
3
3
3
3
3
4
3
5
4
6
7
4
8
4
4
9
4
0
1
2
3
4
P
B
0
/
R
E
S
P
B
5
/
S
C
S
1
2
3
4
5
6
7
8
9
/
V
R
E
F
P
P
P
P
P
P
P
P
P
P
P
D
D
D
E
E
E
E
C
C
C
C
3
4
5
/
/
/
[
[
[
T
T
T
C
P
P
K
1
]
/
T
3
3
3
3
2
2
2
2
2
2
2
3
2
1
0
9
8
7
6
5
4
3
P
E
5
/
[
T
P
3
_
0
]
N
T
0
]
/
[
P
I
N
T
]
/
T
P
2
_
1
K
P
A
7
/
S
C
/
S
C
L
/
A
N
7
2
0
_
_
1
1
]
]
P
A
6
/
S
D
I
/
S
D
A
/
/
A
A
N
N
6
5
P
E
4
/
[
T
P
1
B
_
2
]
C
C
C
P
A
5
/
C
1
X
/
S
D
O
0
1
2
3
P
P
C
C
1
0
/
/
T
T
P
P
1
1
B
B
_
_
1
0
/
/
S
S
C
C
O
O
M
M
1
0
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
4
H
T
6
6
F
5
0
P
A
3
/
I
N
T
0
/
C
0
-
/
A
N
3
4
4
L
Q
F
P
-
A
P
A
+
2
/
T
+
C
/
K
A
0
N
/
2
C
0
/
[
T
P
3
_
1
]
N
C
C
C
C
D
D
D
D
D
2
3
5
0
1
2
3
4
/
/
/
/
/
/
/
/
T
P
[
[
[
[
[
[
C
K
2
/
P
C
K
/
C
1
P
A
1
/
T
P
1
A
/
A
N
1
6
7
0
1
/
/
/
/
[
[
T
T
P
P
0
1
_
A
0
]
/
P
C
7
/
[
T
P
1
A
]
/
S
C
O
M
3
I
N
T
/
2
T
P
2
_
0
/
C
1
-
P
A
0
/
C
0
X
/
T
P
0
_
0
/
A
N
0
]
/
S
P
C
6
/
[
T
P
0
_
0
]
/
S
C
O
M
2
I
T
T
T
N
T
1
]
/
T
P
0
_
1
/
T
P
1
B
_
2
/
[
P
C
K
]
P
P
F
1
/
[
1
C
0
1
1
X
]
]
T
P
1
B
_
0
/
S
C
O
P
E
3
/
[
T
P
3
_
1
]
C
P
C
C
P
K
]
/
[
S
C
S
]
F
0
/
[
1
C
0
X
T
P
1
B
_
1
/
S
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
P
P
P
E
E
E
2
1
0
2
_
0
]
/
[
S
D
O
]
/
[
S
C
K
/
S
C
L
]
K
K
0
1
]
]
/
/
[
[
S
S
D
D
I
O
/
S
D
A
]
T
T
]
P
D
5
/
[
T
P
0
_
1
]
2
_
1
]
H
T
6
6
F
5
0
4
8
S
S
O
P
-
A
4
8
4
4
6
7
4
4
4
4
5
4
3
2
4
4
0
1
3
3
3
8
9
1
2
3
4
5
6
7
8
9
3
3
3
3
3
3
3
2
2
2
2
2
6
5
4
3
2
1
0
9
8
7
6
5
P
P
P
P
P
P
P
P
P
N
P
P
D
D
D
E
E
E
E
C
C
3
4
5
/
/
/
[
[
[
T
T
T
C
P
P
K
1
]
/
N
C
2
0
_
_
1
1
]
]
P
B
5
/
S
C
S
/
V
R
E
F
P
A
7
/
S
C
K
/
S
C
L
/
A
N
7
0
1
2
3
P
A
6
/
S
D
I
/
S
D
A
/
A
A
N
N
6
5
P
A
5
/
C
1
X
/
S
D
O
/
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
4
6 F
H
T
6
5
0
4
8
Q
F
N
-
A
/
[
T
P
3
_
1
]
P
A
3
/
I
N
T
0
/
C
0
-
/
A
N
3
6
7
/
/
[
[
T
T
P
P
0
1
_
A
0
]
P
A
2
/
C
T
0
C
+
K
/
0
A
/
N
2
]
/
S
P
A
1
/
T
P
1
A
/
A
N
1
C
P
A
0
/
C
0
X
/
T
1
1
1
0
1
2
0
_
0
/
A
N
0
0
C
C
/
T
P
1
B
_
0
/
S
N
C
1
/
T
P
1
B
_
1
/
P
F
1
/
[
C
1
X
]
1
3
1
4
1
1
7
5
1
1
8
6
1
9
2
0
2
1
2
2
2
3
2
4
Note: 1. Bracketed pin names indicate non-default pinout remapping locations.
2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the
²/² sign can be used for higher priority.
3. VDD&AVDD means the VDD and AVDD are the double bonding.
Rev. 1.60
13
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
3
3
3
3
3
4
3
5
4
6
7
4
8
4
4
9
4
0
1
2
3
4
3
3
3
3
3
1
2
3
3
3
0
4
3
5
4
6
7
8
9
0
P
B
5
/
S
C
S
1
2
3
4
5
6
7
8
9
/
V
R
E
F
3
3
3
3
2
2
2
2
2
2
2
3
2
1
0
9
8
7
6
5
4
3
P
P
P
P
P
P
P
P
P
P
P
D
D
D
E
E
E
E
C
C
C
C
3
4
5
/
/
/
[
[
[
T
T
T
C
P
P
K
1
]
/
T
P
3
_
0
1
2
3
4
5
6
7
8
9
1
3
2
2
2
2
2
2
2
2
2
P
P
P
P
P
P
P
P
P
P
D
D
D
D
C
C
C
C
E
E
2
3
4
5
6
7
0
1
/
/
/
/
/
/
/
/
[
[
[
[
[
[
T
T
T
T
T
T
T
T
C
C
P
P
P
P
K
0
]
/
[
S
D
I
/
S
D
A
]
P
B
5
/
S
C
S
/
V
R
E
F
P
A
7
/
S
C
K
/
S
C
L
/
A
N
7
2
0
_
_
1
1
]
]
9
8
7
6
5
4
3
2
1
K
1
]
/
T
P
3
_
0
/
[
S
D
O
]
/
[
S
C
K
/
S
C
L
]
P
A
7
/
S
C
K
/
S
C
L
/
A
N
7
P
A
6
/
S
D
I
/
S
D
A
/
/
A
A
N
N
6
5
2
0
0
1
_
_
_
A
1
1
0
]
]
]
P
A
6
/
S
D
I
/
S
D
A
/
/
A
A
N
N
6
5
P
A
5
/
C
1
X
/
S
D
O
0
1
2
3
/
/
/
/
[
[
[
[
I
I
I
T
N
N
N
T
T
T
0
1
2
]
]
]
P
A
5
/
C
1
X
/
S
D
O
P
A
4
2
/
I
N
T
1
/
T
C
K
1
/
A
N
4
/
S
C
O
M
P A
3
H
T
6
6
F 6
4
0
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
H
T
6
6
F
6
0
3
/
I
N
T
0
/
C
0
-
/
A
N
3
4
0
Q
F
3
N
-
A
]
/
S
C
O
M
P
A
3
/
I
N
T
0
/
C
0
-
/
A
N
4
4
L
Q
F
P
-
A
P
A
2
/
T
C
K
0
/
C
0
+
/
A
N
2
P
3
_
1
]
P
1
B
_
0
/
S
C
O
M
0
1
P
A
2
/
T
C
K
0
/
C
0
+
/
A
N
2
P
A
1
/
T
P
1
A
/
A
N
1
6
7
0
1
/
/
/
/
[
[
T
T
T
T
P
P
0
1
_
A
0
]
/
S
C
O
P
1
B
_
1
/
S
C
O
M
P
A
1
/
T
P
1
A
/
A
N
1
P
A
0
/
C
0
X
/
T
P
0
_
0
/
A
N
0
]
/
S
C
O
M
4
/
[
T
P
1
B
_
2
]
P
A
0
/
C
0
X
/
T
P
0
_
0
/
A
N
0
P
F
1
/
/
[
C
1
1
X
0
]
/
A
N
N
1
1
0
P
1
B
_
0
/
S
C
O
M
0
5
/
[
T
P
3
_
0
]
P
F
1
/
[
C
1
X
]
/
A
N
1
1
P
F
0
[
C
0
1
X
1
]
/
A
1
P
1
B
_
1
/
S
C
O
M
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
N
N
C
C
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
V
P
C
C
C
C
D
D
D
D
D
D
E
E
E
E
G
C
C
C
C
E
E
B
D
B
2
3
4
5
0
1
2
3
4
5
/
/
/
/
/
/
/
/
/
/
T
P
I
I
[
[
[
[
[
[
C
K
2
/
P
C
K
/
C
1
+
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
I
N
T
/
T
P
2
_
0
/
C
1
-
P
D
7
/
[
S
C
S
]
N
N
T
T
T
T
T
T
T
T
2
3
K
/
/
[
[
I
I
N
N
T
T
0
1
]
]
/
/
[
T
P
I
N
T
]
/
T
C
K
3
/
T
P
2
_
1
P
D
6
/
[
S
C
K
/
S
C
L
]
]
P
0
_
1
/
T
P
1
B
_
2
/
[
P
C
K
]
P
B
7
/
[
S
D
I
/
S
D
A
C
P
C
C
P
P
2
]
/
T
P
3
_
1
/
[
S
C
S
]
P
B
6
/
[
S
D
O
]
2
_
0
]
/
[
S
D
O
]
/
[
S
C
K
/
S
C
L
]
P
C
F
2
K
K
0
1
]
]
/
/
[
T
S
D
I
/
S
D
A
]
P
B
5
/
S
C
S
/
V
R
E
F
P
3
_
0
/
[
S
D
O
]
/
[
S
C
K
/
S
C
L
]
4 4
4
8
4
4
6
7
4
4
4
5
2
3
4
4
0
1
1
2
3
4
5
6
7
8
9
3
3
3
3
3
3
3
2
2
2
2
2
6
5
4
3
2
1
0
9
8
7
6
5
P
P
P
P
P
P
P
P
P
N
P
P
D
D
D
E
E
E
E
C
C
3
4
5
/
/
/
[
[
[
T
T
T
C
P
P
K
1
]
/
T
P
3
_
N
C
P
A
7
/
S
K
/
S
C
L
/
/
A
A
N
N
7
6
2
0
_
_
1
1
]
]
2
0
_
_
1
1
]
]
P
B
5
/
S
C
S
/
V
R
E
F
P
A
6
/
S
D
I
/
S
D
A
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
P
A
7
/
S
C
K
/
S
C
L
/
A
N
7
0
1
2
3
/
/
/
/
[
[
[
[
I
I
I
T
N
N
N
T
T
T
0
1
2
]
]
]
P
A
6
/
S
D
I
/
S
D
A
/
/
A
A
N
N
6
5
P
A
5
/
S
C
D
1
O
X
/
/
A
N
5
0
1
2
3
/
/
/
/
[
[
[
[
I
I
I
T
N
N
N
T
T
T
0
1
2
]
]
]
P
A
5
/
C
1
X
/
S
D
O
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
4
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
4
6 F
H
T
6
6
0
P
A
3
/
I
N
T
0
/
C
0
-
/
/
A
A
N
N
3
2
4
8
L
Q
F
P
-
A
/
Q
F
N
-
A
P
3
_
1
]
P
A
3
/
I
N
T
0
/
C
0
-
/
A
N
3
P
A
2
/
T
C
K
0
/
C
0
+
P
3
_
1
]
P
A
2
/
T
C
K
0
/
C
0
+
/
A
N
2
6
7
/
/
[
[
T
T
P
P
0
1
_
A
0
]
/
S
C
O
]
/
S
C
O
M
P
A
1
/
T
P
1
A
/
A
N
1
P
A
1
/
T
P
1
A
/
A
N
1
1
/
[
C
1
X
]
C
P
A
0
/
C
0
X
/
T
1
1
1
0
1
2
P
0
_
0
/
A
N
0
P
A
0
/
C
0
X
/
T
P
0
_
0
/
A
N
6
7
0
1
0
/
/
/
/
[
[
T
T
T
T
P
P
0
1
_
A
0
]
/
S
C
O
M
2
C
C
0
1
/
/
T
T
P
1
B
_
0
/
S
C
O
M
N
C
P
P
F
F
1
/
[
C
1
X
]
/
A
N
1
1
C
O
M
3
]
/
S
P
1
B
_
1
/
S
C
O
M
P
F
1
/
[
C
1
X
]
/
A
N
1
1
1
3
1
4
1
1
7
5
1
1
8
6
1
9
2
0
2
1
2
2
2
3
2
4
0
/
[
C
0
X
]
/
A
N
1
0
P
P
1
1
B
B
_
_
0
1
/
/
S
S
C
C
O
O
M
M
0
1
P
P
E
E
7
6
/
/
[
[
I
I
N
N
T
T
1
0
]
]
/
/
A
A
N
N
9
8
4
5
0
/
/
/
[
[
R
T
T
P
P
1
3
B
_
_
2
]
V
S
S
&
A
V
S
S
0
]
P
P
B
B
4
3
/
/
X
X
T
T
2
1
E
S
D
&
A
V
D
D
P
B
2
/
O
S
C
2
1
/
O
S
C
1
H
T
6
6
F
6
0
4
8
S
S
O
P
-
A
4
4
5
5
8
5
9
0
1
2
4
4
4
5
6
7
4
4
4
4
0
4
1
2
3
4
3
3
3
3
3
3
9
8
7
6
5
4
P
P
F
3
2
1
2
3
4
5
6
7
8
9
P
D
3
4
5
/
/
/
[
[
[
T
T
T
C
P
P
K
1
]
/
T
P
3
_
F
P
D
2
0
_
_
1
1
]
]
P
B
5
/
S
C
S
/
V
R
E
F
P
D
P
A
7
/
S
C
K
/
S
C
L
/
A
N
7
P
E
0
1
2
3
/
/
/
/
[
[
[
[
I
I
I
T
N
N
N
T
T
T
0
1
2
]
]
]
P
A
6
/
S
D
I
/
S
D
A
/
/
A
A
N
N
6
5
P
E
P
A
5
/
C
1
X
/
0
S
D
O
P
E
H
T
6
6
F
6
0
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
4
3
3
3
3
2
2
2
3
2
1
0
9
8
7
P
E
P
3
_
1
]
5
2
Q
F
P
-
A
P
A
3
/
I
N
T
/
C
0
-
/
A
N
3
P
F
6
P
A
2
/
T
C
K
0
/
C
0
+
/
A
N
2
P
F
7
P
A
1
/
T
P
1
1
1
1
1
A
0
1
2
3
/
A
N
1
P
P
P
P
G
G
C
C
0
/
[
C
0
X
X
]
]
P
A
0
/
C
0
X
/
T
P
0
_
0
/
A
N
0
1
/
[
C
1
P
F
F
1
/
[
C
1
X
]
/
A
A
N
1
1
6
7
/
/
[
[
T
T
P
P
0
1
_
A
0
]
/
S
C
O
P
0
/
[
C
0
X
]
/
N
1
0
]
/
S
C
O
M
1
4
1
5
1
6
1
7
2
1
3
8
2
1
4
9
2
2
5
0
2
2
6
1
2
2
Note: 1. Bracketed pin names indicate non-default pinout remapping locations.
2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the
²/² sign can be used for higher priority.
3. VDD&AVDD means the VDD and AVDD are the double bonding.
Rev. 1.60
14
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Pin Description
With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1
etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such
as the Analog to Digital Converter, Serial Port pins etc. The function of each pin is listed in the following table, however
the details behind how each pin is configured is contained in other sections of the datasheet.
The following tables only include the pins which are directly related to the MCU. The pin descriptions of the additional
peripheral functions are located at the end of the datasheet along with the relevant peripheral function functional de-
scription.
HT66F20
Pin Name
PA0~PA7
Function
OP
I/T
O/T
Pin-Shared Mapping
PAWU
PAPU
Port A
ST
CMOS
¾
PB0~PB5
PC0~PC3
AN0~AN7
VREF
Port B
Port C
PBPU
PCPU
ST
ST
AN
AN
AN
AN
CMOS
CMOS
¾
¾
¾
ADC input
ACERL
ADCR1
PA0~PA7
PB5
ADC reference input
Comparator 0, 1 input
Comparator 0, 1 input
Comparator 0, 1 output
TM0, TM1 input
TM0 I/O
¾
C0-, C1-
C0+, C1+
C0X, C1X
TCK0, TCK1
TP0_0
TP1_0, TP1_1
INT0, INT1
PINT
PA3, PC3
PA2, PC2
PA0, PA5
PA2, PA4
PA0
¾
CP0C
CP1C
¾
CMOS
¾
ST
ST
ST
ST
ST
¾
TMPC0
TMPC0
¾
¾
CMOS
CMOS
¾
TM1 I/O
PA1, PC0
PA3, PA4
PC3
Ext. Interrupt 0, 1
Peripheral Interrupt
Peripheral Clock output
SPI Data input
SPI Data output
SPI Slave Select
SPI Serial Clock
I2C Clock
¾
¾
PCK
CMOS
PC2
¾
¾
ST
SDI
PA6
¾
¾
CMOS
CMOS
CMOS
NMOS
NMOS
SCOM
¾
SDO
PA5
¾
¾
SCS
ST
PB5
¾
SCK
ST
PA7
¾
SCL
ST
PA7
¾
SDA
I2C Data
ST
PA6
¾
SCOM0~SCOM3
OSC1
SCOM0~SCOM3
HXT/ERC pin
HXT pin
SCOMC
CO
CO
CO
CO
CO
PC0, PC1, PC2, PC3
PB1
¾
HXT
¾
OSC2
HXT
¾
PB2
XT1
LXT pin
LXT
¾
PB3
XT2
LXT pin
LXT
¾
PB4
RES
Reset input
ST
PB0
VDD
Power supply *
ADC power supply *
Ground **
PWR
PWR
PWR
PWR
¾
¾
¾
¾
¾
¾
¾
¾
¾
AVDD
¾
VSS
¾
AVSS
ADC ground **
¾
Rev. 1.60
15
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Note: I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output; NMOS: NMOS output
SCOM: Software controlled LCD COM; AN: Analog input pin
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
*: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together
internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together
internally with VSS.
As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed
pins may be present on package types with smaller numbers of pins.
HT66F30
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
PAWU
PAPU
PA0~PA7
Port A
ST
CMOS
¾
PB0~PB5
PC0~PC7
AN0~AN7
VREF
Port B
Port C
PBPU
PCPU
ST
ST
AN
AN
AN
AN
CMOS
CMOS
¾
¾
¾
ADC input
ACERL
ADCR1
PA0~PA7
PB5
ADC reference input
Comparator 0, 1 input
Comparator 0, 1 input
Comparator 0, 1 output
TM0, TM1 input
TM0 I/O
¾
C0-, C1-
C0+, C1+
C0X, C1X
TCK0, TCK1
TP0_0, TP0_1
TP1A
PA3, PC3
PA2, PC2
PA0, PA5
PA2, PA4
PA0, PC5
PA1
¾
CP0C
CP1C
¾
CMOS
¾
ST
ST
ST
ST
ST
ST
¾
TMPC0
TMPC0
TMPC0
¾
¾
CMOS
CMOS
CMOS
¾
TM1 I/O
TP1B_0, TP1B_1
INT0, INT1
PINT
TM1 I/O
PC0, PC1
PA3, PA4
PC3 or PC4
PC2 or PC5
PA6 or PC0
PA5 or PC1
PB5 or PC6
PA7 or PC7
PA7 or PC7
PA6 or PC0
PC0, PC1, PC6, PC7
PB1
Ext. Interrupt 0, 1
Peripheral Interrupt
Peripheral Clock output
SPI Data input
SPI Data output
SPI Slave Select
SPI Serial Clock
I2C Clock
PRM0
PRM0
PRM0
PRM0
PRM0
PRM0
PRM0
PRM0
SCOMC
CO
¾
PCK
CMOS
¾
SDI
ST
¾
SDO
CMOS
CMOS
CMOS
NMOS
NMOS
SCOM
¾
ST
ST
ST
ST
¾
SCS
SCK
SCL
SDA
I2C Data
SCOM0~SCOM3
OSC1
SCOM0~SCOM3
HXT/ERC pin
HXT pin
HXT
¾
HXT
¾
OSC2
CO
PB2
¾
LXT
¾
XT1
LXT pin
CO
PB3
XT2
LXT pin
CO
LXT
PB4
Rev. 1.60
16
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Pin Name
Function
Reset input
OP
CO
¾
I/T
O/T
¾
Pin-Shared Mapping
PB0
RES
VDD
ST
Power supply *
ADC power supply *
Ground **
PWR
PWR
PWR
PWR
¾
¾
¾
¾
¾
AVDD
VSS
¾
¾
¾
¾
AVSS
ADC ground **
¾
¾
Note: I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output; NMOS: NMOS output
SCOM: Software controlled LCD COM; AN: Analog input pin
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
*: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together
internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together
internally with VSS.
As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed
pins may be present on package types with smaller numbers of pins.
HT66F40
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
PAWU
PAPU
PA0~PA7
Port A
ST
CMOS
¾
PB0~PB7
PC0~PC7
PD0~PD7
PE0~PE7
PF0~PF1
AN0~AN7
VREF
Port B
Port C
Port D
Port E
Port F
PBPU
PCPU
PDPU
PEPU
PFPU
ST
ST
ST
ST
ST
AN
AN
CMOS
CMOS
CMOS
CMOS
CMOS
¾
¾
¾
¾
¾
¾
ADC input
ACERL
ADCR1
PA0~PA7
PB5
ADC reference input
¾
CP0C
CP1C
C0-, C1-
Comparator 0, 1 input
Comparator 0, 1 input
AN
AN
PA3, PC3
PA2, PC2
¾
¾
CP0C
CP1C
C0+, C1+
CP0C
CP1C
PRM0
C0X, C1X
Comparator 0, 1 output
CMOS
PA0, PA5 or PF0, PF1
¾
PA2, PA4, PC2 or
PD2, PD3, PD0
TCK0~TCK2
TP0_0, TP0_1
TP1A
TM0~TM2 input
TM0 I/O
PRM1
ST
ST
ST
ST
¾
TMPC0
PRM2
CMOS
CMOS
CMOS
PA0, PC5 or PC6, PD5
PA1 or PC7
TMPC0
PRM2
TM1 I/O
PC0, PC1, PC5 or
TMPC0
PRM2
TP1B_0~TP1B_2
TM1 I/O
-, -, PE4
Rev. 1.60
17
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
TMPC1
PRM2
TP2_0, TP2_1
TM2 I/O
ST
CMOS
PC3, PC4 or PD1, PD4
PA3, PA4 or PC4, PC5 or
PE6, PE7
INT0, INT1
Ext. Interrupt 0, 1
PRM1
ST
¾
PINT
PCK
Peripheral Interrupt
Peripheral Clock output
SPI Data input
SPI Data output
SPI Slave Select
SPI Serial Clock
I2C Clock
PRM0
PRM0
PRM0
PRM0
PRM0
PRM0
PRM0
PRM0
SCOMC
CO
ST
¾
PC3 or PC4
PC2 or PC5
PA6 or PD2 or PB7
PA5 or PD3 or PB6
PB5 or PD0 or PD7
PA7 or PD1 or PD6
PA7 or PD1 or PD6
PA6 or PD2 or PB7
PC0, PC1, PC6, PC7
PB1
¾
CMOS
SDI
ST
¾
SDO
CMOS
CMOS
CMOS
NMOS
NMOS
SCOM
¾
ST
ST
ST
ST
¾
SCS
SCK
SCL
SDA
I2C Data
SCOM0~SCOM3
OSC1
OSC2
XT1
SCOM0~SCOM3
HXT/ERC pin
HXT pin
HXT
¾
HXT
¾
CO
PB2
¾
LXT pin
CO
LXT
¾
PB3
XT2
LXT pin
CO
LXT
¾
PB4
RES
Reset input
CO
ST
PB0
VDD
Power supply *
ADC power supply *
Ground **
PWR
PWR
PWR
PWR
¾
¾
¾
¾
¾
¾
¾
¾
¾
AVDD
VSS
¾
¾
AVSS
ADC ground **
¾
Note: I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output; NMOS: NMOS output
SCOM: Software controlled LCD COM; AN: Analog input pin
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
*: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together
internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together
internally with VSS.
As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed
pins may be present on package types with smaller numbers of pins.
Rev. 1.60
18
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
HT66F50
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
PAWU
PAPU
PA0~PA7
Port A
ST
CMOS
¾
PB0~PB7
PC0~PC7
PD0~PD7
PE0~PE7
PF0~PF1
AN0~AN7
VREF
Port B
Port C
Port D
Port E
Port F
PBPU
PCPU
PDPU
PEPU
PFPU
ST
ST
ST
ST
ST
AN
AN
CMOS
CMOS
CMOS
CMOS
CMOS
¾
¾
¾
¾
¾
¾
ADC input
ACERL
ADCR1
PA0~PA7
PB5
ADC reference input
¾
CP0C
CP1C
C0-, C1-
Comparator 0, 1 input
Comparator 0, 1 input
AN
AN
PA3, PC3
PA2, PC2
¾
¾
CP0C
CP1C
C0+, C1+
CP0C
CP1C
PRM0
C0X, C1X
Comparator 0, 1 output
CMOS
PA0, PA5 or PF0, PF1
¾
PA2, PA4, PC2, PC4 or
TCK0~TCK3
TP0_0, TP0_1
TP1A
TM0~TM3 input
TM0 I/O
PRM1
ST
ST
ST
ST
ST
ST
ST
¾
PD2, PD3, PD0, -
TMPC0
PRM2
CMOS
CMOS
CMOS
CMOS
CMOS
¾
PA0, PC5 or PC6, PD5
PA1 or PC7
TMPC0
PRM2
TM1 I/O
PC0, PC1, PC5 or
TMPC0
PRM2
TP1B_0~TP1B_2
TP2_0, TP2_1
TP3_0, TP3_1
INT0, INT1
TM1 I/O
-, -, PE4
TMPC1
PRM2
TM2 I/O
PC3, PC4 or PD1, PD4
PD3, PD0 or PE5, PE3
TMPC1
PRM2
TM3 I/O
PA3, PA4 or PC4, PC5 or
PE6, PE7
Ext. Interrupt 0, 1
PRM1
PINT
Peripheral Interrupt
Peripheral Clock output
SPI Data input
SPI Data output
SPI Slave Select
SPI Serial Clock
I2C Clock
PRM0
PRM0
PRM0
PRM0
PRM0
PRM0
PRM0
PRM0
SCOMC
CO
ST
¾
PC3 or PC4
¾
PCK
CMOS
PC2 or PC5
SDI
ST
PA6 or PD2 or PB7
PA5 or PD3 or PB6
PB5 or PD0 or PD7
PA7 or PD1 or PD6
PA7 or PD1 or PD6
PA6 or PD2 or PB7
PC0, PC1, PC6, PC7
PB1
¾
SDO
CMOS
CMOS
CMOS
NMOS
NMOS
SCOM
¾
ST
ST
ST
ST
¾
SCS
SCK
SCL
SDA
I2C Data
SCOM0~SCOM3
OSC1
OSC2
XT1
SCOM0~SCOM3
HXT/ERC pin
HXT pin
HXT
¾
HXT
¾
CO
PB2
¾
LXT pin
CO
LXT
PB3
Rev. 1.60
19
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Pin Name
Function
OP
CO
CO
¾
I/T
¾
O/T
LXT
¾
Pin-Shared Mapping
PB4
XT2
RES
VDD
LXT pin
Reset input
ST
PB0
¾
Power supply *
ADC power supply *
Ground **
PWR
PWR
PWR
PWR
¾
AVDD
VSS
¾
¾
¾
¾
¾
¾
AVSS
ADC ground **
¾
¾
¾
Note: I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output; NMOS: NMOS output
SCOM: Software controlled LCD COM; AN: Analog input pin
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
*: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together
internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together
internally with VSS.
As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed
pins may be present on package types with smaller numbers of pins.
HT66F60
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
PAWU
PAPU
PA0~PA7
Port A
ST
CMOS
¾
PB0~PB7
PC0~PC7
PD0~PD7
PE0~PE7
PF0~PF7
PG0~PG1
Port B
Port C
Port D
Port E
Port F
Port G
PBPU
PCPU
PDPU
PEPU
PFPU
PGPU
ST
ST
ST
ST
ST
ST
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
¾
¾
¾
¾
¾
¾
PA0~PA7, PE6, PE7,
PF0, PF1
AN0~AN11
VREF
ADC input
AN
AN
AN
¾
¾
¾
ACERH
ADCR1
ADC reference input
Comparator 0, 1 input
PB5
CP0C
CP1C
C0-, C1-
PA3, PC3
CP0C
CP1C
C0+, C1+
C0X, C1X
Comparator 0, 1 input
Comparator 0, 1 output
AN
PA2, PC2
¾
CP0C
CP1C
PRM0
PA0, PA5 or PF0, PF1 or
PG0, PG1
CMOS
¾
PA2, PA4, PC2, PC4 or
TCK0~TCK3
TM0~TM3 input
TM0 I/O
PRM1
ST
ST
¾
PD2, PD3, PD0, -
TMPC0
PRM2
TP0_0, TP0_1
CMOS
PA0, PC5 or PC6, PD5
Rev. 1.60
20
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Pin Name
TP1A
Function
OP
I/T
O/T
Pin-Shared Mapping
TMPC0
PRM2
TM1 I/O
TM1 I/O
TM2 I/O
TM3 I/O
ST
CMOS
PA1 or PC7
PC0, PC1, PC5 or
TMPC0
PRM2
TP1B_0~TP1B_2
TP2_0, TP2_1
TP3_0, TP3_1
ST
ST
ST
CMOS
CMOS
CMOS
-, -, PE4
TMPC1
PRM2
PC3, PC4 or PD1, PD4
PD3, PD0 or PE5, PE3
TMPC1
PRM2
PA3, PA4, PC4, PC5 or
PC4, PC5, PE2, -, or
PE0, PE1, -, - or
INT0~INT3
Ext. Interrupt 0~3
PRM1
ST
¾
PE6, PE7, -, -
PINT
PCK
SDI
Peripheral Interrupt
Peripheral Clock output
SPI Data input
PRM0
PRM0
PRM0
ST
¾
PC3 or PC4
¾
CMOS
¾
PC2 or PC5
ST
PA6 or PD2 or PB7
PA5 or PD3 or PB6 or
PD1
SDO
SCS
SCK
SPI Data output
SPI Slave Select
SPI Serial Clock
PRM0
PRM0
PRM0
CMOS
CMOS
CMOS
¾
ST
ST
PB5 or PD0 or PD7
PA7 or PD1 or PD6 or
PD3
PA7 or PD1 or PD6 or
PD3
SCL
I2C Clock
PRM0
ST
NMOS
SDA
I2C Data
PRM0
SCOMC
CO
ST
¾
NMOS
SCOM
¾
PA6 or PD2 or PB7
SCOM0~SCOM3
OSC1
OSC2
XT1
SCOM0~SCOM3
HXT/ERC pin
HXT pin
PC0, PC1, PC6, PC7
HXT
¾
PB1
PB2
PB3
PB4
PB0
¾
CO
HXT
¾
LXT pin
CO
LXT
¾
XT2
LXT pin
CO
LXT
¾
RES
Reset input
Power supply *
ADC power supply *
Ground **
CO
ST
VDD
PWR
PWR
PWR
PWR
¾
¾
AVDD
VSS
¾
¾
¾
¾
¾
¾
AVSS
ADC ground **
¾
¾
¾
Note: I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output; NMOS: NMOS output
SCOM: Software controlled LCD COM; AN: Analog input pin
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
*: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together
internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together
internally with VSS.
As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed
pins may be present on package types with smaller numbers of pins.
Rev. 1.60
21
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Absolute Maximum Ratings
Supply Voltage...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
I
OL Total ................................................................80mA
I
OH Total..............................................................-80mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
f
SYS=8MHz
2.2
2.7
4.5
¾
5.5
5.5
5.5
1.1
2.7
2.4
5.0
3.3
7.5
V
¾
¾
Operating Voltage
(HXT, ERC, HIRC)
VDD
fSYS=12MHz
fSYS=20MHz
V
¾
V
¾
3V
5V
3V
5V
3V
5V
0.7
1.8
1.6
3.3
2.2
5.0
mA
mA
mA
mA
mA
mA
No load, fSYS=fH=4MHz,
ADC off, WDT enable
¾
Operating Current,
Normal Mode, fSYS=fH
(HXT, ERC, HIRC)
¾
No load, fSYS=fH=8MHz,
ADC off, WDT enable
IDD1
¾
¾
No load, fSYS=fH=12MHz,
ADC off, WDT enable
¾
Operating Current,
Normal Mode, fSYS=fH
(HXT)
No load, fSYS=fH=20MHz,
ADC off, WDT enable
IDD2
5V
6.0
9.0
mA
¾
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
10
30
20
50
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating Current, Slow Mode,
No load, fSYS=fL, ADC off,
WDT enable
IDD3
f
SYS=fL (LXT, LIRC)
1.5
3.0
0.55
1.30
¾
3.0
6.0
0.83
2.00
1
IDLE0 Mode Standby Current
(LXT or LIRC on)
No load, ADC off, WDT
enable
IIDLE0
IIDLE1
ISLEEP0
ISLEEP1
No load, ADC off, WDT
enable, fSYS=12MHz on
IDLE1 Mode Standby Current
(HXT, ERC, HIRC)
SLEEP0 Mode Standby Current
(LXT and LIRC off)
No load, ADC off, WDT
disable
2
¾
1.5
2.5
3.0
5.0
SLEEP1 Mode Standby Current
(LXT or LIRC on)
No load, ADC off, WDT
enable
Input Low Voltage for I/O Ports or
Input Pins except RES pin
VIL1
0.3VDD
VDD
0
V
V
¾
¾
¾
¾
¾
¾
Input High Voltage for I/O Ports
or Input Pins except RES pin
VIH1
0.7VDD
VIL2
VIH2
0.4VDD
VDD
Input Low Voltage (RES)
Input High Voltage (RES)
0
V
V
¾
¾
¾
¾
¾
¾
0.9VDD
Rev. 1.60
22
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Conditions
LVR Enable, 2.10V option
LVR Enable, 2.55V option
LVR Enable, 3.15V option
LVR Enable, 4.20V option
LVDEN=1, VLVD=2.0V
LVDEN=1, VLVD=2.2V
LVDEN=1, VLVD=2.4V
LVDEN=1, VLVD=2.7V
LVDEN=1, VLVD=3.0V
LVDEN=1, VLVD=3.3V
LVDEN=1, VLVD=3.6V
LVDEN=1, VLVD=4.4V
LVR Enable, LVDEN=0
LVR disable, LVDEN=1
LVR enable, LVDEN=1
2.10
2.55
3.15
4.20
2.00
2.20
2.40
2.70
3.00
3.30
3.60
4.40
60
+5%
+5%
+5%
+5%
+5%
+5%
+5%
+5%
+5%
+5%
+5%
+5%
90
V
V
-5%
-5%
-5%
-5%
-5%
-5%
-5%
-5%
-5%
-5%
-5%
-5%
¾
VLVR
LVR Voltage Level
¾
V
V
V
V
V
V
VLVD
LVD Voltage Level
¾
V
V
V
V
mA
mA
mA
V
Additional Power Consumption if
LVR and LVD is Used
ILV
75
115
135
0.3
¾
¾
90
¾
I
I
OL=9mA
3V
5V
3V
5V
3V
5V
¾
¾
VOL
VOH
RPH
Output Low Voltage I/O Port
Output High Voltage I/O Port
OL=20mA
0.5
V
¾
¾
2.7
V
IOH=-3.2mA
IOH=-7.4mA
¾
¾
4.5
V
¾
¾
20
60
100
50
kW
kW
mA
mA
mA
mA
VDD
Pull-high Resistance for I/O
Ports
¾
10
30
SCOMC, ISEL[1:0]=00
SCOMC, ISEL[1:0]=01
SCOMC, ISEL[1:0]=10
SCOMC, ISEL[1:0]=11
17.5
35
25.0
50
32.5
65
ISCOM
SCOM Operating Current
VDD/2 Voltage for LCD COM
5V
70
100
200
130
260
140
VSCOM
V125
5V No load
0.475 0.500 0.525
1.25V Reference with Buffer
Voltage
1.25
200
+3%
300
V
¾
¾
¾
-3%
Additional Power Consumption if
1.25V Reference with Buffer is
used
I125
¾
¾
mA
Rev. 1.60
23
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Conditions
2.2V~5.5V
DC
DC
8
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
¾
¾
¾
¾
¾
¾
4
fCPU
Operating Clock
2.7V~5.5V
4.5V~5.5V
2.2V~5.5V
2.7V~5.5V
4.5V~5.5V
Ta=25°C
12
¾
DC
20
0.4
8
fSYS
System Clock (HXT)
0.4
12
¾
0.4
20
3V/5V
3V/5V
5V
+2%
+2%
+2%
+5%
+4%
+3%
-2%
-2%
-2%
-5%
-4%
-5%
8
Ta=25°C
12
4
Ta=25°C
3V/5V
3V/5V
5V
Ta=0~70°C
Ta=0~70°C
Ta=0~70°C
8
12
2.2V~
3.6V
4
4
+7%
+9%
+4%
+9%
+7%
+8%
+9%
+4%
+9%
+7%
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Ta=0~70°C
-7%
-5%
3.0V~
5.5V
Ta=0~70°C
2.2V~
3.6V
8
Ta=0~70°C
-6%
System Clock
(HIRC)
fHIRC
3.0V~
5.5V
8
Ta=0~70°C
-4%
3.0V~
5.5V
12
4
Ta=0~70°C
-6%
2.2V~
3.6V
Ta= -40°C~85°C
Ta= -40°C~85°C
Ta= -40°C~85°C
Ta= -40°C~85°C
Ta= -40°C~85°C
-12%
-10%
-15%
-8%
3.0V~
5.5V
4
2.2V~
3.6V
8
3.0V~
5.5V
8
3.0V~
5.5V
12
-12%
5V
5V
8
8
+2%
+6%
MHz
MHz
Ta=25°C, R=120kW *
-2%
-5%
Ta=0~70°C, R=120kW *
Ta= -40°C~85°C,
R=120kW *
5V
8
8
+9%
MHz
MHz
-7%
-9%
fERC
System Clock (ERC)
3.0V~ Ta= -40°C~85°C,
+10%
5.5V
R=120kW *
2.2V~ Ta= -40°C~85°C,
8
+10%
MHz
kHz
-15%
5.5V
R=120kW *
fLXT
System Clock (LXT)
32.768
¾
¾
¾
¾
Rev. 1.60
24
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Conditions
Ta=25°C
5V
32
32
+10%
+60%
kHz
kHz
fSYS
-10%
-50%
fLIRC
System Clock (LIRC)
2.2V~
5.5V
Ta=-40°C~+85°C
fTIMER
tRES
Timer Input Pin Frequency
External Reset Low Pulse Width
Interrupt Pulse Width
1
¾
¾
480
90
¾
¾
90
4
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
1
¾
¾
ms
tINT
tSYS
1
¾
tLVR
Low Voltage Width to Reset
Low Voltage Width to Interrupt
LVDO stable time
120
20
15
200
¾
¾
¾
¾
¾
240
45
ms
ms
ms
ms
ms
ms
tLVD
tLVDS
tBGS
tEERD
tEEWR
¾
VBG Turn on Stable Time
EEPROM Read Time
¾
45
EEPROM Write Time
2
fSYS=HXT or LXT
1024
15~16
1~2
¾
¾
¾
System Start-up Timer Period
(Wake-up from HALT)
tSST
tSYS
fSYS=ERC or HIRC
fSYS=LIRC OSC
¾
Note: 1. tSYS=1/fSYS
2. * For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should be
connected between VDD and VSS and located as close to the device as possible.
A/D Converter Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
Conditions
AVDD
VADI
A/D Converter Operating Voltage
A/D Converter Input Voltage
A/D Converter Reference Voltage
Differential Non-linearity
2.7
0
5.5
V
V
¾
¾
¾
VREF
AVDD
¾
¾
¾
VREF
DNL
INL
2
V
¾
¾
5V
5V
3V
5V
¾
LSB
LSB
mA
mA
ms
tADCK= 1.0ms
¾
¾
¾
¾
0.5
±1
±2
±4
Integral Non-linearity
t
ADCK= 1.0ms
±2
0.90
1.20
¾
1.35
1.80
10
No load, tADCK= 0.5ms
No load, tADCK= 0.5ms
¾
Additional Power Consumption if
A/D Converter is Used
IADC
tADCK
tADC
A/D Converter Clock Period
A/D Conversion Time (Include
Sample and Hold Time)
tADCK
12-bit A/D Converter
16
¾
¾
¾
tADS
tADCK
A/D Converter Sampling Time
A/D Converter On-to-Start Time
4
¾
¾
¾
¾
¾
¾
¾
tON2ST
2
¾
ms
Rev. 1.60
25
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Comparator Electrical Characteristics
Ta=25°C
Test Conditions
Symbol
VCMP
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
Conditions
Comparator Operating Voltage
Comparator Operating Current
2.2
¾
5.5
56
V
¾
¾
¾
¾
¾
¾
37
3V
5V
¾
mA
mA
mV
mV
ICMP
130
¾
200
10
¾
VCMPOS
VHYS
Comparator Input Offset Voltage
Hysteresis Width
-10
20
40
60
¾
Comparator Common Mode
Voltage Range
VCM
AOL
tPD
VSS
60
¾
VDD-1.4V
¾
V
¾
¾
¾
¾
¾
¾
80
Comparator Open Loop Gain
Comparator Response Time
dB
ns
With 100mV
370
560
overdrive (Note)
Note:
Measured with comparator one input pin at VCM = (VDD-1.4)/2 while the other pin input transition from VSS to
(VCM +100mV) or from VDD to (VCM -100mV).
Power-on Reset Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
VDD Start Voltage to Ensure
Power-on Reset
VPOR
RRVDD
tPOR
100
¾
mV
V/ms
ms
¾
¾
¾
¾
¾
0.035
1
¾
¾
¾
VDD Raising Rate to Ensure
Power-on Reset
¾
¾
Minimum Time for VDD Stays at
¾
V
POR to Ensure Power-on Reset
V
D
D
t
P
O
R
R
V
R
D
D
V
P
O
R
T
i
m
Rev. 1.60
26
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to their in-
ternal system architecture. The range of devices take
advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all instruction set operations, which carries
out arithmetic operations, logic operations, rotation, in-
crement, decrement, branch decisions, etc. The internal
data path is simplified by moving data through the Accu-
mulator and the ALU. Certain internal registers are im-
plemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural fea-
tures ensure that a minimum of external components is
required to provide a functional I/O and A/D control sys-
tem with maximum reliability and flexibility. This makes
the device suitable for low-cost, high-volume production
for controller applications.
ternally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive in-
struction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to com-
plete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
Clocking and Pipelining
The main system clock, derived from either a HXT, LXT,
HIRC, LIRC or ERC oscillator is subdivided into four in-
f
S
Y
S
(
S
y
s
s
t
e
e
m
C
C
l
o
c
k
)
P
h
a
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c
k
T
1
P
P
P
h
h
h
a
a
a
s
s
s
e
e
e
C
C
C
l
l
l
o
o
o
c
c
c
k
k
k
T
T
T
2
3
4
P
r
o
g
r
a
m
C
o
u
n
t
e
r
P
C
P
C
+
1
P
C
+
2
F
e
t
c
h
I
n
s
t
.
(
P
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)
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t
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(
P
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t .
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e
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c
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s
(
P
C
+
1
)
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e
c
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t
.
(
P
C
)
n
F
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c
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I
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.
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P
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+
2
)
E
x
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c
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t
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(
P
C
+
1
System Clocking and Pipelining
F
e
t
c h
]
I
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s
t
.
1
E
x
e
c
u
t
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I
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1
2
3
4
5
6
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:
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[
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:
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Instruction Fetching
Rev. 1.60
27
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Program Counter
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the ac-
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. Only the
lower 8 bits, known as the Program Counter Low Regis-
ter, are directly addressable by the application program.
knowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine in-
struction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For condi-
tional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is dis-
carded and a dummy cycle takes its place while the cor-
rect instruction is obtained.
If the stack is overflow, the first Program Counter save in
the stack will be lost.
P
r
o
g
r
a
m
T
o
p
o
f
S
S
S
S
t
t
t
t
a
a
a
a
c
c
c
c
k
k
k
k
L
L
L
e
e
e
v
v
v
e
e
e
l
l
l
1
2
3
S
t
a
c
k
P
r
o
g
r
a
P
o
i
n
t
e
r
M
e
m
o
r
Program Counter
Device
Program Counter
High Byte
PCL Register
B
o
t
t
o
m
o
S
f
t
a
S
c
t
k
a
c
L
k
e
v
e
l
N
HT66F20
HT66F30
HT66F40
HT66F50
HT66F60
PC9, PC8
PC10~PC8
PC11~PC8
PC12~PC8
PC13~PC8
Device
Stack Levels
PCL7~PCL0
HT66F20/HT66F30
HT66F40/HT66F50
HT66F60
4
8
12
Program Counter
Arithmetic and Logic Unit - ALU
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writeable register.
By transferring data directly into this register, a short pro-
gram jump can be executed directly, however, as only
this low byte is available for manipulation, the jumps are
limited to the present page of memory, that is 256 loca-
tions. When such program jumps are executed it should
also be noted that a dummy cycle will be inserted. Manip-
ulating the PCL register may cause program branching,
so an extra cycle is needed to pre-fetch.
The arithmetic-logic unit or ALU is a critical area of the
microcontrollerthat carries out arithmetic and logic oper-
ations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related in-
struction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or oper-
ations may result in carry, borrow or other status
changes, the status register will be correspondingly up-
dated to reflect these changes. The ALU supports the
following functions:
Stack
·
·
·
Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has multiple levels depending upon the device
and is neither part of the data nor part of the program
space, and is neither readable nor writeable. The acti-
vated level is indexed by the Stack Pointer, and is nei-
ther readable nor writeable. At a subroutine call or
interrupt acknowledge signal, the contents of the Pro-
gram Counter are pushed onto the stack. At the end of a
subroutine or an interrupt routine, signaled by a return
instruction, RET or RETI, the Program Counter is re-
stored to its previous value from the stack. After a device
reset, the Stack Pointer will point to the top of the stack.
Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
·
·
Increment and Decrement INCA, INC, DECA, DEC
Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Rev. 1.60
28
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Flash Program Memory
The Program Memory is the location where the user
code or program is stored. For this device series the
Program Memory is Flash type, which means it can be
programmed and re-programmed a large number of
times, allowing the user the convenience of code modifi-
cation on the same device. By using the appropriate
programming tools, these Flash devices offer users the
flexibility to conveniently debug and develop their appli-
cations while also offering a means of field programming
and updating.
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the address of the look up data
to be retrieved in the table pointer register, TBLP and
TBHP. These registers define the total address of the
look-up table.
After setting up the table pointer, the table data can be
retrieved from the Program Memory using the
²TABRD[m]² or ²TABRDL[m]² instructions, respectively.
When the instruction is executed, the lower order table
byte from the Program Memory will be transferred to the
user defined Data Memory register [m] as specified in
the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
Structure
The Program Memory has a capacity of 1K´14 bits to
12K´16 bits. The Program Memory is addressed by the
Program Counter and also contains data, table informa-
tion and interrupt entries. Table data, which can be
setup in any location within the Program Memory, is ad-
dressed by a separate table pointer register.
Device
Capacity
1K´14
Banks
The accompanying diagram illustrates the addressing
data flow of the look-up table.
HT66F20
HT66F30
HT66F40
HT66F50
HT66F60
0
0
2K´14
P
r
o
g
r
a
m
M
e
m
L
a
s
t
p
a
g
e
o
r
0
4K´15
T
B
H
P
R
e
g
i
s
t
e
r
a
D
t
a
0
8K´16
1
4
~
r
1
6
b
i
t
s
T
B
L
P
R
e
g
i
s
t
e
0, 1
12K´16
The HT66F60 has its Program Memory divided into two
Banks, Bank 0 and Bank 1. The required Bank is se-
lected using Bit 5 of the BP Register.
U
s
e
r
S
e
R
e
g
i
s
t
e
r
T
B
L
H
R
e
g
i
s
t
H
i
g
h
B
y
t
L
e
o
w
B
y
Special Vectors
Table Program Example
Within the Program Memory, certain locations are re-
served for the reset and interrupts. The location 000H is
reserved for use by the device reset for program initialis-
ation. After a device reset is initiated, the program will
jump to this location and begin execution.
The following example shows how the table pointer and
table data is defined and retrieved from the
microcontroller. This example uses raw table data lo-
cated in the Program Memory which is stored there us-
H
T
6
6
F
H
2
T
0
6
6
F
H
3
T
0
6
6
F
H
4
T
0
6
6
F
5
0
H
T
6
6
F
6
0
0
0
0
0
0
0
0
4
R
H
H
e
s
e
t
R
e
s
e
t
R
e
s
e
t
R
e
s
e
t
R
e
s
e
t
I
n
t
e
r
r
I
u
n
p
t
e
t
r
r
I
u
n
p
t
e
t
r
r
I
u
n
p
t
e
t
r
r
u
p
t
I
n
t
e
r
r
u
p
t
V
e
c
t
o
V
r
e
c
t
o
V
r
e
c
t
o
V
r
e
c
t
o
r
V
e
c
t
o
r
0
0
2
C
H
0
0
3
C
H
1 4
H
b
i
t
s
0
3
F
F
B
a
n
k
0
1 4
H
b
i
t
s
0
7
F
F
1 5
H
b
i
t
s
0
F
F
F
1
6
b
i
t
s
1 6
H
b
i
t
s
1
F
F
F
H
1
F
F
F
2
0
0
0
H
B
a
n
k
1
2
F
F
F
H
Program Memory Structure
Rev. 1.60
29
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
ing the ORG statement. The value at this ORG
As an additional convenience, Holtek has provided a
means of programming the microcontroller in-circuit us-
ing a 5-pin interface. This provides manufacturers with
the possibility of manufacturing their circuit boards com-
plete with a programmed or un-programmed
microcontroller, and then programming or upgrading the
program at a later stage. This enables product manufac-
turers to easily keep their manufactured products sup-
plied with the latest program releases without removal
and re-insertion of the device.
statement is ²700H² which refers to the start address of
the last page within the 2K Program Memory of the
HT66F30. The table pointer is setup here to have an ini-
tial value of ²06H². This will ensure that the first data
read from the data table will be at the Program Memory
address ²706H² or 6 locations after the start of the last
page. Note that the value for the table pointer is refer-
enced to the first address of the present page if the
²TABRD [m]² instruction is being used. The high byte of
the table data which in this case is equal to zero will be
transferred to the TBLH register automatically when the
²TABRD [m]² instruction is executed.
MCU Programming
Function
Pins
PA0
PA2
RES
VDD
VSS
Serial Data Input/Output
Serial Clock
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause
errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the inter-
rupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
Device Reset
Power Supply
Ground
The Program Memory and EEPROM data memory can
both be programmed serially in-circuit using this 5-wire
interface. Data is downloaded and uploaded serially on
a single pin with an additional line for the clock. Two ad-
ditional lines are required for the power supply and one
line for the reset. The technical details regarding the
in-circuit programming of the devices are beyond the
scope of this document and will be supplied in supple-
mentary literature.
During the programming process the RES pin will be
held low by the programmer disabling the normal opera-
tion of the microcontroller and taking control of the PA0
and PA2 I/O pins for data and clock programming pur-
poses. The user must there take care to ensure that no
other outputs are connected to these two pins.
In Circuit Programming
The provision of Flash type Program Memory provides
the user with a means of convenient and easy upgrades
and modifications to their programs on the same device.
·
Table Read Program Example
tempreg1 db
tempreg2 db
?
?
; temporary register #1
; temporary register #2
:
:
mov a,06h
mov tblp,a
mov a,07h
tbhp,a
; initialise low table pointer - note that this address
; is referenced
; initialise high table pointer
:
:
tabrd tempreg1
; transfers value in table referenced by table pointer data at program
; memory address ²706H² transferred to tempreg1 and TBLH
dec tblp
; reduce value of table pointer by one
tabrd tempreg2
; transfers value in table referenced by table pointer data at program
; memory address ²705H² transferred to tempreg2 and TBLH in this
; example the data ²1AH² is transferred to tempreg1 and data ²0FH² to
; register tempreg2
:
:
org 700h
; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev. 1.60
30
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
W
r
i
t
e
r
C
o
n
n
e
M
c
C
t
U
o
r
P
r
o
g
Device
Capacity
Banks
S
i
g
n
a
l
s
P
i
n
s
0: 60H~7FH
1: 60H~7FH
W
r
i
t
e
r
_
V
D
D
V
D
D
HT66F20
64´8
0: 60H~7FH
1: 60H~7FH
2: 60H~7FH
R
E
S
R
E
S
HT66F30
HT66F40
HT66F50
96´8
192´8
384´8
D
A
T
A
D
A
T
A
0: 80H~FFH
1: 80H~BFH
C
L
K
C
L
K
0: 80H~FFH
1: 80H~FFH
2: 80H~FFH
W
r
i
t
e
r
_
V
S
S
V
S
S
0: 80H~
1: 80H~FFH
2: 80H~FFH
3: 80H~FFH
4: 80H~BFH
*
*
*
HT66F60
576´8
T
o
o
t
h
e
r
C
i
r
c
u
Note: * may be resistor or capacitor. The resistance
of * must be greater than 1kW or the capacitance
of * must be less than 1nF.
B
a
n
k
0
,
1
B
a
n
k
0
B
I
A
A
R
R
0
1
A
A
D
D
C
C
R
R
0
1
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
3
3
3
3
3
3
3
3
3
3
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
M
M
P
P
0
1
I
A
C
n
E
R
L
U
u
s
e
d
Programmer Pin
RES
Pins
PB0
PA0
PA2
B
P
C
P
0
C
A
C
C
C
P
1
C
P
C
L
S
I
M
C
0
1
T
B
L
P
S
I
M
C
DATA
T
B
L
O
H
S
I
M
D
T
L
B
H
P
S
I
M
A
/
S
I
0
0
A
B
H
H
H
H
H
H
S
T
A
T
U
S
3
3
A
B
T
T
T
M
M
M
0
0
0
C
C
D
0
1
L
S
M
D
Programmer and MCU Pins
0
0
C
D
V
D
C
3
3
C
D
I
N
T
E
G
T
M
0
D
H
0
E
W
D
T
C
3
E
T
M
0
A
L
RAM Data Memory
0
F
T
B
C
3
4
5
F
F
F
T
M
0
A
H
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
I
I
I
N
N
N
T
T
T
u
C
C
C
0
1
2
U
n
u
s
e
d
C
4
4
4
4
4
4
4
4
4
4
0
1
2
3
4
5
6
7
8
9
The Data Memory is a volatile area of 8-bit wide RAM in-
ternal memory and is the location where temporary in-
formation is stored.
E
E
A
E
E
D
U
n
s
e
d
T
M
P
C
0
M
M
M
F
F
F
I
I
I
0
1
2
U
U
U
U
n
n
n
n
u
u
u
u
s
s
s
s
e
e
e
e
d
d
d
d
Structure
Divided into two sections, the first of these is an area of
RAM, known as the Special Function Data Memory.
Here are located registers which are necessary for cor-
rect operation of the device. Many of these registers can
be read from and written to directly under program con-
trol, however, some remain protected from user manipu-
lation.
U
n
u
s
e
d
P
W
A
U
T
T
M
M
1
1
C
C
0
1
P
P
A
B
P
P
U
U
1
1
A
B
H
H
H
H
H
H
P
P
A
B
U
n
u
s
e
d
4
4
A
B
P
P
A
B
C
C
T
M
1
D
L
1
1
C
D
T
M
1
D
H
4
4
C
D
T
M
1
A
L
1
E
T
M
1
A
H
4
E
1
F
P
C
P
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
d
d
d
d
2
0
H
P
C
5
5
5
5
5
5
5
5
5
5
0
1
2
3
4
5
6
7
8
9
2
H
1
P
C
C
H
2
2
2
2
2
2
2
2
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
U
U
U
U
U
U
U
U
U
U
U
U
n
n
n
n
n
n
n
n
n
n
n
n
u
u
u
u
u
u
u
u
u
u
u
u
s
s
s
s
s
s
s
s
s
s
s
s
e
e
e
e
e
e
e
e
e
e
e
e
d
d
d
d
d
d
d
d
d
d
d
d
H
H
H
H
H
H
H
H
H
H
H
H
H
H
d
d
d
d
d
d
d
d
d
d
d
2
2
A
B
H
H
H
H
H
H
5
5
A
B
2
C
5
5
C
D
2
D
2
E
A
D
R
L
5
E
S
C
O
M
C
2
F
A
D
R
H
U
n
u
s
e
d
HT66F20 Special Purpose Data Memory
Rev. 1.60
31
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
B
a
n
k
0
,
1
,
B
2
a
n
k
0
,
2
B
a
n
k
0
,
1
B
a
n
k
B
a
0
n
k
I
A
R
0
A
A
D
D
C
C
R
R
0
1
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
3
3
3
3
3
3
3
3
3
3
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
I
I
A
A
R
R
0
1
U
n
u
s
e
d
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
4
4
4
4
4
4
4
4
4
4
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
M
P
0
M
M
P
P
0
1
E
E
A
I
A
R
1
A
C
n
E
R
L
E
E
D
M
P
1
U
u
s
e
d
T
T
M
M
P
P
C
0
1
B
P
C
P
0
C
B
P
C
A
C
C
C
P
1
C
A
C
C
P
P
P
R
R
R
M
M
M
0
1
2
P
C
L
S
I
M
C
0
1
P
C
L
T
B
L
P
S
I
M
C
T
B
L
P
T
B
L
H
S
I
M
D
T
B
L
H
T
T
T
T
M
M
M
M
1
1
1
1
C
C
C
D
0
1
2
L
T
L
B
H
P
S
I
M
A
/
S
I
T
B
H
P
S
T
U
A
S
T
0
0
A
B
H
H
H
H
H
H
S
T
A
T
U
S
3
3
A
B
T
T
T
M
M
M
0
0
0
C
C
D
0
1
L
0
0
A
B
H
H
H
H
H
H
4
4
A
B
S
M
O
D
S
W
M
O
D
C
L
V
D
C
T
M
1
D
H
0
0
C
D
V
D
C
3
3
C
D
0
0
C
D
4
4
C
D
I
N
T
E
G
T
T
M
M
1
1
A
B
L
L
I
N
T
E
G
T
M
0
D
H
M
A
0
E
D
T
4
E
T
T
M
M
1
1
A
B
H
H
0
E
W
D
T
C
3
E
T
0
L
0
1
2
3
F
F
F
F
T
B
C
0
F
T
B
C
3
4
5
F
F
F
T
M
0
A
H
4
5
6
7
F
F
F
F
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
I
I
I
N
N
N
T
T
T
u
C
C
C
0
1
2
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
I
I
I
N
N
N
T
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F
C
2
2
A
B
P
F
C
6
6
A
B
6
6
A
B
U
U
U
n
n
n
u
u
u
s
s
s
e
e
e
d
d
d
P
G
P
U
2
2
C
D
H
H
2
2
C
D
H
H
P
G
6
6
C
D
6
6
C
D
P
G
C
2
E
H
H
H
H
H
H
H
H
H
H
H
H
H
H
A
D
R
L
2
E
H
H
H
H
H
H
H
H
H
H
H
H
H
H
A
D
R
L
6
E
6
E
A
D
R
H
A
D
R
H
3
3
3
3
3
3
3
3
3
3
0
1
2
3
4
5
6
7
8
9
3
3
3
3
3
3
3
3
3
3
0
1
2
3
4
5
6
7
8
9
A
A
D
C
R
0
7
7
7
7
7
7
7
7
7
7
0
1
2
3
4
5
6
7
8
9
A
A
D
C
R
0
7
7
7
7
7
7
7
7
7
7
0
1
2
3
4
5
6
7
8
9
D
C
R
1
D
C
R
1
A
C
n
E
R
L
A
C
E
R
L
U
u
s
e
d
A
C
E
R
H
C
C
P
0
1
C
C
C
C
P
0
1
C
C
P
P
S
S
I
M
C
0
1
s
e
d
S
S
I
M
C
0
1
s
e
d
I
M
C
s
s
s
s
s
s
s
s
s
e
e
e
e
e
e
e
e
e
d
d
d
d
d
d
d
d
d
I
M
C
s
s
s
s
s
s
s
s
s
e
e
e
e
e
e
e
e
e
d
d
d
d
d
d
d
d
d
S
I
M
D
S
I
M
D
S
I
M
A
/
S
I
M
C
2
S
I
M
A
/
S
I
M
C
2
3
3
A
B
3
3
A
B
T
T
T
M
M
M
0
C
0
7
7
A
B
T
T
T
M
M
M
0
0
0
C
C
D
0
1
L
7
7
A
B
0
C
1
3
3
C
D
H
H
3
3
C
D
H
H
0
D
L
7
7
C
D
7
7
C
D
T
M
0
D
H
T
M
0
D
H
3
E
H
H
3
E
H
H
T
M
0
A
L
7
E
T
M
A
0
L
7
E
T
M
0
A
H
T
M
0
A
H
HT66F50 Special Purpose Data Memory
HT66F60 Special Purpose Data Memory
Rev. 1.60
33
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
The second area of Data Memory is known as the Gen-
pair, IAR0 and MP0 can together access data from Bank
0 while the IAR1 and MP1 register pair can access data
from any bank. As the Indirect Addressing Registers are
not physically implemented, reading the Indirect Ad-
dressing Registers indirectly will return a result of ²00H²
and writing to the registers indirectly will result in no op-
eration.
eral Purpose Data Memory, which is reserved for gen-
eral purpose use. All locations within this area are read
and write accessible under program control.
The overall Data Memory is subdivided into several
banks, the structure of which depends upon the device
chosen. The Special Purpose Data Memory registers
are accessible in all banks, with the exception of the
EEC register at address 40H, which is only accessible in
Bank 1. Switching between the different Data Memory
banks is achieved by setting the Bank Pointer to the cor-
rect value. The start address of the Data Memory for all
devices is the address 00H.
Memory Pointers - MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are pro-
vided. These Memory Pointers are physically imple-
mented in the Data Memory and can be manipulated in
the same way as normal registers providing a conve-
nient way with which to address and track data. When
any operation to the relevant Indirect Addressing Regis-
ters is carried out, the actual address that the
microcontroller is directed to, is the address specified by
the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data
from Bank 0, while MP1 and IAR1 are used to access
data from all banks according to BP register. Direct Ad-
dressing can only be used with Bank 0, all other Banks
must be addressed indirectly using MP1 and IAR1. Note
that for the HT66F20 and HT66F30 devices, bit 7 of the
Memory Pointers is not required to address the full
memory space. When bit 7 of the Memory Pointers for
HT66F20 and HT66F30 devices is read, a value of ²1²
will be returned.
Special Function Register Description
Most of the Special Function Register details will be de-
scribed in the relevant functional section, however sev-
eral registers require a separate description in this
section.
Indirect Addressing Registers - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, al-
though having their locations in normal RAM register
space, do not actually physically exist as normal regis-
ters. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory ad-
dressing, where the actual memory address is speci-
fied. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corre-
sponding Memory Pointers, MP0 or MP1. Acting as a
The following example shows how to clear a section of
four Data Memory locations already defined as loca-
tions adres1 to adres4.
·
Indirect Addressing Program Example
data .section ¢data¢
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ¢code¢
org 00h
start:
mov a,04h
; setup size of block
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
mov block,a
mov a,offset adres1
mov mp0,a
loop:
clr IAR0
inc mp0
sdz block
jmp loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Rev. 1.60
34
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Bank Pointer - BP
unaffected. It should be noted that the Special Function
Data Memory is not affected by the bank selection,
Depending upon which device is used, the Program and
Data Memory are divided into several banks. Selecting
the required Program and Data Memory area is
achieved using the Bank Pointer. Bit 5 of the Bank
Pointer is used to select Program Memory Bank 0 or 1,
while bits 0~2 are used to select Data Memory Banks
0~4.
which means that the Special Function Registers can be
accessed from within any bank. Directly addressing the
Data Memory will always result in Bank 0 being ac-
cessed irrespective of the value of the Bank Pointer. Ac-
cessing data from banks other than Bank 0 must be
implemented using Indirect addressing.
As both the Program Memory and Data Memory share
the same Bank Pointer Register, care must be taken
during programming.
The Data Memory is initialised to Bank 0 after a reset,
except for a WDT time-out reset in the Power Down
Mode, in which case, the Data Memory bank remains
Bit
Device
7
6
5
4
3
2
1
0
HT66F20
HT66F40
DMBP0
¾
¾
¾
¾
¾
¾
¾
HT66F30
HT66F50
DMBP1
DMBP1
DMBP0
DMBP0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
HT66F60
PMBP0
DMBP2
BP Registers List
·
BP Register
¨
HT66F20/HT66F40
Bit
Name
R/W
7
6
5
4
3
2
1
0
DMBP0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7 ~ 1
Bit 0
Unimplemented, read as ²0²
DMBP0: Select Data Memory Banks
0: Bank 0
1: Bank 1
¨
HT66F30/HT66F50
Bit
Name
R/W
7
6
5
4
3
2
1
DMBP1
R/W
0
0
DMBP0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7 ~ 2
Bit 1 ~ 0
Unimplemented, read as ²0²
DMBP1, DMBP0: Select Data Memory Banks
00: Bank 0
01: Bank 1
10: Bank 2
11: Undefined
Rev. 1.60
35
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F60
Bit
Name
R/W
7
6
5
PMBP0
R/W
0
4
3
2
DMBP2
R/W
0
1
DMBP1
R/W
0
0
DMBP0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7 ~ 6
Bit 5
Unimplemented, read as ²0²
PMBP0: Select Program Memory Banks
0: Bank 0, Program Memory Address is from 0000H ~ 1FFFH
1: Bank 1, Program Memory Address is from 2000H ~ 2FFFH
Bit 4 ~ 3
Bit 2 ~ 0
Unimplemented, read as ²0²
DMBP2 ~ DMBP0: Select Data Memory Banks
000: Bank 0
001: Bank 1
010: Bank 2
011: Bank 3
100: Bank 4
101~111: Undefined
Accumulator - ACC
for example using the ²INC² or ²DEC² instructions, al-
lowing for easy table data pointing and reading. TBLH is
the location where the high order byte of the table data is
stored after a table read data instruction has been exe-
cuted. Note that the lower order table data byte is trans-
ferred to a user defined location.
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system manage-
ment flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, opera-
tions related to the status register may give different re-
sults due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² in-
struction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Program Counter Low Register - PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to pro-
grammers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily imple-
mented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory lo-
cation, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are per-
mitted. When such operations are used, note that a
dummy cycle will be inserted.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
·
C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place dur-
ing a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
Look-up Table Registers - TBLP, TBHP, TBLH
These three special function registers are used to con-
trol operation of the look-up table which is stored in the
Program Memory. TBLP and TBHP are the table pointer
and indicates the location where the table data is lo-
cated. Their value must be setup before any table read
commands are executed. Their value can be changed,
·
AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nib-
ble into the low nibble in subtraction; otherwise AC is
cleared.
Rev. 1.60
36
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
·
Z is set if the result of an arithmetic or logical operation
In addition, on entering an interrupt sequence or execut-
ing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
·
·
PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
·
STATUS Register
Bit
Name
R/W
7
6
5
TO
R
4
PDF
R
3
OV
R/W
x
2
Z
1
AC
R/W
x
0
C
¾
¾
¾
¾
¾
¾
R/W
x
R/W
x
POR
0
0
²x² unknown
Bit 7, 6
Unimplemented, read as ²0²
TO: Watchdog Time-Out flag
Bit 5
Bit 4
Bit 3
0: After power up or executing the ²CLR WDT² or ²HALT² instruction
1: A watchdog time-out occurred.
PDF: Power down flag
0: After power up or executing the ²CLR WDT² instruction
1: By executing the ²HALT² instruction
OV: Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2
Bit 1
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
AC: Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow from the
high nibble into the low nibble in subtraction
Bit 0
C: Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does not take place
during a subtraction operation
C is also affected by a rotate through carry instruction.
Rev. 1.60
37
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
EEPROM Data Memory
The device contains an area of internal EEPROM Data
Memory. EEPROM, which stands for Electrically Eras-
able Programmable Read Only Memory, is by its nature
a non-volatile form of re-programmable memory, with
data retention even when its power supply is removed.
By incorporating this kind of data memory, a whole new
host of application possibilities are made available to the
designer. The availability of EEPROM storage allows in-
formation such as product identification numbers, cali-
bration values, specific user data, system setup data or
other product information to be stored directly within the
product microcontroller. The process of reading and
writing data to the EEPROM memory has been reduced
to a very trivial affair.
Device
HT66F20
Capacity
32´8
Address
00H ~ 1FH
00H ~ 3FH
00H ~ 7FH
00H ~ FFH
HT66F30
64´8
HT66F40
128´8
256´8
HT66F50/HT66F60
EEPROM Registers
Three registers control the overall operation of the inter-
nal EEPROM Data Memory. These are the address reg-
ister, EEA, the data register, EED and a single control
register, EEC. As both the EEA and EED registers are lo-
cated in Bank 0, they can be directly accessed in the
same was as any other Special Function Register. The
EEC register however, being located in Bank1, cannot be
directly addressed directly and can only be read from or
written to indirectly using the MP1 Memory Pointer and
Indirect Addressing Register, IAR1. Because the EEC
control register is located at address 40H in Bank 1, the
MP1 Memory Pointer must first be set to the value 40H
and the Bank Pointer register, BP, set to the value, 01H,
before any operations on the EEC register are executed.
EEPROM Data Memory Structure
The EEPROM Data Memory capacity varies from 32x8
to 256´8 bits, according to the device selected. Unlike
the Program Memory and RAM Data Memory, the
EEPROM Data Memory is not directly mapped into
memory space and is therefore not directly addressable
in the same way as the other types of memory. Read
and Write operations to the EEPROM are carried out in
single byte operations using an address and data regis-
ter in Bank 0 and a single control register in Bank 1.
·
EEPROM Register List
¨
¨
¨
HT66F20
Bit
Name
7
6
5
4
3
D3
2
1
D1
0
EEA
EED
EEC
D4
D4
¾
D2
D2
WR
D0
D0
RD
¾
D7
¾
¾
D6
¾
¾
D5
¾
D3
D1
WREN
RDEN
HT66F30
Bit
Name
7
6
5
4
3
D3
2
1
D1
0
EEA
EED
EEC
D5
D5
¾
D4
D4
¾
D2
D2
WR
D0
D0
RD
¾
D7
¾
¾
D6
¾
D3
D1
WREN
RDEN
HT66F40
Bit
Name
7
6
5
4
3
D3
2
1
D1
0
EEA
EED
EEC
D6
D6
¾
D5
D5
¾
D4
D4
¾
D2
D2
WR
D0
D0
RD
¾
D7
¾
D3
D1
WREN
RDEN
Rev. 1.60
38
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F50/HT66F60
Bit
Name
7
6
5
4
3
D3
2
1
D1
0
EEA
EED
EEC
D7
D7
¾
D6
D6
¾
D5
D5
¾
D4
D4
¾
D2
D2
WR
D0
D0
RD
D3
D1
WREN
RDEN
·
EEA Register
¨
HT66F20
Bit
Name
R/W
7
6
5
4
D4
R/W
x
3
D3
R/W
x
2
D2
R/W
x
1
D1
R/W
x
0
D0
R/W
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
x
²x² unknown
Bit 7 ~ 5
Bit 4 ~ 0
Unimplemented, read as ²0²
Data EEPROM address
Data EEPROM address bit 4 ~ bit 0
¨
HT66F30
Bit
Name
R/W
7
6
5
D5
R/W
x
4
D4
R/W
x
3
D3
R/W
x
2
D2
R/W
x
1
D1
R/W
x
0
D0
R/W
¾
¾
¾
¾
¾
¾
POR
x
²x² unknown
Bit 7 ~ 6
Bit 5 ~ 0
Unimplemented, read as ²0²
Data EEPROM address
Data EEPROM address bit 5 ~ bit 0
¨
HT66F40
Bit
Name
R/W
7
6
D6
R/W
x
5
D5
R/W
x
4
D4
R/W
x
3
D3
R/W
x
2
D2
R/W
x
1
D1
R/W
x
0
D0
R/W
¾
¾
¾
POR
x
²x² unknown
Bit 7
Unimplemented, read as ²0²
Bit 6 ~ 0
Data EEPROM address
Data EEPROM address bit 6 ~ bit 0
¨
HT66F50/HT66F60
Bit
Name
R/W
7
D7
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
D4
R/W
x
3
D3
R/W
x
2
D2
R/W
x
1
D1
R/W
x
0
D0
R/W
POR
x
²x² unknown
Bit 7 ~ 0
Data EEPROM address
Data EEPROM address bit 7 ~ bit 0
Rev. 1.60
39
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
EEC Register
Bit
Name
R/W
7
6
5
4
3
WREN
R/W
0
2
WR
R/W
0
1
RDEN
R/W
0
0
RD
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7 ~ 4
Bit 3
Unimplemented, read as ²0²
WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write
operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations.
Bit 2
WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application program will
activate a write cycle. This bit will be automatically reset to zero by the hardware after the write
cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high.
Bit 1
Bit 0
RDEN: Data EEPROM Read Enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read
operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations.
RD: EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application program will
activate a read cycle. This bit will be automatically reset to zero by the hardware after the read
cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high.
Note:
The WREN, WR, RDEN and RD can not be set to ²1² at the same time in one instruction. The WR and RD can
not be set to ²1² at the same time.
Reading Data from the EEPROM
ter and the data placed in the EED register. If the WR bit
in the EEC register is now set high, an internal write cy-
cle will then be initiated. Setting the WR bit high will not
initiate a write cycle if the WREN bit has not been set. As
the EEPROM write cycle is controlled using an internal
timer whose operation is asynchronous to
microcontroller system clock, a certain time will elapse
before the data will have been written into the EEPROM.
Detecting when the write cycle has finished can be im-
plemented either by polling the WR bit in the EEC regis-
ter or by using the EEPROM interrupt. When the write
cycle terminates, the WR bit will be automatically
cleared to zero by the microcontroller, informing the
user that the data has been written to the EEPROM. The
application program can therefore poll the WR bit to de-
termine when the write cycle has ended.
To read data from the EEPROM, the read enable bit,
RDEN, in the EEC register must first be set high to en-
able the read function. The EEPROM address of the
data to be read must then be placed in the EEA register.
If the RD bit in the EEC register is now set high, a read
cycle will be initiated. Setting the RD bit high will not initi-
ate a read operation if the RDEN bit has not been set.
When the read cycle terminates, the RD bit will be auto-
matically cleared to zero, after which the data can be
read from the EED register. The data will remain in the
EED register until another read or write operation is exe-
cuted. The application program can poll the RD bit to de-
termine when the data is valid for reading.
Writing Data to the EEPROM
To write data to the EEPROM, the write enable bit,
WREN, in the EEC register must first be set high to en-
able the write function. The EEPROM address of the
data to be written must then be placed in the EEA regis-
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Write Protection
DEF request flag and its associated multi-function inter-
rupt request flag will both be set. If the global, EEPROM
Protection against inadvertent write operation is pro-
vided in several ways. After the device is powered-on
the Write Enable bit in the control register will be cleared
preventing any write operations. Also at power-on the
Bank Pointer, BP, will be reset to zero, which means that
Data Memory Bank 0 will be selected. As the EEPROM
control register is located in Bank 1, this adds a further
measure of protection against spurious write opera-
tions. During normal program operation, ensuring that
the Write Enable bit in the control register is cleared will
safeguard against incorrect write operations.
and Multi-function interrupts are enabled and the stack
is not full, a jump to the associated Multi-function Inter-
rupt vector will take place. When the interrupt is serviced
only the Multi-function interrupt flag will be automatically
reset, the EEPROM interrupt flag must be manually re-
set by the application program. More details can be ob-
tained in the Interrupt section.
Programming Considerations
Care must be taken that data is not inadvertently written
to the EEPROM. Protection can be enhanced by ensur-
ing that the Write Enable bit is normally cleared to zero
when not writing. Also the Bank Pointer could be nor-
mally cleared to zero as this would inhibit access to
Bank 1 where the EEPROM control register exist. Al-
though certainly not necessary, consideration might be
given in the application program to the checking of the
validity of new write data by a simple read back process.
EEPROM Interrupt
The EEPROM write or read interrupt is generated when
an EEPROM write or read cycle has ended. The
EEPROM interrupt must first be enabled by setting the
DEE bit in the relevant interrupt register. However as the
EEPROM is contained within a Multi-function Interrupt,
the associated multi-function interrupt enable bit must
also be set. When an EEPROM write cycle ends, the
·
Programming Examples
¨
Reading data from the EEPROM - polling method
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, 040H
MOV MP1, A
MOV A, 01H
MOV BP, A
; user defined address
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
SET IAR1.1
SET IAR1.0
BACK:
; set RDEN bit, enable read operations
; start Read Cycle - set RD bit
SZ
JMP BACK
CLR IAR1
CLR BP
MOV A, EEDATA
MOV READ_DATA, A
IAR1.0
; check for read cycle end
; disable EEPROM read/write
; move read data to register
¨
Writing Data to the EEPROM - polling method
MOV A, EEPROM_ADRES
MOV EEA, A
; user defined address
MOV A, EEPROM_DATA
MOV EED, A
; user defined data
MOV A, 040H
MOV MP1, A
MOV A, 01H
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
MOV BP, A
SET IAR1.3
SET IAR1.2
BACK:
; set WREN bit, enable write operations
; start Write Cycle - set WR bit
SZ
IAR1.2
; check for write cycle end
; disable EEPROM read/write
JMP BACK
CLR IAR1
CLR BP
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Oscillator
Various oscillator options offer the user a wide range of
functions according to their various application require-
ments. The flexible features of the oscillator functions
ensure that the best optimisation can be achieved in
terms of speed and power saving. Oscillator selections
and operation are selected through a combination of
configuration options and registers.
Type
Name
HXT
Freq.
Pins
400kHz~
20MHz
OSC1/
OSC2
External Crystal
External RC
ERC
8MHz
OSC1
Internal High
Speed RC
HIRC 4, 8 or 12MHz
¾
Oscillator Overview
External Low
Speed Crystal
XT1/
XT2
LXT
32.768kHz
32kHz
In addition to being the source of the main system clock
the oscillators also provide clock sources for the Watch-
dog Timer and Time Base Interrupts. External oscilla-
tors requiring some external components as well as fully
integrated internal oscillators, requiring no external
components, are provided to form a wide range of both
fast and slow system oscillators. All oscillator options
are selected through the configuration options. The
higher frequency oscillators provide higher performance
but carry with it the disadvantage of higher power re-
quirements, while the opposite is of course true for the
lower frequency oscillators. With the capability of dy-
namically switching between fast and slow system
clock, the device has the flexibility to optimize the perfor-
mance/power ratio, a feature especially important in
power sensitive portable applications.
Internal Low
Speed RC
LIRC
¾
Oscillator Types
System Clock Configurations
There are five methods of generating the system clock,
three high speed oscillators and two low speed oscilla-
tors. The high speed oscillators are the external crystal/
ceramic oscillator, external RC network oscillator and
the internal 4MHz, 8MHz or 12MHz RC oscillator. The
two low speed oscillators are the internal 32kHz RC os-
cillator and the external 32.768kHz crystal oscillator. Se-
lecting whether the low or high speed oscillator is used
as the system oscillator is implemented using the
HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register
and as the system clock can be dynamically selected.
High Speed Oscillation
HXT
fH
ERC
6-stage Prescaler
fH/2
fH/4
HIRC
fH/8
fH/16
fH/32
fH/64
High Speed Oscillation
Configuration Option
Low Speed Oscillation
LIRC
fSYS
fL
LXT
HLCLK,
CKS2~CKS0 bits
Low Speed Oscillation
Configuration Option
fSUB
Fast Wake-up from SLEEP Mode or
IDLE Mode Control (for HXT only)
System Clock Configurations
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The actual source clock used for each of the high speed
termines the oscillation frequency; the external
capacitor has no influence over the frequency and is
connected for stability purposes only. Device trimming
during the manufacturing process and the inclusion of
internal frequency compensation circuits are used to en-
sure that the influence of the power supply voltage, tem-
perature and process variations on the oscillation
frequency are minimised. As a resistance/frequency ref-
erence point, it can be noted that with an external 120kW
resistor connected and with a 5V voltage power supply
and temperature of 25°C degrees, the oscillator will
have a frequency of 8MHz within a tolerance of 2%.
Here only the OSC1 pin is used, which is shared with I/O
pin PB1, leaving pin PB2 free for use as a normal I/O
pin.
and low speed oscillators is chosen via configuration
options. The frequency of the slow speed or high speed
system clock is also determined using the HLCLK bit
and CKS2 ~ CKS0 bits in the SMOD register. Note that
two oscillator selections must be made namely one high
speed and one low speed system oscillators. It is not
possible to choose a no-oscillator selection for either the
high or low speed oscillator.
External Crystal/ Ceramic Oscillator - HXT
The External Crystal/ Ceramic System Oscillator is one
of the high frequency oscillator choices, which is se-
lected via configuration option. For most crystal oscilla-
tor configurations, the simple connection of a crystal
across OSC1 and OSC2 will create the necessary
phase shift and feedback for oscillation, without requir-
ing external capacitors. However, for some crystal types
and frequencies, to ensure oscillation, it may be neces-
sary to add two small value capacitors, C1 and C2.
Using a ceramic resonator will usually require two small
value capacitors, C1 and C2, to be connected as shown
for oscillation to occur. The values of C1 and C2 should
be selected in consultation with the crystal or resonator
manufacturer¢s specification.
Internal RC Oscillator - HIRC
The internal RC oscillator is a fully integrated system os-
cillator requiring no external components. The internal
RC oscillator has three fixed frequencies of either
4MHz, 8MHz or 12MHz. Device trimming during the
manufacturing process and the inclusion of internal fre-
quency compensation circuits are used to ensure that
the influence of the power supply voltage, temperature
and process variations on the oscillation frequency are
minimised. As a result, at a power supply of either 3V or
I
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External RC Oscillator - ERC
2
.
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5V and at a temperature of 25°C degrees, the fixed os-
cillation frequency of 4MHz, 8MHz or 12MHz will have a
tolerance within 2%. Note that if this internal system
clock option is selected, as it requires no external pins
for its operation, I/O pins PB1 and PB2 are free for use
as normal I/O pins.
Crystal/Resonator Oscillator - HXT
Crystal Oscillator C1 and C2 Values
Crystal Frequency
12MHz
C1
0pF
C2
0pF
0pF
0pF
8MHz
0pF
External 32.768kHz Crystal Oscillator - LXT
4MHz
0pF
The External 32.768kHz Crystal System Oscillator is
one of the low frequency oscillator choices, which is se-
lected via configuration option. This clock source has a
fixed frequency of 32.768kHz and requires a 32.768kHz
crystal to be connected between pins XT1 and XT2. The
external resistor and capacitor components connected
to the 32.768kHz crystal are necessary to provide oscil-
lation. For applications where precise frequencies are
essential, these components may be required to provide
frequency compensation due to different crystal manu-
facturing tolerances. During power-up there is a time
delay associated with the LXT oscillator waiting for it to
start-up.
1MHz
100pF
100pF
Note: C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
External RC Oscillator - ERC
Using the ERC oscillator only requires that a resistor,
with a value between 56kW and 2.4MW, is connected
between OSC1 and VDD, and a capacitor is connected
between OSC1 and ground, providing a low cost oscilla-
tor configuration. It is only the external resistor that de-
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LXT Oscillator Low Power Function
When the microcontroller enters the SLEEP or IDLE
Mode, the system clock is switched off to stop
microcontroller activity and to conserve power. How-
ever, in many microcontroller applications it may be nec-
essary to keep the internal timers operational even
when the microcontroller is in the SLEEP or IDLE Mode.
To do this, another clock, independent of the system
clock, must be provided.
The LXT oscillator can function in one of two modes, the
Quick Start Mode and the Low Power Mode. The mode
selection is executed using the LXTLP bit in the TBC
register.
LXTLP Bit
LXT Mode
Quick Start
Low-power
0
1
However, for some crystals, to ensure oscillation and
accurate frequency generation, it is necessary to add
two small value external capacitors, C1 and C2. The ex-
act values of C1 and C2 should be selected in consulta-
tion with the crystal or resonator manufacturer¢s
specification. The external parallel feedback resistor,
Rp, is required.
After power on the LXTLP bit will be automatically
cleared to zero ensuring that the LXT oscillator is in the
Quick Start operating mode. In the Quick Start Mode the
LXT oscillator will power up and stabilise quickly. How-
ever, after the LXT oscillator has fully powered up it can
be placed into the Low-power mode by setting the
LXTLP bit high. The oscillator will continue to run but
with reduced current consumption, as the higher current
consumption is only required during the LXT oscillator
start-up. In power sensitive applications, such as battery
applications, where power consumption must be kept to
a minimum, it is therefore recommended that the appli-
cation program sets the LXTLP bit high about 2 seconds
after power-on.
Some configuration options determine if the XT1/XT2
pins are used for the LXT oscillator or as I/O pins.
·
If the LXT oscillator is not used for any clock source,
the XT1/XT2 pins can be used as normal I/O pins.
·
If the LXT oscillator is used for any clock source, the
32.768kHz crystal should be connected to the
XT1/XT2 pins.
I
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C
1
X
T
1
It should be noted that, no matter what condition the
LXTLP bit is set to, the LXT oscillator will always func-
tion normally, the only difference is that it will take more
time to start up if in the Low-power mode.
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Internal 32kHz Oscillator - LIRC
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2
The Internal 32kHz System Oscillator is one of the low
frequency oscillator choices, which is selected via con-
figuration option. It is a fully integrated RC oscillator with
a typical frequency of 32kHz at 5V, requiring no external
components for its implementation. Device trimming
during the manufacturing process and the inclusion of
internal frequency compensation circuits are used to en-
sure that the influence of the power supply voltage, tem-
perature and process variations on the oscillation
frequency are minimised. As a result, at a power supply
of 5V and at a temperature of 25°C degrees, the fixed
oscillation frequency of 32kHz will have a tolerance
within 10%.
N
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:
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External LXT Oscillator
LXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
10pF
32.768kHz
10pF
Note: 1. C1 and C2 values are for guidance only.
2. RP=5M~10MW is recommended.
32.768kHz Crystal Recommended Capacitor Values
Supplementary Oscillators
The low speed oscillators, in addition to providing a sys-
tem clock source are also used to provide a clock
source to two other device functions. These are the
Watchdog Timer and the Time Base Interrupts.
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Operating Modes and System Clocks
Present day applications require that their
microcontrollers have high performance but often still
demand that they consume as little power as possible,
conflicting requirements that are especially true in bat-
tery powered portable applications. The fast clocks re-
quired for high performance will by their nature increase
current consumption and of course vice-versa, lower
speed clocks reduce current consumption. As Holtek
has provided these devices with both high and low
speed clock sources and the means to switch between
them dynamically, the user can optimise the operation of
their microcontroller to achieve the best perfor-
mance/power ratio.
The main system clock, can come from either a high fre-
quency, fH, or low frequency, fL, source, and is selected
using the HLCLK bit and CKS2~CKS0 bits in the SMOD
register. The high speed system clock can be sourced
from either an HXT, ERC or HIRC oscillator, selected via
a configuration option. The low speed system clock
source can be sourced from internal clock fL. If fL is se-
lected then it can be sourced by either the LXT or LIRC
oscillators, selected via a configuration option. The
other choice, which is a divided version of the high
speed system oscillator has a range of fH/2~fH/64.
There are two additional internal clocks for the periph-
eral circuits, the substitute clock, fSUB, and the Time
Base clock, fTBC. Each of these internal clocks are
sourced by either the LXT or LIRC oscillators, selected
via configuration options. The fSUB clock is used to pro-
vide a substitute clock for the microcontroller just after a
wake-up has occurred to enable faster wake-up times.
System Clocks
The device has many different clock sources for both
the CPU and peripheral function operation. By providing
the user with a wide range of clock options using config-
uration options and register programming, a clock sys-
tem can be configured to obtain maximum application
performance.
High Speed Oscillation
HXT
fH
ERC
6-stage Prescaler
fH/2
HIRC
fH/4
fH/8
fH/16
fH/32
fH/64
High Speed Oscillation
Configuration Option
Low Speed Oscillation
LIRC
fSYS
fL
LXT
HLCLK,
CKS2~CKS0 bits
Low Speed Oscillation
Configuration Option
fSUB
Fast Wake-up from SLEEP Mode or
IDLE Mode Control (for HXT only)
fTB C
fTB
Time Base
fSYS/4
TBCK
fSUB
fS
WDT
fSYS/4
Configuration Option
System Clock Configurations
Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the
power. Thus there is no fH~fH/64 for peripheral circuit to use.
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Together with fSYS/4 it is also used as one of the clock
istics and which can be chosen according to the specific
performance and power requirements of the applica-
tion. There are two modes allowing normal operation of
the microcontroller, the NORMAL Mode and SLOW
Mode. The remaining four modes, the SLEEP0,
SLEEP1, IDLE0 and IDLE1 Mode are used when the
microcontroller CPU is switched off to conserve power.
sources for the Watchdog timer. The fTBC clock is used
as a source for the Time Base interrupt functions and for
the TMs.
System Operation Modes
There are six different modes of operation for the
microcontroller, each one with its own special character-
Description
Operation Mode
CPU
On
On
Off
Off
Off
Off
fSYS
fH~ fH/64
fL
fSUB
On
On
On
On
Off
On
fS
On
fTBC
On
On
On
On
Off
Off
NORMAL Mode
SLOW Mode
IDLE0 Mode
On
Off
On/Off
On
IDLE1 Mode
On
SLEEP0 Mode
SLEEP1 Mode
Off
Off
Off
On
·
NORMAL Mode
to operate if the LVDEN is ²1² or the Watchdog Timer
function is enabled and if its clock source is chosen
As the name suggests this is one of the main operat-
ing modes where the microcontroller has all of its
functions operational and where the system clock is
provided by one of the high speed oscillators. This
mode operates allowing the microcontroller to operate
normally with a clock source will come from one of the
high speed oscillators, either the HXT, ERC or HIRC
oscillators. The high speed oscillator will however first
be divided by a ratio ranging from 1 to 64, the actual
ratio being selected by the CKS2~CKS0 and HLCLK
bits in the SMOD register. Although a high speed os-
cillator is used, running the microcontroller at a di-
vided clock ratio reduces the operating current.
via configuration option to come from the fSUB
.
·
IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction
is executed and when the IDLEN bit in the SMOD reg-
ister is high and the FSYSON bit in the WDTC register
is low. In the IDLE0 Mode the system oscillator will be
inhibited from driving the CPU but some peripheral
functions will remain operational such as the Watch-
dog Timer, TMs and SIM. In the IDLE0 Mode, the sys-
tem oscillator will be stopped. In the IDLE0 Mode the
Watchdog Timer clock, fS, will either be on or off de-
pending upon the fS clock source. If the source is
·
SLOW Mode
fSYS/4 then the fS clock will be off, and if the source co-
This is also a mode where the microcontroller oper-
ates normally although now with a slower speed clock
source. The clock source used will be from one of the
low speed oscillators, either the LXT or the LIRC.
Running the microcontroller in this mode allows it to
run with much lower operating currents. In the SLOW
Mode, the fH is off.
mes from fSUB then fS will be on.
·
IDLE1 Mode
The IDLE1 Mode is entered when an HALT instruction
is executed and when the IDLEN bit in the SMOD reg-
ister is high and the FSYSON bit in the WDTC register
is high. In the IDLE1 Mode the system oscillator will be
inhibited from driving the CPU but may continue to
provide a clock source to keep some peripheral func-
tions operational such as the Watchdog Timer, TMs
and SIM. In the IDLE1 Mode, the system oscillator will
continue to run, and this system oscillator may be high
speed or low speed system oscillator. In the IDLE1
Mode the Watchdog Timer clock, fS, will be on. If the
source is fSYS/4 then the fS clock will be on, and if the
source comes from fSUB then fS will be on.
·
SLEEP0 Mode
The SLEEP Mode is entered when an HALT instruc-
tion is executed and when the IDLEN bit in the SMOD
register is low. In the SLEEP0 mode the CPU will be
stopped, and the fSUB and fS clocks will be stopped too,
and the Watchdog Timer function is disabled. In this
mode, the LVDEN is must set to ²0². If the LVDEN is
set to ²1², it won¢t enter the SLEEP0 Mode.
·
SLEEP1 Mode
The SLEEP Mode is entered when an HALT instruc-
tion is executed and when the IDLEN bit in the SMOD
register is low. In the SLEEP1 mode the CPU will be
stopped. However the fSUB and fS clocks will continue
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Control Register
A single register, SMOD, is used for overall control of the internal clocks within the device.
·
SMOD Register
Bit
7
6
CKS1
R/W
0
5
CKS0
R/W
0
4
FSTEN
R/W
0
3
LTO
R
2
HTO
R
1
IDLEN
R/W
1
0
HLCLK
R/W
1
Name
R/W
CKS2
R/W
0
POR
0
0
Bit 7~5
CKS2~CKS0: The system clock selection when HLCLK is ²0²
000: fL (fLXT or fLIRC
001: fL (fLXT or fLIRC
010: fH/64
)
)
011: fH/32
100: fH/16
101: fH/8
110: fH/4
111: fH/2
These three bits are used to select which clock is used as the system clock source. In addition
to the system clock source, which can be either the LXT or LIRC, a divided version of the high
speed system oscillator can also be chosen as the system clock source.
Bit 4
FSTEN: Fast Wake-up Control (only for HXT)
0: Disable
1: Enable
This is the Fast Wake-up Control bit which determines if the fSUB clock source is initially used
after the device wakes up. When the bit is high, the fSUB clock source can be used as a
temporary system clock to provide a faster wake up time as the fSUB clock is available.
Bit 3
LTO: Low speed system oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed system
oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in
the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after
1024 clock cycles if the LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used.
Bit 2
HTO: High speed system oscillator ready flag
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high speed system
oscillator is stable. This flag is cleared to ²0² by hardware when the device is powered on and
then changes to a high level after the high speed system oscillator is stable. Therefore this flag
will always be read as ²1² by the application program after device power-on. The flag will be
low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to
a high level after 1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if
the ERC or HIRC oscillator is used.
Bit 1
IDLEN: IDLE Mode control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT instruction is
executed. If this bit is high, when a HALT instruction is executed the device will enter the
IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to
keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU
and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the
SLEEP Mode when a HALT instruction is executed.
Bit 0
HLCLK: system clock selection
0: fH/2 ~ fH/64 or fL
1: fH
This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the system
clock. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fL clock will
be selected. When system clock switches from the fH clock to the fL clock and the fH clock will
be automatically switched off to conserve power.
Rev. 1.60
47
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Fast Wake-up
able function is controlled using the FSTEN bit in the
SMOD register.
To minimise power consumption the device can enter
the SLEEP or IDLE0 Mode, where the system clock
source to the device will be stopped. However when the
device is woken up again, it can take a considerable
time for the original system oscillator to restart, stabilise
and allow normal operation to resume. To ensure the
device is up and running as fast as possible a Fast
If the HXT oscillator is selected as the NORMAL Mode
system clock, and if the Fast Wake-up function is en-
abled, then it will take one to two tSUB clock cycles of the
LIRC or LXT oscillator for the system to wake-up. The
system will then initially run under the fSUB clock source
until 1024 HXT clock cycles have elapsed, at which
point the HTO flag will switch high and the system will
switch over to operating from the HXT oscillator.
Wake-up function is provided, which allows fSUB
,
namely either the LXT or LIRC oscillator, to act as a tem-
porary clock to first drive the system until the original
system oscillator has stabilised. As the clock source for
the Fast Wake-up function is fSUB, the Fast Wake-up
function is only available in the SLEEP1 and IDLE0
modes. When the device is woken up from the SLEEP0
mode, the Fast Wake-up function has no effect because
the fSUB clock is stopped. The Fast Wake-up enable/dis-
If the ERC or HIRC oscillators or LIRC oscillator is used
as the system oscillator then it will take 15~16 clock cy-
cles of the ERC or HIRC or 1~2 cycles of the LIRC to
wake up the system from the SLEEP or IDLE0 Mode.
The Fast Wake-up bit, FSTEN will have no effect in
these cases.
System
FSTEN
Bit
Wake-up Time
(SLEEP0 Mode)
Wake-up Time
(SLEEP1 Mode)
Wake-up Time
(IDLE0 Mode)
Wake-up Time
(IDLE1 Mode)
Oscillator
0
1024 HXT cycles
1024 HXT cycles
1~2 HXT cycles
1~2 fSUB cycles
HXT
1
1024 HXT cycles
(System runs with fSUB first for 1024 HXT cycles
and then switches over to run with the HXT clock)
1~2 HXT cycles
ERC
HIRC
LIRC
LXT
X
X
X
X
15~16 ERC cycles
15~16 HIRC cycles
1~2 LIRC cycles
1024 LTX cycles
15~16 ERC cycles
15~16 HIRC cycles
1~2 LIRC cycles
1024 LXT cycles
1~2 ERC cycles
1~2 HIRC cycles
1~2 LIRC cycles
1~2 LXT cycles
Wake-Up Times
Note that if the Watchdog Timer is disabled, which means that the LXT and LIRC are all both off, then there will be no
Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode.
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Rev. 1.60
48
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Operating Mode Switching and Wake-up
sources will also stop running, which may affect the op-
eration of other internal functions such as the TMs and
The device can switch between operating modes dy-
namically allowing the user to select the best perfor-
mance/power ratio for the present task in hand. In this
way microcontroller operations that do not require high
performance can be executed using slower clocks thus
requiring less operating current and prolonging battery
life in portable applications.
the SIM. The accompanying flowchart shows what hap-
pens when the device moves between the various oper-
ating modes.
NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the
high speed system oscillator, and therefore consumes
more power, the system clock can switch to run in the
SLOW Mode by set the HLCLK bit to ²0² and set the
CKS2~CKS0 bits to ²000² or ²001² in the SMOD regis-
ter. This will then use the low speed system oscillator
which will consume less power. Users may decide to do
this for certain operations which do not require high per-
formance and can subsequently reduce power con-
sumption.
In simple terms, Mode Switching between the NORMAL
Mode and SLOW Mode is executed using the HLCLK bit
and CKS2~CKS0 bits in the SMOD register while Mode
Switching from the NORMAL/SLOW Modes to the
SLEEP/IDLE Modes is executed via the HALT instruc-
tion. When a HALT instruction is executed, whether the
device enters the IDLE Mode or the SLEEP Mode is de-
termined by the condition of the IDLEN bit in the SMOD
register and FSYSON in the WDTC register.
The SLOW Mode is sourced from the LXT or the LIRC
oscillators and therefore requires these oscillators to be
stable before full mode switching occurs. This is moni-
tored using the LTO bit in the SMOD register.
When the HLCLK bit switches to a low level, which im-
plies that clock source is switched from the high speed
clock source, fH, to the clock source, fH/2~fH/64 or fL. If
the clock is from the fL, the high speed clock source will
stop running to conserve power. When this happens it
must be noted that the fH/16 and fH/64 internal clock
N
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Rev. 1.60
49
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
S
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SLOW Mode to NORMAL Mode Switching
Entering the SLEEP0 Mode
In SLOW Mode the system uses either the LXT or LIRC
low speed system oscillator. To switch back to the
NORMAL Mode, where the high speed system oscillator
is used, the HLCLK bit should be set to ²1² or HLCLK bit
is ²0², but CKS2~CKS0 is set to ²010², ²011², ²100²,
²101², ²110² or ²111². As a certain amount of time will be
required for the high frequency clock to stabilise, the
status of the HTO bit is checked. The amount of time
required for high speed system oscillator stabilization
depends upon which high speed system oscillator type
is used.
There is only one way for the device to enter the
SLEEP0 Mode and that is to execute the ²HALT² instruc-
tion in the application program with the IDLEN bit in
SMOD register equal to ²0² and the WDT and LVD both
off. When this instruction is executed under the condi-
tions described above, the following will occur:
·
The system clock, WDT clock and Time Base clock
will be stopped and the application program will stop
at the ²HALT² instruction.
·
·
The Data Memory contents and registers will maintain
their present condition.
The WDT will be cleared and stopped no matter if the
WDT clock source originates from the fSUB clock or
from the system clock.
·
·
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Rev. 1.60
50
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Entering the SLEEP1 Mode
Entering the IDLE1 Mode
There is only one way for the device to enter the
SLEEP1 Mode and that is to execute the ²HALT²
instruction in the application program with the IDLEN bit
in SMOD register equal to ²0² and the WDT or LVD on.
When this instruction is executed under the conditions
described above, the following will occur:
There is only one way for the device to enter the IDLE1
Mode and that is to execute the ²HALT² instruction in the
application program with the IDLEN bit in SMOD register
equal to ²1² and the FSYSON bit in WDTC register equal
to ²1². When this instruction is executed under the with
conditions described above, the following will occur:
·
The system clock and Time Base clock will be
stopped and the application program will stop at the
²HALT² instruction, but the WDT or LVD will remain
with the clock source coming from the fSUB clock.
·
The system clock and Time Base clock and fSUB clock
will be on and the application program will stop at the
²HALT² instruction.
·
·
The Data Memory contents and registers will maintain
their present condition.
·
·
The Data Memory contents and registers will maintain
their present condition.
The WDT will be cleared and resume counting if the
WDT is enabled regardless of the WDT clock source
which originates from the fSUB clock or from the system
clock.
The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the fSUB
clock as the WDT is enabled.
·
·
The I/O ports will maintain their present conditions.
·
·
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Standby Current Considerations
Entering the IDLE0 Mode
As the main reason for entering the SLEEP or IDLE
Mode is to keep the current consumption of the device
to as low a value as possible, perhaps only in the order
of several micro-amps except in the IDLE1 Mode, there
are other considerations which must also be taken into
account by the circuit designer if the power consumption
is to be minimised. Special attention must be made to
the I/O pins on the device. All high-impedance input pins
must be connected to either a fixed high or low level as
any floating input pins could create internal oscillations
and result in increased current consumption. This also
applies to devices which have different package types,
as there may be unbonbed pins. These must either be
setup as outputs or if setup as inputs must have
pull-high resistors connected.
There is only one way for the device to enter the IDLE0
Mode and that is to execute the ²HALT² instruction in the
application program with the IDLEN bit in SMOD register
equal to ²1² and the FSYSON bit in WDTC register equal
to ²0². When this instruction is executed under the condi-
tions described above, the following will occur:
·
The system clock will be stopped and the application
program will stop at the ²HALT² instruction, but the
Time Base clock and fSUB clock will be on.
·
·
The Data Memory contents and registers will maintain
their present condition.
The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the fSUB
clock and the WDT is enabled. The WDT will stop if its
clock source originates from the system clock.
Care must also be taken with the loads, which are con-
nected to I/O pins, which are setup as outputs. These
should be placed in a condition in which minimum cur-
rent is drawn or connected only to external circuits that
do not draw current, such as other CMOS inputs. Also
note that additional standby current will also be required
if the configuration options have enabled the LXT or
LIRC oscillator.
·
·
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
In the IDLE1 Mode the system oscillator is on, if the sys-
tem oscillator is from the high speed system oscillator,
the additional standby current will also be perhaps in the
order of several hundred micro-amps
Rev. 1.60
51
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Wake-up
Programming Considerations
After the system enters the SLEEP or IDLE Mode, it can
be woken up from one of various sources listed as fol-
lows:
The HXT and LXT oscillators both use the same SST
counter. For example, if the system is woken up from the
SLEEP0 Mode and both the HXT and LXT oscillators
need to start-up from an off state. The LXT oscillator
uses the SST counter after HXT oscillator has finished
its SST period.
·
·
·
·
An external reset
An external falling edge on Port A
A system interrupt
·
If the device is woken up from the SLEEP0 Mode to
the NORMAL Mode, the high speed system oscillator
needs an SST period. The device will execute first in-
struction after HTO is ²1². At this time, the LXT oscilla-
tor may not be stability if fSUB is from LXT oscillator. The
same situation occurs in the power-on state. The LXT
oscillator is not ready yet when the first instruction is
executed.
A WDT overflow
If the system is woken up by an external reset, the de-
vice will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the ac-
tual source of the wake-up can be determined by exam-
ining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in their
original status.
·
·
·
If the device is woken up from the SLEEP1 Mode to
NORMAL Mode, and the system clock source is from
HXT oscillator and FSTEN is ²1², the system clock can
be switched to the LXT or LIRC oscillator after wake
up.
There are peripheral functions, such as WDT, TMs
and SIM, for which the fSYS is used. If the system clock
source is switched from fH to fL, the clock source to the
peripheral functions mentioned above will change ac-
cordingly.
Each pin on Port A can be setup using the PAWU regis-
ter to permit a negative transition on the pin to wake-up
the system. When a Port A pin wake-up occurs, the pro-
gram will resume execution at the instruction following
the ²HALT² instruction. If the system is woken up by an
interrupt, then two possible situations may occur. The first
is where the related interrupt is disabled or the interrupt is
enabled but the stack is full, in which case the program
will resume execution at the instruction following the
²HALT² instruction. In this situation, the interrupt which
woke-up the device will not be immediately serviced, but
will rather be serviced later when the related interrupt is fi-
nally enabled or when a stack level becomes free. The
other situation is where the related interrupt is enabled
and the stack is not full, in which case the regular inter-
rupt response takes place. If an interrupt request flag is
set high before entering the SLEEP or IDLE Mode, the
wake-up function of the related interrupt will be disabled.
The on/off condition of fSUB and fS depends upon
whether the WDT is enabled or disabled as the WDT
clock source is selected from fSUB
.
Rev. 1.60
52
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown lo-
cations, due to certain uncontrollable external events
such as electrical noise.
However, it should be noted that this specified internal
clock period can vary with VDD, temperature and pro-
cess variations. The LXT oscillator is supplied by an ex-
ternal 32.768kHz crystal. The other Watchdog Timer
clock source option is the fSYS/4 clock. The Watchdog
Timer clock source can originate from its own internal
LIRC oscillator, the LXT oscillator or fSYS/4. It is divided
by a value of 28 to 215, using the WS2~WS0 bits in the
WDTC register to obtain the required Watchdog Timer
time-out period.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the in-
ternal clock, fS, which is in turn supplied by one of two
sources selected by configuration option: fSUB or fSYS/4.
The fSUB clock can be sourced from either the LXT or
LIRC oscillators, again chosen via a configuration op-
tion. The Watchdog Timer source clock is then subdi-
vided by a ratio of 28 to 215 to give longer timeouts, the
actual value being chosen using the WS2~WS0 bits in
the WDTC register. The LIRC internal oscillator has an
approximate period of 32kHz at a supply voltage of 5V.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout
period as well as the enable/disable operation. This reg-
ister together with several configuration options control
the overall operation of the Watchdog Timer.
·
WDTC Register
Bit
7
6
5
4
3
2
1
0
Name
R/W
FSYSON
WS2
R/W
1
WS1
R/W
1
WS0
R/W
1
WDTEN3 WDTEN2 WDTEN1 WDTEN0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
POR
Bit 7
FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable
Bit 6 ~ 4
WS2, WS1, WS0 : WDT time-out period selection
000: 256/fS
001: 512/fS
010: 1024/fS
011: 2048/fS
100: 4096/fS
101: 8192/fS
110: 16384/fS
111: 32768/fS
These three bits determine the division ratio of the Watchdog Timer source clock, which in turn
determines the timeout period.
Bit 3 ~ 0
WDTEN3, WDTEN2, WDTEN1, WDTEN0 : WDT Software Control
1010: Disable
Other: Enable
Rev. 1.60
53
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Watchdog Timer Operation
bit TO. However, if the system is in the SLEEP or IDLE
Mode, when a Watchdog Timer time-out occurs, the TO
The Watchdog Timer operates by providing a device re-
set when its timer overflows. This means that in the ap-
plication program and during normal operation the user
has to strategically clear the Watchdog Timer before it
overflows to prevent the Watchdog Timer from execut-
ing a reset. This is done using the clear watchdog in-
structions. If the program malfunctions for whatever
reason, jumps to an unkown location, or enters an end-
less loop, these clear instructions will not be executed in
the correct manner, in which case the Watchdog Timer
will overflow and reset the device. Some of the Watch-
dog Timer options, such as enable/disable, clock source
selection and clear instruction type are selected using
configuration options. In addition to a configuration op-
tion to enable/disable the Watchdog Timer, there are
also four bits, WDTEN3~WDTEN0, in the WDTC regis-
ter to offer an additional enable/disable control of the
Watchdog Timer. To disable the Watchdog Timer, as
well as the configuration option being set to disable, the
WDTEN3~WDTEN0 bits must also be set to a specific
value of ²1010². Any other values for these bits will keep
the Watchdog Timer enabled, irrespective of the configu-
ration enable/disable setting. After power on these bits
will have the value of 1010. If the Watchdog Timer is used
it is recommended that they are set to a value of 0101 for
maximum noise immunity. Note that if the Watchdog
Timer has been disabled, then any instruction relating to
its operation will result in no operation.
bit in the status register will be set and only the Program
Counter and Stack Pointer will be reset. Three methods
can be adopted to clear the contents of the Watchdog
Timer. The first is an external hardware reset, which
means a low level on the RES pin, the second is using
the Watchdog Timer software clear instructions and the
third is via a HALT instruction.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the sin-
gle ²CLR WDT² instruction while the second is to use
the two commands ²CLR WDT1² and ²CLR WDT2². For
the first option, a simple execution of ²CLR WDT² will
clear the WDT while for the second option, both ²CLR
WDT1² and ²CLR WDT2² must both be executed alter-
nately to successfully clear the Watchdog Timer. Note
that for this second option, if ²CLR WDT1² is used to
clear the Watchdog Timer, successive executions of this
instruction will have no effect, only the execution of a
²CLR WDT2² instruction will clear the Watchdog Timer.
Similarly after the ²CLR WDT2² instruction has been ex-
ecuted, only a successive ²CLR WDT1² instruction can
clear the Watchdog Timer.
The maximum time out period is when the 215 division ra-
tio is selected. As an example, with a 32.768kHz LXT
oscillator as its source clock, this will give a maximum
watchdog period of around 1 second for the 215 division
ratio, and a minimum timeout of 7.8ms for the 28 division
ration. If the fSYS/4 clock is used as the Watchdog Timer
clock source, it should be noted that when the system
enters the SLEEP or IDLE0 Mode, then the instruction
clock is stopped and the Watchdog Timer may lose its
protecting purposes. For systems that operate in noisy
environments, using the fSUB clock source is strongly
recommended.
WDT Configuration
Option
WDTEN3~
WDT
WDTEN0 Bits
WDT Enable
WDT Disable
WDT Disable
xxxx
Except 1010
1010
Enable
Enable
Disable
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer
time-out will initialise a device reset and set the status
C
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Watchdog Timer
Rev. 1.60
54
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Reset and Initialisation
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, af-
ter a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program com-
mences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
·
RES Pin
As the reset pin is shared with PB.0, the reset function
must be selected using a configuration option. Al-
though the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recom-
mended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is force-
fully pulled low. In such a case, known as a normal oper-
ation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high.
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected be-
tween VSS and the RES pin will provide a suitable ex-
ternal reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
For applications that operate within an environment
where more noise is present the Enhanced Reset Cir-
cuit shown is recommended.
Another type of reset is when the Watchdog Timer over-
flows and resets the microcontroller. All types of reset
operations result in different register conditions being
setup. Another reset exists in the form of a Low Voltage
Reset, LVR, where a full reset, similar to the RES reset
is implemented in situations where the power supply
voltage falls below a certain threshold.
V
D
D
0
.
m
0
F
1
*
*
V
D
D
1
N
4
1
4
8
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1
W
0 ~ k
1
0
W
0
k
P
B
0
/
R
E
3
W
0 * 0
Reset Functions
0
.
1
m
F
~
1
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and ex-
ternally:
V
S
S
Note:
²*² It is recommended that this component is
added for added ESD protection
·
Power-on Reset
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory ad-
dress, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
²**² It is recommended that this component is
added in environments where power line noise
is significant
External RES Circuit
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
V
D
D
0
.
D
9
D
V
R
E
S
t
t
R
R
S
S
T
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t
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S
D
D
S
S
I
n
t
e
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n
a
l
R
e
s
e
t
Note: tRSTD is power-on delay, typical time=100ms
Power-On Reset Timing Chart
Rev. 1.60
55
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Pulling the RES Pin low using external hardware will
Program Counter and the Stack Pointer will be
cleared to ²0² and the TO flag will be set to ²1². Refer
to the A.C. Characteristics for tSST details.
also execute a device reset. In this case, as in the
case of other resets, the Program Counter will reset to
zero and program execution initiated from this point.
Note: The tSST is 15~16 clock cycles if the system
clock source is provided by ERC or HIRC. The
tSST is 1024 clock for HXT or LXT. The tSST is
1~2 clock for LIRC.
0
.
D
9
D
V
0
.
D
4
D
V
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S
t
R
S
T
t
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S
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t
Reset Initial Conditions
Note: tRSTD is power-on delay, typical time=100ms
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
SLEEP or IDLE Mode function or Watchdog Timer. The
reset flags are shown in the table:
RES Reset Timing Chart
·
Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit
in order to monitor the supply voltage of the device,
which is selected via a configuration option. If the supply
voltage of the device drops to within a range of
0.9V~VLVR such as might occur when changing the bat-
tery, the LVR will automatically reset the device inter-
nally. The LVR includes the following specifications: For
a valid LVR signal, a low voltage, i.e., a voltage in the
range between 0.9V~VLVR must exist for greater than
the value tLVR specified in the A.C. characteristics. If the
low voltage state does not exceed tLVR, the LVR will ig-
nore it and will not perform a reset function. One of a
range of specified voltage values for VLVR can be se-
lected using configuration options.
TO PDF
RESET Conditions
Power-on reset
0
u
0
u
RES or LVR reset during NORMAL or
SLOW Mode operation
WDT time-out reset during NORMAL or
SLOW Mode operation
1
1
u
1
WDT time-out reset during IDLE or SLEEP
Mode operation
Note: ²u² stands for unchanged
L
V
R
t
R
S
T
t
S
D
S
+
T
The following table indicates the way in which the vari-
ous components of the microcontroller are affected after
a power-on reset occurs.
I
n
t
e
r
n
a
l
R
e
s
e
t
Note: tRSTD is power-on delay, typical time=100ms
Low Voltage Reset Timing Chart
Item
Condition After RESET
Program Counter Reset to zero
·
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal opera-
tion is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
Interrupts
WDT
All interrupts will be disabled
Clear after reset, WDT begins
counting
W
D
T
T
i
m
e
-
o
u
t
Timer/Event
Counter
Timer Counter will be turned off
t
R
S
T
t
S
D
S
+
T
I/O ports will be setup as inputs,
I
n
t
e
r
n
a
l
R
e
s
e
t
Input/Output Ports and AN0~AN11 in as A/D input
pin.
Note: tRSTD is power-on delay, typical time=100ms
WDT Time-out Reset during Normal Operation
Timing Chart
Stack Pointer will point to the top
Stack Pointer
of the stack
·
Watchdog Time-out Reset during SLEEP or IDLE
Mode
The Watchdog time-out Reset during SLEEP or IDLE
Mode is a little different from other kinds of reset. Most
of the conditions remain unchanged except that the
W
D
T
T
i
m
e
-
o
u
t
t
S
S
T
I
n
t
e
r
n
a
l
R
e
s
e
t
WDT Time-out Reset during SLEEP or IDLE
Timing Chart
Rev. 1.60
56
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation
for the larger package type.
·
HT66F20 Register
Register
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
(Power-on)
(Normal Operation)
MP0
- x x x x x x x
- x x x x x x x
- - - - - - - 0
x x x x x x x x
0 0 0 0 0 0 0 0
x x x x x x x x
- - x x x x x x
- - - - - - x x
- - 0 0 x x x x
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
- - - - 0 0 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- x x x x x x x
- x x x x x x x
- - - - - - - 0
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
- - u u u u u u
- - - - - - u u
- - u u u u u u
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
- - - - 0 0 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- x x x x x x x
- x x x x x x x
- - - - - - - 0
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
- - u u u u u u
- - - - - - u u
- - 1 u u u u u
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
- - - - 0 0 0 0
- - - - 1 1 1 1
- - - - 1 1 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- u u u u u u u
- u u u u u u u
- - - - - - - u
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
- - u u u u u u
- - - - - - u u
- - 1 1 u u u u
u u u u u u u u
- - u u - u u u
- - - - u u u u
u u u u u u u u
u u u u u u u u
- u u u u u u u
u u u u u u u u
u u u u u u u u
- - u u - - u u
- - u u - - u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - u u u u u u
- - u u u u u u
- - u u u u u u
- - - - u u u u
- - - - u u u u
- - - - u u u u
u u u u - - - -
u u u u u u u u
u u u u u u u u
MP1
BP
ACC
PCL
TBLP
TBLH
TBHP
STATUS
SMOD
LVDC
INTEG
WDTC
TBC
INTC0
INTC1
INTC2
MFI0
MFI1
MFI2
PAWU
PAPU
PA
PAC
PBPU
PB
PBC
PCPU
PC
PCC
ADRL (ADREF=0)
ADRL (ADREF=1)
ADRH(ADREF=0)
Rev. 1.60
57
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
Register
(Power-on)
(Normal Operation)
ADRH (ADREF=1)
ADCR0
ADCR1
ACERL
CP0C
- - - - x x x x
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- - - x x x x x
x x x x x x x x
- - - - 0 0 0 0
- - 0 1 - - - 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - x x x x
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- - - x x x x x
x x x x x x x x
- - - - 0 0 0 0
- - 0 1 - - - 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - x x x x
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- - - x x x x x
x x x x x x x x
- - - - 0 0 0 0
- - 0 1 - - - 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - u u u u
u u u - u u u u
u u - u - u u u
u u u u u u u u
u u u u u - - u
u u u u u - - u
u u u u u u u -
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
- - - 0 0 0 0 0
u u u u u u u u
- - - - u u u u
- - u u - - - u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
CP1C
SIMC0
SIMC1
SIMD
SIMA/SIMC2
TM0C0
TM0C1
TM0DL
TM0DH
TM0AL
TM0AH
EEA
EED
EEC
TMPC0
TM1C0
TM1C1
TM1DL
TM1DH
TM1AL
TM1AH
SCOMC
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.60
58
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
HT66F30 Register
Register
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
(Power-on)
(Normal Operation)
MP0
- x x x x x x x
- x x x x x x x
- - - - - - 0 0
x x x x x x x x
0 0 0 0 0 0 0 0
x x x x x x x x
- - x x x x x x
- - - - - x x x
- - 0 0 x x x x
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
- x x x x x x x
- x x x x x x x
- - - - - - 0 0
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
- - u u u u u u
- - - - - u u u
- - u u u u u u
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
- x x x x x x x
- x x x x x x x
- - - - - - 0 0
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
- - u u u u u u
- - - - - u u u
- - 1 u u u u u
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - 0 0 0 0 0 0
- - 1 1 1 1 1 1
- - 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
- u u u u u u u
- u u u u u u u
- - - - - - u u
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
- - u u u u u u
- - - - - u u u
- - 1 1 u u u u
u u u u u u u u
- - u u - u u u
- - - - u u u u
u u u u u u u u
u u u u u u u u
- u u u u u u u
u u u u u u u u
u u u u u u u u
- - u u - - u u
- u u u - u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - u u u u u u
- - u u u u u u
- - u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u - - - -
u u u u u u u u
u u u u u u u u
- - - - u u u u
u u u u - u u u
u u - u - u u u
u u u u u u u u
u u u u u - - u
MP1
BP
ACC
PCL
TBLP
TBLH
TBHP
STATUS
SMOD
LVDC
INTEG
WDTC
TBC
INTC0
INTC1
INTC2
MFI0
MFI1
MFI2
PAWU
PAPU
PA
PAC
PBPU
PB
PBC
PCPU
PC
PCC
ADRL (ADREF=0)
ADRL (ADREF=1)
ADRH(ADREF=0)
ADRH (ADREF=1)
ADCR0
ADCR1
ACERL
CP0C
Rev. 1.60
59
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
Register
CP1C
(Power-on)
(Normal Operation)
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- - x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 - 0 1 - - 0 1
- - - - - 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- - x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 - 0 1 - - 0 1
- - - - - 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- - x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 - 0 1 - - 0 1
- - - - - 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
u u u u u - - u
u u u u u u u -
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
- - u u u u u u
u u u u u u u u
- - - - u u u u
u - u u - - u u
- - - - - u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
SIMC0
SIMC1
SIMD
SIMA/SIMC2
TM0C0
TM0C1
TM0DL
TM0DH
TM0AL
TM0AH
EEA
EED
EEC
TMPC0
PRM0
TM1C0
TM1C1
TM1C2
TM1DL
TM1DH
TM1AL
TM1AH
TM1BL
TM1BH
SCOMC
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.60
60
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
HT66F40 Register
Register
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
(Power-on)
(Normal Operation)
MP0
x x x x x x x x
x x x x x x x x
- - - - - - - 0
x x x x x x x x
0 0 0 0 0 0 0 0
x x x x x x x x
- x x x x x x x
- - - - x x x x
- - 0 0 x x x x
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - - - - - 0 0
- - - - - - 1 1
- - - - - - 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
x x x x x x x x
x x x x x x x x
- - - - - - - 0
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
- u u u u u u u
- - - - u u u u
- - u u u u u u
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - - - - - 0 0
- - - - - - 1 1
- - - - - - 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
x x x x x x x x
x x x x x x x x
- - - - - - - 0
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
- u u u u u u u
- - - - u u u u
- - 1 u u u u u
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - - - - - 0 0
- - - - - - 1 1
- - - - - - 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
u u u u u u u u
u u u u u u u u
- - - - - - - u
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
- u u u u u u u
- - - - u u u u
- - 1 1 u u u u
u u u u u u u u
- - u u - u u u
- - - - u u u u
u u u u u u u u
u u u u u u u u
- u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- u u u - u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
- - - - - - u u
- - - - - - u u
u u u u - - - -
u u u u u u u u
u u u u u u u u
- - - - u u u u
MP1
BP
ACC
PCL
TBLP
TBLH
TBHP
STATUS
SMOD
LVDC
INTEG
WDTC
TBC
INTC0
INTC1
INTC2
MFI0
MFI1
MFI2
PAWU
PAPU
PA
PAC
PBPU
PB
PBC
PCPU
PC
PCC
PDPU
PD
PDC
PEPU
PE
PEC
PFPU
PF
PFC
ADRL (ADREF=0)
ADRL (ADREF=1)
ADRH(ADREF=0)
ADRH (ADREF=1)
Rev. 1.60
61
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
Register
ADCR0
(Power-on)
(Normal Operation)
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- x x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 0 0 1 - - 0 1
- - - - - - 0 1
- 0 - 0 0 0 0 0
0 0 0 - 0 0 0 0
- - 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- x x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 0 0 1 - - 0 1
- - - - - - 0 1
- 0 - 0 0 0 0 0
0 0 0 - 0 0 0 0
- - 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- x x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 0 0 1 - - 0 1
- - - - - - 0 1
- 0 - 0 0 0 0 0
0 0 0 - 0 0 0 0
- - 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u - u u u
u u - u - u u u
u u u u u u u u
u u u u u - - u
u u u u u - - u
u u u u u u u -
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
- u u u u u u u
u u u u u u u u
- - - - u u u u
u u u u - - u u
- - - - - - u u
- u - u u u u u
u u u - u u u u
- - u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
u u u u u - - -
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
ADCR1
ACERL
CP0C
CP1C
SIMC0
SIMC1
SIMD
SIMA/SIMC2
TM0C0
TM0C1
TM0DL
TM0DH
TM0AL
TM0AH
EEA
EED
EEC
TMPC0
TMPC1
PRM0
PRM1
PRM2
TM1C0
TM1C1
TM1C2
TM1DL
TM1DH
TM1AL
TM1AH
TM1BL
TM1BH
TM2C0
TM2C1
TM2DL
TM2DH
TM2AL
TM2AH
TM2RP
SCOMC
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.60
62
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
HT66F50 Register
Register
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
(Power-on)
(Normal Operation)
MP0
x x x x x x x x
x x x x x x x x
- - - - - - 0 0
x x x x x x x x
0 0 0 0 0 0 0 0
x x x x x x x x
x x x x x x x x
- - - x x x x x
- - 0 0 x x x x
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - - - - - 0 0
x x x x x x x x
x x x x x x x x
- - - - - - 0 0
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
- - - u u u u u
- - u u u u u u
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - - - - - 0 0
x x x x x x x x
x x x x x x x x
- - - - - - 0 0
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
- - - u u u u u
- - 1 u u u u u
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
- - - - 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - - - - - 0 0
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
- - - u u u u u
- - 1 1 u u u u
u u u u u u u u
- - u u - u u u
- - - - u u u u
u u u u u u u u
u u u u u u u u
- u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- u u u - u u u
u u u u u u u u
- - u u - - u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
MP1
BP
ACC
PCL
TBLP
TBLH
TBHP
STATUS
SMOD
LVDC
INTEG
WDTC
TBC
INTC0
INTC1
INTC2
MFI0
MFI1
MFI2
MFI3
PAWU
PAPU
PA
PAC
PBPU
PB
PBC
PCPU
PC
PCC
PDPU
PD
PDC
PEPU
PE
PEC
PFPU
Rev. 1.60
63
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
Register
(Power-on)
(Normal Operation)
PF
- - - - - - 1 1
- - - - - - 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
x x x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 0 0 1 - - 0 1
- - 0 1 - - 0 1
- 0 - 0 0 0 0 0
0 0 0 - 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- - - - - - 1 1
- - - - - - 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
x x x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 0 0 1 - - 0 1
- - 0 1 - - 0 1
- 0 - 0 0 0 0 0
0 0 0 - 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- - - - - - 1 1
- - - - - - 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
0 1 1 0 - 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
x x x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 0 0 1 - - 0 1
- - 0 1 - - 0 1
- 0 - 0 0 0 0 0
0 0 0 - 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
- - - - - - u u
- - - - - - u u
u u u u - - - -
u u u u u u u u
u u u u u u u u
- - - - u u u u
u u u u - u u u
u u - u - u u u
u u u u u u u u
u u u u u - - u
u u u u u - - u
u u u u u u u -
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
u u u u u u u u
- - - - u u u u
u u u u - - u u
- - u u - - u u
- u - u u u u u
u u u - u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
PFC
ADRL (ADREF=0)
ADRL (ADREF=1)
ADRH(ADREF=0)
ADRH (ADREF=1)
ADCR0
ADCR1
ACERL
CP0C
CP1C
SIMC0
SIMC1
SIMD
SIMA/SIMC2
TM0C0
TM0C1
TM0DL
TM0DH
TM0AL
TM0AH
EEA
EED
EEC
TMPC0
TMPC1
PRM0
PRM1
PRM2
TM1C0
TM1C1
TM1C2
TM1DL
TM1DH
TM1AL
TM1AH
TM1BL
TM1BH
Rev. 1.60
64
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
Register
TM2C0
(Power-on)
(Normal Operation)
0 0 0 0 0 - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
u u u u u - - -
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
TM2C1
TM2DL
TM2DH
TM2AL
TM2AH
TM2RP
TM3C0
TM3C1
TM3DL
TM3DH
TM3AL
TM3AH
SCOMC
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.60
65
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
HT66F60 Register
Register
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
(Power-on)
(Normal Operation)
MP0
x x x x x x x x
x x x x x x x x
- - 0- - 0 0 0
x x x x x x x x
0 0 0 0 0 0 0 0
x x x x x x x x
x x x x x x x x
- - x x x x x x
- - 0 0 x x x x
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
0 0 0 0 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
x x x x x x x x
x x x x x x x x
- - 0- - 0 0 0
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
- - u u u u u u
- - u u u u u u
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
0 0 0 0 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
x x x x x x x x
x x x x x x x x
- - 0- - 0 0 0
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
- - u u u u u u
- - 1 u u u u u
0 0 0 0 0 0 1 1
- - 0 0 - 0 0 0
0 0 0 0 0 0 0 0
0 1 1 1 1 0 1 0
0 0 1 1 0 1 1 1
- 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 0 0 0 0
- - 0 0 - - 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
- - u - - u u u
u u u u u u u u
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
- - u u u u u u
- - 1 1 u u u u
u u u u u u u u
- - u u - u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- u u u - u u u
u u u u u u u u
- - u u - - u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
MP1
BP
ACC
PCL
TBLP
TBLH
TBHP
STATUS
SMOD
LVDC
INTEG
WDTC
TBC
INTC0
INTC1
INTC2
INTC3
MFI0
MFI1
MFI2
MFI3
PAWU
PAPU
PA
PAC
PBPU
PB
PBC
PCPU
PC
PCC
PDPU
PD
PDC
PEPU
PE
PEC
PFPU
Rev. 1.60
66
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
Register
(Power-on)
(Normal Operation)
PF
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - - - - - 0 0
- - - - - - 1 1
- - - - - - 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
0 1 1 0 0 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
- - - - 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
x x x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 0 0 1 - - 0 1
- - 0 1 - - 0 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
u u u u u u u u
PFC
PGPU
PG
- - - - - - 1 1
- - - - - - 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
0 1 1 0 0 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
- - - - 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
x x x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 0 0 1 - - 0 1
- - 0 1 - - 0 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 1 1
- - - - - - 1 1
x x x x - - - -
x x x x x x x x
x x x x x x x x
- - - - x x x x
0 1 1 0 0 0 0 0
0 0 - 0 - 0 0 0
1 1 1 1 1 1 1 1
- - - - 1 1 1 1
1 0 0 0 0 - - 1
1 0 0 0 0 - - 1
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
x x x x x x x x
x x x x x x x x
- - - - 0 0 0 0
1 0 0 1 - - 0 1
- - 0 1 - - 0 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - u u
- - - - - - u u
u u u u - - - -
u u u u u u u u
u u u u u u u u
- - - - u u u u
u u u u u u u u
u u - u - u u u
u u u u u u u u
- - - - u u u u
u u u u u - - u
u u u u u - - u
u u u u u u u -
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
u u u u u u u u
- - - - u u u u
u u u u - - u u
- - u u - - u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
PGC
ADRL (ADREF=0)
ADRL (ADREF=1)
ADRH(ADREF=0)
ADRH (ADREF=1)
ADCR0
ADCR1
ACERL
ACERH
CP0C
CP1C
SIMC0
SIMC1
SIMD
SIMA/SIMC2
TM0C0
TM0C1
TM0DL
TM0DH
TM0AL
TM0AH
EEA
EED
EEC
TMPC0
TMPC1
PRM0
PRM1
PRM2
TM1C0
TM1C1
TM1C2
TM1DL
TM1DH
TM1AL
Rev. 1.60
67
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Reset
RES or LVR
Reset
WDT Time-out
WDT Time-out
(IDLE)
Register
TM1AH
(Power-on)
(Normal Operation)
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 - - -
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - 0 0
0 0 0 0 0 0 0 0
- - - - - - u u
u u u u u u u u
- - - - - - u u
u u u u u - - -
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
- - - - - - u u
u u u u u u u u
TM1BL
TM1BH
TM2C0
TM2C1
TM2DL
TM2DH
TM2AL
TM2AH
TM2RP
TM3C0
TM3C1
TM3DL
TM3DH
TM3AL
TM3AH
SCOMC
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.60
68
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin
fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is
provided with an I/O structure to meet the needs of a wide range of application possibilities.
The device provides bidirectional input/output lines labeled with port names PA~PG. These I/O ports are mapped to the
RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports
can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs
must be ready at the T2 rising edge of instruction ²MOV A,[m]², where m denotes the port address. For output opera-
tion, all the data is latched and remains unchanged until the output latch is rewritten.
·
I/O Register List
¨
HT66F20
Bit
Register
Name
7
6
5
4
3
2
1
0
PAWU
PAPU
PA
D7
D7
D7
D7
¾
¾
¾
¾
¾
¾
D6
D6
D6
D6
¾
¾
¾
¾
¾
¾
D5
D5
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
PAC
PBPU
PB
PBC
PCPU
PC
¾
¾
¾
¾
¾
¾
PCC
¨
HT66F30
Bit
Register
Name
7
6
5
4
3
2
1
0
PAWU
PAPU
PA
D7
D7
D7
D7
¾
D6
D6
D6
D6
¾
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
PAC
PBPU
PB
¾
¾
PBC
PCPU
PC
¾
¾
D7
D7
D7
D6
D6
D6
PCC
Rev. 1.60
69
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F40/HT66F50
Bit
Register
Name
7
6
5
4
3
2
1
0
PAWU
PAPU
PA
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
¾
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
¾
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
¾
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
¾
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
¾
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
¾
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
PAC
PBPU
PB
PBC
PCPU
PC
PCC
PDPU
PD
PDC
PEPU
PE
PEC
PFPU
PF
¾
¾
¾
¾
¾
¾
PFC
¾
¾
¾
¾
¾
¾
Rev. 1.60
70
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F60
Bit
Register
Name
7
6
5
4
3
2
1
0
PAWU
PAPU
PA
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
¾
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
¾
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
¾
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
¾
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
¾
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
¾
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
PAC
PBPU
PB
PBC
PCPU
PC
PCC
PDPU
PD
PDC
PEPU
PE
PEC
PFPU
PF
PFC
PGPU
PG
¾
¾
¾
¾
¾
¾
PGC
¾
¾
¾
¾
¾
¾
Rev. 1.60
71
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external re-
sistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of
being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PGPU,
and are implemented using weak PMOS transistors.
·
PAPU Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
·
PBPU Register
¨
HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
·
·
·
PCPU Register
¨
HT66F30/HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
PDPU Register
¨
HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
PEPU Register
¨
HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Rev. 1.60
72
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
PFPU Register
¨
HT66F60
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bit 7~0
I/O Port bit 7 ~ bit 0 Pull-High Control
0: Disable
1: Enable
·
PBPU Register
¨
HT66F20/HT66F30
Bit
Name
R/W
7
6
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
¾
¾
¾
¾
¾
¾
POR
Bit 7~6
Bit 5~0
²¾² Unimplemented, read as ²0²
PBPU: Port B bit 5 ~ bit 0 Pull-High Control
0: Disable
1: Enable
·
PCPU Register
¨
HT66F20
Bit
Name
R/W
7
6
5
4
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~4
Bit 3~0
²¾² Unimplemented, read as ²0²
PCPU: Port C bit 3 ~ bit 0 Pull-High Control
0: Disable
1: Enable
·
PFPU Register
¨
HT66F40/HT66F50
Bit
Name
R/W
7
6
5
4
3
2
1
D1
R/W
0
0
D0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~2
Bit 1~0
²¾² Unimplemented, read as ²0²
PFPU: Port F bit 1 ~ bit 0 Pull-High Control
0: Disable
1: Enable
Rev. 1.60
73
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
PGPU Register
¨
HT66F60
Bit
Name
R/W
7
6
5
4
3
2
1
D1
R/W
0
0
D0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~2
Bit 1~0
²¾² Unimplemented, read as ²0²
PGPU: Port G bit 1 ~ bit 0 Pull-High Control
0: Disable
1: Enable
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is
important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of
which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for
applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this
wake-up feature using the PAWU register.
·
PAWU Register
Bit
7
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
Name
R/W
D7
R/W
0
POR
Bit 7~0
PAWU: Port A bit 7 ~ bit 0 Wake-up Control
0: Disable
1: Enable
I/O Port Control Registers
Each I/O port has its own control register known as PAC~PGC, to control the input/output configuration. With this con-
trol register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O
ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corre-
sponding bit of the control register must be written as a ²1². This will then allow the logic state of the input pin to be di-
rectly read by instructions. When the corresponding bit of the control register is written as a ²0², the I/O pin will be setup
as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register.
However, it should be noted that the program will in fact only read the status of the output data latch and not the actual
logic status of the output pin.
·
PAC Register
Bit
Name
R/W
7
D7
R/W
1
6
D6
R/W
1
5
D5
R/W
1
4
D4
R/W
1
3
D3
R/W
1
2
D2
R/W
1
1
D1
R/W
1
0
D0
R/W
1
POR
·
PBC Register
¨
HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
D7
R/W
1
6
D6
R/W
1
5
D5
R/W
1
4
D4
R/W
1
3
D3
R/W
1
2
D2
R/W
1
1
D1
R/W
1
0
D0
R/W
1
POR
Rev. 1.60
74
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
·
·
·
PCC Register
¨
HT66F30/HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
D7
R/W
1
6
D6
R/W
1
5
D5
R/W
1
4
D4
R/W
1
3
D3
R/W
1
2
D2
R/W
1
1
D1
R/W
1
0
D0
R/W
1
POR
PDC Register
¨
HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
D7
R/W
1
6
D6
R/W
1
5
D5
R/W
1
4
D4
R/W
1
3
D3
R/W
1
2
D2
R/W
1
1
D1
R/W
1
0
D0
R/W
1
POR
PEC Register
¨
HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
D7
R/W
1
6
D6
R/W
1
5
D5
R/W
1
4
D4
R/W
1
3
D3
R/W
1
2
D2
R/W
1
1
D1
R/W
1
0
D0
R/W
1
POR
PFC Register
¨
HT66F60
Bit
Name
R/W
7
D7
R/W
1
6
D6
R/W
1
5
D5
R/W
1
4
D4
R/W
1
3
D3
R/W
1
2
D2
R/W
1
1
D1
R/W
1
0
D0
R/W
1
POR
Bit 7~0
I/O Port bit 7 ~ bit 0 Input/Output Control
0: Output
1: Input
·
PBC Register
¨
HT66F20/HT66F30
Bit
Name
R/W
7
6
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
¾
¾
¾
¾
¾
¾
POR
Bit 7~6
Bit 5~0
²¾² Unimplemented, read as ²0²
PBC: Port B bit 5 ~ bit 0 Input/Output Control
0: Output
1: Input
Rev. 1.60
75
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
·
·
PCC Register
¨
HT66F20
Bit
Name
R/W
7
6
5
4
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~4
Bit 3~0
²¾² Unimplemented, read as ²0²
PCC: Port C bit 3 ~ bit 0 Input/Output Control
0: Output
1: Input
PFC Register
¨
HT66F40/HT66F50
Bit
Name
R/W
7
6
5
4
3
2
1
D1
R/W
0
0
D0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~2
Bit 1~0
²¾² Unimplemented, read as ²0²
PFC: Port F bit 1 ~ bit 0 Input/Output Control
0: Output
1: Input
PGC Register
¨
HT66F60
Bit
Name
R/W
7
6
5
4
3
2
1
D1
R/W
0
0
D0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~2
Bit 1~0
²¾² Unimplemented, read as ²0²
PGC: Port G bit 1 ~ bit 0 Input/Output Control
0: Output
1: Input
Rev. 1.60
76
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Pin-remapping Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function.
Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions,
many of these difficulties can be overcome. The way in which the pin function of each pin is selected is different for each
function and a priority order is established where more than one pin function is selected simultaneously. Additionally
there are a series of PRM0, PRM1 and PRM2 registers to establish certain pin functions.
Pin-remapping Registers
The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device
can contain. However by allowing the same pins to share several different functions and providing a means of function
selection, a wide range of different functions can be incorporated into even relatively small package sizes. Some de-
vices include PRM0, PRM1 or PRM2 registers which can select the functions of certain pins.
·
Pin-remapping Register List
¨
HT66F30
Bit
Register
Name
7
6
5
4
3
2
1
0
PRM0
PCPRM
SIMPS0
PCKPS
¾
¾
¾
¾
¾
¨
HT66F40
Bit
Register
Name
7
¾
6
5
4
C0XPS0
¾
3
2
1
0
PRM0
PRM1
PRM2
C1XPS0
TCK1PS
¾
PDPRM
SIMPS1
SIMPS0
PCKPS
¾
TCK2PS
¾
TCK0PS
TP21PS
INT1PS1 INT1PS0 INT0PS1 INT0PS0
TP20PS TP1B2PS TP1APS
TP01PS
TP00PS
¨
HT66F50
Bit
Register
Name
7
6
5
4
C0XPS0
¾
3
2
1
0
PRM0
PRM1
PRM2
C1XPS0
TCK1PS
TP30PS
PDPRM
SIMPS1
SIMPS0
PCKPS
¾
¾
TCK2PS
TP31PS
TCK0PS
TP21PS
INT1PS1 INT1PS0 INT0PS1 INT0PS0
TP20PS TP1B2PS TP1APS
TP01PS
TP00PS
¨
HT66F60
Bit
Register
Name
7
6
5
4
3
2
1
0
PRM0
PRM1
PRM2
C1XPS1
TCK2PS
TP31PS
C1XPS0
TCK1PS
TP30PS
C0XPS1
TCK0PS
TP21PS
C0XPS0
PDPRM
SIMPS1
SIMPS0
PCKPS
INT2PS1 INT1PS1 INT1PS0 INT0PS1 INT0PS0
TP20PS TP1B2PS TP1APS TP01PS TP00PS
Rev. 1.60
77
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
PRM0 Register
¨
HT66F30
Bit
Name
R/W
7
6
5
4
3
2
PCPRM
R/W
0
1
SIMPS0
R/W
0
0
PCKPS
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~3
Bit 2
²¾² Unimplemented, read as ²0²
PCPRM: PC1~PC0 pin-shared function Pin Remapping Control
0: No change
1: TP1B_0 on PC0 change to PA6, TP1B_1 on PC1 change to PA7 if SIMPS0=1
Bit 1
Bit 0
SIMPS0: SIM Pin Remapping Control
0: SDO on PA5; SDI/SDA on PA6; SCK/SCL on PA7; SCS on PB5
1: SDO on PC1; SDI/SDA on PC0; SCK/SCL on PC7; SCS on PC6
PCKPS: PCK and PINT Pin Remapping Control
0: PCK on PC2; PINT on PC3
1: PCK on PC5; PINT on PC4
·
PRM0 Register
¨
HT66F40/HT66F50
Bit
Name
R/W
7
6
C1XPS0
R/W
0
5
4
C0XPS0
R/W
0
3
PDPRM
R/W
0
2
SIMPS1
R/W
0
1
SIMPS0
R/W
0
0
PCKPS
R/W
0
¾
¾
¾
¾
¾
¾
POR
Bit 7
Bit 6
²¾² Unimplemented, read as ²0²
C1XPS0: C1X Pin Remapping Control
0: C1X on PA5
1: C1X on PF1
Bit 5
Bit 4
²¾² Unimplemented, read as ²0²
C0XPS0: C0X Pin Remapping Control
0: C0X on PA0
1: C0X on PF0
Bit 3
PDPRM: PD3~PD0 pin-shared function Pin Remapping Control
0: No change
1: TCK2 on PD0 change to PB6, TP2_0 on PD1 change to PB7, TCK0 on PD2 change to PD6,
TCK1 on PD3 change to PD7 if SIMPS1, SIMPS0=01
Bit 2~1
SIMPS1, SIMPS0: SIM Pin Remapping Control
00: SDO on PA5; SDI/SDA on PA6; SCK/SCL on PA7; SCS on PB5
01: SDO on PD3; SDI/SDA on PD2; SCK/SCL on PD1; SCS on PD0
10: SDO on PB6; SDI/SDA on PB7; SCK/SCL on PD6; SCS on PD7
11: Undefined
Bit 0
PCKPS: PCK and PINT Pin Remapping Control
0: PCK on PC2; PINT on PC3
1: PCK on PC5; PINT on PC4
Rev. 1.60
78
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
PRM0 Register
¨
HT66F60
Bit
Name
R/W
7
C1XPS1
R/W
0
6
C1XPS0
R/W
0
5
C0XPS1
R/W
0
4
C0XPS0
R/W
0
3
PDPRM
R/W
0
2
SIMPS1
R/W
0
1
SIMPS0
R/W
0
0
PCKPS
R/W
0
POR
Bit 7~6
C1XPS1, C1XPS0: C1X Pin Remapping Control
00: C1X on PA5
01: C1X on PF1
10: C1X on PG1
11: Undefined
Bit 5~4
C0XPS1, C0XPS0: C0X Pin Remapping Control
00: C0X on PA0
01: C0X on PF0
10: C0X on PG0
11: Undefined
Bit 3
PDPRM: PD3~PD0 pin-shared function Pin Remapping Control
0: No change
1: TCK2 on PD0 change to PB6, TP2_0 on PD1 change to PB7, TCK0 on PD2 change to PD6,
TCK1 on PD3 change to PD7 if SIMPS1, SIMPS0=01 or 11
Bit 2~1
SIMPS1, SIMPS0: SIM Pin Remapping Control
00: SDO on PA5; SDI/SDA on PA6; SCK/SCL on PA7; SCS on PB5
01: SDO on PD3; SDI/SDA on PD2; SCK/SCL on PD1; SCS on PD0
10: SDO on PB6; SDI/SDA on PB7; SCK/SCL on PD6; SCS on PD7
11: SDO on PD1; SDI/SDA on PD2; SCK/SCL on PD3; SCS on PD0
Bit 0
PCKPS: PCK and PINT Pin Remapping Control
0: PCK on PC2; PINT on PC3
1: PCK on PC5; PINT on PC4
·
PRM1 Register
¨
HT66F40/HT66F50
Bit
Name
R/W
7
TCK2PS
R/W
6
TCK1PS
R/W
5
TCK0PS
R/W
4
3
2
1
0
INT1PS1 INT1PS0 INT0PS1 INT0PS0
¾
¾
¾
R/W
0
R/W
0
R/W
0
R/W
0
POR
0
0
0
Bit 7
Bit 6
Bit 5
TCK2PS: TCK2 Pin Remapping Control
0: TCK2 on PC2
1: TCK2 on PD0
TCK1PS: TCK1 Pin Remapping Control
0: TCK1 on PA4
1: TCK1 on PD3
TCK0PS: TCK0 Pin Remapping Control
0: TCK0 on PA2
1: TCK0 on PD2
Bit 4
²¾² Unimplemented, read as ²0²
Bit 3~2
INT1PS1, INT1PS0: INT1 Pin Remapping Control
00: INT1 on PA4
01: INT1 on PC5
10: Undefined
11: INT1 on PE7
Bit 1~0
INT0PS1, INT0PS0: INT0 Pin Remapping Control
00: INT0 on PA3
01: INT0 on PC4
10: Undefined
11: INT0 on PE6
Rev. 1.60
79
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
PRM1 Register
¨
HT66F60
Bit
Name
R/W
7
TCK2PS
R/W
6
TCK1PS
R/W
5
TCK0PS
R/W
4
INT2PS
R/W
0
3
2
1
0
INT1PS1 INT1PS0 INT0PS1 INT0PS0
R/W
0
R/W
0
R/W
0
R/W
0
POR
0
0
0
Bit 7
TCK2PS: TCK2 Pin Remapping Control
0: TCK2 on PC2
1: TCK2 on PD0
Bit 6
TCK1PS: TCK1 Pin Remapping Control
0: TCK1 on PA4
1: TCK1 on PD3
Bit 5
TCK0PS: TCK0 Pin Remapping Control
0: TCK0 on PA2
1: TCK0 on PD2
Bit 4
INT2PS: INT2 Pin Remapping Control
0: INT2 on PC4
1: INT2 on PE2
Bit 3~2
INT1PS1, INT1PS0: INT1 Pin Remapping Control
00: INT1 on PA4
01: INT1 on PC5
10: INT1 on PE1
11: INT1 on PE7
Bit 1~0
INT0PS1, INT0PS0: INT0 Pin Remapping Control
00: INT0 on PA3
01: INT0 on PC4
10: INT0 on PE0
11: INT0 on PE6
·
PRM2 Register
¨
HT66F40
Bit
Name
R/W
7
6
5
TP21PS
R/W
0
4
3
2
1
TP01PS
R/W
0
0
TP00PS
R/W
0
TP20PS TP1B2PS TP1APS
¾
¾
¾
¾
¾
¾
R/W
0
R/W
0
R/W
0
POR
Bit 7~6
Bit 5
²¾² Unimplemented, read as ²0²
TP21PS: TP2_1 Pin Remapping Control
0: TP2_1 on PC4
1: TP2_1 on PD4
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TP20PS: TP2_0 Pin Remapping Control
0: TP2_0 on PC3
1: TP2_0 on PD1
TP1B2PS: TP1B_2 Pin Remapping Control
0: TP1B_2 on PC5
1: TP1B_2 on PE4
TP1APS: TP1A Pin Remapping Control
0: TP1A on PA1
1: TP1A on PC7
TP01PS: TP0_1 Pin Remapping Control
0: TP0_1 on PC5
1: TP0_1 on PD5
TP00PS: TP0_0 Pin Remapping Control
0: TP0_0 on PA0
1: TP0_0 on PC6
Rev. 1.60
80
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
PRM2 Register
¨
HT66F50/HT66F60
Bit
Name
R/W
7
TP31PS
R/W
0
6
TP30PS
R/W
0
5
TP21PS
R/W
0
4
3
2
1
TP01PS
R/W
0
0
TP00PS
R/W
0
TP20PS TP1B2PS TP1APS
R/W
0
R/W
0
R/W
0
POR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TP31PS: TP3_1 Pin Remapping Control
0: TP3_1 on PD0
1: TP3_1 on PE3
TP30PS: TP3_0 Pin Remapping Control
0: TP3_0 on PD3
1: TP3_0 on PE5
TP21PS: TP2_1 Pin Remapping Control
0: TP2_1 on PC4
1: TP2_1 on PD4
TP20PS: TP2_0 Pin Remapping Control
0: TP2_0 on PC3
1: TP2_0 on PD1
TP1B2PS: TP1B_2 Pin Remapping Control
0: TP1B_2 on PC5
1: TP1B_2 on PE4
TP1APS: TP1A Pin Remapping Control
0: TP1A on PA1
1: TP1A on PC7
TP01PS: TP0_1 Pin Remapping Control
0: TP0_1 on PC5
1: TP0_1 on PD5
TP00PS: TP0_0 Pin Remapping Control
0: TP0_0 on PA0
1: TP0_0 on PC6
Rev. 1.60
81
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
I/O Pin Structures
be achieved byte-wide by loading the correct values into
the appropriate port control register or by programming
The accompanying diagrams illustrate the internal
structures of some generic I/O pin types. As the exact
logical construction of the I/O pin will differ from these
drawings, they are supplied as a guide only to assist
with the functional understanding of the I/O pins. The
wide range of pin-shared structures does not permit all
types to be shown.
individual bits in the port control register using the ²SET
[m].i² and ²CLR [m].i² instructions. Note that when using
these bit control instructions, a read-modify-write opera-
tion takes place. The microcontroller must first read in
the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output
ports.
Programming Considerations
Port A has the additional capability of providing wake-up
functions. When the device is in the SLEEP or IDLE
Mode, various methods are available to wake the device
up. One of these is a high to low transition of any of the
Port A pins. Single or multiple pins on Port A can be
setup to have this function.
Within the user program, one of the first things to con-
sider is port initialisation. After a reset, all of the I/O data
and port control registers will be set high. This means
that all I/O pins will default to an input state, the level of
which depends on the other connected circuitry and
whether pull-high selections have been chosen. If the
port control registers, PAC~PGC, are then programmed
to setup some pins as outputs, these output pins will
have an initial high output value unless the associated
port data registers, PA~PG, are first programmed. Se-
lecting which pins are inputs and which are outputs can
V
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Generic Input/Output Structure
Rev. 1.60
82
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
V
D
D
P
R
S
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-
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A/D Input/Output Structure
Rev. 1.60
83
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Timer Modules - TM
One of the most fundamental functions in any
microcontroller device is the ability to control and mea-
sure time. To implement time related functions each de-
vice includes several Timer Modules, abbreviated to the
name TM. The TMs are multi-purpose timing units and
serve to provide operations such as Timer/Counter, In-
put Capture, Compare Match Output and Single Pulse
Output as well as being the functional unit for the gener-
ation of PWM signals. Each of the TMs has either two or
three individual interrupts. The addition of input and out-
put pins for each TM ensures that users are provided
with timing units with a wide and flexible range of fea-
tures.
Introduction
The devices contain from two to four TMs depending
upon which device is selected with each TM having a
reference name of TM0, TM1, TM2 and TM3. Each indi-
vidual TM can be categorised as a certain type, namely
Compact Type TM, Standard Type TM or Enhanced
Type TM. Although similar in nature, the different TM
types vary in their feature complexity. The common fea-
tures to all of the Compact, Standard and Enhanced
TMs will be described in this section, the detailed opera-
tion regarding each of the TM types will be described in
separate sections. The main features and differences
between the three types of TMs are summarised in the
accompanying table.
The common features of the different TM types are de-
scribed here with more detailed information provided in
the individual Compact, Standard and Enhanced TM
sections.
Function
CTM
STM
ETM
Timer/Counter
I/P Capture
Ö
Ö
Ö
¾
Ö
Ö
Compare Match Output
PWM Channels
Ö
Ö
Ö
1
¾
1
2
Single Pulse Output
PWM Alignment
1
2
Edge
Edge
Edge & Centre
Duty or Period
PWM Adjustment Period & Duty
Duty or Period
Duty or Period
TM Function Summary
Each device in the series contains a specific number of either Compact Type, Standard Type and Enhanced Type TM
units which are shown in the table together with their individual reference name, TM0~TM3.
Device
TM0
TM1
10-bit STM
TM2
¾
TM3
HT66F20
HT66F30
HT66F40
HT66F50
HT66F60
10-bit CTM
10-bit CTM
10-bit CTM
10-bit CTM
10-bit CTM
¾
¾
10-bit ETM
¾
10-bit ETM
16-bit STM
16-bit STM
16-bit STM
¾
10-bit ETM
10-bit CTM
10-bit CTM
10-bit ETM
TM Name/Type Reference
Rev. 1.60
84
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
TM Operation
functions, it consequently has three internal interrupts.
When a TM interrupt is generated it can be used to clear
The three different types of TM offer a diverse range of
functions, from simple timing operations to PWM signal
generation. The key to understanding how the TM oper-
ates is to see it in terms of a free running counter whose
value is then compared with the value of
pre-programmed internal comparators. When the free
running counter has the same value as the
pre-programmed comparator, known as a compare
match situation, a TM interrupt signal will be generated
which can clear the counter and perhaps also change
the condition of the TM output pin. The internal TM
counter is driven by a user selectable clock source,
which can be an internal clock or an external pin.
the counter and also to change the state of the TM out-
put pin.
TM External Pins
Each of the TMs, irrespective of what type, has one TM
input pin, with the label TCKn. The TM input pin, is es-
sentially a clock source for the TM and is selected using
the TnCK2~TnCK0 bits in the TMnC0 register. This ex-
ternal TM input pin allows an external clock source to
drive the internal TM. This external TM input pin is
shared with other functions but will be connected to the
internal TM if selected using the TnCK2~TnCK0 bits.
The TM input pin can be chosen to have either a rising or
falling active edge.
TM Clock Source
The clock source which drives the main counter in each
TM can originate from various sources. The selection of
the required clock source is implemented using the
TnCK2~TnCK0 bits in the TM control registers. The
clock source can be a ratio of either the system clock
fSYS or the internal high clock fH, the fTBC clock source or
the external TCKn pin. Note that setting these bits to the
value 101 will select a reserved clock input, in effect dis-
connecting the TM clock source. The TCKn pin clock
source is used to allow an external signal to drive the TM
as an external clock source or for event counting.
The TMs each have one or more output pins with the la-
bel TPn. When the TM is in the Compare Match Output
Mode, these pins can be controlled by the TM to switch
to a high or low level or to toggle when a compare match
situation occurs. The external TPn output pin is also the
pin where the TM generates the PWM output waveform.
As the TM output pins are pin-shared with other func-
tion, the TM output function must first be setup using
registers. Asingle bit in one of the registers determines if
its associated pin is to be used as an external TM output
pin or if it is to have another function. The number of out-
put pins for each TM type and device is different, the de-
tails are provided in the accompanying table.
TM Interrupts
The Compact and Standard type TMs each have two in-
ternal interrupts, one for each of the internal comparator
A or comparator P, which generate a TM interrupt when
a compare match condition occurs. As the Enhanced
type TM has three internal comparators and comparator
A or comparator B or comparator P compare match
All TM output pin names have an ²_n² suffix. Pin names
that include a ²_1² or ²_2² suffix indicate that they are
from a TM with multiple output pins. This allows the TM
to generate a complimentary output pair, selected using
the I/O register data bits.
Device
CTM
STM
ETM
Registers
HT66F20
TP0_0
TP1_0, TP1_1
TMPC0
¾
TP1A, TP1B_0,
TP1B_1
HT66F30
HT66F40
HT66F50
HT66F60
TP0_0, TP0_1
TP0_0, TP0_1
TMPC0
¾
TP1A, TP1B_0,
TP2_0, TP2_1
TP2_0, TP2_1
TMPC0, TMPC1
TMPC0, TMPC1
TMPC0, TMPC1
TP1B_1, TP1B_2
TP0_0, TP0_1
TP3_0, TP3_1
TP1A, TP1B_0,
TP1B_1, TP1B_2
TP0_0, TP0_1
TP3_0, TP3_1
TP1A, TP1B_0,
TP2_0, TP2_1
TP1B_1, TP1B_2
TM Output Pins
Rev. 1.60
85
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
TM Input/Output Pin Control Registers
Selecting to have a TM input/output or whether to retain its other shared function, is implemented using one or two reg-
isters, with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corre-
sponding pin as a TM input/output, if reset to zero the pin will retain its original other function.
Bit
Registers
Device
7
¾
6
5
4
3
2
1
¾
0
TMPC0
TMPC0
HT66F20
HT66F30
T1CP1
T1BCP1
T1CP0
T1BCP0
T0CP0
T0CP0
¾
¾
¾
¾
¾
¾
T1ACP0
T0CP1
HT66F40
HT66F50
HT66F60
TMPC0
T1ACP0
T1BCP2
T1BCP1
T1BCP0
T0CP1
T0CP0
¾
¾
TMPC1
TMPC1
HT66F40
T2CP1
T2CP1
T2CP0
T2CP0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
HT66F50
HT66F60
T3CP1
T3CP0
TM Input/Output Pin Control Registers List
0
1
P
A
0
O
u
t
p
u
t
F
u
n
c
t
i
o
n
P
A
0
/
T
P
0
_
0
O
u
t
p
u
t
T
0
C
P
0
T
M
0
(
C
T
M
)
T
C
K
I
n
p
u
t
P
A
2
/
T
C
K
0
P
A
1
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
A
1
/
T
P
1
_
0
0
1
T
1
C
P
0
P
A
1
P
C
0
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
0
/
T
P
1
_
1
O
u
t
p
u
t
0
1
T
1
C
P
1
P
C
0
1
0
C
a
p
t
u
r
e
I
n
p
u
t
T
M
1
T
1
C
P
1
(
S
T
M
)
1
0
T
1
C
P
0
T
C
K
I
n
p
u
t
P
A
4
/
T
C
K
1
HT66F20 TM Function Pin Control Block Diagram
Note: 1. The I/O register data bits shown are used for TM output inversion control.
2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.
Rev. 1.60
86
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
0
1
P
A
0
O
u
t
p
u
t
F
u
n
c
t
i
o
n
P
A
0
/
T
P
0
_
0
0
1
T
0
C
P
0
P
5
A
0
0
1
P
C
O
u
t
p
u
t
F
u
n
c
t
i
o
n
P
C
5
/
T
P
0
_
1
O
u
t
p
u
t
0
1
T
0
C
P
1
T
M
0
(
C
T
M
)
P
C
5
T
C
K
I
n
p
u
t
P
A
2
/
T
C
K
0
P
A
1
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
A
1
/
T
P
1
A
C
C
R
A
O
u
t
p
u
t
T
1
A
C
P
0
1
0
C
C
R
A
C
a
p
t
u
r
e
I
n
p
u
t
T
1
A
C
P
0
P
C
0
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
0
/
T
P
1
B
_
0
0
1
T
1
B
C
P
0
P
C
0
T
M
1
P
C
1
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
(
E
T
M
)
P
C
1
/
T
P
1
B
_
1
C
C
R
B
O
u
t
p
u
t
0
1
T
1
B
C
P
1
P
C
1
1
0
C
C
R
B
C
a
p
t
u
r
e
I
n
p
u
t
T
1
B
C
P
1
1
0
T
1
B
C
P
0
T
C
K
I
n
p
u
t
P
A
4
/
T
C
K
1
HT66F30 TM Function Pin Control Block Diagram
Note: 1. The I/O register data bits shown are used for TM output inversion control.
2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.
Rev. 1.60
87
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
0
1
P
A
0
O
u
t
p
u
t
F
u
n
c
t
i
o
n
P
A
0
/
T
P
0
_
0
0
1
T
0
C
P
0
P
5
A
0
0
1
P
C
O
u
t
p
u
t
F
u
n
c
t
i
o
n
P
C
5
/
T
P
0
_
1
O
u
t
p
u
t
0
1
T
0
C
P
1
T
M
0
(
C
T
M
)
P
C
5
T
C
K
I
n
p
u
t
P
A
2
/
T
C
K
0
P
C
3
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
3
/
T
P
2
_
0
0
1
T
2
C
P
0
P
C
3
P
C
4
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
4
/
T
P
2
_
1
O
u
t
p
u
t
0
1
T
2
C
P
1
P
C
4
1
0
C
a
p
t
u
r
e
I
n
p
u
t
T
M
2
T
2
C
P
1
(
S
T
M
)
1
0
T
2
C
P
0
T
C
K
I
n
p
u
t
P
C
2
/
T
C
K
2
HT66F40 TM0 & TM2 Function Pin Control Block Diagram
Note: 1. The I/O register data bits shown are used for TM output inversion control.
2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.
Rev. 1.60
88
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
P
A
1
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
A
1
/
T
P
1
A
C
C
R
A
O
u
t
p
u
t
T
1
A
C
P
0
1
0
C
C
R
A
C
a
p
t
u
r
e
I
n
p
u
t
T
1
A
C
P
0
P
C
0
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
0
/
T
P
1
B
_
0
0
1
T
1
B
C
P
0
P
C
0
P
C
1
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
1
/
T
P
1
B
_
1
0
1
T
1
B
C
P
1
T
M
1
P
C
1
(
E
T
M
)
P
C
5
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
5
/
T
P
1
B
_
2
C
C
R
B
O
u
t
p
u
t
0
1
T
1
B
C
P
2
P
C
5
1
0
C
C
R
B
C
a
p
t
u
r
e
I
n
p
u
t
T
1
B
C
P
2
1
0
T
1
B
C
P
1
1
0
T
1
B
C
P
0
T
C
K
I
n
p
u
t
P
A
4
/
T
C
K
1
HT66F40 TM1 Function Pin Control Block Diagram
Note: 1. The I/O register data bits shown are used for TM output inversion control.
2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.
Rev. 1.60
89
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
0
1
P
A
0
O
u
t
p
u
t
F
u
n
c
t
i
o
n
P
A
0
/
T
P
0
_
0
0
1
T
0
C
P
0
P
5
A
0
0
1
P
C
O
u
t
p
u
t
F
u
n
c
t
i
o
n
P
C
5
/
T
P
0
_
1
O
u
t
p
u
t
0
1
T
0
C
P
1
T
M
0
(
C
T
M
)
P
C
5
T
C
K
I
n
p
u
t
P
A
2
/
T
C
K
0
P
C
3
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
3
/
T
P
2
_
0
0
1
T
2
C
P
0
P
C
3
P
C
4
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
4
/
T
P
2
_
1
O
u
t
p
u
t
0
1
T
2
C
P
1
P
C
4
1
0
C
a
p
t
u
r
e
I
n
p
u
t
T
M
2
T
2
C
P
1
(
S
T
M
)
1
0
T
2
C
P
0
T
C
K
I
n
p
u
t
P
C
2
/
T
C
K
2
0
1
P
D
3
O
u
t
p
u
t
F
u
n
c
t
i
o
n
P
D
3
/
T
P
3
_
0
0
1
T
3
C
P
0
P
0
D
3
0
1
P
D
O
u
t
p
u
t
F
u
n
c
t
i
o
n
P
D
0
/
T
P
3
_
1
O
u
t
p
u
t
0
1
T
3
C
P
1
T
M
3
(
C
T
M
)
P
D
0
T
C
K
I
n
p
u
t
P
C
4
/
T
C
K
3
HT66F50 and HT66F60 TM0, TM2, TM3 Function Pin Control Block Diagram
Note: 1. The I/O register data bits shown are used for TM output inversion control.
2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.
Rev. 1.60
90
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
P
A
1
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
A
1
/
T
P
1
A
C
C
R
A
O
u
t
p
u
t
T
1
A
C
P
0
1
0
C
C
R
A
C
a
p
t
u
r
e
I
n
p
u
t
T
1
A
C
P
0
P
C
0
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
0
/
T
P
1
B
_
0
0
1
T
1
B
C
P
0
P
C
0
P
C
1
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
1
/
T
P
1
B
_
1
0
1
T
1
B
C
P
1
T
M
1
P
C
1
(
E
T
M
)
P
C
5
O
u
t
p
u
t
0
1
F
u
n
c
t
i
o
n
P
C
5
/
T
P
1
B
_
2
C
C
R
B
O
u
t
p
u
t
0
1
T
1
B
C
P
2
P
C
5
1
0
C
C
R
B
C
a
p
t
u
r
e
I
n
p
u
t
T
1
B
C
P
2
1
0
T
1
B
C
P
1
1
0
T
1
B
C
P
0
T
C
K
I
n
p
u
t
P
A
4
/
T
C
K
1
HT66F50 and HT66F60 TM1 Function Pin Control Block Diagram
Note: 1. The I/O register data bits shown are used for TM output inversion control.
2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input.
Rev. 1.60
91
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
TMPC0 Register
¨
HT66F20
Bit
Name
R/W
7
6
5
T1CP1
R/W
0
4
T1CP0
R/W
1
3
2
1
0
T0CP0
R/W
1
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7, 6
Bit 5
Unimplemented, read as ²0²
T1CP1: TP1_1 pin Control
0: disable
1: enable
Bit 4
T1CP0: TP1_0 pin Control
0: disable
1: enable
Bit 3~1
Bit 0
Unimplemented, read as ²0²
T0CP0: TP0_0 pin Control
0: disable
1: enable
¨
HT66F30
Bit
Name
R/W
7
T1ACP0
R/W
1
6
5
T1BCP1
R/W
0
4
T1BCP0
R/W
1
3
2
1
T0CP1
R/W
0
0
T0CP0
R/W
1
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7
T1ACP0: TP1A pin Control
0: disable
1: enable
Bit 6
Bit 5
Unimplemented, read as ²0²
T1BCP1: TP1B_1 pin Control
0: disable
1: enable
Bit 4
T1BCP0: TP1B_0 pin Control
0: disable
1: enable
Bit 3~2
Bit 1
Unimplemented, read as ²0²
T0CP1: TP0_1 pin Control
0: disable
1: enable
Bit 0
T0CP0: TP0_0 pin Control
0: disable
1: enable
Rev. 1.60
92
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
T1ACP0
R/W
1
6
T1BCP2
R/W
0
5
T1BCP1
R/W
0
4
T1BCP0
R/W
1
3
2
1
T0CP1
R/W
0
0
T0CP0
R/W
1
¾
¾
¾
¾
¾
¾
POR
Bit 7
Bit 6
Bit 5
Bit 4
T1ACP0: TP1A pin Control
0: disable
1: enable
T1BCP2: TP1B_2 pin Control
0: disable
1: enable
T1BCP1: TP1B_1 pin Control
0: disable
1: enable
T1BCP0: TP1B_0 pin Control
0: disable
1: enable
Bit 3~2
Bit 1
Unimplemented, read as ²0²
T0CP1: TP0_1 pin Control
0: disable
1: enable
Bit 0
T0CP0: TP0_0 pin Control
0: disable
1: enable
·
TMPC1 Register
¨
HT66F40
Bit
Name
R/W
7
6
5
4
3
2
1
T2CP1
R/W
0
0
T2CP0
R/W
1
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~2
Bit 1
Unimplemented, read as ²0²
T2CP1: TP2_1 pin Control
0: disable
1: enable
Bit 0
T2CP0: TP2_0 pin Control
0: disable
1: enable
Rev. 1.60
93
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F50/HT66F60
Bit
Name
R/W
7
6
5
T3CP1
R/W
0
4
T3CP0
R/W
1
3
2
1
T2CP1
R/W
0
0
T2CP0
R/W
1
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~6
Bit 5
Unimplemented, read as ²0²
T3CP1: TP3_1 pin Control
0: disable
1: enable
Bit 4
T3CP0: TP3_0 pin Control
0: disable
1: enable
Bit 3~2
Bit 1
Unimplemented, read as ²0²
T2CP1: TP2_1 pin Control
0: disable
1: enable
Bit 0
T2CP0: TP2_0 pin Control
0: disable
1: enable
Programming Considerations
The TM Counter Registers and the Capture/Compare CCRA and CCRB registers, being either 10-bit or 16-bit, all have
a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via
an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important
point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or
read operation to its corresponding high byte is executed.
TM Counter Register (Read only)
TMxDL TMxDH
8-bit
Buffer
TMxAL TMxAH
TM CCRA Register (Read/Write)
TMxBL TMxBH
TM CCRB Register (Read/Write)
Data
Bus
As the CCRA and CCRB registers are implemented in the way shown in the following diagram and accessing these
register pairs is carried out in a specific way as described above, it is recommended to use the ²MOV² instruction to ac-
cess the CCRA and CCRB low byte registers, named TMxAL and TMxBL, using the following access procedures. Ac-
cessing the CCRA or CCRB low byte registers without following these access procedures will result in unpredictable
values.
The following steps show the read and write procedures:
·
Writing Data to CCRB or CCRA
¨
¨
Step 1. Write data to Low Byte TMxAL or TMxBL
- note that here data is only written to the 8-bit buffer.
Step 2. Write data to High Byte TMxAH or TMxBH
- here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer
to the Low Byte registers.
Rev. 1.60
94
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
Reading Data from the Counter Registers and CCRB or CCRA
¨
Step 1. Read data from the High Byte TMxDH, TMxAH or TMxBH
- here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte
register into the 8-bit buffer.
¨
Step 2. Read data from the Low Byte TMxDL, TMxAL or TMxBL
- this step reads data from the 8-bit buffer.
Compact Type TM
Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are
Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with
an external input pin and can drive one or two external output pins. These two external output pins can be the same sig-
nal or the inverse signal.
CTM
Name
TM No.
TM Input Pin
TCK0
TM Output Pin
TP0_0
HT66F20
HT66F30
HT66F40
HT66F50
HT66F60
10-bit CTM
10-bit CTM
10-bit CTM
10-bit CTM
10-bit CTM
0
0
TCK0
TP0_0, TP0_1
0
TCK0
TP0_0, TP0_1
0, 3
0, 3
TCK0, TCK3
TCK0, TCK3
TP0_0, TP0_1; TP3_0, TP3_1
TP0_0, TP0_1; TP3_0, TP3_1
Compact TM Operation
At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are
also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the
value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the
highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits.
The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by chang-
ing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare
match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be
generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different
clock sources including an input pin and can also control an output pin. All operating setup conditions are selected us-
ing relevant internal registers.
C
C
R
P
C
o
m
p
a
r
a
t
o
r
P
M
a
t
c
h
3
-
b
i
t
C
o
m
p
a
r
a
t
o
r
P
T
n
P
F
I
n
t
e
r
r
u
p
t
f
S
Y
S
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
b
7
~
b
9
f
S
Y
S
T
n
O
C
f
H
H
/
1
6
f
/
6
4
T
T
P
P
n
n
f
T
B
C
O
u
t
p
u
P
t
o
l
a
r
i
T
t
P
y
n
P
i
n
C
o
u
n
t
e
r
C
l
e
a
r
0
C
o
n
t
r
o
C
l
o
n
t
r
o
O
l
u
t
p
u
t
R
e
s
e
r
v
e
d
1
0
-
b
i
t
C
o
u
n
t
-
u
p
C
o
u
n
t
e
r
1
T
C
K
n
1
1
1
T
n
M
1
,
T
T
n
n
M
P
0
O
L
T
n
C
C
L
R
T
n
O
N
T
n
I
O
1
,
T
n
I
O
0
b
0
~
b
9
T
n
P
A
U
C
o
m
p
a
r
a
t
o
r
A
M
a
t
c
h
1
0
-
b
i
t
C
o
m
p
a
r
a
t
o
r
A
T
n
A
F
I
n
t
e
r
r
u
p
t
T
n
C
K
2
~
T
n
C
K
0
C
C
R
A
Compact Type TM Block Diagram
Rev. 1.60
95
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Compact Type TM Register Description
Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the inter-
nal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining
two registers are control registers which setup the different operating and control modes as well as the three CCRP
bits.
Name
TMnC0
TMnC1
TMnDL
TMnDH
TMnAL
TMnAH
Bit7
TnPAU
TnM1
D7
Bit6
TnCK2
TnM0
D6
Bit5
TnCK1
TnIO1
D5
Bit4
TnCK0
TnIO0
D4
Bit3
TnON
TnOC
D3
Bit2
TnRP2
TnPOL
D2
Bit1
TnRP1
TnDPX
D1
Bit0
TnRP0
TnCCLR
D0
D9
D8
¾
¾
¾
¾
¾
¾
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
¾
¾
¾
¾
¾
¾
Compact TM Register List (n=0 or 3)
·
TMnDL Register
Bit
Name
R/W
7
D7
R
6
D6
R
5
D5
R
4
D4
R
3
D3
R
2
D2
R
1
D1
R
0
D0
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
TMnDL: TMn Counter Low Byte Register bit 7 ~ bit 0
TMn 10-bit Counter bit 7 ~ bit 0
·
TMnDH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R
0
D8
R
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
0
0
Bit 7~2
Bit 1~0
Unimplemented, read as ²0²
TMnDH: TMn Counter High Byte Register bit 1 ~ bit 0
TMn 10-bit Counter bit 9 ~ bit 8
·
TMnAL Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bit 7~0
TMnAL: TMn CCRA Low Byte Register bit 7 ~ bit 0
TMn 10-bit CCRA bit 7 ~ bit 0
·
TMnAH Register
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~2
Bit 1~0
Unimplemented, read as ²0²
TMn 10-bit CCRA bit 9 ~ bit 8
Rev. 1.60
96
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
TMnC0 Register
Bit
7
6
TnCK2
R/W
0
5
TnCK1
R/W
0
4
TnCK0
R/W
0
3
TnON
R/W
0
2
TnRP2
R/W
0
1
TnRP1
R/W
0
0
TnRP0
R/W
0
Name
R/W
TnPAU
R/W
0
POR
Bit 7
TnPAU: TMn Counter Pause Control
0: run
1: pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores normal
counter operation. When in a Pause condition the TM will remain powered up and continue to
consume power. The counter will retain its residual value when this bit changes from low to high
and resume counting from this value when the bit changes to a low value again.
Bit 6~4
TnCK2~TnCK0: Select TMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: undefined
110: TCKn rising edge clock
111: TCKn falling edge clock
These three bits are used to select the clock source for the TM. Selecting the Reserved clock
input will effectively disable the internal counter. The external pin clock source can be chosen to
be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and
f
TBC are other internal clocks, the details of which can be found in the oscillator section.
Bit 3
TnON: TMn Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to
run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting
and turn off the TM which will reduce its power consumption. When the bit changes state from
low to high the internal counter value will be reset to zero, however when the bit changes from
high to low, the internal counter will retain its residual value.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial
condition, as specified by the TnOC bit, when the TnON bit changes from low to high.
Bit 2~0
TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7
Comparator P Match Period
000: 1024 TMn clocks
001: 128 TMn clocks
010: 256 TMn clocks
011: 384 TMn clocks
100: 512 TMn clocks
101: 640 TMn clocks
110: 768 TMn clocks
111: 896 TMn clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which are then
compared with the internal counter's highest three bits. The result of this comparison can be
selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to
zero ensures that a compare match with the CCRP values will reset the internal counter. As the
CCRP bits are only compared with the highest three counter bits, the compare values exist in 128
clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at
its maximum value.
Rev. 1.60
97
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
TMnC1 Register
Bit
Name
R/W
7
TnM1
R/W
0
6
TnM0
R/W
0
5
TnIO1
R/W
0
4
TnIO0
R/W
0
3
TnOC
R/W
0
2
TnPOL
R/W
0
1
TnDPX
R/W
0
0
TnCCLR
R/W
POR
0
Bit 7~6
TnM1~TnM0: Select TMn Operating Mode
00: Compare Match Output Mode
01: Undefined
10: PWM Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation the TM
should be switched off before any changes are made to the TnM1 and TnM0 bits. In the
Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
TnIO1~TnIO0: Select TPn_0, TPn_1 output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Undefined
Timer/counter Mode
unused
These two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the TM is
running.
In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output
pin changes state when a compare match occurs from the Comparator A. The TM output pin can
be setup to switch high, switch low or to toggle its present state when a compare match occurs
from the Comparator A. When the bits are both zero, then no change will take place on the
output. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1
register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from
the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin
when a compare match occurs. After the TM output pin changes state it can be reset to its initial
level by changing the level of the TnON bit from low to high.
In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state
when a certain compare match condition occurs. The PWM output function is modified by
changing these two bits. It is necessary to change the values of the TnIO1 and TnIO0 bits only
after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and
TnIO0 bits are changed when the TM is running
Bit 3
TnOC: TPn_0, TPn_1 Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is
in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of
the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM
signal is active high or active low.
Rev. 1.60
98
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Bit 2
TnPOL: TPn_0, TPn_1 Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the
Timer/Counter Mode.
Bit 1
Bit 0
TnDPX: TMn PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and duty
control of the PWM waveform.
TnCCLR: Select TMn Counter clear condition
0: TMn Comparatror P match
1: TMn Comparatror A match
This bit is used to select the method which clears the counter. Remember that the Compact TM
contains two comparators, Comparator A and Comparator P, either of which can be selected to
clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a
compare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero.
The TnCCLR bit is not used in the PWM Mode.
Compact Type TM Operating Modes
As the name of the mode suggests, after a comparison
is made, the TM output pin will change state. The TM
output pin condition however only changes state when
an TnAF interrupt request flag is generated after a com-
pare match occurs from Comparator A. The TnPF inter-
rupt request flag, generated from a compare match
occurs from Comparator P, will have no effect on the TM
output pin. The way in which the TM output pin changes
state are determined by the condition of the TnIO1 and
TnIO0 bits in the TMnC1 register. The TM output pin can
be selected using the TnIO1 and TnIO0 bits to go high,
to go low or to toggle from its present condition when a
compare match occurs from Comparator A. The initial
condition of the TM output pin, which is setup after the
TnON bit changes from low to high, is setup using the
TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero
then no pin change will take place.
The Compact Type TM can operate in one of three oper-
ating modes, Compare Match Output Mode, PWM
Mode or Timer/Counter Mode. The operating mode is
selected using the TnM1 and TnM0 bits in the TMnC1
register.
Compare Match Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1
register, should be set to ²00² respectively. In this mode
once the counter is enabled and running it can be
cleared by three methods. These are a counter over-
flow, a compare match from Comparator A and a com-
pare match from Comparator P. When the TnCCLR bit is
low, there are two ways in which the counter can be
cleared. One is when a compare match occurs from
Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both
TnAF and TnPF interrupt request flags for the Compara-
tor A and Comparator P respectively, will both be gener-
ated.
Timer/Counter Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 11 respectively. The
Timer/Counter Mode operates in an identical way to the
Compare Match Output Mode generating the same in-
terrupt flags. The exception is that in the Timer/Counter
Mode the TM output pin is not used. Therefore the
above description and Timing Diagrams for the Com-
pare Match Output Mode can be used to understand its
function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other
pin-shared function.
If the TnCCLR bit in the TMnC1 register is high then the
counter will be cleared when a compare match occurs
from Comparator A. However, here only the TnAF inter-
rupt request flag will be generated even if the value of
the CCRP bits is less than that of the CCRA registers.
Therefore when TnCCLR is high no TnPF interrupt re-
quest flag will be generated. If the CCRA bits are all
zero, the counter will overflow when its reaches its maxi-
mum 10-bit, 3FF Hex, value, however here the TnAF in-
terrupt request flag will not be generated.
Rev. 1.60
99
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter overflow
Counter Value
TnCCLR = 0; TnM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP=0
0x3FF
CCRP > 0
Counter
Restart
Resume
Pause
CCRP
CCRA
Stop
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
Output not affected by TnAF
flag. Remains High until reset
by TnON bit
Output Inverts
when TnPOL is high
Output pin set to
initial Level Low
if TnOC=0
Output Toggle with
TnAF flag
Output Pin
Reset to Initial value
Note TnIO [1:0] = 10
Active High Output select
Here TnIO [1:0] = 11
Toggle Output select
Output controlled by
other pin-shared function
Compare Match Output Mode -- TnCCLR = 0
Note: 1. With TnCCLR=0, a Comparator P match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
Rev. 1.60
100
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter Value
TnCCLR = 1; TnM [1:0] = 00
CCRA = 0
CCRA > 0 Counter cleared by CCRA value
Counter overflow
0x3FF
CCRA
CCRP
CCRA=0
Resume
Pause
Stop
Counter Restart
Time
TnON
TnPAU
TnPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnPF not
generated
Output does
not change
TM O/P Pin
Output not affected by
TnAF flag. Remains High
until reset by TnON bit
Output Inverts
when TnPOL is high
Output Toggle with
TnAF flag
Output pin set to
initial Level Low
if TnOC=0
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Note TnIO [1:0] = 10
Active High Output select
Here TnIO [1:0] = 11
Toggle Output select
Compare Match Output Mode -- TnCCLR = 1
Note: 1. With TnCCLR=1, a Comparator A match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
4. The TnPF flag is not generated when TnCCLR=1
Rev. 1.60
101
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
PWM Output Mode
while the other one is used to control the duty cycle.
Which register is used to control either frequency or duty
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 10 respectively. The PWM func-
tion within the TM is useful for applications which require
functions such as motor control, heating control, illumi-
nation control etc. By providing a signal of fixed fre-
quency but of varying duty cycle on the TM output pin, a
square wave AC waveform can be generated with vary-
ing equivalent DC RMS values.
cycle is determined using the TnDPX bit in the TMnC1
register. The PWM waveform frequency and duty cycle
can therefore be controlled by the values in the CCRA
and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP,
will be generated when a compare match occurs from
either Comparator A or Comparator P. The TnOC bit in
the TMnC1 register is used to select the required polar-
ity of the PWM waveform while the two TnIO1 and
TnIO0 bits are used to enable the PWM output or to
force the TM output pin to a fixed high or low level. The
TnPOL bit is used to reverse the polarity of the PWM
output waveform.
As both the period and duty cycle of the PWM waveform
can be controlled, the choice of generated waveform is
extremely flexible. In the PWM mode, the TnCCLR bit
has no effect on the PWM operation. Both of the CCRA
and CCRP registers are used to generate the PWM
waveform, one register is used to clear the internal
counter and thus control the PWM waveform frequency,
Counter Value
TnDPX = 0; TnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
TnON returns high
CCRP
Counter Stop if
TnON bit low
Pause
Resume
CCRA
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRA
PWM resumes
operation
Output controlled by
other pin-shared function
Output Inverts
when TnPOL = 1
PWM Period
set by CCRP
PWM Mode -- TnDPX = 0
Note: 1. Here TnDPX=0 -- Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.60
102
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
CTM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
Period
Duty
001b
128
010b
256
011b
384
100b
512
101b
640
110b
768
111b
896
000b
1024
CCRA
If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA =128,
The CTM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty
is 100%.
·
CTM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
Period
Duty
001b
010b
011b
100b
512
101b
640
110b
768
111b
896
000b
1024
CCRA
128
256
384
The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cy-
cle is defined by the CCRP register value.
Counter Value
TnDPX = 1; TnM [1:0] = 10
Counter cleared
by CCRA
Counter Reset when
TnON returns high
CCRA
Counter Stop if
TnON bit low
Pause
Resume
CCRP
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRP
PWM resumes
operation
Output controlled by
other pin-shared function
Output Inverts
when TnPOL = 1
PWM Period
set by CCRA
PWM Mode -- TnDPX = 1
Note: 1. Here TnDPX = 1 -- Counter cleared by CCRA
2. A counter clear sets the PWM Period
3. The internal PWM function continues even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.60
103
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Standard Type TM - STM
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Cap-
ture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external in-
put pin and can drive one or two external output pins.
CTM
Name
10-bit STM
¾
TM No.
TM Input Pin
TCK1
TM Output Pin
TP1_0, TP1_1
¾
HT66F20
HT66F30
HT66F40
HT66F50
HT66F60
1
¾
2
¾
16-bit STM
16-bit STM
16-bit STM
TCK2
TP2_0, TP2_1
TP2_0, TP2_1
TP2_0, TP2_1
2
TCK2
2
TCK2
Standard TM Operation
comparators. When these conditions occur, a TM inter-
rupt signal will also usually be generated. The Standard
Type TM can operate in a number of different opera-
tional modes, can be driven by different clock sources
including an input pin and can also control an output pin.
All operating setup conditions are selected using rele-
vant internal registers.
There are two sizes of Standard TMs, one is 10-bits
wide and the other is 16-bits wide. At the core is a 10 or
16-bit count-up counter which is driven by a user
selectable internal or external clock source. There are
also two internal comparators with the names, Com-
parator A and Comparator P. These comparators will
compare the value in the counter with CCRP and CCRA
registers. The CCRP comparator is 3 or 8-bits wide
whose value is compared the with highest 3 or 8 bits in
the counter while the CCRA is the ten or sixteen bits and
therefore compares all counter bits.
Standard Type TM Register Description
Overall operation of the Standard TM is controlled using
a series of registers. A read only register pair exists to
store the internal counter 10 or 16-bit value, while a
read/write register pair exists to store the internal 10 or
16-bit CCRA value. The remaining two registers are
control registers which setup the different operating and
control modes as well as the three or eight CCRP bits.
The only way of changing the value of the 10 or 16-bit
counter using the application program, is to clear the
counter by changing the TnON bit from low to high. The
counter will also be cleared automatically by a counter
overflow or a compare match with one of its associated
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Standard Type TM Block Diagram
Rev. 1.60
104
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Name
TM1C0
TM1C1
TM1DL
TM1DH
TM1AL
TM1AH
Bit7
T1PAU
T1M1
D7
Bit6
T1CK2
T1M0
D6
Bit5
T1CK1
T1IO1
D5
Bit4
T1CK0
T1IO0
D4
Bit3
T1ON
T1OC
D3
Bit2
T1RP2
T1POL
D2
Bit1
T1RP1
T1DPX
D1
Bit0
T1RP0
T1CCLR
D0
D9
D8
¾
¾
¾
¾
¾
¾
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
¾
¾
¾
¾
¾
¾
10-bit Standard TM Register List (for HT66F20)
Name
TM2C0
TM2C1
TM2DL
TM2DH
TM2AL
TM2AH
TM2RP
Bit7
T2PAU
T2M1
D7
Bit6
T2CK2
T2M0
D6
Bit5
T2CK1
T2IO1
D5
Bit4
T2CK0
T2IO0
D4
Bit3
T2ON
T2OC
D3
Bit2
¾
Bit1
¾
Bit0
¾
T2POL
D2
T2DPX
D1
T2CCLR
D0
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D8
D1
D0
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D8
D1
D0
16-bit Standard TM Register List (for HT66F40/HT66F50/HT66F60)
·
10-bit Standard TM Register List - HT66F20
¨
TM1C0 Register - 10-bit STM
Bit
Name
R/W
7
T1PAU
R/W
0
6
T1CK2
R/W
0
5
T1CK1
R/W
0
4
T1CK0
R/W
0
3
T1ON
R/W
0
2
T1RP2
R/W
0
1
T1RP1
R/W
0
0
T1RP0
R/W
0
POR
Bit 7
T1PAU: TM1 Counter Pause Control
0: run
1: pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores normal
counter operation. When in a Pause condition the TM will remain powered up and continue to
consume power. The counter will retain its residual value when this bit changes from low to high
and resume counting from this value when the bit changes to a low value again.
Bit 6~4
T1CK2~T1CK0: Select TM1 Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: undefined
110: TCK1 rising edge clock
111: TCK1 falling edge clock
These three bits are used to select the clock source for the TM. Selecting the Reserved clock
input will effectively disable the internal counter. The external pin clock source can be chosen to
be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and
f
TBC are other internal clocks, the details of which can be found in the oscillator section.
Rev. 1.60
105
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Bit 3
T1ON: TM1 Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to
run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting
and turn off the TM which will reduce its power consumption. When the bit changes state from
low to high the internal counter value will be reset to zero, however when the bit changes from
high to low, the internal counter will retain its residual value until the bit returns high again.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial
condition, as specified by the T1OC bit, when the T1ON bit changes from low to high.
Bit 2~0
T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7
Comparator P Match Period
000: 1024 TM1 clocks
001: 128 TM1 clocks
010: 256 TM1 clocks
011: 384 TM1 clocks
100: 512 TM1 clocks
101: 640 TM1 clocks
110: 768 TM1 clocks
111: 896 TM1 clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which are then
compared with the internal counter's highest three bits. The result of this comparison can be
selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to
zero ensures that a compare match with the CCRP values will reset the internal counter. As the
CCRP bits are only compared with the highest three counter bits, the compare values exist in 128
clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at
its maximum value.
¨
TM1C1 Register - 10-bit STM
Bit
Name
R/W
7
T1M1
R/W
0
6
T1M0
R/W
0
5
T1IO1
R/W
0
4
T1IO0
R/W
0
3
T1OC
R/W
0
2
T1POL
R/W
0
1
T1DPX
R/W
0
0
T1CCLR
R/W
POR
0
Bit 7~6
T1M1~T1M0: Select TM1 Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation the TM
should be switched off before any changes are made to the T1M1 and T1M0 bits. In the
Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
T1IO1~T1IO0: Select TP1_0, TP1_1 output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of TP1_0, TP1_1
01: Input capture at falling edge of TP1_0, TP1_1
10: Input capture at falling/rising edge of TP1_0, TP1_1
11: Input capture disabled
Timer/counter Mode:
Unused
Rev. 1.60
106
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
These two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the TM is
running.
In the Compare Match Output Mode, the T1IO1 and T1IO0 bits determine how the TM output
pin changes state when a compare match occurs from the Comparator A. The TM output pin can
be setup to switch high, switch low or to toggle its present state when a compare match occurs
from the Comparator A. When the bits are both zero, then no change will take place on the
output. The initial value of the TM output pin should be setup using the T1OC bit in the TM1C1
register. Note that the output level requested by the T1IO1 and T1IO0 bits must be different from
the initial value setup using the T1OC bit otherwise no change will occur on the TM output pin
when a compare match occurs. After the TM output pin changes state it can be reset to its initial
level by changing the level of the T1ON bit from low to high.
In the PWM Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state
when a certain compare match condition occurs. The PWM output function is modified by
changing these two bits. It is necessary to change the values of the T1IO1 and T1IO0 bits only
after the TM has been switched off. Unpredictable PWM outputs will occur if the T1IO1 and
T1IO0 bits are changed when the TM is running
Bit 3
T1OC: TP1_0, TP1_1 Output control bit
Compare Match Output Mode
0: initial low
1: initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it
determines the logic level of the TM output pin before a compare match occurs. In the PWM
Mode it determines if the PWM signal is active high or active low.
Bit 2
T1POL: TP1_0, TP1_1 Output polarity Control
0: non-invert
1: invert
This bit controls the polarity of the TP1_0 or TP1_1 output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the
Timer/Counter Mode.
Bit 1
Bit 0
T1DPX: TM1 PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and duty
control of the PWM waveform.
T1CCLR: Select TM1 Counter clear condition
0: TM1 Comparatror P match
1: TM1 Comparatror A match
This bit is used to select the method which clears the counter. Remember that the Standard
TM contains two comparators, Comparator A and Comparator P, either of which can be selected
to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a
compare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The
T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.
Rev. 1.60
107
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
TM1DL Register - 10-bit STM
Bit
Name
R/W
7
D7
R
6
D6
R
5
D5
R
4
D4
R
3
D3
R
2
D2
R
1
D1
R
0
D0
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
TM1DL: TM1 Counter Low Byte Register bit 7~bit 0
TM1 10-bit Counter bit 7~bit 0
¨
TM1DH Register - 10-bit STM
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R
0
D8
R
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
0
0
Bit 7~2
Bit 1~0
Unimplemented, read as ²0²
TM1DH: TM1 Counter High Byte Register bit 1~bit 0
TM1 10-bit Counter bit 9~bit 8
¨
TM1AL Register - 10-bit STM
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bit 7~0
TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0
TM1 10-bit CCRA bit 7~bit 0
¨
TM1AH Register - 10-bit STM
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~2
Bit 1~0
Unimplemented, read as ²0²
TM1AH: TM1 CCRA High Byte Register bit 1~bit 0
TM1 10-bit CCRA bit 9~bit 8
Rev. 1.60
108
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
16-bit Standard TM Register List - HT66F40/HT66F50/HT66F60
¨
TM2C0 Register - 16-bit STM
Bit
Name
R/W
7
T2PAU
R/W
0
6
T2CK2
R/W
0
5
T2CK1
R/W
0
4
T2CK0
R/W
0
3
T2ON
R/W
0
2
1
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7
T2PAU: TM2 Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores normal
counter operation. When in a Pause condition the TM will remain powered up and continue to
consume power. The counter will retain its residual value when this bit changes from low to high
and resume counting from this value when the bit changes to a low value again.
Bit 6~4
T2CK2, T2CK1, T2CK0: Select TM2 Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: undefined
110: TCK2 rising edge clock
111: TCK2 falling edge clock
These three bits are used to select the clock source for the TM. Selecting the Reserved clock
input will effectively disable the internal counter. The external pin clock source can be chosen to
be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and
f
TBC are other internal clocks, the details of which can be found in the oscillator section.
Bit 3
T2ON: TM2 Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to
run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting
and turn off the TM which will reduce its power consumption. When the bit changes state from
low to high the internal counter value will be reset to zero, however when the bit changes from
high to low, the internal counter will retain its residual value until the bit returns high again.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial
condition, as specified by the T2OC bit, when the T2ON bit changes from low to high.
Bit 2~0
Unimplemented, read as ²0²
Rev. 1.60
109
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
TM2C1 Register - 16-bit STM
Bit
Name
R/W
7
T2M1
R/W
0
6
T2M0
R/W
0
5
T2IO1
R/W
0
4
T2IO0
R/W
0
3
T2OC
R/W
0
2
T2POL
R/W
0
1
T2DPX
R/W
0
0
T2CCLR
R/W
POR
0
Bit 7~6
T2M1~T2M0: Select TM2 Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation the TM
should be switched off before any changes are made to the T2M1 and T2M0 bits. In the
Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
T2IO1~T2IO0: Select TP2_0, TP2_1 output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/ Single Pulse Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of TP2_0, TP2_1
01: Input capture at falling edge of TP2_0, TP2_1
10: Input capture at falling/rising edge of TP2_0, TP2_1
11: Input capture disabled
Timer/counter Mode:
Unused
These two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the TM
is running.
In the Compare Match Output Mode, the T2IO1 and T2IO0 bits determine how the TM output
pin changes state when a compare match occurs from the Comparator A. The TM output pin can
be setup to switch high, switch low or to toggle its present state when a compare match occurs
from the Comparator A. When the bits are both zero, then no change will take place on the
output. The initial value of the TM output pin should be setup using the T2OC bit in the TM2C1
register. Note that the output level requested by the T2IO1 and T2IO0 bits must be different from
the initial value setup using the T2OC bit otherwise no change will occur on the TM output pin
when a compare match occurs. After the TM output pin changes state it can be reset to its initial
level by changing the level of the T2ON bit from low to high.
In the PWM Mode, the T2IO1 and T2IO0 bits determine how the TM output pin changes state
when a certain compare match condition occurs. The PWM output function is modified by
changing these two bits. It is necessary to change the values of the T2IO1 and T2IO0 bits only
after the TM has been switched off. Unpredictable PWM outputs will occur if the T2IO1 and
T2IO0 bits are changed when the TM is running
Bit 3
T2OC: TP2_0, TP2_1 Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
Rev. 1.60
110
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it
determines the logic level of the TM output pin before a compare match occurs. In the PWM
Mode it determines if the PWM signal is active high or active low.
Bit 2
T2POL: TP2_0, TP2_1 Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TP2_0 or TP2_1 output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the
Timer/Counter Mode.
Bit 1
Bit 0
T2DPX: TM2 PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and duty
control of the PWM waveform.
T2CCLR: Select TM2 Counter clear condition
0: TM2 Comparator P match
1: TM2 Comparator A match
This bit is used to select the method which clears the counter. Remember that the Standard
TM contains two comparators, Comparator A and Comparator P, either of which can be selected
to clear the internal counter. With the T2CCLR bit set high, the counter will be cleared when a
compare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero.
The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.
¨
TM2DL Register - 16-bit STM
Bit
Name
R/W
7
D7
R
6
D6
R
5
D5
R
4
D4
R
3
D3
R
2
D2
R
1
D1
R
0
D0
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
TM2DL: TM2 Counter Low Byte Register bit 7~bit 0
TM2 16-bit Counter bit 7~bit 0
¨
TM2DH Register - 16-bit STM
Bit
Name
R/W
7
D15
R
6
D14
R
5
D13
R
4
D12
R
3
D11
R
2
D10
R
1
D9
R
0
D8
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
TM2DH: TM2 Counter High Byte Register bit 7~bit 0
TM2 16-bit Counter bit 15~bit 8
¨
TM2AL Register - 16-bit STM
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bit 7~0
TM2AL: TM2 CCRA Low Byte Register bit 7~bit 0
TM2 16-bit CCRA bit 7~bit 0
Rev. 1.60
111
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
TM2AH Register - 16-bit STM
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
D15
R/W
0
D14
R/W
0
D13
R/W
0
D12
R/W
0
D11
R/W
0
D10
R/W
0
POR
Bit 7~0
TM2AH: TM2 CCRA High Byte Register bit 7~bit 0
TM2 16-bit CCRA bit 15~bit 8
¨
TM2RP Register - 16-bit STM
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bit 7~0
TM2RP: TM2 CCRP Register bit 7 ~ bit 0
TM2 CCRP 8-bit register, compared with the TM2 Counter bit 15 ~ bit 8. Comparator P Match
Period
0: 65536 TM2 clocks
1~255: 256 x (1~255) TM2 clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then
compared with the internal counter's highest eight bits. The result of this comparison can be
selected to clear the internal counter if the T2CCLR bit is set to zero. Setting the T2CCLR bit to
zero ensures that a compare match with the CCRP values will reset the internal counter. As the
CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256
clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at
its maximum value.
Standard Type TM Operating Modes
from Comparator A. However, here only the TnAF inter-
rupt request flag will be generated even if the value of
the CCRP bits is less than that of the CCRA registers.
Therefore when TnCCLR is high no TnPF interrupt re-
quest flag will be generated. In the Compare Match Out-
put Mode, the CCRA can not be set to ²0².
The Standard Type TM can operate in one of five oper-
ating modes, Compare Match Output Mode, PWM Out-
put Mode, Single Pulse Output Mode, Capture Input
Mode or Timer/Counter Mode. The operating mode is
selected using the TnM1 and TnM0 bits in the TMnC1
register.
As the name of the mode suggests, after a comparison
is made, the TM output pin, will change state. The TM
output pin condition however only changes state when
an TnAF interrupt request flag is generated after a com-
pare match occurs from Comparator A. The TnPF inter-
rupt request flag, generated from a compare match
occurs from Comparator P, will have no effect on the TM
output pin. The way in which the TM output pin changes
state are determined by the condition of the TnIO1 and
TnIO0 bits in the TMnC1 register. The TM output pin can
be selected using the TnIO1 and TnIO0 bits to go high,
to go low or to toggle from its present condition when a
compare match occurs from Comparator A. The initial
condition of the TM output pin, which is setup after the
TnON bit changes from low to high, is setup using the
TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero
then no pin change will take place.
Compare Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1
register, should be set to 00 respectively. In this mode
once the counter is enabled and running it can be
cleared by three methods. These are a counter over-
flow, a compare match from Comparator A and a com-
pare match from Comparator P. When the TnCCLR bit is
low, there are two ways in which the counter can be
cleared. One is when a compare match from Compara-
tor P, the other is when the CCRP bits are all zero which
allows the counter to overflow. Here both TnAF and
TnPF interrupt request flags for Comparator Aand Com-
parator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the
counter will be cleared when a compare match occurs
Rev. 1.60
112
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter overflow
Counter Value
TnCCLR = 0; TnM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP=0
0x3FF
CCRP > 0
Counter
Restart
Resume
Pause
CCRP
CCRA
Stop
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
Output not affected by TnAF
flag. Remains High until reset
by TnON bit
Output Inverts
when TnPOL is high
Output pin set to
initial Level Low
if TnOC=0
Output Toggle with
TnAF flag
Output Pin
Reset to Initial value
Note TnIO [1:0] = 10
Active High Output select
Here TnIO [1:0] = 11
Toggle Output select
Output controlled by
other pin-shared function
Compare Match Output Mode -- TnCCLR = 0
Note: 1. With TnCCLR=0 a Comparator P match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to itsinitial state by a TnON bit rising edge
Rev. 1.60
113
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter Value
TnCCLR = 1; TnM [1:0] = 00
CCRA = 0
CCRA > 0 Counter cleared by CCRA value
Counter overflow
0x3FF
CCRA
CCRP
CCRA=0
Resume
Pause
Stop
Counter Restart
Time
TnON
TnPAU
TnPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnPF not
generated
Output does
not change
TM O/P Pin
Output not affected by
TnAF flag. Remains High
until reset by TnON bit
Output Inverts
when TnPOL is high
Output Toggle with
TnAF flag
Output pin set to
initial Level Low
if TnOC=0
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Note TnIO [1:0] = 10
Active High Output select
Here TnIO [1:0] = 11
Toggle Output select
Compare Match Output Mode -- TnCCLR = 1
Note: 1. With TnCCLR=1 a Comparator A match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
4. A TnPF flag is not generated when TnCCLR=1
Rev. 1.60
114
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Timer/Counter Mode
As both the period and duty cycle of the PWM waveform
can be controlled, the choice of generated waveform is
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 11 respectively. The
Timer/Counter Mode operates in an identical way to the
Compare Match Output Mode generating the same in-
terrupt flags. The exception is that in the Timer/Counter
Mode the TM output pin is not used. Therefore the
above description and Timing Diagrams for the Com-
pare Match Output Mode can be used to understand its
function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other
pin-shared function.
extremely flexible. In the PWM mode, the TnCCLR bit
has no effect as the PWM period. Both of the CCRA and
CCRP registers are used to generate the PWM wave-
form, one register is used to clear the internal counter
and thus control the PWM waveform frequency, while
the other one is used to control the duty cycle. Which
register is used to control either frequency or duty cycle
is determined using the TnDPX bit in the TMnC1 regis-
ter. The PWM waveform frequency and duty cycle can
therefore be controlled by the values in the CCRA and
CCRP registers.
PWM Output Mode
An interrupt flag, one for each of the CCRA and CCRP,
will be generated when a compare match occurs from
either Comparator A or Comparator P. The TnOC bit in
the TMnC1 register is used to select the required polar-
ity of the PWM waveform while the two TnIO1 and
TnIO0 bits are used to enable the PWM output or to
force the TM output pin to a fixed high or low level. The
TnPOL bit is used to reverse the polarity of the PWM
output waveform.
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 10 respectively and also the
TnIO1 and TnIO0 bits should be set to 10 respectively.
The PWM function within the TM is useful for applica-
tions which require functions such as motor control,
heating control, illumination control etc. By providing a
signal of fixed frequency but of varying duty cycle on the
TM output pin, a square wave AC waveform can be gen-
erated with varying equivalent DC RMS values.
·
10-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
Period
Duty
001b
128
010b
256
011b
384
100b
512
101b
640
110b
768
111b
896
000b
1024
CCRA
If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA =128,
The STM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty
is 100%.
·
10-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
Period
Duty
001b
010b
011b
100b
101b
640
110b
768
111b
896
000b
1024
CCRA
128
256
384
512
The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cy-
cle is defined by the CCRP register value.
Rev. 1.60
115
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
Period
Duty
1~255
0
65536
CCRP ´ 256
CCRA
If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 2 and CCRA =128,
The STM PWM output frequency = (fSYS/4) / (2´256) = fSYS/2048 = 7.8125 kHz, duty = 128 / (2´256) = 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty
is 100%.
·
16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
Period
Duty
1~255
0
CCRA
65536
CCRP ´ 256
The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cy-
cle is defined by the (CCRP x 256) except when the CCRP value is equal to 0.
Counter Value
TnDPX = 0; TnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
TnON returns high
CCRP
Counter Stop if
TnON bit low
Pause
Resume
CCRA
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRA
PWM resumes
operation
Output controlled by
other pin-shared function
Output Inverts
when TnPOL = 1
PWM Period
set by CCRP
PWM Mode -- TnDPX = 0
Note: 1. Here TnDPX=0 -- Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.60
116
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter Value
TnDPX = 1; TnM [1:0] = 10
Counter cleared
by CCRA
Counter Reset when
TnON returns high
CCRA
CCRP
Counter Stop if
TnON bit low
Pause
Resume
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM resumes
operation
PWM Duty Cycle
set by CCRP
Output controlled by
other pin-shared function
Output Inverts
when TnPOL = 1
PWM Period
set by CCRA
PWM Mode -- TnDPX = 1
Note: 1. Here TnDPX=1 -- Counter cleared by CCRA
2. A counter clear sets the PWM Period
3. The internal PWM function continues even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.60
117
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Single Pulse Mode
automatically change from low to high using the external
TCKn pin, which will in turn initiate the Single Pulse out-
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 10 respectively and also the
TnIO1 and TnIO0 bits should be set to 11 respectively.
The Single Pulse Output Mode, as the name suggests,
will generate a single shot pulse on the TM output pin.
put. When the TnON bit transitions to a high level, the
counter will start running and the pulse leading edge will
be generated. The TnON bit should remain high when
the pulse is in its active state. The generated pulse trail-
ing edge will be generated when the TnON bit is cleared
to zero, which can be implemented using the application
program or when a compare match occurs from Com-
parator A.
The trigger for the pulse output leading edge is a low to
high transition of the TnON bit, which can be imple-
mented using the application program. However in the
Single Pulse Mode, the TnON bit can also be made to
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Single Pulse Generation
Counter Value
TnM [1:0] = 10 ; TnIO [1:0] = 11
Counter stopped
by CCRA
Counter Reset when
TnON returns high
CCRA
CCRP
Counter Stops
by software
Resume
Pause
Time
TnON
Auto. set by
TCKn pin
Software
Trigger
Cleared by
CCRA match
Software
Trigger
Software
Clear
Software
Trigger
Software
Trigger
TCKn pin
TnPAU
TCKn pin
Trigger
TnPOL
No CCRP Interrupts
generated
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
Output Inverts
when TnPOL = 1
Pulse Width
set by CCRA
Single Pulse Mode
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse is triggered by the TCKn pin or by setting the TnON bit high
4. A TCKn pin active edge will automatically set the TnON bit high
5. In the Single Pulse Mode, TnIO [1:0] must be set to ²11² and can not be changed.
Rev. 1.60
118
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
However a compare match from Comparator A will also
be latched into the CCRA registers and a TM interrupt
generated. Irrespective of what events occur on the
TPn_0 or TPn_1 pin the counter will continue to free run
until the TnON bit changes from high to low. When a
CCRP compare match occurs the counter will reset
back to zero; in this way the CCRP value can be used to
control the maximum counter value. When a CCRP
compare match occurs from Comparator P, a TM inter-
rupt will also be generated. Counting the number of
overflow interrupt signals from the CCRP can be a use-
ful method in measuring long pulse widths. The TnIO1
and TnIO0 bits can select the active trigger edge on the
TPn_0 or TPn_1 pin to be a rising edge, falling edge or
both edge types. If the TnIO1 and TnIO0 bits are both
set high, then no capture operation will take place irre-
spective of what happens on the TPn_0 or TPn_1 pin,
however it must be noted that the counter will continue
to run.
automatically clear the TnON bit and thus generate the
Single Pulse output trailing edge. In this way the CCRA
value can be used to control the pulse width. A compare
match from Comparator A will also generate a TM inter-
rupt. The counter can only be reset back to zero when
the TnON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used.
The TnCCLR and TnDPX bits are not used in this Mode.
Capture Input Mode
To select this mode bits TnM1 and TnM0 in the TMnC1
register should be set to 01 respectively. This mode en-
ables external signals to capture and store the present
value of the internal counter and can therefore be used
for applications such as pulse width measurements.
The external signal is supplied on the TPn_0 or TPn_1
pin, whose active edge can be either a rising edge, a
falling edge or both rising and falling edges; the active
edge transition type is selected using the TnIO1 and
TnIO0 bits in the TMnC1 register. The counter is started
when the TnON bit changes from low to high which is ini-
tiated using the application program.
As the TPn_0 or TPn_1 pin is pin shared with other func-
tions, care must be taken if the TM is in the Input Cap-
ture Mode. This is because if the pin is setup as an
output, then any transitions on this pin may cause an in-
put capture operation to be executed. The TnCCLR and
TnDPX bits are not used in this Mode.
When the required edge transition appears on the
TPn_0 or TPn_1 pin the present value in the counter will
Counter Value
TnM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop Reset
CCRP
YY
Resume
Pause
XX
Time
TnON
TnPAU
Active
edge
Active
edge
Active edge
TM capture
pin TPn_x
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value
XX
YY
XX
YY
TnIO [1:0]
Value
00
Rising edge
01
Falling edge 10
Both edges
11
Disable Capture
Capture Input Mode
Note: 1.. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits
2. A TM Capture input pin active edge transfers the counter value to CCRA
3. TnCCLR bit not used
4. No output function -- TnOC and TnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
zero.
Rev. 1.60
119
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Enhanced Type TM - ETM
The Enhanced Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Cap-
ture Input, Single Pulse Output and PWM Output modes. The Enhanced TM can also be controlled with an external in-
put pin and can drive three or four external output pins.
CTM
Name
¾
TM No.
TM Input Pin
¾
TM Output Pin
¾
HT66F20
HT66F30
HT66F40
HT66F50
HT66F60
¾
1
10-bit ETM
10-bit ETM
10-bit ETM
10-bit ETM
TCK1
TP1A; TP1B_0, TP1B_1
TP1A, TP1B_0, TP1B_1, TP1B_2
TP1A, TP1B_0, TP1B_1, TP1B_2
TP1A, TP1B_0, TP1B_1, TP1B_2
1
TCK1
1
TCK1
1
TCK1
Enhanced TM Operation
The only way of changing the value of the 10-bit counter
using the application program, is to clear the counter by
changing the TnON bit from low to high. The counter will
also be cleared automatically by a counter overflow or a
compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will
also usually be generated. The Enhanced Type TM can
operate in a number of different operational modes, can
be driven by different clock sources including an input
pin and can also control output pins. All operating setup
conditions are selected using relevant internal registers.
At its core is a 10-bit count-up/count-down counter
which is driven by a user selectable internal or external
clock source. There are three internal comparators with
the names, Comparator A, Comparator B and Com-
parator P. These comparators will compare the value in
the counter with the CCRA, CCRB and CCRP registers.
The CCRP comparator is 3-bits wide whose value is
compared with the highest 3-bits in the counter while
CCRA and CCRB are 10-bits wide and therefore com-
pared with all counter bits.
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Enhanced Type TM Block Diagram
Rev. 1.60
120
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Enhanced Type TM Register Description
Overall operation of the Enhanced TM is controlled using a series of registers. A read only register pair exists to store
the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRB
value. The remaining three registers are control registers which setup the different operating and control modes as well
as the three CCRP bits.
Name
TM1C0
TM1C1
TM1C2
TM1DL
TM1DH
TM1AL
TM1AH
TM1BL
TM1BH
Bit7
T1PAU
T1AM1
T1BM1
D7
Bit6
T1CK2
T1AM0
T1BM0
D6
Bit5
T1CK1
T1AIO1
T1BIO1
D5
Bit4
T1CK0
T1AIO0
T1BIO0
D4
Bit3
T1ON
T1AOC
T1BOC
D3
Bit2
T1RP2
T1APOL
T1BPOL
D2
Bit1
T1RP1
T1CDN
T1PWM1
D1
Bit0
T1RP0
T1CCLR
T1PWM0
D0
D9
D8
¾
¾
¾
¾
¾
¾
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
¾
¾
¾
¾
¾
¾
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
¾
¾
¾
¾
¾
¾
10-bit Enhanced TM Register List (if ETM is TM1)
·
10-bit Enhanced TM Register List - HT66F30/HT66F40/HT66F50/HT66F60
¨
TM1C0 Register - 10-bit ETM
Bit
Name
R/W
7
T1PAU
R/W
0
6
T1CK2
R/W
0
5
T1CK1
R/W
0
4
T1CK0
R/W
0
3
T1ON
R/W
0
2
T1RP2
R/W
0
1
T1RP1
R/W
0
0
T1RP0
R/W
0
POR
Bit 7
T1PAU: TM1 Counter Pause Control
0: run
1: pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores normal
counter operation. When in a Pause condition the TM will remain powered up and continue to
consume power. The counter will retain its residual value when this bit changes from low to high
and resume counting from this value when the bit changes to a low value again.
Bit 6~4
T1CK2~T1CK0: Select TM1 Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: Undefined
110: TCK1 rising edge clock
111: TCK1 falling edge clock
These three bits are used to select the clock source for the TM. Selecting the Reserved clock
input will effectively disable the internal counter. The external pin clock source can be chosen to
be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and
f
TBC are other internal clocks, the details of which can be found in the oscillator section.
Bit 3
T1ON: TM1 Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to
run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting
and turn off the TM which will reduce its power consumption. When the bit changes state from
low to high the internal counter value will be reset to zero, however when the bit changes from
high to low, the internal counter will retain its residual value until the bit returns high again.
Rev. 1.60
121
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial
condition, as specified by the T1OC bit, when the T1ON bit changes from low to high.
Bit 2~0
T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7
Comparator P Match Period
000: 1024 TM1 clocks
001: 128 TM1 clocks
010: 256 TM1 clocks
011: 384 TM1 clocks
100: 512 TM1 clocks
101: 640 TM1 clocks
110: 768 TM1 clocks
111: 896 TM1 clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which are then
compared with the internal counter¢s highest three bits. The result of this comparison can be
selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to
zero ensures that a compare match with the CCRP values will reset the internal counter. As the
CCRP bits are only compared with the highest three counter bits, the compare values exist in 128
clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at
its maximum value.
¨
TM1C1 Register - 10-bit ETM
Bit
Name
R/W
7
T1AM1
R/W
0
6
T1AM0
R/W
0
5
T1AIO1
R/W
0
4
T1AIO0
R/W
0
3
T1AOC
R/W
0
2
T1APOL
R/W
0
1
0
T1CCLR
R/W
T1CDN
R
0
POR
0
Bit 7~6
T1AM1~T1AM0: Select TM1 CCRA Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation the TM
should be switched off before any changes are made to the T1AM1 and T1AM0 bits. In the
Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
T1AIO1~T1AIO0: Select TP1A output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/ Single Pulse Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of TP1A
01: Input capture at falling edge of TP1A
10: Input capture at falling/rising edge of TP1A
11: Input capture disabled
Timer/counter Mode
Unused
These two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the TM is
running.
Rev. 1.60
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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
In the Compare Match Output Mode, the T1AIO1 and T1AIO0 bits determine how the TM
output pin changes state when a compare match occurs from the Comparator A. The TM output
pin can be setup to switch high, switch low or to toggle its present state when a compare match
occurs from the Comparator A. When the bits are both zero, then no change will take place on
the output. The initial value of the TM output pin should be setup using the T1AOC bit in the
TM1C1 register. Note that the output level requested by the T1AIO1 and T1AIO0 bits must be
different from the initial value setup using the T1AOC bit otherwise no change will occur on the
TM output pin when a compare match occurs. After the TM output pin changes state it can be
reset to its initial level by changing the level of the T1ON bit from low to high.
In the PWM Mode, the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state
when a certain compare match condition occurs. The PWM output function is modified by
changing these two bits. It is necessary to change the values of the T1AIO1 and T1AIO0 bits
only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1AIO1
and T1AIO0 bits are changed when the TM is running
Bit 3
T1AOC: TP1A Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it
determines the logic level of the TM output pin before a compare match occurs. In the PWM
Mode it determines if the PWM signal is active high or active low.
Bit 2
T1APOL: TP1A Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TP1A output pin. When the bit is set high the TM output pin
will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the
Timer/Counter Mode.
Bit 1
Bit 0
T1CDN: TM1 Counter count up or down flag
0: Count up
1: Count down
T1CCLR: Select TM1 Counter clear condition
0: TM1 Comparator P match
1: TM1 Comparator A match
This bit is used to select the method which clears the counter. Remember that the Enhanced
TM contains three comparators, Comparator A, Comparator B and Comparator P, but only
Comparator A or Comparator Pan be selected to clear the internal counter. With the T1CCLR bit
set high, the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from the
Comparator P or with a counter overflow. A counter overflow clearing method can only be
implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the
Single Pulse or Input Capture Mode.
Rev. 1.60
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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
TM1C2 Register - 10-bit ETM
Bit
Name
R/W
7
T1BM1
R/W
0
6
T1BM0
R/W
0
5
T1BIO1
R/W
0
4
T1BIO0
R/W
0
3
T1BOC
R/W
0
2
T1BPOL
R/W
0
1
0
T1PWM1 T1PWM0
R
0
R/W
0
POR
Bit 7~6
T1BM1~T1BM0: Select TM1 CCRB Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter mode
These bits setup the required operating mode for the TM. To ensure reliable operation the TM
should be switched off before any changes are made to the T1BM1 and T1BM0 bits. In the
Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
T1BIO1~T1BIO0: Select TP1B_0, TP1B_1, TP1B_2 output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of TP1B_0, TP1B_1, TP1B_2
01: Input capture at falling edge of TP1B_0, TP1B_1, TP1B_2
10: Input capture at falling/rising edge of TP1B_0, TP1B_1, TP1B_2
11: Input capture disabled
Timer/counter Mode
Unused
These two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the
TM is running.
In the Compare Match Output Mode, the T1BIO1 and T1BIO0 bits determine how the TM
output pin changes state when a compare match occurs from the Comparator A. The TM output
pin can be setup to switch high, switch low or to toggle its present state when a compare match
occurs from the Comparator A. When the bits are both zero, then no change will take place on
the output. The initial value of the TM output pin should be setup using the T1BOC bit in the
TM1C2 register. Note that the output level requested by the T1BIO1 and T1BIO0 bits must be
different from the initial value setup using the T1BOC bit otherwise no change will occur on the
TM output pin when a compare match occurs. After the TM output pin changes state it can be
reset to its initial level by changing the level of the T1ON bit from low to high.
In the PWM Mode, the T1BIO1 and T1BIO0 bits determine how the TM output pin changes
state when a certain compare match condition occurs. The PWM output function is modified by
changing these two bits. It is necessary to change the values of the T1BIO1 and T1BIO0 bits only
after the TM has been switched off. Unpredictable PWM outputs will occur if the T1BIO1 and
T1BIO0 bits are changed when the TM is running
Bit 3
T1BOC: TP1B_0, TP1B_1, TP1B_2 Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
Rev. 1.60
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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it
determines the logic level of the TM output pin before a compare match occurs. In the PWM
Mode it determines if the PWM signal is active high or active low.
Bit 2
T1BPOL: TP1B_0, TP1B_1, TB1B_2 Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TP1B_0, TP1B_1, TP1B_2 output pin. When the bit is set
high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
Bit 1~0
T1PWM1~T1PWM0: Select PWM Mode
00: Edge aligned
01: Centre aligned, compare match on count up
10: Centre aligned, compare match on count down
11: Centre aligned, compare match on count up or down
¨
TM1DL Register - 10-bit ETM
Bit
Name
R/W
7
D7
R
6
D6
R
5
D5
R
4
D4
R
3
D3
R
2
D2
R
1
D1
R
0
D0
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
TM1DL: TM1 Counter Low Byte Register bit 7~bit 0
TM1 10-bit Counter bit 7~bit 0
¨
TM1DH Register - 10-bit ETM
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R
0
D8
R
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
0
0
Bit 7~2
Bit 1~0
Unimplemented, read as ²0²
TM1DH: TM1 Counter High Byte Register bit 1~bit 0
TM1 10-bit Counter bit 9~bit 8
¨
TM1AL Register - 10-bit ETM
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bit 7~0
TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0
TM1 10-bit CCRA bit 7~bit 0
¨
TM1AH Register - 10-bit ETM
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~2
Bit 1~0
Unimplemented, read as ²0²
TM1AH: TM1 CCRA High Byte Register bit 1~bit 0
TM1 10-bit CCRA bit 9~bit 8
Rev. 1.60
125
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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
TM1BL Register - 10-bit ETM
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
POR
Bit 7 ~ 0
TM1BL: TM1 CCRB Low Byte Register bit 7~bit 0
TM1 10-bit CCRB bit 7~bit 0
¨
TM1BH Register - 10-bit ETM
Bit
Name
R/W
7
6
5
4
3
2
1
D9
R/W
0
0
D8
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~2
Bit 1~0
Unimplemented, read as ²0²
TM1BH: TM1 CCRB High Byte Register bit 1~bit 0
TM1 10-bit CCRB bit 9 ~ bit 8
Enhanced Type TM Operating Modes
The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output
Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using
the TnAM1 and TnAM0 bits in the TMnC1, and the TnBM1 and TnBM0 bits in the TMnC2 register.
CCRA Com-
CCRA
CCRA Single CCRA Input
CCRA PWM
ETM Operating Mode
pare Match Timer/Coun-
Pulse Output
Mode
Capture
Mode
Output Mode
Output Mode
ter Mode
CCRB Compare Match Output Mode
CCRB Timer/Counter Mode
CCRB PWM Output Mode
Ö
¾
Ö
¾
¾
Ö
¾
¾
¾
Ö
¾
¾
¾
¾
Ö
¾
¾
¾
¾
¾
¾
¾
CCRB Single Pulse Output Mode
CCRB Input Capture Mode
¾
¾
¾
²Ö²: permitted; ²¾² : not permitted
Compare Output Mode
If the TnCCLR bit in the TMnC1 register is high then the
counter will be cleared when a compare match occurs
from Comparator A. However, here only the TnAF inter-
rupt request flag will be generated even if the value of
the CCRP bits is less than that of the CCRA registers.
Therefore when TnCCLR is high no TnPF interrupt re-
quest flag will be generated.
To select this mode, bits TnAM1, TnAM0 and TnBM1,
TnBM0 in the TMnC1/TMnC2 registers should be all
cleared to zero. In this mode once the counter is en-
abled and running it can be cleared by three methods.
These are a counter overflow, a compare match from
Comparator A and a compare match from Comparator
P. When the TnCCLR bit is low, there are two ways in
which the counter can be cleared. One is when a com-
pare match occurs from Comparator P, the other is when
the CCRP bits are all zero which allows the counter to
overflow. Here both the TnAF and TnPF interrupt re-
quest flags for Comparator A and Comparator P respec-
tively, will both be generated.
Rev. 1.60
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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
As the name of the mode suggests, after a comparison
be selected using the TnAIO1, TnAIO0 bits (for the
TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0,
TPnB_1 or TPnB_2 pins) to go high, to go low or to tog-
gle from its present condition when a compare match
occurs from Comparator A or a compare match occurs
from Comparator B. The initial condition of the TM out-
put pin, which is setup after the TnON bit changes from
low to high, is setup using the TnAOC or TnBOC bit for
TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note
that if the TnAIO1,TnAIO0 and TnBIO1, TnBIO0 bits are
zero then no pin change will take place.
is made, the TM output pin, will change state. The TM
output pin condition however only changes state when
an TnAF or TnBF interrupt request flag is generated af-
ter a compare match occurs from Comparator Aor Com-
parator B. The TnPF interrupt request flag, generated
from a compare match from Comparator P, will have no
effect on the TM output pin. The way in which the TM
output pin changes state is determined by the condition
of the TnAIO1 and TnAIO0 bits in the TMnC1 register for
ETM CCRA, and the TnBIO1 and TnBIO0 bits in the
TMnC2 register for ETM CCRB. The TM output pin can
Counter overflow
CCRP=0
Counter Value
TnCCLR = 0; TnAM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
0x3FF
CCRP > 0
Counter
Restart
Resume
CCRP
CCRA
Pause
Stop
Time
TnON
TnPAU
TnAPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TPnA O/P
Pin
Output not affected by TnAF
flag. Remains High until reset
by TnON bit
Output Inverts
when TnAPOL is high
Output pin set to
initial Level Low
if TnAOC=0
Output Toggle with
TnAF flag
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Note TnAIO [1:0] = 10
Active High Output select
Here TnAIO [1:0] = 11
Toggle Output select
ETM CCRA Compare Match Output Mode -- TnCCLR = 0
Note: 1. With TnCCLR=0 a Comparator P match will clear the counter
2. The TPnA output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
Rev. 1.60
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September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter overflow
Counter Value
TnCCLR = 0; TnBM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP=0
0x3FF
CCRP > 0
Counter
Restart
Resume
Pause
CCRP
CCRB
Stop
Time
TnON
TnPAU
TnBPOL
CCRP Int.
Flag TnPF
CCRB Int.
Flag TnBF
TPnB O/P
Pin
Output not affected by TnBF
flag. Remains High until reset
by TnON bit
Output Inverts
when TnBPOL is high
Output pin set to
initial Level Low
if TnBOC=0
Output Toggle with
TnBF flag
Output Pin
Reset to Initial value
Note TnBIO [1:0] = 10
Active High Output select
Here TnBIO [1:0] = 11
Toggle Output select
Output controlled by
other pin-shared function
ETM CCRB Compare Match Output Mode -- TnCCLR = 0
Note: 1. With TnCCLR=0 a Comparator P match will clear the counter
2. The TPnB output pin is controlled only by the TnBF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
Rev. 1.60
128
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter Value
TnCCLR = 1; TnAM [1:0] = 00
CCRA = 0
CCRA > 0 Counter cleared by CCRA value
Counter overflow
0x3FF
CCRA
CCRP
CCRA=0
Resume
Pause
Stop Counter Restart
Time
TnON
TnPAU
TnAPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnPF not
generated
Output does
not change
TPnA O/P
Pin
Output not affected by
TnAF flag. Remains High
until reset by TnON bit
Output Inverts
when TnAPOL is high
Output pin set to
initial Level Low
if TnAOC=0
Output Toggle with
TnAF flag
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Note TnAIO [1:0] = 10
Active High Output select
Here TnAIO [1:0] = 11
Toggle Output select
ETM CCRA Compare Match Output Mode -- TnCCLR = 1
Note: 1. With TnCCLR=1 a Comparator A match will clear the counter
2. The TPnA output pin is controlled only by the TnAF flag
3. The TPnA output pin is reset to its initial state by a TnON bit rising edge
4. The TnPF flag is not generated when TnCCLR=1
Rev. 1.60
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September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter Value
TnCCLR = 1; TnBM [1:0] = 00
CCRA = 0
CCRA > 0 Counter cleared by CCRA value
Counter overflow
0x3FF
CCRA
CCRB
CCRA=0
Resume
Pause
Stop Counter Restart
Time
TnON
TnPAU
TnBPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
TPnB O/P
Pin
Output not affected by
TnBF flag. Remains High
until reset by TnON bit
Output Toggle with
TnBF flag
Output Inverts
when TnBPOL is high
Output pin set to
initial Level Low
if TnBOC=0
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Note TnBIO [1:0] = 10
Active High Output select
Here TnBIO [1:0] = 11
Toggle Output select
ETM CCRB Compare Match Output Mode -- TnCCLR = 1
Note: 1. With TnCCLR=1 a Comparator A match will clear the counter
2. The TPnB output pin is controlled only by the TnBF flag
3. The TPnB output pin is reset to its initial state by a TnON bit rising edge
4. The TnPF flag is not generated when TnCCLR=1
Rev. 1.60
130
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Timer/Counter Mode
can be finely controlled using the CCRA registers. In this
case the CCRB registers are used to set the PWM duty
To select this mode, bits TnAM1, TnAM0 and TnBM1,
TnBM0 in the TMnC1 and TMnC2 register should all be
set high. The Timer/Counter Mode operates in an identi-
cal way to the Compare Match Output Mode generating
the same interrupt flags. The exception is that in the
Timer/Counter Mode the TM output pin is not used.
Therefore the above description and Timing Diagrams
for the Compare Match Output Mode can be used to un-
derstand its function. As the TM output pin is not used in
this mode, the pin can be used as a normal I/O pin or
other pin-shared function.
value (for TPnB output pins). The CCRP bits are not used
and TPnA output pin is not used. The PWM output can
only be generated on the TPnB output pins. With the
TnCCLR bit cleared to zero, the PWM period is set using
one of the eight values of the three CCRP bits, in multi-
ples of 128. Now both CCRA and CCRB registers can be
used to setup different duty cycle values to provide dual
PWM outputs on their relative TPnA and TPnB pins.
The TnPWM1 and TnPWM0 bits determine the PWM
alignment type, which can be either edge or centre type.
In edge alignment, the leading edge of the PWM signals
will all be generated concurrently when the counter is re-
set to zero. With all power currents switching on at the
same time, this may give rise to problems in higher
power applications. In centre alignment the centre of the
PWM active signals will occur sequentially, thus reduc-
ing the level of simultaneous power switching currents.
PWM Output Mode
To select this mode, the required bit pairs, TnAM1,
TnAM0 and TnBM1, TnBM0 should be set to 10 respec-
tively and also the TnAIO1, TnAIO0 and TnBIO1,
TnBIO0 bits should be set to 10 respectively. The PWM
function within the TM is useful for applications which re-
quire functions such as motor control, heating control, il-
lumination control etc. By providing a signal of fixed
frequency but of varying duty cycle on the TM output pin,
a square wave AC waveform can be generated with
varying equivalent DC RMS values.
Interrupt flags, one for each of the CCRA, CCRB and
CCRP, will be generated when a compare match occurs
from either the Comparator A, Comparator B or Com-
parator P. The TnAOC and TnBOC bits in the TMnC1 and
TMnC2 register are used to select the required polarity of
the PWM waveform while the two TnAIO1, TnAIO0 and
TnBIO1, TnBIO0 bits pairs are used to enable the PWM
output or to force the TM output pin to a fixed high or low
level. The TnAPOL and TnBPOL bit are used to reverse
the polarity of the PWM output waveform.
As both the period and duty cycle of the PWM waveform
can be controlled, the choice of generated waveform is
extremely flexible. In the PWM mode, the TnCCLR bit is
used to determine in which way the PWM period is con-
trolled. With the TnCCLR bit set high, the PWM period
·
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0
CCRP
Period
A Duty
B Duty
001b
010b
011b
100b
101b
110b
111b
000b
128
256
384
512
640
768
896
1024
CCRA
CCRB
If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 100b, CCRA = 128 and CCRB = 256,
The TP1A PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%.
The TP1B_n PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125kHz, duty = 256/512 = 50%.
If the Duty value defined by CCRAor CCRB register is equal to or greater than the Period value, then the PWM output
duty is 100%.
·
·
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1
CCRA
Period
B Duty
1
2
3
......
511
512
......
1021
1022
1023
1
2
3
......
511
512
......
1021
1022
1023
CCRB
ETM, PWM Mode, Center-aligned Mode, TnCCLR=0
CCRP
Period
A Duty
B Duty
001b
010b
011b
100b
101b
1280
110b
111b
1792
000b
256
512
768
1024
1536
2046
(CCRA´2)-1
(CCRB´2)-1
Rev. 1.60
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September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
ETM, PWM Mode, Center-aligned Mode, TnCCLR=1
CCRA
Period
B Duty
1
2
3
511
512
1021
1022
1023
2
4
6
1022
1024
2042
2044
2046
(CCRB´2)-1
Counter Value
TnCCLR = 0;
TnAM [1:0] = 10, TnBM [1:0] = 10;
TnPWM [1:0] = 00
Counter Cleared by CCRP
CCRP
CCRA
CCRB
Counter
Restart
Resume
Stop
Pause
Time
TnON
TnPAU
TnAPOL
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
TPnA Pin
(TnAOC=1)
Duty Cycle
set by CCRA
Duty Cycle
set by CCRA
Duty Cycle
set by CCRA
Output Inverts
when TnAPOL
is high
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Duty Cycle
set by CCRB
Output controlled by Output Pin
other pin-shared function Reset to Initial value
PWM Period set by CCRP
ETM PWM Mode -- Edge Aligned
Note: 1. Here TnCCLR=0 therefore CCRP clears counter and determines the PWM period
2. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01
3. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty
Rev. 1.60
132
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter Value
CCRA
TnCCLR = 1; TnBM [1:0] = 10;
TnPWM [1:0] = 00
Counter Cleared by CCRA
Counter
Restart
Resume
Stop
Pause
CCRB
Time
TnON
TnPAU
TnBPOL
CCRP Int.
Flag TnPF
CCRB Int.
Flag TnBF
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Duty Cycle
set by CCRB
Output Pin
Output Inverts
when TnBPOL
is high
Reset to
Initial value
Output controlled by
other pin-shared function
PWM Period set by CCRA
ETM PWM Mode -- Edge Aligned
Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period
2. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01
3. The CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty
4. Here the TM pin control register should not enable the TPnA pin as a TM output pin.
Rev. 1.60
133
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter Value
TnCCLR = 0;
TnAM [1:0] = 10, TnBM [1:0] = 10;
TnPWM [1:0] = 11
CCRP
CCRA
CCRB
Counter
Restart
Stop
Resume
Pause
Time
TnON
TnPAU
TnAPOL
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
TPnA Pin
(TnAOC=1)
Duty Cycle set by CCRA
Output Inverts
when TnAPOL
is high
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Duty Cycle set by CCRB
PWM Period set by CCRP
Output controlled by
Other pin-shared function
Output Pin
Reset to Initial value
ETM PWM Mode -- Centre Aligned
Note: 1. Here TnCCLR=0 therefore CCRP clears the counter and determines the PWM period
2. TnPWM [1:0] =11 therefore the PWM is centre aligned
3. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01
4. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty
5. CCRP will generate an interrupt request when the counter decrements to its zero value
Rev. 1.60
134
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter Value
CCRA
TnCCLR = 1; TnBM [1:0] = 10;
TnPWM [1:0] = 11
Counter
Restart
Stop
Resume
Pause
CCRB
Time
TnON
TnPAU
TnBPOL
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Output controlled
Output Inverts
Duty Cycle set by CCRB
PWM Period set by CCRA
by other pin-shared
function
when TnBPOL is high
Output Pin
Reset to Initial value
ETM PWM Mode -- Centre Aligned
Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period
2. TnPWM [1:0] =11 therefore the PWM is centre aligned
3. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01
4. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty
5. CCRP will generate an interrupt request when the counter decrements to its zero value
Rev. 1.60
135
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Single Pulse Output Mode
TPnA will be generated. The TnON bit should remain
high when the pulse is in its active state. The generated
To select this mode, the required bit pairs, TnAM1,
TnAM0 and TnBM1, TnBM0 should be set to 10 respec-
tively and also the corresponding TnAIO1, TnAIO0 and
TnBIO1, TnBIO0 bits should be set to 11 respectively.
The Single Pulse Output Mode, as the name suggests,
will generate a single shot pulse on the TM output pin.
pulse trailing edge of TPnA and TPnB will be generated
when the TnON bit is cleared to zero, which can be im-
plemented using the application program or when a
compare match occurs from Comparator A.
However a compare match from Comparator A will also
automatically clear the TnON bit and thus generate the
Single Pulse output trailing edge of TPnA and TPnB. In
this way the CCRA value can be used to control the
pulse width of TPnA. The CCRA-CCRB value can be
used to control the pulse width of TPnB. A compare
match from Comparator A and Comparator B will also
generate TM interrupts. The counter can only be reset
back to zero when the TnON bit changes from low to
high when the counter restarts. In the Single Pulse
Mode CCRP is not used. The TnCCLR bit is also not
used.
The trigger for the pulse TPnA output leading edge is a
low to high transition of the TnON bit, which can be im-
plemented using the application program. The trigger
for the pulse TPnB output leading edge is a compare
match from Comparator B, which can be implemented
using the application program. However in the Single
Pulse Mode, the TnON bit can also be made to automat-
ically change from low to high using the external TCKn
pin, which will in turn initiate the Single Pulse output of
TPnA. When the TnON bit transitions to a high level, the
counter will start running and the pulse leading edge of
Single Pulse Generation
Rev. 1.60
136
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Counter Value
TnAM [1:0] = 10, TnBM [1:0] = 10;
TnAIO [1:0] = 11, TnBIO [1:0] = 11
Counter stopped
by CCRA
Counter Reset
when TnON
returns high
CCRA
CCRB
Counter Stops
by software
Resume
Pause
Time
TnON
Auto. set by
TCKn pin
Software
Trigger
Cleared by
CCRA match
Software
Trigger
Software
Clear
Software
Trigger
Software
Trigger
TCKn pin
TnPAU
TCKn pin
Trigger
TnAPOL
TnBPOL
CCRB Int.
Flag TnBF
CCRA Int.
Flag TnAF
TPnA Pin
(TnAOC=1)
Pulse Width
set by CCRA
TPnA Pin
(TnAOC=0)
Output Inverts
when TnAPOL=1
TPnB Pin
(TnBOC=1)
TPnB Pin
(TnBOC=0)
Pulse Width set
by (CCRA-CCRB)
Output Inverts
when TnBPOL=1
ETM -- Single Pulse Mode
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse is triggered by the TCKn pin or by setting the TnON bit high
4. A TCKn pin active edge will automatically set the TnON bit high
5. In the Single Pulse Mode, TnAIO [1:0] and TnBIO [1:0] must be set to ²11² and can not be changed.
Rev. 1.60
137
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Capture Input Mode
zero; in this way the CCRP value can be used to control
the maximum counter value. When a CCRP compare
To select this mode bits TnAM1, TnAM0 and TnBM1,
TnBM0 in the TMnC1 and TMnC2 registers should be
set to 01 respectively. This mode enables external sig-
nals to capture and store the present value of the inter-
nal counter and can therefore be used for applications
such as pulse width measurements. The external signal
is supplied on the TPnA and TPnB_0, TPnB_1, TPnB_2
pins, whose active edge can be either a rising edge, a
falling edge or both rising and falling edges; the active
edge transition type is selected using the TnAIO1,
TnAIO0 and TnBIO1, TnBIO0 bits in the TMnC1 and
TMnC2 registers. The counter is started when the TnON
bit changes from low to high which is initiated using the
application program.
match occurs from Comparator P, a TM interrupt will
also be generated. Counting the number of overflow in-
terrupt signals from the CCRP can be a useful method in
measuring long pulse widths. The TnAIO1, TnAIO0 and
TnBIO1, TnBIO0 bits can select the active trigger edge
on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins to be
a rising edge, falling edge or both edge types. If the
TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits are both set
high, then no capture operation will take place irrespec-
tive of what happens on the TPnA and TPnB_0,
TPnB_1, TPnB_2 pins, however it must be noted that
the counter will continue to run.
As the TPnA and TPnB_0, TPnB_1, TPnB_2 pins are
pin shared with other functions, care must be taken if the
TM is in the Capture Input Mode. This is because if the
pin is setup as an output, then any transitions on this pin
may cause an input capture operation to be executed.
The TnCCLR, TnAOC, TnBOC, TnAPOL and TnBPOL
bits are not used in this mode.
When the required edge transition appears on the TPnA
and TPnB_0, TPnB_1, TPnB_2 pins the present value
in the counter will be latched into the CCRA and CCRB
registers and a TM interrupt generated. Irrespective of
what events occur on the TPnA and TPnB_0, TPnB_1,
TPnB_2 pins the counter will continue to free run until
the TnON bit changes from high to low. When a CCRP
compare match occurs the counter will reset back to
Counter Value
TnAM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop Reset
CCRP
YY
Resume
Pause
XX
Time
TnON
TnPAU
Active
edge
Active
edge
Active edge
TM capture
pin TPnA
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value
XX
YY
XX
YY
TnAIO [1:0]
Value
00
Rising edge
01
Falling edge 10
Both edges
11
Disable Capture
ETM CCRA Capture Input Mode
Note: 1. TnAM [1:0] = 01 and active edge set by the TnAIO [1:0] bits
2. The TM Capture input pin active edge transfers he counter value to CCRA
3. TnCCLR bit not used
4. No output function -- TnAOC and TnAPOL bits not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal
to zero.
Rev. 1.60
138
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
TnBM1, TnBM0 = 01
Counter
Value
Counter
overflow
Counter
CCRP
YY
Stop
Reset
Pause Resume
XX
Time
TnON bit
TnPAU bit
Active
edges
Active
edge
Active
edge
TM Capture Pin
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
CCRB
Value
XX
YY
XX
YY
TnBIO1, TnBIO0
Value
00 - Rising edge
01 - Falling edge
10 - Both edges
11 - Disable Capture
ETM CCRB Capture Input Mode
Note: 1. TnBM [1:0] = 01 and active edge set by the TnBIO [1:0] bits
2. The TM Capture input pin active edge transfers the counter value to CCRB
3. TnCCLR bit not used
4. No output function -- TnBOC and TnBPOL bits not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP
is equal to zero.
Rev. 1.60
139
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Analog to Digital Converter
The need to interface to real world analog signals is a
common requirement for many electronic systems.
However, to properly process these signals by a
microcontroller, they must first be converted into digital
signals by A/D converters. By integrating the A/D con-
version electronic circuitry into the microcontroller, the
need for external components is reduced significantly
with the corresponding follow-on benefits of lower costs
and reduced component space requirements.
Input
A/D Channel
Select Bits
Input
Pins
Part No.
Channels
HT66F20
HT66F30
HT66F40
HT66F50
ACS4,
8
AN0~AN7
ACS2~ACS0
ACS4,
HT66F60
12
AN0~AN11
ACS3~ACS0
A/D Overview
The accompanying block diagram shows the overall in-
ternal structure of the A/D converter, together with its as-
sociated registers.
The devices contains a multi-channel analog to digital
converter which can directly interface to external analog
signals, such as that from sensors or other control sig-
nals and convert these signals directly into either a
12-bit digital value.
A/D Converter Register Description
Overall operation of the A/D converter is controlled us-
ing six registers. A read only register pair exists to store
the ADC data 12-bit value. The remaining three or four
registers are control registers which setup the operating
and control function of the A/D converter.
Bit
Register
Name
7
D3
6
D2
5
D1
4
D0
3
2
¾
1
¾
0
¾
ADRL(ADRFS=0)
ADRL(ADRFS=1)
ADRH(ADRFS=0)
ADRH(ADRFS=1)
ADCR0
¾
D7
D6
D5
D4
D3
D7
D11
D2
D1
D0
D11
¾
D10
D9
D8
D6
D5
D4
D10
ACS2
ADCK2
ACE2
D9
D8
¾
¾
¾
START
ACS4
ACE7
EOCB
V125EN
ACE6
ADOFF
ADRFS
VREFS
ACE4
ACS1
ADCK1
ACE1
ACS0
ADCK0
ACE0
¾
¾
ADCR1
¾
ACERL
ACE5
ACE3
HT66F20/HT66F30/HT66F40/HT66F50 A/D Converter Register List
Bit
Register
Name
7
D3
6
D2
5
D1
4
D0
3
¾
2
¾
1
¾
0
¾
ADRL(ADRFS=0)
ADRL(ADRFS=1)
ADRH(ADRFS=0)
ADRH(ADRFS=1)
ADCR0
D7
D6
D5
D4
D3
D2
D1
D0
D11
¾
D10
¾
D9
D8
D7
D6
D5
D4
D11
ACS3
¾
D10
D9
D8
¾
¾
START
ACS4
ACE7
¾
EOCB
V125EN
ACE6
¾
ADOFF
¾
ADRFS
VREFS
ACE4
¾
ACS2
ADCK2
ACE2
ACE10
ACS1
ADCK1
ACE1
ACE9
ACS0
ADCK0
ACE0
ACE8
ADCR1
ACERL
ACE5
¾
ACE3
ACE11
ACERH
HT66F60 A/D Converter Register List
Rev. 1.60
140
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
V
D
D
f
S
Y
S
N
¸
2
A
D
C
K
2
~
A
D
C
K
0
~ 6
P
B
5
/
V
R
E
F
(
N
=
0
)
A
D
O
F
F
A
C
E
1
1
~
A
C
E
0
B
i
t
c
V
R
E
F
S
A
/
D
C
l
o
k
B
i
t
A
/
D
R
e
f
e
r
e
n
c
e
V
P
A
0
/
A
N
0
~
P
A
7
/
A
N
7
P
E
6
/
A
N
8
A
D
R
L
A
/
D
D
a
t
a
P
E
7
/
A
N
9
A
/
D
C
o
n
v
e
r
t
e
r
R
H
e
g
i
s
t
e
r
A
D
R
P
F
0
/
A
N
1
0
P
F
1
/
A
N
1
1
V
S
S
A
D
R
F
S
1
.
2
5
V
b
i
t
V
1
2
5
E
N
A
C
S
4
~
A
S
C
T
S
A
0
E
R
O
T
C
A
B
D
O
F
F
A/D Converter Structure
A/D Converter Data Registers - ADRL, ADRH
As the devices contain an internal 12-bit A/D converter, they require two data registers to store the converted value.
These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process
takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only
12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the
ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits
will be read as zero.
ADRH
ADRL
ADRFS
7
6
5
4
3
2
1
0
7
6
5
4
3
0
2
0
1
0
0
0
0
1
D11 D10 D9
D8
0
D7
D6
D5
D4
D8
D3
D7
D2
D6
D1
D5
D0
D4
0
0
0
D11 D10 D9
D3
D2
D1
D0
A/D Data Registers
A/D Converter Control Registers -
ADCR0, ADCR1, ACERL, ACERH
The ACERH and ACERL control registers contain the
ACER11~ACER0 bits which determine which pins on
Port A, PE6, PE7, PF0 and PF1 are used as analog in-
puts for the A/D converter input and which pins are not
to be used as the A/D converter input. Setting the corre-
sponding bit high will select the A/D input function, clear-
ing the bit to zero will select either the I/O or other
pin-shared function. When the pin is selected to be an
A/D input, its original function whether it is an I/O or
other pin-shared function will be removed. In addition,
any internal pull-high resistors connected to these pins
will be automatically removed if the pin is selected to be
an A/D input.
To control the function and operation of the A/D con-
verter, three or four control registers known as ADCR0,
ADCR1, ACERL and ACERH are provided. These 8-bit
registers define functions such as the selection of which
analog channel is connected to the internal A/D con-
verter, the digitised data format, the A/D clock source as
well as controlling the start function and monitoring the
A/D converter end of conversion status. The
ACS3~ACS0 bits in the ADCR0 register and ACS4 bit is
the ADCR1 register define the ADC input channel num-
ber. As the device contains only one actual analog to
digital converter hardware circuit, each of the individual
8 or 12 analog inputs must be routed to the converter. It
is the function of the ACS4~ACS0 bits to determine
which analog channel input pins or internal 1.25V is ac-
tually connected to the internal A/D converter.
Rev. 1.60
141
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
ADCR0 Register
¨
HT66F20/HT66F30/HT66F40/HT66F50
Bit
Name
R/W
7
START
R/W
0
6
EOCB
R
5
ADOFF
R/W
1
4
ADRFS
R/W
0
3
2
ACS2
R/W
0
1
ACS1
R/W
0
0
ACS0
R/W
0
¾
¾
¾
POR
1
Bit 7
START: Start the A/D conversion
0®1®0 : start
0®1
: reset the A/D converter and set EOCB to ²1²
This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and
then cleared low again, the A/D converter will initiate a conversion process. When the bit is set
high the A/D converter will be reset.
Bit 6
Bit 5
EOCB: End of A/D conversion flag
0: A/D conversion ended
1: A/D conversion in progress
This read only flag is used to indicate when an A/D conversion process has completed. When
the conversion process is running the bit will be high.
ADOFF : ADC module power on/off control bit
0: ADC module power on
1: ADC module power off
This bit controls the power to the A/D internal function. This bit should be cleared to zero to
enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing
the device power consumption. As the A/D converter will consume a limited amount of power,
even when not executing a conversion, this may be an important consideration in power sensitive
battery powered applications.
Note: 1. it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving
power.
2. ADOFF=1 will power down the ADC module.
Bit 4
ADRFS: ADC Data Format Control
0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4
1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0
This bit controls the format of the 12-bit converted A/D value in the two A/D data registers.
Details are provided in the A/D data register section.
Bit 3
unimplemented, read as ²0²
Bit 2~0
ACS2, ACS1, ACS0: Select A/D channel (when ACS4 is ²0²)
000: AN0
001: AN1
010: AN2
011: AN3
100: AN4
101: AN5
110: AN6
111: AN7
These are the A/D channel select control bits. As there is only one internal hardware A/D
converter each of the eight A/D inputs must be routed to the internal converter using these bits.
If bit ACS4 in the ADCR1 register is set high then the internal 1.25V will be routed to the A/D
Converter.
Rev. 1.60
142
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
ADCR0 Register
¨
HT66F60
Bit
Name
R/W
7
START
R/W
0
6
EOCB
R
5
ADOFF
R/W
1
4
ADRFS
R/W
0
3
ACS3
R/W
0
2
ACS2
R/W
0
1
ACS1
R/W
0
0
ACS0
R/W
0
POR
1
Bit 7
START: Start the A/D conversion
0®1®0 : start
0®1
: reset the A/D converter and set EOCB to ²1²
This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and
then cleared low again, the A/D converter will initiate a conversion process. When the bit is set
high the A/D converter will be reset.
Bit 6
Bit 5
EOCB: End of A/D conversion flag
0: A/D conversion ended
1: A/D conversion in progress
This read only flag is used to indicate when an A/D conversion process has completed. When
the conversion process is running the bit will be high.
ADOFF : ADC module power on/off control bit
0: ADC module power on
1: ADC module power off
This bit controls the power to the A/D internal function. This bit should be cleared to zero to
enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing
the device power consumption. As the A/D converter will consume a limited amount of power,
even when not executing a conversion, this may be an important consideration in power sensitive
battery powered applications.
Note: 1. it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving
power.
2. ADOFF=1 will power down the ADC module.
Bit 4
ADRFS: ADC Data Format Control
0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4
1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0
This bit controls the format of the 12-bit converted A/D value in the two A/D data registers.
Details are provided in the A/D data register section.
Bit 3~0
ACS3, ACS2, ACS1, ACS0: Select A/D channel (when ACS4 is ²0²)
0000: AN0
0001: AN1
0010: AN2
0011: AN3
0100: AN4
0101: AN5
0110: AN6
0111: AN7
1000: AN8
1001: AN9
1010: AN10
1011: AN11
1100~1111: undefined, can¢t be used
These are the A/D channel select control bits. As there is only one internal hardware A/D
converter each of the eight A/D inputs must be routed to the internal converter using these bits.
If bit ACS4 in the ADCR1 register is set high then the internal 1.25V will be routed to the A/D
Converter.
Rev. 1.60
143
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
ADCR1 Register
Bit
7
6
V125EN
R/W
0
5
4
VREFS
R/W
0
3
2
ADCK2
R/W
0
1
ADCK1
R/W
0
0
ADCK0
R/W
0
Name
R/W
ACS4
R/W
0
¾
¾
¾
¾
¾
¾
POR
Bit 7
ACS4: Selecte Internal 1.25V as ADC input Control
0: Disable
1: Enable
This bit enables 1.25V to be connected to the A/D converter. The V125EN bit must first have
been set to enable the bandgap circuit 1.25V voltage to be used by the A/D converter. When the
ACS4 bit is set high, the bandgap 1.25V voltage will be routed to the A/D converter and the other
A/D input channels disconnected.
Bit 6
V125EN: Internal 1.25V Control
0: Disable
1: Enable
This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit
is set high the bandgap voltage 1.25V can be used by the A/D converter. If 1.25V is not used by
the A/D converter and the LVR/LVD function is disabled then the bandgap reference circuit will be
automatically switched off to conserve power. When 1.25V is switched on for use by the A/D
converter, a time tBG should be allowed for the bandgap circuit to stabilise before implementing
an A/D conversion.
Bit 5
Bit 4
unimplemented, read as ²0²
VREFS: Selecte ADC reference voltage
0: Internal ADC power
1: VREF pin
This bit is used to select the reference voltage for the A/D converter. If the bit is high, then the
A/D converter reference voltage is supplied on the external VREF pin. If the pin is low, then the
internal reference is used which is taken from the power supply pin VDD.
Bit 3
unimplemented, read as ²0²
Bit 2~0
ADCK2, ADCK1, ADCK0: Select ADC clock source
000: fSYS
001: fSYS/2
010: fSYS/4
011: fSYS/8
100: fSYS/16
101: fSYS/32
110: fSYS/64
111: Undefined
These three bits are used to select the clock source for the A/D converter.
Rev. 1.60
144
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
ACERL Register
Bit
7
6
ACE6
R/W
1
5
ACE5
R/W
1
4
ACE4
R/W
1
3
ACE3
R/W
1
2
ACE2
R/W
1
1
ACE1
R/W
1
0
ACE0
R/W
1
Name
R/W
ACE7
R/W
1
POR
Bit 7
ACE7: Define PA7 is A/D input or not
0: Not A/D input
1: A/D input, AN7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ACE6: Define PA6 is A/D input or not
0: Not A/D input
1: A/D input, AN6
ACE5: Define PA5 is A/D input or not
0: Not A/D input
1: A/D input, AN5
ACE4: Define PA4 is A/D input or not
0: Not A/D input
1: A/D input, AN4
ACE3: Define PA3 is A/D input or not
0: Not A/D input
1: A/D input, AN3
ACE2: Define PA2 is A/D input or not
0: Not A/D input
1: A/D input, AN2
ACE1: Define PA1 is A/D input or not
0: Not A/D input
1: A/D input, AN1
ACE0: Define PA0 is A/D input or not
0: Not A/D input
1: A/D input, AN0
·
ACERH Register
¨
HT66F60
Bit
Name
R/W
7
6
5
4
3
ACE11
R/W
1
2
ACE10
R/W
1
1
ACE9
R/W
1
0
ACE8
R/W
1
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~4
Bit 3
unimplemented, read as ²0²
ACE11: Define PF1 is A/D input or not
0: Not A/D input
1: A/D input, AN11
Bit 2
Bit 1
Bit 0
ACE10: Define PF0 is A/D input or not
0: Not A/D input
1: A/D input, AN10
ACE9: Define PE7 is A/D input or not
0: Not A/D input
1: A/D input, AN9
ACE8: Define PE6 is A/D input or not
0: Not A/D input
1: A/D input, AN8
Rev. 1.60
145
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Operation
whether it has been cleared as an alternative method of
detecting the end of an A/D conversion cycle.
The START bit in the ADCR0 register is used to start
and reset the A/D converter. When the microcontroller
sets this bit from low to high and then low again, an ana-
log to digital conversion cycle will be initiated. When the
START bit is brought from low to high but not low again,
the EOCB bit in the ADCR0 register will be set high and
the analog to digital converter will be reset. It is the
START bit that is used to control the overall start opera-
tion of the internal analog to digital converter.
The clock source for the A/D converter, which originates
from the system clock fSYS, can be chosen to be either
fSYS or a subdivided version of fSYS. The division ratio
value is determined by the ADCK2~ADCK0 bits in the
ADCR1 register.
Although the A/D clock source is determined by the sys-
tem clock fSYS, and by bits ADCK2~ADCK0, there are
some limitations on the maximum A/D clock source
speed that can be selected. As the minimum value of per-
missible A/D clock period, tADCK, is 0.5ms, care must be
taken for system clock frequencies equal to or greater
than 4MHz. For example, if the system clock operates at
a frequency of 4MHz, the ADCK2~ADCK0 bits should
not be set to ²000². Doing so will give A/D clock periods
that are less than the minimum A/D clock period which
may result in inaccurate A/D conversion values. Refer to
the following table for examples, where values marked
with an asterisk * show where, depending upon the de-
vice, special care must be taken, as the values may be
less than the specified minimum A/D Clock Period.
The EOCB bit in the ADCR0 register is used to indicate
when the analog to digital conversion process is com-
plete. This bit will be automatically set to ²0² by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the inter-
rupts are enabled, an appropriate internal interrupt sig-
nal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D inter-
nal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR0 register to check
A/D Clock Period (tADCK
)
ADCK2,
ADCK1,
ADCK0
= 000
ADCK2,
ADCK1,
ADCK0
= 001
ADCK2,
ADCK1,
ADCK0
= 010
ADCK2,
ADCK1,
ADCK0
= 011
ADCK2,
ADCK1,
ADCK0
= 100
ADCK2,
ADCK1,
ADCK0
= 101
ADCK2,
ADCK1,
ADCK0
= 110
ADCK2,
ADCK1,
ADCK0
= 111
fSYS
(fSYS
)
(fSYS/2)
(fSYS/4)
(fSYS/8)
(fSYS/16)
(fSYS/32)
(fSYS/64)
1MHz
2MHz
4MHz
8MHz
12MHz
Undefined
Undefined
Undefined
Undefined
Undefined
1ms
2ms
1ms
4ms
2ms
8ms
4ms
16ms
8ms
32ms
16ms
8ms
64ms
32ms
16ms
8ms
500ns
250ns*
125ns*
83ns*
500ns
250ns*
167ns*
1ms
2ms
4ms
500ns
333ns*
1ms
2ms
4ms
667ns
1.33ms
2.67ms
5.33ms
A/D Clock Period Examples
Controlling the power on/off function of the A/D con-
verter circuitry is implemented using the ADOFF bit in
the ADCR0 register. This bit must be zero to power on
the A/D converter. When the ADOFF bit is cleared to
zero to power on the A/D converter internal circuitry a
certain delay, as indicated in the timing diagram, must
be allowed before an A/D conversion is initiated. Even if
no pins are selected for use as A/D inputs by clearing
the ACE11~ACE0 bits in the ACERH and ACERL regis-
ters, if the ADOFF bit is zero then some power will still
be consumed. In power conscious applications it is
therefore recommended that the ADOFF is set high to
reduce power consumption when the A/D converter
function is not being used.
functions, when the VREFS bit is set high, the VREF pin
function will be selected and the other pin functions will
be disabled automatically.
A/D Input Pins
All of the A/D analog input pins are pin-shared with the
I/O pins on Port A, PE6, PF7, PF0 or PF1 as well as
other functions. The ACE11~ ACE0 bits in the ACERH
and ACERL registers, determine whether the input pins
are setup as A/D converter analog inputs or whether
they have other functions. If the ACE11~ ACE0 bits for
its corresponding pin is set high then the pin will be
setup to be an A/D converter input and the original pin
functions disabled. In this way, pins can be changed un-
der program control to change their function between
A/D inputs and other functions. All pull-high resistors,
which are setup through register programming, will be
automatically disconnected if the pins are setup as A/D
inputs. Note that it is not necessary to first setup the A/D
The reference voltage supply to the A/D Converter can
be supplied from either the positive power supply pin,
VDD, or from an external reference sources supplied on
pin VREF. The desired selection is made using the
VREFS bit. As the VREF pin is pin-shared with other
Rev. 1.60
146
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
·
·
Step 3
pin as an input in the PAC, PEC or PFC port control reg-
ister to enable the A/D input as when the ACE11~ ACE0
bits enable an A/D input, the status of the port control
register will be overridden.
Select which channel is to be connected to the internal
A/D converter by correctly programming the
ACS4~ACS0 bits which are also contained in the
ADCR1 and ADCR0 register.
The A/D converter has its own reference voltage pin,
VREF, however the reference voltage can also be sup-
plied from the power supply pin, a choice which is made
through the VREFS bit in the ADCR1 register. The ana-
log input values must not be allowed to exceed the value
of VREF.
Step 4
Select which pins are to be used as A/D inputs and
configure them by correctly programming the
ACE11~ACE0 bits in the ACERH and ACERL
registers.
Step 5
P
A
0
/
A
P
N
F
0
1
/
A
N
1
1
If the interrupts are to be used, the interrupt control
registers must be correctly configured to ensure the
A/D converter interrupt function is active. The master
interrupt control bit, EMI, and the A/D converter inter-
rupt bit, EADI, must both be set high to do this.
1
.
2
5
V
A
C
S
4
~
A
C
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B
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r
1
2
·
·
Step 6
B
a
n
d
g
a
The analog to digital conversion process can now be
initialised by setting the START bit in the ADCR regis-
ter from low to high and then low again. Note that this
bit should have been originally cleared to zero.
V
R
E F
C
S
1
2
-
b
i
t
A
D
R
e
f
e
r
e
n
V
o
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a
g
V
D
D
V
R
E
F
P
B
5
/
V
R
E
F
Step 7
A/D Input Structure
Summary of A/D Conversion Steps
To check when the analog to digital conversion pro-
cess is complete, the EOCB bit in the ADCR0 register
can be polled. The conversion process is complete
when this bit goes low. When this occurs the A/D data
registers ADRL and ADRH can be read to obtain the
conversion value. As an alternative method, if the in-
terrupts are enabled and the stack is not full, the pro-
gram can wait for an A/D interrupt to occur.
Note: When checking for the end of the conversion
process, if the method of polling the EOCB bit in the
ADCR0 register is used, the interrupt enable step
above can be omitted.
The following summarises the individual steps that
should be executed in order to implement an A/D con-
version process.
·
Step 1
Select the required A/D conversion clock by correctly
programming bits ADCK2~ADCK0 in the ADCR1 reg-
ister.
·
Step 2
Enable the A/D by clearing the ADOFF bit in the
ADCR0 register to zero.
A
D
O
F
F
t
O
N
2
S
T
A
D
C
M
o
d
u
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e
o
f
f
o
f
f
o
n
o
n
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N
A
/
D
s
a
m
p
l
i
n
g
A
/
t
D
i
m
s
e
a
m
p
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t
i
m
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A
D
t
S
A
D
S
S
T
A
R
T
E
O
C
B
A
C
S
4
~
A
C
0
S
0
0
0
1
1
B
0
0
0
1
0
B
0
0
0
0
0
B
0
0
0
0
1
B
P
o
w
e
r
-
o
n
S
t
a
r
t
o
f
A
/
D
S
t
a
r
t
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f
A
/
D
S
t
a
r
t
o
f
A
/
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R
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t
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v
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R
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t
A
/
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R
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s
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t
A
/
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R
e
s
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t
A
/
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c
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v
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t
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d
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A
/
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n
d
o
f
A
/
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c
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v
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r
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c
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1
:
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e
f
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p
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2
:
S
e
l
e
c
t
a
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a
l
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g
c
h
a
n
n
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l
t
A
D
C
t
A
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C
A
/
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c
o
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v
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r
s
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A
o
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n
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t
c
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e
v
e
r
s
i
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t
i
m
e
A/D Conversion Timing
Rev. 1.60
147
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
The accompanying diagram shows graphically the vari-
value of VDD or VREF divided by 4096.
ous stages involved in an analog to digital conversion
process and its associated timing. After an A/D conver-
sion process has been initiated by the application pro-
gram, the microcontroller internal hardware will begin to
carry out the conversion, during which time the program
can continue with other functions. The time taken for the
A/D conversion is 16tADCK where tADCK is equal to the A/D
clock period.
1 LSB= (VDD or VREF) ¸ 4096
The A/D Converter input voltage value can be
calculated using the following equation:
A/D input voltage =
A/D output digital value ´ (VDD or VREF) ¸ 4096
The diagram shows the ideal transfer function between
the analog input value and the digitised output value for
the A/D converter. Except for the digitised zero value,
the subsequent digitised values will change at a point
0.5 LSB below where they would change without the off-
set, and the last full scale digitised value will change at a
point 1.5 LSB below the VDD or VREF level.
Programming Considerations
During microcontroller operations where the A/D con-
verter is not being used, the A/D internal circuitry can be
switched off to reduce power consumption, by setting bit
ADOFF high in the ADCR0 register. When this happens,
the internal A/D converter circuits will not consume
power irrespective of what analog voltage is applied to
their input lines. If the A/D converter input lines are used
as normal I/Os, then care must be taken as if the input
voltage is not at a valid logic level, then this may lead to
some increase in power consumption.
A/D Programming Example
The following two programming examples illustrate how
to setup and implement an A/D conversion. In the first
example, the method of polling the EOCB bit in the
ADCR0 register is used to detect when the conversion
cycle is complete, whereas in the second example, the
A/D interrupt is used to determine when the conversion
is complete.
A/D Transfer Function
As the devices contain a 12-bit A/D converter, its
full-scale converted digitised value is equal to FFFH.
Since the full-scale analog input value is equal to the
VDD or VREF voltage, this gives a single bit analog input
1
.
5
L
S
B
F
F
F
H
F
F
E
H
F
F
D
H
A
/
D
C
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v
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r
s
i
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s
u
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t
0
.
5
L
S
B
0
0
0
3
2
1
H
H
H
V
D
D
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r
R
E
F
(
4
0
9
6
6
0
1
2
3
4
0
4
9
0
3
9
4
4
0
9
5
4
0
9
A
n
a
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n
p
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t
V
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l
t
a
g
e
Ideal A/D Transfer Function
Rev. 1.60
148
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Example: using an EOCB polling method to detect the end of conversion
clr EADI
mov a,03H
mov ADCR1,a
clr ADOFF
mov a,0Fh
mov ACERL,a
mov a,00h
mov ACERH,00h
mov a,00h
mov ADCR0,a
:
; disable ADC interrupt
; select fSYS/8 as A/D clock and switch off 1.25V
; setup ACERL and ACERH to configure pins AN0~AN3
; ACERH is only for HT66F60
; enable and connect AN0 channel to A/D converter
start_conversion:
clr START
set START
clr START
polling_EOC:
; high pulse on start bit to initiate conversion
; reset A/D
; start A/D
sz
EOCB
; poll the ADCR0 register EOCB bit to detect end
; of A/D conversion
; continue polling
; read low byte conversion result value
; save result to user defined register
; read high byte conversion result value
; save result to user defined register
jmp polling_EOC
mov a,ADRL
mov ADRL_buffer,a
mov a,ADRH
mov ADRH_buffer,a
:
:
jmp start_conversion ; start next a/d conversion
Example: using the interrupt method to detect the end of conversion
clr EADI
mov a,03H
mov ADCR1,a
Clr ADOFF
mov a,0Fh
mov ACERL,a
mov a,00h
mov ACERH,00h
mov a,00h
mov ADCR0,a
Start_conversion:
clr START
set START
clr START
clr ADF
; disable ADC interrupt
; select fSYS/8 as A/D clock and switch off 1.25V
; setup ACERL and ACERH to configure pins AN0~AN3
; ACERH is only for HT66F60
; enable and connect AN0 channel to A/D converter
; high pulse on START bit to initiate conversion
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
set EADI
set EMI
:
:
; ADC interrupt service routine
ADC_ISR:
mov acc_stack,a
mov a,STATUS
; save ACC to user defined memory
mov status_stack,a
:
; save STATUS to user defined memory
:
mov a,ADRL
mov adrl_buffer,a
mov a,ADRH
mov adrh_buffer,a
; read low byte conversion result value
; save result to user defined register
; read high byte conversion result value
; save result to user defined register
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a
mov a,acc_stack
reti
; restore STATUS from user defined memory
; restore ACC from user defined memory
Rev. 1.60
149
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Comparators
Two independent analog comparators are contained
within these devices. These functions offer flexibility via
their register controlled features such as power-down,
polarity select, hysteresis etc. In sharing their pins with
normal I/O pins the comparators do not waste precious
I/O pins if there functions are otherwise unused.
Any pull-high resistors connected to the shared com-
parator input pins will be automatically disconnected
when the comparator is enabled. As the comparator in-
puts approach their switching level, some spurious out-
put signals may be generated on the comparator output
due to the slow rising or falling nature of the input sig-
nals. This can be minimised by selecting the hysteresis
function will apply a small amount of positive feedback
to the comparator. Ideally the comparator should switch
at the point where the positive and negative inputs sig-
nals are at the same voltage level, however, unavoid-
able input offsets introduce some uncertainties here.
The hysteresis function, if enabled, also increases the
switching offset value.
C
n
P
O
C
L
n
O
U
T
C
n
+
C
n
X
C
n
-
C
n
S
E
L
Comparator
Comparator Operation
The device contains two comparator functions which
are used to compare two analog voltages and provide
an output based on their difference. Full control over the
two internal comparators is provided via two control reg-
isters, CP0C and CP1C, one assigned to each com-
parator. The comparator output is recorded via a bit in
their respective control register, but can also be trans-
ferred out onto a shared I/O pin. Additional comparator
functions include, output polarity, hysteresis functions
and power down control.
Comparator Registers
There are two registers for overall comparator opera-
tion, one for each comparator. As corresponding bits in
the two registers have identical functions, they following
register table applies to both registers.
Bit
Register
Name
7
6
5
4
3
2
1
0
CP0C
CP1C
C0SEL
C1SEL
C0EN
C1EN
C0POL
C1POL
C0OUT
C1OUT
C0OS
C1OS
C0HYEN
C1HYEN
¾
¾
¾
¾
Comparator Registers List
Comparator Interrupt
Programming Considerations
Each also possesses its own interrupt function. When
any one of the changes state, its relevant interrupt flag
will be set, and if the corresponding interrupt enable bit
is set, then a jump to its relevant interrupt vector will be
executed. Note that it is the changing state of the
C0OUT or C1OUT bit and not the output pin which gen-
erates an interrupt. If the microcontroller is in the SLEEP
or IDLE Mode and the Comparator is enabled, then if the
external input lines cause the Comparator output to
change state, the resulting generated interrupt flag will
also generate a wake-up. If it is required to disable a
wake-up from occurring, then the interrupt flag should
be first set high before entering the SLEEP or IDLE
Mode.
If the comparator is enabled, it will remain active when
the microcontroller enters the SLEEP or IDLE Mode,
however as it will consume a certain amount of power,
the user may wish to consider disabling it before the
SLEEP or IDLE Mode is entered.
As comparator pins are shared with normal I/O pins the
I/O registers for these pins will be read as zero (port con-
trol register is ²1²) or read as port data register value
(port control register is ²0²) if the comparator function is
enabled.
Rev. 1.60
150
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
CP0C Register
Bit
Name
R/W
7
C0SEL
R/W
1
6
C0EN
R/W
0
5
C0POL
R/W
0
4
3
C0OS
R/W
0
2
1
0
C0HYEN
R/W
C0OUT
¾
¾
¾
¾
¾
¾
R
0
POR
1
Bit 7
C0SEL: Select Comparator pins or I/O pins
0: I/O pin select
1: Comparator pin select
This is the Comparator pin or I/O pin select bit. If the bit is high the comparator will be selected
and the two comparator input pins will be enabled. As a result, these two pins will lose their I/O
pin functions. Any pull-high configuration options associated with the comparator shared pins will
also be automatically disconnected.
Bit 6
C0EN: Comparator On/Off control
0: Off
1: On
This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off
and no power consumed even if analog voltages are applied to its inputs. For power sensitive
applications this bit should be cleared to zero if the comparator is not used or before the device
enters the SLEEP or IDLE mode.
Bit 5
C0POL: Comparator output polarity
0: output not inverted
1: output inverted
This is the comparator polarity bit. If the bit is zero then the C0OUT bit will reflect the
non-inverted output condition of the comparator. If the bit is high the comparator C0OUT bit will
be inverted.
Bit 4
C0OUT: Comparator output bit
C0POL=0
0: C0+ < C0-
1: C0+ > C0-
C0POL=1
0: C0+ > C0-
1: C0+ < C0-
This bit stores the comparator output bit. The polarity of the bit is determined by the voltages
on the comparator inputs and by the condition of the C0POL bit.
Bit 3
C0OS: Output path select
0: C0X pin
1: Internal use
This is the comparator output path select control bit. If the bit is set to ²0² and the C0SEL bit is
²1² the comparator output is connected to an external C0X pin. If the bit is set to ²1² or the
C0SEL bit is ²0² the comparator output signal is only used internally by the device allowing the
shared comparator output pin to retain its normal I/O operation.
Bit 2~1
Bit 0
unimplemented, read as ²0²
C0HYEN: Hysteresis Control
0: Off
1: On
This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the
comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback
induced by hysteresis reduces the effect of spurious switching near the comparator threshold.
Rev. 1.60
151
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
CP1C Register
Bit
Name
R/W
7
C1SEL
R/W
1
6
C1EN
R/W
0
5
C1POL
R/W
0
4
3
C1OS
R/W
0
2
1
0
C1HYEN
R/W
C1OUT
¾
¾
¾
¾
¾
¾
R
0
POR
1
Bit 7
C1SEL: Select Comparator pins or I/O pins
0: I/O pin select
1: Comparator pin select
This is the Comparator pin or I/O pin select bit. If the bit is high the comparator will be selected
and the two comparator input pins will be enabled. As a result, these two pins will lose their I/O
pin functions. Any pull-high configuration options associated with the comparator shared pins will
also be automatically disconnected.
Bit 6
C1EN: Comparator On/Off control
0: Off
1: On
This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off
and no power consumed even if analog voltages are applied to its inputs. For power sensitive
applications this bit should be cleared to zero if the comparator is not used or before the device
enters the SLEEP or IDLE mode.
Bit 5
C1POL: Comparator output polarity
0: output not inverted
1: output inverted
This is the comparator polarity bit. If the bit is zero then the C1OUT bit will reflect the
non-inverted output condition of the comparator. If the bit is high the comparator C1OUT bit will
be inverted.
Bit 4
C1OUT: Comparator output bit
C1POL=0
0: C1+ < C1-
1: C1+ > C1-
C1POL=1
0: C1+ > C1-
1: C1+ < C1-
This bit stores the comparator output bit. The polarity of the bit is determined by the voltages
on the comparator inputs and by the condition of the C1POL bit.
Bit 3
C1OS: Output path select
0: C1X pin
1: Internal use
This is the comparator output path select control bit. If the bit is set to ²0² and the C1SEL bit is
²1² the comparator output is connected to an external C1X pin. If the bit is set to ²1² or the
C1SEL bit is ²0² the comparator output signal is only used internally by the device allowing the
shared comparator output pin to retain its normal I/O operation.
Bit 2~1
Bit 0
unimplemented, read as ²0²
C1HYEN: Hysteresis Control
0: Off
1: On
This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the
comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback
induced by hysteresis reduces the effect of spurious switching near the comparator threshold.
Rev. 1.60
152
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Serial Interface Module - SIM
These devices contain a Serial Interface Module, which
includes both the four line SPI interface or the two line
I2C interface types, to allow an easy method of commu-
nication with external peripheral hardware. Having rela-
tively simple communication protocols, these serial
interface types allow the microcontroller to interface to
external SPI or I2C based hardware such as sensors,
Flash or EEPROM memory, etc. The SIM interface pins
are pin-shared with other I/O pins therefore the SIM in-
terface function must first be selected using a configura-
tion option. As both interface types share the same pins
and registers, the choice of whether the SPI or I2C type
is used is made using the SIM operating mode control
bits, named SIM2~SIM0, in the SIMC0 register. These
pull-high resistors of the SIM pin-shared I/O are se-
lected using pull-high control registers, and also if the
SIM function is enabled.
needs to control multiple slave devices from a single
master, the master can use I/O pin to select the slave
devices.
·
SPI Interface Operation
The SPI interface is a full duplex synchronous serial
data link. It is a four line interface with pin names SDI,
SDO, SCK and SCS. Pins SDI and SDO are the Serial
Data Input and Serial Data Output lines, SCK is the
Serial Clock line and SCS is the Slave Select line. As
the SPI interface pins are pin-shared with normal I/O
pins and with the I2C function pins, the SPI interface
must first be enabled by selecting the SIM enable con-
figuration option and setting the correct bits in the
SIMC0 and SIMC2 registers. After the SPI configura-
tion option has been configured it can also be addi-
tionally disabled or enabled using the SIMEN bit in the
SIMC0 register. Communication between devices
connected to the SPI interface is carried out in a
slave/master mode with all data transfer initiations be-
ing implemented by the master. The Master also con-
trols the clock signal. As the device only contains a
single SCS pin only one slave device can be utilized.
The SCS pin is controlled by software, set CSEN bit to
²1² to enable SCS pin function, set CSEN bit to ²0² the
SCS pin will be floating state.
SPI Interface
The SPI interface is often used to communicate with ex-
ternal peripheral devices such as sensors, Flash or
EEPROM memory devices etc. Originally developed by
Motorola, the four line SPI interface is a synchronous
serial data interface that has a relatively simple commu-
nication protocol simplifying the programming require-
ments when communicating with external hardware
devices.
S
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The communication is full duplex and operates as a
slave/master type, where the device can be either mas-
ter or slave. Although the SPI interface specification can
control multiple slave devices from a single master, but
this device provided only one SCS pin. If the master
S
C
S
SPI Master/Slave Connection
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SPI Block Diagram
Rev. 1.60
153
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
The SPI function in this device offers the following
features:
There are several configuration options associated with
the SPI interface. One of these is to enable the SIM
function which selects the SIM pins rather than normal
I/O pins. Note that if the configuration option does not
select the SIM function then the SIMEN bit in the SIMC0
register will have no effect. Another two SPI configura-
tion options determine if the CSEN and WCOL bits are
to be used.
¨
¨
¨
¨
¨
¨
Full duplex synchronous data transfer
Both Master and Slave modes
LSB first or MSB first data transmission modes
Transmission complete flag
Rising or falling active clock edge
WCOL and CSEN bit enabled or disable select
SPI Registers
The status of the SPI interface pins is determined by a
number of factors such as whether the device is in the
master or slave mode and upon the condition of certain
control bits such as CSEN and SIMEN.
There are three internal registers which control the over-
all operation of the SPI interface. These are the SIMD
data register and two registers SIMC0 and SIMC2. Note
that the SIMC1 register is only used by the I2C interface.
Bit
Register
Name
7
SIM2
D7
6
SIM1
D6
5
SIM0
D5
4
3
2
1
0
¾
SIMC0
PCKEN
D4
PCKP1
D3
PCKP0
D2
SIMEN
D1
SIMD
D0
TRF
SIMC2
D7
D6
CKPOLB
CKEG
MLS
CSEN
WCOL
SIM Registers List
The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI
and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the
SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmis-
sion or reception of data from the SPI bus must be made via the SIMD register.
·
SIMD Register
Bit
Name
R/W
7
D7
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
D4
R/W
x
3
D3
R/W
x
2
D2
R/W
x
1
D1
R/W
x
0
D0
R/W
POR
x
²x² unknown
Rev. 1.60
154
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has
the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C
function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock fre-
quency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock
Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc.
·
SIMC0 Register
Bit
Name
R/W
7
SIM2
R/W
1
6
SIM1
R/W
1
5
SIM0
R/W
1
4
PCKEN
R/W
0
3
PCKP1
R/W
0
2
PCKP0
R/W
0
1
SIMEN
R/W
0
0
¾
¾
¾
POR
Bit 7~5
SIM2, SIM1, SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fTBC
100: SPI master mode; SPI clock is TM0 CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Unused mode
These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C
or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock
frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced
from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external
Master device.
Bit 4
PCKEN: PCK Output Pin Control
0: Disable
1: Enable
Bit 3~2
PCKP1, PCKP0: Select PCK output pin frequency
00: fSYS
01: fSYS/4
10: fSYS/8
11: TM0 CCRP match frequency/2
Bit 1
SIMEN: SIM Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero
to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a
floating condition and the SIM operating current will be reduced to a minimum value. When the bit
is high the SIM interface is enabled. The SIM configuration option must have first enabled the
SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via
the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings
when the SIMEN bit changes from low to high and should therefore be first initialised by the
application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0
bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX
and TXAK will remain at the previous settings and should therefore be first initialised by the
application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will
be set to their default states.
Bit 0
unimplemented, read as ²0²
Rev. 1.60
155
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
SIMC2 Register
Bit
Name
R/W
7
D7
R/W
0
6
D6
R/W
0
5
CKPOLB
R/W
4
CKEG
R/W
0
3
2
CSEN
R/W
0
1
WCOL
R/W
0
0
MLS
R/W
0
TRF
R/W
0
POR
0
Bit 7~6
Bit 5
Undefined bit
This bit can be read or written by user software program.
CKPOLB: Determines the base condition of the clock line
0: the SCK line will be high when the clock is inactive
1: the SCK line will be low when the clock is inactive
The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK
line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be
high when the clock is inactive.
Bit 4
CKEG: Determines SPI SCK active clock edge type
CKPOLB=0
0: SCK is high base level and data capture at SCK rising edge
1: SCK is high base level and data capture at SCK falling edge
CKPOLB=1
0: SCK is low base level and data capture at SCK falling edge
1: SCK is low base level and data capture at SCK rising edge
The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and
inputs data on the SPI bus. These two bits must be configured before data transfer is executed
otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base
condition of the clock line, if the bit is high, then the SCK line will be low when the clock is
inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive.
The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB
bit.
Bit 3
Bit 2
MLS: SPI Data shift order
0: LSB
1: MSB
This is the data shift select bit and is used to select how the data is transferred, either MSB or
LSB first. Setting the bit high will select MSB first and low for LSB first.
CSEN: SPI SCS pin Control
0: Disable
1: Enable
The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS
pin will be disabled and placed into a floating condition. If the bit is high the SCS pin will be
enabled and used as a select pin.
Note that using the CSEN bit can be disabled or enabled via configuration option.
Bit 1
WCOL: SPI Write Collision flag
0: No collision
1: Collision
The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that
data has been attempted to be written to the SIMD register during a data transfer operation. This
writing operation will be ignored if data is being transferred. The bit can be cleared by the
application program. Note that using the WCOL bit can be disabled or enabled via configuration
option.
Bit 0
TRF: SPI Transmit/Receive Complete flag
0: Data is being transferred
1: SPI data transmission is completed
The TRF bit is the Transmit/Receive Complete flag and is set ²1² automatically when an SPI
data transmission is completed, but must set to ²0² by the application program. It can be used to
generate an interrupt.
Rev. 1.60
156
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
SPI Communication
The master should output an SCS signal to enable the
slave device before a clock signal is provided. The slave
After the SPI interface is enabled by setting the SIMEN
bit high, then in the Master Mode, when data is written to
the SIMD register, transmission/reception will begin si-
multaneously. When the data transfer is complete, the
TRF flag will be set automatically, but must be cleared
using the application program. In the Slave Mode, when
the clock signal from the master has been received, any
data in the SIMD register will be transmitted and any
data on the SDI pin will be shifted into the SIMD register.
data to be transferred should be well prepared at the ap-
propriate moment relative to the SCS signal depending
upon the configurations of the CKPOLB bit and CKEG
bit. The accompanying timing diagram shows the rela-
tionship between the slave data and SCS signal for vari-
ous configurations of the CKPOLB and CKEG bits.
The SPI will continue to function even in the IDLE Mode.
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SPI Slave Mode Timing - CKEG=0
Rev. 1.60
157
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
S
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SPI Transfer Control Flowchart
Rev. 1.60
158
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
I2C Interface
lationship between the system clock, fSYS, and the I2C
debounce time. For either the I2C Standard or Fast
The I2C interface is used to communicate with external
peripheral devices such as sensors, EEPROM memory
etc. Originally developed by Philips, it is a two line low
speed serial interface for synchronous serial data trans-
fer. The advantage of only two lines for communication,
relatively simple communication protocol and the ability
to accommodate multiple devices on the same bus has
made it an extremely popular interface type for many
applications.
mode operation, users must take care of the selected
system clock frequency and the configured debounce
time to match the criterion shown in the following ta-
ble.
I2C Debounce
I2C Standard
I2C Fast Mode
(400kHz)
Time Selection Mode (100kHz)
No debounce
f
SYS > 2MHz
SYS > 4MHz
fSYS > 5MHz
2 system clock
debounce
f
fSYS > 10MHz
V
D
4 system clock
debounce
f
SYS > 8MHz
fSYS > 20MHz
S
D
S
C
I2C Minimum fSYS Frequency
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I2C Master Slave Bus Connection
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I2C Interface Operation
·
The I2C serial interface is a two line interface, a serial
data line, SDA, and serial clock line, SCL. As many
devices may be connected together on the same bus,
their outputs are both open drain types. For this rea-
son it is necessary that external pull-high resistors are
connected to these outputs. Note that no chip select
line exists, as each device on the I2C bus is identified
by a unique address which will be transmitted and re-
ceived on the I2C bus.
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When two devices communicate with each other on
the bidirectional I2C bus, one is known as the master
device and one as the slave device. Both master and
slave can transmit and receive data, however, it is the
master device that has overall control of the bus. For
these devices, which only operates in slave mode,
there are two methods of transferring data on the I2C
bus, the slave transmit mode and the slave receive
mode.
S
T
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f
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I2C Registers
·
There are three control registers associated with the
I2C bus, SIMC0, SIMC1 and SIMA and one data regis-
ter, SIMD. The SIMD register, which is shown in the
above SPI section, is used to store the data being
transmitted and received on the I2C bus. Before the
microcontroller writes data to the I2C bus, the actual
data to be transmitted must be placed in the SIMD
register. After the data is received from the I2C bus,
the microcontroller can read it from the SIMD register.
Any transmission or reception of data from the I2C bus
must be made via the SIMD register.
There are several configuration options associated
with the I2C interface. One of these is to enable the
function which selects the SIM pins rather than normal
I/O pins. Note that if the configuration option does not
select the SIM function then the SIMEN bit in the
SIMC0 register will have no effect. A configuration op-
tion determines the debounce time of the I2C inter-
face. This uses the system clock to in effect add a
debounce time to the external clock to reduce the pos-
sibility of glitches on the clock line causing erroneous
operation. The debounce time, if selected, can be
chosen to be either 2 or 4 system clocks. To achieve
the required I2C data transfer speed, there exists a re-
Note that the SIMA register also has the name SIMC2
which is used by the SPI function. Bit SIMEN and bits
SIM2~SIM0 in register SIMC0 are used by the I2C in-
terface.
Rev. 1.60
159
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Bit
Register
Name
7
6
5
4
3
2
1
0
¾
SIMC0
SIM2
HCF
D7
SIM1
HAAS
D6
SIM0
HBB
D5
PCKEN
HTX
PCKP1
TXAK
D3
PCKP0
SRW
D2
SIMEN
IAMWU
D1
SIMC1
SIMD
SIMA
RXAK
D0
D4
IICA6
IICA5
IICA4
IICA3
IICA2
IICA1
IICA0
D0
I2C Registers List
·
SIMC0 Register
Bit
Name
R/W
7
SIM2
R/W
1
6
5
4
3
2
1
SIMEN
R/W
0
0
SIM1
R/W
1
SIM0
R/W
1
PCKEN
R/W
0
PCKP1
R/W
0
PCKP0
¾
¾
¾
R/W
0
POR
Bit 7~5
SIM2, SIM1, SIM0: SIM Operating Mode Control
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fTBC
100: SPI master mode; SPI clock is TM0 CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Unused mode
These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C
or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock
frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced
from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external
Master device.
Bit 4
PCKEN: PCK Output Pin Control
0: Disable
1: Enable
Bit 3~2
PCKP1, PCKP0: Select PCK output pin frequency
00: fSYS
01: fSYS/4
10: fSYS/8
11: TM0 CCRP match frequency/2
Bit 1
SIMEN: SIM Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero
to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a
floating condition and the SIM operating current will be reduced to a minimum value. When the bit
is high the SIM interface is enabled. The SIM configuration option must have first enabled the
SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via
SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings
when the SIMEN bit changes from low to high and should therefore be first initialised by the
application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0
bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX
and TXAK will remain at the previous settings and should therefore be first initialised by the
application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will
be set to their default states.
Bit 0
unimplemented, read as ²0²
Rev. 1.60
160
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
SIMC1 Register
Bit
Name
R/W
7
HCF
R
6
HAAS
R
5
HBB
R
4
3
TXAK
R/W
0
2
SRW
R
1
IAMWU
R/W
0
0
RXAK
R
HTX
R/W
0
POR
1
0
0
0
1
Bit 7
HCF: I2C Bus data transfer completion flag
0: Data is being transferred
1: Completion of an 8-bit data transfer
The HCF flag is the data transfer flag. This flag will be zero when data is being transferred.
Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated.
Bit 6
HAAS: I2C Bus address match flag
0: Not address match
1: Address match
The HASS flag is the address match flag. This flag is used to determine if the slave device
address is the same as the master transmit address. If the addresses match then this bit will be
high, if there is no match then the flag will be low.
Bit 5
HBB: I2C Bus busy flag
0: I2C Bus is not busy
1: I2C Bus is busy
The HBB flag is the I2C busy flag. This flag will be ²1² when the I2C bus is busy which will
occur when a START signal is detected. The flag will be set to ²0² when the bus is free which will
occur when a STOP signal is detected.
Bit 4
Bit 3
HTX: Select I2C slave device is transmitter or receiver
0: Slave device is the receiver
1: Slave device is the transmitter
TXAK: I2C Bus transmit acknowledge flag
0: Slave send acknowledge flag
1: Slave do not send acknowledge flag
The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data,
this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device
must always set TXAK bit to ²0² before further data is received.
Bit 2
SRW: I2C Slave Read/Write flag
0: Slave device should be in receive mode
1: Slave device should be in transmit mode
The SRW flag is the I2C Slave Read/Write flag. This flag determines whether the master
device wishes to transmit or receive data from the I2C bus. When the transmitted address and
slave address is match, that is when the HAAS flag is set high, the slave device will check the
SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is
high, the master is requesting to read data from the bus, so the slave device should be in transmit
mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave
device should be in receive mode to read this data.
Bit 1
IAMWU: I2C Address Match Wake-up Control
0: Disable
1: Enable - must be cleared by the application program after wake-up
This bit should be set to ²1² to enable the I2C address match wake up from the SLEEP or IDLE
Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable
the I2C address match wake up, then this bit must be cleared by the application program after
wake-up to ensure correction device operation.
Bit 0
RXAK: I2C Bus Receive acknowledge flag
0: Slave receive acknowledge flag
1: Slave do not receive acknowledge flag
The RXAK flag is the receiver acknowledge flag. When the RXAK flag is ²0², it means that a
acknowledge signal has been received at the 9th clock, after 8 bits of data have been
transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag
to determine if the master receiver wishes to receive the next byte. The slave transmitter will
therefore continue sending out data until the RXAK flag is ²1². When this occurs, the slave
transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C
Bus.
Rev. 1.60
161
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI
and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the
SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmis-
sion or reception of data from the SPI bus must be made via the SIMD register.
·
SIMD Register
Bit
Name
R/W
7
D7
R/W
x
6
D6
R/W
x
5
D5
R/W
x
4
D4
R/W
x
3
D3
R/W
x
2
D2
R/W
x
1
D1
R/W
x
0
D0
R/W
POR
x
²x² unknown
·
SIMA Register
Bit
Name
R/W
7
IICA6
R/W
x
6
IICA5
R/W
x
5
IICA4
R/W
x
4
IICA3
R/W
x
3
IICA2
R/W
x
2
IICA1
R/W
x
1
IICA0
R/W
x
0
¾
¾
POR
¾
²x² unknown
Bit 7~1
IICA6~ IICA0: I2C slave address
IICA6~ IICA0 is the I2C slave address bit 6~ bit 0.
The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA
register is the location where the 7-bit slave address of the slave device is stored. Bits 7~ 1 of the
SIMA register define the device slave address. Bit 0 is not defined.
When a master device, which is connected to the I2C bus, sends out an address, which
matches the slave address in the SIMA register, the slave device will be selected. Note that the
SIMA register is the same register address as SIMC2 which is used by the SPI interface.
Bit 0
Undefined bit
This bit can be read or written by user software program.
D
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I2C Block Diagram
Rev. 1.60
162
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
I2C Bus Communication
I2C Bus Start Signal
Communication on the I2C bus requires four separate
steps, a START signal, a slave device address transmis-
sion, a data transmission and finally a STOP signal.
When a START signal is placed on the I2C bus, all de-
vices on the bus will receive this signal and be notified of
the imminent arrival of data on the bus. The first seven
bits of the data will be the slave address with the first bit
being the MSB. If the address of the slave device
matches that of the transmitted address, the HAAS bit in
the SIMC1 register will be set and an I2C interrupt will be
generated. After entering the interrupt service routine,
the slave device must first check the condition of the
HAAS bit to determine whether the interrupt source orig-
inates from an address match or from the completion of
an 8-bit data transfer. During a data transfer, note that
after the 7-bit slave address has been transmitted, the
following bit, which is the 8th bit, is the read/write bit
whose value will be placed in the SRW bit. This bit will
be checked by the slave device to determine whether to
go into transmit or receive mode. Before any transfer of
data to or from the I2C bus, the microcontroller must in-
itialise the bus, the following are steps to achieve this:
The START signal can only be generated by the master
device connected to the I2C bus and not by the slave de-
vice. This START signal will be detected by all devices
connected to the I2C bus. When detected, this indicates
that the I2C bus is busy and therefore the HBB bit will be
set. ASTART condition occurs when a high to low transi-
tion on the SDA line takes place when the SCL line re-
mains high.
Slave Address
The transmission of a START signal by the master will
be detected by all devices on the I2C bus. To determine
which slave device the master wishes to communicate
with, the address of the slave device will be sent out im-
mediately following the START signal. All slave devices,
after receiving this 7-bit address data, will compare it
with their own 7-bit slave address. If the address sent
out by the master matches the internal address of the
microcontroller slave device, then an internal I2C bus in-
terrupt signal will be generated. The next bit following
the address, which is the 8th bit, defines the read/write
status and will be saved to the SRW bit of the SIMC1
register. The slave device will then transmit an acknowl-
edge bit, which is a low level, as the 9th bit. The slave
device will also set the status flag HAAS when the ad-
dresses match.
Step 1
Set the SIM2~SIM0 and SIMEN bits in the SIMC0 regis-
ter to ²1² to enable the I2C bus.
Step 2
As an I2C bus interrupt can come from two sources,
when the program enters the interrupt subroutine, the
HAAS bit should be examined to see whether the inter-
rupt source has come from a matching slave address or
from the completion of a data byte transfer. When a
slave address is matched, the device must be placed in
either the transmit mode and then write data to the SIMD
register, or in the receive mode where it must implement
a dummy read from the SIMD register to release the
SCL line.
Write the slave address of the device to the I2C bus ad-
dress register SIMA.
Step 3
Set the SIME and SIM Muti-Function interrupt enable bit
of the interrupt control register to enable the SIM inter-
rupt and Multi-function interrupt.
S
t
a
r
t
I2C Bus Read/Write Signal
S
E
T
S
I
M
[
2
:
0
]
=
1
1
0
S
E
T
S
I
M
E
N
The SRW bit in the SIMC1 register defines whether the
slave device wishes to read data from the I2C bus or
write data to the I2C bus. The slave device should exam-
ine this bit to determine if it is to be a transmitter or a re-
ceiver. If the SRW flag is ²1² then this indicates that the
master device wishes to read data from the I2C bus,
therefore the slave device must be setup to send data to
the I2C bus as a transmitter. If the SRW flag is ²0² then
this indicates that the master wishes to send data to the
I2C bus, therefore the slave device must be setup to
read data from the I2C bus as a receiver.
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I2C Bus Slave Address Acknowledge Signal
I2C Bus Initialisation Flow Chart
After the master has transmitted a calling address, any
slave device on the I2C bus, whose own internal address
matches the calling address, must generate an ac-
knowledge signal. The acknowledge signal will inform
Rev. 1.60
163
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
the master that a slave device has accepted its calling
²0², before it can receive the next data byte. If the slave
transmitter does not receive an acknowledge bit signal
from the master receiver, then the slave transmitter will
release the SDA line to allow the master to send a STOP
signal to release the I2C Bus. The corresponding data
will be stored in the SIMD register. If setup as a transmit-
ter, the slave device must first write the data to be trans-
mitted into the SIMD register. If setup as a receiver, the
slave device must read the transmitted data from the
SIMD register.
address. If no acknowledge signal is received by the
master then a STOP signal must be transmitted by the
master to end the communication. When the HAAS flag
is high, the addresses have matched and the slave de-
vice must check the SRW flag to determine if it is to be a
transmitter or a receiver. If the SRW flag is high, the
slave device should be setup to be a transmitter so the
HTX bit in the SIMC1 register should be set to ²1². If the
SRW flag is low, then the microcontroller slave device
should be setup as a receiver and the HTX bit in the
SIMC1 register should be set to ²0².
When the slave receiver receives the data byte, it must
generate an acknowledge bit, known as TXAK, on the
9th clock. The slave device, which is setup as a trans-
mitter will check the RXAK bit in the SIMC1 register to
determine if it is to send another data byte, if not then it
will release the SDAline and await the receipt of a STOP
signal from the master.
I2C Bus Data and Acknowledge Signal
The transmitted data is 8-bits wide and is transmitted af-
ter the slave device has acknowledged receipt of its
slave address. The order of serial bit transmission is the
MSB first and the LSB last. After receipt of 8-bits of data,
the receiver must transmit an acknowledge signal, level
S
t
a
r
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0
1
0
1
0
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0
1
0
1
0
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7
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8
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P
Note: * When a slave address is matched, the device must be placed in either the transmit mode and then write data
to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to
release the SCL line.
I2C Communication Timing Diagram
Rev. 1.60
164
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
S
t
a
r
t
N
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A
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=
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I
I2C Bus ISR Flow Chart
Rev. 1.60
165
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Peripheral Clock Output
The Peripheral Clock Output allows the device to supply
external hardware with a clock signal synchronised to
the microcontroller clock.
for the Peripheral Clock Output can originate from either
the TM0 CCRP match frequency/2 or a divided ratio of
the internal fSYS clock. The PCKEN bit in the SIMC0 reg-
ister is the overall on/off control, setting PCKEN bit to
²1² enables the Peripheral Clock, setting PCKEN bit to
²0² disables it. The required division ratio of the system
clock is selected using the PCKP1 and PCKP0 bits in
the same register. If the device enters the SLEEP Mode
this will disable the Peripheral Clock output.
Peripheral Clock Operation
As the peripheral clock output pin, PCK, is shared with
I/O line, the required pin function is chosen via PCKEN
in the SIMC0 register. The Peripheral Clock function is
controlled using the SIMC0 register. The clock source
·
SIMC0 Register
Bit
7
6
SIM1
R/W
1
5
SIM0
R/W
1
4
PCKEN
R/W
0
3
PCKP1
R/W
0
2
PCKP0
R/W
0
1
SIMEN
R/W
0
0
Name
R/W
SIM2
R/W
1
¾
¾
¾
POR
Bit 7~5
SIM2, SIM1, SIM0: SIM operating mode control
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fTBC
100: SPI master mode; SPI clock is TM0 CCRP match frequency/2
101: SPI slave mode
110: I2C slave mode
111: Unused mode
These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C
or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock
frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced
from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external
Master device.
Bit 4
PCKEN: PCK output pin control
0: Disable
1: Enable
Bit 3~2
PCKP1, PCKP0: select PCK output pin frequency
00: fSYS
01: fSYS/4
10: fSYS/8
11: TM0 CCRP match frequency/2
Bit 1
SIMEN: SIM control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero
to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a
floating condition and the SIM operating current will be reduced to a minimum value. When the bit
is high the SIM interface is enabled. The SIM configuration option must have first enabled the
SIM interface for this bit to be effective. Note that when the SIMEN bit changes from low to high
the contents of the SPI control registers will be in an unknown condition and should therefore be
first initialised by the application program.
Bit 0
unimplemented, read as ²0²
Rev. 1.60
166
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer Module or an A/D converter requires
microcontroller attention, their corresponding interrupt
will enforce a temporary suspension of the main pro-
gram allowing the microcontroller to direct attention to
their respective needs. The device contains several ex-
ternal interrupt and internal interrupts functions. The ex-
ternal interrupts are generated by the action of the
external INT0~INT3 and PINT pins, while the internal in-
terrupts are generated by various internal functions
such as the TMs, Comparators, Time Base, LVD,
EEPROM, SIM and the A/D converter.
indicate the presence of an interrupt request. The nam-
ing convention of these follows a specific pattern. First is
listed an abbreviated interrupt type, then the (optional)
number of that interrupt followed by either an ²E² for en-
able/disable bit or ²F² for request flag.
Enable
Bit
Request
Flag
Function
Global
Notes
EMI
CPnE
INTnE
ADE
¾
¾
n = 0 or 1
n = 0~3
¾
Comparator
INTn Pin
A/D Converter
Multi-function
Time Base
SIM
CPnF
INTnF
ADF
MFnE
TBnE
SIME
LVE
MFnF
TBnF
SIMF
LVF
n = 0~5
n = 0 or 1
¾
Interrupt Registers
Overall interrupt control, which basically means the set-
ting of request flags when certain microcontroller condi-
tions occur and the setting of interrupt enable bits by the
application program, is controlled by a series of regis-
ters, located in the Special Purpose Data Memory, as
shown in the accompanying table. The number of regis-
ters depends upon the device chosen but fall into three
categories. The first is the INTC0~INTC3 registers
which setup the primary interrupts, the second is the
MFI0~MFI3 registers which setup the Multi-function in-
terrupts. Finally there is an INTEG register to setup the
external interrupt trigger edge type.
LVD
¾
EEPROM
PINT Pin
DEE
DEF
¾
XPE
XPF
¾
TnPE
TnAE
TnBE
TnPF
TnAF
TnBF
TM
n = 0~3
Interrupt Register Bit Naming Conventions
Each register contains a number of enable bits to enable
or disable individual registers as well as interrupt flags to
·
Interrupt Register Contents
¨
HT66F20
Bit
Name
7
¾
6
5
4
3
INT1S1
CP0E
ADE
MF3E
¾
2
INT1S0
INT1E
MF1E
TB1E
¾
1
0
INTEG
INTC0
INTC1
INTC2
MFI0
INT0S1
INT0E
MF0E
TB0E
T0AE
T1AE
XPE
INT0S0
EMI
¾
¾
¾
CP0F
MF1F
TB1F
¾
INT1F
MF0F
TB0F
T0AF
T1AF
XPF
INT0F
CP1F
MF2F
T0PF
T1PF
SIMF
¾
ADF
MF3F
¾
CP1E
MF2E
T0PE
T1PE
SIME
MFI1
¾
¾
¾
¾
MFI2
DEF
LVF
DEE
LVE
Rev. 1.60
167
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
¨
¨
HT66F30
Bit
Name
7
¾
6
5
4
3
INT1S1
CP0E
ADE
MF3E
¾
2
1
0
INTEG
INTC0
INTC1
INTC2
MFI0
INT1S0
INT1E
MF1E
TB1E
¾
INT0S1
INT0E
MF0E
TB0E
T0AE
T1AE
XPE
INT0S0
EMI
¾
¾
¾
CP0F
MF1F
TB1F
¾
INT1F
MF0F
TB0F
T0AF
T1AF
XPF
INT0F
CP1F
MF2F
T0PF
T1PF
SIMF
¾
ADF
MF3F
¾
CP1E
MF2E
T0PE
T1PE
SIME
MFI1
T1BF
LVF
T1BE
LVE
¾
¾
MFI2
DEF
DEE
HT66F40
Bit
Name
7
¾
6
5
4
3
2
1
0
INTEG
INTC0
INTC1
INTC2
MFI0
INT1S1
CP0E
ADE
INT1S0
INT1E
MF1E
TB1E
T2PE
T1BE
LVE
INT0S1
INT0E
MF0E
TB0E
T0AE
T1AE
XPE
INT0S0
EMI
¾
¾
¾
CP0F
MF1F
TB1F
T2PF
T1BF
LVF
INT1F
MF0F
TB0F
T0AF
T1AF
XPF
INT0F
CP1F
MF2F
T0PF
T1PF
SIMF
¾
ADF
MF3F
T2AF
¾
CP1E
MF2E
T0PE
T1PE
SIME
MF3E
T2AE
¾
MFI1
MFI2
DEF
DEE
HT66F50
Bit
Name
7
¾
6
5
4
3
INT1S1
CP0E
ADE
MF3E
T2AE
¾
2
1
0
INTEG
INTC0
INTC1
INTC2
MFI0
INT1S0
INT1E
MF1E
TB1E
T2PE
T1BE
LVE
INT0S1
INT0E
MF0E
TB0E
T0AE
T1AE
XPE
INT0S0
EMI
¾
¾
¾
CP0F
MF1F
TB1F
T2PF
T1BF
LVF
¾
INT1F
MF0F
TB0F
T0AF
T1AF
XPF
INT0F
CP1F
MF2F
T0PF
T1PF
SIMF
T3PF
¾
ADF
MF3F
T2AF
¾
CP1E
MF2E
T0PE
T1PE
SIME
T3PE
MFI1
MFI2
DEF
¾
DEE
¾
MFI3
T3AF
T3AE
¾
Rev. 1.60
168
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F60
Bit
Name
7
INT3S1
¾
6
5
4
3
2
1
0
INTEG
INTC0
INTC1
INTC2
INTC3
MFI0
INT3S0
INT2F
CP1F
MF3F
TB1F
T2PF
T1BF
LVF
INT2S1
INT1F
CP0F
MF2F
TB0F
T0AF
T1AF
XPF
INT2S0
INT0F
INT3F
MF1F
MF4F
T0PF
T1PF
SIMF
T3PF
INT1S1
INT2E
MF0E
ADE
MF5E
T2AE
¾
INT1S0
INT1E
CP1E
MF3E
TB1E
T2PE
T1BE
LVE
INT0S1
INT0E
CP0E
MF2E
TB0E
T0AE
T1AE
XPE
INT0S0
EMI
MF0F
ADF
MF5F
T2AF
¾
INT3E
MF1E
MF4E
T0PE
T1PE
SIME
T3PE
MFI1
MFI2
DEF
¾
DEE
¾
MFI3
T3AF
T3AE
¾
¾
·
INTEG Register
¨
HT66F20/HT66F30/HT66F40/HT66F50
Bit
Name
R/W
7
6
5
4
3
INT1S1
R/W
0
2
INT1S0
R/W
0
1
INT0S1
R/W
0
0
INT0S0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~4
Bit 3~2
unimplemented, read as ²0²
INT1S1, INT1S0: interrupt edge control for INT1 pin
00: disable
01: rising edge
10: falling edge
11: rising and falling edges
Bit 1~0
INT0S1, INT0S0: interrupt edge control for INT0 pin
00: disable
01: rising edge
10: falling edge
11: rising and falling edges
Rev. 1.60
169
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F60
Bit
Name
R/W
7
INT3S1
R/W
0
6
INT3S0
R/W
0
5
INT2S1
R/W
0
4
INT2S0
R/W
0
3
INT1S1
R/W
0
2
INT1S0
R/W
0
1
INT0S1
R/W
0
0
INT0S0
R/W
0
POR
Bit 7~6
INT3S1, INT3S0: Interrupt edge control for INT3 pin
00: disable
01: rising edge
10: falling edge
Bit 5~4
INT2S1, INT2S0: interrupt edge control for INT2 pin
00: disable
01: rising edge
10: falling edge
11: rising and falling edges
Bit 3~2
Bit 1~0
INT1S1, INT1S0: interrupt edge control for INT1 pin
00: disable
01: rising edge
10: falling edge
11: rising and falling edges
INT0S1, INT0S0: interrupt edge control for INT0 pin
00: disable
01: rising edge
10: falling edge
11: rising and falling edges
·
INTC0 Register
¨
HT66F20/HT66F30/HT66F40/HT66F50
Bit
Name
R/W
7
6
CP0F
R/W
0
5
INT1F
R/W
0
4
INT0F
R/W
0
3
CP0E
R/W
0
2
INT1E
R/W
0
1
INT0E
R/W
0
0
EMI
R/W
0
¾
¾
¾
POR
Bit 7
Bit 6
unimplemented, read as ²0²
CP0F: Comparator 0 interrupt request flag
0: no request
1: interrupt request
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT1F: INT1 interrupt request flag
0: no request
1: interrupt request
INT0F: INT0 interrupt request flag
0: no request
1: interrupt request
CP0E: Comparator 0 interrupt control
0: disable
1: enable
INT1E: INT1 interrupt control
0: disable
1: enable
INT0E: INT0 interrupt control
0: disable
1: enable
EMI: Global interrupt control
0: disable
1: enable
Rev. 1.60
170
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F60
Bit
Name
R/W
7
6
INT2F
R/W
0
5
INT1F
R/W
0
4
INT0F
R/W
0
3
INT2E
R/W
0
2
INT1E
R/W
0
1
INT0E
R/W
0
0
EMI
R/W
0
¾
¾
¾
POR
Bit 7
Bit 6
unimplemented, read as ²0²
INT2F: INT2 interrupt request flag
0: no request
1: interrupt request
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT1F: INT1 interrupt request flag
0: no request
1: interrupt request
INT0F: INT0 interrupt request flag
0: no request
1: interrupt request
INT2E: INT2 interrupt control
0: disable
1: enable
INT1E: INT1 interrupt control
0: disable
1: enable
INT0E: INT0 interrupt control
0: disable
1: enable
EMI: Global interrupt control
0: disable
1: enable
Rev. 1.60
171
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
INTC1 Register
¨
HT66F20/HT66F30/HT66F40/HT66F50
Bit
Name
R/W
7
6
MF1F
R/W
0
5
MF0F
R/W
0
4
CP1F
R/W
0
3
2
MF1E
R/W
0
1
MF0E
R/W
0
0
CP1E
R/W
0
ADF
R/W
0
ADE
R/W
0
POR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADF: A/D Converter Interrupt Request Flag
0: no request
1: interrupt request
MF1F: Multi-function Interrupt 1 Request Flag
0: no request
1: interrupt request
MF0F: Multi-function Interrupt 0 Request Flag
0: no request
1: interrupt request
CP1F: Comparator 1 Interrupt Request Flag
0: no request
1: interrupt request
ADE: A/D Converter Interrupt Control
0: disable
1: enable
MF1E: Multi-function Interrupt 1 Control
0: disable
1: enable
MF0E: Multi-function Interrupt 0 Control
0: disable
1: enable
CP1E: Comparator 1 Interrupt Control
0: Disable
1: Enable
Rev. 1.60
172
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F60
Bit
Name
R/W
7
MF0F
R/W
0
6
CP1F
R/W
0
5
CP0F
R/W
0
4
INT3F
R/W
0
3
MF0E
R/W
0
2
CP1E
R/W
0
1
CP0E
R/W
0
0
INT3E
R/W
0
POR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MF0F: Multi-function Interrupt 0 Request Flag
0: no request
1: interrupt request
CP1F: Comparator 1 Interrupt Request Flag
0: no request
1: interrupt request
CP0F: Comparator 0 Interrupt Request Flag
0: no request
1: interrupt request
INT3F: INT3 Interrupt Request Flag
0: no request
1: interrupt request
MF0E: Multi-function Interrupt 0 Control
0: disable
1: enable
CP1E: Comparator 1 Interrupt Control
0: disable
1: enable
CP0E: Comparator 0 Interrupt Control
0: disable
1: enable
INT3E: INT3 Interrupt Control
0: disable
1: enable
Rev. 1.60
173
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
INTC2 Register
¨
HT66F20/HT66F30/HT66F40/HT66F50
Bit
Name
R/W
7
MF3F
R/W
0
6
TB1F
R/W
0
5
TB0F
R/W
0
4
MF2F
R/W
0
3
MF3E
R/W
0
2
TB1E
R/W
0
1
TB0E
R/W
0
0
MF2E
R/W
0
POR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MF3F: Multi-function Interrupt 3 Request Flag
0: no request
1: interrupt request
TB1F: Time Base 1 Interrupt Request Flag
0: no request
1: interrupt request
TB0F: Time Base 0 Interrupt Request Flag
0: no request
1: interrupt request
MF2F: Multi-function Interrupt 2 Request Flag
0: no request
1: interrupt request
MF3E: Multi-function Interrupt 3 Control
0: disable
1: enable
TB1E: Time Base 1 Interrupt Control
0: disable
1: enable
TB0E: Time Base 0 Interrupt Control
0: disable
1: enable
MF2E: Multi-function Interrupt 2 Control
0: disable
1: enable
Rev. 1.60
174
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F60
Bit
Name
R/W
7
6
MF3F
R/W
0
5
MF2F
R/W
0
4
MF1F
R/W
0
3
2
MF3E
R/W
0
1
MF2E
R/W
0
0
MF1E
R/W
0
ADF
R/W
0
ADE
R/W
0
POR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADF: A/D Converter Interrupt Request Flag
0: no request
1: interrupt request
MF3F: Multi-function Interrupt 3 Request Flag
0: no request
1: interrupt request
MF2F: Multi-function Interrupt 2 Request Flag
0: no request
1: interrupt request
MF1F: Multi-function Interrupt 1 Request Flag
0: no request
1: interrupt request
ADE: A/D Converter Interrupt Control
0: disable
1: enable
MF3E: Multi-function Interrupt 3 Control
0: disable
1: enable
MF2E: Multi-function Interrupt 2 Control
0: disable
1: enable
MF1E: Multi-function Interrupt 1 Control
0: disable
1: enable
Rev. 1.60
175
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
INTC3 Register
¨
HT66F60
Bit
Name
R/W
7
MF5F
R/W
0
6
TB1F
R/W
0
5
TB0F
R/W
0
4
MF4F
R/W
0
3
MF5E
R/W
0
2
TB1E
R/W
0
1
TB0E
R/W
0
0
MF4E
R/W
0
POR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MF5F: Multi-function interrupt 5 request flag
0: no request
1: interrupt request
TB1F: Time Base 1 interrupt request flag
0: no request
1: interrupt request
TB0F: Time Base 0 interrupt request flag
0: no request
1: interrupt request
MF4F: Multi-function interrupt 4 request flag
0: no request
1: interrupt request
MF5E: Multi-function interrupt 5 control
0: disable
1: enable
TB1E: Time Base 1 interrupt control
0: disable
1: enable
TB0E: Time Base 0 interrupt control
0: disable
1: enable
MF4E: Multi-function interrupt 4 control
0: disable
1: enable
·
MFI0 Register
¨
HT66F20/HT66F30
Bit
Name
R/W
7
6
5
T0AF
R/W
0
4
T0PF
R/W
0
3
2
1
T0AE
R/W
0
0
T0PE
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~6
Bit 5
unimplemented, read as ²0²
T0AF: TM0 Comparator A match interrupt request flag
0: no request
1: interrupt request
Bit 4
T0PF: TM0 Comparator P match interrupt request flag
0: no request
1: interrupt request
Bit 3~2
Bit 1
unimplemented, read as ²0²
T0AE: TM0 Comparator A match interrupt control
0: disable
1: enable
Bit 0
T0PE: TM0 Comparator P match interrupt control
0: disable
1: enable
Rev. 1.60
176
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
T2AF
R/W
0
6
T2PF
R/W
0
5
T0AF
R/W
0
4
T0PF
R/W
0
3
T2AE
R/W
0
2
T2PE
R/W
0
1
T0AE
R/W
0
0
T0PE
R/W
0
POR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T2AF: TM2 Comparator A match interrupt request flag
0: no request
1: interrupt request
T2PF: TM2 Comparator P match interrupt request flag
0: no request
1: interrupt request
T0AF: TM0 Comparator A match interrupt request flag
0: no request
1: interrupt request
T0PF: TM0 Comparator P match interrupt request flag
0: no request
1: interrupt request
T2AE: TM2 Comparator A match interrupt control
0: disable
1: enable
T2PE: TM2 Comparator P match interrupt control
0: disable
1: enable
T0AE: TM0 Comparator A match interrupt control
0: disable
1: enable
T0PE: TM0 Comparator P match interrupt control
0: disable
1: enable
·
MFI1 Register
¨
HT66F20
Bit
Name
R/W
7
6
5
T1AF
R/W
0
4
T1PF
R/W
0
3
2
1
T1AE
R/W
0
0
T1PE
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~6
Bit 5
unimplemented, read as ²0²
T1AF: TM1 Comparator A match interrupt request flag
0: no request
1: interrupt request
Bit 4
T1PF: TM1 Comparator P match interrupt request flag
0: no request
1: interrupt request
Bit 3~2
Bit 1
unimplemented, read as ²0²
T1AE: TM1 Comparator A match interrupt control
0: disable
1: enable
Bit 0
T1PE: TM1 Comparator P match interrupt control
0: disable
1: enable
Rev. 1.60
177
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F30/HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
6
T1BF
R/W
0
5
T1AF
R/W
0
4
T1PF
R/W
0
3
2
T1BE
R/W
0
1
T1AE
R/W
0
0
T1PE
R/W
0
¾
¾
¾
¾
¾
¾
POR
Bit 7
Bit 6
unimplemented, read as ²0²
T1BF: TM1 Comparator B match interrupt request flag
0: no request
1: interrupt request
Bit 5
Bit 4
T1AF: TM1 Comparator A match interrupt request flag
0: no request
1: interrupt request
T1PF: TM1 Comparator P match interrupt request flag
0: no request
1: interrupt request
Bit 3
Bit 2
unimplemented, read as ²0²
T1BE: TM1 Comparator B match interrupt control
0: disable
1: enable
Bit 1
Bit 0
T1AE: TM1 Comparator A match interrupt control
0: disable
1: enable
T1PE: TM1 Comparator P match interrupt control
0: disable
1: enable
·
MFI2 Register
Bit
Name
R/W
7
6
5
4
SIMF
R/W
0
3
2
1
0
SIME
R/W
0
DEF
R/W
0
LVF
R/W
0
XPF
R/W
0
DEE
R/W
0
LVE
R/W
0
XPE
R/W
0
POR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DEF: Data EEPROM interrupt request flag
0: No request
1: Interrupt request
LVF: LVD interrupt request flag
0: No request
1: Interrupt request
XPF: External peripheral interrupt request flag
0: No request
1: Interrupt request
SIMF: SIM interrupt request flag
0: No request
1: Interrupt request
DEE: Data EEPROM Interrupt Control
0: Disable
1: Enable
LVE: LVD Interrupt Control
0: Disable
1: Enable
XPE: External Peripheral Interrupt Control
0: Disable
1: Enable
SIME: SIM Interrupt Control
0: Disable
1: Enable
Rev. 1.60
178
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
MFI3 Register
¨
HT66F50/HT66F60
Bit
Name
R/W
7
6
5
T3AF
R/W
0
4
T3PF
R/W
0
3
2
1
T3AE
R/W
0
0
T3PE
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~6
Bit 5
unimplemented, read as ²0²
T3AF: TM3 Comparator A match interrupt request flag
0: no request
1: interrupt request
Bit 4
T3PF: TM3 Comparator P match interrupt request flag
0: no request
1: interrupt request
Bit 3~2
Bit 1
unimplemented, read as ²0²
T3AE: TM3 Comparator A match interrupt control
0: disable
1: enable
Bit 0
T3PE: TM3 Comparator P match interrupt control
0: disable
1: enable
Interrupt Operation
The various interrupt enable bits, together with their as-
sociated request flags, are shown in the accompanying
diagrams with their order of priority. Some interrupt
sources have their own individual vector while others
share the same multi-function interrupt vector. Once an
interrupt subroutine is serviced, all the other interrupts
will be blocked, as the global interrupt enable bit, EMI bit
will be cleared automatically. This will prevent any fur-
ther interrupt nesting from occurring. However, if other
interrupt requests occur during this interval, although
the interrupt will not be immediately serviced, the re-
quest flag will still be recorded.
When the conditions for an interrupt event occur, such
as a TM Comparator P, Comparator A or Comparator B
match or A/D conversion completion etc, the relevant in-
terrupt request flag will be set. Whether the request flag
actually generates a program jump to the relevant inter-
rupt vector is determined by the condition of the interrupt
enable bit. If the enable bit is set high then the program
will jump to its relevant vector; if the enable bit is zero
then although the interrupt request flag is set an actual
interrupt will not be generated and the program will not
jump to the relevant interrupt vector. The global interrupt
enable bit, if cleared to zero, will disable all interrupts.
If an interrupt requires immediate servicing while the
program is already in another interrupt service routine,
the EMI bit should be set after entering the routine, to al-
low interrupt nesting. If the stack is full, the interrupt re-
quest will not be acknowledged, even if the related
interrupt is enabled, until the Stack Pointer is decre-
mented. If immediate service is desired, the stack must
be prevented from becoming full. In case of simulta-
neous requests, the accompanying diagram shows the
priority that is applied. All of the interrupt request flags
when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occur-
ring the corresponding flag should be set before the de-
vice is in SLEEP or IDLE Mode.
When an interrupt is generated, the Program Counter,
which stores the address of the next instruction to be ex-
ecuted, will be transferred onto the stack. The Program
Counter will then be loaded with a new address which
will be the value of the corresponding interrupt vector.
The microcontroller will then fetch its next instruction
from this interrupt vector. The instruction at this vector
will usually be a ²JMP² which will jump to another sec-
tion of program which is known as the interrupt service
routine. Here is located the code to control the appropri-
ate interrupt. The interrupt service routine must be ter-
minated with a ²RETI², which retrieves the original
Program Counter address from the stack and allows the
microcontroller to continue with normal execution at the
point where the interrupt occurred.
Rev. 1.60
179
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
EMI auto disabled in ISR
Legend
Interrupt Request
Flags
Enable
Bits
Master
Enable
Vector
Request Flag – no auto reset in ISR
xxF
xxF
xxE
Priority
High
Name
Request Flag – auto reset in ISR
Enable Bit
INT0 Pin
INT0F
INT0E
INT1E
EMI
EMI
04H
08H
INT1 Pin
INT1F
Comp. 0
Comp. 1
CP0F
CP1F
CP0E
CP1E
EMI
EMI
Interrupt Request
Flags
Enable
Bits
0CH
10H
Name
TM0 P
T0PF
T0AF
T0PE
T0AE
TM0 A
M. Funct. 0 MF0F
M. Funct. 1 MF1F
MF0E
MF1E
ADE
EMI
EMI
EMI
14H
18H
1CH
TM1 P
TM1 A
TM1 B
T1PF
T1AF
T1BF
T1PE
T1AE
T1BE
A/D
ADF
SIM SIMF
PINT Pin
SIME
XPE
M. Funct. 2 MF2F
MF2E
EMI
20H
XPF
Time Base 0 TB0F
Time Base 1 TB1F
TB0E
TB1E
EMI
EMI
24H
28H
LVD
LVF
LVE
DEE
EEPROM DEF
M. Funct. 3 MF3F
MF3E
EMI
2CH
Low
Interrupts contained within
Multi-Function Interrupts
HT66F30 only
Interrupt Structure - HT66F20/HT66F30
Rev. 1.60
180
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
EMI auto disabled in ISR
Legend
Interrupt Request
Flags
Enable
Bits
Master
Enable
Vector
Priority
High
Request Flag – no auto reset in ISR
xxF
xxF
xxE
Name
Request Flag – auto reset in ISR
Enable Bit
INT0 Pin
INT0F
INT0E
INT1E
EMI
EMI
04H
08H
INT1 Pin
INT1F
Comp. 0
Comp. 1
CP0F
CP1F
CP0E
CP1E
EMI
EMI
0CH
10H
Interrupt Request
Name Flags
Enable
Bits
TM0 P TP0AF
TM0 A TP0AF
T0PE
T0AE
M. Funct. 0 MF0F
MF0E
EMI
14H
TM2 P
TM2 A
T2PF
T2AF
T2PE
T2AE
TM1 P
TM1 A
TM1 B
T1PF
T1AF
T1BF
T1PE
T1AE
T1BE
M. Funct. 1 MF1F
MF1E
ADE
EMI
EMI
18H
1CH
A/D
ADF
TM3 P
TM3 A
T3PF
T3AF
T3PE
T3AE
SIM SIMF
PINT Pin XPF
SIME
XPE
M. Funct. 2 MF2F
Time Base 0 TB0F
Time Base 1 TB1F
M. Funct. 3 MF3F
MF2E
TB0E
TB1E
MF3E
EMI
EMI
EMI
EMI
20H
24H
28H
2CH
LVD
LVF
LVE
EEPROM DEF
DEE
Low
Interrupts contained within
Multi-Function Interrupts
HT66F50 only
Interrupt Structure - HT66F40/HT66F50
Rev. 1.60
181
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
EMI auto disabled in ISR
Interrupt Request
Flags
Enable
Bits
Master
Enable
Vector
04H
Priority
High
Name
Legend
INT0 Pin
INT0F
INT0E
INT1E
INT2E
INT3E
EMI
EMI
EMI
EMI
Request Flag – no auto reset in ISR
Request Flag – auto reset in ISR
Enable Bit
xxF
xxF
xxE
INT1 Pin
INT2 Pin
INT3 Pin
INT1F
INT2F
INT3F
08H
0CH
10H
Interrupt Request
Flags
Enable
Bits
Comp. 0
Comp. 1
CP0F
CP1F
CP0E
CP1E
EMI
EMI
14H
18H
Name
TM0 P
TM0 A
T0PF
T0PE
1CH
T0AF
T0AE
M. Funct. 0 MF0F
M. Funct. 1 MF1F
MF0E
MF1E
MF2E
EMI
EMI
EMI
TM1 P
TM1 A
TM1 B
T1PF
T1AF
T1BF
T1PE
T1AE
T1BE
20H
24H
TM2 P
TM2 A
T2PF
T2AF
T2PE
T2AE
M. Funct. 2 MF2F
M. Funct. 3 MF3F
TM3 P
TM3 A
T3PF
T3AF
T3PE
T3AE
MF3E
ADE
EMI
EMI
EMI
28H
A/D
ADF
2CH
30H
SIM SIMF
PINT Pin XPF
SIME
XPE
M. Funct. 4 MF4F
MF4E
Time Base 0 TB0F
Time Base 1 TB1F
TB0E
TB1E
EMI
EMI
34H
38H
LVD
LVF
LVE
EEPROM DEF
DEE
M. Funct. 5 MF5F
MF5E
EMI
3CH
Low
Interrupts contained within
Multi-Function Interrupts
Interrupt Structure - HT66F60
Rev. 1.60
182
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
External Interrupt
the TM Interrupts, SIM Interrupt, External Peripheral In-
terrupt, LVD interrupt and EEPROM Interrupt.
The external interrupts are controlled by signal transi-
tions on the pins INT0~INT3. An external interrupt re-
quest will take place when the external interrupt request
flags, INT0F~INT3F, are set, which will occur when a
transition, whose type is chosen by the edge select bits,
appears on the external interrupt pins. To allow the pro-
gram to branch to its respective interrupt vector ad-
dress, the global interrupt enable bit, EMI, and
respective external interrupt enable bit, INT0E~INT3E,
must first be set. Additionally the correct interrupt edge
type must be selected using the INTEG register to en-
able the external interrupt function and to choose the
trigger edge type. As the external interrupt pins are
pin-shared with I/O pins, they can only be configured as
external interrupt pins if their external interrupt enable
bit in the corresponding interrupt register has been set.
The pin must also be setup as an input by setting the
corresponding bit in the port control register. When the
interrupt is enabled, the stack is not full and the correct
transition type appears on the external interrupt pin, a
subroutine call to the external interrupt vector, will take
place. When the interrupt is serviced, the external inter-
rupt request flags, INT0F~INT3F, will be automatically
reset and the EMI bit will be automatically cleared to dis-
able other interrupts. Note that any pull-high resistor se-
lections on the external interrupt pins will remain valid
even if the pin is used as an external interrupt input.
A Multi-function interrupt request will take place when
any of the Multi-function interrupt request flags,
MF0F~MF5F are set. The Multi-function interrupt flags
will be set when any of their included functions generate
an interrupt request flag. To allow the program to branch
to its respective interrupt vector address, when the
Multi-function interrupt is enabled and the stack is not
full, and either one of the interrupts contained within
each of Multi-function interrupt occurs, a subroutine call
to one of the Multi-function interrupt vectors will take
place. When the interrupt is serviced, the related
Multi-Function request flag, will be automatically reset
and the EMI bit will be automatically cleared to disable
other interrupts.
However, it must be noted that, although the
Multi-function Interrupt flags will be automatically reset
when the interrupt is serviced, the request flags from the
original source of the Multi-function interrupts, namely
the TM Interrupts, SIM Interrupt, External Peripheral In-
terrupt, LVD interrupt and EEPROM Interrupt will not be
automatically reset and must be manually reset by the
application program.
A/D Converter Interrupt
The A/D Converter Interrupt is controlled by the termina-
tion of an A/D conversion process. An A/D Converter In-
terrupt request will take place when the A/D Converter
Interrupt request flag, ADF, is set, which occurs when
the A/D conversion process finishes. To allow the pro-
gram to branch to its respective interrupt vector ad-
dress, the global interrupt enable bit, EMI, and A/D
Interrupt enable bit, ADE, must first be set. When the in-
terrupt is enabled, the stack is not full and the A/D con-
version process has ended, a subroutine call to the A/D
Converter Interrupt vector, will take place. When the in-
terrupt is serviced, the A/D Converter Interrupt flag,
ADF, will be automatically cleared. The EMI bit will also
be automatically cleared to disable other interrupts.
The INTEG register is used to select the type of active
edge that will trigger the external interrupt. A choice of
either rising or falling or both edge types can be chosen
to trigger an external interrupt. Note that the INTEG reg-
ister can also be used to disable the external interrupt
function.
Comparator Interrupt
The comparator interrupt is controlled by the two inter-
nal comparators. A comparator interrupt request will
take place when the comparator interrupt request flags,
CP0F or CP1F, are set, a situation that will occur when
the comparator output changes state. To allow the pro-
gram to branch to its respective interrupt vector ad-
dress, the global interrupt enable bit, EMI, and
comparator interrupt enable bits, CP0E and CP1E, must
first be set. When the interrupt is enabled, the stack is
not full and the comparator inputs generate a compara-
tor output transition, a subroutine call to the comparator
interrupt vector, will take place. When the interrupt is
serviced, the external interrupt request flags, will be au-
tomatically reset and the EMI bit will be automatically
cleared to disable other interrupts.
Time Base Interrupts
The function of the Time Base Interrupts is to provide reg-
ular time signal in the form of an internal interrupt. They
are controlled by the overflow signals from their respec-
tive timer functions. When these happens their respec-
tive interrupt request flags, TB0F or TB1F will be set. To
allow the program to branch to their respective interrupt
vector addresses, the global interrupt enable bit, EMI and
Time Base enable bits, TB0E or TB1E, must first be set.
When the interrupt is enabled, the stack is not full and the
Time Base overflows, a subroutine call to their respective
vector locations will take place. When the interrupt is ser-
viced, the respective interrupt request flag, TB0F or
TB1F, will be automatically reset and the EMI bit will be
cleared to disable other interrupts.
Multi-function Interrupt
Within these devices there are up to six Multi-function
interrupts. Unlike the other independent interrupts,
these interrupts have no independent source, but rather
are formed from other existing interrupt sources, namely
Rev. 1.60
183
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources origi-
nate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is se-
lected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges.
The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several
different sources, as shown in the System Operating Mode section.
·
TBC Register
Bit
Name
R/W
7
TBON
R/W
0
6
TBCK
R/W
0
5
TB11
R/W
1
4
TB10
R/W
1
3
LXTLP
R/W
0
2
TB02
R/W
1
1
TB01
R/W
1
0
TB00
R/W
1
POR
Bit 7
TBON: TB0 and TB1 Control
0: Disable
1: Enable
Bit 6
TBCK: Select fTB Clock
0: fTBC
1: fSYS/4
Bit 5~4
TB11~TB10: Select Time Base 1 Time-out Period
00: 4096/fTB
01: 8192/fTB
10: 16384/fTB
11: 32768/fTB
Bit 3
LXTLP: LXT Low Power Control
0: Disable
1: Enable
Bit 2~0
TB02~TB00: Select Time Base 0 Time-out Period
000: 256/fTB
001: 512/fTB
010: 1024/fTB
011: 2048/fTB
100: 4096/fTB
101: 8192/fTB
110: 16384/fTB
111: 32768/fTB
T
B
0
2
~
T
B
0
0
f
S
Y
S
L
X
T
8
1
5
T
T
i
i
m
m
e
B
B
a
a
s
s
e
e
0
1
I
I
n
n
t
t
e
e
M
U
X
¸
2
~
2
M
U
X
f
T
B
f
T
B
C
L
I
R
C
1
2
1
5
e
¸
2
~
2
C
o
n
f
i
g
u
r
a
t
i
o
n
B
T
B
C
K
i
t
O
p
t
i
o
n
T
B
1
1
~
T
B
1
0
Time Base Interrupt
Rev. 1.60
184
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Serial Interface Module Interrupt
must first be set. When the interrupt is enabled, the
stack is not full and an EEPROM Write or Read cycle
The Serial Interface Module Interrupt, also known as the
SIM interrupt, is contained within the Multi-function In-
terrupt. A SIM Interrupt request will take place when the
SIM Interrupt request flag, SIMF, is set, which occurs
when a byte of data has been received or transmitted by
the SIM interface. To allow the program to branch to its
respective interrupt vector address, the global interrupt
enable bit, EMI, and the Serial Interface Interrupt enable
bit, SIME, and Muti-function interrupt enable bits, must
first be set. When the interrupt is enabled, the stack is
not full and a byte of data has been transmitted or re-
ceived by the SIM interface, a subroutine call to the re-
spective Multi-function Interrupt vector, will take place.
When the Serial Interface Interrupt is serviced, the EMI
bit will be automatically cleared to disable other inter-
rupts, however only the Multi-function interrupt request
flag will be also automatically cleared. As the SIMF flag
will not be automatically cleared, it has to be cleared by
the application program.
ends, a subroutine call to the respective Multi-function
Interrupt vector, will take place. When the EEPROM In-
terrupt is serviced, the EMI bit will be automatically
cleared to disable other interrupts, however only the
Multi-function interrupt request flag will be also automat-
ically cleared. As the DEF flag will not be automatically
cleared, it has to be cleared by the application program.
LVD Interrupt
The Low Voltage Detector Interrupt is contained within
the Multi-function Interrupt. An LVD Interrupt request will
take place when the LVD Interrupt request flag, LVF, is
set, which occurs when the Low Voltage Detector func-
tion detects a low power supply voltage. To allow the
program to branch to its respective interrupt vector ad-
dress, the global interrupt enable bit, EMI, Low Voltage
Interrupt enable bit, LVE, and associated Multi-function
interrupt enable bit, must first be set. When the interrupt
is enabled, the stack is not full and a low voltage condi-
tion occurs, a subroutine call to the Multi-function Inter-
rupt vector, will take place. When the Low Voltage
Interrupt is serviced, the EMI bit will be automatically
cleared to disable other interrupts, however only the
Multi-function interrupt request flag will be also automat-
ically cleared. As the LVF flag will not be automatically
cleared, it has to be cleared by the application program.
External Peripheral Interrupt
The External Peripheral Interrupt operates in a similar
way to the external interrupt and is contained within the
Multi-function Interrupt. A Peripheral Interrupt request
will take place when the External Peripheral Interrupt re-
quest flag, XPF, is set, which occurs when a negative
edge transition appears on the PINT pin. To allow the
program to branch to its respective interrupt vector ad-
dress, the global interrupt enable bit, EMI, external pe-
ripheral interrupt enable bit, XPE, and associated
Multi-function interrupt enable bit, must first be set.
When the interrupt is enabled, the stack is not full and a
negative transition appears on the External Peripheral
Interrupt pin, a subroutine call to the respective
Multi-function Interrupt, will take place. When the Exter-
nal Peripheral Interrupt is serviced, the EMI bit will be
automatically cleared to disable other interrupts, how-
ever only the Multi-function interrupt request flag will be
also automatically cleared.
TM Interrupts
The Compact and Standard Type TMs have two inter-
rupts each, while the Enhanced Type TM has three in-
terrupts. All of the TM interrupts are contained within the
Multi-function Interrupts. For each of the Compact and
Standard Type TMs there are two interrupt request flags
TnPF and TnAF and two enable bits TnPE and TnAE.
For the Enhanced Type TM there are three interrupt re-
quest flags TnPF, TnAF and TnBF and three enable bits
TnPE, TnAE and TnBE. A TM interrupt request will take
place when any of the TM request flags are set, a situa-
tion which occurs when a TM comparator P, A or B
match situation happens.
As the XPF flag will not be automatically cleared, it has
to be cleared by the application program. The external
peripheral interrupt pin is pin-shared with several other
pins with different functions. It must therefore be prop-
erly configured to enable it to operate as an External Pe-
ripheral Interrupt pin.
To allow the program to branch to its respective interrupt
vector address, the global interrupt enable bit, EMI, re-
spective TM Interrupt enable bit, and relevant
Multi-function Interrupt enable bit, MFnE, must first be
set. When the interrupt is enabled, the stack is not full
and a TM comparator match situation occurs, a subrou-
tine call to the relevant Multi-function Interrupt vector lo-
cations, will take place. When the TM interrupt is
serviced, the EMI bit will be automatically cleared to dis-
able other interrupts, however only the related MFnF
flag will be automatically cleared. As the TM interrupt re-
quest flags will not be automatically cleared, they have
to be cleared by the application program.
EEPROM Interrupt
The EEPROM Interrupt, is contained within the
Multi-function Interrupt. An EEPROM Interrupt request
will take place when the EEPROM Interrupt request
flag, DEF, is set, which occurs when an EEPROM Write
or Read cycle ends. To allow the program to branch to
its respective interrupt vector address, the global inter-
rupt enable bit, EMI, EEPROM Interrupt enable bit,
DEE, and associated Multi-function interrupt enable bit,
Rev. 1.60
185
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Interrupt Wake-up Function
It is recommended that programs do not use the ²CALL²
instruction within the interrupt service subroutine. Inter-
Each of the interrupt functions has the capability of wak-
ing up the microcontroller when in the SLEEP or IDLE
Mode. A wake-up is generated when an interrupt re-
quest flag changes from low to high and is independent
of whether the interrupt is enabled or not. Therefore,
even though the device is in the SLEEP or IDLE Mode
and its system oscillator stopped, situations such as ex-
ternal edge transitions on the external interrupt pins, a
low power supply voltage or comparator input change
may cause their respective interrupt flag to be set high
and consequently generate an interrupt. Care must
therefore be taken if spurious wake-up situations are to
be avoided. If an interrupt wake-up function is to be dis-
abled then the corresponding interrupt request flag
should be set high before the device enters the SLEEP
or IDLE Mode. The interrupt enable bits have no effect
on the interrupt wake-up function.
rupts often occur in an unpredictable manner or need to
be serviced immediately. If only one stack is left and the
interrupt is not well controlled, the original control se-
quence will be damaged once a CALL subroutine is exe-
cuted in the interrupt subroutine.
Every interrupt has the capability of waking up the
microcontroller when it is in SLEEP or IDLE Mode, the
wake up being generated when the interrupt request
flag changes from low to high. If it is required to prevent
a certain interrupt from waking up the microcontroller
then its respective request flag should be first set high
before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack,
then when the interrupt is serviced, if the contents of the
accumulator, status register or other registers are al-
tered by the interrupt service program, their contents
should be saved to the memory at the beginning of the
interrupt service routine.
Programming Considerations
By disabling the relevant interrupt enable bits, a re-
quested interrupt can be prevented from being serviced,
however, once an interrupt request flag is set, it will re-
main in this condition in the interrupt register until the
corresponding interrupt is serviced or until the request
flag is cleared by the application program.
To return from an interrupt subroutine, either a RET or
RETI instruction may be executed. The RETI instruction
in addition to executing a return to the main program
also automatically sets the EMI bit high to allow further
interrupts. The RET instruction however only executes a
return to the main program leaving the EMI bit in its
present zero state and therefore disabling the execution
of further interrupts.
Where a certain interrupt is contained within a
Multi-function interrupt, then when the interrupt service
routine is executed, as only the Multi-function interrupt
request flags, MF0F~MF5F, will be automatically
cleared, the individual request flag for the function
needs to be cleared by the application program.
Rev. 1.60
186
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Power Down Mode and Wake-up
Entering the IDLE or SLEEP Mode
Wake-up
There is only one way for the device to enter the SLEEP
or IDLE Mode and that is to execute the ²HALT² instruc-
tion in the application program. When this instruction is
executed, the following will occur:
After the system enters the SLEEP or IDLE Mode, it can
be woken up from one of various sources listed as follows:
·
·
·
·
An external reset
An external falling edge on Port A
A system interrupt
·
·
·
The system clock will be stopped and the application
program will stop at the ²HALT² instruction.
A WDT overflow
The Data Memory contents and registers will maintain
their present condition.
If the system is woken up by an external reset, the de-
vice will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the ac-
tual source of the wake-up can be determined by exam-
ining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the fSUB
clock source and the WDT is enabled. The WDT will
stop if its clock source originates from the system clock.
·
·
The I/O ports will maintain their present condition.
In the status register, the Power Down flag, PDF, will be
set and the Watchdog time-out flag, TO, will be cleared.
Standby Current Considerations
As the main reason for entering the SLEEP or IDLE
Mode is to keep the current consumption of the device
to as low a value as possible, perhaps only in the order
of several micro-amps, there are other considerations
which must also be taken into account by the circuit de-
signer if the power consumption is to be minimised.
Special attention must be made to the I/O pins on the
device. All high-impedance input pins must be con-
nected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. This also applies to de-
vices which have different package types, as there may
be unbonbed pins. These must either be setup as out-
puts or if setup as inputs must have pull-high resistors
connected. Care must also be taken with the loads,
which are connected to I/O pins, which are setup as out-
puts. These should be placed in a condition in which
minimum current is drawn or connected only to external
circuits that do not draw current, such as other CMOS
inputs. Also note that additional standby current will also
be required if the configuration options have enabled
the LIRC oscillator.
Each pin on Port A can be setup using the PAWU regis-
ter to permit a negative transition on the pin to wake-up
the system. When a Port A pin wake-up occurs, the pro-
gram will resume execution at the instruction following
the ²HALT² instruction.
If the system is woken up by an interrupt, then two possi-
ble situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume exe-
cution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be ser-
viced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set high before
entering the SLEEP or IDLE Mode, the wake-up func-
tion of the related interrupt will be disabled.
Rev. 1.60
187
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Low Voltage Detector - LVD
Each device has a Low Voltage Detector function, also
known as LVD. This enabled the device to monitor the
power supply voltage, VDD, and provide a warning signal
should it fall below a certain level. This function may be
especially useful in battery applications where the sup-
ply voltage will gradually reduce as the battery ages, as
it allows an early warning battery low signal to be gener-
ated. The Low Voltage Detector also has the capability
of generating an interrupt signal.
fixed voltages below which a low voltage condition will
be detemined. A low voltage condition is indicated when
the LVDO bit is set. If the LVDO bit is low, this indicates
that the VDD voltage is above the preset low voltage
value. The LVDEN bit is used to control the overall
on/off function of the low voltage detector. Setting the bit
high will enable the low voltage detector. Clearing the bit
to zero will switch off the internal low voltage detector
circuits. As the low voltage detector will consume a cer-
tain amount of power, it may be desirable to switch off
the circuit when not in use, an important consideration in
power sensitive battery powered applications.
LVD Register
The Low Voltage Detector function is controlled using a
single register with the name LVDC. Three bits in this
register, VLVD2~VLVD0, are used to select one of eight
·
LVDC Register
Bit
Name
R/W
7
6
5
LVDO
R
4
LVDEN
R/W
0
3
2
VLVD2
R/W
0
1
VLVD1
R/W
0
0
VLVD0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
0
Bit 7~6
Bit 5
unimplemented, read as ²0²
LVDO: LVD Output Flag
0: No Low Voltage Detect
1: Low Voltage Detect
Bit
LVDEN: Low Voltage Detector Control
0: Disable
1: Enable
Bit 3
unimplemented, read as ²0²
Bit 2~0
VLVD2 ~ VLVD0: Select LVD Voltage
000: 2.0V
001: 2.2V
010: 2.4V
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.4V
Rev. 1.60
188
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
LVD Operation
LCD Operation
The Low Voltage Detector function operates by compar-
ing the power supply voltage, VDD, with a pre-specified
voltage level stored in the LVDC register. This has a
range of between 2.0V and 4.4V. When the power sup-
ply voltage, VDD, falls below this pre-determined value,
the LVDO bit will be set high indicating a low power sup-
ply voltage condition. The Low Voltage Detector func-
tion is supplied by a reference voltage which will be
automatically enabled. When the device is powered
down the low voltage detector will remain active if the
LVDEN bit is high. After enabling the Low Voltage De-
tector, a time delay tLVDS should be allowed for the cir-
cuitry to stabilise before reading the LVDO bit. Note also
that as the VDD voltage may rise and fall rather slowly, at
the voltage nears that of VLVD, there may be multiple bit
LVDO transitions.
An external LCD panel can be driven using this device
by configuring the PC0~PC3 or PC0 ~ PC1, PC6 ~ PC7
pins as common pins and using other output ports lines
as segment pins. The LCD driver function is controlled
using the SCOMC register which in addition to control-
ling the overall on/off function also controls the bias volt-
age setup function. This enables the LCD COM driver to
generate the necessary VDD/2 voltage levels for LCD 1/2
bias operation.
The SCOMEN bit in the SCOMC register is the overall
master control for the LCD driver, however this bit is
used in conjunction with the COMnEN bits to select
which Port C pins are used for LCD driving. Note that the
Port Control register does not need to first setup the pins
as outputs to enable the LCD driver operation.
V
D
D
V
D
D
S
C
O
M
o
p
e
r
a
t
i
n
g
V
L
V
D
V
D
/
D
2
S
C
O
M
0
~
L
V
D
E
N
S
C
O
M
3
C
O
M
n
E
N
L
V
D
O
S
C
O
M
E
N
t
L
V
D
S
LVD Operation
The Low Voltage Detector also has its own interrupt
which is contained within one of the Multi-function inter-
rupts, providing an alternative means of low voltage de-
tection, in addition to polling the LVDO bit. The interrupt
will only be generated after a delay of tLVD after the LVDO
bit has been set high by a low voltage condition. When
the device is powered down the Low Voltage Detector
will remain active if the LVDEN bit is high. In this case,
the LVF interrupt request flag will be set, causing an in-
terrupt to be generated if VDD falls below the preset LVD
voltage. This will cause the device to wake-up from the
SLEEP or IDLE Mode, however if the Low Voltage De-
tector wake up function is not required then the LVF flag
should be first set high before the device enters the
SLEEP or IDLE Mode.
LCD COM Bias
SCOMEN COMnEN Pin Function O/P Level
0
1
1
X
0
1
I/O
I/O
0 or 1
0 or 1
SCOMn
VDD/2
Output Control
LCD Bias Control
The LCD COM driver enables a range of selections to
be provided to suit the requirement of the LCD panel
which is being used. The bias resistor choice is imple-
mented using the ISEL1 and ISEL0 bits in the SCOMC
register.
SCOM Function for LCD
The devices have the capability of driving external LCD
panels. The common pins for LCD driving, SCOM0~
SCOM3, are pin shared with certain pin on the PC0~
PC3 or PC0 ~ PC1, PC6 ~ PC7 port. The LCD signals
(COM and SEG) are generated using the application
program.
Rev. 1.60
189
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
SCOMC Register
¨
HT66F20
Bit
Name
R/W
7
D7
R/W
0
6
ISEL1
R/W
0
5
ISEL0
R/W
0
4
3
2
1
0
SCOMEN COM3EN COM2EN COM1EN COM0EN
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bit 7
Reserved Bit
0: Correct level - bit must be reset to zero for correct operation
1: Unpredictable operation - bit must not be set high
Bit 6~5
ISEL1, ISEL0: ISEL1 ~ ISEL0: Select SCOM typical bias current (VDD=5V)
00: 25mA
01: 50mA
10: 100mA
11: 200mA
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCOMEN: SCOM module Control
0: Disable
1: Enable
COM3EN: PC3 or SCOM3 selection
0: GPIO
1: SCOM3
COM2EN: PC2 or SCOM2 selection
0: GPIO
1: SCOM2
COM1EN: PC1 or SCOM1 selection
0: GPIO
1: SCOM1
COM0EN: PC0 or SCOM0 selection
0: GPIO
1: SCOM0
Rev. 1.60
190
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
¨
HT66F30/HT66F40/HT66F50/HT66F60
Bit
Name
R/W
7
D7
R/W
0
6
ISEL1
R/W
0
5
ISEL0
R/W
0
4
3
2
1
0
SCOMEN COM3EN COM2EN COM1EN COM0EN
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POR
Bit 7
Reserved Bit
0: Correct level - bit must be reset to zero for correct operation
1: Unpredictable operation - bit must not be set high
Bit 6~5
ISEL1, ISEL0: Select SCOM typical bias current (VDD=5V)
00: 25mA
01: 50mA
10: 100mA
11: 200mA
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCOMEN: SCOM module control
0: disable
1: enable
COM3EN: PC7 or SCOM3 selection
0: GPIO
1: SCOM3
COM2EN: PC6 or SCOM2 selection
0: GPIO
1: SCOM2
COM1EN: PC1 or SCOM1 selection
0: GPIO
1: SCOM1
COM0EN: PC0 or SCOM0 selection
0: GPIO
1: SCOM0
Rev. 1.60
191
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the program-
ming process. During the development process, these options are selected using the HT-IDE software development
tools. As these options are programmed into the device using the hardware programming tools, once they are selected
they cannot be changed later using the application program. All options must be defined for proper system function, the
details of which are shown in the table.
No.
Options
Oscillator Options
High Speed System Oscillator Selection - fH:
1. HXT
2. ERC
3. HIRC
1
Low Speed System Oscillator Selection - fL:
2
3
1. LXT
2. LIRC
WDT Clock Selection - fS:
1. fSUB
2. fSYS/4
HIRC Frequency Selection:
1. 4MHz
4
2. 8MHz
3. 12MHz
Note: The fSUB and the fTBC clock source are LXT or LIRC selection by the fL configuration option.
Reset Pin Options
PB0/RES Pin Options:
5
1. RES pin
2. I/O pin
Watchdog Options
Watchdog Timer Function:
6
7
1. Enable
2. Disable
CLRWDT Instructions Selection:
1. 1 instructions
2. 2 instructions
LVR Options
LVR Function:
8
9
1. Enable
2. Disable
LVR Voltage Selection:
1. 2.10V
2. 2.55V
3. 3.15V
4. 4.20V
Rev. 1.60
192
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
No.
Options
SIM Options
SIM Function:
10
11
12
1. Enable
2. Disable
SPI - WCOL bit:
1. Enable
2. Disable
SPI - CSEN bit:
1. Enable
2. Disable
I2C Debounce Time Selection:
1. No debounce
13
2. 2 system clock debounce
3. 4 system clock debounce
Application Circuits
V
D
D
0
.
m
0
F
1
*
*
V
D
D
R
e
s
e
t
1
W
0 ~ k
C
i
r
c
u
i
t
1
0
W
0
k
1
N
4
1
4
8
*
0
m
. F 1
R
E
S
A
N
0
~
A
N
1
1
3
0
W
* 0
0
.
1
m
F
~
1
P
B
5
~
P
B
7
V
S
S
P
C
0
~
P
C
7
P
P
P
D
E
F
0
~
P
D
7
O
O
S
S
C
C
1
2
O
S
C
0
~
P
E
5
C
i
r
c
u
i
t
2
~
P
F
7
S
e
e
O
s
c
i
l
l
a
t
o
r
S
e
c
t
i
o
n
P
G
0
~
P
G
1
X
X
T
T
1
2
O
S
C
C
i
r
c
u
i
t
S
e
e
O
s
c
i
l
l
a
t
o
r
S
e
c
t
i
o
n
Note:
²*² It is recommended that this component is added for added ESD protection.
²**² It is recommended that this component is added in environments where power line noise is significant.
Rev. 1.60
193
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
UART Module Serial Interface
-
UART Module Features
Transmit and Receive Multiple Interrupt
Generation Sources:
·
·
Interconnected to Holtek MCU via SPI interface
¨
¨
¨
¨
¨
Transmitter Empty
Transmitter Idle
Full-duplex, Universal Asynchronous Receiver and
Transmitter (UART) communication
Receiver Full
-
-
-
-
-
-
-
-
-
8 or 9 bit character length
Receiver Overrun
Address Mode Detect
Even, odd or no parity options
One or two stop bits
-
-
TX pin is high impedance when the UART transmit
module is disabled
Baud rate generator with 8-bit prescaler
Parity, framing, noise and overrun error detection
Support for interrupt on address detect
Address Detect Interrupt - last character bit=1
Transmitter and receiver enabled independently
4-byte deep FIFO receiver data buffer
RX pin is high impedance when the UART receive
module is disabled
·
CMOS clock input, CLKI, up to 20MHz at 5V
operating voltage
UART Module Overview
The device contains a fully embedded full-duplex asyn-
chronous serial communications UART interface that
enables data transmission and data reception with ex-
ternal devices. Possible applications could include data
communication networks between microcontrollers,
low-cost data links between PCs and peripheral
devices, portable and battery operated device commu-
nication, factory automation and process control to
name but a few.
UART Module Block Diagram
U
A
R
T
M
o
d
u
l
e
S
D
I
S
D
O
T
R
X
S
C
K
U
A
R
T
S
P
I
I n
e
t
e
r
f
a
c
e
I
n
t
e
r
f
a
c
V
D
D
X
S
C
S
V
D
D
C
L
K
I
G
N
D
I
N
T
Rev. 1.60
194
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Pin Assignment
P
A
0
/
C
0
X
/
T
1
2
3
4
5
6
7
8
9
1
1
1
P
0
_
0
/
P
P
P
P
P
P
P
P
R
T
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1
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6
1
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2
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1
2
2
2
3
2
4
Rev. 1.60
195
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
4
8
4
4
6
7
4
4
4
4
5
4
3
2
4
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1
3
3
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T
6
6
F U
4
6
0
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
H
T
6
6
F
U
6
0
P
A
3
3
/
I
N
T
0
/
C
0
-
/
A
N
3
4
0
Q
F
3
N
-
A
]
/
S
C
O
M
P
A
3
/
I
N
T
/
C
0
-
/
A
N
4
4
L
Q
F
P
-
A
P
A
2
0
/
T
+
C
/
K
A
0
N
/
2
C
0
P
3
_
P
1
B
_
0
/
S
C
O
O
M
P
A
2
/
T
+
C
/
K
A
0
N
/
2
C
0
P A
1
0
1
/
T
P
1
A
/
A
N
1
6
7
0
1
/
/
[
[
T
T
P
P
0
1
_
A
P
1
B
_
1
/
S
C
M
P
A
1
/
T
P
1
A
/
A
N
1
P
A
/
C
0
X
/
T
P
0
_
0
/
A
N
0
4
/
[
2
T
]
P
1
B
_
P
A
0
/
C
0
X
/
T
P
0
_
0
/
A
N
0
P
P
F
F
1
/
/
[
C
1
1
X
0
]
/
A
N
1
1
0
/
T
P
1
B
_
0
0
5
/
[
T
P
3
_
0
]
P
F
1
/
[
C
1
X
]
/
A
N
1
1
0
[
C
0
X
]
1
/
A
N
1
/
T
P
1
B
1
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
4
4
5
5
8
5
9
0
1
2
4
4
4
5
6
7
4
4
4
4
0
4
1
2
3
4
3
3
3
3
3
3
9
8
7
6
5
4
P
P
F
3
2
1
2
3
4
5
6
7
8
9
N
P
P
P
P
P
P
P
P
P
P
P
P
C
4
8
4
4
6
7
4
4
4
4
5
4
3
2
4
4
0
1
F
D
D
E
E
E
E
F
F
G
G
C
C
4
5
/
/
[
[
T
T
P
P
2
0
1
2
3
4
5
6
7
8
9
3
3
3
3
3
3
3
2
2
2
2
2
6
5
4
3
2
1
0
9
8
7
6
5
N
P
P
P
P
P
P
P
P
N
P
P
C
N
C
P
B
5
/
S
C
S
/
V
R
E
F
D
D
E
E
E
E
C
C
4
5
/
/
[
[
T
T
P
P
2
0
_
_
1
1
]
]
P
B
5
/
S
C
S
/
V
R
E
F
P
A
7
/
S
C
K
/
S
C
L
/
A
N
7
0
1
2
3
/
/
/
/
[
[
[
[
I
I
I
T
N
N
N
T
T
T
P
A
7
/
S
C
K
/
S
C
L
/
A
N
7
P
A
6
/
S
D
I
/
S
D
A
/
/
A
A
N
N
6
5
0
1
2
3
/
/
/
/
[
[
[
[
I
I
I
T
N
N
N
T
T
T
0
1
2
]
]
]
P
A
6
/
S
D
I
/
S
D
A
/
/
A
A
N
N
6
5
P
A
5
/
C
1
X
/
S
D
O
P
A
5
/
C
1
X
/
0
S
D
O
H
T
6
6
F
U
6
0
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
4
3
3
3
3
2
2
2
3
2
1
0
9
8
7
P
3
P
A
4
/
I
N
T
1
/
T
C
K
1
/
A
N
4
F
H
T
6
6
U
6
0
5
2
Q
F
P
-
A
P
A
3
/
I
N
T
0
/
C
0
-
/
A
N
3
6
4
8
L
Q
F
P
-
A
/
Q
F
N
-
A
P
3
_
1
]
P
A
3
/
I
N
T
/
C
0
-
/
A
N
3
P
A
C
2
/
K
T 0
2
/
C
0
+
/
A
N
2
7
6
7
/
/
[
[
T
T
P
P
0
1
_
A
0
]
/
S
C
O
M
P
A
2
/
C
T
0
C
+
K
/
0
A
/
N
2
P
A
1
3
/
T
P
1
1
1
1
1
A
0
1
2
3
/
A
N
1
0
/
[
C
0
X
]
/
S
C
O
M
P
A
1
/
T
P
1
A
/
A
N
1
P
A
0
/
C
0
X
/
T
P
0
_
0
/
A
N
0
1
/
[
C
1
X
C
P
A
0
/
C
0
X
/
T
1
1
1
0
1
2
P
0
_
0
/
A
N
0
P
F
1
0
/
[
C
C
1
X
]
/
A
N
1
1
6
7
/
/
[
[
S
T
T
C
P
P
O
0
1
C
0
/
T
P
1
B
_
0
/
S
C
O
M
N
C
P
F
0 /
1
[
0
X
]
/
A
N
1
0
C
1
/
T
P
1
B
_
1
/
S
C
O
M
P
F
1
/
[
C
1
X
]
/
A
N
1
1
1
4
1
5
1
6
1
7
2
1
3
8
2
1
4
9
2
2
5
0
2
2
6
1
2
2
1
3
1
4
1
1
7
5
1
1
8
6
1
9
2
0
2
1
2
2
2
3
2
4
Rev. 1.60
196
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
UART Module Pin Description
Pin Name
I/O
Description
External UART RX serial data input pin
RX
I
If UARTEN=1 and RXEN=1, then RX is the UART serial data input
If UARTEN=0 or RXEN=0, then RX is high impedance
External UART TX serial data output pin
TX
O
If UARTEN=1 and TXEN=1, then TX is the UART serial data output
If UARTEN=0 or TXEN=0, then TX is high impedance
Internal Slave SPI Serial Data In Input Signal
SDI
I
O
I
Internally connected to the MCU Master SPI SDO output signal
Internal Slave SPI Serial Data Out Output Signal
SDO
SCK
Internally connected to the MCU Master SPI SDI input signal
Internal Slave SPI Serial Clock Input Signal
Internally connected to the MCU Master SPI SCK output signal
Internal Slave SPI Device Select Input Signal
SCS
CLKI
I
I
Internally connected to the MCU Master SPI SCS output signal -- connected to pull high
resistor
Internal Clock Input Signal
Internally connected to the MCU Master PCK output signal
Internal UART Interrupt Output Signal
INT
NC
O
Internally connected to the MCU Master PINT input signal
A UART related interrupt will generate a low pulse signal on this line
¾
Implies that the pin is ²Not Connected² and can therefore not be used.
Notes: The pin description for all pins with the exception of the UART TX and RX pins are described in the preceding
MCU section.
UART Module D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
fCLKI=12MHz, SCK=fCLKI/4,
Output no load
3.0V
1.0
2.0
4.2
4.8
mA
mA
mA
mA
¾
¾
¾
¾
¾
¾
¾
¾
Operating Current *
IDD1
(SPI Enabled, UART disabled)
f
CLKI=16MHz, SCK=fCLKI/4,
5.0V
2.2V
5.0V
Output no load
fCLKI=6MHz, SCK=fCLKI/4,
Output no load
Operating Current *
IDD2
(SPI enabled, UART enabled)
f
CLKI=12MHz, SCK=fCLKI/4,
Output no load
fCLKI=16MHz, SCK=fCLKI/4,
SCS=VDD, UARTEN=0,
TXEN=1, RXEN=1, SDI=H,
RX=H, Output no load
Standby Current *
ISTB
5.0V
0.6
¾
¾
mA
(SPI disabled, UART disabled)
VIL
VIH
0.3VDD
VDD
¾
Input Low Voltage for RX Ports
Input High Voltage for RX Ports
0
V
¾
¾
¾
¾
¾
0.7VDD
2.5
V
¾
3.0V
5.0V
3.0V
5.0V
5.0
mA
mA
mA
mA
IOL
VO=0.1VDD
VO=0.9VDD
TX Port Sink Current
10.0
-1.5
-5.0
25.0
-3.0
-8.0
¾
¾
IOH
RX Port Source Current
¾
Rev. 1.60
197
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Test Conditions
Symbol
RPH
Parameter
Min.
Typ.
Max.
Unit
VDD
3.0V
5.0V
Conditions
20
10
60
30
100
50
kW
kW
Pull-high Resistance for SCS only
¾
Note:
²*² The operating current IDD1 listed here is the additional current consumed when the slave SPI interface in the
UART module is enabled and the UART interface is disabled. Similarly, the operating current IDD2 here is the
additional current consumed when both the slave SPI interface and UART interface are enabled. If the UART
module is enabled, either IDD1 or IDD2 should be added to calculate the relevant operating current of the device
for different conditions. To calculate the standby current for the whole device, the standby current shown above
should be taken into account.
UART Module A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
3.0V
5.0V
3.0V
5.0V
3.0V
5.0V
3.0V
5.0V
¾
Conditions
62.5
50.0
28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
10
10
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
tCP
SCK Period (tCH + tCL)
tCH
SCK High Time
SCK Low Time
22
28
tCL
22
500
400
100
0
tCSW
SCS High Pulse Width
tCSS
tCSH
tSDS
tSDH
tR
SCS to SCK Setup Time
SCS to SCK Hold Time
SDI to SCK Setup Time
SDI to SCK Hold Time
SPI Output Rise Time
SPI Output Fall Time
¾
100
0
¾
¾
¾
¾
tF
¾
¾
tW
SPI Data Output Delay Time
0
¾
Rev. 1.60
198
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
UART Module Functional Description
UART Module SPI Interface
The embedded UART Module is full-duplex asynchron-
ous serial communications UART interface that enables
communication with external devices that contain a se-
rial interface. The UART function has many features and
can transmit and receive data serially by transferring a
frame of data with eight or nine data bits per transmis-
sion as well as being able to detect errors when the data
is overwritten or incorrectly framed. Interconnection be-
tween the MCU and the UART module is implemented
by internally connecting the MCU Master SPI interface
to the UART Slave SPI interface. All data transmissions
and receptions between MCU and UART module in-
cluding UART commands are conducted along this in-
terconnected SPI interface. The UART function control
is executed by the MCU using its SPI Master serial inter-
face. The UART module contains its own independent
interrupt which can be used to indicate when a data re-
ception occurs or when a data transmission has termi-
nated.
The MCU communicates with the UART Module via an
internal SPI interface. The SPI interface on this device is
comprised of four signals: SCS (SPI Chip Select), SCK
(SPI Clock), SDI (Serial Data Input) and SDO (Serial
Data Output). The SPI master, which is the MCU, as-
serts SCS by pulling it low to start the data transaction
cycle. When the first 8 bits of data are transmitted, SCS
should not return to a high level. Instead, SCS must re-
main at a low level until the whole 16-bit data transaction
is completed. If SCS is de-asserted, that is returned to a
high level before the 16-bit data transaction is com-
pleted, all data bits will be discarded by the UART Mod-
ule SPI slave.
SPI Timing
Both read and write operations are conducted along the
SPI common interface with the following format:
·
Write Type Format: 8-bit command input + 8-bit data
input
UART Module Internal Signal
·
Read Type Format: 8-bit command input + 8-bit data
output
In addition to the TX and RX external pins described
above there are other MCU to UART Module intercon-
necting lines that are described in the following table.
Note that these lines are internal to the device and are
not bonded to external pins.
To initiate a data transaction, the MCU master SPI
needs to pull SCS to a low level first and then also pull
SCK low. The input data bit on SDI should be stable be-
fore the next SCK rising edge, as the device will latch
the SDI status on the next SCK rising edge. Regarding
the SDO line, the output data bit will be updated on the
SCK falling edge. The master needs to obtain the line
status before the next SCK falling edge.
V
D
D
V
D
D
V
D
D
There are 16 bits of data transmitted and/or received by
the SPI interface for each transaction. Each transaction
consists of a command phase and a data phase. When
SCS is high, the SPI interface is disabled and SDO will
be set to a high impedance state.
S
S
S
S
I
C
C
D
D
C
K
I
O
S
S
C
K
R
X
S
D
O
S
D
I
M
C
U
U
A
R
T
M
o
d
u
l
e
S
C
S
After a complete transaction has been implemented,
which requires 16 SCK clock cycles, the master needs
to set SCS to a high level in preparation for the next data
transaction.
T
X
P
I
N
T
N
T
P
C
K
L
K
I
G
N
D
G
N
D
For write operations, the device will begin to execute the
command only after it receives a 16-bit serial data se-
quence and when the SCS has been set high again by
the master.
MCU to UART Internal Connection
Rev. 1.60
199
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
For read operations, the device will begin to execute the
to the TXR register by the application program. The data
will then be transferred to the Transmitter Shift Register
named TSR from where it will be shifted out, LSB first,
onto the TX pin at a rate controlled by the Baud Rate
Generator. Only the TXR register is accessible to the
application program, the Transmitter Shift Register is
not mapped into the Data Memory area and is inacces-
sible to the application program.
command only after it receives an 8-bit read command
after which it will be ready to output data. If necessary,
the master can de-assert the SCS pin to abort the trans-
action at any time which will cause any data transac-
tions to be abandoned.
UART Module External Pin Interfacing
Data to be received by the UART is accepted on the ex-
ternal RX pin, from where it is shifted in, LSB first, to the
Receiver Shift Register named RSR at a rate controlled
by the Baud Rate Generator. When the shift register is
full, the data will then be transferred from the shift regis-
ter to the internal RXR register, where it is buffered and
can be manipulated by the application program. Only
the RXR register is accessible to the application pro-
gram, the Receiver Shift Register is not mapped into the
Data Memory area and is inaccessible to the application
program. It should be noted that the actual register for
data transmission and reception, although referred to in
the text, and in application programs, as separate TXR
and RXR registers, only exists as a single shared regis-
ter physically. This shared register known as the
TXR/RXR register is used for both data transmission
and data reception.
To communicate with an external serial interface, the in-
ternal UART has two external pins known as TX and RX.
The TX pin is the UART transmitter serial data output pin
if the corresponding control bits named UARTEN in
UCR1 register and TXEN in UCR2 register are set to 1.
If the control bit UARTEN or TXEN is equal to zero, the
TX pin is in the state of high impedance. Similarly, the
RX pin is the UART receiver serial data input pin if the
corresponding control bits named UARTEN and RXEN
in UCR1 and UCR2 registers are set to 1. If the control
bit UARTEN or RXEN is equal to zero, the RX pin is in
the state of high impedance.
UART Data Transfer Scheme
The following block diagram shows the overall data
transfer structure arrangement for the UART. The actual
data to be transmitted from the MCU is first transferred
SCS
SCK
SDI
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
Writing Type Format: 8-bit Command Input + 8-bit Data Input
SCS
SCK
SDI
tw
A7
A6
A5
A4
A3
A2
A1
A0
SDO
D7
D6
D5
D4
D3
D2
D1
D0
Reading Type Format: 8-bit Command Input + 8-bit Data Output
Transmitter Shift Register (TSR)
MSB LSB
Receiver Shift Register (RSR)
MSB LSB
TX Pin
RX Pin
Buffer 3
Buffer 2
Buffer 1
Baud Rate
Generator
TX Register (TXR)
RX Register (RXR)
Data received
Data to be transmitted
UART Data Transfer Scheme
Rev. 1.60
200
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
UART Commands
There are both read and write commands for the UART Module. For reading and writing to registers both command and
address information is contained within a single byte. The format for reading and writing is shown in the following table.
Command Type
Read FIFO
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
X
Bit 1
X
Bit 0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
Read Register
Write FIFO
A2
X
A1
X
A0
X
Write Register
A2
A1
A0
Note: ²X² here stands for ²don¢t care²
UART Status and Control Registers
There are six registers associated with the UART function. The USR, UCR1, UCR2 and UCR3 registers control the
overall function of the UART module, while the BRG register controls the Baud rate. The actual data to be transmitted
and received on the serial interface is managed through the TXR/RXR data register.
A[2:0] Name
Reset
Bit 7
PERR
UARTEN
TXEN
Bit 6
NF
Bit 5
FERR
PREN
Bit 4
OERR RIDLE
PRT STOPS TXBRK
Bit 3
Bit 2
Bit 1
TIDLE
RX8
Bit 0
TXIF
TX8
00H
01H
02H
03H
04H
USR
0000 1011
0000 0X00
0000 0000
XXXX XXXX
0--- ----
RXIF
UCR1
UCR2
BRG
BNO
RXEN BRGH ADDEN WAKE
RIE
BRG2
¾
TIIE
TEIE
BRG7
BRG6 BRG5
BRG4
BRG3
BRG1 BRG0
UCR3
URST
¾
¾
¾
¾
¾
¾
05H~
07H
Unused
Reserved
UART Register Summary
---- ----
·
USR Register
The USR register is the status register for the UART, which can be read by the application program to determine the
present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is
given below:
Bit
Name
R/W
7
PERR
R
6
NF
R
5
FERR
R
4
OERR
R
3
RIDLE
R
2
RXIF
R
1
TIDLE
R
0
TXIF
R
POR
0
0
0
0
1
0
1
1
Bit 7
PERR: Parity error flag
0: no parity error is detected
1: parity error is detected
The PERR flag is the parity error flag. When this read only flag is ²0², it indicates a parity error
has not been detected. When the flag is ²1², it indicates that the parity of the received word is
incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can
also be cleared by a software sequence which involves a read to the status register USR
followed by an access to the RXR data register.
Bit 6
NF: Noise flag
0: no noise is detected
1: noise is detected
The NR flag is the noise flag. When this read only flag is ²0², it indicates no noise condition.
When the flag is ²1², it indicates that the UART has detected noise on the receiver input.
The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as
overrun. The NF flag can be cleared by a software sequence which will involve a read to the
status register USR followed by an access to the RXR data register.
Rev. 1.60
201
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Bit 5
FERR: Framing error flag
0: no framing error is detected
1: framing error is detected
The FERR flag is the framing error flag. When this read only flag is ²0², it indicates that there
is no framing error. When the flag is ²1², it indicates that a framing error has been detected
for the current character. The flag can also be cleared by a software sequence which will involve
a read to the status register USR followed by an access to the RXR data register.
Bit 4
OERR: Overrun error flag
0: no overrun error is detected
1: overrun error is detected
The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed.
When this read only flag is ²0², it indicates that there is no overrun error. When the flag is
²1², it indicates that an overrun error occurs which will inhibit further transfers to the RXR
receive data register. The flag is cleared by a software sequence, which is a read to the status
register USR followed by an access to the RXR data register.
Bit 3
RIDLE: Receiver status
0: data reception is in progress (data being received)
1: no data reception is in progress (receiver is idle)
The RIDLE flag is the receiver status flag. When this read only flag is ²0², it indicates that the
receiver is between the initial detection of the start bit and the completion of the stop bit. When
the flag is ²1², it indicates that the receiver is idle. Between the completion of the stop bit and
the detection of the next start bit, the RIDLE bit is ²1² indicating that the UART receiver is idle
and the RX pin stays in logic high condition.
Bit 2
RXIF: Receive RXR data register status
0: RXR data register is empty
1: RXR data register has available data
The RXIF flag is the receive data register status flag. When this read only flag is ²0², it indicates
that the RXR read data register is empty. When the flag is ²1², it indicates that the RXR read data
register contains new data. When the contents of the shift register are transferred to the RXR
register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are
detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are
set within the same clock cycle. The RXIF flag is cleared when the USR register is read with
RXIF set, followed by a read from the RXR register, and if the RXR register has no data
available.
Bit 1
TIDLE: Transmission idle
0: data transmission is in progress (data being transmitted)
1: no data transmission is in progress (transmitter is idle)
The TIDLE flag is known as the transmission complete flag. When this read only flag is ²0², it
indicates that a transmission is in progress. This flag will be set to ²1² when the TXIF flag is
²1² and when there is no transmit data or break character being transmitted. When TIDLE is
equal to ²1², the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is
cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag
is not generated when a data character or a break is queued and ready to be sent.
Bit 0
TXIF: Transmit TXR data register status
0: character is not transferred to the transmit shift register
1: character has transferred to the transmit shift register (TXR data register is empty)
The TXIF flag is the transmit data register empty flag. When this read only flag is ²0², it
indicates that the character is not transferred to the transmitter shift register. When the flag is
²1², it indicates that the transmitter shift register has received a character from the TXR data
register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and
then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will
also be set since the transmit data register is not yet full.
Rev. 1.60
202
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
UCR1 register
The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the vari-
ous options for the UART function such as overall on/off control, parity control, data transfer bit length, etc. Further
explanation on each of the bits is given below:
Bit
Name
R/W
7
UARTEN
R/W
6
5
PREN
R/W
0
4
3
STOPS
R/W
0
2
TXBRK
R/W
0
1
RX8
R
0
BNO
R/W
0
PRT
R/W
0
TX8
W
POR
0
X
0
²x² unknown
Bit 7
UARTEN: UART function enable control
0: disable UART. TX and RX pins are in the state of high impedance
1: enable UART. TX and RX pins function as UART pins
The UARTEN bit is the UART enable bit. When this bit is equal to ²0², the UART will be
disabled and the RX pin as well as the TX pin will be in the state of high impedance. When the
bit is equal to ²1², the UART will be enabled and the TX and RX pins will function as defined by
the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so
any character remaining in the buffer will be discarded. In addition, the value of the baud rate
counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the
TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE,
TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain
unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and
receptions will be terminated and the module will be reset as defined above. When the UART is
re-enabled, it will restart in the same configuration.
Bit 6
BNO: Number of data transfer bits selection
0: 8-bit data transfer
1: 9-bit data transfer
This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit
format. When this bit is equal to ²1², a 9-bit data length format will be selected. If the bit is
equal to ²0², then an 8-bit data length format will be selected. If 9-bit data length format is
selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted
data respectively.
Bit 5
Bit 4
Bit 3
Bit 2
PREN: Parity function enable control
0: parity function is disabled
1: parity function is enabled
This is the parity enable bit. When this bit is equal to ²1², the parity function will be enabled. If
the bit is equal to ²0², then the parity function will be disabled.
PRT: Parity type selection bit
0: even parity for parity generator
1: odd parity for parity generator
This bit is the parity type selection bit. When this bit is equal to ²1², odd parity type will be
selected. If the bit is equal to ²0², then even parity type will be selected.
STOPS: Number of Stop bits selection
0: one stop bit format is used
1: two stop bits format is used
This bit determines if one or two stop bits are to be used. When this bit is equal to ²1², two
stop bits are used. If this bit is equal to ²0², then only one stop bit is used.
TXBRK: Transmit break character
0: no break character is transmitted
1: break characters transmit
The TXBRK bit is the Transmit Break Character bit. When this bit is ²0², there are no break
characters and the TX pin operates normally. When the bit is ²1², there are transmit break
characters and the transmitter will send logic zeros. When this bit is equal to ²1², after the
buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit
length and until the TXBRK bit is reset.
Rev. 1.60
203
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Bit 1
Bit 0
RX8: Receive data bit 8 for 9-bit data transfer format (read only)
This bit is only used if 9-bit data transfers are used, in which case this bit location will store the
9th bit of the received data known as RX8. The BNO bit is used to determine whether data
transfers are in 8-bit or 9-bit format.
TX8: Transmit data bit 8 for 9-bit data transfer format (write only)
This bit is only used if 9-bit data transfers are used, in which case this bit location will store the
9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data
transfers are in 8-bit or 9-bit format.
·
UCR2 register
The UCR2 register is the second of the UART control registers and serves several purposes. One of its main func-
tions is to control the basic enable/disable operation if the UART Transmitter and Receiver as well as enabling the
various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up function
enable and the address detect function enable. Further explanation on each of the bits is given below:
Bit
Name
R/W
7
TXEN
R/W
0
6
RXEN
R/W
0
5
BRGH
R/W
0
4
ADDEN
R/W
0
3
WAKE
R/W
1
2
RIE
R/W
0
1
TIIE
R
0
TEIE
W
POR
1
1
Bit 7
TXEN: UART Transmitter enable control
0: UART transmitter is disabled
1: UART transmitter is enabled
The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to ²0², the transmitter
will be disabled with any pending data transmissions being aborted. In addition the buffers will be
reset. In this situation the TX pin will be in the state of high impedance. If the TXEN bit is equal to
²1² and the UARTEN bit is also equal to ²1², the transmitter will be enabled and the TX pin will
be controlled by the UART. Clearing the TXEN bit during a transmission will cause the data
transmission to be aborted and will reset the transmitter. If this situation occurs, the TX pin will
be in the state of high impedance.
Bit 6
RXEN: UART Receiver enable control
0: UART receiver is disabled
1: UART receiver is enabled
The bit named RXEN is the Receiver Enable Bit. When this bit is equal to ²0², the receiver will
be disabled with any pending data receptions being aborted. In addition the receive buffers will
be reset. In this situation the RX pin will be in the state of high impedance. If the RXEN bit is
equal to ²1² and the UARTEN bit is also equal to ²1², the receiver will be enabled and the RX pin
will be controlled by the UART. Clearing the RXEN bit during a reception will cause the data
reception to be aborted and will reset the receiver. If this situation occurs, the RX pin will be in the
state of high impedance.
Bit 5
BRGH: Baud Rate speed selection
0: low speed baud rate
1: high speed baud rate
The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit,
together with the value placed in the baud rate register BRG, controls the Baud Rate of the
UART. If this bit is equal to ²1², the high speed mode is selected. If the bit is equal to ²0²,
the low speed mode is selected.
Bit 4
ADDEN: Address detect function enable control
0: address detect function is disabled
1: address detect function is enabled
The bit named ADDEN is the address detect function enable control bit. When this bit is equal to
²1², the address detect function is enabled. When it occurs, if the 8th bit, which corresponds to
RX7 if BNO=0 or the 9th bit, which corresponds to RX8 if BNO=1, has a value of ²1²,
then the received word will be identified as an address, rather than data. If the corresponding
interrupt is enabled, an interrupt request will be generated each time the received word has the
address bit set, which is the 8th or 9th bit depending on the value of BNO. If the address bit
known as the 8th or 9th bit of the received word is ²0² with the address detect function being
enabled, an interrupt will not be generated and the received data will be discarded.
Rev. 1.60
204
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Bit 3
Bit 2
Bit 1
Bit 0
WAKE: RX pin falling edge wake-up function enable control
0: RX pin wake-up function is disabled
1: RX pin wake-up function is enabled
This bit enables or disables the receiver wake-up function. If this bit is equal to ²1² and the
MCU is in IDLE or SLEEP mode, a falling edge on the RX input pin will wake-up
the device. If this bit is equal to ²0² and the MCU is in IDLE or SLEEP mode,
any edge transitions on the RX pin will not wake-up the device.
RIE: Receiver interrupt enable control
0: receiver related interrupt is disabled
1: receiver related interrupt is enabled
This bit enables or disables the receiver interrupt. If this bit is equal to ²1² and when the
receiver overrun flag OERR or receive data available flag RXIF is set, the UART interrupt request
flag will be set. If this bit is equal to ²0², the UART interrupt request flag will not be influenced
by the condition of the OERR or RXIF flags.
TIIE: Transmitter Idle interrupt enable control
0: transmitter idle interrupt is disabled
1: transmitter idle interrupt is enabled
This bit enables or disables the transmitter idle interrupt. If this bit is equal to ²1² and when
the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt
request flag will be set. If this bit is equal to ²0², the UART interrupt request flag will not be
influenced by the condition of the TIDLE flag.
TEIE: Transmitter Empty interrupt enable control
0: transmitter empty interrupt is disabled
1: transmitter empty interrupt is enabled
This bit enables or disables the transmitter empty interrupt. If this bit is equal to ²1² and when
the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt
request flag will be set. If this bit is equal to ²0², the UART interrupt request flag will not be
influenced by the condition of the TXIF flag.
·
UCR3 register
The UCR3 register is the last of the UART control registers and controls the software reset operation of the UART
module. The only one available bit named URST in the UART control register UCR3 is the UART software reset con-
trol bit. When this bit is equal to ²0², the UART operates normally. If this bit is equal to ²1², the whole UART module
will be reset. When this situation occurs, the transmitter and receiver will be reset. The UART registers including the
status register and control registers will keep the POR states shown in the above UART registers table after the reset
condition occurs.
Bit
Name
R/W
7
URST
R/W
0
6
5
4
3
2
1
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7
URST: UART software reset
0: no action
1: UART reset occurs
Bit 6~0
unimplemented, read as ²0²
Rev. 1.60
205
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Baud Rate Generator
·
Calculating the baud rate and error values
For a clock frequency of 4MHz, and with BRGH set to
²0² determine the BRG register value N, the actual
baud rate and the error value for a desired baud rate
of 4800.
To setup the speed of the serial data communication,
the UART function contains its own dedicated baud rate
generator. The baud rate is controlled by its own internal
free running 8-bit timer, the period of which is deter-
mined by two factors. The first of these is the value
placed in the baud rate register BRG and the second is
the value of the BRGH bit with the control register
UCR2. The BRGH bit decides if the baud rate generator
is to be used in a high speed mode or low speed mode,
which in turn determines the formula that is used to cal-
culate the baud rate. The value N in the BRG register
which is used in the following baud rate calculation for-
mula determines the division factor. Note that N is the
decimal value placed in the BRG register and has a
range of between 0 and 255.
From the above table the desired baud rate BR =
fCLKI
[64 (N+1)]
fCLKI
(BRx64)
Re-arranging this equation gives N =
- 1
4000000
Giving a value for N =
- 1 = 12.0208
(4800x64)
To obtain the closest value, a decimal value of 12 should
be placed into the BRG register. This gives an actual or
4000000
calculated baud rate value of BR=
= 4808
[64(12+1)]
UCR2 BRGH Bit
0
1
fCLKI
fCLKI
Baud Rate (BR)
4
8
-
0
4
8
8
0
[64 (N+1)]
[16 (N+1)]
Therefore the error is equal to
= 0.16%
0
4
8
0
By programming the BRGH bit which allows selection of
the related formula and programming the required value
in the BRG register, the required baud rate can be
setup. Note that because the actual baud rate is deter-
mined using a discrete value, N, placed in the BRG reg-
ister, there will be an error associated between the
actual and requested value. The following example
shows how the BRG register value N and the error value
can be calculated.
The following tables show the actual values of baud rate and error values for the two value of BRGH.
Baud Rates for BRGH=0
Baud
Rate
fCLKI=4MHz
fCLKI=3.579545MHz
fCLKI=7.159MHz
Kbaud Error (%)
K/BPS
BRG
207
51
25
12
6
Kbaud Error (%)
BRG Kbaud Error (%)
BRG
¾
92
46
22
11
5
0.3
1.2
0.300
1.202
2.404
4.808
8.929
20.833
¾
0.16
0.16
0.16
0.16
-6.99
8.51
¾
185
46
22
11
5
0.300
1.190
2.432
4.661
9.321
18.643
¾
0.00
-0.83
1.32
-2.90
-2.90
-2.90
¾
¾
¾
1.203
0.23
2.4
2.380
-0.83
1.32
4.8
4.863
9.6
9.322
-2.90
-2.90
-2.90
-2.90
-2.90
19.2
38.4
57.6
115.2
2
2
18.643
32.286
55.930
111.859
2
¾
0
¾
0
62.500
¾
8.51
¾
55.930
¾
1
-2.90
¾
0
¾
¾
Baud Rates and Error Values for BRGH = 0
Rev. 1.60
206
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Baud Rates for BRGH=1
Baud
Rate
fCLKI=4MHz
fCLKI=3.579545MHz
BRG Kbaud Error (%)
fCLKI=7.159MHz
Kbaud Error (%)
K/BPS
BRG
¾
Kbaud Error (%)
BRG
¾
0.3
1.2
¾
¾
0.16
0.16
0.16
0.16
0.16
-6.99
8.51
8.51
0
¾
185
92
46
22
11
5
¾
¾
¾
¾
¾
207
103
51
25
12
6
1.202
2.404
4.808
9.615
19.231
35.714
62.5
1.203
2.406
4.76
0.23
0.23
-0.83
1.32
-2.90
-2.90
-2.90
-2.90
¾
¾
¾
2.4
185
92
46
22
11
7
2.406
4.811
9.520
19.454
37.286
55.930
111.86
0.23
0.23
4.8
9.6
9.727
18.643
37.286
55.930
111.86
¾
-0.83
1.32
19.2
38.4
57.6
115.2
250
-2.90
-2.90
-2.90
¾
3
3
1
125
1
3
0
250
¾
¾
¾
Baud Rates and Error Values for BRGH = 1
·
BRG Register
Bit
Name
R/W
7
BRG7
R/W
x
6
5
BRG5
R/W
x
4
BRG4
R/W
x
3
BRG3
R/W
x
2
1
BRG1
R/W
x
0
BRG0
R/W
BRG6
R/W
x
BRG2
R/W
x
POR
x
²x²: unknown
Bit 7~0
BRG7~BRG0: Baud Rate values
By programming the BRGH bit in UCR2 Register which allows selection of the related formula
described above and programming the required value in the BRG register, the required baud rate
can be setup.
Rev. 1.60
207
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
UART Module Setup and Control
For data transfer, the UART function utilizes a
non-return-to-zero, more commonly known as NRZ, for-
mat. This is composed of one start bit, eight or nine data
bits and one or two stop bits. Parity is supported by the
UART hardware and can be setup to be even, odd or no
parity. For the most common data format, 8 data bits
along with no parity and one stop bit, denoted as 8, N, 1,
is used as the default setting, which is the setting at
power-on. The number of data bits and stop bits, along
with the parity, are setup by programming the corre-
sponding BNO, PRT, PREN and STOPS bits in the
UCR1 register. The baud rate used to transmit and re-
ceive data is setup using the internal 8-bit baud rate
generator, while the data is transmitted and received
LSB first. Although the transmitter and receiver of the
UART are functionally independent, they both use the
same data format and baud rate. In all cases stop bits
will be used for data transmission.
then all pending transmissions and receptions will be
immediately suspended and the UART will be reset to
a condition as defined above. If the UART is then sub-
sequently re-enabled, it will restart again in the same
configuration.
·
Data, parity and stop bit selection
The format of the data to be transferred is composed
of various factors such as data bit length, parity on/off,
parity type, address bits and the number of stop bits.
These factors are determined by the setup of various
bits within the UCR1 register. The BNO bit controls the
number of data bits which can be set to either 8 or 9.
The PRT bit controls the choice if odd or even parity.
The PREN bit controls the parity on/off function. The
STOPS bit decides whether one or two stop bits are to
be used. The following table shows various formats
for data transmission. The address detect mode con-
trol bit identifies the frame as an address character.
The number of stop bits, which can be either one or
two, is independent of the data length.
·
Enabling/Disabling the UART
Start
Bit
Data
Bits
Address Parity
Stop
Bit
The basic on/off function of the internal UART function
is controlled using the UARTEN bit in the UCR1 regis-
ter. If the UARTEN, TXEN and RXEN bits are set, then
these two UART pins will act as normal TX output pin
and RX input pin respectively. If no data is being trans-
mitted on the TX pin, then it will default to a logic high
value.
Bits
Bits
Example of 8-bit Data Formats
1
1
1
8
7
7
0
0
1
0
1
0
1
1
1
Clearing the UARTEN bit will disable the TX and RX
pins and these two pins will be in the state of high im-
pedance. When the UART function is disabled, the
buffer will be reset to an empty condition, at the same
time discarding any remaining residual data. Dis-
abling the UART will also reset the enable control, the
error and status flags with bits TXEN, RXEN, TXBRK,
RXIF, OERR, FERR, PERR and NF being cleared
while bits TIDLE, TXIF and RIDLE will be set. The re-
maining control bits in the UCR1, UCR2 and BRG reg-
isters will remain unaffected. If the UARTEN bit in the
UCR1 register is cleared while the UART is active,
Example of 9-bit Data Formats
1
1
1
9
8
8
0
0
1
0
1
0
1
1
1
Transmitter Receiver Data Format
The following diagram shows the transmit and receive
waveforms for both 8-bit and 9-bit data formats.
N
e
t
x
t
P
a
r
i
t
y
B
i
S
t
a
r
t
S
t
a
r
t
B
i
t
B 0
B
i
t
i
t
B
1
i
t
B
2
i
t
B
3
i
t
B
4
i
t
B
5
i
t
B
6
i
t
7
B
i
t
i t
S
t
o
p
B
8
-
B
i
t
D
a
t
a
F
o
r
m
a
t
N
e
t
x
t
P
a
r
i
t
y
B
i
S
t
a
r
t
S
t
a
r
t
B
i
t
B 0
B
i
t
i
t
B
1
i
t
B
2
i
t
B
3
i
t
B
4
i
t
B
5
i
t
B
6
i
t
B
7
i
t
8
B
i
t
i t
S
t
o
p
B
9
-
B
i
t
D
a
t
a
F
o
r
m
a
t
Rev. 1.60
208
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
UART transmitter
This sequence of events can now be repeated to send
additional data.
Data word lengths of either 8 or 9 bits can be selected
by programming the BNO bit in the UCR1 register.
When BNO bit is set, the word length will be set to 9
bits. In this case the 9th bit, which is the MSB, needs
to be stored in the TX8 bit in the UCR1 register. At the
transmitter core lies the Transmitter Shift Register,
more commonly known as the TSR, whose data is ob-
tained from the transmit data register, which is known
as the TXR register. The data to be transmitted is
loaded into this TXR register by the application pro-
gram. The TSR register is not written to with new data
until the stop bit from the previous transmission has
been sent out. As soon as this stop bit has been trans-
mitted, the TSR can then be loaded with new data
from the TXR register, if it is available. It should be
noted that the TSR register, unlike many other regis-
ters, is not directly mapped into the Data Memory area
and as such is not available to the application program
for direct read/write operations. An actual transmis-
sion of data will normally be enabled when the TXEN
bit is set, but the data will not be transmitted until the
TXR register has been loaded with data and the baud
rate generator has defined a shift clock source. How-
ever, the transmission can also be initiated by first
loading data into the TXR register, after which the
TXEN bit can be set. When a transmission of data be-
gins, the TSR is normally empty, in which case a
transfer to the TXR register will result in an immediate
transfer to the TSR. If during a transmission the TXEN
bit is cleared, the transmission will immediately cease
and the transmitter will be reset. The TX output pin will
then return to the high impedance state.
It should be noted that when TXIF=0, data will be in-
hibited from being written to the TXR register. Clear-
ing the TXIF flag is always achieved using the
following software sequence:
1. A USR register access
2. A TXR register write execution
The read-only TXIF flag is set by the UART hardware
and if set indicates that the TXR register is empty and
that other data can now be written into the TXR regis-
ter without overwriting the previous data. If the TEIE
bit is set, then the TXIF flag will generate an interrupt.
During a data transmission, a write instruction to the
TXR register will place the data into the TXR register,
which will be copied to the shift register at the end of
the present transmission. When there is no data
transmission in progress, a write instruction to the
TXR register will place the data directly into the shift
register, resulting in the commencement of data trans-
mission, and the TXIF bit being immediately set.
When a frame transmission is complete, which hap-
pens after stop bits are sent or after the break frame,
the TIDLE bit will be set. To clear the TIDLE bit the fol-
lowing software sequence is used:
1. A USR register access
2. A TXR register write execution
Note that both the TXIF and TIDLE bits are cleared by
the same software sequence.
·
Transmitting break
If the TXBRK bit is set, then the break characters will
be sent on the next transmission. Break character
transmission consists of a start bit, followed by 13´N
²0² bits, where N=1, 2, etc. if a break character is to be
transmitted, then the TXBRK bit must be first set by
the application program and then cleared to generate
the stop bits. Transmitting a break character will not
generate a transmit interrupt. Note that a break condi-
tion length is at least 13 bits long. If the TXBRK bit is
continually kept at a logic high level, then the transmit-
ter circuitry will transmit continuous break characters.
After the application program has cleared the TXBRK
bit, the transmitter will finish transmitting the last break
character and subsequently send out one or two stop
bits. The automatic logic high at the end of the last
break character will ensure that the start bit of the next
frame is recognized.
·
Transmitting data
When the UART is transmitting data, the data is
shifted on the TX pin from the shift register, with the
least significant bit LSB first. In the transmit mode, the
TXR register forms a buffer between the internal bus
and the transmitter shift register. It should be noted
that if 9-bit data format has been selected, then the
MSB will be taken from the TX8 bit in the UCR1 regis-
ter. The steps to initiate a data transfer can be sum-
marized as follows:
¨
Make the correct selection of the BNO, PRT, PREN
and STOPS bits to define the required word length,
parity type and number of stop bits.
¨
¨
Setup the BRG register to select the desired baud
rate.
Set the TXEN bit to ensure that the UART transmit-
ter is enabled and the TX pin is used as a UART
transmitter pin.
¨
Access the USR register and write the data that is to
be transmitted into the TXR register. Note that this
step will clear the TXIF bit.
Rev. 1.60
209
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
UART receiver
The RXIF bit can be cleared using the following soft-
ware sequence:
The UART is capable of receiving word lengths of ei-
ther 8 or 9 bits can be selected by programming the
BNO bit in the UCR1 register. When BNO bit is set, the
word length will be set to 9 bits. In this case the 9th bit,
which is the MSB, will be stored in the RX8 bit in the
UCR1 register. At the receiver core lies the Receiver
Shift Register more commonly known as the RSR.
The data which is received on the RX external input
pin is sent to the data recovery block. The data recov-
ery block operating speed is 16 times that of the baud
rate, while the main receive serial shifter operates at
the baud rate. After the RX pin is sampled for the stop
bit, the received data in RSR is transferred to the re-
ceive data register, if the register is empty. The data
which is received on the external RX input pin is sam-
pled three times by a majority detect circuit to deter-
mine the logic level that has been placed onto the RX
pin. It should be noted that the RSR register, unlike
many other registers, is not directly mapped into the
Data Memory area and as such is not available to the
application program for direct read/write operations.
1. A USR register access
2. A RXR register read execution
·
Receiving break
Any break character received by the UART will be
managed as a framing error. The receiver will count
and expect a certain number of bit times as specified
by the values programmed into the BNO and STOPS
bits. If the break is much longer than 13 bit times, the
reception will be considered as complete after the
number of bit times specified by BNO and STOPS.
The RXIF bit is set, FERR is set, zeros are loaded into
the receive data register, interrupts are generated if
appropriate and the RIDLE bit is set. If a long break
signal has been detected and the receiver has re-
ceived a start bit, the data bits and the invalid stop bit,
which sets the FERR flag, the receiver must wait for a
valid stop bit before looking for the next start bit. The
receiver will not make the assumption that the break
condition on the line is the next start bit. A break is re-
garded as a character that contains only zeros with
the FERR flag set. The break character will be loaded
into the buffer and no further data will be received until
stop bits are received. It should be noted that the
RIDLE read only flag will go high when the stop bits
have not yet been received. The reception of a break
character on the UART registers will result in the fol-
lowing:
·
Receiving data
When the UART receiver is receiving data, the data is
serially shifted in on the external RX input pin to the
shift register, with the least significant bit LSB first.
The RXR register is a four byte deep FIFO data buffer,
where four bytes can be held in the FIFO while the 5th
byte can continue to be received. Note that the appli-
cation program must ensure that the data is read from
RXR before the 5th byte has been completely shifted
in, otherwise the 5th byte will be discarded and an
overrun error OERR will be subsequently indicated.
The steps to initiate a data transfer can be summa-
rized as follows:
¨
¨
¨
The framing error flag, FERR, will be set.
The receive data register, RXR, will be cleared.
The OERR, NF, PERR, RIDLE or RXIF flags will
possibly be set.
·
Idle status
¨
Make the correct selection of the BNO, PRT, PREN
and STOPS bits to define the required word length,
parity type and number of stop bits.
When the receiver is reading data, which means it will
be in between the detection of a start bit and the read-
ing of a stop bit, the receiver status flag in the USR
register, otherwise known as the RIDLE flag, will have
a zero value. In between the reception of a stop bit
and the detection of the next start bit, the RIDLE flag
will have a high value, which indicates the receiver is
in an idle condition.
¨
¨
Setup the BRG register to select the desired baud
rate.
Set the RXEN bit to ensure that the UART receiver
is enabled and the RX pin is used as a UART re-
ceiver pin.
At this point the receiver will be enabled which will be-
gin to look for a start bit.
·
Receiver interrupt
The read only receive interrupt flag RXIF in the USR
register is set by an edge generated by the receiver.
An interrupt is generated if RIE=1, when a word is
transferred from the Receive Shift Register, RSR, to
the Receive Data Register, RXR. An overrun error can
also generate an interrupt if RIE=1.
When a character is received, the following sequence
of events will occur:
¨
¨
¨
The RXIF bit in the USR register will be set then
RXR register has data available, at least three more
character can be read.
When the contents of the shift register have been
transferred to the RXR register and if the RIE bit is
set, then an interrupt will be generated.
If during reception, a frame error, noise error, parity
error or an overrun error has been detected, then
the error flags can be set.
Rev. 1.60
210
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Managing Receiver Errors
UART Module Interrupt Structure
Several types of reception errors can occur within the
UART module, the following section describes the vari-
ous types and how they are managed by the UART.
Several individual UART conditions can generate a
UART interrupt. When these conditions exist, a low
pulse will be generated on the INT line to get the atten-
tion of the microcontroller. These conditions are a trans-
mitter data register empty, transmitter idle, receiver data
available, receiver overrun, address detect and an RX
pin wake-up. When any of these conditions are created,
if its corresponding interrupt control is enabled and the
stack is not full, the program will jump to its correspond-
ing interrupt vector where it can be serviced before re-
turning to the main program. Four of these conditions
have the corresponding USR register flags which will
generate a UART interrupt if its associated interrupt en-
able control bit in the UCR2 register is set. The two
transmitter interrupt conditions have their own corre-
sponding enable control bits, while the two receiver in-
terrupt conditions have a shared enable control bit.
These enable bits can be used to mask out individual
UART interrupt sources.
·
Overrun Error - OERR flag
The RXR register is composed of a four byte deep
FIFO data buffer, where four bytes can be held in the
FIFO register, while a 5th byte can continue to be re-
ceived. Before the 5th byte has been entirely shifted
in, the data should be read from the RXR register. If
this is not done, the overrun error flag OERR will be
consequently indicated.
In the event of an overrun error occurring, the follow-
ing will happen:
¨
¨
¨
¨
The OERR flag in the USR register will be set.
The RXR contents will not be lost.
The shift register will be overwritten.
An interrupt will be generated if the RIE bit is set.
The OERR flag can be cleared by an access to the
USR register followed by a read to the RXR register.
The address detect condition, which is also a UART in-
terrupt source, does not have an associated flag, but will
generate a UART interrupt when an address detect con-
dition occurs if its function is enabled by setting the
ADDEN bit in the UCR2 register. An RX pin wake-up,
which is also a UART interrupt source, does not have an
associated flag, but will generate a UART interrupt if the
microcontroller is woken up by a falling edge on the RX
pin, if the WAKE and RIE bits in the UCR2 register are
set. Note that in the event of an RX wake-up interrupt
occurring, there will be a certain period of delay, com-
monly known as the System Start-up Time, for the oscil-
lator to restart and stabilize before the system resumes
normal operation.
·
Noise Error - NF flag
Over-sampling is used for data recovery to identify
valid incoming data and noise. If noise is detected
within a frame, the following will occur:
¨
¨
¨
The read only noise flag, NF, in the USR register
will be set on the rising edge of the RXIF bit.
Data will be transferred from the shift register to the
RXR register.
No interrupt will be generated. However this bit
rises at the same time as the RXIF bit which itself
generates an interrupt.
Note that the NF flag is reset by a USR register read
operation followed by an RXR register read operation.
·
Framing Error - FERR flag
Note that the USR register flags are read only and can-
not be cleared or set by the application program, neither
will they be cleared when the program jumps to the cor-
responding interrupt servicing routine, as is the case for
some of the other interrupts. The flags will be cleared
automatically when certain actions are taken by the
UART, the details of which are given in the UART regis-
ter section. The overall UART interrupt can be disabled
or enabled by the related interrupt enable control bits in
the interrupt control registers of the microcontroller to
decide whether the interrupt requested by the UART
module is masked out or allowed.
The read only framing error flag, FERR, in the USR
register, is set if a zero is detected instead of stop bits.
If two stop bits are selected, both stop bits must be
high. Otherwise the FERR flag will be set. The FERR
flag is buffered along with the received data and is
cleared in any reset.
·
Parity Error - PERR flag
The read only parity error flag, PERR, in the USR reg-
ister, is set if the parity of the received word is incor-
rect. This error flag is only applicable if the parity
function is enabled, PREN=1, and if the parity type,
odd or even, is selected. The read only PERR flag is
buffered along with the received data bytes. It is
cleared on any reset, it should be noted that the FERR
and PERR flags are buffered along with the corre-
sponding word and should be read before reading the
data word.
Rev. 1.60
211
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
U
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UART Module Interrupt Structure
·
Address detect mode
UART Module Power-down and Wake-up
Setting the Address Detect function enable control bit,
ADDEN, in the UCR2 register, enables this special
function. If this bit is set to ²1², then an additional qual-
ifier will be placed on the generation of a Receiver
Data Available interrupt, which is requested by the
RXIF flag. If the ADDEN bit is equal to ²1², then when
the data is available, an interrupt will only be gener-
ated, if the highest received bit has a high value. Note
that the related interrupt enable control bit and the
EMI bit of the microcontroller must also be enabled for
correct interrupt generation. The highest address bit is
the 9th bit if the bit BNO=1 or the 8th bit if the bit
BNO=0. If the highest bit is high, then the received
word will be defined as an address rather than data. A
Data Available interrupt will be generated every time
the last bit of the received word is set. If the ADDEN bit
is equal to ²0², then a Receive Data Available interrupt
will be generated each time the RXIF flag is set, irre-
spective of the data last but status. The address de-
tect and parity functions are mutually exclusive
functions. Therefore if the address detect function is
enabled, then to ensure correct operation, the parity
function should be disabled by resetting the parity
function enable bit PREN to zero.
The MCU and UART Module are powered down inde-
pendently of each other. The method of powering down
the MCU is covered in the previous MCU section of the
datasheet. The UART Module must be powered down
before the MCU is powered down. This is implemented
by first clearing the UARTEN bit in the UCR1 register to
disable the UART Module circuitry after which the SCS
internal line can be set high to disable the SPI interface
circuits. When the UART and SPI interfaces are pow-
ered down, the SCK and CLKI clock sources to the
UART module will be disabled. The UART Module can
be powered up by the MCU by first clearing the SCS line
to zero and then setting the UARTEN bit. If the UART
circuits is powered down while a transmission is still in
progress, then the transmission will be terminated and
the external TX transmit pin will be forced to a logic high
level. In a similar way, if the UART circuits is powered
down while receiving data, then the reception of data will
likewise be terminated. When the UART circuits is pow-
ered down, note that the USR, UCR1, UCR2, UCR3,
transmit and receive registers, as well as the BRG regis-
ter will not be affected.
Bit 9 if BNO=1, UART Interrupt
ADDEN
The UART Module contains a receiver RX pin wake-up
function, which is enabled or disabled by the WAKE bit
in the UCR2 register. If this bit, along with the UART en-
able bit named UARTEN, the receiver enable bit named
RXEN and the receiver interrupt enable bit named RIE,
are all set before the MCU and UART module are is
powered down, then a falling edge on the RX pin will
wake up the MCU from its power down condition. Note
Bit 8 if BNO=0
Generated
0
1
0
1
Ö
Ö
X
Ö
0
1
ADDEN Bit Function
Rev. 1.60
212
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
The SIM operating mode control bits SIM2~SIM0, in
the SIMC0 register have to be configured to enable
the SIM to operate in the SPI master mode with a dif-
ferent SPI clock frequency.
that as it takes a certain period of time known as the
System Start-up Time for oscillator to restart and stabi-
lize after a wake-up, any data received during this time
on the RX pin will be ignored.
¨
SIM operating mode control bits SIM2~SIM0 in the
SIMC0 Register
For a UART wake-up interrupt to occur, in addition to the
bits for the wake-up enable control and Receive inter-
rupt enable control being set, the global interrupt enable
control and the related interrupt enable control bits must
also be set. If these two bits are not set, then only a
wake-up event will occur and no interrupt will be ser-
viced. Note also that as it takes a period of delay after a
wake-up before normal microcontroller resumes, the
relevant UART interrupt will not be serviced until this pe-
riod of delay time has elapsed.
Bit
Name
value
7
6
5
SIM2
SIM1
SIM0
100, 011, 010, 001 or 000
000: SPI master mode; SPI clock is fSYS/4
001: SPI master mode; SPI clock is fSYS/16
010: SPI master mode; SPI clock is fSYS/64
011: SPI master mode; SPI clock is fTBC
100: SPI master mode; SPI clock is TM0 CCRP
match frequency/2
Using the UART Function
101~111: must not be used
To use the UART function, several important steps must
be implemented to ensure that the UART module oper-
ates normally:
·
The PCK control bit is set to 1 to enable the PCK out-
put as the clock source for the UART baud rate gener-
ator with various PCK output frequencies determined
by the PCKP1 and PCKP0 bits in the SIMC0 Register.
·
The SPI pin-remapping function must be properly
configured when the SPI functional pins of the
microcontroller are used to control the UART module
and for data transmission and data reception.
¨
PCK output frequency selection bits
PCKP1~PCKP0 in the SIMC0 Register
To correctly connect the MCU Master SPI to the UART
Module Slave SPI, the SIM pin-remapping settings for
PCK and PINTB in the MCU PRM0 register should be
the same as the values listed in the following table.
Bit
3
2
Name
Value
PCKP1
PCKP0
11, 10, 01 or 00
¨
¨
¨
HT66FU30
PRM0 Register - PCK and PINT pin-remap setup
00: PCK output frequency is fSYS
01: PCK output frequency is fSYS/4
10: PCK output frequency is fSYS/8
Bit
Name
Setting value
1
SIMPS0
1
0
PCKPS
1
11: PCK output frequency is TM0 CCRP match
frequency/2
¨
PCK output enable control bit PCKEN in the
SIMC0 Register
HT66FU40/HT66FU50
PRM0 Register - PCK and PINT pin-remap setup
Bit
4
PCKEN
1
Bit
Name
2
1
0
Name
Value
SIMPS1 SIMPS0 PCKPS
Setting value
0
1
1
0: Disable PCK output
1: Enable PCK output
HT66FU60
PRM0 Register - PCK and PINT pin-remap setup
After the above setup conditions have been imple-
mented, the MCU can enable the SIM interface by set-
ting the SIMEN bit high. The MCU can then begin
communication with external UART connected devices
using its SPI interface. The detailed MCU Master SPI
functional description is provided within the Serial Inter-
face Module section of the MCU datasheet.
Bit
Name
Setting value
2
1
0
SIMPS1 SIMPS0 PCKPS
1
1
1
Rev. 1.60
213
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Application Circuit with UART Module
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Note:
²*² It is recommended that this component is added for added ESD protection.
²**² It is recommended that this component is added in environments where power line noise is significant.
Rev. 1.60
214
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Instruction Set
Introduction
sure correct handling of carry and borrow data when re-
sults exceed 255 for addition and less than 0 for sub-
Central to the successful operation of any
microcontroller is its instruction set, which is a set of pro-
gram instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontroller, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of pro-
gramming overheads.
traction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Logical and Rotate Operations
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on pro-
gram requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
For easier understanding of the various instruction
codes, they have been subdivided into several func-
tional groupings.
Instruction Timing
Most instructions are implemented within one instruc-
tion cycle. The exceptions to this are branch, call, or ta-
ble read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be im-
plemented within 1ms. Although instructions which re-
quire one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instruc-
tions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to imple-
ment. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instruc-
tions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the re-
sult of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a sub-
routine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the sub-
routine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made re-
garding the condition of a certain data memory or indi-
vidual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the pro-
gram perhaps determined by the condition of certain in-
put switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific imme-
diate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to en-
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Mem-
ory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The fea-
ture removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write pro-
cess is taken care of automatically when these bit oper-
ation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² in-
struction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electro-
magnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be con-
sulted as a basic instruction reference using the follow-
ing listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using regis-
ters. However, when working with large amounts of
fixed data, the volume involved often makes it inconve-
nient to store the fixed data in the Data Memory. To over-
come this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instruc-
tions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Arithmetic
Description
Cycles Flag Affected
ADD A,[m]
ADDM A,[m]
ADD A,x
Add Data Memory to ACC
1
1Note
1
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
Add ACC to Data Memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add Data Memory to ACC with Carry
1
1Note
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
1
1Note
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1Note
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1Note
1Note
1
OR A,x
1
XOR A,x
1
1Note
CPL [m]
CPLA [m]
Complement Data Memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment Data Memory with result in ACC
1
Z
Z
Z
Z
Increment Data Memory
1Note
DECA [m]
DEC [m]
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
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Mnemonic
Rotate
Description
Cycles Flag Affected
RRA [m]
RR [m]
Rotate Data Memory right with result in ACC
Rotate Data Memory right
1
1Note
1
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
1Note
C
1
None
None
C
1Note
1
RLCA [m]
RLC [m]
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1Note
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Branch
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if Data Memory is zero
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRD [m]
Read table to TBLH and Data Memory
2note
2Note
None
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Miscellaneous
NOP
No operation
1
1Note
1Note
1
None
None
CLR [m]
Clear Data Memory
SET [m]
Set Data Memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO, PDF
TO, PDF
TO, PDF
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1
1Note
1
None
1
TO, PDF
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then in-
crements by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruc-
tion.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Operation
Each bit of the specified Data Memory is cleared to 0.
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Description
Operation
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-
sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-
ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Operation
Data in the specified Data Memory is decremented by 1.
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-
mulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Operation
Data in the specified Data Memory is incremented by 1.
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-
lator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Description
Operation
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
Operation
The immediate data specified is loaded into the Accumulator.
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Description
Operation
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-
ation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-
ation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the re-
stored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by set-
ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed be-
fore returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-
main unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-
tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-
places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-
sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Operation
Each bit of the specified Data Memory is set to 1.
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is set to 1.
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumu-
lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-
tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.60
225
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
SWAP [m]
Description
Operation
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruc-
tion.
Operation
Skip if [m] = 0
None
Affected flag(s)
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-
tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
None
Affected flag(s)
TABRD [m]
Read table to TBLH and Data Memory
Description
The program code addressed by the table pointer (TBHP and TBLP) is moved to the speci-
fied Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.60
226
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.60
227
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be updated at regu-
lar intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for
the latest version of the package information.
16-pin DIP (300mil) Outline Dimensions
A
A
9
8
1
6
9
8
1
6
B
B
1
1
H
H
C
D
C
D
G
G
E
E
I
I
F
F
Fig1. Full Lead Packages
Fig2. 1/2 Lead Packages
·
MS-001d (see fig1)
Dimensions in inch
Symbol
Min.
0.780
0.240
0.115
0.115
0.014
0.045
¾
Nom.
¾
Max.
0.880
0.280
0.195
0.150
0.022
0.070
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
0.100
0.300
¾
0.325
0.430
¾
¾
Dimensions in mm
Symbol
Min.
19.81
6.10
2.92
2.92
0.36
1.14
¾
Nom.
¾
Max.
22.35
7.11
4.95
3.81
0.56
1.78
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
2.54
7.62
¾
8.26
10.92
¾
¾
Rev. 1.60
228
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
MS-001d (see fig2)
Dimensions in inch
Symbol
Min.
0.735
0.240
0.115
0.115
0.014
0.045
¾
Nom.
¾
Max.
0.775
0.280
0.195
0.150
0.022
0.070
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
0.100
¾
0.300
¾
0.325
0.430
¾
Dimensions in mm
Symbol
Min.
18.67
6.10
2.92
2.92
0.36
1.14
¾
Nom.
¾
Max.
19.69
7.11
4.95
3.81
0.56
1.78
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
2.54
7.62
¾
8.26
10.92
¾
¾
Rev. 1.60
229
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
MO-095a (see fig2)
Dimensions in inch
Symbol
Min.
0.745
0.275
0.120
0.110
0.014
0.045
¾
Nom.
¾
Max.
0.785
0.295
0.150
0.150
0.022
0.060
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
0.100
¾
0.300
¾
0.325
0.430
¾
Dimensions in mm
Symbol
Min.
18.92
6.99
3.05
2.79
0.36
1.14
¾
Nom.
¾
Max.
19.94
7.49
3.81
3.81
0.56
1.52
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
2.54
7.62
¾
8.26
10.92
¾
¾
Rev. 1.60
230
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
16-pin NSOP (150mil) Outline Dimensions
1
6
9
8
A
B
1
C
C
'
G
H
D
a
F
E
·
MS-012
Dimensions in inch
Symbol
Min.
0.228
0.150
0.012
0.386
¾
Nom.
¾
Max.
0.244
0.157
0.020
0.402
0.069
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.050
¾
¾
0.004
0.016
0.007
0°
0.010
0.050
0.010
8°
G
H
a
¾
¾
¾
Dimensions in mm
Symbol
Min.
5.79
3.81
0.30
9.80
¾
Nom.
¾
Max.
6.20
3.99
0.51
10.21
1.75
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
1.27
¾
0.10
0.41
0.18
0°
0.25
1.27
0.25
8°
¾
¾
¾
¾
G
H
a
Rev. 1.60
231
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
16-pin SSOP (150mil) Outline Dimensions
1
6
9
A
B
1
8
C
C
'
G
H
D
a
E
F
Dimensions in inch
Symbol
Min.
Nom.
¾
Max.
0.244
0.157
0.012
0.197
0.060
¾
A
B
C
C¢
D
E
F
0.228
0.150
0.008
0.189
0.054
¾
¾
¾
¾
¾
0.025
¾
0.004
0.022
0.007
0°
0.010
0.028
0.010
8°
G
H
a
¾
¾
¾
Dimensions in mm
Symbol
Min.
5.79
3.81
0.20
4.80
1.37
¾
Nom.
¾
Max.
6.20
3.99
0.30
5.00
1.52
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.64
0.10
0.56
0.18
0°
0.25
0.71
0.25
8°
¾
¾
¾
¾
G
H
a
Rev. 1.60
232
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
20-pin DIP (300mil) Outline Dimensions
A
A
2
0
1
1
1
0
2
0
1
1
1
0
B
B
1
1
H
H
C
D
C
D
I
I
E
F
G
E
F
G
Fig1. Full Lead Packages
Fig2. 1/2 Lead Packages
·
MS-001d (see fig1)
Dimensions in inch
Symbol
Min.
0.980
0.240
0.115
0.115
0.014
0.045
¾
Nom.
¾
Max.
1.060
0.280
0.195
0.150
0.022
0.070
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
0.100
0.300
¾
0.325
¾
¾
0.430
Dimensions in mm
Symbol
Min.
24.89
6.10
2.92
2.92
0.36
1.14
¾
Nom.
¾
Max.
26.92
7.11
4.95
3.81
0.56
1.78
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
2.54
7.62
¾
8.26
¾
¾
10.92
Rev. 1.60
233
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
MO-095a (see fig2)
Dimensions in inch
Symbol
Min.
0.945
0.275
0.120
0.110
0.014
0.045
¾
Nom.
¾
Max.
0.985
0.295
0.150
0.150
0.022
0.060
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
0.100
¾
0.300
¾
0.325
¾
0.430
Dimensions in mm
Symbol
Min.
24.00
6.99
3.05
2.79
0.36
1.14
¾
Nom.
¾
Max.
25.02
7.49
3.81
3.81
0.56
1.52
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
2.54
7.62
¾
8.26
¾
¾
10.92
Rev. 1.60
234
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
20-pin SOP (300mil) Outline Dimensions
2
0
1
1
A
B
1
1
0
C
C
'
G
H
D
a
E
F
·
MS-013
Dimensions in inch
Symbol
Min.
0.393
0.256
0.012
0.496
¾
Nom.
¾
Max.
0.419
0.300
0.020
0.512
0.104
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.050
¾
¾
0.004
0.016
0.008
0°
0.012
0.050
0.013
8°
G
H
a
¾
¾
¾
Dimensions in mm
Symbol
Min.
9.98
6.50
0.30
12.60
¾
Nom.
¾
Max.
10.64
7.62
0.51
13.00
2.64
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
1.27
¾
0.10
0.41
0.20
0°
0.30
1.27
0.33
8°
¾
¾
¾
¾
G
H
a
Rev. 1.60
235
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
20-pin SSOP (150mil) Outline Dimensions
2
0
1
1
0
A
B
1
1
C
C
'
G
H
D
a
E
F
Dimensions in inch
Symbol
Min.
0.228
0.150
0.008
0.335
0.049
¾
Nom.
¾
Max.
0.244
0.158
0.012
0.347
0.065
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.025
¾
0.004
0.015
0.007
0°
0.010
0.050
0.010
8°
G
H
a
¾
¾
¾
Dimensions in mm
Symbol
Min.
5.79
3.81
0.20
8.51
1.24
¾
Nom.
¾
Max.
6.20
4.01
0.30
8.81
1.65
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.64
0.10
0.38
0.18
0°
0.25
1.27
0.25
8°
¾
¾
¾
¾
G
H
a
Rev. 1.60
236
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
24-pin SKDIP (300mil) Outline Dimensions
A
A
2
4
1
1
3
2
1
1
3
2
2
4
B
B
1
1
H
H
C
D
C
D
I
I
E
F
G
E
F
G
Fig2. 1/2 Lead Packages
Fig1. Full Lead Packages
·
MS-001d (see fig1)
Dimensions in inch
Symbol
Min.
1.230
0.240
0.115
0.115
0.014
0.045
¾
Nom.
¾
Max.
1.280
0.280
0.195
0.150
0.022
0.070
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
0.100
0.300
¾
0.325
¾
¾
0.430
Dimensions in mm
Symbol
Min.
31.24
6.10
2.92
2.92
0.36
1.14
¾
Nom.
¾
Max.
32.51
7.11
4.95
3.81
0.56
1.78
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
2.54
7.62
¾
8.26
¾
¾
10.92
Rev. 1.60
237
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
MS-001d (see fig2)
Dimensions in inch
Symbol
Min.
1.160
0.240
0.115
0.115
0.014
0.045
¾
Nom.
¾
Max.
1.195
0.280
0.195
0.150
0.022
0.070
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
0.100
¾
0.300
¾
0.325
¾
0.430
Dimensions in mm
Symbol
Min.
29.46
6.10
2.92
2.92
0.36
1.14
¾
Nom.
¾
Max.
30.35
7.11
4.95
3.81
0.56
1.78
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
2.54
7.62
¾
8.26
¾
¾
10.92
Rev. 1.60
238
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
·
MO-095a (see fig2)
Dimensions in inch
Symbol
Min.
1.145
0.275
0.120
0.110
0.014
0.045
¾
Nom.
¾
Max.
1.185
0.295
0.150
0.150
0.022
0.060
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
0.100
¾
0.300
¾
0.325
¾
0.430
Dimensions in mm
Symbol
Min.
29.08
6.99
3.05
2.79
0.36
1.14
¾
Nom.
¾
Max.
30.10
7.49
3.81
3.81
0.56
1.52
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
2.54
7.62
¾
8.26
¾
¾
10.92
Rev. 1.60
239
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
24-pin SOP (300mil) Outline Dimensions
2
4
1
3
B
2
A
1
1
C
C
'
G
H
D
a
E
F
·
MS-013
Dimensions in inch
Symbol
Min.
0.393
0.256
0.012
0.598
¾
Nom.
¾
Max.
0.419
0.300
0.020
0.613
0.104
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.050
¾
¾
0.004
0.016
0.008
0°
0.012
0.050
0.013
8°
G
H
a
¾
¾
¾
Dimensions in mm
Symbol
Min.
9.98
6.50
0.30
15.19
¾
Nom.
¾
Max.
10.64
7.62
0.51
15.57
2.64
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
1.27
¾
0.10
0.41
0.20
0°
0.30
1.27
0.33
8°
¾
¾
¾
¾
G
H
a
Rev. 1.60
240
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
24-pin SSOP (150mil) Outline Dimensions
2
4
1
3
A
B
1
1
2
C
C
'
G
H
D
a
E
F
Dimensions in inch
Symbol
Min.
0.228
0.150
0.008
0.335
0.054
¾
Nom.
¾
Max.
0.244
0.157
0.012
0.346
0.060
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.025
0.004
0.022
0.007
0°
0.010
0.028
0.010
8°
¾
¾
¾
¾
G
H
a
Dimensions in mm
Symbol
Min.
5.79
3.81
0.20
8.51
1.37
¾
Nom.
¾
Max.
6.20
3.99
0.30
8.79
1.52
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.64
0.10
0.56
0.18
0°
0.25
0.71
0.25
8°
¾
¾
¾
¾
G
H
a
Rev. 1.60
241
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
28-pin SKDIP (300mil) Outline Dimensions
A
1
1
5
4
2
8
B
1
H
C
D
I
E
F
G
Dimensions in inch
Symbol
Min.
1.375
0.278
0.125
0.125
0.016
0.050
¾
Nom.
¾
Max.
1.395
0.298
0.135
0.145
0.020
0.070
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
0.100
0.295
¾
0.315
¾
¾
0.375
Dimensions in mm
Symbol
Min.
34.93
7.06
3.18
3.18
0.41
1.27
¾
Nom.
¾
Max.
35.43
7.57
3.43
3.68
0.51
1.78
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
2.54
7.49
¾
8.00
¾
¾
9.53
Rev. 1.60
242
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
28-pin SOP (300mil) Outline Dimensions
2
8
1
5
A
B
1
1
4
C
C
'
G
H
D
a
E
F
·
MS-013
Dimensions in inch
Symbol
Min.
0.393
0.256
0.012
0.697
¾
Nom.
¾
Max.
0.419
0.300
0.020
0.713
0.104
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.050
¾
0.004
0.016
0.008
0°
0.012
0.050
0.013
8°
¾
¾
¾
¾
G
H
a
Dimensions in mm
Symbol
Min.
9.98
6.50
0.30
17.70
¾
Nom.
¾
Max.
10.64
7.62
0.51
18.11
2.64
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
1.27
¾
0.10
0.41
0.20
0°
0.30
1.27
0.33
8°
¾
¾
¾
¾
G
H
a
Rev. 1.60
243
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
28-pin SSOP (150mil) Outline Dimensions
2
8
1
1
5
4
A
B
1
C
C
'
G
H
D
a
E
F
Dimensions in inch
Symbol
Min.
0.228
0.150
0.008
0.386
0.054
¾
Nom.
¾
Max.
0.244
0.157
0.012
0.394
0.060
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.025
0.004
0.022
0.007
0°
0.010
0.028
0.010
8°
¾
¾
¾
¾
G
H
a
Dimensions in mm
Symbol
Min.
5.79
3.81
0.20
9.80
1.37
¾
Nom.
¾
Max.
6.20
3.99
0.30
10.01
1.52
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.64
0.10
0.56
0.18
0°
0.25
0.71
0.25
8°
¾
¾
¾
¾
G
H
a
Rev. 1.60
244
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
SAW Type 32-pin (5mm´ 5mm) QFN Outline Dimensions
D
D
2
2
5
3
2
2
4
1
b
E
E
2
e
1
7
8
1
6
9
A
A
1
3
L
K
A
·
ASECL
Dimensions in inch
Symbol
Min.
0.028
0.000
¾
Nom.
¾
Max.
0.031
0.002
¾
A
A1
A3
b
0.001
0.008
0.010
0.197
0.197
0.020
0.007
¾
0.012
¾
D
E
¾
¾
e
¾
¾
D2
E2
L
0.122
0.122
0.014
0.008
0.130
0.130
0.018
¾
¾
¾
0.016
¾
K
Dimensions in mm
Symbol
Min.
0.70
0.00
¾
Nom.
¾
Max.
0.80
0.05
¾
A
A1
A3
b
0.02
0.20
0.25
5.00
5.00
0.50
0.18
¾
0.30
¾
D
E
¾
¾
e
¾
¾
D2
E2
L
3.10
3.10
0.35
0.20
3.30
3.30
0.45
¾
¾
¾
0.40
¾
K
Rev. 1.60
245
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
SAW Type 40-pin (6mm´ 6mm for 0.75mm) QFN Outline Dimensions
D
D
2
3
1
4
0
3
0
1
b
E
E
2
e
2
1
1
0
2
0
1
1
A
A
1
L
K
3
A
·
GTK
Dimensions in inch
Nom.
Symbol
Min.
0.028
0.000
¾
Max.
A
A1
A3
b
0.030
0.031
0.002
¾
0.001
0.008
0.007
¾
0.010
0.012
¾
D
0.236
E
0.236
¾
¾
e
0.020
¾
¾
D2
E2
L
0.173
0.173
0.014
0.008
0.177
0.179
0.179
0.018
¾
0.177
0.016
K
¾
Dimensions in mm
Symbol
Min.
0.70
0.00
¾
Nom.
0.75
0.02
0.20
0.25
6.00
6.00
0.50
4.50
4.50
0.40
¾
Max.
0.80
0.05
¾
A
A1
A3
b
0.18
¾
0.30
¾
D
E
¾
¾
e
¾
¾
D2
E2
L
4.40
4.40
0.35
0.20
4.55
4.55
0.45
¾
K
Rev. 1.60
246
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
44-pin LQFP (10mm´ 10mm) (FP3.2mm) Outline Dimensions
C
H
D
G
3
3
2
3
I
3
4
2
2
F
A
B
E
1
2
4
4
a
K
J
1
1
1
Dimensions in inch
Symbol
Min.
0.512
0.390
0.512
0.390
¾
Nom.
0.520
0.394
0.520
0.394
0.031
0.012
0.055
¾
Max.
0.528
0.398
0.528
0.398
¾
A
B
C
D
E
F
G
H
I
¾
¾
0.053
¾
0.057
0.063
0.010
0.053
0.008
0.004
0.041
0.004
¾
J
0.047
¾
K
a
0°
¾
7°
Dimensions in mm
Symbol
Min.
13.00
9.90
13.00
9.90
¾
Nom.
13.20
10.00
13.20
10.00
0.80
0.30
1.40
¾
Max.
13.40
10.10
13.40
10.10
¾
A
B
C
D
E
F
G
H
I
¾
¾
1.35
¾
1.45
1.60
0.25
1.35
0.25
0.10
1.05
0.10
¾
J
1.20
¾
K
a
0°
¾
7°
Rev. 1.60
247
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
48-pin SSOP (300mil) Outline Dimensions
4
8
2
2
5
4
A
B
1
C
C
'
G
H
D
a
E
F
Dimensions in inch
Symbol
Min.
0.395
0.291
0.008
0.613
0.085
¾
Nom.
¾
Max.
0.420
0.299
0.012
0.637
0.099
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.025
0.004
0.025
0.004
0°
0.010
0.035
0.012
8°
¾
¾
¾
¾
G
H
a
Dimensions in mm
Symbol
Min.
10.03
7.39
0.20
15.57
2.16
¾
Nom.
¾
Max.
10.67
7.59
0.30
16.18
2.51
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.64
0.10
0.64
0.10
0°
0.25
0.89
0.30
8°
¾
¾
¾
¾
G
H
a
Rev. 1.60
248
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
SAW Type 48-pin (7mm´ 7mm) QFN Outline Dimensions
D
D
2
3
7
4
8
1
b
3
6
E
E
2
e
2
5
1
2
1
3
2
4
A
A
1
L
K
3
A
·
ASECL
Dimensions in inch
Nom.
Symbol
Min.
0.031
0.000
¾
Max.
0.035
0.002
¾
A
A1
A3
b
0.033
0.001
0.008
0.007
¾
0.010
0.012
¾
D
0.276
E
0.276
¾
¾
e
0.020
¾
¾
D2
E2
L
0.219
0.219
0.014
0.222
0.226
0.226
0.018
0.222
0.016
Dimensions in mm
Nom.
Symbol
Min.
0.800
0.000
¾
Max.
0.900
0.050
¾
A
A1
A3
b
0.850
0.035
0.203
0.180
¾
0.250
0.300
¾
D
7.000
E
7.000
¾
¾
e
0.500
¾
¾
D2
E2
L
5.550
5.550
0.350
5.650
5.750
5.750
0.450
5.650
0.400
Rev. 1.60
249
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
48-pin LQFP (7mm´ 7mm) Outline Dimensions
C
H
D
G
3
6
2
5
I
3
7
2
4
F
A
B
E
4
8
1
3
a
K
J
1
1
2
Dimensions in inch
Symbol
Min.
0.350
0.272
0.350
0.272
¾
Nom.
¾
Max.
0.358
0.280
0.358
0.280
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
0.020
0.008
¾
¾
0.053
¾
0.057
0.063
¾
¾
¾
0.004
¾
¾
J
0.018
0.004
0°
0.030
0.008
7°
K
a
¾
¾
Dimensions in mm
Symbol
Min.
8.90
6.90
8.90
6.90
¾
Nom.
¾
Max.
9.10
7.10
9.10
7.10
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
0.50
0.20
¾
¾
1.35
¾
1.45
1.60
¾
¾
¾
0.10
¾
¾
J
0.45
0.10
0°
0.75
0.20
7°
K
a
¾
¾
Rev. 1.60
250
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
52-pin QFP (14mm´ 14mm) Outline Dimensions
C
H
D
G
3
9
2
7
I
4
0
2
6
F
A
B
E
1
4
5
2
K
J
1
1
3
Dimensions in inch
Symbol
Min.
0.681
0.547
0.681
0.547
¾
Nom.
¾
Max.
0.689
0.555
0.689
0.555
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
0.039
0.016
¾
¾
0.098
¾
0.122
0.134
¾
¾
¾
0.004
¾
¾
J
0.029
0.004
0°
0.041
0.008
7°
K
a
¾
¾
Dimensions in mm
Symbol
Min.
17.30
13.90
17.30
13.90
¾
Nom.
¾
Max.
17.50
14.10
17.50
14.10
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
1.00
0.40
¾
¾
2.50
¾
3.10
3.40
¾
¾
¾
0.10
¾
¾
J
0.73
0.10
0°
1.03
0.20
7°
K
a
¾
¾
Rev. 1.60
251
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Product Tape and Reel Specifications
Reel Dimensions
D
T
2
C
A
B
T
1
SOP 16N (150mil)
Symbol
Description
Dimensions in mm
330.0±1.0
A
B
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
100.0±1.5
+0.5/-0.2
13.0
C
D
2.0±0.5
+0.3/-0.2
16.8
T1
T2
Space Between Flange
Reel Thickness
22.2±0.2
SOP 20W, SOP 24W, SOP 28W (300mil)
Symbol
Description
Dimensions in mm
330.0±1.0
A
B
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
100.0±1.5
+0.5/-0.2
13.0
C
D
2.0±0.5
+0.3/-0.2
24.8
T1
T2
Space Between Flange
Reel Thickness
30.2±0.2
Rev. 1.60
252
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
SSOP 16S
Symbol
Description
Reel Outer Diameter
Dimensions in mm
330.0±1.0
A
B
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
100.0±1.5
+0.5/-0.2
13.0
C
D
2.0±0.5
+0.3/-0.2
12.8
T1
T2
Space Between Flange
Reel Thickness
18.2±0.2
SSOP 20S (150mil), SSOP 24S (150mil), SSOP 28S (150mil)
Symbol
Description
Reel Outer Diameter
Dimensions in mm
330.0±1.0
A
B
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
100.0±1.5
+0.5/-0.2
13.0
C
D
2.0±0.5
+0.3/-0.2
16.8
T1
T2
Space Between Flange
Reel Thickness
22.2±0.2
SSOP 48W
Symbol
Description
Dimensions in mm
330.0±1.0
A
B
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
100.0±0.1
+0.5/-0.2
13.0
C
D
2.0±0.5
+0.3/-0.2
32.2
T1
T2
Space Between Flange
Reel Thickness
38.2±0.2
Rev. 1.60
253
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Carrier Tape Dimensions
P
0
P
1
t
D
E
F
W
B
0
C
D
1
P
K
0
A
0
R
e
e
l
H
o
l
e
I
C
p
a
c
k
a
g
e
p
i
n
1
a
n
a
r
e
l
o
c
a
t
e
d
o
n
t
h
e
s
SOP 16N (150mil)
Symbol
Description
Dimensions in mm
16.0±0.3
W
P
Carrier Tape Width
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
7.5±0.1
+0.10/-0.00
1.55
D
+0.25/-0.00
1.50
D1
P0
P1
A0
B0
K0
t
4.0±0.1
2.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
6.5±0.1
Cavity Width
10.3±0.1
2.1±0.1
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
0.30±0.05
13.3±0.1
C
SOP 20W
Symbol
Description
Carrier Tape Width
Dimensions in mm
+0.3/-0.1
24.0
W
P
Cavity Pitch
12.0±0.1
1.75±0.10
11.5±0.1
E
Perforation Position
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
F
+0.1/-0.0
1.5
D
+0.25/-0.00
1.50
D1
P0
P1
A0
B0
K0
t
4.0±0.1
2.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
10.8±0.1
13.3±0.1
3.2±0.1
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
0.30±0.05
21.3±0.1
C
Rev. 1.60
254
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
SOP 24W
Symbol
Description
Carrier Tape Width
Dimensions in mm
24.0±0.3
W
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
11.5±0.1
+0.10/-0.00
D
1.55
1.50
+0.25/-0.00
D1
P0
P1
A0
B0
K0
t
4.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
2.0±0.1
10.9±0.1
15.9±0.1
3.1±0.1
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
0.35±0.05
21.3±0.1
C
SOP 28W (300mil)
Symbol
Description
Carrier Tape Width
Cavity Pitch
Dimensions in mm
24.0±0.3
W
P
12.0±0.1
E
Perforation Position
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
1.75±0.10
F
11.5±0.1
+0.1/-0.0
D
1.5
+0.25/-0.00
D1
P0
P1
A0
B0
K0
t
1.50
4.0±0.1
2.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
10.85±0.10
18.34±0.10
2.97±0.10
0.35±0.01
21.3±0.1
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
Rev. 1.60
255
September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
SSOP 16S
Symbol
Description
Carrier Tape Width
Dimensions in mm
+0.3/-0.1
12.0
W
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
5.5±0.1
D
1.55±0.10
+0.25/-0.00
1.50
D1
P0
P1
A0
B0
K0
t
4.0±0.1
2.0±0.1
6.4±0.1
5.2±0.1
2.1±0.1
0.30±0.05
9.3±0.1
Cavity to Perforation (Length Direction)
Cavity Length
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
SSOP 20S (150mil)
Symbol
Description
Carrier Tape Width
Dimensions in mm
+0.3/-0.1
16.0
W
P
Cavity Pitch
8.0±0.1
1.75±0.10
7.5±0.1
E
Perforation Position
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
F
+0.1/-0.0
1.5
D
+0.25/-0.00
1.50
D1
P0
P1
A0
B0
K0
t
4.0±0.1
2.0±0.1
6.5±0.1
9.0±0.1
2.3±0.1
0.30±0.05
13.3±0.1
Cavity to Perforation (Length Direction)
Cavity Length
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
SSOP 24S (150mil)
Symbol
Description
Carrier Tape Width
Dimensions in mm
16.0+0.3/-0.1
W
P
Cavity Pitch
Perforation Position
8.0±0.1
E
1.75±0.10
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
7.5±0.1
1.5+0.1/-0.0
1.50+0.25/-0.00
4.0±0.1
D
D1
P0
P1
A0
B0
K0
t
Cavity to Perforation (Length Direction)
Cavity Length
2.0±0.1
6.5±0.1
Cavity Width
9.5±0.1
Cavity Depth
2.1±0.1
Carrier Tape Thickness
Cover Tape Width
0.30±0.05
13.3±0.1
C
SSOP 28S (150mil)
Symbol
Description
Carrier Tape Width
Dimensions in mm
16.0±0.3
W
P
Cavity Pitch
8.0±0.1
E
Perforation Position
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
1.75±0.1
F
7.5±0.1
+0.10/-0.00
D
1.55
+0.25/-0.00
D1
P0
P1
A0
B0
K0
t
1.50
4.0±0.1
2.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
6.5±0.1
Cavity Width
10.3±0.1
2.1±0.1
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
0.30±0.05
13.3±0.1
C
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September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Carrier Tape Dimensions
P
0
P
1
t
D
E
F
B
0
W
C
K
1
D
1
P
K
2
A
0
R
e
e
l
H
o
l
e
(
C
i
r
c
l
e
)
I
C
p
a
c
k
a
g
e
p
i
n
1
a
n
d
t
h
e
r
e
a
r
e
l
o
c
a
t
e
d
o
n
t
h
e
s
a
m
e
s
i
d
R
e
e
l
H
o
l
e
(
E
l
l
i
p
s
e
)
SSOP 48W
Symbol
Description
Dimensions in mm
32.0±0.3
W
P
Carrier Tape Width
Cavity Pitch
16.0±0.1
E
Perforation Position
1.75±0.10
14.2±0.1
F
Cavity to Perforation (Width Direction)
Perforation Diameter
D
2 Min.
+0.25/-0.00
D1
P0
P1
A0
B0
K1
K2
t
Cavity Hole Diameter
1.50
Perforation Pitch
4.0±0.1
2.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
12.0±0.1
16.2±0.1
2.4±0.1
Cavity Width
Cavity Depth
Cavity Depth
3.2±0.1
Carrier Tape Thickness
Cover Tape Width
0.35±0.05
25.5±0.1
C
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September 9, 2011
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.60
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September 9, 2011
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