HT82K70A-L_技术文档

HT82K70E-L/HT82K70A-L/HT82K76E-L

I/O Type 8-Bit MCU

Technical Document

·

Application Note

-

HA0075E MCU Reset and Oscillator Circuits Application Note

Features

·

Operating voltage: 1.8V~5.5V

43 bidirectional I/O lines

Program Memory:

Crystal and RC oscillator

8-level subroutine nesting

Bit manipulation instruction

Low voltage detector

4K´16 -- HT82K70E-L/HT82K70A-L

8K´16 -- HT82K76E-L

Table read instructions

63 powerful instructions

·

216´8 Data RAM

One external interrupt input shared with I/O lines

All instructions executed in one or two machine

cycles

Two 16-bit programmable Timer/Event Counters

with overflow interrupt

·

Integrated SPI interface (Max. 8Mb/s)

·

Watchdog Timer function

Some pins with CMOS and NMOS outputs

Power down and wake-up functions to reduce power

consumption

28/48-pin SSOP, 32-pin QFN and

48-pin LQFP packages

General Description

The device is an 8-bit high performance, RISC architec-

ture microcontroller devices specifically designed for

multiple I/O control product applications. The low volt-

age operating requirements of these devices opens up

new application possibilities.

The advantages of low power consumption, I/O flexibil-

ity, timer functions, oscillator options, Power-down

wake-up functions, Watchdog timer, motor driving, in-

dustrial control, consumer products, subsystem control-

lers, etc.

Selection Table

Program

Memory

Data

16-bit

Timer

LVD for

Part No.

I/O

SPI

Stack

Package

Memory

Battery-in

HT82K70E-L

HT82K70A-L

4K´16

8K´16

28/48SSOP

43

2

8

216´8

Ö

32QFN, 48LQFP

HT82K76E-L

Rev. 1.20

1

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Block Diagram

W

a

t

c

h

d

o

g

W

a

t

c

h

d

o

g

T

i

m

e

r

T

i

m

e

r

O

s

c

i

l

P

r

o

g

r

a

m

D

a

t

a

S

t

a

c

k

M

e

m

o

r

y

M

e

m

o

r

y

R

e

s

e

t

8

-

b

i

t

C

i

r

c

u

i

t

R

I

S

C

M

C

U

C

o

r

e

I

n

t

e

r

u

p

t

C

o

n

t

r

o

l

e

r

L

o

w

S

P

I

/

O

1

6

-

b

i

t

V

o

l

t

a

g

e

R

C

/

C

r

y

s

t

a

l

I

n

t

2

e

r

f

a

c

e

P

o

r

t

s

T

i

m

e

r

x

D

e

t

e

c

t

O

s

c

i

l

a

t

o

r

Pin Assignment

P

B

5

4

P

O

V

R

P

B

A

F

E

6

7

4

5

6

7

4

3

2

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

1

2

3

4

5

6

7

8

9

1

2

5

2

6

3

7

3

8

9

0

1

2

1

2

3

4

5

6

7

8

2

1

4

3

2

1

0

9

8

7

P

D

0

V

P

S

D

B

A

S

P

A

3

2

/

T

M

R

1

0

/

S

C

D

S

K

I

O

P

D

1

4

P

E

4

/

B

A

T

5

H

T

8

2

K

7

0

6

E

-

L

P

A

1

0

/

Z

2

1

R

E

S

0

1

2

3

0

/

V

1

H

T

8

2

K

7

0

A

-

L

V

D

2

O

S

C

1

3

2

Q

F

N

-

A

P

B

3

2

7

O

S

2

P

A

7

/

S

D

O

/

Z

1

9

1

0

1

2

1

3

1

4

1

5

1

P

B

1

0

/

V

2

1

6

5

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

P

B

5

4

P

O

V

R

P

B

A

6

7

4

5

6

7

1

2

3

4

5

6

7

8

9

1

2

1

8

7

6

5

4

3

2

1

0

9

8

7

6

5

P

F

1

0

7

6

5

4

S

C

2

1

P

A

3

2

/

T

M

R

1

0

/

S

C

D

S

K

I

O

P

D

S

E

P

A

1

0

/

Z

2

1

E

D

C

4

/

B

A

T

3

2

1

0

7

6

5

4

3

P

B

3

2

S

C

2

1

V

S

4

8

4

7

4

6

4

5

4

3

4

P

E

2

3

0

1

2

3

4

5

6

7

8

9

1

3

2

6

5

4

3

2

1

0

9

8

7

6

5

P

A

0

/

Z

1

P

O

V

R

P

F

E

2

P

B

1

0

/

V

2

1

D

S

P

B

3

2

7

6

5

E

0

1

2

3

4

P

C

P

B

1

/

V

2

1

V

S

E

C

4

/

B

A

T

P

B

0

/

V

S

C

H

T

8

2

K

7

0

6

E

-

L

P

E

2

3

6

5

4

P

C

2

/

I

N

T

P

D

7

6

5

4

C

S

1

H

T

8

2

K

7

0

A

-

L

P

E

0

1

7

F

D

S

4

8

L

Q

P

-

A

P

C

2

/

I

N

T

E

D

4

H

T

8

2

K

7

0

6

E

-

L

H

T

8

E

2

K

-

L

7

0

1

2

V

S

3

2

1

H

T

8

2

K

7

0

A

-

L

H

T

8

2

K

7

0

A

-

L

P

E

2

H

T

8

2

K

7

6

E

-

L

N

C

2

8

S

O

P

-

A

4

8

S

O

P

-

A

1

3

1

4

1

5

1

6

1

7

1

8

1

Rev. 1.20

2

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Pin Description

Pin Name

I/O

Options

Description

Bidirectional 8-bit input/output port. Each pin can be configured as a

wake-up input by a configuration option. Software instructions determine if

the pin is a CMOS output or input. Configuration options determine if the

pins have pull-high resistors. Configuration options determine whether the

pins are configured as CMOS or NMOS pins. Configuration options deter-

mine whether the pins are configured with Schmitt trigger or non-Schmitt

trigger inputs. PA2 is shared with the external timer input pin TMR0. PA3 is

shared with the external timer input pin TMR1. PA0 and PA1 are shared

with the Z1 and Z2 pins. PA4~ PA7 are pins shared with SPI interface.

PA0/Z1

Wake-up

Pull-high

PA1/Z2

PA2/TMR0

PA3/TMR1

PA4/SCS

PA5/SCK

PA6/SDI

PA7/SDO

CMOS or NMOS

I/O

Schmitt trigger or

non-Schmitt

trigger

Bidirectional 8-bit input/output port. Each pin, PB0 and PB1 can be config-

ured as wake-up inputs using configuration options. Two configuration op-

tions, one for pins PB2 and PB3 and one for pins PB4~PB7, can also setup

these pin groups as wake-up inputs. Software instructions determine if the

pin is a CMOS output or Schmitt Trigger input. Configuration options deter-

mine if each nibble, PB0~PB3 and PB4~PB7 have pull-high resistors. PB0

and PB1 are shared with the V1 and V2 pins.

PB0/V1

PB1/V2

PB2~PB7

Wake-up

Pull-high

I/O

Bidirectional 8-bit input/output port. Each nibble, PC0~PC3 and PC4~PC7,

can be configured as wake-up inputs by configuration options. Software in-

structions determine if the pin is a CMOS output or Schmitt Trigger input.

Configuration options determine if each nibble, PC0~PC3 and PC4~PC7

have pull-high resistors. PC2 is pin shared with the external interrupt input.

PC0~PC1

PC2/INT

Wake-up

Pull-high

I/O

PC3~PC7

Bidirectional 8-bit input/output port. Each nibble, PD0~PD3 and PD4~PD7,

can be configured as wake-up inputs by configuration options. Software in-

structions determine if the pin is a CMOS output or Schmitt Trigger input.

Configuration options determine if each nibble, PD0~PD3 and PD4~PD7

have pull-high resistors.

Wake-up

Pull-high

PD0~PD7

Bidirectional 8-bit input/output port. Each nibble, PE0~PE3 and PE4~PE7,

can be configured as wake-up inputs by configuration options. Software in-

structions determine if the pin is a CMOS output or Schmitt Trigger input.

Configuration options determine if each nibble, PE0~PE3 and PE4~PE7

have pull-high resistors. A configuration option determines if PE4 is an I/O

pin or a Battery input pin.

Wake-up

Pull-high

PE0~PE3

PE4/BAT

PE5~PE7

I/O

PE4 IO or BAT

Bidirectional 3-bit input/output port. The pins, PF0~PF2 can be configured

together to be wake-up inputs using a configuration options. Software in-

structions determine if the pin is a CMOS output or Schmitt Trigger input. A

configuration option determine if the pins have pull-high resistors.

Wake-up

Pull-high

PF0~PF2

OSC1, OSC2 are connected to an external RC network or external crystal,

determined by configuration option, for the internal system clock. If the RC

system clock option is selected, pin OSC2 can be used to measure the sys-

tem clock at 1/4 frequency.

OSC1

OSC2

I

Crystal or RC

O

RES

VSS

VDD

I

Schmitt trigger reset input. Active low

Negative power supply, ground

Positive power supply

¾

Note: Each pin can be chosen via configuration option to have a wake-up function.

Rev. 1.20

3

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Absolute Maximum Ratings

Supply Voltage...........................V_SS-0.3V to V_SS+6.0V

Input Voltage..............................V_SS-0.3V to V_DD+0.3V

Storage Temperature............................-50°C to 125°C

Operating Temperature...........................-40°C to 85°C

I

_OLTotal ..............................................................150mA

I

_OHTotal............................................................-100mA

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed

in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

f_SYS=4MHz

1.8

3.3

¾

5.5

2

V

¾

1

V_DD

Operating Voltage (Crystal OSC)

f_SYS=8MHz

I_DD

No load, f_SYS=6MHz

Operating Current (Crystal OSC)

Standby Current

3V

mA

No load, system HALT,

WDT Enabled

I_STB1

20

5

¾

mA

V

No load, system HALT,

WDT Disabled

I_STB2

V_IL1

V_IH1

Standby Current

3V

¾

Input Low Voltage for I/O, TMR

and INT

0.3V_DD

V_DD

0

¾

Input High Voltage for I/O, TMR

and INT

0.7V_DD

V

V_IL2

V_IH2

I_OL

0.4V_DD

V_DD

Input Low Voltage (RES)

Input High Voltage (RES)

I/O Port Sink Current

0

0.9V_DD

4

V

¾

V

_OL=0.1V_DD

_OH=0.9V_DD

3V

mA

kW

¾

50

I_OH

V

I/O Port Source Current

Pull-high Resistance

-2.5

10

-4.5

30

R_PH

¾

Rev. 1.20

4

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

A.C. Characteristics

Ta=25°C

Test Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

Conditions

1.8V~5.5V

3.3V~5.5V

400

4000

8000

kHz

¾

f_SYS

System Clock (Crystal OSC)

¾

Watchdog OSC with 6-stage

Prescaler Period

f_RCSYS

f_SPI

3V

71

¾

ms

¾

f_SYS/64

f_SYS

SPI Clock

¾

Watchdog Time-out Period

(WDT OSC)

t_WDT

3V WDTS=1

4.57

ms

¾

t_RES

External Reset Low Pulse Width

System Start-up Timer Period

Oscillation Start-up Timer Period

1

ms

t_RCSYS

t_SYS

¾

t_CONFIGURE

t_OST

1024

512

¾

Note: t_SYS=1/f_SYS

t_RCSYS=1/f_RCSYS

D.C. - A.C. Power-on Reset Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

1.8V~

5.5V

I_POR

Operating Current

0.7

¾

0.05

0.9

2

¾

mA

V/ms

V

VDD Rise Rate to Ensure

Power-on Reset

Without 0.1mF between

VDD and VSS

RSR_POR

¾

Maximum V_DDStart Voltage to

Ensure Power-on Reset

Ta=25°C, Without 0.1mF

between VDD and VSS

V_{POR_MAX}

1.5

¾

Without 0.1mF between

VDD and VSS

ms

t_OPR

Power-on Reset Low Pulse Width

With 0.1mF between

VDD and VSS

10

¾

Rev. 1.20

5

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

System Architecture

A key factor in the high-performance features of the

Holtek range of microcontrollers is attributed to the inter-

nal system architecture. The range of devices take ad-

vantage of the usual features found within RISC

microcontrollers providing increased speed of operation

and enhanced performance. The pipelining scheme is

implemented in such a way that instruction fetching and

instruction execution are overlapped, hence instructions

are effectively executed in one cycle, with the exception

of branch or call instructions. An 8-bit wide ALU is used

in practically all operations of the instruction set. It car-

ries out arithmetic operations, logic operations, rotation,

increment, decrement, branch decisions, etc. The inter-

nal data path is simplified by moving data through the

Accumulator and the ALU. Certain internal registers are

implemented in the Data Memory and can be directly or

indirectly addressed. The simple addressing methods of

these registers along with additional architectural fea-

tures ensure that a minimum of external components is

required to provide a functional I/O control system with

maximum reliability and flexibility.

Program Counter is incremented at the beginning of the

T1 clock during which time a new instruction is fetched.

The remaining T2~T4 clocks carry out the decoding and

execution functions. In this way, one T1~T4 clock cycle

forms one instruction cycle. Although the fetching and

execution of instructions takes place in consecutive in-

struction cycles, the pipelining structure of the

microcontroller ensures that instructions are effectively

executed in one instruction cycle. The exception to this

are instructions where the contents of the Program

Counter are changed, such as subroutine calls or

jumps, in which case the instruction will take one more

instruction cycle to execute.

For instructions involving branches, such as jump or call

instructions, two machine cycles are required to com-

plete instruction execution. An extra cycle is required as

the program takes one cycle to first obtain the actual

jump or call address and then another cycle to actually

execute the branch. The requirement for this extra cycle

should be taken into account by programmers in timing

sensitive applications

Clocking and Pipelining

The main system clock, derived from either a Crys-

tal/Resonator or RC oscillator is subdivided into four in-

ternally generated non-overlapping clocks, T1~T4. The

O

s

c

i

l

a

t

o

r

C

l

o

c

k

(

S

y

s

t

e

m

C

l

o

c

k

)

P

h

a

l

o

c

k

T

1

P

h

a

s

e

C

l

o

c

k

T

2

3

4

P

r

o

g

r

a

m

C

o

u

n

t

e

r

P

C

P

C

+

1

P

C

+

2

F

e

t

c

h

I

n

s

t

.

(

P

C

)

P

i

p

e

l

i

n

i

n

g

E

x

e

c

u

t

e

I

n

s

t

.

(

P

C

-

1

)

t .

F

e

t

c

h

I

n

s

(

P

C

+

1

)

E

x

e

c

u

t

e

I

n

s

t

.

(

P

C

)

n

F

e

t

c

h

I

s

t

.

(

P

C

+

2

)

E

x

e

c

u

t

e

I

n

s

t

.

(

P

C

+

System Clocking and Pipelining

F

e

t

c h

]

I

n

s

t

.

1

E

x

e

c

u

t

e

I

n

s

t

.

1

2

3

4

5

6

M

C

:

N

O

V

A

,

[

E

1

2

H

F

e

t

c

h

E

I

x

n

e

s

c

t

u

.

t

2

e

I

n

s

t

.

3

2

A

P

L

D

L

A

Y

F

e

t

c

h

F

I

l

n

u

s

t

h

.

P

i

p

e

l

i

n

e

[

1

2

H

]

F

e

t

c

h

E

I

x

n

e

s

c

t

u

.

t

6

e

I

n

s

F

e

t

c

h

I

n

s

t

D

E

L

A

Y

O

:

P

Instruction Fetching

Rev. 1.20

6

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Program Counter

Stack

During program execution, the Program Counter is used

to keep track of the address of the next instruction to be

executed. It is automatically incremented by one each

time an instruction is executed except for instructions,

such as ²JMP² or ²CALL² that demand a jump to a

non-consecutive Program Memory address. It must be

noted that only the lower 8 bits, known as the Program

Counter Low Register, are directly addressable by user.

This is a special part of the memory which is used to

save the contents of the Program Counter only. The

stack has 8 levels and is neither part of the data nor part

of the program space, and is neither readable nor

writeable. The activated level is indexed by the Stack

Pointer, SP, and is neither readable nor writeable. At a

subroutine call or interrupt acknowledge signal, the con-

tents of the Program Counter are pushed onto the stack.

At the end of a subroutine or an interrupt routine, sig-

naled by a return instruction, RET or RETI, the Program

Counter is restored to its previous value from the stack.

After a device reset, the Stack Pointer will point to the

top of the stack.

When executing instructions requiring jumps to

non-consecutive addresses such as a jump instruction,

a subroutine call, interrupt or reset, etc., the

microcontroller manages program control by loading the

required address into the Program Counter. For condi-

tional skip instructions, once the condition has been

met, the next instruction, which has already been

fetched during the present instruction execution, is dis-

carded and a dummy cycle takes its place while the cor-

rect instruction is obtained.

P

r

o

g

r

a

m

T

o

p

o

f

S

t

a

c

k

L

e

v

e

l

1

2

3

S

t

a

c

k

P

r

o

g

r

a

P

o

i

n

t

e

r

The lower byte of the Program Counter, known as the

Program Counter Low register or PCL, is available for

program control and is a readable and writeable register.

By transferring data directly into this register, a short pro-

gram jump can be executed directly, however, as only

this low byte is available for manipulation, the jumps are

limited to the present page of memory, that is 256 loca-

tions. When such program jumps are executed it should

also be noted that a dummy cycle will be inserted.

M

e

m

o

r

B

o

t

o

m

o

S

f

t

a

S

c

t

k

a

c

L

k

e

v

e

l

8

If the stack is full and an enabled interrupt takes place,

the interrupt request flag will be recorded but the ac-

knowledge signal will be inhibited. When the Stack

Pointer is decremented, by RET or RETI, the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

However, when the stack is full, a CALL subroutine in-

struction can still be executed which will result in a stack

overflow. Precautions should be taken to avoid such

cases which might cause unpredictable program

branching.

The lower byte of the Program Counter is fully accessi-

ble under program control. Manipulating the PCL might

cause program branching, so an extra cycle is needed

to pre-fetch. Further information on the PCL register can

be found in the Special Function Register section.

Program Counter Bits

Mode

b12

0

b11

0

b10

0

b9

0

b8

0

b7

0

b6

0

b5

0

b4

0

b3

0

b2

0

b1

0

b0

0

Initial Reset

INT Interrupt

0

1

0

Timer/Event Counter 0 Overflow

Timer/Event Counter 1 Overflow

SPI Interrupt

0

1

0

1

0

1

0

Skip

Program Counter + 2

Loading PCL

PC12 PC11 PC10 PC9 PC8

@7

#7

@6

#6

@5

#5

@4

#4

@3

#3

@2

#2

@1

#1

@0

#0

Jump, Call Branch

Return from Subroutine

#12

S12

#11

S11

#10

S10

#9

S9

#8

S8

S7

S6

S5

S4

S3

S2

S1

S0

Program Counter

Note: PC12~PC8: Current Program Counter bits

#12~#0: Instruction code address bits

@7~@0: PCL bits

S12~S0: Stack register bits

For the HT82K70E-L and HT82K70A-L, the Program Counter Bits is 12 bits wide, the b12 column in the table

is not applicable

For the HT82K76E-L, the Program Counter Bits is 13 bits wide, i.e. from b12 ~ b0

Rev. 1.20

7

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Arithmetic and Logic Unit - ALU

tion and interrupt entries. Table data, which can be

setup in any location within the Program Memory, is ad-

dressed by separate table pointer registers.

The arithmetic-logic unit or ALU is a critical area of the

microcontroller that carries out arithmetic and logic op-

erations of the instruction set. Connected to the main

microcontroller data bus, the ALU receives related in-

struction codes and performs the required arithmetic or

logical operations after which the result will be placed in

the specified register. As these ALU calculation or oper-

ations may result in carry, borrow or other status

changes, the status register will be correspondingly up-

dated to reflect these changes. The ALU supports the

following functions:

Special Vectors

Within the Program Memory, certain locations are re-

served for special usage such as reset and interrupts.

·

Location 000H

This vector is reserved for use by the device reset for

program initialisation. After a device reset is initiated, the

program will jump to this location and begin execution.

Location 004H

·

Arithmetic operations: ADD, ADDM, ADC, ADCM,

SUB, SUBM, SBC, SBCM, DAA

This vector is used by the external interrupt. If the INT

external input pin on the device receives a high to low

transition, the program will jump to this location and

begin execution, if the interrupt is enabled and the

stack is not full.

Logic operations: AND, OR, XOR, ANDM, ORM,

XORM, CPL, CPLA

Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,

RLC

·

Location 008H

·

This vector is used by the timer0 counter. If a counter

overflow occurs, the program will jump to this location

and begin execution if the timer interrupt is enabled

and the stack is not full.

Increment and Decrement INCA, INC, DECA, DEC

Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,

SIZA, SDZA, CALL, RET, RETI

Location 00CH

Program Memorys

This vector is used by the timer1 counter. If a counter

overflow occurs, the program will jump to this location

and begin execution if the timer interrupt is enabled

and the stack is not full.

The Program Memory is the location where the user

code or program is stored. The HT82K70E-L and

HT82K76E-L are a One-Time Programmable, OTP,

memory type device where users can program their ap-

plication code into the device. By using the appropriate

programming tools, OTP devices offer users the flexibil-

ity to freely develop their applications which may be use-

ful during debug or for products requiring frequent

upgrades or program changes. OTP devices are also

applicable for use in applications that require low or me-

dium volume production runs. The HT82K70A-L is a

Mask memory type device and offers the most cost ef-

fective solution for high volume products.

Location 010H

This vector is used by serial interface . When 8-bits of

data have been received or transmitted successfully

from serial interface, the program will jump to this lo-

cation and begin execution if the interrupt is enabled

and the stack is not full.

·

Table location

Any location in the program memory can be used as

look-up tables. There are three method to read the

ROM data by two table read instructions: ²TABRDC²

and ²TABRDL², transfer the contents of the lower-or-

der byte to the specified data memory, and the

higher-order byte to TBLH. The three methods are

shown as follows:

Structure

The Program Memory has a capacity of 4K by 16 or 8K

by 16 bits. The Program Memory is addressed by the

Program Counter and also contains data, table informa-

¨

The instructions ²TABRDC [m]² (the current page,

one page=256words), where the table locations is

defined by TBLP in the current page. And the

configuration option TBHP is disabled (default).

H

T

8

2

K

7

0

E

-

L

H

T

8

2

K

7

0

A

-

L

H

T

8

2

K

7

6

0

4

8

H

0

4

8

H

I

n

i

t

i

a

l

i

s

a

t

i

o

n

I

n

i

t

i

a

l

i

s

V

e

c

t

o

r

V

e

c

t

o

r

¨

The instructions ²TABRDC [m]², where the table lo-

E

x

t

e

r

n

a

l

E

x

t

e

r

n

a

cations is defined by registers TBLP (07H) and

TBHP (01FH). And the configuration option TBHP

is enabled.

I

n

t

e

r

u

p

t

V

e

c

t

o

n

r

t

e

r

u

p

T

i

m

e

r

/

E

v

e

n

t

C

o

T

u

i

n

m

t

e

r

/

E

0

v

e

I

n

0

C

H

0

C

H

¨

The instructions ²TABRDL [m]², where the table lo-

cations is defined by Registers TBLP (07H) in the

T

i

m

e

r

/

E

v

e

n

t

C

o

T

u

i

n

m

t

e

r

/

E

1

v

e

I

n

t

e

r

u

p

t

V

e

c

t

I

o

n

r

t

e

r

u

p

0

1

0

H

0

1

0

H

last page (0F00H~0FFFH or 1F00H~1FFFH).

S

P

I

S

P

I

n

t

e

r

u

p

t

V

e

c

t

o

n

r

t

e

r

u

p

0

F

H

1

F

H

1

6

b

i

t

s

1

6

b

i

t

s

Program Memory Structure

Rev. 1.20

8

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Only the destination of the lower-order byte in the ta-

ble is well-defined, the other bits of the table word are

transferred to the lower portion of TBLH, and the re-

maining 1-bit words are read as ²0². The Table

Higher-order byte register (TBLH) is read only. The ta-

ble pointer (TBLP, TBHP) is a read/write register,

which indicates the table location. Before accessing

the table, the location must be placed in the TBLP and

TBHP (If the OTP option TBHP is disabled, the value

in TBHP has no effect). The TBLH is read only and

cannot be restored. If the main routine and the ISR

(Interrupt Service Routine) both employ the table read

instruction, the contents of the TBLH in the main rou-

tine are likely to be changed by the table read instruc-

tion used in the ISR. Errors can occur. In other words,

using the table read instruction in the main routine and

the ISR simultaneously should be avoided.

T

B

H

P

r

o

g

r

a

m

M

e

m

o

r

y

T

B

L

P

T

B

L

H

S

p

e

c

i

f

i

e

d

H

i

g

h

B

y

t

e

o

f

L

o

T

w

a

b

B

l

y

e

t

e

C

o

f

Table Read - TBLP/TBHP

Table Program Example

The following example, for the HT82K76E_L, shows

how the table pointer and table data is defined and re-

trieved from the microcontroller. This example uses raw

table data located in the last page which is stored there

using the ORG statement. The value at this ORG state-

ment is ²1F00H² which refers to the start address of the

last page within the 8K Program Memory of device. The

table pointer is setup here to have an initial value of

²06H². This will ensure that the first data read from the

data table will be at the Program Memory address

²1F06H² or 6 locations after the start of the last page.

Note that the value for the table pointer is referenced to

the first address of the present page if the ²TABRDC

[m]² instruction is being used. The high byte of the table

data which in this case is equal to zero will be trans-

ferred to the TBLH register automatically when the

²TABRDL [m]² instruction is executed.

However, if the table read instruction has to be applied

in both the main routine and the ISR, the interrupt

should be disabled prior to the table read instruction. It

will not be enabled until the TBLH has been backed

up. All table related instructions require two cycles to

complete the operation. These areas may function as

normal program memory depending on the require-

ments.

Once configuration option is enabled, the instruction

²TABRDC [m]² reads the ROM data as defined by

TBLP and TBHP value. Otherwise, the configuration

option TBHP is disabled, the instruction ²TABRDC

[m]² reads the ROM data as defined by TBLP and the

current program counter bits.

The following diagram illustrates the addressing/data

flow of the look-up table:

P

r

o

g

r

a

m

C

o

u

n

t

e

r

H

i

g

h

B

y

t

e

r o

P

g

r

a

m

M

e

m

o

r

y

T

B

L

P

T

B

L

H

S

p

e

c

i

f

i

e

d

T

a

b

l

e

C

o

t n

h

T

a

b

l

e

C

o

n

t

e

n

t

s

H

i

g

Table Read - TBLP only

Table Location Bits

Instruction

b12

TABRDC[m] PC12 PC11 PC10 PC9 PC8

TABRDL [m]

b11

b10

b9

b8

b7

@7

b6

@6

b5

@5

b4

@4

b3

@3

b2

@2

b1

@1

b0

@0

1

Table Location

Note: PC12~PC8: Current Program Counter bits when configuration option TBHP is disable

@7~@0: Table Pointer TBLP bits

For the HT82K70E-L and HT82K70A-L, the table address location is 12 bits wide, i.e. from b11 ~ b0

For the HT82K76E-L, the table address location is 13 bits wide, i.e. from b12 ~ b0

Rev. 1.20

9

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

·

Table Read Program Example

tempreg1 db

tempreg2 db

?

; temporary register #1

; temporary register #2

:

mov a,06h

; initialise table pointer - note that this address

; is referenced

mov tblp,a

; to the last page or present page

:

tabrdl

tempreg1

tempreg2

; transfers value in table referenced by table pointer

; to tempregl

; data at prog. memory address ²1F06H² transferred to

; tempreg1 and TBLH

dec tblp

tabrdl

; reduce value of table pointer by one

; transfers value in table referenced by table pointer

; to tempreg2

; data at prog.memory address ²1F05H² transferred to

; tempreg2 and TBLH

; in this example the data ²1AH² is transferred to

; tempreg1 and data ²0FH² to register tempreg2

; the value ²00H² will be transferred to the high byte

; register TBLH

:

org 1F00h

; sets initial address of last page

dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh

:

Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection

if both the main routine and Interrupt Service Routine use the table read instructions. If using the table read instructions,

the Interrupt Service Routines may change the value of TBLH and subsequently cause errors if used again by the main

routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However,

in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any

main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete

their operation.

Rev. 1.20

10

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Data Memory

The Data Memory is a volatile area of 8-bit wide RAM

internal memory and is the location where temporary in-

formation is stored. Divided into two sections, the first of

these is an area of RAM where special function registers

are located. These registers have fixed locations and

are necessary for correct operation of the device. Many

of these registers can be read from and written to di-

rectly under program control, however, some remain

protected from user manipulation. The second area of

Data Memory is reserved for general purpose use. All

locations within this area are read and write accessible

under program control.

Special Purpose Data Memory

This area of Data Memory is where registers, necessary

for the correct operation of the microcontroller, are

stored. Most of the registers are both readable and

writable but some are protected and are readable only,

the details of which are located under the relevant Spe-

cial Function Register section. Note that for locations

that are unused, any read instruction to these addresses

will return the value ²00H².

0

1

2

3

4

5

6

7

8

9

H

I

A

R

0

1

M

P

0

1

Structure

A

C

The two sections of Data Memory, the Special Purpose

and General Purpose Data Memory are located at con-

secutive locations. All are implemented in RAM and are

8 bits wide but the length of each memory section is dic-

tated by the type of microcontroller chosen. The start

address of the Data Memory for all devices is the ad-

dress ²00H². Registers which are common to all

microcontrollers, such as ACC, PCL, etc., have the

same Data Memory address.

P

C

L

T

B

L

P

T

B

L

H

W

D

T

S

0

A

B

H

S

T

A

T

U

S

I

N

T

C

0

C

D

T

M

R

0

H

T

M

R

0

L

0

E

T

M

R

0

1

C

H

0

F

1

0

1

2

3

4

5

6

7

8

9

H

T

M

R

1

L

T

M

R

1

C

P

A

B

0

H

P

A

B

C

S

p

e

c

i

a

l

P

u

r

p

o

s

e

P

C

D

a

t

a

P

C

D

C

M

e

m

o

r

y

2

5

8

H

1

A

B

H

P

E

P

E

C

G

e

n

e

r

a

l

1

C

D

P

F

P

u

r

p

o

s

e

P

F

C

D

a

t

a

1

E

I

N

T

C

1

M

e

m

o

r

y

1

F

T

B

H

P

2

0

1

2

3

4

5

6

7

H

S

B

C

D

R

F

H

S

Data Memory Structure

W

S

R

C

T

L

R

Note: Most of the Data Memory bits can be directly

manipulated using the ²SET [m].i² and ²CLR

[m].i² with the exception of a few dedicated bits.

The Data Memory can also be accessed

through the memory pointer register MP.

:

U

n

R

u

e

s

a

e

d

a

s

"

0

"

General Purpose Data Memory

All microcontroller programs require an area of

read/write memory where temporary data can be stored

and retrieved for use later. It is this area of RAM memory

that is known as General Purpose Data Memory. This

area of Data Memory is fully accessible by the user pro-

gram for both read and write operations. By using the

²SET [m].i² and ²CLR [m].i² instructions individual bits

can be set or reset under program control giving the

user a large range of flexibility for bit manipulation in the

Data Memory.

Rev. 1.20

11

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Special Function Registers

To ensure successful operation of the microcontroller,

certain internal registers are implemented in the Data

Memory area. These registers ensure correct operation

of internal functions such as timers, interrupts, etc., as

well as external functions such as I/O data control. The

location of these registers within the Data Memory be-

gins at the address ²00H². Any unused Data Memory lo-

cations between these special function registers and the

point where the General Purpose Memory begins is re-

served and attempting to read data from these locations

will return a value of ²00H².

rather to the memory location specified by their corre-

sponding Memory Pointer, MP0 or MP1. As the Indirect

Addressing Registers are not physically implemented,

reading the Indirect Addressing Registers indirectly will

return a result of ²00H² and writing to the registers indi-

rectly will result in no operation.

Memory Pointer - MP0, MP1

For all devices, two Memory Pointers, known as MP0

and MP1 are provided. These Memory Pointers are

physically implemented in the Data Memory and can be

manipulated in the same way as normal registers pro-

viding a convenient way with which to address and track

data. When any operation to the relevant Indirect Ad-

dressing Registers is carried out, the actual address that

the microcontroller is directed to, is the address speci-

fied by the related Memory Pointer.

Indirect Addressing Register - IAR0, IAR1

The Indirect Addressing Registers, IAR0 and IAR1, al-

though having their locations in normal RAM register

space, do not actually physically exist as normal regis-

ters. The method of indirect addressing for RAM data

manipulation uses these Indirect Addressing Registers

and Memory Pointers, in contrast to direct memory ad-

dressing, where the actual memory address is speci-

fied. Actions on the IAR0 and IAR1 registers will result in

no actual read or write operation to these registers but

data .section ¢data¢

adres1

adres2

adres3

adres4

block

db ?

code .section at 0 ¢code¢

org 00h

start:

mov a,04h

mov block,a

mov a,offset adres1; Accumulator loaded with first RAM address

; setup size of block

mov mp0,a

; setup memory pointer with first RAM address

loop:

clr IAR0

inc mp0

sdz block

jmp loop

; clear the data at address defined by MP0

; increment memory pointer

; check if last memory location has been cleared

continue:

The important point to note here is that in the example shown above, no reference is made to specific Data Memory ad-

dresses.

Rev. 1.20

12

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Accumulator - ACC

Status Register - STATUS

The Accumulator is central to the operation of any

microcontroller and is closely related with operations

carried out by the ALU. The Accumulator is the place

where all intermediate results from the ALU are stored.

Without the Accumulator it would be necessary to write

the result of each calculation or logical operation such

as addition, subtraction, shift, etc., to the Data Memory

resulting in higher programming and timing overheads.

Data transfer operations usually involve the temporary

storage function of the Accumulator; for example, when

transferring data between one user defined register and

another, it is necessary to do this by passing the data

through the Accumulator as no direct transfer between

two registers is permitted.

This 8-bit register contains the zero flag (Z), carry flag

(C), auxiliary carry flag (AC), overflow flag (OV), power

down flag (PDF), and watchdog time-out flag (TO).

These arithmetic/logical operation and system manage-

ment flags are used to record the status and operation of

the microcontroller.

With the exception of the TO and PDF flags, bits in the

status register can be altered by instructions like most

other registers. Any data written into the status register

will not change the TO or PDF flag. In addition, opera-

tions related to the status register may give different re-

sults due to the different instruction operations. The TO

flag can be affected only by a system power-up, a WDT

time-out or by executing the ²CLR WDT² or ²HALT² in-

struction. The PDF flag is affected only by executing the

²HALT² or ²CLR WDT² instruction or during a system

power-up.

Program Counter Low Register - PCL

To provide additional program control functions, the low

byte of the Program Counter is made accessible to pro-

grammers by locating it within the Special Purpose area

of the Data Memory. By manipulating this register, direct

jumps to other program locations are easily imple-

mented. Loading a value directly into this PCL register

will cause a jump to the specified Program Memory lo-

cation, however, as the register is only 8-bit wide, only

jumps within the current Program Memory page are per-

mitted. When such operations are used, note that a

dummy cycle will be inserted.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

·

C is set if an operation results in a carry during an ad-

dition operation or if a borrow does not take place dur-

ing a subtraction operation; otherwise C is cleared. C

is also affected by a rotate through carry instruction.

AC is set if an operation results in a carry out of the

low nibbles in addition, or no borrow from the high nib-

ble into the low nibble in subtraction; otherwise AC is

cleared.

Look-up Table Registers - TBLP, TBLH, TBHP

·

Z is set if the result of an arithmetic or logical operation

These three special function registers are used to con-

trol operation of the look-up table which is stored in the

Program Memory. TBLP is the table pointer and indi-

cates the location where the table data is located. Its

value must be setup before any table read commands

are executed. Its value can be changed, for example us-

ing the ²INC² or ²DEC² instructions, allowing for easy ta-

ble data pointing and reading. TBLH is the location

where the high order byte of the table data is stored after

a table read data instruction has been executed. Note

that the lower order table data byte is transferred to a

user defined location. Once configuration option TBHP

is enabled, the instruction ²TABRDC [m]² reads the

ROM data as defined by TBLP and TBHP value.

is zero; otherwise Z is cleared.

OV is set if an operation results in a carry into the high-

est-order bit but not a carry out of the highest-order bit,

or vice versa; otherwise OV is cleared.

·

PDF is cleared by a system power-up or executing the

²CLR WDT² instruction. PDF is set by executing the

²HALT² instruction.

TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is set by a

WDT time-out.

b

7

b

0

T

O

P

D

F

O

V

Z

A

C

T

S

A

T

A

U

S

R

e

g

i

s

t

e

r

i

t

h

m

e

t

i

c

/

L

o

g

i

c

O

p

e

C

A

Z

O

a

r

y

f

l

a

g

u

x

i

l

i

a

r

y

c

a

r

y

f

l

a

g

e

r

o

f

l

a

g

v

e

r

f

l

o

w

f

l

a

g

S

y

s

t

e

m

M

a

n

a

g

e

m

e

n

t

F

P

W

N

o

w

e

r

d

o

w

n

f

l

a

g

a

t

c

h

d

o

g

t

i

e

m

e

-

o

u

t

f

l

o

t

i

m

p

l

e

m

n

t

e

d

,

r

e

a

Status Register

Rev. 1.20

13

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

In addition, on entering an interrupt sequence or execut-

ing a subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status registers are important and if the interrupt rou-

tine can change the status register, precautions must be

taken to correctly save it.

manipulating specific bits of the I/O control registers dur-

ing normal program operation is a useful feature of

these devices.

Input/Output Ports

Holtek microcontrollers offer considerable flexibility on

their I/O ports. With the input or output designation of ev-

ery pin fully under user program control, pull-high op-

tions for all ports and wake-up options on certain pins,

the user is provided with an I/O structure to meet the

needs of a wide range of application possibilities.

Interrupt Control Registers - INTC0, INTC1

The microcontrollers provide one external interrupts, two

internal timer/event counter overflow interrupt and one

SPI interrupt. By setting various bits within this register

using standard bit manipulation instructions, the en-

able/disable function of each interrupt can be independ-

ently controlled. A master interrupt bit within this register,

the EMI bit, acts like a global enable/disable and is used

to set all of the interrupt enable bits on or off. This bit is

cleared when an interrupt routine is entered to disable

further interrupt and is set by executing the ²RETI² in-

struction.

Depending upon which package is chosen, the

microcontroller provides up to 43 bidirectional input/out-

put lines labeled with port names PA, PB, PC, PD, PE

and PF0~PF2.

This register is mapped to the Data Memory with an ad-

dresses as shown in the Special Purpose Data Memory

table. Seven of these I/O lines can be used for input and

output operations and one line as an input only. For in-

put operation, these ports are non-latching, which

means the inputs must be ready at the T2 rising edge of

instruction ²MOV A,[m]², where m denotes the port ad-

dress. For output operation, all the data is latched and

remains unchanged until the output latch is rewritten.

Timer/Event Counter Registers -

TMR0H/TMR1H, TMR0L/TMR1L,TMR0C/TMR1C

All devices possess two internal 16-bit count-up timer. An

associated register pair known as TMR0L(TMR1L)/

TMR0H(TMR1H) is the location where the timer 16-bit

value is located. This register can also be preloaded with

fixed data to allow different time intervals to be setup. An

associated control register, known as TMR0C(TMR1C),

contains the setup information for this timer, which deter-

mines in what mode the timer is to be used as well as

containing the timer on/off control function.

Pull-high Resistors

Many product applications require pull-high resistors for

their switch inputs usually requiring the use of an exter-

nal resistor. To eliminate the need for these external re-

sistors, I/O pins, when configured as an input have the

capability of being connected to an internal pull-high re-

sistor. The pull-high resistors are selectable via configu-

ration options and are implemented using weak PMOS

transistors. Each pin on all of I/O can be selected indi-

vidually to have this pull-high resistors feature and each

nibble on each of the other ports.

Input/Output Ports and Control Registers

Within the area of Special Function Registers, the I/O

registers and and their associated control registers play

a prominent role. All I/O ports have a designated regis-

ter correspondingly labeled as PA, PB, PC, PD, PE and

PF0~PF2. These labeled I/O registers are mapped to

specific addresses within the Data Memory as shown in

the Data Memory table, which are used to transfer the

appropriate output or input data on that port. With each

I/O port there is an associated control register labeled

PAC, PBC, PCC, PDC, PEC and PFC.0~PFC.2, also

mapped to specific addresses with the Data Memory.

The control register specifies which pins of that port are

set as inputs and which are set as outputs. To setup a

pin as an input, the corresponding bit of the control reg-

ister must be set high, for an output it must be set low.

During program initialisation, it is important to first setup

the control registers to specify which pins are outputs

and which are inputs before reading data from or writing

data to the I/O ports. One flexible feature of these regis-

ters is the ability to directly program single bits using the

²SET [m].i² and ²CLR [m].i² instructions. The ability to

change I/O pins from output to input and vice versa by

Port Pin Wake-up

If the HALT instruction is executed, the device will enter

the Power Down Mode, where the system clock will stop

resulting in power being conserved, a feature that is im-

portant for battery and other low-power applications.

Various methods exist to wake-up the microcontroller,

one of which is to change the logic condition on one of

the Port pins from high to low or low to high. After a

HALT instruction forces the microcontroller into entering

the Power Down Mode, the processor will remain idle or

in a low-power state until the logic condition of the se-

lected wake-up pin on Port pins changes from high to

low or low to high. This function is especially suitable for

applications that can be woken up via external switches.

Note that each pin on PA, PB, PC, PD, PE and PF0~PF2

can be selected individually to have this wake-up fea-

ture.

Rev. 1.20

14

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

V

D

P

u

l

-

H

i

g

h

C

o

n

t

r

o

l

B

i

t

n

O

p

t

i

o

W

e

a

k

D

a

t

a

B

u

s

D

Q

P

u

l

-

u

p

W

r

i

t

e

C

o

n

t

r

e

o

l

K

Q

R

e

g

i

s

t

e

r

C

S

C

h

i

p

R

s

e

t

I

/

O

p

i

n

R

e

a

d

C

o

n

t

r

o

l

R

e

g

i

s

t

e

r

D

a

t

a

B

i

t

D

C

Q

W

r

i

t

e

D

a

t

a

R

K

Q

e

g

i

s

t

e

r

S

M

U

X

R

e

a

d

D

a

t

a

R

e

g

i

s

t

e

r

S

y

s

t

e

m

W

a

k

e

-

u

p

W

a

k

e

-

u

p

S

e

l

e

c

t

Generic Input/Output Structure

·

I/O Port Control Registers

External Timer 0 Clock Input

The external timer pin TMR0 is pin-shared with the I/O

pin PA2. To configure this pin to operate as timer input,

the corresponding control bits in the timer control reg-

ister must be correctly set. For applications that do not

require an external timer input, this pin can be used as

a normal I/O pin. Note that if used as a normal I/O pin

the timer mode control bits in the timer control register

must select the timer mode, which has an internal

clock source, to prevent the input pin from interfering

with the timer operation.

Each I/O port has its own control register PAC, PBC,

PCC, PDC, PEC and PFC.0~PFC.2, to control the in-

put/output configuration. With this control register, each

CMOS output or input with or without pull-high resistor

structures can be reconfigured dynamically under soft-

ware control. Each of the I/O ports is directly mapped to a

bit in its associated port control register. Note that several

pins can be setup to have NMOS outputs using configu-

ration options.

·

External Timer1 Clock Input

For the I/O pin to function as an input, the corresponding

bit of the control register must be written as a ²1². This

will then allow the logic state of the input pin to be di-

rectly read by instructions. When the corresponding bit

of the control register is written as a ²0², the I/O pin will

be setup as an output. If the pin is currently setup as an

output, instructions can still be used to read the output

register. However, it should be noted that the program

will in fact only read the status of the output data latch

and not the actual logic status of the output pin.

The external timer pin TMR1 is pin-shared with the I/O

pin PA3. To configure this pin to operate as timer input,

the corresponding control bits in the timer control reg-

ister must be correctly set. For applications that do not

require an external timer input, this pin can be used as

a normal I/O pin. Note that if used as a normal I/O pin

the timer mode control bits in the timer control register

must select the timer mode, which has an internal

clock source, to prevent the input pin from interfering

with the timer operation.

·

V1/V2 is for V-axis function

Pin-shared Functions

The V1/V2 pins are pin shared with the PB0/PB1 pins,

PB0, PB1 has falling and rising edge wake-up func-

tion, if it select can wake-up by configuration option. In

HALT Mode if PB0 wake-up the V1-Wakeup [23H.4]

will be set, if PB1 wake-up the V2-Wakeup [23H.5] will

be set. If user read WSR register by software, the bit

will be clear.

The flexibility of the microcontroller range is greatly en-

hanced by the use of pins that have more than one func-

tion. Limited numbers of pins can force serious design

constraints on designers but by supplying pins with

multi-functions, many of these difficulties can be over-

come. For some pins, the chosen function of the

multi-function I/O pins is set by configuration options

while for others the function is set by application pro-

gram control.

·

Z1/Z2 is for Z-axis function

The Z1/Z2 pins are pin shared with the PA0/PA1 pins,

PA0, PA1 has falling and rising edge wake-up func-

tion, if it select can wake-up by configuration option. In

halt mode if PA0 wake-up the Z1-Wakeup [23H.6] will

be set, if PA1 wake-up the Z2-Wakeup [23H.7] will be

set. If user WSR register by software, the bit will be

clear.

·

External Interrupt Input

The external interrupt pin INT is pin-shared with the

I/O pin PC2. For applications not requiring an external

interrupt input, the pin-shared external interrupt pin

can be used as a normal I/O pin, however to do this,

the external interrupt enable bits in the INTC0 register

must be disabled.

Rev. 1.20

15

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Output Pin Slew Rate Control

to operate as a general timer, an external event counter

or as a pulse width measurement device.

The output pin slew rate can be setup using a configura-

tion option and can be set to be either 0ns, 50ns, 100ns

or 200ns.

There are two types of registers related to the

Timer/Event Counters. The first is the register that con-

tain the actual value of the Timer/Event Counter and into

which an initial value can be preloaded, and is known as

TMR0H/TMR0L, TMR1H/TMR1L. Reading from this

register retrieves the contents of the Timer/Event Coun-

ter. The second type of associated register is the Timer

Control Register, which defines the timer options and

determines how the Timer/Event Counter is to be used,

and has the name TMR0C or TMR1C. This device can

have the timer clocks configured to come from the inter-

nal clock sources. In addition, the timer clock sources

can also be configured to come from the external timer

pins.

I/O Pin Structures

The accompanying diagrams illustrate the internal

structures of some I/O pin types. As the exact logical

construction of the I/O pin will differ from these draw-

ings, they are supplied as a guide only to assist with the

functional understanding of the I/O pins. The wide range

of pin-shared structures does not permit all types to be

shown.

Programming Considerations

Within the user program, one of the first things to con-

sider is port initialisation. After a reset, all of the data and

port control register will be set high. This means that all

I/O pins will default to an input state, the level of which

depends on the other connected circuitry and whether

pull-high options have been selected. If the PAC, PBC,

PCC, PDC, PEC and PFC.0~PFC.2 port control regis-

ter, are then programmed to setup some pins as out-

puts, these output pins will have an initial high output

value unless the associated PA, PB, PC, PD, PE and

PF0~PF2 port data registers are first programmed. Se-

lecting which pins are inputs and which are outputs can

be achieved byte-wide by loading the correct value into

the port control register or by programming individual

bits in the port control register using the ²SET [m].i² and

²CLR [m].i² instructions. Note that when using these bit

control instructions, a read-modify-write operation takes

place. The microcontroller must first read in the data on

the entire port, modify it to the required new bit values

and then rewrite this data back to the output ports.

The external clock source is used when the Timer/Event

Counter is in the event counting mode, the clock source

being provided on the external timer pin. The external

timer pin has the name TMR0 or TMR1. Depending

upon the condition of the T0E or T1E bit in the Timer

Control Register, each high to low, or low to high transi-

tion on the external timer input pin will increment the

Timer/Event Counter by one.

Configuring the Timer/Event Counter Input Clock

Source

The Timer/Event Counter¢s clock can originate from vari-

ous sources. The instruction clock source or WDTOSC

(system clock source divided by 4) is used when the

Timer/Event Counter 0 or Timer/Event Counter 1 is in the

timer mode or in the pulse width measurement mode.

The external clock source is used when the Timer/Event

Counter is in the event counting mode, the clock source

being provided on the external timer pin, TMR0 or TMR1.

Depending upon the condition of the T0E or T1E bit, each

high to low, or low to high transition on the external timer

pin will increment the counter by one.

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

S

y

s

t

e

m

C

l

o

c

k

P

o

r

t

D

a

t

a

Timer Registers - TMR0H/TMR0L, TMR1H/TMR1L

W

r

i

t

e

t

o

P

R

o

e

r

a

t

d

f

r

o

m

The timer registers are special function registers located

in the Special Purpose RAM Data Memory and are the

places where the actual timer values are stored. The

timer registers are known as TMR0L/ TMR0H, TMR1L

/TMR1H. The value in the timer registers increases by

one each time an internal clock pulse is received or an

external transition occurs on the external timer pin. The

timer will count from the initial value loaded by the

preload register to the full count of FFFFH for the 16-bit

timer at which point the timer overflows and an internal

interrupt signal is generated. The timer value will then

be reset with the initial preload register value and con-

tinue counting.

Read/Write Timing

All I/O pins has the additional capability of providing

wake-up functions. When the device is in the Power

Down Mode, various methods are available to wake the

device up. One of these is a high to low or low to high

transition of any of all I/O pins. Single or multiple pins on

all I/O pins can be setup to have this function.

Timer/Event Counters

The provision of timers form an important part of any

microcontroller, giving the designer a means of carrying

out time related functions. This device contains two

count-up timers of 16-bit capacities. As each timer has

three different operating modes, they can be configured

To achieve a maximum full range count of FFFFH, the

preload registers must first be cleared to all zeros. It

should be noted that after power-on, the preload register

Rev. 1.20

16

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

D

a

t

a

B

u

s

L

o

w

B

y

t

e

B

u

f

e

r

1

6

-

b

i

t

T

i

m

e

r

R

/

e

E

l

v

o

e

a

n

d

t

C

o

T

0

M

0

T

0

M

1

P

r

e

l

o

a

d

R

e

g

i

s

t

e

r

f

S

Y

S

T

i

m

e

r

/

E

v

e

n

t

C

o

u

n

t

e

r

T

M

R

0

M

o

d

e

C

o

n

t

r

o

l

H i

g

h

B

y

t

e

v

e

r

f

l

o

w

L

o

w

B

y

t

e

O

t

o

I

n

t

e

r

T

0

O

N

1 6

T

0

E

-

B

i

t

T

i

m

e

r

/

E

v

e

n

t

C

o

16-bit Timer/Event Counter 0 Structure

D

a

t

a

B

u

s

L

o

w

B

y

t

e

B

u

f

e

r

M

C

W

D

T

O

S

U

f

S

Y

S

X

1

6

-

b

i

t

T

i

m

e

r

R

/

e

E

l

v

o

e

a

n

d

t

C

o

T 1

1

M

0

P

r

e

l

o

a

d

R

e

g

i

s

t

e

r

T

1

M

T

M

R

1

S

O

p

t

i

o

n

T

i

m

e

r

/

E

v

e

n

t

C

o

u

n

t

e

r

T

M

R

1

M

o

d

e

C

o

n

t

r

o

l

H i

g

h

B

y

t

e

v

e

r

f

l

o

w

L

o

w

B

y

t

e

O

t

o

I

n

t

e

r

T

1

O

N

1 6

T

1

E

-

B

i

t

T

i

m

e

r

/

E

v

e

n

t

C

o

16-bit Timer/Event Counter 1 Structure

will be in an unknown condition. Note that if the

Timer/Event Counter is switched off and data is written

to its preload registers, this data will be immediately writ-

ten into the actual timer registers. However, if the

Timer/Event Counter is enabled and counting, any new

data written into the preload data registers during this

period will remain in the preload registers and will only

be written into the timer registers the next time an over-

flow occurs.

associated low byte buffer. After this has been done, the

low byte timer register can be read in the normal way.

Note that reading the low byte timer register will result in

reading the previously latched contents of the low byte

buffer and not the actual contents of the low byte timer

register.

Timer Control Register - TMR0C, TMR1C

The flexible features of the Holtek microcontroller

Timer/Event Counters enable them to operate in three

different modes, the options of which are determined by

the contents of their control register, which has the

name TMR0C or TMR1C. It is the Timer Control Regis-

ter together with its corresponding timer register that

control the full operation of the Timer/Event Counter.

Before the Timer/Event Counter can be used, it is es-

sential that the Timer Control Register is fully pro-

grammed with the right data to ensure its correct

operation, a process that is normally carried out during

program initialisation.

For the 16-bit Timer/Event Counter which has both low

byte and high byte timer registers, accessing these reg-

isters is carried out in a specific way. It must be note

when using instructions to preload data into the low byte

timer register, namely TMR0L/TMR1L, the data will only

be placed in a low byte buffer and not directly into the

low byte timer register. The actual transfer of the data

into the low byte timer register is only carried out when a

write to its associated high byte timer register, namely

TMR0H/TMR1H, is executed. On the other hand, using

instructions to preload data into the high byte timer reg-

ister will result in the data being directly written to the

high byte timer register. At the same time the data in the

low byte buffer will be transferred into its associated low

byte timer register. For this reason, the low byte timer

register should be written first when preloading data into

the 16-bit timer registers. It must also be noted that to

read the contents of the low byte timer register, a read to

the high byte timer register must be executed first to

latch the contents of the low byte timer register into its

To choose which of the three modes the Timer/Event

Counter is to operate in, either in the timer mode, the

event counting mode or the pulse width measurement

mode, bits 7 and 6 of the Timer Control Register, which

are known as the bit pair T0M1/T0M0 or T1M1/T1M0,

must be set to the required logic levels. The Timer/Event

Counter on/off bit, which is bit 4 of the Timer Control

Register and known as T0ON or T1ON, provides the ba-

sic on/off control of the Timer/Event Counter. Setting the

Rev. 1.20

17

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

b

7

b

0

T

0

M

0

1

T

0

O

E

N

T

M

R

0

C

R

e

g

i

s

t

e

r

N

o

t

i

m

p

l

e

m

e

n

t

e

d

,

r

e

a

d

E

1

0

v

e

n

t

C

o

u

n

t

e

r

A

c

t

i

v

e

E

:

c

o

u

n

t

o

n

f

a

l

i

n

g

e

d

u

n

t

o

r

i

s

i

n

g

e

d

g

P

1

0

u

l

s

e

W

i

d

t

h

M

e

a

s

u

r

e

m

e

:

s

t

a

r

t

c

o

u

n

t

i

n

g

o

n

r

i

r

t

c

o

u

n

o

n

f

a

T

1

0

i

m

e

r

/

E

v

e

n

t

C

o

u

n

t

e

r

C

:

e

d

n

a

b

l

e

i

s

a

b

l

e

N

o

t

i

m

p

l

e

m

e

n

t

e

d

,

r

e

a

d

O

p

e

r

a

t

i

n

g

M

o

d

e

S

e

l

e

c

t

T

0

M

1

T

0

M

0

n

e

t

p

o

v

d

m

e

o

a

v

a

i

l

a

b

l

e

0

1

0

1

0

1

e

n

t

c

o

u

n

t

e

r

m

i

m

e

r

m

o

d

e

u

l

s

e

w

i

d

t

h

m

e

Timer/Event Counter 0 Control Register

b

7

b

0

T

1

M

0

1

T

1

O

E

N

T

M

R

1

C

R

e

g

i

s

t

e

r

N

o

t

i

m

p

l

e

m

e

n

t

e

d

,

r

e

a

d

E

1

0

v

e

n

t

C

o

u

n

t

e

r

A

c

t

i

v

e

E

:

c

o

u

n

t

o

n

f

a

l

i

n

g

e

d

g

u

n

t

n

r

i

s

i

n

g

e

d

g

e

P

1

0

u

l

s

e

W

i

d

t

h

M

d

e

g

a

e

s

S

u

r

e

l

e

m

c

e

t

n

:

s

t

a

r

t

c

o

u

n

t

i

n

g

o

n

r

i

r

t

c

o

u

n

o

n

f

a

T

1

0

i

m

e

r

/

E

v

e

n

t

C

o

u

n

t

e

r

C

o

:

e

d

n

a

b

l

e

i

s

a

b

l

e

N

o

t

i

m

p

l

e

m

e

n

t

e

d

,

r

e

a

d

O

p

e

r

a

t

i

n

g

M

o

d

e

S

e

l

e

c

t

T

1

M

1

T

1

M

0

n

o

v

d

m

e

o

a

v

a

i

l

a

b

l

e

0

1

0

1

0

1

e

t

p

e

n

t

c

o

u

n

t

e

r

m

i

m

e

r

m

o

d

e

u

l

s

e

w

i

d

t

h

m

e

a

Timer/Event Counter 1 Control Register

Rev. 1.20

18

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

bit high allows the Timer/Event Counter to run, clearing

the bit stops it running. If the Timer/Event Counter is in

the event count or pulse width measurement mode, the

active transition edge level type is selected by the logic

level of bit 3 of the Timer Control Register which is

known as T0E or T1E.

In this mode, the external timer pin, TMR0 or TMR1, is

used as the Timer/Event Counter clock source, however

it is not divided by the internal prescaler. After the other

bits in the Timer Control Register have been setup, the

enable bit T0ON or T1ON, which is bit 4 of the Timer

Control Register, can be set high to enable the

Timer/Event Counter to run. If the Active Edge Select bit

T0E or T1E, which is bit 3 of the Timer Control Register,

is low, the Timer/Event Counter will increment each time

the external timer pin receives a low to high transition. If

the Active Edge Select bit is high, the counter will incre-

ment each time the external timer pin receives a high to

low transition. When it is full and overflows, an interrupt

signal is generated and the Timer/Event Counter will re-

load the value already loaded into the preload register

and continue counting. The interrupt can be disabled by

ensuring that the Timer/Event Counter Interrupt Enable

bit in the Interrupt Control Register, INTC0, is reset to

zero.

Configuring the Timer Mode

In this mode, the Timer/Event Counter can be utilised to

measure fixed time intervals, providing an internal inter-

rupt signal each time the Timer/Event Counter over-

flows. To operate in this mode, the Operating Mode

Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer

Control Register must be set to the correct value as

shown.

Bit7 Bit6

Control Register Operating Mode

Select Bits for the Timer Mode

1

0

In this mode the internal clock is used as the internal

clock for the Timer/Event Counter. After the other bits in

the Timer Control Register have been setup, the enable

bit T0ON or T1ON, which is bit 4 of the Timer Control

Register, can be set high to enable the Timer/Event

Counter to run. Each time an internal clock cycle occurs,

the Timer/Event Counter increments by one. When it is

full and overflows, an interrupt signal is generated and

the Timer/Event Counter will reload the value already

loaded into the register and continue counting. The in-

terrupt can be disabled by ensuring that the Timer/Event

Counter Interrupt Enable bit in the Interrupt Control Reg-

ister, INTC0, is reset to zero.

As the external timer pin is an independent pin and not

shared with an I/O pin, the only thing to ensure the timer

operate as an event counter is to ensure that the Oper-

ating Mode Select bits in the Timer Control Register

place the Timer/Event Counter in the Event Counting

Mode. It should be noted that in the event counting

mode, even if the microcontroller is in the Power Down

Mode, the Timer/Event Counter will continue to record

externally changing logic events on the timer input pin.

As a result when the timer overflows it will generate a

timer interrupt and corresponding wake-up source.

Configuring the Pulse Width Measurement Mode

Configuring the Event Counter Mode

In this mode, the Timer/Event Counter can be utilised to

measure the width of external pulses applied to the ex-

ternal timer pin. To operate in this mode, the Operating

Mode Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the

Timer Control Register must be set to the correct value

as shown.

In this mode, a number of externally changing logic

events, occurring on the external timer pin, can be re-

corded by the Timer/Event Counter. To operate in this

mode, the Operating Mode Select bit pair, T0M1/T0M0

or T1M1/T1M0, in the Timer Control Register must be

set to the correct value as shown.

Control Register Operating Mode

Select Bits for the Pulse Width Measure-

ment Mode

Bit7 Bit6

Control Register Operating Mode

Select Bits for the Event Counter Mode

1

0

1

P

r

e

s

c

a

l

e

r

O

u

t

p

u

t

I

n

c

r

e

m

e

n

t

T

i

m

e

r

+

2

T

i

m

e

r

+

T

N

i

m

e

r

T

i

m

e r

r

+

1

T

i

m

e

r

C

o

n

t

r

o

l

e

Timer Mode Timing Chart

E

x

t

e

r

n

a

l

T

i

m

e

r

P

i

n

I

n

p

u

t

T

0

E

o

r

T

1

E

=

1

I

n

c

r

e

m

e

n

t

T

i

m

e

r

+

1

T

i

m

e

r

+

2

T

i

m

e

r

+

T

i

m

e

r

C

o

u

n

t

e

r

Event Counter Mode Timing Chart

Rev. 1.20

19

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

I/O Interfacing

In this mode the internal clock, f_SYS/4 is used as the in-

ternal clock for the 16-bit Timer/Event Counters. After

the other bits in the Timer Control Register have been

setup, the enable bit T0ON or T1ON, which is bit 4 of the

Timer Control Register, can be set high to enable the

Timer/Event Counter, however it will not actually start

counting until an active edge is received on the external

timer pin.

The Timer/Event Counter, when configured to run in the

event counter or pulse width measurement mode, re-

quires the use of an external pin for correct operation.

This is implemented by ensuring that the mode select bits

in the Timer/Event Counter control register, select either

the event counter or pulse width measurement mode.

Programming Considerations

If the Active Edge Select bit T0E or T1E, which is bit 3 of

the Timer Control Register, is low, once a high to low

transition has been received on the external timer pin,

TMR0 or TMR1, the Timer/Event Counter will start

counting until the external timer pin returns to its original

high level. At this point the enable bit will be automati-

cally reset to zero and the Timer/Event Counter will stop

counting. If the Active Edge Select bit is high, the

Timer/Event Counter will begin counting once a low to

high transition has been received on the external timer

pin and stop counting when the external timer pin re-

turns to its original low level. As before, the enable bit

will be automatically reset to zero and the Timer/Event

Counter will stop counting. It is important to note that in

the Pulse Width Measurement Mode, the enable bit is

automatically reset to zero when the external control

signal on the external timer pin returns to its original

level, whereas in the other two modes the enable bit can

only be reset to zero under program control.

When configured to run in the timer mode, an internal

timer clock source is used. In this mode, when the ap-

propriate timer register is full, the microcontroller will

generate an internal interrupt signal directing the pro-

gram flow to the respective internal interrupt vector. For

the pulse width measurement mode, the instruction

clock is also used as the timer clock source but the timer

will only run when the correct logic condition appears on

the external timer input pin. As this is an external event

and not synchronised with the internal timer clock, the

microcontroller will only see this external event when the

next timer clock pulse arrives. As a result there may be

small differences in measured values requiring pro-

grammers to take this into account during programming.

The same applies if the timer is configured to be in the

event counting mode which again is an external event

and not synchronised with the internal system or timer

clock.

The residual value in the Timer/Event Counter, which

can now be read by the program, therefore represents

the length of the pulse received on the external timer

pin. As the enable bit has now been reset, any further

transitions on the external timer pin will be ignored. Not

until the enable bit is again set high by the program can

the timer begin further pulse width measurements. In

this way, single shot pulse measurements can be easily

made.

When the Timer/Event Counter is read or if data is written

to the preload registers, the clock is inhibited to avoid er-

rors, however as this may result in a counting error, this

should be taken into account by the programmer. Care

must be taken to ensure that the timers are properly in-

itialised before using them for the first time. The associ-

ated timer interrupt enable bits in the interrupt control

register must be properly set otherwise the internal inter-

rupt associated with the timer will remain inactive. The

edge select, timer mode and clock source control bits in

timer control register must also be correctly set to ensure

the timer is properly configured for the required applica-

tion. It is also important to ensure that an initial value is

first loaded into the timer register before the timer is

switched on; this is because after power-on the initial

value of the timer register is unknown. After the timer has

been initialised the timer can be turned on and off by con-

trolling the enable bit in the timer control register. Note

It should be noted that in this mode the Timer/Event

Counter is controlled by logical transitions on the external

timer pin and not by the logic level. When the Timer/Event

Counter is full and overflows, an interrupt signal is gener-

ated and the Timer/Event Counter will reload the value al-

ready loaded into the preload register and continue

counting. The interrupt can be disabled by ensuring that

the Timer/Event Counter Interrupt Enable bit in the Inter-

rupt Control Register, INTC0, is reset to zero.

E

x

t

e

r

n

a

l

T

i

m

e

r

P

i

n

I

n

p

u

t

T

0

O

N

o

r

T

1

O

N

(

w

i

t

h

T

0

E

o

r

T

1

E

=

0

)

P

r

e

s

c

a

l

e

r

O

u

t

p

u

t

I

n

c

r

e

m

e

n

t

+

1

+

2

+

3

+

4

T

i

m

e

r

T

i

m

e

n

r

t

e

C

r

o

u

P

r

e

s

c

a

l

e

r

O

u

t

p

u

t

i

s

a

m

p

l

e

d

a

t

e

v

e

r

y

Pulse Width Measure Mode Timing Chart

Rev. 1.20

20

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

that setting the timer enable bit high to turn the timer on,

should only be executed after the timer mode bits have

been properly setup. Setting the timer enable bit high to-

gether with a mode bit modification, may lead to improper

timer operation if executed as a single timer control regis-

ter byte write instruction.

woken up from its Power-down condition. To prevent

such a wake-up from occurring, the timer interrupt re-

quest flag should first be set high before issuing the

HALT instruction to enter the Power Down Mode.

Timer Program Example

This program example shows how the Timer/Event

Counter registers are setup, along with how the inter-

rupts are enabled and managed. Note how the

Timer/Event Counter is turned on, by setting bit 4 of the

Timer Control Register. The Timer/Event Counter can

be turned off in a similar way by clearing the same bit.

This example program sets the Timer/Event Counter

tobe in the timer mode, which uses the internal system

clock as the clock source.

When the Timer/Event counter overflows, its corre-

sponding interrupt request flag in the interrupt control

register will be set. If the timer interrupt is enabled this

will in turn generate an interrupt signal. However irre-

spective of whether the timer interrupt is enabled or not,

a Timer/Event counter overflow will also generate a

wake-up signal if the device is in a Power-down condi-

tion. This situation may occur if the Timer/Event Counter

is in the Event Counting Mode and if the external signal

continues to change state. In such a case, the

Timer/Event Counter will continue to count these exter-

nal events and if an overflow occurs the device will be

org 04h

reti

; external interrupt vector

org 08h

jmp tmr0int

org 0ch

jmp tmr1int

:

; Timer/Event Counter 0 interrupt vector

; jump here when Timer/Event Counter 0 overflows

; Timer/Event Counter 1 interrupt vector

; jump here when Timer/Event Counter 1 overflows

org 20h

:

;internal Timer/Event Counter 0 interrupt routine

; main program

tmr0int:

:

; Timer/Event Counter 0 main program placed here

:

reti

:

;internal Timer/Event Counter 1 interrupt routine

tmr1int:

:

; Timer/Event Counter 1 main program placed here

:

reti

:

begin:

;setup Timer/Event Counter 0 registers

mov a,0e8h

mov tmr0l,a

mov a,09bh

mov tmr0h,a

mov a,080h

mov tmr0c,a

; setup low byte preload value for Timer/Event Counter 0

; low byte must be setup before high byte

; setup high byte preload value for Timer/Event Counter 0

;

; setup Timer control register TMR0C

; Timer/Event Counter 0 has no prescaler and clock source is f_SYS/4

;setup Timer/Event Counter 1 registers

mov a,09bh

mov tmr1l,a

mov a,0e8h

mov tmr1h,a

mov a,080h

mov tmr1c,a

; setup low byte preload value for Timer/Event Counter 1

; low byte must be setup before high byte

; setup high byte preload value for Timer/Event Counter 1

;

; setup Timer control register TMR1C

; Timer/Event Counter 1 has no prescaler and clock source is f_SYS/4

; setup interrupt register

mov a,00dh

mov intc,a

:

; enable master interrupt and timer interrupts

set tmr0c.4

set tmr1c.4

; start Timer/Event Counter 0 - note mode bits must be previously setup

; start Timer/Event Counter 1 - note mode bits must be previously setup

Rev. 1.20

21

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Interrupts

Interrupts are an important part of any microcontroller

system. When an external interrupt pin transition or two

internal function such as a Timer/Event Counter over-

flow, a transmission or reception of SPI data occurs,

their corresponding interrupt will enforce a temporary

suspension of the main program allowing the

microcontroller to direct attention to their respective

needs. Each device contains one external interrupts

and several internal interrupts functions. The external

interrupt is controlled by the action of the external inter-

rupt pins, while the internal interrupts are controlled by

the Timer/Event Counter overflow and SPI data trans-

mission or reception.

The various interrupt enable bits, together with their as-

sociated request flags, are shown in the accompanying

diagram with their order of priority.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked, as the EMI bit will be cleared au-

tomatically. This will prevent any further interrupt nesting

from occurring. However, if other interrupt requests oc-

cur during this interval, although the interrupt will not be

immediately serviced, the request flag will still be re-

corded. If an interrupt requires immediate servicing

while the program is already in another interrupt service

routine, the EMI bit should be set after entering the rou-

tine, to allow interrupt nesting. If the stack is full, the in-

terrupt request will not be acknowledged, even if the

related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

Interrupt Register

Overall interrupt control, which means interrupt enabling

and request flag setting, is controlled by the two inter-

rupt control registers, which are located in the Data

Memory. By controlling the appropriate enable bits in

these registers each individual interrupt can be enabled

or disabled. Also when an interrupt occurs, the corre-

sponding request flag will be set by the microcontroller.

The global enable flag if cleared to zero will disable all

interrupts.

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests,

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Operation

Interrupt Source

Priority

Vector

Two Timer/Event Counter overflow, 16-bits of data

transmission or reception on either of the one SPI inter-

faces or an active edge on any of the one external inter-

rupt pins will all generate an interrupt request by setting

their corresponding request flag, if their appropriate in-

terrupt enable bit is set. When this happens, the Pro-

gram Counter, which stores the address of the next

instruction to be executed, will be transferred onto the

stack. The Program Counter will then be loaded with a

new address which will be the value of the correspond-

ing interrupt vector. The microcontroller will then fetch its

next instruction from this interrupt vector. The instruction

at this vector will usually be a JMP statement which will

jump to another section of program which is known as

the interrupt service routine. Here is located the code to

control the appropriate interrupt. The interrupt service

routine must be terminated with a RETI statement,

which retrieves the original Program Counter address

from the stack and allows the microcontroller to continue

with normal execution at the point where the interrupt

occurred.

External Interrupt INT

1

0004H

Timer/Event Counter 0

Overflow Interrupt

2

0008H

Timer/Event Counter 1

Overflow Interrupt

3

4

000CH

0010H

SPI Interrupt

In cases where both external and internal interrupts are

enabled and where an external and internal interrupt oc-

curs simultaneously, the external interrupt will always

have priority and will therefore be serviced first. Suitable

masking of the individual interrupts using the interrupt

registers can prevent simultaneous occurrences.

Rev. 1.20

22

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

A

u

t

o

m

a

t

i

c

a

l

y

C

A

l

e

u

a

t

r

o

e

m

d

a

t

b

i

y

c

a

I

l

S

l

y

R

D

i

s

a

b

l

e

d

b

y

M

a

n

u

a

l

y

S

e

t

o

r

C

l

e

a

p

n

r

t

e

b

d

e

b

E

y

n

a

S

b

o

l

f

e

t

d

w

a

M

r

a

e

n

u

a

l

y

P

r

i

o

r

i

t

y

E

x

e

t

e

r

n

a

l

I

n

t

e

r

u

E

I

E

M

I

H

i

g

h

R

q

u

e

s

t

F

l

a

g

E

I

F

T

i

m

e

r

/

E

v

e

n

t

C

o

u

n

t

e

r

0

E

T

S

0

1

I

n

t

e

r

u

p

t

R

e

q

u

e

s

t

F

l

a

g

T

0

F

I

n

t

e

r

u

p

t

P

o

l

i

n

g

T

i

m

e

r

/

E

v

e

n

t

C

o

u

n

t

e

r

1

I

n

t

e

r

u

p

t

R

e

q

u

e

s

t

F

l

a

g

T

1

F

S

P

I

n

t

e

r

u

p

t

I

L

o

w

R

e

q

u

e

s

t

F

l

a

g

S

I

F

Interrupt Structure

b

7

b

0

T

1

F

E

T

I

0

F

E

F

T

E

1

I

T

0

E

I

E

I

M

I

I N

T

C

0

R

e

g

i

s

t

e

r

M

1

0

a

s

t

e

r

I

n

t

e

r

u

p

t

G

l

o

b

a

l

:

g

l

o

b

a

l

e

n

a

b

l

e

g

l

o

b

a

l

d

i

s

a

b

l

e

E

1

0

x

t

e

r

n

a

l

I

n

t

e

r

u

p

t

E

n

a

b

l

:

e

d

n

i

a

b

l

s

a

b

t

l

e

T

1

0

i

m

e

r

/

E

v

e

n

t

C

o

u

n

t

e

r

0

1

I

n

:

e

d

n

i

T

1

0

:

e

d

n

i

E

1

0

x

t

e

r

n

a

l

I

n

t

e

r

u

p

t

R

e

q

u

e

:

a

i

c

t

i

c

v

e

n

i

v

e

T

1

0

i

m

e

r

/

E

v

e

n

t

C

o

u

n

t

e

r

0

I

n

:

a

i

c

a

t

T

1

0

i

m

e

r

/

E

v

e

n

t

C

o

u

n

t

e

r

1

I

n

:

a

i

c

a

t

N

o

i

m

p

l

e

m

e

n

t

e

d

,

r

e

a

d

a

s

INTC0 Register

b

0

b

7

S

I

F

E

S

I

N

T

C

1

R

e

g

i

s

t

e

r

S

1

0

P

I

S

e

r

i

a

l

I

n

t

e

r

f

a

c

e

i

n

t

e

r

u

:

e

d

n

i

a

b

l

e

s

a

b

l

e

N

o

t

i

m

p

l

i

e

a

m

l

e

n

t

e

d

,

r

e

a

d

a

s

"

0

S

1

0

P

I

S

e

r

i

n

t

e

r

f

a

c

e

d

a

t

a

t

r

:

a

i

c

t

i

v

e

n

a

c

t

i

v

e

N

o

t

i

m

p

l

e

a

m

s

e

n

"

t

0

e

"

d

,

r

e

a

d

INTC1 Register

Rev. 1.20

23

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

External Interrupt

SPI Interrupt

For an external interrupt to occur, the global interrupt en-

able bit, EMI, and external interrupt enable bit, EEI must

first be set. An actual external interrupt will take place

when the external interrupt request flag, EIF is set, a sit-

uation that will occur when a high to low transition ap-

pears on the interrupt pins. The external interrupt pin is

pin-shared with the I/O pins PC2 can only be configured

as an external interrupt pin if the corresponding external

interrupt enable bits in the interrupt control register

INTC0 have been set. The pins must also be setup as

inputs by setting the corresponding PCC.2 bits in the

port control register. When the interrupt is enabled, the

stack is not full and a high to low transition appears on

the external interrupt pin, a subroutine call to the exter-

nal interrupt vector at location 04H will take place. When

the interrupt is serviced, the external interrupt request

flag, EIF will be automatically reset and the EMI bit will

be automatically cleared to disable other interrupts.

Note that any pull-high resistor configuration options on

these pins will remain valid even if the pins are used as

external interrupt inputs.

For an SPI Interrupt to occur, the global interrupt enable

bit, EMI, and the corresponding SPI interrupt enable bit,

ESII, must be first set. The SBEN bit in the SBCR regis-

ter must also be set. An actual SPI Interrupt will take

place when one of the one SPI interrupt request flags,

SIF, is set, a situation that will occur when 8-bits of data

are transferred or received from either of the SPI inter-

faces. When the interrupt is enabled, the stack is not full

and an SPI interrupt occurs, a subroutine call to the SPI

interrupt vector at location 10H, will take place. When

the interrupt is serviced, the SPI interrupt request flag,

SIF, will be automatically reset and the EMI bit will be au-

tomatically cleared to disable other interrupts.

Programming Considerations

By disabling the interrupt enable bits, a requested inter-

rupt can be prevented from being serviced, however,

once an interrupt request flag is set, it will remain in this

condition in the interrupt control register until the corre-

sponding interrupt is serviced or until the request flag is

cleared by a software instruction.

It is recommended that programs do not use the ²CALL

subroutine² instruction within the interrupt subroutine.

Interrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications. If

only one stack is left and the interrupt is not well con-

trolled, the original control sequence will be damaged

once a ²CALL subroutine² is executed in the interrupt

subroutine.

Timer/Event Counter Interrupt

For a Timer/Event Counter interrupt to occur, the global

interrupt enable bit, EMI, and the corresponding timer

interrupt enable bit, ET0I or ET1I, must first be set. An

actual Timer/Event Counter interrupt will take place

when the Timer/Event Counter interrupt request flag,

T0F or T1F, is set, a situation that will occur when the

Timer/Event Counter overflows. When the interrupt is

enabled, the stack is not full and a Timer/Event Counter

overflow occurs, a subroutine call to the timer interrupt

vector at location 08H or 0CH, will take place. When the

interrupt is serviced, the timer interrupt request flag, T0F

or T1F, will be automatically reset and the EMI bit will be

automatically cleared to disable other interrupts.

All of these interrupts have the capability of waking up

the processor when in the Power Down Mode.

Only the Program Counter is pushed onto the stack. If

the contents of the accumulator or status register are al-

tered by the interrupt service program, which may cor-

rupt the desired control sequence, then the contents

should be saved in advance.

Rev. 1.20

24

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Reset and Initialisation

A reset function is a fundamental part of any

microcontroller ensuring that the device can be set to

some predetermined condition irrespective of outside

parameters. The most important reset condition is after

power is first applied to the microcontroller. In this case,

internal circuitry will ensure that the microcontroller, af-

ter a short delay, will be in a well defined state and ready

to execute the first program instruction. After this

power-on reset, certain important internal registers will

be set to defined states before the program com-

mences. One of these registers is the Program Counter,

which will be reset to zero forcing the microcontroller to

begin program execution from the lowest Program

Memory address.

the RES pin, whose additional time delay will ensure

that the RES pin remains low for an extended period

to allow the power supply to stabilise. During this time

delay, normal operation of the microcontroller will be

inhibited. After the RES line reaches a certain voltage

value, the reset delay time t_RSTDis invoked to provide

an extra delay time after which the microcontroller will

begin normal operation. The abbreviation SST in the

figures stands for System Start-up Timer.

V

D

0

.

D

9

D

V

R

E

S

t

R

S

T

D

S

T

i

m

e

-

o

u

t

I

n

t

e

r

n

a

l

R

e

s

e

t

In addition to the power-on reset, situations may arise

where it is necessary to forcefully apply a reset condition

when the microcontroller is running. One example of this

is where after power has been applied and the

microcontroller is already running, the RES line is force-

fully pulled low. In such a case, known as a normal oper-

ation reset, some of the microcontroller registers remain

unchanged allowing the microcontroller to proceed with

normal operation after the reset line is allowed to return

high. Another type of reset is when the Watchdog Timer

overflows and resets the microcontroller. All types of re-

set operations result in different register conditions be-

ing setup.

Power-On Reset Timing Chart

For most applications a resistor connected between

VDD and the RES pin and a capacitor connected be-

tween VSS and the RES pin will provide a suitable ex-

ternal reset circuit. Any wiring connected to the RES

pin should be kept as short as possible to minimise

any stray noise interference.

V

R

D

S

1

0

W

0

k

E

0

m

. F 1

V

S

Reset Functions

Basic Reset Circuit

There are five ways in which a microcontroller reset can

occur, through events occurring both internally and ex-

ternally:

For applications that operate within an environment

where more noise is present the Enhanced Reset Cir-

cuit shown is recommended.

·

Power-on Reset

The most fundamental and unavoidable reset is the

one that occurs after power is first applied to the

microcontroller. As well as ensuring that the Program

Memory begins execution from the first memory ad-

dress, a power-on reset also ensures that certain

other registers are preset to known conditions. All the

I/O port and port control registers will power up in a

high condition ensuring that all pins will be first set to

inputs.

0

.

m

0

F

1

V

R

D

S

1

0

W

0

k

E

1

0

W

k

0

m

. F 1

V

S

Although the microcontroller has an internal RC reset

function, if the VDD power supply rise time is not fast

enough or does not stabilise quickly at power-on, the

internal reset function may be incapable of providing a

proper reset operation. In such cases it is recom-

mended that an external RC network is connected to

Enhanced Reset Circuit

More information regarding external reset circuits is

located in Application Note HA0075E on the Holtek

website.

Rev. 1.20

25

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

·

RES Pin Reset

Watchdog Time-out Reset during Power Down

The Watchdog time-out Reset during Power Down is

a little different from other kinds of reset. Most of the

conditions remain unchanged except that the Pro-

gram Counter and the Stack Pointer will be cleared to

²0² and the TO flag will be set to ²1². Refer to the A.C.

Characteristics for t_SSTdetails.

This type of reset occurs when the microcontroller is

already running and the RES pin is forcefully pulled

low by external hardware such as an external switch.

In this case as in the case of other reset, the Program

Counter will reset to zero and program execution initi-

ated from this point.

0

.

D

9

D

V

W

D

T

i

m

e

-

o

u

t

0

.

D

4

D

V

R

E

S

t

S

T

t

R

S

T

D

S

T

i

m

e

-

o

u

t

S

T

i

m

e

-

o

u

t

WDT Time-out Reset during Power Down

Timing Chart

I

n

t

e

r

n

a

l

R

e

s

e

t

RES Reset Timing Chart

Reset Initial Conditions

The different types of reset described affect the reset

flags in different ways. These flags, known as PDF and

TO are located in the status register and are controlled

by various microcontroller operations, such as the

Power Down function or Watchdog Timer. The reset

flags are shown in the table:

·

Low Voltage Reset - LVR

The microcontroller contains a low voltage reset cir-

cuit in order to monitor the supply voltage of the de-

vice. The LVR function is selected via a configuration

option. If the supply voltage of the device drops to

within a range of 0.9V~V_LVRsuch as might occur when

changing the battery, the LVR will automatically reset

the device internally. For a valid LVR signal, a low sup-

ply voltage, i.e., a voltage in the range between

0.9V~V_LVRmust exist for a time greater than that spec-

ified by t_LVRin the A.C. characteristics. If the low sup-

ply voltage state does not exceed this value, the LVR

will ignore the low supply voltage and will not perform

a reset function. The actual V_LVRvalue can be se-

lected via configuration options.

TO PDF

RESET Conditions

0

u

1

0

1

u

1

RES reset during power-on

RES wake-up during Power Down

RES reset during normal operation

WDT time-out reset during normal operation

WDT time-out reset during Power Down

L

V

R

Note: ²u² stands for unchanged

t

R

S

T

D

S

T

i

m

e

-

o

u

t

The following table indicates the way in which the vari-

ous components of the microcontroller are affected after

a power-on reset occurs.

I

n

t

e

r

n

a

l

R

e

s

e

t

Low Voltage Reset Timing Chart

Item

Condition After RESET

·

Program Counter Reset to zero

Watchdog Time-out Reset during Normal Operation

The Watchdog Time-out Reset during normal opera-

tion is the same as a hardware RES pin reset except

that the Watchdog time-out flag TO will be set to ²1².

Interrupts

WDT

All interrupts will be disabled

Clear after reset, WDT begins

counting

W

D

T

i

m

e

-

o

u

t

Timer/Event

Counter

t

R

S

T

D

Timer Counter will be turned off

S

T

i

m

e

-

o

u

t

The Timer Counter Prescaler will

be cleared

I

n

t

e

r

n

a

l

R

e

s

e

t

Prescaler

WDT Time-out Reset during Normal Operation

Timing Chart

Input/Output Ports I/O ports will be setup as inputs

Stack Pointer will point to the top

Stack Pointer

of the stack

Rev. 1.20

26

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable

continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller

is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller in-

ternal registers.

Reset

WDT Time-out

RES Reset

WDT Time-out

Register

(Power-on) (Normal Operation) (Normal Operation)

(HALT)

(HALT)*

MP0

MP1

ACC

PCL

x x x x x x x x

0 0 0 0 0 0 0 0

x x x x x x x x

- x x x x x x x

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

- u u u u u u u

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

- u u u u u u u

u u u u u u u u u u u u u u u u

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

u u u u u u u u u u u u u u u u

- u u u u u u u - u u u u u u u

TBLP

TBLH

WDTS

(for HT82K76E-L)

- - - - - 1 1 1

- - - - 0 1 1 1

- - - - - 1 1 1

- - - - 0 1 1 1

- - - - - 1 1 1

- - - - 0 1 1 1

- - - - - 1 1 1 - - - - - u u u

- - - - 0 1 1 1 - - - - u u u u

WDTS

(for HT82K70E-L/A-L )

STATUS

INTC0

TMR0H

TMR0L

TMR0C

TMR1H

TMR1L

TMR1C

PA

- - 0 0 x x x x

- 0 0 0 0 0 0 0

x x x x x x x x

0 0 - 0 1 0 0 0

x x x x x x x x

0 0 - 0 1 0 0 0

1 1 1 1 1 1 1 1

- - - - - 1 1 1

- - - 0 - - - 0

x x x x x x x x

0 1 1 0 0 0 0 0

x x x x x x x x

0 0 0 0 0 0 0 0

- - 1 u u u u u

- 0 0 0 0 0 0 0

x x x x x x x x

0 0 - 0 1 0 0 0

x x x x x x x x

0 0 - 0 1 0 0 0

1 1 1 1 1 1 1 1

- - - - - 1 1 1

- - - 0 - - - 0

u u u u u u u u

0 1 1 0 0 0 0 0

x x x x x x x x

u u u u 0 0 0 0

- - u u u u u u

- 0 0 0 0 0 0 0

x x x x x x x x

0 0 - 0 1 0 0 0

x x x x x x x x

0 0 - 0 1 0 0 0

1 1 1 1 1 1 1 1

- - - - - 1 1 1

- - - 0 - - - 0

u u u u u u u u

0 1 1 0 0 0 0 0

x x x x x x x x

u u u u 0 0 0 0

- - 0 1 u u u u - - 1 1 u u u u

- 0 0 0 0 0 0 0 - u u u u u u u

x x x x x x x x u u u u u u u u

0 0 - 0 1 0 0 0 u u - u u u u u

x x x x x x x x u u u u u u u u

0 0 - 0 1 0 0 0 u u - u u u u u

1 1 1 1 1 1 1 1 u u u u u u u u

PAC

PB

PBC

PC

PCC

PD

PDC

PE

PEC

PF

u u u u u u u u

- - - - - 1 1 1

PFC

INTC1

TBHP

SBCR

SBDR

WSR

- - - 0 - - - 0 - - - u - - - u

u u u u u u u u u u u u u u u u

0 1 1 0 0 0 0 0 u u u u u u u u

x x x x x x x x u u u u u u u u

u u u u 0 0 0 0 u u u u u u u u

CTLR

(for HT82K76E-L)

0 0 0 0 x 0 0 0

0 0 0 0 x 0 0 0 u u u u x u u 0

0 0 0 0 x 0 0 0 u u u u x u u u

CTLR

(for HT82K70E-L/A-L )

Note:

²*² means ²warm reset²

²-² not implemented

²u² means ²unchanged²

²x² means ²unknown²

Rev. 1.20

27

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

V

D

Oscillator

There are two oscillator circuits contained within the de-

vice. The first is the system oscillator which utilises an

external crystal or RC and the second is the Watchdog

timer oscillator which is fully integrated and requires no

external components.

2

7

W

~

k

7

5

W

0

k

O

S

C

1

4

7

0

p

F

f

S

Y

/

S

4

N

M

O

S

O

p

O

e

S

n

C

D

2

r

a

i

n

System Clock Configurations

RC Oscillator

There are two oscillator mode Crystal and RC. For Crys-

tal mode no built-in capacitor between OSC1, OSC2

and GND. The simple connection of a crystal across

OSC1 and OSC2 will create the necessary phase shift

and feedback for oscillation, without requiring external

capacitors. However, for some crystal types and fre-

quencies, to ensure oscillation, it may be necessary to

add two small value capacitors, C1 and C2. Using a ce-

ramic resonator will usually require two small value ca-

pacitors, C1 and C2, to be connected as shown for

oscillation to occur. The values of C1 and C2 should be

selected in consultation with the crystal or resonator

manufacturer's specification. In most applications, re-

sistor R1 is not required, R1 may be necessary to en-

sure the oscillator stops running when VDD falls below

its operating range.

More information regarding the oscillator is located in

Application Note HA0075E on the Holtek website.

Watchdog Timer Oscillator

The WDT oscillator is a fully self-contained free running

on-chip RC oscillator with a typical period of 65ms at 5V

requiring no external components. When the device en-

ters the Power Down Mode, the system clock will stop

running but the WDT oscillator continues to free-run and

to keep the watchdog active. However, to preserve

power in certain applications the WDT oscillator can be

disabled via a configuration option.

Power Down Mode and Wake-up

Power Down Mode

External RC Oscillator

All of the Holtek microcontrollers have the ability to enter

a Power Down Mode. When the device enters this mode,

the normal operating current, will be reduced to an ex-

tremely low standby current level. This occurs because

when the device enters the Power Down Mode, the sys-

tem oscillator is stopped which reduces the power con-

sumption to extremely low levels, however, as the device

maintains its present internal condition, it can be woken

up at a later stage and continue running, without requiring

a full reset. This feature is extremely important in applica-

tion areas where the microcontroller must have its power

supply constantly maintained to keep the device in a

known condition but where the power supply capacity is

limited such as in battery applications.

Using the external system RC oscillator requires that a

resistor, with a value between 27kW and 750kW, is con-

nected between OSC1 and VDD, and a capacitor is con-

nected to ground. The generated system clock divided

by 4 will be provided on OSC2 as an output which can

be used for external synchronization purposes. Note

that as the OSC2 output is an NMOS open-drain type, a

pull high resistor should be connected if it to be used to

monitor the internal frequency. Although this is a cost ef-

fective oscillator configuration, the oscillation frequency

can vary with VDD, temperature and process variations

and is therefore not suitable for applications where tim-

ing is critical or where accurate oscillator frequencies

are required.For the value of the external resistor ROSC

refer to the Holtek website for typical RC Oscillator vs.

Temperature and VDD characteristics graphics. Note

that it is the only microcontroller internal circuitry to-

gether with the external resistor, that determine the fre-

quency of the oscillator. The external capacitor shown

on the diagram does not influence the frequency of os-

cillation.

Entering the Power Down Mode

There is only one way for the device to enter the Power

Down Mode and that is to execute the ²HALT² instruc-

tion in the application program. When this instruction is

executed, the following will occur:

·

The system oscillator will stop running and the appli-

cation program will stop at the ²HALT² instruction.

C

1

The Data Memory contents and registers will maintain

their present condition.

O

S

C

1

R

1

The WDT will be cleared and resume counting if the

WDT clock source come from the WDT oscillator. The

WDT will stop if its clock source originates from the

system clock.

O

S

C

2

C

2

Crystal/Ceramic Oscillator

·

The I/O ports will maintain their present condition.

In the status register, the Power Down flag, PDF, will be

set and the Watchdog time-out flag, TO, will be cleared.

Rev. 1.20

28

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Standby Current Considerations

When a PA0/PA1 or PB0/PB1 wake up occurs, bits in the

WSR register can be read to know which pin changed

first.

As the main reason for entering the Power Down Mode

is to keep the current consumption of the microcontroller

to as low a value as possible, perhaps only in the order

of several micro-amps, there are other considerations

which must also be taken into account by the circuit de-

signer if the power consumption is to be minimised.

If the system is woken up by an interrupt, then two possi-

ble situations may occur. The first is where the related

interrupt is disabled or the interrupt is enabled but the

stack is full, in which case the program will resume exe-

cution at the instruction following the ²HALT² instruction.

In this situation, the interrupt which woke-up the device

will not be immediately serviced, but will rather be ser-

viced later when the related interrupt is finally enabled or

when a stack level becomes free. The other situation is

where the related interrupt is enabled and the stack is

not full, in which case the regular interrupt response

takes place. If an interrupt request flag is set to ²1² be-

fore entering the Power Down Mode, the wake-up func-

tion of the related interrupt will be disabled.

Special attention must be made to the I/O pins on the

device. All high-impedance input pins must be con-

nected to either a fixed high or low level as any floating

input pins could create internal oscillations and result in

increased current consumption. Care must also be

taken with the loads, which are connected to I/O pins,

which are setup as outputs. These should be placed in a

condition in which minimum current is drawn or con-

nected only to external circuits that do not draw current,

such as other CMOS inputs.

No matter what the source of the wake-up event is, once

a wake-up situation occurs, a time period equal to 1024

system clock periods will be required before normal sys-

tem operation resumes. However, if the wake-up has

originated due to an interrupt, the actual interrupt sub-

routine execution will be delayed by an additional one or

more cycles. If the wake-up results in the execution of

the next instruction following the ²HALT² instruction, this

will be executed immediately after the 1024 system

clock period delay has ended.

If the configuration options have enabled the Watchdog

Timer internal oscillator then this will continue to run

when in the Power Down Mode and will thus consume

some power. For power sensitive applications it may be

therefore preferable to use the system clock source for

the Watchdog Timer.

Wake-up

After the system enters the Power Down Mode, it can be

woken up from one of various sources listed as follows:

·

An external reset

Low Voltage Detector - LVD

An external falling edge on any of the I/O pins

A system interrupt

The Low Voltage Detector internal function provides a

means for the user to monitor when the power supply

voltage falls below a certain fixed level as specified in

the DC characteristics.

A WDT overflow

If the system is woken up by an external reset, the de-

vice will experience a full system reset, however, if the

device is woken up by a WDT overflow, a Watchdog

Timer reset will be initiated. Although both of these

wake-up methods will initiate a reset operation, the ac-

tual source of the wake-up can be determined by exam-

ining the TO and PDF flags. The PDF flag is cleared by a

system power-up or executing the clear Watchdog

Timer instructions and is set when executing the ²HALT²

instruction. The TO flag is set if a WDT time-out occurs,

and causes a wake-up that only resets the Program

Counter and Stack Pointer, the other flags remain in

their original status.

Operation

The LVD enable/disable control bit is bit 4 of the CTLR

register. Under normal operation, and when the power

supply voltage is above the specified VLVD value, spec-

ified by the LVD_sel bits in the CTLR register, the Low

battery bit will remain at a zero value. If the power supply

voltage should fall below this V_LVDvalue then the Low

battery bit will change to a high value indicating a low

voltage condition. Note that the Low battery bit is a

read-only bit. By polling the Low battery bit in the CTLR

register, the application program can therefore deter-

mine the presence of a low voltage condition.

Configuration options determine which pin or groups of

pins can be setup to permit a negative transition on the

pin to wake-up the system. When a Port pin wake-up oc-

curs, the program will resume execution at the instruc-

tion following the ²HALT² instruction.

Rev. 1.20

29

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Watchdog Timer

The Watchdog Timer is provided to prevent program

malfunctions or sequences from jumping to unknown lo-

cations, due to certain uncontrollable external events

such as electrical noise. It operates by providing a de-

vice reset when the WDT counter overflows. The WDT

clock is supplied by its own internal dedicated internal

WDT oscillator or by the f_SYS/4 clock source. Note that if

the WDT enable/disable configuration option has been

disabled, then any instruction relating to its operation

will result in no operation.

Timer time-out, it is completely dependent upon the fre-

quency the internal WDT oscillator.

Under normal program operation, a WDT time-out will

initialise a device reset and set the status bit TO. How-

ever, if the system is in the Power Down Mode, when a

WDT time-out occurs, the TO bit in the status register

will be set and only the Program Counter and Stack

Pointer will be reset. Three methods can be adopted to

clear the contents of the WDT. The first is an external

hardware reset, which means a low level on the RES

pin, the second is using the watchdog software instruc-

tions and the third is via a HALT instruction.

The WDT enable/disable is controlled using a bit in the

CTLR register. The WDT clock source and clear instruc-

tion type are selected through configuration options.

However, it should be noted that the WDT oscillator

clock period can vary with VDD, temperature and pro-

cess variations. Whether the WDT clock source is its

own internal WDT oscillator, it is further divided by an in-

ternal 6-bit counter and a clearable single bit counter to

give longer Watchdog time-outs. As the clear instruction

only resets the last stage of the divider chain, for this

reason the actual division ratio and corresponding

Watchdog Timer time-out can vary by a factor of two.

There are two methods of using software instructions to

clear the Watchdog Timer, one of which must be chosen

by configuration option. The first option is to use the sin-

gle ²CLR WDT² instruction while the second is to use

the two commands ²CLR WDT1² and ²CLR WDT2². For

the first option, a simple execution of ²CLR WDT² will

clear the WDT while for the second option, both ²CLR

WDT1² and ²CLR WDT2² must both be executed to

successfully clear the WDT. Note that for this second

option, if ²CLR WDT1² is used to clear the WDT, succes-

sive executions of this instruction will have no effect,

only the execution of a ²CLR WDT2² instruction will

clear the WDT. Similarly after the ²CLR WDT2² instruc-

tion has been executed, only a successive ²CLR WDT1²

instruction can clear the Watchdog Timer.

The exact division ratio depends upon the residual value

in the Watchdog Timer counter before the clear instruc-

tion is executed. It is important to realise that as there

are no independent internal registers or configuration

options associated with the length of the Watchdog

C

L

R

W

D

T

1

F

l

a

g

r

C

l

e

a

W

D

T

y

p

e

C

o

n

f

i

g u

g

r

a

t

i

o

n

O

p

t

i

o

n

C

L

R

W

D

T

2

F

l

a

1

o

r

2

I

n

s

t

r

u

c

t

i

o

n

s

C

L

R

C

L

R

f

S

Y

S

W

D

T

C

l

o

c

k

S

o

u

r

c

e

u

6

-

b

i

t

C

o

n

t

e

r

7

-

b

i

n

t

P

r

e

s

c

a

l

e

r

C

o

n

f

i

g

u

r

a

t

i

o

n

) (

O

p

t

i

o

W

D

T

O

s

c

i

l

a

t

o

¸

6

4

W

D

T

C

l

o

c

k

S

o

u

r

c

e

W

S

0

X

~

W

S

2

8

-

t

o

-

1

M

U

W

D

T

i

m

e

-

o

u

t

Watchdog Timer

b

7

b

0

W

S

2

W

S

W

1

S

0

W

D

T

S

R

e

g

i

s

t

e

r

W

D

T

p

r

e

s

c

a

l

e

r

a

t

e

s

e

l

e

W

S

W

S

1

W

S

0

W

D

T

R

a

t

e

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D

i

s

a

b

l

e

W

D

T

1

:

1

4

8

1

:

1

6

1

:

3

6

1

2

4

2

8

N

o

t

u

s

e

d

Watchdog Timer Register for HT82K76E-L

Rev. 1.20

30

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

b

7

b

0

W

S

2

W

P

S

2

R

S

1

W

D

T

S

R

e

g

i

s

t

e

r

W

S

0

W

D

T

p

r

e

s

c

a

l

e

r

a

t

e

s

e

l

e

W

S

W

S

1

W

S

0

W

D

T

R

a

t

e

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D

i

s

a

b

l

e

W

D

T

1

:

1

4

8

1

:

1

6

1

:

3

6

1

2

4

2

8

P

C

0

/

P

C

1

r

e

s

i

s

t

o

r

s

e

l

e

c

t

1

:

W

4

.

7

k

0

W

3

(

0

d

k

e

f

a

u

l

t

)

(

o

C

o

n

f

i

g

u

r

a

t

i

o

n

o

p

t

i

o

n

e

p

t

i

o

n

,

t

h

a

n

t

h

e

b

i

t

s

e

t

N

o

t

u

s

e

d

Watchdog Timer Register for HT82K70E-L and HT82K70A-L

Bit

Name

Description

Read only bit.

7

Z2_WAKEUP 1: Z2 changed before Z1

0: default

Read only bit.

Z1_WAKEUP 1: Z1 changed before Z2

0: default

6

5

4

Read only bit.

V2_WAKEUP 1: V2 changed before V1

0: default

Read only bit.

V1_WAKEUP 1: V1 changed before V2

0: default

This bit control the shared PIN (SCS, SDI, SDO and SCK) is SPI or GPIO mode

3

2

SPI_EN

1: SPI mode

0: IO mode (default)

1: enable, this bit is used to enable/disable software CSEN function

0: disable, SCS define as GPIO (default)

SPI_CSEN

1: SPI first output the data immediately after the SPI is enable. And SPI output the data in

the falling edge(polarity=0) or rising edge (polarity=1); SPI read data in the in the rising

edge (polarity=0) or falling edge (polarity=1);

1

0

CKEG

0: SPI output the data in the rising edge(polarity=0) or falling edge (polarity=1);

SPI read data in the in the falling edge(polarity=0) or rising edge (polarity=1); (default)

1: clock polarity rising

SPI_ CPOL

0: clock polarity falling (default)

Note: The Internal Register bit4~bit7 data will clear to zero after F/W read the register.

Wake-up Status Register - WSR

Rev. 1.20

31

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Bit

Name

Description

To Selected low voltage detector level, Bit7, 6, 5 =

000: 1.0V

001: 1.2V

010: 1.4V

7~5

LVD_sel

011: 2.0V

100: 2.4V

101: 2.7V

110: 3.0V or 1.8V, control by CTLR register bit 0

111: 3.3V or 2.2V, control by CTLR register bit 0

To control the DC/DC to check the LVD voltage

1: enable LVD

4

3

LVD_Rd_ctrl

Low battery

0: disable LVD (default)

Flag for battery low signal (error 5%)

1: battery voltage £ according LVD_sel voltage

0: battery voltage > according LVD_sel voltage

The user should wait at least 20ms after set LVD_rd_ctrl and then read the corresponding

voltage Low battery signal

To control the Watchdog timer

1: enable

2

1

0

WDTEN

TMR1S

0: disable

To selected Timer 1 source

1: WDT OSC

0: f_SYS/4

Where WDTOSC is selected as TMR1 source. WDTOSC is always enabled.

To selected LVD_sel=110 & 111 mode

1: 1.8V/2.2V

LVD_mod

0: 3.0V/3.3V (default)

Control Register - CTLR for HT82K70E-L and HT82K70A-L

Bit

Name

Description

To Selected low voltage detector level, Bit7, 6, 5 =

000: 1.0V

001: 1.2V

010: 1.4V

011: 2.0V

100: 2.4V

101: 2.7V

110: 3.0V

111: 3.3V

7~5

LVD_sel

To control the DC/DC to check the LVD voltage

1: enable LVD

4

3

2

LVD_Rd_ctrl

Low battery

WDTEN

0: disable LVD (default)

Flag for battery low signal (error 5%)

1: battery voltage £ according LVD_sel voltage

0: battery voltage > according LVD_sel voltage

The user should wait at least 20ms after set LVD_rd_ctrl and then read the corresponding

voltage Low battery signal

To control the Watchdog timer

1: enable

0: disable

To selected Timer 1 source

1: WDT OSC

1

0

TMR1S

0: f_SYS/4

Where WDTOSC is selected as TMR1 source. WDTOSC is always enabled.

¾

Unimplemented, read as ²0²

Control Register - CTLR for HT82K76E-L

Rev. 1.20

32

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

SPI Serial Interface

The device include single SPI Serial Interfaces. The SPI

interface is a full duplex serial data link, originally de-

signed by Motorola, which allows multiple devices con-

nected to the same SPI bus to communicate with each

other. The devices communicate using a master/slave

technique where only the single master device can initi-

ate a data transfer. A simple four line signal bus is used

for all communication.

SPI Registers

There are three registers associated with the SPI Inter-

face. These are the SBCR register which is the control

register and the SBDR which is the data register and

WSR low nibble byte which is the SPI mode control reg-

ister. The SBCR register is used to setup the required

setup parameters for the SPI bus and also used to store

associated operating flags, while the SBDR register is

used for data storage.

SPI Interface Communication

The WSR register low nibble byte is used to select SPI

mode, clock polarity edge selection and SPI enable or

disable selection.

Four lines are used for SPI communication known as

SDI - Serial Data Input, SDO - Serial Data Output, SCK -

Serial Clock and SCS - Slave Select. Note that the con-

dition of the Slave Select line is conditioned by the

CSEN bit in the SBCR control register. If the CSEN bit is

high then the SCS line is active while if the bit is low then

the SCS line will be in a floating condition. The following

timing diagram depicts the basic timing protocol of the

SPI bus.

D

a

t

a

B

u

s

S

B

D

R

(

R

e

c

e

i

v

e

d

D

a

t

a

R

e

g

i

s

t

e

r

)

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

M

S

D

O

B

u

f

S

f

e

r

O

U

X

D

M

L

S

B

E

N

M

U

X

S

D

I

n

t

e

r

n

a

l

B

a

u

d

R

a

t

e

C

l

o

c

k

a

n

d

,

s

t

a

r

t

M

U

E

N

X

S

C

K

a

n

d

,

s

t

a

r

t

C

0

1

2

T

R

F

C

l

o

c

k

P

o

l

a

M

r

a

i

s

t

y

e

r

o

r

S

l

a

v

e

A

N

D

W

C

O

L

F

l

a

g

I

n

t

e

r

n

a

l

B

u

s

y

F

l

a

g

S

B

E

N

W

r

i

t

e

S

B

D

R

S

B

E

N

W

r

i

t

e

S

B

D

R

E

n

a

b

l

e

/

D

a

n

d

,

s

t

a

r

t

W

r

i

t

e

S

B

D

R

E

N

S

C

S

M

a

s

t

e

r

o

r

S

l

a

v

e

S

B

E

N

C

S

E

N

SPI Block Diagram

Note: WCOL: set by SPI cleared by users

CSEN: enable/disable chip selection function pin

master mode: 1/0 = with/without SCS output function

Slave mode: 1/0 = with/without SCS input control function

SBEN: enable/disable serial bus (0: initialise all status flags)

when SBEN=0, all status flags should be initialised

when SBEN=1, all SPI related function pins should stay at floating state

TRF: 1 = data transmitted or received, 0= data is transmitting or still not received

CPOL: I/O = clock polarity rising/falling edge: WSR register bit 0

If clock polarity set to rising edge (SPI_CPOL=1), serial clock timing follow SCK, otherwise (SPI_CPOL=0)

SCK is the serial clock timing.

Rev. 1.20

33

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

C

K

E

G

=

0

S

B

E

N

=

1

,

C

S

E

N

=

0

a

n

d

w

r

i

P

(

A

4

/

S

C

S

B

E

N

=

C

S

E

N

=

1

a

n

d

w

r

i

t

e

d

a

t

S

P

I

_

C

S

E

N

=

1

)

P

(

A

5

/

S

C

K

S

P

I

_

C

P

O

L

=

0

)

P

(

A

5

/

S

C

K

S

P

I

_

C

P

O

L

=

1

)

P

A

6

/

S

D

I

D

7

/

D

0

6

/

D

1

5

/

D

2

4

/

D

3

/

D

4

2

/

D

5

1

/

D

6

0

/

D

7

P

A

7

/

S

D

O

D

7

C

K

E

G

=

1

S

B

E

N

=

1

,

C

S

E

N

=

0

a

n

d

w

r

i

P

(

A

4

/

S

C

S

B

E

N

=

C

S

E

N

=

1

a

n

d

w

r

i

t

e

d

a

t

S

P

I

_

C

S

E

N

=

1

)

P

(

A

5

/

S

C

K

S

P

I

_

C

P

O

L

=

0

)

P

(

A

5

/

S

C

K

S

P

I

_

C

P

O

L

=

1

)

P

A

6

/

S

D

I

D

7

/

D

0

6

/

D

1

5

/

D

2

4

/

D

3

/

D

4

2

/

D

5

1

/

D

6

0

/

D

7

P

A

7

/

S

D

O

D

7

/

D

SPI Bus Timing

Rev. 1.20

34

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

SPI Operation

After Power on, the contents of the SBDR register will be

in an unknown condition while the SBCR register will de-

fault to the condition below:

All communication is carried out using the 4-line inter-

face for both Master or Slave Mode. The timing diagram

shows the basic operation of the bus.

CKS M1 M0 SBEN MLS CSEN WCOL TRF

The SBEN bit in the SBCR register controls the SCS line

of the SPI interface. Setting this bit high, will enable the

SPI interface by allowing the SCS line to be active,

which can then be used to control the SPI interface. If

the SBEN bit is low, the SCS line will be in a floating con-

dition and can therefore not be used for control of the

SPI interface. The SBEN bit in the SBCR register must

also be high which will place the SDI line in a floating

condition and the SDO line high. If in the Master Mode

the SCK line will be either high or low depending upon

the clock polarity configuration option. If in the Slave

Mode the SCK line will be in a floating condition. If SBEN

is low then the bus will be disabled and SCS, SDI, SDO

and SCK will all be in a floating condition.

0

1

0

Note that data written to the SBDR register will only be

written to the TXRX buffer, whereas data read from the

SBDR register will actual be read from the register.

SPI Bus Enable/Disable

To enable the SPI bus, SBEN should be set high, then

SCK, SDI, SDO and SCS lines should all be zero, then

wait for data to be written to the SBDR (TXRX buffer)

register. For the Master Mode, after data has been writ-

ten to the SBDR (TXRX buffer) register then transmis-

sion or reception will start automatically. When all the

data has been transferred the TRF bit should be set. For

the Slave Mode, when clock pulses are received on

SCK, data in the TXRX buffer will be shifted out or data

on SDI will be shifted in.

To Disable the SPI bus SCK, SDI, SDO, SCS should be

floating.

b

7

b

0

C

K

M

1

M

0

S

B

E

M

N

L

C

S

E

W

N

C

O

T

R

L

S

F

B

C

R

e

g

i

s

t

e

r

T

0

1

r

a

n

s

m

i

t

/

R

e

c

e

i

v

e

f

l

a

g

:

n

t

o

t

c

o

m

p

l

e

t

e

r

a

n

s

m

i

s

i

o

n

/

r

e

c

e

p

t

W

0

1

r

i

t

e

c

o

l

i

s

i

o

n

b

i

t

:

c

o

l

i

s

i

o

n

f

r

e

o

l

i

s

i

o

n

d

e

t

e

c

t

e

d

S

0

1

e

l

e

c

t

i

b

o

n

e

s

i

g

n

a

l

e

n

a

b

l

:

S

e

o

C

a

S

t

i

n

f

g

l

n

S

a

l

M

0

1

S

B

/

L

S

B

F

i

r

s

t

B

i

t

:

L

M

B

s

h

i

f

t

f

i

r

s

t

S

B

s

h

i

f

t

f

i

r

s

t

S

0

1

e

r

i

a

l

b

u

s

e

n

a

b

l

e

/

d

i

s

a

:

d

e

i

n

s

a

b

l

e

a

b

l

e

M

a

s

t

e

r

/

S

l

a

v

e

/

B

a

u

d

r

a

t

M

1

M

0

1

0

1

0

1

m

a

s

t

e

r

,

S

P

b

I

a

u

d

r

a

t

e

m

a

s

t

e

r

,

/

b

4

a

u

d

r

a

t

e

m

s

1

6

l

a

v

e

m

o

d

e

C

0

1

l

o

c

k

s

o

u

r

c

e

s

e

l

e

c

t

b

i

:

S

P

=

S

I

f

Y

/

S

4

=

f

SPI Interface Control Register

Rev. 1.20

35

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Step 2. Setup the M0 and M1 bits to 11 to select the

Slave Mode. The CKS bit is don¢t care.

Step 3. Setup the CSEN bit and setup the MLS bit to

choose if the data is MSB or LSB first,

this must be same as the Master device.

Step 4. Setup the SBEN bit in the SBCR control

register to enable the SPI interface.

In the Master Mode, the Master will always generate the

clock signal. The clock and data transmission will be ini-

tiated after data has been written to the SBDR register.

In the Slave Mode, the clock signal will be received from

an external master device for both data transmission or

reception. The following sequences show the order to

be followed for data transfer in both Master and Slave

Mode:

Step 5. For write operations: write data to the SBCR

register, which will actually place the data into

the TXRX register, then wait for the master

clock and SCS signal. After this goto step 6.

For read operations: the data transferred in

on the SDI line will be stored in the TXRX

buffer until all the data has been received

at which point it will be latched into the SBDR

register.

·

Master Mode

Step 1. Select the clock source using the CKS bit in

the SBCR control register

Step 2. Setup the M0 and M1 bits in the SBCR control

register to select the Master Mode and the

required Baud rate. Values of 00, 01 or 10 can

be selected.

Step 6. Check the WCOL bit, if set high then a

collision error has occurred so return to step5.

If equal to zero then go to the following step.

Step 7. Check the TRF bit or wait for an SPI serial bus

interrupt.

Step 3. Setup the CSEN bit and setup the MLS bit to

choose if the data is MSB or LSB first,

this must be same as the Slave device.

Step 4. Setup the SBEN bit in the SBCR control

register to enable the SPI interface.

Step 5. For write operations: write the data to the

SBDR register, which will actually place the

data into the TXRX buffer. Then use the SCK

and SCS lines to output the data.

Step 8. Read data from the SBDR register

Step 9. Clear TRF

Step10. step 5

SPI Configuration Options and Status Control

Goto to step 6.For read operations: the data

transferred in on the SDI line will be stored

in the TXRX buffer until all the data has been

received at which point it will be latched into

the SBDR register.

Several configuration options exist for the SPI Interface

function which must be setup during device programming.

One option is to enable the operation of the WCOL, write

collision bit, in the SBCR register. Another option exists to

select the clock polarity of the SCK line. A configuration

option also exists to disable or enable the operation of the

CSEN bit in the SBCR register. If the configuration option

disables the CSEN bit then this bit cannot be used to affect

overall control of the SPI Interface.

Step 6. Check the WCOL bit, if set high then a

collision error has occurred so return to step5.

If equal to zero then go to the following step.

Step 7. Check the TRF bit or wait for an SPI serial bus

interrupt.

Step 8. Read data from the SBDR register

Step 9. Clear TRF

SPI include four pins , can share I/O mode status . The

status control combine with four bits for WSR and SBCR

register. Include SPI_CSEN , SPI_EN for WSR register

and CSEN, SBEN for SBCR register.

Step10. step 5

·

Slave Mode

Step 1. The CKS bit has a don¢t care value in the

slave mode.

Control Bit for Register

SPI Share Function Pins Status

SPI_EN SPI_CSEN

SBEN

CSEN

SCS

SCK

SDO

SDI

0

1

x

0

1

x

0

1

0

1

x

0

1

I/O mode

SPI mode (Z)

SPI mode

SPI mode (Z)

SPI mode

SPI mode (Z)

SPI mode

SPI mode (Z)

SPI mode

SPI mode (Z)

I/O mode

SPI mode (Z)

SPI mode

Note:

X: don¢t care

(Z) floating

Rev. 1.20

36

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Error Detection

Programming Considerations

The WCOL bit in the SBCR register is provided to indi-

cate errors during data transfer. The bit is set by the Se-

rial Interface but must be cleared by the application

program. This bit indicates a data collision has occurred

which happens if a write to the SBDR register takes

place during a data transfer operation and will prevent

the write operation from continuing. The bit will be set

high by the Serial Interface but has to be cleared by the

user application program. The overall function of the

WCOL bit can be disabled or enabled by a configuration

option.

When the device is placed into the Power Down Mode

note that data reception and transmission will continue.

The TRF bit is used to generate an interrupt when the

data has been transferred or received.

SPI Transfer Control FlowChart

A

S

P

I

T

r

a

n

s

f

e

r

W

r

i

t

e

D

a

t

a

C

l

e

a

r

W

C

O

L

S

B

D

R

M

a

s

t

e

r

S

r

l

a

v

e

M

a

s

t

e

r

o

S

l

a

v

e

Y

e

s

W

C

O

L

=

1

?

[

M

1

,

M

0

]

=

0

,

0

1

,

1

0

M

[

1

,

M

0

]

=

1

S

e

l

e

c

t

c

l

o

c

k

[

C

K

S

]

N

o

T

r

a

n

s

m

i

s

i

N

o

C

o

m

p

l

e

t

e

d

?

C

o

n

f

i

g

u

r

e

(

T

R

F

=

1

?

)

C

S

E

N

a

n

d

M

L

S

Y

e

s

S

B

E

N

=

1

r

e

a

d

a

t

a

f

S

B

D

R

A

c

l

e

a

r

T

R

F

N

o

r

T

r

a

n

s

f

e

F

i

n

i

s

h

e

d

?

Y

e

s

E

N

D

SPI Transfer Control Flowchart

Rev. 1.20

37

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Configuration Options

Item

Options

I/O Options

1

2

PA pull-high: enable or disable by bit

PB, PC, PD, PE, PF0~PF2 pull-high: enable or disable by nibble

3

PB, PC, PD, PE, PF0~PF2: Schmitt Trigger or Non-Schmitt Trigger by nibble

PA wake-up: enable or disable by bit

4

5

PB0, PB1 wake-up: enable or disable by bit

6

PB2~PB7, PC, PD, PE, PF0~PF2 wake-up: enable or disable by nibble

PA input type Schmitt Trigger and Non-Schmitt Trigger by bit

PE4 function option: PE4 as battery LVD input or PE4 as GPIO (default)

Output slew rate select: 0ns, 50ns, 100ns or 200ns

PA, NMOS or CMOS by bit

7

8

9

10

11

TBHP: enable or disable

Oscillator Options

12

OSC type selection: RC or crystal

Watchdog Options

13

14

CLRWDT instructions: one or two instructions

WDT Clock Source: f_SYS/4 or WDT oscillator

Application Circuits

1

2

3

4

5

6

7

8

9

4

3

2

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

P

V

P

B

A

B

F

D

S

E

C

E

5

4

3

2

1

0

3

2

1

0

P

B

6

7

V

D

/

T

Z

M

2

1

P

R

A

1

0

4

5

/

S

C

S

K

1

m

0

F

0

m

. F 1

P

A

6

/

S

D

I

P

A

7

/

S

D

O

P

F

2

7

6

5

V

D

/

V

2

1

P

E

1

2

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

1

0

W

0

k

R

e

s

e

t

1

0

O

S

C

2

1

0

m

. F 1

7

6

5

4

V

D

R

E

S

P

E

4

/

B

A

T

P

D

C

3

2

1

0

7

6

5

4

3

B

a

t

e

r

y

S

2

3

0

1

2

/

I

N

T

0

1

Rev. 1.20

38

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Instruction Set

Introduction

sure correct handling of carry and borrow data when re-

sults exceed 255 for addition and less than 0 for sub-

traction. The increment and decrement instructions

INC, INCA, DEC and DECA provide a simple means of

increasing or decreasing by a value of one of the values

in the destination specified.

Central to the successful operation of any

microcontroller is its instruction set, which is a set of pro-

gram instruction codes that directs the microcontroller to

perform certain operations. In the case of Holtek

microcontrollers, a comprehensive and flexible set of

over 60 instructions is provided to enable programmers

to implement their application with the minimum of pro-

gramming overheads.

Logical and Rotate Operations

The standard logical operations such as AND, OR, XOR

and CPL all have their own instruction within the Holtek

microcontroller instruction set. As with the case of most

instructions involving data manipulation, data must pass

through the Accumulator which may involve additional

programming steps. In all logical data operations, the

zero flag may be set if the result of the operation is zero.

Another form of logical data manipulation comes from

the rotate instructions such as RR, RL, RRC and RLC

which provide a simple means of rotating one bit right or

left. Different rotate instructions exist depending on pro-

gram requirements. Rotate instructions are useful for

serial port programming applications where data can be

rotated from an internal register into the Carry bit from

where it can be examined and the necessary serial bit

set high or low. Another application where rotate data

operations are used is to implement multiplication and

division calculations.

For easier understanding of the various instruction

codes, they have been subdivided into several func-

tional groupings.

Instruction Timing

Most instructions are implemented within one instruc-

tion cycle. The exceptions to this are branch, call, or ta-

ble read instructions where two instruction cycles are

required. One instruction cycle is equal to 4 system

clock cycles, therefore in the case of an 8MHz system

oscillator, most instructions would be implemented

within 0.5ms and branch or call instructions would be im-

plemented within 1ms. Although instructions which re-

quire one more cycle to implement are generally limited

to the JMP, CALL, RET, RETI and table read instruc-

tions, it is important to realize that any other instructions

which involve manipulation of the Program Counter Low

register or PCL will also take one more cycle to imple-

ment. As instructions which change the contents of the

PCL will imply a direct jump to that new address, one

more cycle will be required. Examples of such instruc-

tions would be ²CLR PCL² or ²MOV PCL, A². For the

case of skip instructions, it must be noted that if the re-

sult of the comparison involves a skip operation then

this will also take one more cycle, if no skip is involved

then only one cycle is required.

Branches and Control Transfer

Program branching takes the form of either jumps to

specified locations using the JMP instruction or to a sub-

routine using the CALL instruction. They differ in the

sense that in the case of a subroutine call, the program

must return to the instruction immediately when the sub-

routine has been carried out. This is done by placing a

return instruction RET in the subroutine which will cause

the program to jump back to the address right after the

CALL instruction. In the case of a JMP instruction, the

program simply jumps to the desired location. There is

no requirement to jump back to the original jumping off

point as in the case of the CALL instruction. One special

and extremely useful set of branch instructions are the

conditional branches. Here a decision is first made re-

garding the condition of a certain data memory or indi-

vidual bits. Depending upon the conditions, the program

will continue with the next instruction or skip over it and

jump to the following instruction. These instructions are

the key to decision making and branching within the pro-

gram perhaps determined by the condition of certain in-

put switches or by the condition of internal data bits.

Moving and Transferring Data

The transfer of data within the microcontroller program

is one of the most frequently used operations. Making

use of three kinds of MOV instructions, data can be

transferred from registers to the Accumulator and

vice-versa as well as being able to move specific imme-

diate data directly into the Accumulator. One of the most

important data transfer applications is to receive data

from the input ports and transfer data to the output ports.

Arithmetic Operations

The ability to perform certain arithmetic operations and

data manipulation is a necessary feature of most

microcontroller applications. Within the Holtek

microcontroller instruction set are a range of add and

subtract instruction mnemonics to enable the necessary

arithmetic to be carried out. Care must be taken to en-

Rev. 1.20

39

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Bit Operations

Other Operations

The ability to provide single bit operations on Data Mem-

ory is an extremely flexible feature of all Holtek

microcontrollers. This feature is especially useful for

output port bit programming where individual bits or port

pins can be directly set high or low using either the ²SET

[m].i² or ²CLR [m].i² instructions respectively. The fea-

ture removes the need for programmers to first read the

8-bit output port, manipulate the input data to ensure

that other bits are not changed and then output the port

with the correct new data. This read-modify-write pro-

cess is taken care of automatically when these bit oper-

ation instructions are used.

In addition to the above functional instructions, a range

of other instructions also exist such as the ²HALT² in-

struction for Power-down operations and instructions to

control the operation of the Watchdog Timer for reliable

program operations under extreme electric or electro-

magnetic environments. For their relevant operations,

refer to the functional related sections.

Instruction Set Summary

The following table depicts a summary of the instruction

set categorised according to function and can be con-

sulted as a basic instruction reference using the follow-

ing listed conventions.

Table Read Operations

Table conventions:

Data storage is normally implemented by using regis-

ters. However, when working with large amounts of

fixed data, the volume involved often makes it inconve-

nient to store the fixed data in the Data Memory. To over-

come this problem, Holtek microcontrollers allow an

area of Program Memory to be setup as a table where

data can be directly stored. A set of easy to use instruc-

tions provides the means by which this fixed data can be

referenced and retrieved from the Program Memory.

x: Bits immediate data

m: Data Memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Mnemonic

Arithmetic

Description

Cycles Flag Affected

ADD A,[m]

ADDM A,[m]

ADD A,x

Add Data Memory to ACC

1

1^Note

1

Z, C, AC, OV

C

Add ACC to Data Memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add Data Memory to ACC with Carry

1

1^Note

Add ACC to Data memory with Carry

Subtract immediate data from the ACC

Subtract Data Memory from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

1

1^Note

Subtract Data Memory from ACC with result in Data Memory

Subtract Data Memory from ACC with Carry

Subtract Data Memory from ACC with Carry, result in Data Memory

Decimal adjust ACC for Addition with result in Data Memory

1

1^Note

Logic Operation

AND A,[m]

OR A,[m]

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

Logical AND Data Memory to ACC

Logical OR Data Memory to ACC

Logical XOR Data Memory to ACC

Logical AND ACC to Data Memory

Logical OR ACC to Data Memory

Logical XOR ACC to Data Memory

Logical AND immediate Data to ACC

Logical OR immediate Data to ACC

Logical XOR immediate Data to ACC

Complement Data Memory

1

Z

1

1^Note

1

OR A,x

1

XOR A,x

1

1^Note

CPL [m]

CPLA [m]

Complement Data Memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment Data Memory with result in ACC

1

Z

Increment Data Memory

1^Note

DECA [m]

DEC [m]

Decrement Data Memory with result in ACC

Decrement Data Memory

1

1^Note

Rev. 1.20

40

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Mnemonic

Rotate

Description

Cycles Flag Affected

RRA [m]

RR [m]

Rotate Data Memory right with result in ACC

Rotate Data Memory right

1

1^Note

1

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate Data Memory right through Carry with result in ACC

Rotate Data Memory right through Carry

Rotate Data Memory left with result in ACC

Rotate Data Memory left

1^Note

C

1

None

C

1^Note

1

RLCA [m]

RLC [m]

Rotate Data Memory left through Carry with result in ACC

Rotate Data Memory left through Carry

1^Note

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move Data Memory to ACC

Move ACC to Data Memory

Move immediate data to ACC

1

1^Note

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of Data Memory

Set bit of Data Memory

1^Note

None

Branch

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if Data Memory is zero

1^Note

1^note

1^Note

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if Data Memory is zero with data movement to ACC

Skip if bit i of Data Memory is zero

Skip if bit i of Data Memory is not zero

Skip if increment Data Memory is zero

Skip if decrement Data Memory is zero

Skip if increment Data Memory is zero with result in ACC

Skip if decrement Data Memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC [m]

TABRDL [m]

Read table (current page) to TBLH and Data Memory

Read table (last page) to TBLH and Data Memory

2^Note

None

Miscellaneous

NOP

No operation

1

1^Note

1

None

CLR [m]

Clear Data Memory

SET [m]

Set Data Memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO, PDF

None

Pre-clear Watchdog Timer

Swap nibbles of Data Memory

Swap nibbles of Data Memory with result in ACC

Enter power down mode

1

1^Note

1

None

1

TO, PDF

Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,

if no skip takes place only one cycle is required.

2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.

3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by

the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and

²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags

remain unchanged.

Rev. 1.20

41

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Instruction Definition

ADC A,[m]

Add Data Memory to ACC with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the Accumulator.

Operation

ACC ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADCM A,[m]

Add ACC to Data Memory with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADD A,[m]

Add Data Memory to ACC

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

ADD A,x

Add immediate data to ACC

Description

The contents of the Accumulator and the specified immediate data are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + x

Affected flag(s)

OV, Z, AC, C

ADDM A,[m]

Add ACC to Data Memory

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

AND A,[m]

Logical AND Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

Z

AND A,x

Logical AND immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical AND

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

Z

ANDM A,[m]

Logical AND ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

Z

Rev. 1.20

42

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

CALL addr

Subroutine call

Description

Unconditionally calls a subroutine at the specified address. The Program Counter then in-

crements by 1 to obtain the address of the next instruction which is then pushed onto the

stack. The specified address is then loaded and the program continues execution from this

new address. As this instruction requires an additional operation, it is a two cycle instruc-

tion.

Operation

Stack ¬ Program Counter + 1

Program Counter ¬ addr

Affected flag(s)

None

CLR [m]

Clear Data Memory

Description

Operation

Each bit of the specified Data Memory is cleared to 0.

[m] ¬ 00H

Affected flag(s)

None

CLR [m].i

Clear bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

None

CLR WDT

Description

Operation

Clear Watchdog Timer

The TO, PDF flags and the WDT are all cleared.

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT1

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT2 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT2

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT1 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

Rev. 1.20

43

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

CPL [m]

Complement Data Memory

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa.

Operation

[m] ¬ [m]

Affected flag(s)

Z

CPLA [m]

Complement Data Memory with result in ACC

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa. The complemented result

is stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

Z

DAA [m]

Decimal-Adjust ACC for addition with result in Data Memory

Description

Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-

sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or

if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble

remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of

6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-

ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C

flag may be affected by this instruction which indicates that if the original BCD sum is

greater than 100, it allows multiple precision decimal addition.

Operation

[m] ¬ ACC + 00H or

[m] ¬ ACC + 06H or

[m] ¬ ACC + 60H or

[m] ¬ ACC + 66H

Affected flag(s)

C

DEC [m]

Decrement Data Memory

Description

Operation

Data in the specified Data Memory is decremented by 1.

[m] ¬ [m] - 1

Affected flag(s)

Z

DECA [m]

Decrement Data Memory with result in ACC

Description

Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-

mulator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] - 1

Affected flag(s)

Z

HALT

Enter power down mode

Description

This instruction stops the program execution and turns off the system clock. The contents

of the Data Memory and registers are retained. The WDT and prescaler are cleared. The

power down flag PDF is set and the WDT time-out flag TO is cleared.

Operation

TO ¬ 0

PDF ¬ 1

Affected flag(s)

TO, PDF

Rev. 1.20

44

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

INC [m]

Increment Data Memory

Description

Operation

Data in the specified Data Memory is incremented by 1.

[m] ¬ [m] + 1

Affected flag(s)

Z

INCA [m]

Increment Data Memory with result in ACC

Description

Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-

lator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] + 1

Affected flag(s)

Z

JMP addr

Jump unconditionally

Description

The contents of the Program Counter are replaced with the specified address. Program

execution then continues from this new address. As this requires the insertion of a dummy

instruction while the new address is loaded, it is a two cycle instruction.

Operation

Program Counter ¬ addr

Affected flag(s)

None

MOV A,[m]

Description

Operation

Move Data Memory to ACC

The contents of the specified Data Memory are copied to the Accumulator.

ACC ¬ [m]

Affected flag(s)

None

MOV A,x

Move immediate data to ACC

Description

Operation

The immediate data specified is loaded into the Accumulator.

ACC ¬ x

Affected flag(s)

None

MOV [m],A

Description

Operation

Move ACC to Data Memory

The contents of the Accumulator are copied to the specified Data Memory.

[m] ¬ ACC

Affected flag(s)

None

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

No operation

None

OR A,[m]

Logical OR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-

ation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

Z

Rev. 1.20

45

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

OR A,x

Logical OR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

Z

ORM A,[m]

Logical OR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-

ation. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²OR² [m]

Affected flag(s)

Z

RET

Return from subroutine

Description

The Program Counter is restored from the stack. Program execution continues at the re-

stored address.

Operation

Program Counter ¬ Stack

Affected flag(s)

None

RET A,x

Return from subroutine and load immediate data to ACC

Description

The Program Counter is restored from the stack and the Accumulator loaded with the

specified immediate data. Program execution continues at the restored address.

Operation

Program Counter ¬ Stack

ACC ¬ x

Affected flag(s)

None

RETI

Return from interrupt

Description

The Program Counter is restored from the stack and the interrupts are re-enabled by set-

ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending

when the RETI instruction is executed, the pending Interrupt routine will be processed be-

fore returning to the main program.

Operation

Program Counter ¬ Stack

EMI ¬ 1

Affected flag(s)

None

RL [m]

Rotate Data Memory left

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ [m].7

Affected flag(s)

None

RLA [m]

Rotate Data Memory left with result in ACC

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-

main unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ [m].7

Affected flag(s)

None

Rev. 1.20

46

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

RLC [m]

Rotate Data Memory left through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7

replaces the Carry bit and the original carry flag is rotated into bit 0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RLCA [m]

Rotate Data Memory left through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces

the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in

the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RR [m]

Rotate Data Memory right

Description

The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into

bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ [m].0

Affected flag(s)

None

RRA [m]

Rotate Data Memory right with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-

tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data

Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ [m].0

Affected flag(s)

None

RRC [m]

Rotate Data Memory right through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0

replaces the Carry bit and the original carry flag is rotated into bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

C

RRCA [m]

Rotate Data Memory right through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-

places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is

stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

C

Rev. 1.20

47

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

SBC A,[m]

Subtract Data Memory from ACC with Carry

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result

of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or

zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SBCM A,[m]

Subtract Data Memory from ACC with Carry and result in Data Memory

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-

sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is

positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SDZ [m]

Skip if decrement Data Memory is 0

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0 the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] - 1

Skip if [m] = 0

Affected flag(s)

None

SDZA [m]

Skip if decrement Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0, the program proceeds with the following instruction.

Operation

ACC ¬ [m] - 1

Skip if ACC = 0

Affected flag(s)

None

SET [m]

Set Data Memory

Description

Operation

Each bit of the specified Data Memory is set to 1.

[m] ¬ FFH

Affected flag(s)

None

SET [m].i

Set bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is set to 1.

[m].i ¬ 1

Affected flag(s)

None

Rev. 1.20

48

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

SIZ [m]

Skip if increment Data Memory is 0

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] + 1

Skip if [m] = 0

Affected flag(s)

None

SIZA [m]

Skip if increment Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0 the program proceeds with the following instruction.

Operation

ACC ¬ [m] + 1

Skip if ACC = 0

Affected flag(s)

None

SNZ [m].i

Skip if bit i of Data Memory is not 0

Description

If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is 0 the program proceeds with the following instruction.

Operation

Skip if [m].i ¹ 0

Affected flag(s)

None

SUB A,[m]

Subtract Data Memory from ACC

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUBM A,[m]

Subtract Data Memory from ACC with result in Data Memory

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUB A,x

Subtract immediate data from ACC

Description

The immediate data specified by the code is subtracted from the contents of the Accumu-

lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-

tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will

be set to 1.

Operation

ACC ¬ ACC - x

Affected flag(s)

OV, Z, AC, C

Rev. 1.20

49

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

SWAP [m]

Description

Operation

Swap nibbles of Data Memory

The low-order and high-order nibbles of the specified Data Memory are interchanged.

[m].3~[m].0 « [m].7 ~ [m].4

Affected flag(s)

None

SWAPA [m]

Swap nibbles of Data Memory with result in ACC

Description

The low-order and high-order nibbles of the specified Data Memory are interchanged. The

result is stored in the Accumulator. The contents of the Data Memory remain unchanged.

Operation

ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4

ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0

Affected flag(s)

None

SZ [m]

Skip if Data Memory is 0

Description

If the contents of the specified Data Memory is 0, the following instruction is skipped. As

this requires the insertion of a dummy instruction while the next instruction is fetched, it is a

two cycle instruction. If the result is not 0 the program proceeds with the following instruc-

tion.

Operation

Skip if [m] = 0

None

Affected flag(s)

SZA [m]

Skip if Data Memory is 0 with data movement to ACC

Description

The contents of the specified Data Memory are copied to the Accumulator. If the value is

zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-

tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the

program proceeds with the following instruction.

Operation

ACC ¬ [m]

Skip if [m] = 0

Affected flag(s)

None

SZ [m].i

Skip if bit i of Data Memory is 0

Description

If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is not 0, the program proceeds with the following instruction.

Operation

Skip if [m].i = 0

None

Affected flag(s)

TABRDC [m]

Read table (current page) to TBLH and Data Memory

Description

The low byte of the program code (current page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

TABRDL [m]

Read table (last page) to TBLH and Data Memory

Description

The low byte of the program code (last page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

Rev. 1.20

50

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

XOR A,[m]

Logical XOR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XORM A,[m]

Logical XOR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XOR A,x

Logical XOR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical XOR

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

Z

Rev. 1.20

51

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Package Information

28-pin SSOP (150mil) Outline Dimensions

2

8

1

5

4

A

B

1

C

'

G

H

D

a

E

F

Dimensions in inch

Symbol

Min.

0.228

0.150

0.008

0.386

0.054

¾

Nom.

¾

Max.

0.244

0.157

0.012

0.394

0.060

¾

A

B

C

C¢

D

E

F

¾

0.025

¾

0.004

0.022

0.007

0°

0.010

0.028

0.010

8°

G

H

a

¾

Dimensions in mm

Symbol

Min.

5.79

3.81

0.20

9.80

1.37

¾

Nom.

¾

Max.

6.20

3.99

0.30

10.01

1.52

¾

A

B

C

C¢

D

E

F

¾

0.64

0.10

0.56

0.18

0°

0.25

0.71

0.25

8°

¾

G

H

a

Rev. 1.20

52

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

48-pin SSOP (300mil) Outline Dimensions

4

8

2

5

4

A

B

1

C

'

G

H

D

a

E

F

Dimensions in inch

Symbol

Min.

0.395

0.291

0.008

0.613

0.085

¾

Nom.

¾

Max.

0.420

0.299

0.012

0.637

0.099

¾

A

B

C

C¢

D

E

F

¾

0.025

0.004

0.025

0.004

0°

0.010

0.035

0.012

8°

¾

G

H

a

Dimensions in mm

Symbol

Min.

10.03

7.39

0.20

15.57

2.16

¾

Nom.

¾

Max.

10.67

7.59

0.30

16.18

2.51

¾

A

B

C

C¢

D

E

F

¾

0.64

0.10

0.64

0.10

0°

0.25

0.89

0.30

8°

¾

G

H

a

Rev. 1.20

53

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

SAW Type 32-pin (5mm´ 5mm) QFN Outline Dimensions

D

2

5

3

2

4

1

b

E

2

e

1

7

8

1

6

9

A

1

A

3

L

K

A

Dimensions in inch

Symbol

Min.

0.028

0.000

¾

Nom.

¾

Max.

0.031

0.002

¾

A

A1

A3

b

¾

0.008

0.007

¾

0.012

¾

0.197

0.020

¾

D

E

¾

e

¾

D2

E2

L

0.049

0.012

¾

0.128

0.020

¾

K

¾

Dimensions in mm

Symbol

Min.

0.70

0.00

¾

Nom.

¾

Max.

0.80

0.05

¾

A

A1

A3

b

¾

0.20

0.18

¾

0.30

¾

5.00

0.50

¾

D

E

¾

e

¾

D2

E2

L

1.25

0.30

¾

3.25

0.50

¾

K

¾

Rev. 1.20

54

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

48-pin LQFP (7mm´ 7mm) Outline Dimensions

C

H

D

G

3

6

2

5

I

3

7

2

4

F

A

B

E

4

8

1

3

a

K

J

1

2

Dimensions in inch

Symbol

Min.

0.350

0.272

0.350

0.272

¾

Nom.

¾

Max.

0.358

0.280

0.358

0.280

¾

A

B

C

D

E

F

G

H

I

¾

0.020

0.008

¾

0.053

¾

0.057

0.063

¾

0.004

¾

J

0.018

0.004

0°

0.030

0.008

7°

K

a

¾

Dimensions in mm

Symbol

Min.

8.90

6.90

8.90

6.90

¾

Nom.

¾

Max.

9.10

7.10

9.10

7.10

¾

A

B

C

D

E

F

G

H

I

¾

0.50

0.20

¾

1.35

¾

1.45

1.60

¾

0.10

¾

J

0.45

0.10

0°

0.75

0.20

7°

K

a

¾

Rev. 1.20

55

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Product Tape and Reel Specifications

Reel Dimensions

D

T

2

C

A

B

T

1

SSOP 28S (150mil)

Symbol

Description

Dimensions in mm

330.0±1.0

A

B

Reel Outer Diameter

Reel Inner Diameter

Spindle Hole Diameter

Key Slit Width

100.0±1.5

+0.5/-0.2

13.0

C

D

2.0±0.5

+0.3/-0.2

16.8

T1

T2

Space Between Flange

Reel Thickness

22.2±0.2

SSOP 48W

Symbol

Description

Dimensions in mm

330.0±1.0

A

B

Reel Outer Diameter

Reel Inner Diameter

Spindle Hole Diameter

Key Slit Width

100.0±0.1

+0.5/-0.2

13.0

C

D

2.0±0.5

+0.3/-0.2

32.2

T1

T2

Space Between Flange

Reel Thickness

38.2±0.2

Rev. 1.20

56

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Carrier Tape Dimensions

P

0

P

1

t

D

E

F

W

B

0

C

D

1

P

K

0

A

0

R

e

l

H

o

l

e

I

C

p

a

c

k

a

g

e

p

i

n

1

a

n

d

a

r

e

l

o

c

a

t

e

d

o

n

t

h

e

s

a

SSOP 28S (150mil)

Symbol

Description

Dimensions in mm

16.0±0.3

8.0±0.1

W

P

Carrier Tape Width

Cavity Pitch

E

Perforation Position

1.75±0.1

7.5±0.1

1.55^+0.10/-0.00

1.50^+0.25/-0.00

4.0±0.1

F

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

D

D1

P0

P1

A0

B0

K0

t

Cavity to Perforation (Length Direction)

Cavity Length

2.0±0.1

6.5±0.1

Cavity Width

10.3±0.1

2.1±0.1

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

0.30±0.05

13.3±0.1

C

Rev. 1.20

57

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Carrier Tape Dimensions

P

0

P

1

t

D

E

F

B

0

W

C

K

1

D

1

P

K

2

A

0

R

e

l

H

o

l

e

(

C

i

r

c

l

e

)

I

C

p

a

c

k

a

g

e

p

i

n

1

a

n

d

t

h

e

r

e

a

r

e

l

o

c

a

t

e

d

o

n

t

h

e

s

a

m

e

s

i

d

R

e

l

H

o

l

e

(

E

l

i

p

s

e

)

SSOP 48W

Symbol

Description

Dimensions in mm

32.0±0.3

W

P

Carrier Tape Width

Cavity Pitch

16.0±0.1

E

Perforation Position

1.75±0.10

14.2±0.1

F

Cavity to Perforation (Width Direction)

Perforation Diameter

D

2 Min.

+0.25/-0.00

D1

P0

P1

A0

B0

K1

K2

t

Cavity Hole Diameter

1.50

Perforation Pitch

4.0±0.1

2.0±0.1

Cavity to Perforation (Length Direction)

Cavity Length

12.0±0.1

16.2±0.1

2.4±0.1

Cavity Width

Cavity Depth

3.2±0.1

Carrier Tape Thickness

Cover Tape Width

0.35±0.05

25.5±0.1

C

Rev. 1.20

58

February 1, 2011

HT82K70E-L/HT82K70A-L/HT82K76E-L

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057

Tel: 86-755-8616-9908, 86-755-8616-9308

Fax: 86-755-8616-9722

Holtek Semiconductor (USA), Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538

Tel: 1-510-252-9880

Fax: 1-510-252-9885

http://www.holtek.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 1.20

59

February 1, 2011


型号：	HT82K70A-L
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	I/O Type 8-Bit MCU I / O型8位MCU
文件：	总59页 (文件大小：378K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT82K70A-L [HOLTEK]

相关型号：

HT82K70E-L

HT82K70E-L_11

HT82K74E

HT82K74EE

HT82K75R

HT82K75RE

HT82K75REW

HT82K76E-L

HT82K94A

HT82K94A(40DIP-A)

HT82K94E

HT82K94E(40DIP-A)