HT86BXX_技术文档

HT86BXX/HT86BRXX

Enhanced Voice 8-Bit MCU

Technical Document

·

Application Note

-

HA0075E MCU Reset and Oscillator Circuits Application Note

Features

·

Operating voltage: 2.2V~5.5V

System clock: 4MHz~8MHz

Crystal and RC system oscillator

16/20/24 I/O pins

External RC oscillator converter

8 capacitor/resistor sensor input

Watchdog timer function

8-level subroutine nesting

Low voltage reset function

8K´16-bit Program Memory

192´8/384´8-bit Data Memory

External interrupt input

Integrated voice ROM with various capacities

Power-down function and wake-up feature reduce

power consumption

Three 8-bit programmable Timers with overflow

interrupt and 8-stage prescaler

·

Up to 0.5ms instruction cycle with 8MHz system clock

at V_DD= 5V

·

12-bit high quality voltage type D/A output

PWM circuit direct audio output

63 powerful instructions

General Description

The Voice type series of MCUs are 8-bit high perfor-

mance microcontrollers which include a voice synthe-

sizer and tone generator. They are designed for

applications which require multiple I/Os and sound ef-

fects, such as voice and melody. The devices can pro-

vide various sampling rates and beats, tone levels,

tempos for speech synthesizer and melody generator.

They also include an integrated high quality, voltage

type DAC output. The external interrupt can be trig-

gered with falling edges or both falling and rising edges.

The devices are excellent solutions for versatile voice

and sound effect product applications with their efficient

MCU instructions providing the user with programming

capability for powerful custom applications. The system

frequency can be up to 8MHz at an operating voltage of

2.2V and include a power-down function to reduce

power consumption.

Rev. 1.60

1

October 20, 2009

HT86BXX/HT86BRXX

Device Types

Devices which have the letter ²BR² within their part number, indicate that they are OTP devices offering the advantages

of easy and effective program updates, using the Holtek range of development and programming tools. These devices

provide the designer with the means for fast and low-cost product development cycles. Devices which have the letter

²B² within their part number indicate that they are mask version devices. These devices offer a complementary device

for applications that are at a mature state in their design process and have high volume and low cost demands.

Part numbers including ²R² are OTP devices, all others are mask version devices.

Fully pin and functionally compatible with their OTP sister devices, the mask version devices provide the ideal substi-

tute for products which have gone beyond their development cycle and are facing cost-down demands.

In this datasheet, for convenience, when describing device functions, only the OTP types are mentioned by name,

however the same described functions also apply to the Mask type devices.

Selection Table

The devices include a comprehensive range of features, with most features common to all devices. The main features

distinguishing them are Program Memory and Data Memory capacity, Voice ROM and Voice capacity, I/O count, stack

size and package types. The functional differences between the devices are shown in the following table.

Timer

Program

Data

Voice

Part No.

VDD

I/O

C/R-F D/A Stack Package Types

Memory Memory ROM Capacity

8-bit 16-bit

24SSOP

HT86B05 2.2V~5.5V 8K´16

192´8

96K´8

36sec

16

3

¾

12-bit

8

(150/209mil),

28SOP, 44QFP

24SSOP(209mil),

28SOP, 44QFP

HT86BR10

2.2V~5.5V 8K´16

192´8 192K´8

192´8 256K´8

72sec

96sec

16

3

24SSOP

HT86B10

(150/209mil),

28SOP, 44QFP

HT86B20 2.2V~5.5V 8K´16

16

3

¾

12-bit

8

28SOP, 44QFP

HT86BR30

2.2V~5.5V 8K´16

192´8 384K´8 144sec

HT86B30

HT86B40 2.2V~5.5V 8K´16

HT86B50 2.2V~5.5V 8K´16

384´8 512K´8 192sec

384´8 768K´8 288sec

20

3

1

Ö

12-bit

8

28SOP, 44QFP

28SOP

HT86BR60

2.2V~5.5V 8K´16

384´8 1024K´8 384sec

20

3

1

Ö

12-bit

8

HT86B60

28SOP, 44QFP

44/100QFP

100QFP

HT86B70 2.2V~5.5V 8K´16

HT86B80 2.2V~5.5V 8K´16

HT86B90 2.2V~5.5V 8K´16

384´8 1536K´8 576sec

384´8 2048K´8 768sec

24

3

1

Ö

12-bit

8

384´8 3072K´8 1152sec 24

Note: 1. For devices that exist in more than one package formats, the table reflects the situation for the larger

package.

2. For the HT86B90, the operating voltage is 2.2V~5.5V at f_SYS=4MHz/3.3V~5.5V at f_SYS=8MHz.

3. Voice length is estimated by 21K-bit data rate

Rev. 1.60

2

October 20, 2009

HT86BXX/HT86BRXX

Block Diagram

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Rev. 1.60

3

October 20, 2009

HT86BXX/HT86BRXX

Pad Assignment

HT86BR10

P

A

7

1

3

4

V

S

P

(

0

,

0

)

3

2

V

P

S

W

S

P

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2

1

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6

5

4

3

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1

2

1

3

1

4

1

8

1

5

1

9

1

6

1

7

2

0

2

1

3

Chip size: 3265´4010 (mm)²

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.60

4

October 20, 2009

HT86BXX/HT86BRXX

HT86B05/HT86B10

3

2

V

P

S

W

S

P

(

0

,

0

)

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2

1

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A

B

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6

5

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3

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4

1

5

1

8

1

6

1

9

1

7

2

0

1

2

3

2

4

Chip size: 1975´2640 (mm)²

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.60

5

October 20, 2009

HT86BXX/HT86BRXX

HT86BR30

(

0

,

0

)

3

2

V

P

S

W

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1

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6

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4

1

5

1

7

1

8

1

9

2

5

1

Chip size: 4280´4330 (mm)²

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.60

6

October 20, 2009

HT86BXX/HT86BRXX

HT86B20/HT86B30

(

0

,

0

)

3

V

P

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6

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8

1

7

9

2

0

2

1

2

4

3

Chip size: 1975´3300 (mm)²

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.60

7

October 20, 2009

HT86BXX/HT86BRXX

HT86B40

(

0

,

0

)

3

7

V

P

S

W

S

P

3

6

M

2

1

2

3

4

5

6

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8

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9

1

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2

1

3

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4

1

5

6

1

8

2

4

3

1

7

1

9

2

0

2

1

2

1

2

6

2

7

8

2

5

Chip size: 1975´3970 (mm)²

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.60

8

October 20, 2009

HT86BXX/HT86BRXX

HT86BR60

(

0

,

0

)

3

7

6

V

P

S

W

S

P

A

7

M

2

1

P

A

B

6

5

4

3

2

1

0

1

2

3

5

4

P

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W

D

4

5

D

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A

3

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A

D

U

D

6

7

3

2

3

1

V

S

A

8

9

3

0

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S

C

2

1

0

1

2

3

2

5

4

2

9

1

2

1

3

1

4

6

1

5

7

1

8

1

9

2

0

2

1

2

6

2

7

8

S

C

1

Chip size: 4290´8835 (mm)²

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.60

9

October 20, 2009

HT86BXX/HT86BRXX

HT86B50/HT86B60

(

0

,

0

)

3

7

V

P

S

W

S

P

3

6

M

2

1

P

A

B

7

6

5

4

3

2

1

0

1

2

3

5

P

V

W

D

3

4

5

6

7

8

9

3

4

D

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3

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A

D

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D

3

2

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1

V

S

A

3

0

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2

9

S

C

1

0

1

2

1

3

4

1

6

5

1

7

1

8

9

2

0

2

1

2

3

2

4

6

2

1

2

5

2

8

7

Chip size: 1975´5725 (mm)²

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.60

10

October 20, 2009

HT86BXX/HT86BRXX

HT86B70/HT86B80

(

0

,

0

)

4

1

0

V

P

S

W

S

P

A

B

7

6

5

4

3

2

1

0

1

2

1

2

3

4

5

6

7

8

9

M

2

1

3

9

8

P

W

V

D

P

3

7

A

3

6

A

V

U

S

D

3

5

S

A

1

0

3

4

O

S

C

2

1

2

1

3

1

4

1

5

9

1

2

6

2

0

2

1

2

7

2

1

2

3

1

5

8

2

4

7

2

6

8

2 9

3

0

3

1

3

2

1

3

S

C

1

Chip size: 3615´4940 (mm)²

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.60

11

October 20, 2009

HT86BXX/HT86BRXX

HT86B90

(

0

,

0

)

4

1

V

P

S

W

S

P

A

B

7

6

5

4

3

2

1

0

1

2

1

2

3

4

5

6

7

8

9

4

0

M

2

1

P

W

3

9

8

V

D

P

A

3

7

A

O

U

D

3

6

3

5

S

C

2

1

V

O

S

A

3

4

1

0

1

2

1

3

1

6

4

1

7

5

1

8

2

1

2

9

2

3

0

5

2

4

7

1

2

6

8

3

0

1

3

2

9

3

1

Chip size: 3620´6700 (mm)²

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.60

12

October 20, 2009

HT86BXX/HT86BRXX

Pad Coordinates

HT86BR10

Unit: mm

Pad No.

X

Y

Pad No.

X

Y

1

2

1900.000

-838.050

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

-1483.900

-1474.850

-1379.850

-1276.850

-1181.850

-1078.850

-983.850

-779.500

-682.500

-521.245

-447.245

-373.245

-299.245

1478.900

1442.800

1439.405

1442.395

1468.400

-1856.400

-1860.845

-1821.650

-1700.550

-1605.550

-1497.530

-1395.130

-1295.470

-1162.343

-1024.550

-814.050

3

-933.050

4

-1036.050

-1131.050

-1234.050

-1329.050

-1432.050

-1527.050

-1630.050

-1856.400

5

6

7

8

9

10

11

12

13

14

15

16

17

-683.200

1879.850

-881.645

HT86B05/HT86B10

Pad No.

Unit: mm

X

Y

Pad No.

X

Y

1

2

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

-839.400

-632.150

-537.150

-434.150

-339.150

-236.150

-141.150

-189.100

-284.100

-387.100

-482.100

-585.100

-680.100

-783.100

-878.100

-981.100

-1076.100

-1179.100

-1171.900

-45.150

50.850

-1171.900

-1188.650

-945.650

-843.250

-704.400

-601.500

-504.300

-351.400

-218.050

-7.550

3

153.850

294.450

368.450

442.450

516.450

838.940

802.900

792.250

803.900

4

5

6

7

8

9

10

11

12

13

14

15

16

17

112.000

Rev. 1.60

13

October 20, 2009

HT86BXX/HT86BRXX

HT86BR30

Pad No.

Unit: mm

X

Y

Pad No.

X

Y

1

2

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

-1991.400

-1771.750

-1668.750

-1573.750

-1470.750

-1375.750

-1251.695

-1030.120

-1133.120

-1228.120

-1331.120

-1426.120

-1529.120

-1624.120

-1727.120

-1822.120

-1925.120

-2020.120

-2016.400

-2016.780

-1152.895

-1055.695

-913.745

-709.506

-635.506

-561.506

-487.506

1984.750

1941.835

1946.850

-2016.400

-2015.810

-2016.500

-1921.500

-1711.230

-1586.960

-1487.300

-1363.920

-1233.070

-1022.570

-891.720

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

HT86B20/HT86B30

Pad No.

Unit: mm

X

Y

Pad No.

X

Y

1

2

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

-839.400

-632.150

-537.150

-434.150

-339.150

-236.150

-141.150

-519.100

-614.100

-717.100

-812.100

-915.100

-1010.100

-1113.100

-1208.100

-1311.100

-1406.100

-1509.100

-1501.900

-45.150

50.850

-1501.900

-1518.650

-1275.650

-1173.250

-1034.400

-931.500

-834.300

-681.400

-548.050

-337.550

-218.000

3

153.850

294.450

368.450

442.450

516.450

838.940

802.900

792.250

803.900

4

5

6

7

8

9

10

11

12

13

14

15

16

17

Rev. 1.60

14

October 20, 2009

HT86BXX/HT86BRXX

HT86B40

Pad No.

Unit: mm

X

Y

Pad No.

X

Y

1

2

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

44.500

149.650

255.250

359.150

462.150

619.850

693.850

767.850

841.850

839.390

802.900

792.350

803.900

-839.400

-848.700

-745.700

-650.700

-547.700

-452.700

-349.700

-254.700

-153.500

-50.500

-701.930

-804.930

-1836.900

-1853.600

-1551.700

-1449.300

-1311.300

-1207.800

-1103.500

-959.450

3

-899.930

4

-1002.930

-1097.930

-1200.930

-1295.930

-1398.930

-1493.930

-1596.930

-1836.900

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

-829.350

-618.850

-499.300

HT86BR60

Unit: mm

Pad No.

X

Y

Pad No.

X

Y

1

2

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

954.350

853.150

753.150

657.150

515.200

345.100

271.100

197.100

123.100

1991.750

1948.850

1953.850

-1996.400

-1750.825

-1655.825

-1552.825

-1457.825

-1354.825

-1259.825

-1152.350

-1049.350

-3279.080

-3382.080

-3477.080

-3580.080

-3675.080

-3778.080

-3873.080

-3976.080

-4074.580

-4177.580

-4272.580

-4269.280

-4268.900

-4268.850

-4269.000

-4174.000

-3963.730

-3839.460

-3739.800

-3616.420

-3485.570

-3275.070

-3144.220

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

Rev. 1.60

15

October 20, 2009

HT86BXX/HT86BRXX

HT86B50/HT86B60

Pad No.

Unit: mm

X

Y

Pad No.

X

Y

1

2

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

44.600

149.650

255.250

359.150

462.150

619.850

693.850

767.850

841.850

839.390

802.900

792.350

803.900

-839.400

-848.700

-745.700

-650.700

-547.700

-452.700

-349.700

-254.700

-153.400

-50.400

-1579.430

-1682.430

-1777.430

-1880.430

-1975.430

-2078.430

-2173.430

-2276.430

-2371.430

-2474.430

-2714.400

-2731.100

-2427.100

-2326.800

-2188.800

-2085.300

-1981.000

-1836.950

-1706.850

-1496.350

-1376.800

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

HT86B70/HT86B80

Pad No.

Unit: mm

X

Y

Pad No.

X

Y

1

2

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

-1659.400

-1419.255

-1324.255

-1221.255

-1126.255

-1023.255

-928.255

-1342.900

-1437.900

-1540.900

-1635.900

-1738.900

-1833.900

-1936.900

-2031.900

-2134.900

-2229.900

-2332.900

-2321.900

-431.055

-328.055

-233.055

-130.855

-32.865

67.140

-2321.900

-2327.150

-2324.995

-2229.995

-2087.795

-1979.695

-1869.845

-1774.245

-1640.895

-1430.395

-1310.845

3

4

5

6

7

170.140

332.095

406.095

480.095

554.095

1658.950

1576.095

1495.595

1623.910

8

9

10

11

12

13

14

15

16

17

18

19

20

21

-825.255

-730.255

-627.255

-532.255

Rev. 1.60

16

October 20, 2009

HT86BXX/HT86BRXX

HT86B90

Pad No.

Unit: mm

X

Y

Pad No.

X

Y

1

2

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

-1661.900

-1421.755

-1326.755

-1223.755

-1128.755

-1025.755

-930.755

-2222.900

-2317.900

-2420.900

-2515.900

-2618.900

-2713.900

-2816.900

-2911.900

-3014.900

-3109.900

-3212.900

-3201.900

-433.555

-330.555

-235.555

-133.355

-35.365

64.640

-3201.900

-3207.150

-3204.995

-2859.695

-2967.795

-3109.995

-2749.845

-2654.245

-2520.895

-2310.395

-2190.845

3

4

5

6

7

167.640

329.595

403.595

477.595

551.595

1656.900

1493.095

1573.595

1656.900

1493.095

1621.410

8

9

10

11

12

13

14

15

16

17

18

19

20

21

-827.755

-732.755

-629.755

-534.755

Pin Description

HT86B05/HT86B10/HT86B20/HT86B30/HT86BR10/HT86BR30

Pad Name

I/O

Options

Description

Wake-up,

Pull-high

or None

Bi-directional 8-bit I/O port. Software instructions determined the CMOS out-

put or Schmitt trigger with a pull-high resistor (determined by option).

PA0~PA7

I/O

Pull-high

or None

Bi-directional 8-bit I/O port. Software instructions determined the CMOS out-

put or Schmitt trigger with a pull-high resistor (determined by option).

PB0~PB7

AUD

I/O

O

I

Audio output for driving an external transistor or for driving HT82V733

Audio PWM outputs

¾

PWM1

PWM2

RES

Schmitt trigger reset input. Active low.

External interrupt Schmitt trigger input without pull-high resistor. A configura-

tion option determines if the interrupt active edge is a falling edge only or both

a falling and rising edge. Falling edge triggered active on a high to low transi-

tion. Rising edge triggered active on a low to high transition. Input voltage is

the same as operating voltage.

Falling Edge

Trigger or

INT

I

Falling/Rising

Edge Trigger

OSC1, OSC2 are connected to an external RC network or external crystal,

determined by configuration option, for the internal system clock. If the RC

system clock option is selected, pin OSC2 can be used to measure the sys-

tem clock at 1/4 frequency.

OSC1

OSC2

Crystal or RC

¾

VDD

Positive digital power supply

¾

VSS

Negative digital power supply, ground.

Positive DAC circuit power supply

Negative DAC circuit power supply, ground.

VDDA

VSSA

Rev. 1.60

17

October 20, 2009

HT86BXX/HT86BRXX

Pad Name

VDDP

I/O

¾

Options

Description

Positive audio PWM circuit power supply

Negative audio PWM circuit power supply, ground.

¾

VSSP

¾

Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins can be selected to have pull-high resistors.

HT86B40/HT86B50/HT86B60/HT86BR60

Pad Name

I/O

Options

Description

Wake-up,

Pull-high

or None

Bi-directional 8-bit I/O port. Software instructions determined the CMOS out-

put or Schmitt trigger with a pull-high resistor (determined by option).

PA0~PA7

I/O

Bi-directional 8-bit I/O port. Software instructions determined the CMOS out-

put or Schmitt trigger with a pull-high resistor (determined by option).

Pins PB0~PB7 are pin-shared with C/R-F input pins K0~K7.

PB0~PB7/

K0~K7

Pull-high

or None

I/O

Bi-directional 4-bit I/O port. Software instructions determined the CMOS out-

put or Schmitt trigger with a pull-high resistor (determined by option).

Pins PD4~PD7 are pin-shared with R/F OSC input pins RR, RC and CC.

RCOUT: Capacitor or resistor connection pin to RC OSC for input.

RR: Oscillation input pin

PD4/RCOUT

PD5/RR

Pull-high

or None

PD6/RC

PD7/CC

RC: Reference resistor connection pin for output

CC: Reference capacitor connection pin for output

AUD

O

I

Audio output for driving an external transistor or for driving HT82V733

Audio PWM outputs

¾

PWM1

PWM2

RES

Schmitt trigger reset input. Active low.

External interrupt Schmitt trigger input without pull-high resistor. A configura-

tion option determines if the interrupt active edge is a falling edge only or both

a falling and rising edge. Falling edge triggered active on a high to low transi-

tion. Rising edge triggered active on a low to high transition. Input voltage is

the same as operating voltage.

Falling Edge

Trigger or

INT

I

Falling/Rising

Edge Trigger

OSC1, OSC2 are connected to an external RC network or external crystal,

determined by configuration option, for the internal system clock. If the RC

system clock option is selected, pin OSC2 can be used to measure the sys-

tem clock at 1/4 frequency.

OSC1

OSC2

Crystal or RC

¾

VDD

Positive digital power supply

¾

VSS

Negative digital power supply, ground.

Positive DAC circuit power supply

VDDA

VSSA

VDDP

VSSP

Negative DAC circuit power supply, ground.

Positive audio PWM circuit power supply

Negative audio PWM circuit power supply, ground.

Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins can be selected to have pull-high resistors.

Rev. 1.60

18

October 20, 2009

HT86BXX/HT86BRXX

HT86B70/HT86B80/HT86B90

Pad Name

I/O

Options

Description

Wake-up,

Pull-high

or None

Bi-directional 8-bit I/O port. Software instructions determined the CMOS out-

put or Schmitt trigger with a pull-high resistor (determined by option).

PA0~PA7

I/O

Bi-directional 8-bit I/O port. Software instructions determined the CMOS out-

put or Schmitt trigger with a pull-high resistor (determined by option).

Pins PB0~PB7 are pin-shared with C/R-F input pins K0~K7.

PB0~PB7/

K0~K7

Pull-high

or None

I/O

Bi-directional 8-bit I/O port. Software instructions determined the CMOS out-

put or Schmitt trigger with a pull-high resistor (determined by option).

Pins PD4~PD7 are pin-shared with R/F OSC input pins RR, RC and CC.

RCOUT: Capacitor or resistor connection pin to RC OSC for input.

RR: Oscillation input pin

PD0~PD3

PD4/RCOUT

PD5/RR

Pull-high

or None

PD6/RC

PD7/CC

RC: Reference resistor connection pin for output

CC: Reference capacitor connection pin for output

AUD

O

I

Audio output for driving an external transistor or for driving HT82V733

Audio PWM outputs

¾

PWM1

PWM2

RES

Schmitt trigger reset input. Active low.

External interrupt Schmitt trigger input without pull-high resistor. A configura-

tion option determines if the interrupt active edge is a falling edge only or both

a falling and rising edge. Falling edge triggered active on a high to low transi-

tion. Rising edge triggered active on a low to high transition. Input voltage is

the same as operating voltage.

Falling Edge

Trigger or

INT

I

Falling/Rising

Edge Trigger

OSC1, OSC2 are connected to an external RC network or external crystal,

determined by configuration option, for the internal system clock. If the RC

system clock option is selected, pin OSC2 can be used to measure the sys-

tem clock at 1/4 frequency.

OSC1

OSC2

Crystal or RC

¾

VDD

Positive digital power supply

¾

VSS

Negative digital power supply, ground.

Positive DAC circuit power supply

VDDA

VSSA

VDDP

VSSP

Negative DAC circuit power supply, ground.

Positive audio PWM circuit power supply

Negative audio PWM circuit power supply, ground.

Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins can be selected to have pull-high resistors.

Absolute Maximum Ratings

Supply Voltage...........................V_SS+2.2V to V_SS+5.5V

Storage Temperature............................-50°C to 125°C

Input Voltage..............................V_SS-0.3V to V_DD+0.3V

_OLTotal ..............................................................150mA

Total Power Dissipation .....................................500mW

Operating Temperature...........................-40°C to 85°C

_OHTotal............................................................-100mA

I

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed

in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

Rev. 1.60

19

October 20, 2009

HT86BXX/HT86BRXX

D.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

f_SYS=4MHz/8MHz

2.2

5.5

V

¾

f_SYS=4MHz

V_DD

Operating Voltage

¾

for HT86B90 only

f

_SYS=8MHz

3.3

5.5

V

¾

for HT86B90 only

3V

5V

3V

5V

3V

5V

3V

5V

¾

1.5

5

mA

V

¾

2.2

¾

60

30

No load, f_SYS=4MHz,

DAC/PWM disable

I_DD

Operating Current

3

¾

No load, f_SYS=8MHz,

DAC/PWM disable

7

¾

1

¾

No load, system HALT

WDT disable

I_STB1

Standby Current (WDT Off)

Standby Current (WDT On)

2

¾

7

¾

No load, system HALT

WDT enable

I_STB2

10

¾

V_IL1

V_IH1

V_IL2

V_IH2

V_IL3

V_IH3

V_LVR

0.3V_DD

V_DD

0.4V_DD

V_DD

0.3V_DD

V_DD

2.3

¾

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Input Low Voltage (RES)

0

¾

0.7V_DD

0

V

¾

V

¾

0.9V_DD

0

Input High Voltage (RES)

Input Low Voltage for EXT INT

Input High Voltage for EXT INT

Low Voltage Reset

V

¾

V

¾

0.7V_DD

2.1

4

V

¾

LVR 2.2V option

V

¾

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

mA

kW

I_OL1

I_OH1

I_OL2

I_OH2

I_OL3

I_OH3

I_AUD

R_PH

V_OL=0.1V_DD

V_OH=0.9V_DD

V_OL=0.1V_DD

V_OH=0.9V_DD

V_OL=0.1V_DD

V_OH=0.9V_DD

¾

I/O Port Sink Current

10

¾

-2

¾

I/O Port Source Current

RC and CC Sink Current

RC and CC Source Current

PWM1/PWM2 Sink Current

PWM1/PWM2 Source Current

AUD Source Current

-5

¾

4

¾

10

¾

-2

¾

-5

¾

50

¾

80

¾

-14.5

-26

-1.5

-3

¾

20

100

50

Pull-high Resistance

10

Rev. 1.60

20

October 20, 2009

HT86BXX/HT86BRXX

A.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

System Clock

f_SYS

2.2V~5.5V

4

8

MHz

¾

(RC OSC, Crystal OSC)

3V

5V

¾

45

32

1

90

65

180

130

¾

ms

t_WDTOSC

Watchdog Oscillator Period

¾

t_RES

t_SST

t_LVR

t_INT

External Reset Low Pulse Width

System Start-up Timer Period

Low Voltage Reset Time

Interrupt Pulse Width

¾

ms

*t_SYS

Wake-up from HALT

1024

¾

2

¾

ms

¾

1

¾

ms

Circumscribe Memory Access

Time

t_MAT

2.2V~5.5V

400

ns

¾

Note: *t_SYS=1/f_SYS

Characteristics Curves

HT86BRxx

·

R vs. F Chart Characteristics Curves

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Rev. 1.60

21

October 20, 2009

HT86BXX/HT86BRXX

·

V vs. F Chart Characteristics Curves - 3.0V

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HT86Bxx

·

R vs. F Chart Characteristics Curves

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Rev. 1.60

22

October 20, 2009

HT86BXX/HT86BRXX

·

T vs. F Chart Characteristics Curves

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Rev. 1.60

23

October 20, 2009

HT86BXX/HT86BRXX

System Architecture

A key factor in the high-performance features of the

Holtek range of Voice microcontrollers is attributed to

the internal system architecture. The range of devices

take advantage of the usual features found within RISC

microcontrollers providing increased speed of operation

and enhanced performance. The pipelining scheme is

implemented in such a way that instruction fetching and

instruction execution are overlapped, hence instructions

are effectively executed in one cycle, with the exception

of branch or call instructions. An 8-bit wide ALU is used

in practically all operations of the instruction set. It car-

ries out arithmetic operations, logic operations, rotation,

increment, decrement, branch decisions, etc. The inter-

nal data path is simplified by moving data through the

Accumulator and the ALU. Certain internal registers are

implemented in the Data Memory and can be directly or

indirectly addressed. The simple addressing methods of

these registers along with additional architectural fea-

tures ensure that a minimum of external components is

required to provide a functional I/O, voltage type DAC,

PWM direct drive output, capacitor/resistor sensor input

and external RC oscillator converter with maximum reli-

ability and flexibility.

nally generated non-overlapping clocks, T1~T4. The

Program Counter is incremented at the beginning of the

T1 clock during which time a new instruction is fetched.

The remaining T2~T4 clocks carry out the decoding and

execution functions. In this way, one T1~T4 clock cycle

forms one instruction cycle. Although the fetching and

execution of instructions takes place in consecutive in-

struction cycles, the pipelining structure of the

microcontroller ensures that instructions are effectively

executed in one instruction cycle. The exception to this

are instructions where the contents of the Program

Counter are changed, such as subroutine calls or

jumps, in which case the instruction will take one more

instruction cycle to execute.

When the RC oscillator is used, OSC2 is freed for use as

a T1 phase clock synchronizing pin. This T1 phase clock

has a frequency of f_SYS/4 with a 1:3 high/low duty cycle.

For instructions involving branches, such as jump or call

instructions, two machine cycles are required to com-

plete instruction execution. An extra cycle is required as

the program takes one cycle to first obtain the actual

jump or call address and then another cycle to actually

execute the branch. The requirement for this extra cycle

should be taken into account by programmers in timing

sensitive applications.

Clocking and Pipelining

The main system clock, derived from either a Crystal/

Resonator or RC oscillator is subdivided into four inter-

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Instruction Fetching

Rev. 1.60

24

October 20, 2009

HT86BXX/HT86BRXX

Program Counter

The lower byte of the Program Counter is fully accessi-

ble under program control. Manipulating the PCL might

cause program branching, so an extra cycle is needed

to pre-fetch. Further information on the PCL register can

be found in the Special Function Register section.

During program execution, the Program Counter is used

to keep track of the address of the next instruction to be

executed. It is automatically incremented by one each

time an instruction is executed except for instructions,

such as ²JMP² or ²CALL², that demand a jump to a

non-consecutive Program Memory address. Note that

the Program Counter width varies with the Program

Memory capacity depending upon which device is se-

lected. However, it must be noted that only the lower 8

bits, known as the Program Counter Low Register, are

directly addressable by user.

Stack

This is a special part of the memory which is used to

save the contents of the Program Counter only. The

stack has 8 levels and is neither part of the data nor part

of the program space, and is neither readable nor

writable. The activated level is indexed by the Stack

Pointer, SP, and is neither readable nor writable. At a

subroutine call or interrupt acknowledge signal, the con-

tents of the Program Counter are pushed onto the stack.

At the end of a subroutine or an interrupt routine, sig-

naled by a return instruction, ²RET² or ²RETI², the Pro-

gram Counter is restored to its previous value from the

stack. After a device reset, the Stack Pointer will point to

the top of the stack.

When executing instructions requiring jumps to

non-consecutive addresses such as a jump instruction,

a subroutine call, interrupt or reset, etc., the

microcontroller manages program control by loading the

required address into the Program Counter. For condi-

tional skip instructions, once the condition has been

met, the next instruction, which has already been

fetched during the present instruction execution, is dis-

carded and a dummy cycle takes its place while the cor-

rect instruction is obtained.

P

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The lower byte of the Program Counter, known as the

Program Counter Low register or PCL, is available for

program control and is a readable and writable register.

By transferring data directly into this register, a short

program jump can be executed directly, however, as

only this low byte is available for manipulation, the

jumps are limited to the present page of memory, that is

256 locations. When such program jumps are executed

it should also be noted that a dummy cycle will be in-

serted.

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Program Counter

Mode

*12 *11 *10

*9

0

*8

0

*7

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*6

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*5

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*4

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*3

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*0

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Initial Reset

0

External Interrupt

Timer 0 Overflow

Timer 1 Overflow

Timer 2 Overflow

Timer 3 Overflow

Skip

Program Counter + 2

*8 @7 @6 @5 @4 @3 @2 @1 @0

Loading PCL

*12 *11 *10

*9

Jump, Call Branch

Return from Subroutine

#12 #11 #10 #9

S12 S11 S10 S9

#8

S8

#7

S7

#6

S6

#5

S5

#4

S4

#3

S3

#2

S2

#1

S1

#0

S0

Program Counter

Note: *12~*0: Program counter bits

#12~#0: Instruction code bits

S12~S0: Stack register bits

@7~@0: PCL bits

Rev. 1.60

25

October 20, 2009

HT86BXX/HT86BRXX

·

Location 000H

If the stack is full and an enabled interrupt takes place,

the interrupt request flag will be recorded but the ac-

knowledge signal will be inhibited. When the Stack

Pointer is decremented, by RET or RETI, the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

However, when the stack is full, a CALL subroutine in-

struction can still be executed which will result in a stack

overflow. Precautions should be taken to avoid such

cases which might cause unpredictable program

branching.

This vector is reserved for use by the device reset for

program initialisation. After a device reset is initiated,

the program will jump to this location and begin execu-

tion.

Location 004H

This vector is used by the external interrupt. If the ex-

ternal interrupt pin on the device goes low, the pro-

gram will jump to this location and begin execution if

the external interrupt is enabled and the stack is not

full.

·

Location 008H

Arithmetic and Logic Unit - ALU

This internal vector is used by the 8-bit Timer 0. If a

overflow occurs, the program will jump to this location

and begin execution if the timer interrupt is enabled

and the stack is not full.

The arithmetic-logic unit or ALU is a critical area of the

microcontroller that carries out arithmetic and logic op-

erations of the instruction set. Connected to the main

microcontroller data bus, the ALU receives related in-

struction codes and performs the required arithmetic or

logical operations after which the result will be placed in

the specified register. As these ALU calculation or oper-

ations may result in carry, borrow or other status

changes, the status register will be correspondingly up-

dated to reflect these changes. The ALU supports the

following functions:

Location 00CH

This internal vector is used by the 8-bit Timer1. If a

overflow occurs, the program will jump to this location

and begin execution if the timer interrupt is enabled

and the stack is not full.

Location 010H

For the HT86B40, HT86B50, HT86B50, HT86B60,

HT86BR60, HT86B70, HT86B80, HT86B90 devices,

this internal vector is used by the 16-bit Timer2. If a

overflow occurs, the program will jump to this location

and begin execution if the timer interrupt is enabled

and the stack is not full.

·

Arithmetic operations ADD, ADDM, ADC, ADCM,

SUB, SUBM, SBC, SBCM, DAA

Logic operations AND, OR, XOR, ANDM, ORM,

XORM, CPL, CPLA

·

Location 014H

Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,

RLC

This internal vector is used by the 8-bit Timer3. If a

overflow occurs, the program will jump to this location

and begin execution if the timer interrupt is enabled

and the stack is not full.

·

Increment and Decrement INCA, INC, DECA, DEC

Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA,

SDZA, CALL, RET, RETI

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Program Memory

3

0

The Program Memory is the location where the user

code or program is stored. By using the appropriate pro-

gramming tools, this Program memory device offer us-

ers the flexibility to conveniently debug and develop

their applications while also offering a means of field

programming.

0

4

8

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Organization

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The program memory stores the program instructions

that are to be executed. It also includes data, table and

interrupt entries, addressed by the Program Counter

along with the table pointer. The program memory size

is 8192´16 bits. Certain locations in the program mem-

ory are reserved for special usage.

0

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Special Vectors

Program Memory Structure

Within the Program Memory, certain locations are re-

served for special usage such as reset and interrupts.

Rev. 1.60

26

October 20, 2009

HT86BXX/HT86BRXX

Look-up Table

The following diagram illustrates the addressing/data

flow of the look-up table for the devices:

Any location within the Program Memory can be defined

as a look-up table where programmers can store fixed

data. To use the look-up table, table pointers are used to

setup the address of the data that is to be accessed from

the Program Memory. However, as some devices pos-

sess only a low byte table pointer and other devices pos-

sess both a high and low byte pointer it should be noted

that depending upon which device is used, accessing

look-up table data is implemented in slightly different

ways.

T

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Look-up Table

For the devices, there are two Table Pointer Registers

known as TBLP and TBHP in which the lower order and

higher order address of the look-up data to be retrieved

must be respectively first written. Unlike the other de-

vices in which only the low address byte is defined using

the TBLP register, the additional TBHP register allows

the complete address of the look-up table to be defined

and consequently allow table data from any address

and any page to be directly accessed. For these de-

vices, after setting up both the low and high byte table

pointers, the table data can then be retrieved from any

area of Program Memory using the ²TABRDC [m]² in-

struction or from the last page of the Program Memory

using the ²TABRDL [m]² instruction. When either of

these instructions are executed, the lower order table

byte from the Program Memory will be transferred to the

user defined Data Memory register [m] as specified in

the instruction. The higher order table data byte from the

Program Memory will be transferred to the TBLH special

register. Any unused bits in this transferred higher order

byte will be read as ²0².

Table Program Example

The following example shows how the table pointer and

table data is defined and retrieved from the devices.

This example uses raw table data located in the last

page which is stored there using the ORG statement.

The value at this ORG statement is ²1F00H² which re-

fers to the start address of the last page within the Pro-

gram Memory of the microcontroller. The table pointer is

setup here to have an initial value of ²06H². This will en-

sure that the first data read from the data table will be at

the Program Memory address ²1F06H² or 6 locations

after the start of the last page. Note that the value for the

table pointer is referenced to the first address of the

present page if the ²TABRDC [m]² instruction is being

used. The high byte of the table data which in this case

is equal to zero will be transferred to the TBLH register

automatically when the ²TABRDL [m]² instruction is exe-

cuted.

tempreg1

tempreg2

db

:

?

; temporary register #1

; temporary register #2

:

mov

a,06h

; initialise table pointer - note that this address

; is referenced

tblp,a

; to the last page or present page

:

tabrdl

tempreg1

; transfers value in table referenced by table pointer

; to tempregl

; data at prog. memory address ²1F06H² transferred to

; tempreg1 and TBLH

dec

tblp

; reduce value of table pointer by one

tabrdl

tempreg2

; transfers value in table referenced by table pointer

; to tempreg2

; data at prog.memory address ²1F05H² transferred to

; tempreg2 and TBLH

; in this example the data ²1AH² is transferred to

; tempreg1 and data ²0FH² to register tempreg2

; the value ²00H² will be transferred to the high byte

; register TBLH

:

org

dc

1F00h

; sets initial address of HT86B60 last page

00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh

:

Rev. 1.60

27

October 20, 2009

HT86BXX/HT86BRXX

Because the TBLH register is a read-only register and

cannot be restored, care should be taken to ensure its

protection if both the main routine and Interrupt Service

Routine use table read instructions. If using the table

read instructions, the Interrupt Service Routines may

change the value of the TBLH and subsequently cause

errors if used again by the main routine. As a rule it is

recommended that simultaneous use of the table read

instructions should be avoided. However, in situations

where simultaneous use cannot be avoided, the inter-

rupts should be disabled prior to the execution of any

main routine table-read instructions. Note that all table

related instructions require two instruction cycles to

complete their operation.

Table Location

Instruction

*12

*11

*10

*9

P9

1

*8

P8

1

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

P12 P11 P10

@7

@6

@5

@4

@3

@2

@1

@0

1

Table Location

P12~P8: Write P12~P8 to TBHP pointer register

Note: *12~*0: Current Program ROM table

@7~@0: Write @7~@0 to TBLP pointer register

Data Memory

The Data Memory is a volatile area of 8-bit wide RAM in-

ternal memory and is the location where temporary in-

formation is stored. Divided into two sections, the first of

these is an area of RAM where special function registers

are located. These registers have fixed locations and

are necessary for correct operation of the device. Many

of these registers can be read from and written to di-

rectly under program control, however, some remain

protected from user manipulation. The second area of

RAM Data Memory is reserved for general purpose use.

All locations within this area are read and write accessi-

ble under program control.

cated in Bank 0 which is also subdivided into two sec-

tions, the Special Purpose Data Memory and the

General Purpose Data Memory. The length of these

sections is dictated by the type of microcontroller cho-

sen. The start address of the RAM Data Memory for all

devices is the address ²00H², and the last Data Memory

address is ²FFH². Registers which are common to all

microcontrollers, such as ACC, PCL, etc., have the

same Data Memory address.

General Purpose Data Memory

All microcontroller programs require an area of

read/write memory where temporary data can be stored

and retrieved for use later. It is this area of RAM memory

that is known as General Purpose Data Memory. This

area of Data Memory is fully accessible by the user pro-

gram for both read and write operations. By using the

Organization

The Data Memory is subdivided into two banks, known

as Bank 0 and Bank 1, all of which are implemented in

8-bit wide RAM. Most of the RAM Data Memory is lo-

H

T

8

6

B

4

6

7

9

0

/

H

T

8

6

B

5

R

8

0

H

T

8

6

B

0

5

/

H

T

8

6

B

1

0

6

0

H

T

8

6

B

R

3

1

0

/

H

T

8

6

B

R

2

0

/

H

8

6

B

3

0

H

0

H

S

p

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c

i

a

l

P

u

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p

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D

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a

M

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m

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S

p

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i

a

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P

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e

B

a

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k

1

2

D

H

D

a

t

a

M

e

m

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r

y

M

e

m

o

r

y

3

4

9

0

H

4

0

H

G

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r

a

l

4

P

0

u

H

r

p

o

s

e

G

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a

l

P

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p

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e

D

a

t

a

M

e

m

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y

D

a

t

a

M

e

m

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y

(

1

B

9

2

B

y

t

e

s

)

(

1

9

2

B

y

t

e

s

)

a

n

k

0

F

H

F

H

B

a

n

k

1

F F

H

:

U

n

k

n

o

w

n

RAM Data Memory Structure - Bank 0, Bank1

Most of the RAM Data Memory bits can be directly manipulated using the ²SET [m].i² and ²CLR [m].i² instruc-

tions with the exception of a few dedicated bits. The RAM Data Memory can also be accessed through the

Memory Pointer registers MP0 and MP1.

Note:

Rev. 1.60

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HT86BXX/HT86BRXX

H

T

8

6

B

4

5

6

R

7

8

9

0

²SET [m].i² and ²CLR [m].i² instructions individual bits

can be set or reset under program control giving the

user a large range of flexibility for bit manipulation in the

Data Memory.

H

T

8

6

B

0

1

R

2

3

R

5

0

1

3

0

6

0

Special Purpose Data Memory

I

A

R

0

1

0

1

2

3

4

5

6

7

8

9

H

I

A

R

0

1

2

3

4

5

6

7

8

9

H

M

P

0

1

M

P

0

This area of Data Memory, is located in Bank 0, where

registers, necessary for the correct operation of the

microcontroller, are stored. Most of the registers are

both readable and writable but some are protected and

are readable only, the details of which are located under

the relevant Special Function Register section. Note

that for locations that are unused, any read instruction to

these addresses will return the value ²00H². Although

the Special Purpose Data Memory registers are located

in Bank 0, they will still be accessible even if the Bank

Pointer has selected Bank 1.

I

A

R

1

M

P

1

B

P

A

C

A

C

P

C

L

P

C

L

T

B

L

P

T

B

L

P

T

B

L

H

T

B

L

H

W

D

T

S

W

D

T

S

T

A

T

0

U

A

B

S

T

A

T

U

S

0

A

B

I

N

T

C

I

N

T

C

0

C

D

H

0

C

D

T

M

R

0

1

T

M

R

0

1

T

M

R

0

1

0

C

E

T

M

R

0

1

C

0

E

H

0

F

0

F

1

0

1

2

3

4

5

6

7

8

9

1

0

1

2

3

4

5

6

7

8

9

Special Function Registers

P

A

P

A

B

P

C

A

P

A

B

C

To ensure successful operation of the microcontroller,

certain internal registers are implemented in the RAM

Data Memory area. These registers ensure correct op-

eration of internal functions such as timers, interrupts,

watchdog, etc., as well as external functions such as I/O

data control. The location of these registers within the

RAM Data Memory begins at the address ²00H². Any

unused Data Memory locations between these special

function registers and the point where the General Pur-

pose Memory begins is reserved for future expansion

purposes, attempting to read data from these locations

will return a value of ²00H².

P

B

P

B

C

L

A

T

C

H

0

H

L

A

T

C

H

0

H

L

A

T

C

H

0

M

L

A

T

C

H

0

M

L

A

T

C

H

1

A

B

0

L

A

T

C

H

0

L

1

A

B

L

A

T

C

H

1

H

L

A

T

C

H

1

H

T

8

6

B

L

A

T

C

H

1

M

L

A

T

C

H

1

M

1

C

D

H

1

C

D

H

T

8

6

B

L

A

T

C

H

1

L

A

T

C

H

1

L

H

T

8

6

B

H

T

8

6

0

B

I

N

T

C

H

I

N

T

C

H

1

E

H

1

E

H

T

8

6

B

T

B

H

P

T

B

H

P

1

F

1

F

2

0

T

M

R

2

H

2

0

2

H

1

2

1

H

T

M

R

2

L

2

3

4

5

6

7

8

9

H

T

M

R

2

C

E

H

P

D

2

3

4

5

6

7

8

9

H

2

F

H

P

D

C

T

M

R

3

T

M

R

3

0

1

2

3

4

5

6

7

8

9

H

Indirect Addressing Register - IAR0, IAR1

T

M

R

3

C

T

M

R

3

C

V

O

I

C

E

C

V

O

I

C

E

C

The Indirect Addressing Registers, IAR0 and IAR1, al-

though having their locations in normal RAM register

space, do not actually physically exist as normal regis-

ters. The method of indirect addressing for RAM data

manipulation uses these Indirect Addressing Registers

and Memory Pointers, in contrast to direct memory ad-

dressing, where the actual memory address is speci-

fied. Actions on the IAR0 and IAR1 registers will result in

no actual read or write operation to these registers but

rather to the memory location specified by their corre-

sponding Memory Pointer, MP0 or MP1. Acting as a

pair, IAR0 and MP0 can together only access data from

Bank 0, while the IAR1 and MP1 register pair can ac-

cess data from both Bank 0 and Bank 1. As the Indirect

Addressing Registers are not physically implemented,

reading the Indirect Addressing Registers indirectly will

return a result of ²00H² and writing to the registers indi-

rectly will result in no operation.

D

A

L

D

A

L

D

A

H

D

A

H

V

O

L

V

O

L

A

S

C

R

L

A

T

C

H

D

L

A

T

C

H

D

R

C

O

C

2

A

B

2

A

B

P

W

M

C

H

P

W

M

C

T

M

R

4

H

P

W

M

L

P

W

M

L

T

M

R

4

2

C

D

H

2

C

D

P

W

M

H

R

C

R

O

C

:

U

n

k

n

o

w

n

Special Purpose Data Memory Structure

physically implemented in the Data Memory and can be

manipulated in the same way as normal registers pro-

viding a convenient way with which to address and track

data. When any operation to the relevant Indirect Ad-

dressing Registers is carried out, the actual address that

the microcontroller is directed to, is the address speci-

fied by the related Memory Pointer. MP0, together with

Indirect Addressing Register, IAR0, are used to access

data from Bank 0 only, while MP1 and IAR1 are used to

access data from both Bank 0 and Bank 1.

Memory Pointer - MP0, MP1

For all devices, two Memory Pointers, known as MP0

The following example shows how to clear a section of

four RAM locations already defined as locations adres1

to adres4.

and MP1 are provided. These Memory Pointers are

Rev. 1.60

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HT86BXX/HT86BRXX

data .section ¢data¢

adres1

adres2

adres3

adres4

block

db ?

code .section at 0 ¢code¢

org 00h

start:

mov a,04h

mov block,a

mov a,offset adres1

; setup size of block

; Accumulator loaded with first RAM address

; setup memory pointer with first RAM address

mov mp0,a

loop:

clr IAR0

inc mp0

sdz block

jmp loop

; clear the data at address defined by MP0

; increment memory pointer

; check if last memory location has been cleared

continue:

The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.

Bank Pointer - BP

as addition, subtraction, shift, etc., to the Data Memory

resulting in higher programming and timing overheads.

Data transfer operations usually involve the temporary

storage function of the Accumulator; for example, when

transferring data between one user defined register and

another, it is necessary to do this by passing the data

through the Accumulator as no direct transfer between

two registers is permitted.

The RAM Data Memory is divided into two Banks,

known as Bank 0 and Bank 1. With the exception of the

BP register, all of the Special Purpose Registers and

General Purpose Registers are contained in Bank 0. If

data in Bank 0 is to be accessed, then the BP register

must be loaded with the value "00", while if data in Bank

1 is to be accessed, then the BP register must be loaded

with the value ²01².

Program Counter Low Register - PCL

Using Memory Pointer MP0 and Indirect Addressing

Register IAR0 will always access data from Bank 0, irre-

spective of the value of the Bank Pointer.

To provide additional program control functions, the low

byte of the Program Counter is made accessible to pro-

grammers by locating it within the Special Purpose area

of the Data Memory. By manipulating this register, direct

jumps to other program locations are easily imple-

mented. Loading a value directly into this PCL register

will cause a jump to the specified Program Memory lo-

cation, however, as the register is only 8-bit wide, only

jumps within the current Program Memory page are per-

mitted. When such operations are used, note that a

dummy cycle will be inserted.

The Data Memory is initialised to Bank 0 after a reset,

except for the WDT time-out reset in the Power Down

Mode, in which case, the Data Memory bank remains

unaffected. It should be noted that Special Function

Data Memory is not affected by the bank selection,

which means that the Special Function Registers can be

accessed from within either Bank 0 or Bank 1. Directly

addressing the Data Memory will always result in Bank 0

being accessed irrespective of the value of the Bank

Pointer.

Look-up Table Registers - TBLP, TBLH

These two special function registers are used to control

operation of the look-up table which is stored in the Pro-

gram Memory. TBLP is the table pointer and indicates

the location where the table data is located. Its value

must be setup before any table read commands are ex-

ecuted. Its value can be changed, for example using the

²INC² or ²DEC² instructions, allowing for easy table data

pointing and reading. TBLH is the location where the

Accumulator - ACC

The Accumulator is central to the operation of any

microcontroller and is closely related with operations

carried out by the ALU. The Accumulator is the place

where all intermediate results from the ALU are stored.

Without the Accumulator it would be necessary to write

the result of each calculation or logical operation such

b

7

b

0

B

P

0

B

a

n

k

P

o

i

n

t

e

r

B

P

0

D

a

t

a

M

e

m

o

r

y

0

B

a

n

k

0

1

B

a

n

k

1

N

o

t

u

s

e

d

,

m

u

s

t

b

e

r

e

Bank Pointer - BP

Rev. 1.60

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HT86BXX/HT86BRXX

is also affected by a rotate through carry instruction.

high order byte of the table data is stored after a table

read data instruction has been executed. Note that the

lower order table data byte is transferred to a user de-

fined location.

·

AC is set if an operation results in a carry out of the

low nibbles in addition, or no borrow from the high nib-

ble into the low nibble in subtraction; otherwise AC is

cleared.

Watchdog Timer Register - WDTS

·

Z is set if the result of an arithmetic or logical operation

The Watchdog feature of the microcontroller provides

an automatic reset function giving the microcontroller a

means of protection against spurious jumps to incorrect

Program Memory addresses. To implement this, a timer

is provided within the microcontroller which will issue a

reset command when its value overflows. To provide

variable Watchdog Timer reset times, the Watchdog

Timer clock source can be divided by various division ra-

tios, the value of which is set using the WDTS register.

By writing directly to this register, the appropriate divi-

sion ratio for the Watchdog Timer clock source can be

setup. Note that only the lower 3 bits are used to set divi-

sion ratios between 1 and 128.

is zero; otherwise Z is cleared.

OV is set if an operation results in a carry into the high-

est-order bit but not a carry out of the highest-order bit,

or vice versa; otherwise OV is cleared.

·

PDF is cleared by a system power-up or executing the

²CLR WDT² instruction. PDF is set by executing the

²HALT² instruction.

TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is set by a

WDT time-out.

In addition, on entering an interrupt sequence or execut-

ing a subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status registers are important and if the subroutine

can corrupt the status register, precautions must be

taken to correctly save it.

Status Register - STATUS

This 8-bit register contains the zero flag (Z), carry flag

(C), auxiliary carry flag (AC), overflow flag (OV), power

down flag (PDF), and watchdog time-out flag (TO).

These arithmetic/logical operation and system manage-

ment flags are used to record the status and operation of

the microcontroller.

Interrupt Control Register - INTC, INTCH

Two 8-bit register, known as the INTC and INTCH regis-

ters, controls the operation of both external and internal

timer interrupts. By setting various bits within these reg-

isters using standard bit manipulation instructions, the

enable/disable function of the external and timer inter-

rupts can be independently controlled. A master inter-

rupt bit within this register, the EMI bit, acts like a global

enable/disable and is used to set all of the interrupt en-

able bits on or off. This bit is cleared when an interrupt

routine is entered to disable further interrupt and is set

by executing the ²RETI² instruction.

With the exception of the TO and PDF flags, bits in the

status register can be altered by instructions like most

other registers. Any data written into the status register

will not change the TO or PDF flag. In addition, opera-

tions related to the status register may give different re-

sults due to the different instruction operations. The TO

flag can be affected only by a system power-up, a WDT

time-out or by executing the ²CLR WDT² or ²HALT² in-

struction. The PDF flag is affected only by executing the

²HALT² or ²CLR WDT² instruction or during a system

power-up.

Note: In situations where other interrupts may require

servicing within present interrupt service rou-

tines, the EMI bit can be manually set by the pro-

gram after the present interrupt service routine

has been entered.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

·

C is set if an operation results in a carry during an ad-

dition operation or if a borrow does not take place dur-

ing a subtraction operation; otherwise C is cleared. C

b

7

b

0

T

O

P

D

F

O

V

Z

A

C

T

S

A

T

A

U

S

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i

s

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i

t

h

m

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L

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A

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O

a

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P

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a

Status Register

Rev. 1.60

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HT86BXX/HT86BRXX

Timer Registers

Voice ROM Data Address Latch Counter Registers

Depending upon which device is selected, all devices

contain three or four integrated Timers of either 8-bit or

16-bit size. All devices contain three 8-bit Timers whose

associated registers are known as TMR0, TMR1 and

TMR3, which is the location where the associated

timer's 8-bit value is located. Their associated control

registers, known as TMR0C, TMR1C and TMR3C, con-

tain the setup information for these timers. Some de-

vices also contain an additional 16-bit timer whose

register pair name is known as TMR2L/TMR2H and is

the location where the timer's 16-bit value is located. An

associated control register, known as TMR2C, contains

the setup information for this timer. Note that all timer

registers can be directly written to in order to preload

their contents with fixed data to allow different time inter-

vals to be setup.

These are the LATCH0H/LATCH0M/LATCH0L,

LATCH1H/LATCH1M/LATCH1L and the Voice ROM

data registers. The voice ROM data address latch coun-

ter provides the handshaking between the

microcontroller and the voice ROM, where the voice

codes are stored. Eight bits of voice ROM data will be

addressed by using the 22-bit address latch counter,

which is composed of LATCH0H/LATCH0M/LATCH0L

or LATCH1H/LATCH1M/LATCH1L. After the 8-bit voice

ROM data is addressed, several instruction cycles of at

least 4us at least, will be required to latch the voice ROM

data, after which the microcontroller can read the voice

data from LATCHD.

Voice Control and Audio output Registers -

VOICEC, DAL, DAH, VOL

The device includes a single 12-bit current type DAC

function for driving an external 8W speaker through an

external NPN transistor. The programmer must write the

voice data to the DAL/DAH registers.

Input/Output Ports and Control Registers

Within the area of Special Function Registers, the I/O

registers and their associated control registers play a

prominent role. All I/O ports have a designated register

correspondingly labeled as PA, PB, PD, etc. These la-

beled I/O registers are mapped to specific addresses

within the Data Memory as shown in the Data Memory

table, which are used to transfer the appropriate output

or input data on that port. With each I/O port there is an

associated control register labeled PAC, PBC, PDC,

etc., also mapped to specific addresses with the Data

Memory. The control register specifies which pins of that

port are set as inputs and which are set as outputs. To

setup a pin as an input, the corresponding bit of the con-

trol register must be set high, for an output it must be set

low. During program initialisation, it is important to first

setup the control registers to specify which pins are out-

puts and which are inputs before reading data from or

writing data to the I/O ports. One flexible feature of these

registers is the ability to directly program single bits us-

ing the ²SET [m].i² and ²CLR [m].i² instructions. The

ability to change I/O pins from output to input and

vice-versa by manipulating specific bits of the I/O control

registers during normal program operation is a useful

feature of these devices.

Pulse Width Modulator Registers -

PWMC, PWML, PWMH

Each device contains a single 12-bit PWM function for

driving an external 8W speaker. The programmer must

write the voice data to PWML/PWMH register.

Analog Switch Registers - ASCR

Some devices, include 8 analog switch lines, which

have an associated register, known as ASCR, for their

setup and control.

External RC Oscillation Converter Registers -

RCOCCR, RCOCR, TMR4L, TMR4H

For the HT86B40/HT86B50/HT86B60/HT86BR60/

HT86B70/ HT86B80/HT86B90 devices, which have two

16-bit programmable timers, the TMR4L and TMR4H

registers are for one of the 16-bit timers. The RCOCCR

and RCOCR registers are the control registers for the

external RC oscillator.

Rev. 1.60

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October 20, 2009

HT86BXX/HT86BRXX

Input/Output Ports

Holtek microcontrollers offer considerable flexibility on

their I/O ports. With the input or output designation of ev-

ery pin fully under user program control, pull-high op-

tions for all ports and wake-up options on certain pins,

the user is provided with an I/O structure to meet the

needs of a wide range of application possibilities.

I/O Port Control Registers

Each I/O port has its own control register PAC, PBC,

PDC, etc., to control the input/output configuration. With

this control register, each CMOS output or input with or

without pull-high resistor structures can be reconfigured

dynamically under software control. Each pin of the I/O

ports is directly mapped to a bit in its associated port

control register. For the I/O pin to function as an input,

the corresponding bit of the control register must be writ-

ten as a ²1². This will then allow the logic state of the in-

put pin to be directly read by instructions. When the

corresponding bit of the control register is written as a

²0², the I/O pin will be setup as a CMOS output. If the pin

is currently setup as an output, instructions can still be

used to read the output register. However, it should be

noted that the program will in fact only read the status of

the output data latch and not the actual logic status of

the output pin.

Depending upon which device or package is chosen,

the microcontroller range provides from 16 to 24

bidirectional input/output lines labeled with port names

PA, PB, PD, etc. These I/O ports are mapped to the Data

Memory with specific addresses as shown in the Special

Purpose Data Memory table. All of these I/O ports can

be used for input and output operations. For input oper-

ation, these ports are non-latching, which means the in-

puts must be ready at the T2 rising edge of instruction

²MOV A,[m]², where m denotes the port address. For

output operation, all the data is latched and remains un-

changed until the output latch is rewritten.

Pull-high Resistors

Pin-shared Functions

Many product applications require pull-high resistors for

their switch inputs usually requiring the use of an exter-

nal resistor. To eliminate the need for these external re-

sistors, all I/O pins, when configured as an input have

the capability of being connected to an internal pull-high

resistor. These pull-high resistors are selectable via

configuration options and are implemented using a

weak PMOS transistor. Note that if the pull-high option

is selected, then all I/O pins on that port will be con-

nected to pull-high resistors, individual pins can be se-

lected for pull-high resistor options.

The flexibility of the microcontroller range is greatly en-

hanced by the use of pins that have more than one func-

tion. Limited numbers of pins can force serious design

constraints on designers but by supplying pins with

multi-functions, many of these difficulties can be over-

come. For some pins, the chosen function of the

multi-function I/O pins is set by configuration options

while for others the function is set by application pro-

gram control.

·

Analog Switch

For the HT86B40, HT86B50, HT86B60, HT86BR60,

HT86B70, HT86B80 and HT86B90 devices, pins

PB0~PB7 are pin-shared with analog switch pins K0

to K7. The choice of which function is used is selected

using configuration options and remains fixed after

the device is programmed.

Port A Wake-up

Each device has a HALT instruction enabling the

microcontroller to enter a Power Down Mode and pre-

serve power, a feature that is important for battery and

other low-power applications. Various methods exist to

wake-up the microcontroller, one of which is to change

the logic condition on one of the Port A pins from high to

low. After a ²HALT² instruction forces the microcontroller

into entering a HALT condition, the processor will re-

main idle or in a low-power state until the logic condition

of the selected wake-up pin on Port Achanges from high

to low. This function is especially suitable for applica-

tions that can be woken up via external switches. Note

that each pin on Port A can be selected individually to

have this wake-up feature.

·

External RC Oscillator Converter

For the HT86B40, HT86B50, HT86B60, HT86BR60,

HT86B70, HT86B80 and HT86B90 devices, pins

PD4~PD7 are pin-shared with external oscillator con-

verter pins RCOUT, RR, RC and CC. The external RC

oscillator converter function is selected via a configu-

ration option and remains fixed after the device is pro-

grammed.

·

I/O Pin Structures

The following diagrams illustrate the I/O pin internal

structures. As the exact logical construction of the I/O

pin may differ from these drawings, they are supplied

as a guide only to assist with the functional under-

standing of the I/O pins. Note also that the specified

pins refer to the largest device package, therefore not

all pins specified will exist on all devices.

Rev. 1.60

33

October 20, 2009

HT86BXX/HT86BRXX

V

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PD Input/Output Port

Rev. 1.60

34

October 20, 2009

HT86BXX/HT86BRXX

Programming Considerations

MCU series contain either three or four count up timers

of either 8 or 16-bit capacity depending upon which de-

vice is selected. The provision of an internal prescaler to

the clock circuitry of some of the timer gives added

range to the timer.

Within the user program, one of the first things to con-

sider is port initialization. After a reset, all of the I/O data

and port control registers will be set high. This means

that all I/O pins will default to an input state, the level of

which depends on the other connected circuitry and

whether pull-high options have been selected. If the port

control registers, PAC, PBC, PDC, etc., are then pro-

grammed to setup some pins as outputs, these output

pins will have an initial high output value unless the as-

sociated port data registers, PA, PB, PD, etc., are first

programmed. Selecting which pins are inputs and which

are outputs can be achieved byte-wide by loading the

correct values into the appropriate port control register

or by programming individual bits in the port control reg-

ister using the ²SET [m].i² and ²CLR [m].i² instructions.

Note that when using these bit control instructions, a

read-modify-write operation takes place. The

microcontroller must first read in the data on the entire

port, modify it to the required new bit values and then re-

write this data back to the output ports.

There is single type of register related to the Timer. The

first is the register that contains the actual value of the

timer and into which an initial value can be preloaded.

Reading from this register retrieves the contents of the

Timer. All devices can have the timer clock configured to

come from the internal clock source. The accompanying

table lists the associated timer register names.

HT86B40

HT86B05

HT86B50

HT86B10

HT86B60

HT86BR10

HT86BR60

HT86B20

HT86B70

HT86B30

HT86B80

HT86BR30

HT86B90

No. of 8-bit Timers

3

TMR0

TMR1

TMR3

TMR0

TMR1

TMR3

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

Timer Register Name

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TMR0C

TMR1C

TMR3C

TMR0C

TMR1C

TMR3C

Timer Control Register

W

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Read/Write Timing

No. of 16-bit Timers

Timer Register Name

Timer Control Register

1

¾

TMR2L

TMR2H

Port A has the additional capability of providing wake-up

functions. When the device is in the Power Down Mode,

various methods are available to wake the device up.

One of these is a high to low transition of any of the Port

A pins. Single or multiple pins on Port A can be setup to

have this function.

TMR2C

Configuring the Timer Input Clock Source

The clock source for the 8-bit timers is the system clock

divided by four while the 16-bit timer has a choice of ei-

ther the system clock or the system clock divided by

four. The 8-bit timer clock source is also first divided by

the division ratio of which is conditioned by the three

lower bits of the associated timer control register.

Timers

The provision of timers form an important part of any

microcontroller, giving the designer a means of carrying

out time related functions. The devices in the Voice Type

D

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8-bit Timer Structure

Rev. 1.60

35

October 20, 2009

HT86BXX/HT86BRXX

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16-bit Timer Structure - HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90

Timer Registers - TMR0, TMR1, TMR2L/TMR2H,

and not directly into the low byte register. The actual

transfer of the data into the low byte register is only car-

ried out when a write to its associated high byte register,

namely TMR2H, is executed. However, using instruc-

tions to preload data into the high byte timer register will

result in the data being directly written to the high byte

register. At the same time the data in the low byte buffer

will be transferred into its associated low byte register.

For this reason, when preloading data into the 16-bit

timer registers, the low byte should be written first. It

must also be noted that to read the contents of the low

byte register, a read to the high byte register must first

be executed to latch the contents of the low byte buffer

into its associated low byte register. After this has been

done, the low byte register can be read in the normal

way. Note that reading the low byte timer register will

only result in reading the previously latched contents of

the low byte buffer and not the actual contents of the low

byte timer register.

TMR3

The timer registers are special function registers located

in the special purpose Data Memory and is the place

where the actual timer value is stored. All devices con-

tain three 8-bit timers, whose registers are known as

TMR0, TMR1 and TMR3. The HT86B40, HT86B50,

HT86B60, HT86BR60, HT86B70, HT86B80 and

HT86B90 devices also contain an additional single

16-bit timer, which has a pair of registers known as

TMR2L and TMR2H. The value in the timer registers in-

creases by one each time an internal clock pulse is re-

ceived. The timer will count from the initial value loaded

by the preload register to the full count of FFH for the

8-bit timer or FFFFH for the 16-bit timers at which point

the timer overflows and an internal interrupt signal is

generated. The timer value will then be reset with the ini-

tial preload register value and continue counting.

Note that to achieve a maximum full range count of FFH

for the 8-bit timer or FFFFH for the 16-bit timers, the

preload registers must first be cleared to all zeros. It

should be noted that after power-on, the preload regis-

ters will be in an unknown condition. Note that if the

Timer Counters are in an OFF condition and data is writ-

ten to their preload registers, this data will be immedi-

ately written into the actual counter. However, if the

counter is enabled and counting, any new data written

into the preload data register during this period will re-

main in the preload register and will only be written into

the actual counter the next time an overflow occurs.

Note also that when the timer registers are read, the

timer clock will be blocked to avoid errors, however, as

this may result in certain timing errors, programmers

must take this into account.

Timer Control Registers - TMR0C, TMR1C, TMR2C,

TMR3C

Each timer has its respective timer control register,

known as TMR0C, TMR1C, TMR2C and TMR3C. It is

the timer control register together with their correspond-

ing timer registers that control the full operation of the

timers. Before the timers can be used, it is essential that

the appropriate timer control register is fully pro-

grammed with the right data to ensure its correct opera-

tion, a process that is normally carried out during

program initialization. Bits 7 and 6 of the Timer Control

Register, which are known as the bit pair TM1/TM0 re-

spectively, must be set to the required logic levels. The

timer-on bit, which is bit 4 of the Timer Control Register

and known as TON, depending upon which timer is

used, provides the basic on/off control of the respective

timer. setting the bit high allows the timer to run, clearing

the bit stops the timer. For the 8-bit timers, which have

prescalers, bits 0~2 of the Timer Control Register deter-

mine the division ratio of the input clock prescaler.

For devices which have an internal 16-bit Timer, and

which therefore have both low byte and high byte timer

registers, accessing these registers is carried out in a

specific way. It must be noted that when using instruc-

tions to preload data into the low byte register, namely

TMR2L, the data will only be placed in a low byte buffer

Rev. 1.60

36

October 20, 2009

HT86BXX/HT86BRXX

b

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Timer Control Register - All Devices

b

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Timer Control Register - HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90

Configuring the Timer

Prescaler Rate Select bits, which are bits 0~2 in the

Timer Control Register. After the other bits in the Timer

Control Register have been setup, the enable bit, which

is bit 4 of the Timer Control Register, can be set high to

enable the Timer to run. Each time an internal clock cy-

cle occurs, the Timer increments by one. When it is full

and overflows, an interrupt signal is generated and the

Timer will reload the value already loaded into the

preload register and continue counting. The interrupt

can be disabled by ensuring that the Timer Interrupt En-

able bit in the Interrupt Control Register, INTC, is reset

to zero.

The Timer is used to measure fixed time intervals, pro-

viding an internal interrupt signal each time the Timer

overflows. To do this the Operating Mode Select bit pair

in the Timer Control Register must be set to the correct

value as shown.

Bit7 Bit6

Control Register Operating Mode

Select Bits

1

0

The internal clock, f_SYS, is used as the Timer clock.

However, this clock source is further divided by a

prescaler, the value of which is determined by the

P

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Timer Mode Timing Diagram

Rev. 1.60

37

October 20, 2009

HT86BXX/HT86BRXX

Prescaler

important to ensure that an initial value is first loaded into

the timer registers before the timer is switched on; this is

because after power-on the initial values of the timer reg-

isters are unknown. After the timer has been initialized

the timer can be turned on and off by controlling the en-

able bit in the timer control register.

All of the 8-bit timers possess a prescaler. Bits 0~2 of

their associated timer control register, define the

pre-scaling stages of the internal clock source of the

Timer. The Timer overflow signal can be used to gener-

ate signals for the Timer interrupt.

Timer Program Example

Programming Considerations

The following example program section is based on the

HT86B40, HT86B50, HT86B60, HT86BR60, HT86B70,

HT86B80 and HT86B90 devices, which contain a single

internal 16-bit timer. Programming the timer for other de-

vices is conducted in a very similar way. The program

shows how the timer registers are setup along with how

the interrupts are enabled and managed. Points to note

in the example are how, for the 16-bit timer, the low byte

must be written first, this is because the 16-bit data will

only be written into the actual timer register when the

high byte is loaded. Also note how the timer is turned on

by setting bit 4 of the respective timer control register.

The timer can be turned off in a similar way by clearing

the same bit. This example program sets the timer to be

in the timer mode which uses the internal system clock

as their clock source.

The internal system clock is used as the timer clock

source and is therefore synchronized with the overall

operation of the microcontroller. In this mode, when the

appropriate timer register is full, the microcontroller will

generate an internal interrupt signal directing the pro-

gram flow to the respective internal interrupt vector.

When the Timer is read, the clock is blocked to avoid er-

rors, however as this may result in a counting error, this

should be taken into account by the programmer. Care

must be taken to ensure that the timers are properly ini-

tialized before using them for the first time. The associ-

ated timer enable bits in the interrupt control register must

be properly set otherwise the internal interrupt associated

with the timer will remain inactive. The edge select, timer

mode and clock source control bits in timer control regis-

ter must also be correctly set to ensure the timer is prop-

erly configured for the required application. It is also

#include HT86B40.inc

jmp begin

:

org 04h

reti

; external interrupt vectors

org 08h

reti

org 0Ch

reti

org 10h

jmp tmr2int

org 14h

reti

; timer 2 interrupt vector

; jump here when timer 2 overflows

:

; internal timer 2 interrupt routine

tmr2int:

:

; timer 2 main program placed here

:

reti

:

begin:

; setup timer 2 registers

mov a,09bh

mov tmr2l,a

mov a,0e8h

mov tmr2h,a

mov a,090h

mov tmr2c,a

; setup timer 2 low byte

; low byte must be setup before high byte

; setup timer 2 high byte

; setup timer 2 control register

; setup timer mode

; setup interrupt register

mov a,01h

mov intc,a

mov a,01h

mov intch,a

:

; enable master interrupt

; enable timer 2 interrupt

Rev. 1.60

38

October 20, 2009

HT86BXX/HT86BRXX

Interrupts

Interrupts are an important part of any microcontroller

system. When an external event or an internal function

such as a Timer requires microcontroller attention, their

corresponding interrupt will enforce a temporary sus-

pension of the main program allowing the

microcontroller to direct attention to their respective

needs. Each device contains a single external interrupt

and three or four internal timer interrupt functions. The

external interrupt is controlled by the action of the exter-

nal INT pin, while the internal interrupt is controlled by

the relevant Timer overflow.

stack. The Program Counter will then be loaded with a

new address which will be the value of the correspond-

ing interrupt vector. The microcontroller will then fetch

its next instruction from this interrupt vector. The instruc-

tion at this vector will usually be a JMP statement which

will take program execution to another section of pro-

gram which is known as the interrupt service routine.

Here is located the code to control the appropriate inter-

rupt. The interrupt service routine must be terminated

with a RETI statement, which retrieves the original Pro-

gram Counter address from the stack and allows the

microcontroller to continue with normal execution at the

point where the interrupt occurred.

Interrupt Register

Overall interrupt control, which means interrupt enabling

and flag setting, is controlled using two registers, known

as INTC and INTCH, which are located in the Data

Memory. By controlling the appropriate enable bits in

these registers each individual interrupt can be enabled

or disabled. Also when an interrupt occurs, the corre-

sponding request flag will be set by the microcontroller.

The global enable flag if cleared to zero will disable all

interrupts.

The various interrupt enable bits, together with their as-

sociated request flags, are shown in the accompanying

diagram with their order of priority.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked, as the EMI bit will be cleared au-

tomatically. This will prevent any further interrupt nesting

from occurring. However, if other interrupt requests oc-

cur during this interval, although the interrupt will not be

immediately serviced, the request flag will still be re-

corded. If an interrupt requires immediate servicing

while the program is already in another interrupt service

routine, the EMI bit should be set after entering the rou-

tine, to allow interrupt nesting. If the stack is full, the in-

terrupt request will not be acknowledged, even if the

related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

Interrupt Operation

A timer overflow or the external interrupt line being

pulled low will all generate an interrupt request by set-

ting their corresponding request flag, if their appropriate

interrupt enable bit is set. When this happens, the Pro-

gram Counter, which stores the address of the next in-

struction to be executed, will be transferred onto the

b

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Interrupt Control Register

Rev. 1.60

39

October 20, 2009

HT86BXX/HT86BRXX

b

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Interrupt Structure - HT86B05/HT86B10/HT86BR10/HT86B20/HT86B30/HT86BR30

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Interrupt Structure - HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90

Rev. 1.60

40

October 20, 2009

HT86BXX/HT86BRXX

Interrupt Priority

Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter

of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the accompanying

table shows the priority that is applied.

HT86B05/HT86B10

HT86BR10/HT86B20

HT86B30/HT86BR30

Priority

HT86B40/HT86B50/HT86B60

HT86BR60/HT86B70/HT86B80

HT86B90

Interrupt Source

Interrupt Vector

Priority

External Interrupt

Timer 0 Overflow

Timer 1 Overflow

Timer 2 Overflow

Timer 3 Overflow

04H

08H

0CH

10H

14H

1

2

1

2

3

4

5

3

¾

4

In cases where both external and timer interrupts are

enabled and where an external and timer interrupt occur

simultaneously, the external interrupt will always have

priority and will therefore be serviced first. Suitable

masking of the individual interrupts using the INTC and

INTCH registers can prevent simultaneous occur-

rences.

in the INTC and INTCH registers. Some devices also

contain a 16-bit timer, which has a corresponding timer

interrupt enable bit, ET2I, and a corresponding timer re-

quest flag, T2F, which are contained in the INTCH regis-

ter. When the master interrupt and corresponding timer

interrupt enable bits are enabled, the stack is not full,

and when the corresponding timer overflows a subrou-

tine call to the corresponding timer interrupt vector will

occur. The corresponding Program Memory vector loca-

tions for Timer 0, Timer1, Timer 2 and Timer 3 are 08H,

0CH, 10H and 14H. After entering the interrupt execu-

tion routine, the corresponding interrupt request flags,

T0F, T1F, T2F or T3F will be reset and the EMI bit will be

cleared to disable other interrupts.

External Interrupt

Each device contains a single external interrupt function

controlled by the external pin, INT. For an external inter-

rupt to occur, the corresponding external interrupt en-

able bit must be first set. This is bit 1 of the INTC register

and known as EEI. An external interrupt is triggered by

an external edge transition on the external interrupt pin

INT, after which the related interrupt request flag, EIF,

which is bit 4 of INTC, will be set. A configuration option

exists for the external interrupt pin to determine the type

of external edge transition which will trigger an external

interrupt. There are two options available, a low going

edge or both high and low going edges. When the mas-

ter interrupt and external interrupt bits are enabled, the

stack is not full and an active edge transition, as setup in

the configuration options, occurs on the INT pin, a sub-

routine call to the corresponding external interrupt vec-

tor, which is located at 04H, will occur. After entering the

interrupt execution routine, the corresponding interrupt

request flag, EIF, will be reset and the EMI bit will be

cleared to disable other interrupts.

Programming Considerations

By disabling the interrupt enable bits, a requested inter-

rupt can be prevented from being serviced, however,

once an interrupt request flag is set, it will remain in this

condition in the INTC or INTCH register until the corre-

sponding interrupt is serviced or until the request flag is

cleared by a software instruction.

It is recommended that programs do not use the ²CALL

subroutine² instruction within the interrupt subroutine.

Interrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications. If

only one stack is left and the interrupt is not well con-

trolled, the original control sequence will be damaged

once a ²CALL subroutine² is executed in the interrupt

subroutine.

Timer Interrupt

All of these interrupts have the capability of waking up

the processor when in the Power Down Mode. Only the

Program Counter is pushed onto the stack. If the con-

tents of the register or status register are altered by the

interrupt service program, which may corrupt the de-

sired control sequence, then the contents should be

saved in advance.

For a timer generated interrupt to occur, the correspond-

ing timer interrupt enable bit must be first set. Each de-

vice contains three 8-bit timers whose corresponding

interrupt enable bits are known as ET0I, ET1I and ET3I

and are located in the INTC and INTCH registers. Each

timer also has a corresponding timer interrupt request

flag, which are known as T0F, T1F and T3F, also located

Rev. 1.60

41

October 20, 2009

HT86BXX/HT86BRXX

Reset and Initialisation

A reset function is a fundamental part of any

microcontroller ensuring that the device can be set to

some predetermined condition irrespective of outside

parameters. The most important reset condition is after

power is first applied to the microcontroller. In this case,

internal circuitry will ensure that the microcontroller, af-

ter a short delay, will be in a well defined state and ready

to execute the first program instruction. After this

power-on reset, certain important internal registers will

be set to defined states before the program com-

mences. One of these registers is the Program Counter,

which will be reset to zero forcing the microcontroller to

begin program execution from the lowest Program

Memory address.

inhibited. After the RES line reaches a certain voltage

value, the reset delay time t_RSTDis invoked to provide

an extra delay time after which the microcontroller will

begin normal operation. The abbreviation SST in the

figures stands for System Start-up Timer.

V

D

0

.

D

9

D

V

R

E

S

t

R

S

T

D

S

T

i

m

e

-

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u

t

I

n

t

e

r

n

a

l

R

e

s

e

t

Power-On Reset Timing Chart

For most applications a resistor connected between

VDD and the RES pin and a capacitor connected be-

tween VSS and the RES pin will provide a suitable ex-

ternal reset circuit. Any wiring connected to the RES

pin should be kept as short as possible to minimise

any stray noise interference.

In addition to the power-on reset, situations may arise

where it is necessary to forcefully apply a reset condition

when the microcontroller is running. One example of this

is where after power has been applied and the

microcontroller is already running, the RES line is force-

fully pulled low. In such a case, known as a normal oper-

ation reset, some of the microcontroller registers remain

unchanged allowing the microcontroller to proceed with

normal operation after the reset line is allowed to return

high. Another type of reset is when the Watchdog Timer

overflows and resets the microcontroller. All types of re-

set operations result in different register conditions be-

ing setup.

V

R

D

S

1

0

W

0

k

E

0

m

. F 1

V

S

Basic Reset Circuit

For applications that operate within an environment

where more noise is present the Enhanced Reset Cir-

cuit shown is recommended.

Another reset exists in the form of a Low Voltage Reset,

LVR, where a full reset, similar to the RES reset is imple-

mented in situations where the power supply voltage

falls below a certain threshold.

0

.

m

0

F

1

V

D

1

0

W

0

k

Reset Functions

R

E

S

There are five ways in which a microcontroller reset can

occur, through events occurring both internally and ex-

ternally:

1

0

W

k

0

m

. F 1

V

S

·

Power-on Reset

Enhanced Reset Circuit

The most fundamental and unavoidable reset is the

one that occurs after power is first applied to the

microcontroller. As well as ensuring that the Program

Memory begins execution from the first memory ad-

dress, a power-on reset also ensures that certain

other registers are preset to known conditions. All the

I/O port and port control registers will power up in a

high condition ensuring that all pins will be first set to

inputs.

More information regarding external reset circuits is

located in Application Note HA0075E on the Holtek

website.

·

RES Pin Reset

This type of reset occurs when the microcontroller is

already running and the RES pin is forcefully pulled

low by external hardware such as an external switch.

In this case as in the case of other reset, the Program

Counter will reset to zero and program execution initi-

ated from this point.

Although the microcontroller has an internal RC reset

function, if the VDD power supply rise time is not fast

enough or does not stabilise quickly at power-on, the

internal reset function may be incapable of providing

proper reset operation. For this reason it is recom-

mended that an external RC network is connected to

the RES pin, whose additional time delay will ensure

that the RES pin remains low for an extended period

to allow the power supply to stabilise. During this time

delay, normal operation of the microcontroller will be

0

.

D

9

D

V

0

.

D

4

D

V

R

E

S

t

R

S

T

D

S

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e

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t

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r

n

a

l

R

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s

e

t

RES Reset Timing Chart

October 20, 2009

Rev. 1.60

42

HT86BXX/HT86BRXX

·

Reset Initial Conditions

Low Voltage Reset - LVR

The microcontroller contains a low voltage reset circuit

in order to monitor the supply voltage of the device,

which is selected via a configuration option. If the supply

voltage of the device drops to within a range of

0.9V~V_LVRsuch as might occur when changing the bat-

tery, the LVR will automatically reset the device inter-

nally. The LVR includes the following specifications: For

a valid LVR signal, a low voltage, i.e., a voltage in the

range between 0.9V~V_LVRmust exist for greater than the

value t_LVRspecified in the A.C. characteristics. If the low

voltage state does not exceed 1ms, the LVR will ignore it

and will not perform a reset function.

The different types of reset described affect the reset

flags in different ways. These flags, known as PDF and

TO are located in the status register and are controlled

by various microcontroller operations, such as the

Power Down function or Watchdog Timer. The reset

flags are shown in the table:

TO PDF

RESET Conditions

0

u

1

0

u

1

RES reset during power-on

RES or LVR reset during normal operation

WDT time-out reset during normal operation

WDT time-out reset during Power Down

L

V

R

t

R

S

T

D

S

T

i

m

e

-

o

u

t

Note: ²u² stands for unchanged

I

n

t

e

r

n

a

l

R

e

s

e

t

The following table indicates the way in which the vari-

ous components of the microcontroller are affected after

a power-on reset occurs.

Low Voltage Reset Timing Chart

·

Watchdog Time-out Reset during Normal Operation

The Watchdog time-out Reset during normal opera-

tion is the same as a hardware RES pin reset except

that the Watchdog time-out flag TO will be set to ²1².

Item

Condition After RESET

Program Counter Reset to zero

Interrupts

WDT

All interrupts will be disabled

W

D

T

i

m

e

-

o

u

t

Clear after reset, WDT begins

counting

t

R

S

T

D

S

T

i

m

e

-

o

u

t

Timer

All Timer will be turned off

I

n

t

e

r

n

a

l

R

e

s

e

t

The Timer Prescaler will be

cleared

Prescaler

WDT Time-out Reset during Normal Operation

Timing Chart

Input/Output Ports I/O ports will be setup as inputs

Stack Pointer will point to the top

Stack Pointer

of the stack

·

Watchdog Time-out Reset during Power Down

The Watchdog time-out Reset during Power Down is

a little different from other kinds of reset. Most of the

conditions remain unchanged except that the Pro-

gram Counter and the Stack Pointer will be cleared to

²0² and the TO flag will be set to ²1². Refer to the A.C.

Characteristics for t_SSTdetails.

The different kinds of resets all affect the internal regis-

ters of the microcontroller in different ways. To ensure

reliable continuation of normal program execution after

a reset occurs, it is important to know what condition the

microcontroller is in after a particular reset occurs. The

following table describes how each type of reset affects

each of the microcontroller internal registers. Note that

where more than one package type exists the table will

reflect the situation for the larger package type.

W

D

T

i

m

e

-

o

u

t

S

T

S

T

i

m

e

-

o

u

t

WDT Time-out Reset during Power Down

Timing Chart

Rev. 1.60

43

October 20, 2009

HT86BXX/HT86BRXX

HT86B05/HT86B10/HT86BR10/HT86B20/HT86B30/HT86BR30

Reset

WDT Time-out

RES Reset

(HALT)

WDT Time-out

from HALT

Register

(Power-on)

(Normal Operation) (Normal Operation)

MP0

x x x x x x x x

0 0 0 0 0 0 0 0

x x x x x x x x

0 0 0 0 0 1 1 1

- - 0 0 x x x x

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

0 0 0 0 0 1 1 1

- - 1 u u u u u

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

- - 0 - - - 0 -

u u u u u u u u

u u u u - - - -

u u u u u u u u

u u u - u u u u

- - - 0 - 0 0 -

u u u u u u u u

0 - - - 0 - - 0

u u u u - - - -

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

0 0 0 0 0 1 1 1

- - u u u u u u

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

- - 0 - - - 0 -

u u u u u u u u

u u u u - - - -

u u u u u u u u

u u u - u u u u

- - - 0 - 0 0 -

u u u u u u u u

0 - - - 0 - - 0

u u u u - - - -

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

0 0 0 0 0 1 1 1

- - 0 1 u u u u

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

- - 0 - - - 0 -

u u u u u u u u

u u u u - - - -

u u u u u u u u

u u u - u u u u

- - - 0 - 0 0 -

u u u u u u u u

0 - - - 0 - - 0

u u u u - - - -

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

- - 1 1 u u u u

- u u u u u u u

u u u u u u u u

u u - u u u u u

u u u u u u u u

u u - u u u u u

u u u u u u u u

u u - u u u u u

- - u - - - u -

u u u u u u u u

u u u u - - - -

u u u u u u u u

u u u - u u u u

- - - u - u u -

u u u u u u u u

u - - - u - - u

u u u u - - - -

u u u u u u u u

MP1

ACC

PCL

TBLP

TBLH

WDTS

STATUS

INTC

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

- - 0 - - - 0 -

x x x x x x x x

x x x x - - - -

x x x x x x x x

x x x - x x x x

- - - 0 - 0 0 -

x x x x x x x x

0 - - - 0 - - 0

x x x x - - - -

x x x x x x x x

TMR0

TMR0C

TMR1

TMR1C

PA

PAC

PB

PBC

TMR3

TMR3C

INTCH

TBHP

DAL

DAH

VOL

VOICEC

LATCH0H

LATCH0M

LATCH0L

LATCH1H

LATCH1M

LATCH1L

LATCHD

PWMC

PWML

PWMH

Note:

²u² stands for unchanged

²x² stands for unknown

²-² stands for undefined

Rev. 1.60

44

October 20, 2009

HT86BXX/HT86BRXX

HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90

Reset

WDT Time-out

RES Reset

(HALT)

WDT Time-out

from HALT

Register

(Power-on)

(Normal Operation) (Normal Operation)

MP0

x x x x x x x x

0 0 0 0 0 0 0 0

x x x x x x x x

0 0 0 0 0 0 0 0

x x x x x x x x

0 0 0 0 0 1 1 1

- - 0 0 x x x x

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

0 0 0 0 0 1 1 1

- - 1 u u u u u

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 - 0 - - - -

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

- - 0 0 - - 0 0

u u u u u u u u

u u u u - - - -

u u u u u u u u

u u u - u u u u

- - - 0 - 0 0 -

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

0 0 0 0 0 1 1 1

- - u u u u u u

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 - 0 - - - -

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

- - 0 0 - - 0 0

u u u u u u u u

u u u u - - - -

u u u u u u u u

u u u - u u u u

- - - 0 - 0 0 -

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

0 0 0 0 0 1 1 1

- - 0 1 u u u u

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 - 0 - - - -

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

- - 0 0 - - 0 0

u u u u u u u u

u u u u - - - -

u u u u u u u u

u u u - u u u u

- - - 0 - 0 0 -

u u u u u u u u

0 0 0 0 0 0 0 0

u u u u u u u u

- - 1 1 u u u u

- u u u u u u u

u u u u u u u u

u u - u u u u u

u u u u u u u u

u u - u u u u u

u u u u u u u u

u u - u - - - -

u u u u u u u u

u u - u u u u u

- - u u - - u u

u u u u u u u u

u u u u - - - -

u u u u u u u u

u u u - u u u u

- - - u - u u -

u u u u u u u u

MP1

BP

ACC

PCL

TBLP

TBLH

WDTS

STATUS

INTC

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 - 0 - - - -

0 0 0 0 0 0 0 0

0 0 - 0 1 0 0 0

- - 0 0 - - 0 0

x x x x x x x x

x x x x - - - -

x x x x x x x x

x x x - x x x x

- - - 0 - 0 0 -

x x x x x x x x

TMR0

TMR0C

TMR1

TMR1C

PA

PAC

PB

PBC

PD

PDC

TMR2H

TMR2L

TMR2C

TMR3

TMR3C

INTCH

TBHP

DAL

DAH

VOL

VOICEC

LATCH0H

LATCH0M

LATCH0L

LATCH1H

LATCH1M

LATCH1L

LATCHD

Rev. 1.60

45

October 20, 2009

HT86BXX/HT86BRXX

Reset

WDT Time-out

RES Reset

(HALT)

WDT Time-out

from HALT

Register

(Power-on)

(Normal Operation) (Normal Operation)

PWMC

PWML

0 - - - 0 - - 0

x x x x - - - -

x x x x x x x x

- - - - 1 1 1 1

0 0 1 0 - - - -

x x x x x x x x

1 x x x - - 0 0

0 - - - 0 - - 0

u u u u - - - -

u u u u u u u u

- - - - 1 1 1 1

0 0 1 0 - - - -

x x x x x x x x

1 x x x - - 0 0

0 - - - 0 - - 0

u u u u - - - -

u u u u u u u u

- - - - 1 1 1 1

0 0 1 0 - - - -

x x x x x x x x

1 x x x - - 0 0

0 - - - 0 - - 0

u u u u - - - -

u u u u u u u u

- - - - 1 1 1 1

0 0 1 0 - - - -

x x x x x x x x

1 x x x - - 0 0

u - - - u - - u

u u u u - - - -

u u u u u u u u

- - - - u u u u

u u u u - - - -

u u u u u u u u

u u u u - - u u

PWMH

ASCR

RCOCCR

TMR4H

TMR4L

RCOCR

Note:

²u² stands for unchanged

²x² stands for unknown

²-² stands for undefined

Rev. 1.60

46

October 20, 2009

HT86BXX/HT86BRXX

Oscillator

Various oscillator options offer the user a wide range of

functions according to their various application require-

ments. Two types of system clocks can be selected

while various clock source options for the Watchdog

Timer are provided for maximum flexibility. All oscillator

options are selected through the configuration options.

External RC Oscillator

Using the external system RC oscillator requires that a

resistorco. The mask MCU value between 60kW and

130kW, the OTP MCU value between 150kW and

300kW. They connected between OSC1 and VSS. The

generated system clock divided by 4 will be provided on

OSC2 as an output which can be used for external syn-

chronization purposes. Note that as the OSC2 output is

an NMOS open-drain type, a pull high resistor should be

connected if it to be used to monitor the internal fre-

quency. Although this is a cost effective oscillator config-

uration, the oscillation frequency can vary with VDD,

temperature and process variations and is therefore not

suitable for applications where timing is critical or where

accurate oscillator frequencies are required. Note that it

is the only microcontroller internal circuitry together with

the external resistor, that determine the frequency of the

oscillator. The external capacitor shown on the diagram

does not influence the frequency of oscillation.

The two methods of generating the system clock are:

·

External crystal/resonator oscillator

External RC oscillator

One of these two methods must be selected using the

configuration options.

More information regarding the oscillator is located in

Application Note HA0075E on the Holtek website.

External Crystal/Resonator Oscillator

The simple connection of a crystal across OSC1 and

OSC2 will create the necessary phase shift and feed-

back for oscillation, and will normally not require exter-

nal capacitors. However, for some crystals and most

resonator types, to ensure oscillation and accurate fre-

quency generation, it may be necessary to add two

small value external capacitors, C1 and C2. The exact

values of C1 and C2 should be selected in consultation

O

S

C

1

R

O

S

C

O

S

C

2

D

f

S

Y

/

S

4

N

M

O

S

O

p

e

n

r

a

i

I

O

C

n

t

e

r

n

C

1

External RC Oscillator

O

S

C

1

s

c

i

l

i

r

c

u

C

a

R

p

R

f

Watchdog Timer Oscillator

The WDT oscillator is a fully self-contained free running

on-chip RC oscillator with a typical period of 65ms at 5V

requiring no external components. When the device en-

ters the Power Down Mode, the system clock will stop

running but the WDT oscillator continues to free-run and

to keep the watchdog active. However, to preserve

power in certain applications the WDT oscillator can be

disabled via a configuration option.

C

b

T

o

i

n

c

i

r

c

u

O

S

C

2

C

2

N

o

t

e

:

1

.

R

p

i

s

n

o

r

m

a

l

y

2

.

A

l

t

h

o

u

g

h

n

o

t

s

h

o

w

n

c

a

p

a

c

i

t

a

n

c

e

o

f

a

r

o

Crystal/Resonator Oscillator

with the crystal or resonator manufacturer¢s specifica-

tion. The external parallel feedback resistor, Rp, is nor-

mally not required but in some cases may be needed to

assist with oscillation start up.

Internal Ca, Cb, Rf Typical Values @ 5V, 25°C

Ca

Cb

Rf

11~13pF

13~15pF

800kW

Oscillator Internal Component Values

Rev. 1.60

47

October 20, 2009

HT86BXX/HT86BRXX

Power Down Mode and Wake-up

Power Down Mode

outputs. These should be placed in a condition in which

minimum current is drawn or connected only to external

circuits that do not draw current, such as other CMOS

inputs. Also note that additional standby current will also

be required if the configuration options have enabled the

Watchdog Timer internal oscillator.

All of the Holtek microcontrollers have the ability to enter

a Power Down Mode, also known as the HALT Mode or

Sleep Mode. When the device enters this mode, the nor-

mal operating current, will be reduced to an extremely

low standby current level. This occurs because when

the device enters the Power Down Mode, the system

oscillator is stopped which reduces the power consump-

tion to extremely low levels, however, as the device

maintains its present internal condition, it can be woken

up at a later stage and continue running, without requir-

ing a full reset. This feature is extremely important in ap-

plication areas where the MCU must have its power

supply constantly maintained to keep the device in a

known condition but where the power supply capacity is

limited such as in battery applications.

Wake-up

After the system enters the Power Down Mode, it can be

woken up from one of various sources listed as follows:

·

An external reset

An external falling edge on Port A

A system interrupt

A WDT overflow

If the system is woken up by an external reset, the de-

vice will experience a full system reset, however, if the

device is woken up by a WDT overflow, a Watchdog

Timer reset will be initiated. Although both of these

wake-up methods will initiate a reset operation, the ac-

tual source of the wake-up can be determined by exam-

ining the TO and PDF flags. The PDF flag is cleared by a

system power-up or executing the clear Watchdog

Timer instructions and is set when executing the ²HALT²

instruction. The TO flag is set if a WDT time-out occurs,

and causes a wake-up that only resets the Program

Counter and Stack Pointer, the other flags remain in

their original status.

Entering the Power Down Mode

There is only one way for the device to enter the Power

Down Mode and that is to execute the ²HALT² instruc-

tion in the application program. When this instruction is

executed, the following will occur:

·

The system oscillator will stop running and the appli-

cation program will stop at the ²HALT² instruction.

The Data Memory contents and registers will maintain

their present condition.

The WDT will be cleared and resume counting if the

WDT clock source is selected to come from the WDT

oscillator. The WDT will stop if its clock source origi-

nates from the system clock.

Each pin on Port A can be setup via an individual config-

uration option to permit a negative transition on the pin

to wake-up the system. When a Port A pin wake-up oc-

curs, the program will resume execution at the instruc-

tion following the ²HALT² instruction.

·

The I/O ports will maintain their present condition.

In the status register, the Power Down flag, PDF, will

be set and the Watchdog time-out flag, TO, will be

cleared.

If the system is woken up by an interrupt, then two possi-

ble situations may occur. The first is where the related

interrupt is disabled or the interrupt is enabled but the

stack is full, in which case the program will resume exe-

cution at the instruction following the ²HALT² instruction.

In this situation, the interrupt which woke-up the device

will not be immediately serviced, but will rather be ser-

viced later when the related interrupt is finally enabled or

when a stack level becomes free. The other situation is

where the related interrupt is enabled and the stack is

not full, in which case the regular interrupt response

takes place. If an interrupt request flag is set to ²1² be-

fore entering the Power Down Mode, the wake-up func-

tion of the related interrupt will be disabled.

Standby Current Considerations

As the main reason for entering the Power Down Mode

is to keep the current consumption of the MCU to as low

a value as possible, perhaps only in the order of several

micro-amps, there are other considerations which must

also be taken into account by the circuit designer if the

power consumption is to be minimized. Special atten-

tion must be made to the I/O pins on the device. All

high-impedance input pins must be connected to either

a fixed high or low level as any floating input pins could

create internal oscillations and result in increased cur-

rent consumption. Care must also be taken with the

loads, which are connected to I/Os, which are setup as

Rev. 1.60

48

October 20, 2009

HT86BXX/HT86BRXX

No matter what the source of the wake-up event is, once

a wake-up situation occurs, a time period equal to 1024

system clock periods will be required before normal sys-

tem operation resumes. However, if the wake-up has

originated due to an interrupt, the actual interrupt sub-

routine execution will be delayed by an additional one or

more cycles. If the wake-up results in the execution of

the next instruction following the ²HALT² instruction, this

will be executed immediately after the 1024 system

clock period delay has ended.

source instead of the internal WDT oscillator. If the in-

struction clock is used as the clock source, it must be

noted that when the system enters the Power Down

Mode, as the system clock is stopped, then the WDT

clock source will also be stopped. Therefore the WDT

will lose its protecting purposes. In such cases the sys-

tem cannot be restarted by the WDT and can only be re-

started using external signals. For systems that operate

in noisy environments, using the internal WDT oscillator

is therefore the recommended choice.

Under normal program operation, a WDT time-out will

initialise a device reset and set the status bit TO. How-

ever, if the system is in the Power Down Mode, when a

WDT time-out occurs, only the Program Counter and

Stack Pointer will be reset. Three methods can be

adopted to clear the contents of the WDT and the WDT

prescaler. The first is an external hardware reset, which

means a low level on the RES pin, the second is using

the watchdog software instructions and the third is via a

²HALT² instruction.

Watchdog Timer

The Watchdog Timer is provided to prevent program

malfunctions or sequences from jumping to unknown lo-

cations, due to certain uncontrollable external events

such as electrical noise. It operates by providing a de-

vice reset when the WDT counter overflows. The WDT

clock is supplied by one of two sources selected by con-

figuration option: its own self-contained dedicated inter-

nal WDT oscillator, or the instruction clock which is the

system clock divided by 4. Note that if the WDT configu-

ration option has been disabled, then any instruction re-

lating to its operation will result in no operation.

There are two methods of using software instructions to

clear the Watchdog Timer, one of which must be chosen

by configuration option. The first option is to use the sin-

gle ²CLR WDT² instruction while the second is to use

the two commands ²CLR WDT1² and ²CLR WDT2². For

the first option, a simple execution of ²CLR WDT² will

clear the WDT while for the second option, both ²CLR

WDT1² and ²CLR WDT2² must both be executed to

successfully clear the WDT. Note that for this second

option, if ²CLR WDT1² is used to clear the WDT, succes-

sive executions of this instruction will have no effect,

only the execution of a ²CLR WDT2² instruction will

clear the WDT. Similarly, after the ²CLR WDT2² instruc-

tion has been executed, only a successive ²CLR WDT1²

instruction can clear the Watchdog Timer.

The internal WDT oscillator has an approximate period

of 65ms at a supply voltage of 5V. If selected, it is first di-

vided by 256 via an 8-stage counter to give a nominal

period of 17ms. Note that this period can vary with VDD,

temperature and process variations. For longer WDT

time-out periods the WDT prescaler can be utilized. By

writing the required value to bits 0, 1 and 2 of the WDTS

register, known as WS0, WS1 and WS2, longer time-out

periods can be achieved. With WS0, WS1 and WS2 all

equal to 1, the division ratio is 1:128 which gives a maxi-

mum time-out period of about 2.1s.

A configuration option can select the instruction clock,

which is the system clock divided by 4, as the WDT clock

b

7

b

0

W

S

2

W

S

W

1

S

0

W

D

T

S

R

e

g

i

s

t

e

r

W

D

T

p

r

e

s

c

a

l

e

r

a

t

e

s

W

S

2

S

1

W

S

0

W

D

T

R

a

t

e

0

1

0

1

0

1

0

1

0

1

0

1

0

1

:

1

2

4

8

1

:

1

6

1

:

3

6

1

2

4

2

8

N

o

t

u

s

e

d

Watchdog Timer Register

Rev. 1.60

49

October 20, 2009

HT86BXX/HT86BRXX

C

L

R

W

D

T

1

F

l

a

g

r

C

l

e

a

W

D

T

y

p

e

C

o

n

f

i

g u

g

r

a

t

i

o

n

O

p

t

i

o

n

C

L

R

W

D

T

2

F

l

a

1

o

r

2

I

n

s

t

r

u

c

t

i

o

n

s

C

L

R

C

L

R

f

S

Y

S

W

D

T

C

l

o

c

k

S

o

u

r

c

e

u

8

-

b

i

t

C

o

n

t

e

r

7

-

b

i

n

t

P

r

e

s

c

a

l

e

r

C

o

n

f

i

g

u

r

a

t

i

o

n

O

)

p

t

i

o

W

D

T

O

s

c

i

l

a

t

o

¸

2

5

6

(

W

D

T

C

l

o

c

k

S

o

u

r

c

e

W

S

0

X

~

W

S

2

8

-

t

o

-

1

M

U

W

D

T

i

m

e

-

o

u

t

Watchdog Timer

Voice Output

Voice Control

two sets of three registers to store this address, which

are LATCH0H/LATCH0M/LATCH0L and LATCH1H/

LATCH1M/LATCH1L. The 22-bit address stored in one

set of these three registers is used to access the 8-bit

voice code data in the Voice ROM. After the 8-bit Voice

ROM data is addressed, a few instruction cycles, of at

least 4us duration, are needed to latch the Voice ROM

data. After this the microcontroller can read the voice

data from the LATCHD register.

The voice control register controls the voice ROM circuit

and the DAC circuit and selects the Voice ROM latch

counter. If the DAC circuit is not enabled, any DAH/DAL

outputs will be invalid. Writing a ²1² to the DAC bit will

enable the enable DAC circuit, while writing a ²0² to the

DAC bit will disable the DAC circuit. If the voice ROM cir-

cuit is not enabled, then voice ROM data cannot be ac-

cessed. Writing a ²1² to the VROMC bit will enable the

voice ROM circuit, while writing a ²0² to the VROMC bit

is will disable the voice ROM circuit. The LATCH bit de-

termines which voice ROM address latch counter will be

used as the voice ROM address latch counter.

b

7

b

0

D

3

D

2

D

1

D

0

D

A

L

R

e

g

i

N

o

t

u

s

e

d

,

A

u

d

i

o

u

t

D

i

g

i

t

a

l

t

o

A

n

a

l

o

g

Audio Output and Volume Control - DAL, DAH, VOL

b

7

b

0

The audio output is 12-bits wide whose highest 8-bits

are written into the DAH register and whose lowest four

bits are written into the highest four bits of the DAL regis-

ter. Bits 0~3 of the DAL register are always read as zero.

There are 8 levels of volume which are setup using the

VOL register. Only the highest 3-bits of this register are

used for volume control, the other bits are not used and

read as zero.

D

1

D

1

0

D

7

9

D

6

8

D

5

A

D

H

4

R

e

g

i

A

u

d

i

o

u

t

D

i

g

i

t

a

l

t

o

A

n

a

l

o

g

b

7

b

0

V

O

L

2

V

O

L

1

V

O

L

0

V

O

L

R

e

g

i

U

s

e

d

b

y

P

N

o

t

u

s

e

d

,

D

A

v

o

l

u

m

Voice ROM Data Address Latch Counter

V

o

l

u

m

e

C

o

n

t

r

o

l

The Voice ROM address is 22-bits wide and therefore

requires three registers to store the address. There are

b

7

b

0

L

A

T

C

H

V

C

R

O

D

M

A

C

V

O

I

C

E

C

R

e

g

i

s

t

e

r

N

o

t

i

m

p

l

e

m

e

n

t

e

d

,

r

e

D

1

0

A

C

E

n

a

b

l

e

:

e

n

a

b

l

e

:

d

i

s

a

b

l

e

V

1

0

o

i

c

e

R

O

M

E

n

a

b

l

e

:

e

n

a

b

l

e

:

d

i

s

a

b

l

e

N

o

t

i

m

p

l

e

m

e

n

t

e

d

,

r

e

V

1

0

o

i

c

e

R

O

M

C

o

u

n

t

e

r

S

:

A

d

r

e

s

L

a

t

c

h

1

:

A

d

r

e

s

a

t

c

h

0

N

o

t

i

m

p

l

e

m

e

n

t

e

d

,

r

e

VOICE Control Register

Rev. 1.60

50

October 20, 2009

HT86BXX/HT86BRXX

Example: Read an 8-bit voice ROM data which is located at address 000007H by address latch 0

Set

mov

call

mov

[26H].2

A, 07H

; Enable voice ROM circuit

;

LATCH0L, A

A, 00H

; Set LATCH0L to 07H

;

LATCH0M, A

A, 00H

; Set LATCH0M to 00H

;

LATCH0H, A

Delay

; Set LATCH0H to 00H

; Delay a short period of time

; Get voice data at 000007H

A, LATCHD

Pulse Width Modulation Output

All device include a single 12-bit PWM function. The

PWM output is provided on two complimentary outputs

on the PWM1 and PWM2 pins. These two pins can di-

rectly drive a piezo buzzer or an 8 ohm speaker without

requiring any external components. The PWM1 output

can also be used alone to drive a piezo buzzer or an 8

ohm speaker without requiring external components.

When the single PWM1 output is chosen, which is

achieved by setting the Single_PWM bit in the PWMC

register.

P

W

M

1

S

p

e

a

k

e

r

P

W

M

2

0

.

m

0

F

1

*

0

.

m

0

F

1

*

N

o

t

"

e

*

"

:

F

o

r

e

d

u

c

i

n

g

t

h

e

c

a

u

s

e

,

c

a

n

c

o

n

s

i

d

e

r

b

7

b

0

P

3

P

2

P

1

P

0

P

W

M

L

R

e

g

i

N

P

o

t

u

s

e

d

,

The PWM output will initially be at a low level, and if

stopped will also return to a low level. If the PWMCC bit

changes from low to high then the PWM function will

start and latch new data. If the data is not updated then

the old value will remain. If the PWMCC bit changes

from high to low, at the end of the duty cycle, the PWM

output will stop.

W

M

o

u

t

p

u

P

u

l

s

e

W

i

d

t

h

M

o

d

u

l

a

b

7

b

0

P

1

P

1

0

P

7

9

P

6

8

P

5

W

P

M

4

H

R

e

g

P

W

M

o

u

t

p

u

P

u

l

s

e

W

i

d

t

h

M

o

d

u

l

a

b

7

b

0

V

O

L

V

6

O

L

V

5

O

L

V

4

O

L

V

3

O

L

R

e

g

i

s

t

e

r

P

W

M

v

o

l

u

m

e

c

o

n

t

r

o

l

d

a

t

a

V

O

L

V

6

O

L

V

5

O

L

V

4

O

L

3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P

W

M

v

o

l

u

m

e

l

e

v

e

l

1

2

3

4

5

6

P

W

M

v

o

l

u

m

e

P

W

M

v

o

l

u

m

e

P

W

M

v

o

l

u

m

e

P

W

M

v

o

l

u

m

e

P

W

M

v

o

l

u

m

e

P

W

M

v

l

o

e

l

v

u

e

m

l

e

7

x

l

e

v

e

l

8

N

U

o

s

t

u

s

e

d

,

r

e

a

d

a

s

"

0

"

e

d

b

y

D

A

o

u

t

p

u

t

Volume Control Register

b

7

b

0

S

i

n

g

l

e

_

P

W

M

P

W

M

C

P

C

W

M

C

R

e

g

i

s

t

e

r

P

1

0

W

M

E

n

a

b

l

e

:

e

d

n

i

a

b

l

e

s

a

b

l

e

N

o

t

i

m

p

l

e

m

e

n

t

e

d

,

r

S

1

0

i

n

g

l

e

a

P

W

M

O

u

t

p

u

t

:

s

d

i

n

g

l

e

o

u

t

p

u

t

u

p

u

l

t

s

o

u

N

o

t

i

m

p

l

e

m

e

n

t

e

d

,

r

Pulse Width Modulator Control Register

Rev. 1.60

51

October 20, 2009

HT86BXX/HT86BRXX

External RC Oscillation Converter

An external RC oscillation converter is implemented in

certain devices and is a function which allows analog

switch functions to be implemented. When used in con-

junction with the Analog Switch function up to eight

C/R-F can be implemented.

TMR4L and RCOCR. The internal timer clock is the in-

put clock source for TMR2H and TMR2L, while the ex-

ternal RC oscillator is the clock source input to TMR4H

and TMR4L. The OVB bit, which is bit 0 of the RCOCR

register, decides whether the timer interrupt is sourced

from either the Timer 2 overflows or Timer 4 overflow.

When a timer overflow occurs, the T2F bit is set and an

external RC oscillation converter interrupt occurs. When

the RC oscillation converter Timer 2 or Timer 4 over-

flows, the RCOCON bit is automatically reset to zero

and stops counting.

External RC Oscillation Converter Operation

The RC oscillation converter is composed of two 16-bit

count-up programmable timers. One is Timer 2, de-

scribed in the Timer section and the other is an addi-

tional counter known as Timer 4. The RC oscillation

converter is enabled when the RCO bit, which is bit 1 of

the RCOCR register, is set high. The RC oscillation con-

verter will then be composed of four registers, TMR2L,

TMR2H, TMR4L and TMR4H. The Timer 2 clock source

comes from the system clock or from the system

clock/4, the choice of which is determined by bits in the

RCOCCR register. The RC oscillation converter Timer 4

clock source comes from an external RC oscillator. As

the oscillation frequency is dependent upon external ca-

pacitance and resistance values, it can therefore be

used to detect the increased capacitance of a analog

switch pad.

The resistor and capacitor form an oscillation circuit and

input to TMR4H and TMR4L. The RCOM0, RCOM1 and

RCOM2 bits of RCOCCR define the clock source of

Timer 2.

When the RCOCON bit, which is bit 4 of the RCOCCR

register, is set high, Timer 2 and Timer 4 will start count-

ing until Timer 2 or Timer 4 overflows. Now the timer

counter will generate an interrupt request flag which is

bit T2F, bit 4 of the INTCH register. Both Timer 2 and

Timer 4 will then stop counting and the RCOCON bit will

automatically be reset to "0" at the same time. Note that

if the RCOCON bit is high, the TMR2H, TMR2L, TMR4H

and TMR4L registers cannot be read or written to.

There are six registers related to the RC oscillation con-

verter. These are, TMR2H, TMR2L, RCOCCR, TMR4H,

b

7

b

0

R

C

O

R

M

C

2

O

M

1

R

C

O

M

0

R

C

O

C

O

N

R

C

O

C

R

e

g

i

s

t

e

r

U

n

d

e

f

i

n

e

d

,

r

e

a

d

a

s

z

R

1

0

C

O

s

c

i

l

a

t

o

r

C

o

n

v

e

r

:

E

n

a

b

l

e

:

D

i

s

a

b

l

e

T

i

m

e

r

2

C

l

o

c

k

S

o

u

r

c

e

R

C

O

M

R

2

C

O

M

R

1

C

O

M

0

1

0

1

0

f

:

U

S

Y

S

/

4

:

1

n

d

e

f

i

n

e

RCOCCR Register

b

7

b

0

R

C

O

V

B

C

R

O

C

R

e

g

i

s

t

e

r

I

1

0

n

t

e

T

r

u

p

t

S

o

u

r

c

e

:

i

m

e

r

4

o

v

e

r

f

l

o

i

m

r

2

o

v

e

r

f

l

o

R

1

0

C

o

n

v

e

r

t

e

r

M

o

d

:

E

D

n

a

b

l

e

i

s

a

b

l

e

U

n

d

e

f

i

n

e

d

,

r

e

a

d

a

RCOCR Register

Rev. 1.60

52

October 20, 2009

HT86BXX/HT86BRXX

R

C

O

M

O

B

i

t

O

V

B

=

0

f

S

Y

S

C

l

o

c

k

T

i

m

e

r

2

E

x

t

e

r

n

a

l

R

C

O

s

c

i

l

a

t

S

e

l

e

c

t

f

S

Y

S

R

C

O

C

O

N

O

V

B

=

1

T

i

m

e

r

4

R

e

s

e

t

R

C

O

C

O

N

R

C

O

S

C

O

u

t

p

u

t

Programming Considerations

the data in the low byte buffer will be transferred into its

associated low byte register. For this reason, when

preloading data into the 16-bit timer registers, the low

byte should be written first. It must also be noted that to

read the contents of the low byte register, a read to the

high byte register must first be executed to latch the con-

tents of the low byte buffer into its associated low byte

register. After this has been done, the low byte register

can be read in the normal way. Note that reading the low

byte timer register will only result in reading the previ-

ously latched contents of the low byte buffer and not the

actual contents of the low byte timer register.

As the 16-bit Timers have both low byte and high byte

timer registers, accessing these registers is carried out

in a specific way. It must be noted that when using in-

structions to preload data into the low byte registers,

namely TMR2L or TMR4L, the data will only be placed

into a low byte buffer and not directly into the low byte

register. The actual transfer of the data into the low byte

register is only carried out when a write to its associated

high byte register, namely TMR2H or TMR4H, is exe-

cuted. However, using instructions to preload data into

the high byte timer register will result in the data being

directly written to the high byte register. At the same time

Program Example

External RC oscillation converter mode example program - Timer 2 overflow:

clr

RCOCCR

mov

a, 00000010b

; Enable External RC oscillation mode and set Timer 2

; overflow interrupt

mov

clr

RCOCR,a

intch.4

; Clear External RC Oscillation Converter interrupt

; request flag

mov

p10:

clr

snz

a, low (65536-1000); Give timer 2 initial value

Tmr2l, a

; Timer 2 count 1000 time and then overflow

a, high (65536-1000)

Tmr2h, a

a, 00h

; Give timer 4 initial value

Tmr4l, a

a, 00h

Tmr4h, a

a, 00110000b

RCOCCR, a

; Timer 2 clock source=fSYS/4 and timer on

Wdt

intch.4

; Polling External RC Oscillation Converter interrupt

; request flag

jmp

clr

p10

intch.4

; Clear External RC Oscillation Converter interrupt

; request flag

; Program continue

Rev. 1.60

53

October 20, 2009

HT86BXX/HT86BRXX

Analog Switch

There are 8 analog switch lines in the microcontroller, labeled as K0 ~ K7, and the Analog Switch control register, which

is mapped to the data memory by option. All of these Analog Switch lines can be used together with the external RC

Oscillation Converter for C/R-F input keys.

b

7

b

0

A

S

O

A

N

S

3

O

N

2

A

S

O

N

1

A

S

O

N

0

e g

A

S

C

R

i

s

t

e

r

A

n

a

l

o

g

S

w

i

t

c

h

S

e

l

e

c

t

A

S

O

A

N

S

3

O

A

N

S

2

O

A

N

S

1

O

N

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K

0

o

n

,

o

t

K

1

o

n

,

o

t

K

2

o

n

,

o

t

K

3

o

n

,

o

t

K

4

o

n

,

o

t

K

5

o

n

,

o

t

K

A

6

7

l

o

n

,

o

t

X

l

o

f

,

O

U

n

d

e

f

i

n

e

d

,

r

e

a

d

a

s

z

e

r

Analog Switch Control Register - ASCR

A

S

O

N

K

0

1

2

3

4

5

6

7

T

.

G

.

1

2

3

4

5

6

7

8

R

C

O

U

T

R

C

R

C

T

i

m

e

r

4

Analog Switch

Rev. 1.60

54

October 20, 2009

HT86BXX/HT86BRXX

Configuration Options

Configuration options refer to certain options within the MCU that are programmed into the device during the program-

ming process. During the development process, these options are selected using the HT-IDE software development

tools. As these options are programmed into the device using the hardware programming tools, once they are selected

they cannot be changed later by the application software.

No.

HT86B05/HT86B10/HT86BR10/HT86B20/HT86B30/HT86BR30 Options

I/O Options

1

2

3

PA0~PA7: wake-up enable or disable (bit option)

PA0~PA7: pull-high enable or disable (bit option)

PB0~PB7: pull-high enable or disable (bit option)

Oscillation Option

4

OSC type selection: RC or crystal

Interrupt Option

5

INT Triggering edge: Falling or both

Watchdog Options

6

7

8

WDT: enable or disable

WDT clock source: WDROSC or T1

CLRWDT instructions: 1 or 2 instructions

Low Voltage Reset Option

9

LVR select: enable or disable

No.

HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90 Options

I/O Options

1

2

3

4

5

6

PA0~PA7: wake-up enable or disable

PA0~PA7: pull-high enable or disable

PB0~PB7: pull-high enable or disable

PD0~PD7: pull-high enable or disable

PB share pin select: PB0~7 or K0~7

PD share pin select: PD4~7 or external RC oscillation converter pin

Oscillation Option

7

OSC type selection: RC or crystal

Interrupt Option

8

INT Triggering edge: Falling or both

Watchdog Options

9

WDT: enable or disable

10 WDT clock source: WDROSC or T1

11 CLRWDT instructions: 1 or 2 instructions

Low Voltage Reset Option

12 LVR select: enable or disable

Rev. 1.60

55

October 20, 2009

HT86BXX/HT86BRXX

Application Circuits

T

r

a

n

s

i

s

t

o

r

O

u

t

p

u

t

D

V

D

V

D

1

W

0

S

P

K

0

.

m

F

1

(

W

8

/

W

1 ) 6

4

m

7 F

0

m

. F 1

8

0

5

0

A

U

D

V

D

A

V

D

P

R

1

R

2

O

S

C

2

1

V

D

R

O

S

C

V

D

P

o

w

e

r

A

m

p

l

i

f

i

e

r

O

u

t

p

u

t

1

m

0 F 0

1

0

W

0

k

C

E

P

A

B

0

~

P

A

B

7

1

5

V

D

R

E

S

O

U

T

N

A

U

D

8

0

m

. F 1

V

D

V

D

0

m

. F 1

2

3

A

u

d

i

o

I

n

A

U

D

S

P

K

H

T

8

2

V

7

3

(

W

8

/

W

1 ) 6

4

m

7 F

V

R

E

F

V

S

4

1

m

0 F

V

S

A

N

C

O

U

T

P

I

N

T

V

S

P

6

7

H

T

8

6

B

0

2

5

0

/

H

T

8

6

B

1

3

0

/

H

T

8

6

B

R

1

3

0

T

B

V

D

4

m

7 F

V

D

A

V

D

P

O

S

C

2

1

4

M

H

z

~

8

M

H

V

D

V

D

P

A

B

0

~

P

A

B

7

1

m

0 F 0

1

0

W

0

k

R

E

S

V

S

V

S

A

V

D

0

m

. F 1

V

S

P

W

M

1

S

P

K

I

N

T

P

W

M

2

(

W

8

/

1

W

)

6

H

T

8

6

B

0

2

5

0

/

H

T

8

6

B

1

3

0

/

H

T

8

6

B

R

1

3

0

T

B

N

o

t

e

:

T

h

e

P

W

M

a

p

l

i

c

a

t

i

o

n

r

e

f

e

r

t

o

t

h

e

d

e

s

c

r

i

p

t

i

o

n

o

f

P

u

Rev. 1.60

56

October 20, 2009

HT86BXX/HT86BRXX

T

r

a

n

s

i

s

t

o

r

O

u

t

p

u

t

D

V

D

V

D

1

W

0

S

P

K

0

.

m

F

1

(

W

8

/

W

1 ) 6

4

m

7 F

0

m

. F 1

8

0

5

0

A

U

D

V

D

A

V

D

P

R

1

O

S

C

2

1

R

2

V

D

R

O

S

C

V

D

P

o

w

e

r

A

m

p

l

i

f

i

e

r

O

u

t

p

u

t

1

m

0 F 0

P

A

B

0

~

P

A

B

7

1

0

W

0

k

C

E

1

5

V

D

R

E

S

O

U

T

N

A

U

D

8

P

D

4

~

P

D

0

m

. F 1

V

D

V

D

0

m

. F 1

2

3

A

u

d

i

o

I

n

S

P

K

A

U

D

H

T

8

2

V

7

3

(

W

8

/

W

1 ) 6

4

m

7 F

V

R

E

F

V

S

4

1

m

0 F

V

S

A

N

C

O

U

T

P

I

N

T

V

S

P

6

7

H

T

8

6

B

4

0

/

H

T

8

6

B

5

0

/

H

T

8

6

B

6

0

/

H

T

8

6

B

R

6

0

V

D

4

m

7 F

V

D

A

V

D

P

O

S

C

2

1

4

M

H

z

~

8

M

H

z

V

D

V

D

P

A

B

0

~

P

A

B

7

1

m

0 F 0

1

0

W

0

k

P

D

4

~

P

D

R

E

S

V

S

V

D

0

m

. F 1

V

S

A

V

S

P

S

P

K

P

W

M

1

I

N

T

P

W

M

2

(

W

8

/

W

1 ) 6

H

T

8

6

B

4

0

/

H

T

8

6

B

5

0

/

H

T

8

6

B

6

0

/

H

T

8

6

B

R

6

0

N

o

t

e

:

T

h

e

P

W

M

a

p

l

i

c

a

t

d

i

t

o

h

n

M

r

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Rev. 1.60

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Instruction Set

Introduction

subtract instruction mnemonics to enable the necessary

arithmetic to be carried out. Care must be taken to en-

sure correct handling of carry and borrow data when re-

sults exceed 255 for addition and less than 0 for

subtraction. The increment and decrement instructions

INC, INCA, DEC and DECA provide a simple means of

increasing or decreasing by a value of one of the values

in the destination specified.

Central to the successful operation of any

microcontroller is its instruction set, which is a set of pro-

gram instruction codes that directs the microcontroller to

perform certain operations. In the case of Holtek

microcontrollers, a comprehensive and flexible set of

over 60 instructions is provided to enable programmers

to implement their application with the minimum of pro-

gramming overheads.

Logical and Rotate Operations

For easier understanding of the various instruction

codes, they have been subdivided into several func-

tional groupings.

The standard logical operations such as AND, OR, XOR

and CPL all have their own instruction within the Holtek

microcontroller instruction set. As with the case of most

instructions involving data manipulation, data must pass

through the Accumulator which may involve additional

programming steps. In all logical data operations, the

zero flag may be set if the result of the operation is zero.

Another form of logical data manipulation comes from

the rotate instructions such as RR, RL, RRC and RLC

which provide a simple means of rotating one bit right or

left. Different rotate instructions exist depending on pro-

gram requirements. Rotate instructions are useful for

serial port programming applications where data can be

rotated from an internal register into the Carry bit from

where it can be examined and the necessary serial bit

set high or low. Another application where rotate data

operations are used is to implement multiplication and

division calculations.

Instruction Timing

Most instructions are implemented within one instruc-

tion cycle. The exceptions to this are branch, call, or ta-

ble read instructions where two instruction cycles are

required. One instruction cycle is equal to 4 system

clock cycles, therefore in the case of an 8MHz system

oscillator, most instructions would be implemented

within 0.5ms and branch or call instructions would be im-

plemented within 1ms. Although instructions which re-

quire one more cycle to implement are generally limited

to the JMP, CALL, RET, RETI and table read instruc-

tions, it is important to realize that any other instructions

which involve manipulation of the Program Counter Low

register or PCL will also take one more cycle to imple-

ment. As instructions which change the contents of the

PCL will imply a direct jump to that new address, one

more cycle will be required. Examples of such instruc-

tions would be ²CLR PCL² or ²MOV PCL, A². For the

case of skip instructions, it must be noted that if the re-

sult of the comparison involves a skip operation then

this will also take one more cycle, if no skip is involved

then only one cycle is required.

Branches and Control Transfer

Program branching takes the form of either jumps to

specified locations using the JMP instruction or to a sub-

routine using the CALL instruction. They differ in the

sense that in the case of a subroutine call, the program

must return to the instruction immediately when the sub-

routine has been carried out. This is done by placing a

return instruction RET in the subroutine which will cause

the program to jump back to the address right after the

CALL instruction. In the case of a JMP instruction, the

program simply jumps to the desired location. There is

no requirement to jump back to the original jumping off

point as in the case of the CALL instruction. One special

and extremely useful set of branch instructions are the

conditional branches. Here a decision is first made re-

garding the condition of a certain data memory or indi-

vidual bits. Depending upon the conditions, the program

will continue with the next instruction or skip over it and

jump to the following instruction. These instructions are

the key to decision making and branching within the pro-

gram perhaps determined by the condition of certain in-

put switches or by the condition of internal data bits.

Moving and Transferring Data

The transfer of data within the microcontroller program

is one of the most frequently used operations. Making

use of three kinds of MOV instructions, data can be

transferred from registers to the Accumulator and

vice-versa as well as being able to move specific imme-

diate data directly into the Accumulator. One of the most

important data transfer applications is to receive data

from the input ports and transfer data to the output ports.

Arithmetic Operations

The ability to perform certain arithmetic operations and

data manipulation is a necessary feature of most

microcontroller applications. Within the Holtek

microcontroller instruction set are a range of add and

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Bit Operations

Other Operations

The ability to provide single bit operations on Data Mem-

ory is an extremely flexible feature of all Holtek

microcontrollers. This feature is especially useful for

output port bit programming where individual bits or port

pins can be directly set high or low using either the ²SET

[m].i² or ²CLR [m].i² instructions respectively. The fea-

ture removes the need for programmers to first read the

8-bit output port, manipulate the input data to ensure

that other bits are not changed and then output the port

with the correct new data. This read-modify-write pro-

cess is taken care of automatically when these bit oper-

ation instructions are used.

In addition to the above functional instructions, a range

of other instructions also exist such as the ²HALT² in-

struction for Power-down operations and instructions to

control the operation of the Watchdog Timer for reliable

program operations under extreme electric or electro-

magnetic environments. For their relevant operations,

refer to the functional related sections.

Instruction Set Summary

The following table depicts a summary of the instruction

set categorised according to function and can be con-

sulted as a basic instruction reference using the follow-

ing listed conventions.

Table Read Operations

Table conventions:

Data storage is normally implemented by using regis-

ters. However, when working with large amounts of

fixed data, the volume involved often makes it inconve-

nient to store the fixed data in the Data Memory. To over-

come this problem, Holtek microcontrollers allow an

area of Program Memory to be setup as a table where

data can be directly stored. A set of easy to use instruc-

tions provides the means by which this fixed data can be

referenced and retrieved from the Program Memory.

x: Bits immediate data

m: Data Memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Mnemonic

Arithmetic

Description

Cycles Flag Affected

ADD A,[m]

ADDM A,[m]

ADD A,x

Add Data Memory to ACC

1

1^Note

1

Z, C, AC, OV

C

Add ACC to Data Memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add Data Memory to ACC with Carry

1

1^Note

Add ACC to Data memory with Carry

Subtract immediate data from the ACC

Subtract Data Memory from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

1

1^Note

Subtract Data Memory from ACC with result in Data Memory

Subtract Data Memory from ACC with Carry

Subtract Data Memory from ACC with Carry, result in Data Memory

Decimal adjust ACC for Addition with result in Data Memory

1

1^Note

Logic Operation

AND A,[m]

OR A,[m]

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

Logical AND Data Memory to ACC

Logical OR Data Memory to ACC

Logical XOR Data Memory to ACC

Logical AND ACC to Data Memory

Logical OR ACC to Data Memory

Logical XOR ACC to Data Memory

Logical AND immediate Data to ACC

Logical OR immediate Data to ACC

Logical XOR immediate Data to ACC

Complement Data Memory

1

Z

1

1^Note

1

OR A,x

1

XOR A,x

1

1^Note

CPL [m]

CPLA [m]

Complement Data Memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment Data Memory with result in ACC

1

Z

Increment Data Memory

1^Note

DECA [m]

DEC [m]

Decrement Data Memory with result in ACC

Decrement Data Memory

1

1^Note

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Mnemonic

Rotate

Description

Cycles Flag Affected

RRA [m]

RR [m]

Rotate Data Memory right with result in ACC

Rotate Data Memory right

1

1^Note

1

1^Note

1

1^Note

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate Data Memory right through Carry with result in ACC

Rotate Data Memory right through Carry

Rotate Data Memory left with result in ACC

Rotate Data Memory left

C

None

C

RLCA [m]

RLC [m]

Rotate Data Memory left through Carry with result in ACC

Rotate Data Memory left through Carry

1

1^Note

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move Data Memory to ACC

Move ACC to Data Memory

Move immediate data to ACC

1

1^Note

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of Data Memory

Set bit of Data Memory

1^Note

None

Branch

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if Data Memory is zero

1^Note

1^note

1^Note

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if Data Memory is zero with data movement to ACC

Skip if bit i of Data Memory is zero

Skip if bit i of Data Memory is not zero

Skip if increment Data Memory is zero

Skip if decrement Data Memory is zero

Skip if increment Data Memory is zero with result in ACC

Skip if decrement Data Memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC [m]

TABRDL [m]

Read table (current page) to TBLH and Data Memory

Read table (last page) to TBLH and Data Memory

2^Note

None

Miscellaneous

NOP

No operation

1

1^Note

1

None

CLR [m]

Clear Data Memory

SET [m]

Set Data Memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO, PDF

None

Pre-clear Watchdog Timer

Swap nibbles of Data Memory

Swap nibbles of Data Memory with result in ACC

Enter power down mode

1

1^Note

1

None

1

TO, PDF

Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,

if no skip takes place only one cycle is required.

2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.

3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by

the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and

²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags

remain unchanged.

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Instruction Definition

ADC A,[m]

Add Data Memory to ACC with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the Accumulator.

Operation

ACC ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADCM A,[m]

Add ACC to Data Memory with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADD A,[m]

Add Data Memory to ACC

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

ADD A,x

Add immediate data to ACC

Description

The contents of the Accumulator and the specified immediate data are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + x

Affected flag(s)

OV, Z, AC, C

ADDM A,[m]

Add ACC to Data Memory

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

AND A,[m]

Logical AND Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

Z

AND A,x

Logical AND immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical AND

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

Z

ANDM A,[m]

Logical AND ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

Z

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CALL addr

Subroutine call

Description

Unconditionally calls a subroutine at the specified address. The Program Counter then in-

crements by 1 to obtain the address of the next instruction which is then pushed onto the

stack. The specified address is then loaded and the program continues execution from this

new address. As this instruction requires an additional operation, it is a two cycle instruc-

tion.

Operation

Stack ¬ Program Counter + 1

Program Counter ¬ addr

Affected flag(s)

None

CLR [m]

Clear Data Memory

Description

Operation

Each bit of the specified Data Memory is cleared to 0.

[m] ¬ 00H

Affected flag(s)

None

CLR [m].i

Clear bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

None

CLR WDT

Description

Operation

Clear Watchdog Timer

The TO, PDF flags and the WDT are all cleared.

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT1

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT2 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT2

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT1 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

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CPL [m]

Complement Data Memory

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa.

Operation

[m] ¬ [m]

Affected flag(s)

Z

CPLA [m]

Complement Data Memory with result in ACC

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa. The complemented result

is stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

Z

DAA [m]

Decimal-Adjust ACC for addition with result in Data Memory

Description

Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-

sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or

if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble

remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of

6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-

ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C

flag may be affected by this instruction which indicates that if the original BCD sum is

greater than 100, it allows multiple precision decimal addition.

Operation

[m] ¬ ACC + 00H or

[m] ¬ ACC + 06H or

[m] ¬ ACC + 60H or

[m] ¬ ACC + 66H

Affected flag(s)

C

DEC [m]

Decrement Data Memory

Description

Operation

Data in the specified Data Memory is decremented by 1.

[m] ¬ [m] - 1

Affected flag(s)

Z

DECA [m]

Decrement Data Memory with result in ACC

Description

Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-

mulator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] - 1

Affected flag(s)

Z

HALT

Enter power down mode

Description

This instruction stops the program execution and turns off the system clock. The contents

of the Data Memory and registers are retained. The WDT and prescaler are cleared. The

power down flag PDF is set and the WDT time-out flag TO is cleared.

Operation

TO ¬ 0

PDF ¬ 1

Affected flag(s)

TO, PDF

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INC [m]

Increment Data Memory

Description

Operation

Data in the specified Data Memory is incremented by 1.

[m] ¬ [m] + 1

Affected flag(s)

Z

INCA [m]

Increment Data Memory with result in ACC

Description

Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-

lator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] + 1

Affected flag(s)

Z

JMP addr

Jump unconditionally

Description

The contents of the Program Counter are replaced with the specified address. Program

execution then continues from this new address. As this requires the insertion of a dummy

instruction while the new address is loaded, it is a two cycle instruction.

Operation

Program Counter ¬ addr

Affected flag(s)

None

MOV A,[m]

Description

Operation

Move Data Memory to ACC

The contents of the specified Data Memory are copied to the Accumulator.

ACC ¬ [m]

Affected flag(s)

None

MOV A,x

Move immediate data to ACC

Description

Operation

The immediate data specified is loaded into the Accumulator.

ACC ¬ x

Affected flag(s)

None

MOV [m],A

Description

Operation

Move ACC to Data Memory

The contents of the Accumulator are copied to the specified Data Memory.

[m] ¬ ACC

Affected flag(s)

None

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

No operation

None

OR A,[m]

Logical OR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-

ation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

Z

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OR A,x

Logical OR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

Z

ORM A,[m]

Logical OR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-

ation. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²OR² [m]

Affected flag(s)

Z

RET

Return from subroutine

Description

The Program Counter is restored from the stack. Program execution continues at the re-

stored address.

Operation

Program Counter ¬ Stack

Affected flag(s)

None

RET A,x

Return from subroutine and load immediate data to ACC

Description

The Program Counter is restored from the stack and the Accumulator loaded with the

specified immediate data. Program execution continues at the restored address.

Operation

Program Counter ¬ Stack

ACC ¬ x

Affected flag(s)

None

RETI

Return from interrupt

Description

The Program Counter is restored from the stack and the interrupts are re-enabled by set-

ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending

when the RETI instruction is executed, the pending Interrupt routine will be processed be-

fore returning to the main program.

Operation

Program Counter ¬ Stack

EMI ¬ 1

Affected flag(s)

None

RL [m]

Rotate Data Memory left

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ [m].7

Affected flag(s)

None

RLA [m]

Rotate Data Memory left with result in ACC

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-

main unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ [m].7

Affected flag(s)

None

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RLC [m]

Rotate Data Memory left through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7

replaces the Carry bit and the original carry flag is rotated into bit 0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RLCA [m]

Rotate Data Memory left through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces

the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in

the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RR [m]

Rotate Data Memory right

Description

The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into

bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ [m].0

Affected flag(s)

None

RRA [m]

Rotate Data Memory right with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-

tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data

Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ [m].0

Affected flag(s)

None

RRC [m]

Rotate Data Memory right through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0

replaces the Carry bit and the original carry flag is rotated into bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

C

RRCA [m]

Rotate Data Memory right through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-

places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is

stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

C

Rev. 1.60

67

October 20, 2009

HT86BXX/HT86BRXX

SBC A,[m]

Subtract Data Memory from ACC with Carry

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result

of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or

zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SBCM A,[m]

Subtract Data Memory from ACC with Carry and result in Data Memory

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-

sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is

positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SDZ [m]

Skip if decrement Data Memory is 0

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0 the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] - 1

Skip if [m] = 0

Affected flag(s)

None

SDZA [m]

Skip if decrement Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0, the program proceeds with the following instruction.

Operation

ACC ¬ [m] - 1

Skip if ACC = 0

Affected flag(s)

None

SET [m]

Set Data Memory

Description

Operation

Each bit of the specified Data Memory is set to 1.

[m] ¬ FFH

Affected flag(s)

None

SET [m].i

Set bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is set to 1.

[m].i ¬ 1

Affected flag(s)

None

Rev. 1.60

68

October 20, 2009

HT86BXX/HT86BRXX

SIZ [m]

Skip if increment Data Memory is 0

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] + 1

Skip if [m] = 0

Affected flag(s)

None

SIZA [m]

Skip if increment Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0 the program proceeds with the following instruction.

Operation

ACC ¬ [m] + 1

Skip if ACC = 0

Affected flag(s)

None

SNZ [m].i

Skip if bit i of Data Memory is not 0

Description

If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is 0 the program proceeds with the following instruction.

Operation

Skip if [m].i ¹ 0

Affected flag(s)

None

SUB A,[m]

Subtract Data Memory from ACC

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUBM A,[m]

Subtract Data Memory from ACC with result in Data Memory

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUB A,x

Subtract immediate data from ACC

Description

The immediate data specified by the code is subtracted from the contents of the Accumu-

lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-

tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will

be set to 1.

Operation

ACC ¬ ACC - x

Affected flag(s)

OV, Z, AC, C

Rev. 1.60

69

October 20, 2009

HT86BXX/HT86BRXX

SWAP [m]

Description

Operation

Swap nibbles of Data Memory

The low-order and high-order nibbles of the specified Data Memory are interchanged.

[m].3~[m].0 « [m].7 ~ [m].4

Affected flag(s)

None

SWAPA [m]

Swap nibbles of Data Memory with result in ACC

Description

The low-order and high-order nibbles of the specified Data Memory are interchanged. The

result is stored in the Accumulator. The contents of the Data Memory remain unchanged.

Operation

ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4

ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0

Affected flag(s)

None

SZ [m]

Skip if Data Memory is 0

Description

If the contents of the specified Data Memory is 0, the following instruction is skipped. As

this requires the insertion of a dummy instruction while the next instruction is fetched, it is a

two cycle instruction. If the result is not 0 the program proceeds with the following instruc-

tion.

Operation

Skip if [m] = 0

None

Affected flag(s)

SZA [m]

Skip if Data Memory is 0 with data movement to ACC

Description

The contents of the specified Data Memory are copied to the Accumulator. If the value is

zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-

tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the

program proceeds with the following instruction.

Operation

ACC ¬ [m]

Skip if [m] = 0

Affected flag(s)

None

SZ [m].i

Skip if bit i of Data Memory is 0

Description

If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is not 0, the program proceeds with the following instruction.

Operation

Skip if [m].i = 0

None

Affected flag(s)

TABRDC [m]

Read table (current page) to TBLH and Data Memory

Description

The low byte of the program code (current page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

TABRDL [m]

Read table (last page) to TBLH and Data Memory

Description

The low byte of the program code (last page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

Rev. 1.60

70

October 20, 2009

HT86BXX/HT86BRXX

XOR A,[m]

Logical XOR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XORM A,[m]

Logical XOR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XOR A,x

Logical XOR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical XOR

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

Z

Rev. 1.60

71

October 20, 2009

HT86BXX/HT86BRXX

Package Information

24-pin SSOP (150mil) Outline Dimensions

2

4

1

3

A

B

1

2

C

'

G

H

D

a

E

F

Dimensions in mil

Symbol

Min.

228

150

8

Nom.

¾

Max.

244

157

12

A

B

C

C¢

D

E

F

¾

335

54

¾

346

60

¾

25

¾

4

10

¾

G

H

a

22

7

28

10

0°

8°

Rev. 1.60

72

October 20, 2009

HT86BXX/HT86BRXX

24-pin SSOP (209mil) Outline Dimensions

2

4

1

3

A

B

1

2

C

'

G

H

D

a

E

F

·

MO-150

Dimensions in mm

Symbol

Min.

7.40

5.00

0.22

7.90

¾

Nom.

¾

Max.

8.20

5.60

0.33

8.50

2.00

¾

A

B

C

C¢

D

E

F

¾

0.65

¾

0.05

0.55

0.09

0°

¾

G

H

a

0.95

0.21

8°

¾

Rev. 1.60

73

October 20, 2009

HT86BXX/HT86BRXX

28-pin SOP (300mil) Outline Dimensions

2

8

1

5

A

B

1

4

C

'

G

H

D

a

E

F

·

MS-013

Dimensions in mil

Symbol

Min.

393

256

12

697

¾

Nom.

¾

Max.

419

300

20

A

B

C

C¢

D

E

F

¾

713

104

¾

50

¾

4

12

¾

G

H

a

16

8

50

13

0°

8°

Rev. 1.60

74

October 20, 2009

HT86BXX/HT86BRXX

44-pin QFP (10mm´10mm) Outline Dimensions

C

H

D

G

3

2

3

I

3

4

2

L

F

A

B

E

1

2

4

a

K

J

1

Dimensions in mm

Symbol

Min.

13.0

9.9

13.0

9.9

¾

Nom.

¾

Max.

13.4

10.1

13.4

10.1

¾

A

B

C

D

E

F

G

H

I

¾

0.8

0.3

¾

1.9

¾

2.2

¾

0.1

¾

2.7

0.25

0.73

0.1

¾

0.50

0.93

0.2

J

K

L

¾

a

0°

7°

Rev. 1.60

75

October 20, 2009

HT86BXX/HT86BRXX

100-pin QFP (14mm´20mm) Outline Dimensions

C

H

D

G

8

0

5

1

I

8

1

5

0

F

A

B

E

1

0

3

1

a

K

J

1

3

0

Dimensions in mm

Symbol

Min.

18.5

13.9

24.5

19.9

¾

Nom.

¾

Max.

19.2

14.1

25.2

20.1

¾

A

B

C

D

E

F

G

H

I

¾

0.65

0.30

¾

2.5

¾

3.1

3.4

¾

0.1

¾

J

1.0

0.1

0°

1.4

0.2

7°

K

a

Rev. 1.60

76

October 20, 2009

HT86BXX/HT86BRXX

Product Tape and Reel Specifications

Reel Dimensions

D

T

2

C

A

B

T

1

SSOP 24S (150mil)

Symbol

Description

Dimensions in mm

A

B

Reel Outer Diameter

Reel Inner Diameter

Spindle Hole Diameter

Key Slit Width

330.0±1.0

100.0±1.5

13^+0.5/-0.2

C

D

2.0±0.5

16.8^+0.3/-0.2

T1

T2

Space Between Flange

Reel Thickness

22.2±0.2

SOP 28W (300mil)

Symbol

Description

Reel Outer Diameter

Reel Inner Diameter

Dimensions in mm

A

B

330.0±1.0

100.0±1.5

13^+0.5/-0.2

C

Spindle Hole Diameter

Key Slit Width

D

2.0±0.5

24.8^+0.3/-0.2

T1

T2

Space Between Flange

Reel Thickness

30.2±0.2

Rev. 1.60

77

October 20, 2009

HT86BXX/HT86BRXX

Carrier Tape Dimensions

P

0

P

1

t

D

E

F

W

B

0

C

D

1

P

K

0

A

0

R

e

l

H

o

l

e

I

C

p

a

c

k

a

g

e

p

i

n

1

a

n

d

t

a

r

e

l

o

c

a

t

e

d

o

n

t

h

e

s

a

m

SSOP 24S (150mil)

Symbol

Description

Dimensions in mm

16^+0.3/-0.1

W

P

Carrier Tape Width

Cavity Pitch

8.0±0.1

1.75±0.10

7.5±0.1

1.5^+0.1/-0.0

1.5^+0.25/-0.0

4.0±0.1

E

Perforation Position

F

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

D

D1

P0

P1

A0

B0

K0

t

Cavity to Perforation (Length Direction)

Cavity Length

2.0±0.1

6.5±0.1

Cavity Width

9.5±0.1

Cavity Depth

2.1±0.1

Carrier Tape Thickness

Cover Tape Width

0.30±0.05

13.3±0.1

C

SOP 28W (300mil)

Symbol

Description

Carrier Tape Width

Cavity Pitch

Dimensions in mm

24.0±0.3

W

P

12.0±0.1

E

Perforation Position

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

1.75±0.10

F

11.5±0.1

D

1.5^+0.1/-0.0

1.5^+0.25/-0.0

4.0±0.1

D1

P0

P1

A0

B0

K0

t

Cavity to Perforation (Length Direction)

Cavity Length

2.0±0.1

10.85±0.10

18.34±0.10

2.97±0.10

0.35±0.01

21.3±0.1

Cavity Width

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

C

Rev. 1.60

78

October 20, 2009

HT86BXX/HT86BRXX

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057

Tel: 86-755-8616-9908, 86-755-8616-9308

Fax: 86-755-8616-9722

Holtek Semiconductor (USA), Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538

Tel: 1-510-252-9880

Fax: 1-510-252-9885

http://www.holtek.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 1.60

79

October 20, 2009


型号：	HT86BXX
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	Enhanced Voice 8-Bit MCU 增强型语音8位MCU
文件：	总79页 (文件大小：490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT86BXX [HOLTEK]

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