首页 |元器件品牌

HT99C811(40DIP) [HOLTEK]

Microcontroller, 8-Bit, UVPROM, 4MHz, PDIP40;
HT99C811(40DIP)
型号： HT99C811(40DIP)
厂家： HOLTEK SEMICONDUCTOR INC    HOLTEK SEMICONDUCTOR INC
描述：

Microcontroller, 8-Bit, UVPROM, 4MHz, PDIP40

可编程只读存储器 时钟 微控制器 光电二极管
文件： 总47页 (文件大小：299K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
HT99C810/HT99C811  
Cordless Phone Controller  
Features  
·
Provide mask type, OTP type and  
·
·
63 powerful instructions  
Up to 1ms instruction cycle with 4MHz  
system clock at VDD=5V  
CERDIP window type versions  
Operating voltage: 2.4V~5.0V (mask type),  
3.0V~5.0V (OTP type)  
·
·
·
·
·
·
·
All instructions in 1 or 2 machine cycles  
16-bit table read instructions  
8-level subroutine nesting  
Bit manipulation instructions  
Built-in 8-bit D/A converter  
HT99C810/HT99C811: 40-pin DIP/48-pin  
SSOP package  
·
·
·
48 bidirectional I/O lines  
One interrupt input  
Two 16-bit programmable timer/event  
counter with overflow interrupt  
On-chip crystal and RC oscillator  
Watchdog timer  
·
·
·
·
·
8K´16 program memory ROM  
224´8 data memory RAM  
Halt function and wake-up feature reduce  
HT99C811C: 40-pin CERDIP window  
package  
power consumption  
General Description  
The HT99C810 is an 8-bit high performance  
RISC-like microcontroller which combines  
HT48C70 8-bit microcontroller and 8-bit D/A  
converter in one chip. It is specifically designed  
for multiple I/O product applications. It also  
provides UV-erasable CERDIP window type  
version HT99C811C and OTP type version  
HT99C811, both support designers in making  
fast evaluation of private products during de-  
velopment stages.  
The device is particularly suitable for use in  
products such as cordless phone controllers, mC  
dialers, feature phone controllers and various  
subsystem controllers. A halt feature is in-  
cluded to reduce power consumption.  
Selection Table  
Function  
ROM  
(Bits)  
RAM  
(Bits)  
I/O  
(Lines)  
Timer/ DAC  
Counter (Bits)  
Type  
WDT  
Part No.  
HT99C410  
HT99C411  
Mask  
OTP  
HT99C411C CERDIP window  
24  
48  
2
2
8
8
4K´15  
8K´16  
160´8  
224´8  
Ö
HT99C810 Mask  
HT99C811 OTP  
HT99C811C CERDIP window  
Ö
1
November 10, 1999  
HT99C810/HT99C811  
Block Diagram  
S
Y
S
C
L
K
/
4
M
U
T
M
R
0
S
S
T
T
A
A
C
C
K
K
0
1
X
I
N
T
T
M
R
0
T
M
R
0
C
S
S
T
T
A
A
C
C
K
K
2
3
1
6
-
b
i
t
I
n
t
e
r
r
u
p
t
S
S
T
T
A
A
C
C
K
K
4
5
P
r
o
g
r
a
m
C
i
r
c
u
i
t
S
Y
S
C
L
K
/
4
C
o
u
n
t
e
r
S
S
T
T
A
A
C
C
K
K
6
7
M
P
r
o
g
r
a
m
U
I
N
T
C
T
M
R
1
X
T
M
R
1
R
O
M
T
M
R
1
C
1
6
-
b
i
t
I
n
s
t
r
u
c
t
i
o
n
S
Y
S
C
L
K
/
4
M
M
P
P
0
1
R
e
g
i
s
t
e
r
M
D
A
T
A
W
D
T
S
M
U
M
e
m
o
r
y
U
W
D
T
a l  
X
W
D
T
P
r
e
s
c
e
r
X
R
C
O
S
C
P
C
O
R
T
G
P
P
P
P
G
F
E
D
P
G
0
~
P
G
7
M
U
X
I
n
s
t
r
u
c
t
i
o
n
P
P
P
P
G
F
E
D
D
e
c
o
d
e
r
P
O
R
T
F
C
P
F
0
~
P
F
7
S
T
A
T
U
S
A
L
U
P
O
R
T
E
C
T
i
m
i
n
g
S
h
i
f
t
e
r
P
E
0
~
P
E
7
G
e
n
e
r
a
t
o
r
P
O
R
T
D
C
P
D
0
~
P
D
7
A
C
C
O
S
C
2
O
S
C
1
P
C
C
8
-
b
i
t
R
/
2
R
D
/
A
C
o
n
v
e
r
t
e
r
P
C
R
E
S
A
O
U
T
V
D
D
S
P
P
O
O
R
R
T
T
B
A
P
P
B
A
C
C
V
S
P
P
B
A
0
0
~
~
P
P
B
A
7
7
P
P
B
A
A
V
D
D
S
A
V
S
2
November 10, 1999  
HT99C810/HT99C811  
Pin Assignment  
P
P
P
P
P
B
B
B
B
A
4
5
6
7
4
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
P
P
P
P
G
G
G
G
7
6
5
4
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
P
P
P
P
P
P
O
O
V
A
R
T
P
P
N
P
P
A
P
B
B
A
A
A
A
6
7
4
5
6
7
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
P
P
P
P
P
P
O
O
V
A
R
T
P
P
N
P
P
A
P
B
B
A
A
A
A
6
7
4
5
6
7
P
P
P
P
P
P
P
P
P
P
B
B
A
A
A
A
B
B
B
B
5
4
3
2
1
0
3
2
1
0
P
P
P
P
P
P
P
P
P
P
B
B
A
A
A
A
B
B
B
B
5
4
3
2
1
0
3
2
1
0
P
P
P
P
P
P
P
P
A
A
A
A
B
B
B
B
3
2
1
0
3
2
1
0
P
P
A
A
5
6
P
A
7
O
O
P
P
P
V
A
R
T
S
S
C
C
2
1
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
F
5
6
7
S
S
C
C
2
1
S
S
C
C
2
1
F
F
D
V
D
D
V
D
P
P
P
P
D
D
D
D
7
6
5
4
D
V
D
D
D
D
D
0
1
2
3
4
5
6
7
8
9
0
0
1
2
3
4
5
6
7
8
9
0
D
D
E
C
S
E
C
S
P
P
P
P
D
D
D
D
7
6
5
4
P
P
P
P
D
D
D
D
7
6
5
4
M
R
1
M
R
1
E
S
M
R
1
D
D
3
2
D
D
3
2
V
S
S
A
V
S
S
P
D
D
3
2
I
N
T
V
S
S
V
S
S
P
D
D
O
G
1
D
D
O
G
1
T
M
R
0
N
N
P
P
A
C
C
A
V
S
S
A
V
S
S
0
0
P
P
P
P
G
G
G
G
0
1
2
3
I
N
T
I
N
T
U
3
T
U
3
T
D
D
O
1
0
T
M
R
0
T
M
R
0
P
P
G
G
0
1
P
P
G
G
0
1
P
G
2
P
G
2
2
5
U
T
H
T
9
9
C
8
1
0
/
H
T
9
9
C
8
1
1
H
C
T
9
9
C
8
1
0
/
H
T
9
9
C
8
1
1
H
T
9
9
C
8
1
1
4
0
D
I
P
4
8
S
w
S
O
P
4
0
C
E
R
D
I
P
w
i
n
d
o
Note: The analog VDD (AVDD) pad and digital VDD pad must be bonded to VDD pin.  
The analog VSS (AVSS) pad and digital VSS pad must be bonded to VSS pin.  
The TMR0 and TMR1 pads must be bonded to VDD or VSS (if not used).  
3
November 10, 1999  
HT99C810/HT99C811  
Pad Assignment  
HT99C810  
5
8
5
7
5
6
5
5
5
4
5
3
4
9
8
4
7
5
1
5
5
2
0
4
P
P
A
A
1
0
5
9
4
6
P
A
6
7
1
2
4
5
P
P
P
P
P
A
F
F
F
F
P
P
P
P
P
P
P
P
P
P
P
P
E
E
E
E
B
B
B
B
E
E
E
E
7
4
4
4
3
0
1
2
3
6
3
5
5
4
4
2
4
4
1
3
6
7
8
9
4
0
O
S
S
C
C
2
1
2
1
0
3
9
O
3
1
1
0
2
(
0
,
0
)
2
1
1
3
3
8
6
P
P
P
P
V
F
F
F
F
D
4
5
6
7
1
3
7
0
1
1
3
4
P
P
D
D
7
6
3
5
1
5
3
4
D
3
3
A
V
D
D
P
P
D
D
5
4
1
1
6
7
3
2
R
T
E
S
3
1
M
R
1
V
S
S
1
8
1
9
A
V
S
S
3
0
P
P
D
D
3
2
2
6
2
7
2
8
2
2
2
3
4
2
2
1
5
2
0
2
2
9
Chip size: 3600 ´ 3940 (mm)2  
* The IC substrate should be connected to VSS in the PCB layout artwork.  
4
November 10, 1999  
HT99C810/HT99C811  
HT99C811  
5
8
5
7
4
8
4
7
5
5
5
6
5
4
5
3
4
9
5
2
5
1
5
0
P
P
A
A
1
0
5
9
4
6
4
5
P
P
A
F
7
1
4
4
4
3
0
P
P
F
F
1
2
P
P
P
P
E
E
E
E
7
6
5
4
2
3
4
5
4
2
4
1
P
F
3
4
0
O
S
S
C
C
2
P
P
P
P
P
P
P
P
B
B
B
B
E
E
E
E
3
6
7
8
9
2
1
0
3
9
O
1
(
0
,
0
)
3
1
0
3
8
P
P
P
P
F
F
F
F
4
5
6
7
2
1
1
3
3
3
7
6
5
1
1
2
0
1
1
1
1
1
3
4
5
6
7
P
P
P
P
D
D
D
D
7
6
5
4
3
3
4
3
V
A
D
V
D
D
D
3
2
R
T
E
S
V
S
S
1
8
3
1
M
R
1
A
V
S
S
1
9
3
2
0
9
P
P
D
D
3
2
2
6
2
0
2
1
2
2
2
3
2
4
2
5
2
7
2
8
P
D
1
Chip size: 3640 ´ 4120 (mm)2  
* The IC substrate should be connected to VSS in the PCB layout artwork.  
5
November 10, 1999  
HT99C810/HT99C811  
Pad Coordinates  
HT99C810  
Unit: mm  
Pad No.  
X
Y
Pad No.  
X
Y
1
1421.85  
1264.05  
1113.35  
965.15  
814.45  
666.15  
515.65  
367.25  
216.75  
68.45  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
1581.15  
1581.75  
1607.85  
1636.05  
1535.85  
1535.85  
1535.85  
1535.85  
1660.45  
1572.35  
1559.05  
1559.05  
1559.05  
1559.05  
1559.05  
1459.05  
1116.25  
924.45  
-1559.35  
-1561.85  
-1561.85  
-1561.85  
-1561.85  
-1526.35  
-1526.35  
-1526.35  
-1526.35  
-1561.85  
-1561.85  
-1561.85  
-1561.85  
-1561.85  
-1561.85  
-1606.35  
-1355.65  
-1199.65  
-912.35  
-733.85  
-580.95  
-430.85  
-282.05  
-131.95  
88.05  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
528.65  
748.15  
-82.25  
-230.45  
-381.15  
-529.35  
-680.05  
-952.35  
898.25  
1047.05  
1197.15  
1355.25  
1601.45  
1701.45  
1701.45  
1677.55  
1677.55  
1677.55  
1677.55  
1701.45  
1701.45  
1701.45  
1701.45  
1748.45  
1748.45  
1643.45  
-1606.35 -1208.95  
-1657.25 -1417.35  
-1504.75 -1482.65  
-1581.15 -1713.75  
-1405.25 -1713.75  
-1217.95 -1713.75  
-1042.05 -1713.75  
738.55  
558.25  
373.85  
193.55  
6.95  
-853.25  
-677.35  
829.85  
-1713.75  
-1713.75  
-1672.35  
-1685.25  
-1685.25  
-1723.85  
-1535.05  
-168.95  
-357.75  
-533.65  
-849.95  
-1127.75  
-1459.35  
1059.15  
1247.95  
1556.15  
1556.15  
6
November 10, 1999  
HT99C810/HT99C811  
HT99C811  
Unit: mm  
Pad No.  
X
Y
Pad No.  
X
Y
1
1511.45  
1294.60  
1140.30  
978.50  
824.20  
663.05  
507.45  
346.95  
191.35  
30.20  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
1491.55  
1493.95  
1527.35  
1527.35  
1527.35  
1527.35  
1527.35  
1527.35  
1474.65  
1506.35  
1527.35  
1527.35  
1527.35  
1527.35  
1525.40  
1207.40  
1017.40  
825.40  
-1528.90  
-1566.20  
-1566.20  
-1566.20  
-1566.20  
-1512.20  
-1512.20  
-1512.20  
-1512.20  
-1566.20  
-1566.20  
-1566.20  
-1566.20  
-1566.20  
-1566.20  
-1566.20  
-1370.50  
-1195.00  
-784.55  
-633.10  
-479.10  
-325.10  
-180.90  
-26.90  
2
3
4
5
6
7
8
9
188.70  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
726.05  
1010.40  
1164.40  
1308.60  
1462.60  
1630.85  
1685.85  
1740.85  
1740.85  
1724.10  
1724.10  
1724.10  
1724.10  
1729.80  
1729.80  
1729.80  
1729.80  
1740.85  
1764.75  
1701.45  
-124.10  
-285.90  
-440.20  
-602.00  
-756.30  
-918.10  
-1566.20 -1072.40  
-1598.50 -1227.80  
-1524.00 -1405.15  
-1144.05 -1767.85  
647.30  
494.50  
331.20  
-989.75  
-824.30  
-680.10  
-526.10  
-381.90  
1037.30  
1226.50  
1520.10  
1544.10  
1544.10  
-1767.85  
-1767.85  
-1767.85  
-1767.85  
-1767.85  
-1746.85  
-1767.85  
-1830.50  
-1671.70  
-1527.50  
178.40  
15.85  
-138.45  
-300.25  
-471.35  
-655.10  
-1065.60  
-1473.90  
7
November 10, 1999  
HT99C810/HT99C811  
Pad Description  
HT99C810  
Pad  
Pad No.  
Mask  
Option  
I/O  
Description  
Name  
Bidirectional 8-bit Input/Output port. Each bit can  
be configured as a wake-up input by mask option.  
Software instructions determine the CMOS output  
or schmitt trigger input with or without pull-high re-  
sistor (mask option).  
1,  
Wake-up  
Pull-high  
or None  
48~45  
59~57  
PA0~PA7 I/O  
Bidirectional 8-bit Input/Output port. Software in-  
structions determine the CMOS output or schmitt  
trigger input with or without pull-high resistor  
(mask option).  
Pull-high  
or None  
(mask type only)  
13~10  
5~2  
PE0~PE3  
I/O  
PE4~PE7  
Bidirectional 8-bit Input/Output port. Software in-  
structions determine the NMOS open drain output  
or schmitt trigger input.  
9~6  
52~49  
PB0~PB7 I/O  
¾
Bidirectional 8-bit Input/Output port. Software in-  
structions determine the CMOS output or schmitt  
trigger input with or without a pull-high resistor  
(mask option).  
Pull-high  
or None  
(mask type only)  
27~30  
17~14  
PD0~PD3  
I/O  
PD4~PD7  
18  
19  
VSS  
AVSS  
Negative power supply, GND.  
Analog negative power supply, AGND  
¾
External interrupt schmitt trigger input with  
pull-high resistor. Edge triggered activated on a  
high to low transition.  
20  
21  
INT  
I
I
¾
¾
TMR0  
Schmitt trigger input for timer/event counter 0  
Bidirectional 8-bit Input/Output port. Software in-  
structions determine the CMOS output or schmitt  
trigger input with or without pull-high resistor  
(mask option).  
Pull-high  
or None  
(mask type only)  
22~25  
56~53  
PG0~PG3  
PG4~PG7  
I/O  
O
The D/A converter output can be programmed by  
D/A controlled register. The register has a total of 8  
digits from MSB to LSB, and offers 8-bit resolution  
26  
AOUT  
¾
for D/A converter and one LSB is 1/256 VDD  
.
31  
32  
TMR1  
RES  
I
I
Schmitt trigger input for timer/event counter 1  
Schmitt trigger reset input. Active low.  
¾
¾
34  
33  
VDD  
AVDD  
Positive power supply, VDD  
Analog positive power supply, AVDD  
¾
¾
Bidirectional 8-bit Input/Output port. Software in-  
structions determine the CMOS output or schmitt  
trigger input with or without pull-high resistor  
(mask option).  
Pull-high  
or None  
(mask type only)  
44~41  
38~35  
PF0~PF3  
PF4~PF7  
I/O  
8
November 10, 1999  
HT99C810/HT99C811  
Pad  
Name  
Mask  
Option  
Pad No.  
I/O  
Description  
OSC1, OSC2 are connected to an RC network or a  
crystal (determined by mask option) for the internal  
system clock. In the case of RC operation, OSC2 is  
the output terminal for 1/4 system clock.  
39  
40  
OSC1  
OSC2  
I
Crystal  
or RC  
O
Absolute Maximum Ratings  
Supply Voltage..............................-0.3V to 5.5V  
Input Voltage.................VSS-0.3V to VDD+0.3V  
Storage Temperature.................-50°C to 125°C  
Operating Temperature ..............-25°C to 70°C  
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-  
mum Ratings² may cause substantial damage to the device. Functional operation of this device  
at other conditions beyond those listed in the specification is not implied and prolonged expo-  
sure to extreme conditions may affect device reliability.  
D.C. Characteristics  
Ta=25°C  
Test Conditions  
Symbol  
Parameter  
Min. Typ. Max. Unit  
VDD Conditions  
V
DD (mask)  
2.4  
3.0  
¾
¾
¾
¾
¾
¾
¾
¾
0
5.0  
5.0  
2
V
V
¾
¾
¾
¾
¾
1
Operating Voltage  
VDD (OTP)  
¾
3V  
5V  
3V  
5V  
3V  
5V  
3V  
5V  
3V  
5V  
3V  
5V  
3V  
5V  
3V  
5V  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
V
No load,  
fSYS=4MHz  
Operating Current  
(Crystal OSC)  
IDD1  
IDD2  
ISTB1  
ISTB2  
VIL  
2.5  
0.75  
1.5  
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
5
1.5  
5
No load,  
fSYS=2MHz  
Operating Current  
(RC OSC)  
5
Standby Current  
(WDT Enabled)  
No load,  
system halt  
20  
1
Standby Current  
(WDT Disabled)  
No load,  
system halt  
2
0.9  
1.5  
3
¾
¾
¾
¾
¾
¾
¾
¾
Input Low Voltage for I/O Ports  
0
V
2.1  
3.5  
0
V
Input High Voltage for I/O  
Ports  
VIH  
5
V
0.7  
1.3  
3
V
Input Low Voltage  
(RES, TMR0, TMR1, INT)  
VIL1  
0
V
2.3  
3.8  
V
Input High Voltage  
(RES, TMR0, TMR1, INT)  
VIH1  
5
V
9
November 10, 1999  
HT99C810/HT99C811  
Test Conditions  
Symbol  
Parameter  
I/O Port Sink Current  
I/O Port Source Current  
Min. Typ. Max. Unit  
VDD Conditions  
V
OL=0.3V  
VOL=0.5V  
OH=2.7V  
3V  
5V  
3V  
5V  
3V  
5V  
¾
1.5  
¾
2.5  
6
mA  
mA  
mA  
mA  
kW  
kW  
V
¾
¾
IOL  
V
-1  
-1.5  
-3  
60  
30  
¾
¾
IOH  
VOH=4.5V  
¾
¾
40  
80  
¾
¾
¾
Pull-high Resistance of I/O  
Ports and INT  
RPH  
10  
50  
VDAC  
IDAC  
AVSS  
¾
AVDD  
¾
DAC Output Level  
DAC Drive Current  
VOH=0.9VDD  
5V  
50  
mA  
A.C. Characteristics  
Ta=25°C  
Min. Typ. Max. Unit  
Test Conditions  
Symbol  
fSYS1  
Parameter  
VDD  
Conditions  
3V  
5V  
3V  
5V  
3V  
5V  
3V  
5V  
3V  
5V  
400  
400  
400  
400  
0
4000 kHz  
4000 kHz  
2000 kHz  
3000 kHz  
4000 kHz  
4000 kHz  
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
90  
65  
23  
17  
System Clock (Crystal OSC)  
System Clock (RC OSC)  
Timer I/P Frequency (TMR)  
Watchdog Oscillator  
fSYS2  
fTIMER  
tWDTOSC  
tWDT1  
0
45  
35  
12  
9
180  
130  
45  
ms  
ms  
ms  
ms  
Watchdog Time-out Period  
(RC)  
Without WDT  
prescaler  
35  
Watchdog Time-out Period  
(System Clock)  
Without WDT  
prescaler  
tWDT2  
tRES  
tXST  
tINT  
tSYS  
1024  
¾
¾
¾
¾
¾
External Reset Low Pulse  
Width  
1
¾
¾
ms  
Power-up or  
wake-up from halt  
tSYS  
System Start-up Timer  
Interrupt Pulse Width  
1024  
¾
¾
¾
¾
¾
1
¾
¾
ms  
Note: tSYS=1/fSYS  
For other important system architecture and function description, refer to HT48CX0 data  
sheet.  
10  
November 10, 1999  
HT99C810/HT99C811  
Functional Description  
D/A converter description  
8-bit resolution. The HT48700 general I/O  
PORTC is replaced by a D/A converter control  
register to control the D/A output value as  
shown below:  
The HT99C810/HT99C811 built-in 8-bit D/A  
converter is one of the simple designed methods  
of the D/A converter. The R/2R lattice method is  
used in HT99C810/HT99C811 which offers  
PORTC  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC0  
(MSB)  
(LSB)  
Determine  
D/A value  
1/2  
AVDD  
1/4  
AVDD  
1/8  
AVDD  
1/16  
AVDD  
1/32  
AVDD  
1/64  
AVDD  
1/128  
AVDD  
1/256  
AVDD  
* D/Aconverter has isolated power line layout itself, in addition, AVDD and AVSS pads are included.  
D/A converter circuit  
D
a
t
a
B
u
D
C
s
Q
W
r
i
t
e
C
o
n
t
r
o
l
K
R
Q
e
g
i
s
t
e
r
S
A
D
V
D
C
h
i
p
R
e
s
e
t
R
e
a
d
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
P
C
0
~
P
C
7
D
C
Q
K
O
Q
W
r
i
t
e
I
/
S
A
S
V
S
M
U
X
R
e
a
d
I
/
O
2
R
R
R
R
R
R
R
R
A
O
U
T
A
S
V
S
2
R
2
R
2
R
2
R
2
R
2
R
2
R
2
R
P
C
0
P
C
1
P
C
2
P
C
3
P
C
4
P
C
5
P
C
6
P
C
7
(
D
0
)
(
D
1
(
)
D
2
)
(
D
3
)
(
D
4
)
(
D
5
)
(
D
6
)
(
D
7
)
R
=
1
W
0
k
11  
November 10, 1999  
HT99C810/HT99C811  
Execution flow  
The conditional skip is activated by instruction.  
Once the condition is met, the next instruction,  
fetched during the current instruction execu-  
tion, is discarded and a dummy cycle replaces it  
to get the proper instruction. Otherwise pro-  
ceed with the next instruction.  
The system clock for the HT99C810/HT99C811  
is derived from either a crystal or an RC oscilla-  
tor. The system clock is internally divided into  
four non-overlapping clocks. One instruction  
cycle consists of four system clock cycles.  
The lower byte of the program counter (PCL) is  
a readable and writeable register (06H). Moving  
data into the PCL performs a short jump. The  
destinationwillbewithin256locations.  
Instruction fetching and execution are  
pipelined in such a way that a fetch takes one  
instruction cycle while decoding and execution  
takes the next instruction cycle. However, the  
pipelining scheme causes each instruction to ef-  
fectively execute in one cycle. If an instruction  
changes the program counter, two cycles are re-  
quired to complete the instruction.  
When a control transfer takes place, an addi-  
tional dummy cycle is required.  
Program memory - ROM  
The program memory is used to store the pro-  
gram instructions which are to be executed. It  
also contains data, table, and interrupt entries,  
and is organized into 8192 ´ 16 bits, addressed  
by the program counter and table pointer.  
Program counter - PC  
The 13-bit program counter (PC) controls the  
sequence in which the instructions stored in  
program ROM are executed and its contents  
specify a maximum of 8192 addresses.  
Certain locations in the program memory are  
reserved for special usage:  
After accessing a program memory word to  
fetch an instruction code, the contents of the  
program counter are incremented by one. The  
program counter then points to the memory  
word containing the next instruction code.  
·
Location 000H  
This area is reserved for the initialization  
program. After chip reset, the program al-  
ways begins execution at location 000H.  
When executing a jump instruction, conditional  
skip execution, loading PCL register, subrou-  
tine call, initial reset, internal interrupt, exter-  
nal interrupt or return from subroutine, the PC  
manipulates the program transfer by loading  
the address corresponding to each instruction.  
·
Location 004H  
This area is reserved for the external inter-  
rupt service program. If the INT input pin is  
activated, and the interrupt is enabled and  
the stack is not full, the program begins exe-  
cution at location 004H.  
T
1
T
2
T
3
T
1
T
4
T
2
T
3
T
1
T
4
T
2
T
3
T
4
S
y
s
t
e
m
C
l
o
c
k
O
S
C
2
(
R
C
o
n
l
y
)
(
N
M
O
S
o
p
e
n
d
r
a
i
n
o
u
t
p
u
t
)
P
C
P
C
+
1
P
C
+
2
P
C
F
E
e
t
e
c
h
I
N
S
T
(
P
C
)
x
c
u
t
e
I
N
S
T
(
P
C
-
1
)
S T  
F
E
e
t
e
c
h
I
N
(
P
C
+
1
)
x
c
u
t
e
I
N
S
T
(
P
C
)
N
F
E
e
t
e
c
h
I
S
T
(
P
C
+
2
)
x
c
u
t
e
I
N
S
T
(
P
C
+
1
)
Execution flow  
12  
November 10, 1999  
HT99C810/HT99C811  
·
·
·
0
0
0
0
0
0
0
0
0
0
4
8
H
H
H
Location 008H  
D
e
v
i
c
e
i
n
i
t
i
a
l
i
z
a
t
i
o
n
p
r
o
g
r
a
m
This area is reserved for the timer/event coun-  
ter 0 interrupt service program. If timer inter-  
rupt results from a timer/event counter 0  
overflow, and if the interrupt is enabled and the  
stack is not full, the program begins execution  
at location 008H.  
E
x
t
e
r
n
a
l
i
n
t
e
r
r
u
p
t
s
u
b
r
o
u
t
i
n
e
T
i
m
e
e
r
r
/
/
e
e
v
v
e
e
n
n
t
t
c
c
o
o
u
u
n
n
t
t
e
e
r
r
0
1
i
i
n
n
t
t
e
e
r
r
r
r
u
u
p
p
t
t
s
s
u
u
0
0
0
C
H
T
i
m
P
R
r
o
g
r
a
m
O
M
n
n
0
F
0
H
Location 00CH  
L
L
o
o
o
o
k
k
-
-
u
u
p
p
t
t
a
a
b
b
l
l
e
e
(
(
2
2
5
5
6
6
w
o
r
d
s
)
This area is reserved for the timer/event  
counter 1 interrupt service program. If timer  
interrupt resulting from a timer/event coun-  
ter 1 overflow, and if the interrupt is enabled  
and the stack is not full, the program begins  
execution at location 00CH.  
F
H
w
o
r
d
s
)
1
F
F
F
H
1
6
b
i
t
s
N
o
t
e
:
n
r
a
n
g
e
s
f
r
o
m
0
0
t
o
1
F
Table location  
Any location in the ROM space can be used as  
look-up tables. The instructions TABRDC [m]  
(the current page, 1 page=256 words) and  
TABRDL [m] (the last page) transfer the con-  
tents of the lower-order byte to the specified  
data memory, and the higher-order byte to  
TBLH (08H). Only the destination of the  
lower-order byte in the table is well-defined,  
the higher-order byte of the table word are  
transferred to the TBLH. The Table  
Higher-order byte register (TBLH) is read  
Program memory  
only. The Table Pointer (TBLP) is a  
read/write register (07H), which indicates the  
table location. Before accessing the table, the  
location must be placed in TBLP. The TBLH  
is read only and cannot be restored. If the  
main routine and the ISR (Interrupt Service  
Routine) both employ the table read instruc-  
tion, the contents of the TBLH in the main  
routine are likely to be changed by the table  
Program Counter  
Mode  
*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0  
Initial reset  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
External interrupt  
Timer/event counter 0  
overflow  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
Timer/event counter 1  
overflow  
0
Skip  
PC+2  
Loading PCL  
*12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0  
#12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0  
S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0  
Program counter  
Jump, call branch  
Return from subroutine  
#12~#0: Instruction code bits  
@7~@0: PCL bits  
Note: *12~*0: Program counter bits  
S12~S0: Stack register bits  
13  
November 10, 1999  
HT99C810/HT99C811  
read instruction used in the ISR. Errors can  
occur. In other words, simultaneously using  
the table read instruction in the main routine  
and the ISR should be avoided. However, if  
the table read instruction has to be applied in  
both the main routine and the ISR, the inter-  
rupt(s) is supposed to be disabled prior to the  
table read instruction and will not be enabled  
until the TBLH has been backed-up. All table  
related instructions need 2 cycles to complete  
the operation. These areas may function as  
normal program memory depending upon the  
requirements.  
subsequently executed, stack overflow occurs and  
the first entry will be lost (only the most recent  
eight return addresses are stored).  
Data memory - RAM  
The data memory is designed with 255 ´ 8 bits.  
The data memory is divided into two functional  
groups: special function registers and general  
purpose data memory (224´8). Most of them are  
read/write, but some are read only.  
The special function registers include the indi-  
rect addressing register 0 (00H), the memory  
pointer register 0 (MP0;01H), the indirect ad-  
dressing register 1 (02H), the memory pointer  
register 1 (MP1;03H), the accumulator  
(ACC;05H), the program counter lower-byte  
register (PCL;06H), the table pointer  
(TBLP;07H), the table higher-order byte regis-  
ter (TBLH;08H), the watchdog timer option set-  
ting register (WDTS;09H), the status register  
(STATUS;0AH), the interrupt control register  
(INTC;0BH), the timer/event counter 0  
higher-order byte register (TMR0H;0CH), the  
timer/event counter 0 lower-order byte register  
(TMR0L;0DH), the timer/event counter 0 con-  
trol register (TMR0C;0EH),the timer/event  
Stack register - STACK  
This is a special part of the memory which is  
used to save the contents of the program coun-  
ter (PC) only. The stack is organized into 8 lev-  
els and is neither part of the data nor part of the  
program space, and is neither readable nor  
writeable. The activated level is indexed by the  
stack pointer (SP) and is neither readable nor  
writeable. At a subroutine call or interrupt ac-  
knowledgment, the contents of the program  
counter are pushed onto the stack. At the end of  
a subroutine or an interrupt routine, as sig-  
naled by a return instruction (RET or RETI),  
the program counter is restored to its previous  
value from the stack. After a chip reset, the SP  
will point to the top of the stack.  
counter  
1 higher-order byte register  
(TMR1H;0FH), the timer/event counter 1  
lower-order byte register (TMR1L;10H), the  
timer/event counter 1 control register  
(TMR1C;11H), the I/O registers (PA;12H,  
PB;14H, PD;18H, PE;1AH, PF;1CH, PG;1EH)  
and the I/O control registers (PAC;13H,  
PBC;15H, PDC;19H, PEC;1BH, PFC;1DH,  
PGC;1FH). The remaining space before the  
20H is reserved for future expanded usage and  
reading these locations will return the result to  
00H. The general purpose data memory, ad-  
If the stack is full and a non-masked interrupt  
takes place, the interrupt request flag will be re-  
corded but the acknowledgment will be inhibited.  
When the stack pointer is decremented (by RET  
or RETI), the interrupt will be serviced. This fea-  
ture prevents stack overflow allowing the pro-  
grammer to use the structure more easily. In a  
similar case, if the stack is full and a ²CALL² is  
Table Location  
Instruction(s)  
*12 *11 *10  
P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0  
@7 @6 @5 @4 @3 @2 @1 @0  
*9  
*8 *7  
*6 *5  
*4 *3 *2  
*1  
*0  
TABRDC [m]  
TABRDL [m]  
1
1
1
1
1
Table location  
@7~@0: Table pointer bits  
Note: *12~*0: Table location bits  
P12~P8: Current program counter bits  
14  
November 10, 1999  
HT99C810/HT99C811  
Indirectt addressing register  
I
I
n
n
d
d
i
i
r
r
e
e
c
c
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
i
i
n
n
g
g
R
R
e
e
g
i
s
e
r
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
M
M
P
P
0
1
Location 00H and 02H are indirect addressing  
g
i
s
t
e
r
1
registers that are not physically implemented.  
Any read/write operation of [00H] and [02H] ac-  
cess data memory pointed to by MP0 (01H) and  
MP1 (03H) respectively. Reading location 00H  
or 02H indirectly will return the result to 00H.  
Writing indirectly results in no operation.  
A
C
C
P
C
L
T
B
L
P
T
B
L
H
W
D
T
S
The function of data movement between two in-  
direct addressing registers, is not supported.  
S
T
A
T
U
S
0
0
A
B
H
H
I
N
T
C
0
S
p
e
c
i
a
l
P
r
o
s
e
u The p memory pointer registers, MP0 and MP1,  
T
M
R
H
C
D
A
T
A
M
E
M
O
R
Y
0
0
C
D
H
H
are 8-bit registers which can be used to access  
the data memory by combining corresponding  
indirect addressing registers.  
T
T
M
M
R
R
0
1
L
T
T
M
M
R
R
0
1
0
E
H
H
C
0
F
0
1
2
3
4
5
6
7
8
9
H
L
1
1
1
1
1
1
1
1
1
1
H
H
H
H
H
H
H
H
H
H
T
M
R
1
Accumulator  
P
P
A
B
The accumulator closely relates to ALU opera-  
tions. It is also mapped to location 05H of the  
data memory and is capable of carrying out im-  
mediate data operations. Data movement be-  
tween these two data memories has to pass  
through the accumulator.  
P
P
A
B
C
C
D
/
A
O
u
t
p
u
t
R
e
g
i
s
t
e
r
D
/
A
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
P
D
P
D
C
P
E
1
1
A
B
H
H
Arithmetic and logic unit - ALU  
P
E
C
P
F
1
1
C
D
H
H
This circuit performs 8-bit arithmetic and logic  
operation. The ALU provides the following  
functions:  
P
F
C
P
G
1
E
H
P
G
C
1
F
H
H
2
0
·
Arithmetic operations (ADD, ADC, SUB,  
SBC, DAA)  
G
e
A
n
e
r
a
l
P
u
r
p
o
s
e
u
:
U
n
s
e
d
D
T
A
M
E
M
O
R
Y
·
Logic operations (AND, OR, XOR, CPL)  
R
e
a
d
a
s
"
0
0
"
(
2
2
4
B
y
t
e
s
)
·
·
·
Rotation (RL, RR, RLC, RRC)  
F
F
H
Increment and Decrement (INC, DEC)  
Branch decision (SZ, SNZ, SIZ, SDZ ....)  
RAM mapping  
The ALU not only saves the results of a data op-  
eration but also changes the contents of the sta-  
tus register.  
dressed from 20H to FFH, is used for data and  
control information under instruction command.  
All data memory areas can execute arithmetic,  
logic, increment, decrement and rotate opera-  
tions directly. Except for some dedicated bits,  
each bit in the data memory can be set and re-  
set by the SET [m].i and CLR [m].i instructions,  
respectively. They are also indirectly accessible  
through Memory pointer registers (MP0;01H,  
MP1;03H).  
Status register - STATUS  
This 8-bit status register (0AH) contains a zero  
flag (Z), a carry flag (C), an auxiliary carry flag  
(AC), an overflow flag (OV), a power down flag  
(PD) and a watchdog time-out flag (TO). The  
status register not only records the status infor-  
mation but also controls the operation sequence.  
15  
November 10, 1999  
HT99C810/HT99C811  
With the exception of the TO and PD flags, bits  
in the status register can be altered by instruc-  
tions like most other register. Any data written  
into the status register will not change the TO  
or PD flags. It should be noted that operations  
related to the status register may give different  
results from those intended. The TO and PD  
flags can only be changed by system power up,  
watchdog timer overflow, executing the HALT  
instruction and clearing the watchdog timer.  
(INTC;0BH) contains the interrupt control bits to  
set the enable/disable and the interrupt request  
flags.  
Once an interrupt subroutine is serviced, all  
other interrupts will be blocked (by clearing the  
EMI bit). This scheme may prevent any further  
interrupt nesting. Other interrupt requests may  
occur during this interval but only the interrupt  
request flag is recorded. If a certain interrupt  
needs servicing within the service routine, the  
EMI bit and the corresponding bit of the INTC  
may be set to permit interrupt nesting. If the  
stack is full, the interrupt request will not be ac-  
knowledged, even if the related interrupt is en-  
abled, until the SP is decremented. If immediate  
service is desired, the stack must be prevented  
from becoming full.  
The Z, OV, AC and C flags generally reflect the  
status of the latest operations.  
In addition, on entering the interrupt sequence  
or executing the subroutine call, the status reg-  
ister will not be automatically pushed onto the  
stack. If the contents of the status are impor-  
tant and if the subroutine can corrupt the sta-  
tus register, precaution must be taken to save it  
properly.  
All these kinds of interrupt have a wake-up ca-  
pability. As an interrupt is serviced, a control  
transfer occurs by pushing the program counter  
onto the stack, followed by a branch to a sub-  
routine at specified location in the program  
memory. Only the the contents of the program  
counter is pushed onto the stack. If the contents  
of the register and Status register (STATUS)  
Interrupt  
The HT99C810/HT99C811 provides an exter-  
nal interrupt and internal timer/event counter  
interrupts. The interrupt control register  
Labels Bits  
Function  
C is set if the operation results in a carry during an addition operation or if a bor-  
row does not take place during a subtraction operation; otherwise C is cleared. C  
is also affected by a rotate through carry instruction.  
C
0
1
AC is set if the operation results in a carry out of the low nibbles in addition or a  
borrow does not take place from the high nibble into the low nibble in subtrac-  
tion; otherwise AC is cleared.  
AC  
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is  
cleared.  
Z
2
3
4
5
OV is set if the operation results in a carry into the highest-order bit but not a  
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.  
OV  
PD  
TO  
PD is cleared when either a system power-up or executing the CLR WDT in-  
struction. PD is set by executing the HALT instruction.  
TO is cleared by a system power-up or executing the CLR WDT or HALT in-  
struction. TO is set by a WDT time-out.  
6
7
¾
¾
Undefined, read as ²0²  
Undefined, read as ²0²  
STATUS register  
16  
November 10, 1999  
HT99C810/HT99C811  
are altered by the interrupt service program  
which corrupts the desired control sequence,  
the contents should be saved in advance.  
During the execution of an interrupt subroutine,  
other interrupt acknowledgments are held until  
the RETI instruction is executed or the EMI bit  
and the related interrupt control bit are set to 1  
(if the stack is not full). To return from the inter-  
rupt subroutine, the RET or RETI instruction  
may be invoked. RETI will set the EMI bit to en-  
able an interrupt service, but RET will not.  
External interrupt is triggered by a high to low  
transition of INT and the related interrupt re-  
quest flag (EIF; bit 4 of INTC) will be set. When  
the interrupt is enabled, and the stack is not  
full and the external interrupt is active, a sub-  
routine call to location 04H will occur. The in-  
terrupt request flag (EIF) and EMI bits will be  
cleared to disable other interrupts.  
Interrupts occurring in the interval between  
the rising edges of two consecutive T2 pulses,  
will be serviced on the latter of the two T2  
pulses, if the corresponding interrupts are en-  
abled. In the case of simultaneous requests, the  
following table shows the priority that is ap-  
plied. These can be masked by resetting the  
EMI bit.  
The internal timer/event counter 0 interrupt is  
initialized by setting the timer/event counter 0  
interrupt request flag (T0F; bit 5 of INTC),  
which is normally caused by a timer/event  
counter 0 overflow. When the interrupt is en-  
abled, and the stack is not full and the T0F bit  
is set, a subroutine call to location 08H will oc-  
cur. The related interrupt request flag (T0F)  
will be reset and the EMI bit cleared to disable  
further interrupts.  
No. Interrupt Source Priority Vector  
a
b
External interrupt  
1
2
04H  
08H  
Timer/event  
counter 0 overflow  
The timer/event counter 1 interrupt is operated  
in the same manner as timer/event counter 0.  
The related interrupt control bits ET1I and  
T1F of timer/event counter 1 are bit 3 and bit 6  
of the INTC respectively.  
Timer/event  
counter 1 overflow  
c
3
0CH  
Register Bit No.  
Label  
Function  
Controls the master (global) interrupt  
(1=enabled; 0=disabled)  
0
EMI  
Controls the external interrupt  
(1=enabled; 0=disabled)  
1
2
EEI  
Controls the timer/event counter 0 interrupt  
(1=enabled; 0=disabled)  
ET0I  
ET1I  
EIF  
Controls the timer/event counter1 interrupt  
(1=enabled; 0=disabled  
3
INTC  
(0BH)  
External interrupt request flag  
(1=active; 0=inactive)  
4
Internal timer/event counter 0 request flag.  
(1=active; 0=inactive)  
5
T0F  
Internal timer/event counter1 request flag.  
(1=active; 0=inactive)  
6
7
T1F  
¾
Unused bit, read as ²0²  
INTC register  
17  
November 10, 1999  
HT99C810/HT99C811  
V
D
D
The timer/event counter 0/1 interrupt request  
flag (T0F/T1F), external interrupt request flag  
(EIF), enable timer/event counter 0/1 bit  
(ET0I/ET1I), enable external interrupt bit  
(EEI) and enable master interrupt bit (EMI)  
constitute an interrupt control register (INTC)  
which is located at 0BH in the data memory.  
EMI, EEI, ET0I, ET1I are used to control the  
enabling/disabling of interrupts. These bits  
prevent the requested interrupt from being ser-  
viced. Once the interrupt request flags (T0F,  
T1F, EIF) are set, they will remain in the INTC  
register until the interrupts are serviced or  
cleared by a software instruction.  
O
O
S
S
C
C
1
2
O
S
S
C
C
1
2
0
m
. 0 F 1  
O
R
f
(
d
S
Y
S
N
M
O
S
o
p
e
n
r
a
i
n
o
u
t
p
u
t
)
C
r
y
s
t
a
l
O
s
c
i
l
l
a
t
C
o
r
O
s
c
i
l
l
a
t
o
r
System oscillator  
other external components are needed. Instead  
of a crystal, a resonator can also be connected  
between OSC1 and OSC2 to get a frequency ref-  
erence, but two external capacitors in OSC1  
and OSC2 are required.  
It is suggested that a program does not use the  
²CALL subroutine² within the interrupt sub-  
routine. Because interrupts often occur in an un-  
predictable manner or need to be serviced  
immediately in some applications, if only one  
stack is left and enabling the interrupt is not well  
controlled, once the ²CALL subroutine² operates in  
the interrupt subroutine, it will damage the original  
control sequence.  
The WDT oscillator is a free running on-chip  
RC oscillator, and no external components are  
required. Even if the system enters the power  
down mode, the system clock is stopped, but the  
WDT oscillator still works with a period of ap-  
proximately 78 ms. The WDT oscillator can be  
disabled by mask option to conserve power.  
Oscillator configuration  
Watchdog timer - WDT  
There are two oscillator circuits in the  
HT99C810/HT99C811. Both are designed for  
system clocks; the RC oscillator and the crystal  
oscillator, which are determined by mask options.  
No matter what oscillator type is selected, the  
signal provides the system clock. The HALT  
mode stops the system oscillator and ignores the  
external signal to conserve power.  
The clock source of the WDT is implemented by  
a dedicated RC oscillator (WDT oscillator) or in-  
struction clock (system clock divided by 4), de-  
cided by mask options. This timer is designed to  
prevent a software malfunction or the program  
sequence from jumping to an unknown location  
with unpredictable results. The watchdog  
timer can be disabled by mask option. If the  
watchdog timer is disabled, all the executions  
related to the WDT result to no operation.  
If an RC oscillator is used, an external resistor  
between OSC1 and VDD is needed and the re-  
sistance must range from 51kW to 1MW. The  
system clock, divided by four, is available on  
OSC2, which can be used to synchronize exter-  
nal logic. The RC oscillator provides the most  
cost effective solution. However, the frequency  
of the oscillation may vary with VDD, tempera-  
ture and the chip itself due to process varia-  
tions. It is, therefore, not suitable for timing  
sensitive operations where accurate oscillator  
frequency is desired.  
Once the internal WDT oscillator (RC oscillator  
with period 78ms normally) is selected, it is first  
divided by 256 (8-stages) to get the nominal  
time-out period of approximately 20ms. This  
time-out period may vary with temperature,  
VDD and process variations. By invoking the  
WDT prescaler, longer time-out periods can be  
realized. Writing data to WS2, WS1, WS0 (bit  
2,1,0 of the WDTS) can give different time-out  
periods. If WS2, WS1, WS0 are all equal to 1,  
the division ratio is up to 1:128, and the maxi-  
mum time-out period is 2.6 seconds.  
If a crystal oscillator is used, a crystal across  
OSC1 and OSC2 is needed to provide the feed-  
back and phase shift needed for oscillator, no  
18  
November 10, 1999  
HT99C810/HT99C811  
If the WDT oscillator is disabled, the WDT clock  
may still come from the instruction clock and  
operate in the same manner except that in the  
HALT state the WDT may stop counting and  
lose its protection purpose. In this situation the  
logic can only be restarted by external logic.  
The high nibble and bit 3 of the WDTS are re-  
served for user defined flags, which can be used  
to indicate some specified status.  
Of these two types of instruction, only one can  
be active depending on the mask option ¾  
²CLR WDT times selection option². If the ²CLR  
WDT² is selected (i.e.. CLRWDT times equal  
one), any execution of the CLR WDT instruc-  
tion will clear the WDT. In case ²CLR WDT1²  
and ²CLR WDT2² are chosen (i.e.. CLRWDT  
times equal two), these two instructions must  
be executed to clear the WDT; otherwise, the  
WDT may reset the chip due to a time-out.  
WS2  
WS1  
WS0  
Division Ratio  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1  
1:2  
Power down operation - HALT  
The HALT mode is initialized by the HALT in-  
struction and results in the following...  
1:4  
·
The system oscillator will turn off but the  
WDT oscillator keeps running (if the WDT os-  
cillator is selected).  
1:8  
1:16  
1:32  
1:64  
1:128  
·
·
The contents of the on chip RAM and regis-  
ters remain unchanged.  
WDT and WDT prescaler will be cleared and  
counted again (if the WDT clock is from the  
WDT oscillator).  
WDTS register  
·
·
All I/O ports maintain their original status.  
The PD flag is set and the TO flag is cleared.  
If the device operates in a noisy environment,  
using the on-chip RC oscillator (WDT OSC) is  
strongly recommended, since the HALT will  
stop the system clock.  
The system can quit the HALT mode by means  
of an external reset, an interrupt, an external  
falling edge signal on port A or a WDT overflow.  
An external reset causes a device initialization  
and the WDT overflow performs a ²warm reset².  
Examining the TO and PD flags, the reason for  
chip reset can be determined. The PD flag is  
cleared when system power-up or executing the  
CLR WDT instruction and is set when the HALT  
instruction is executed. The TO flag is set if the  
WDT time-out occurs, which causes a wake-up  
that only resets the PC and SP, and leaves the  
others in their original status.  
The overflow of the WDT under normal opera-  
tion will initialize ²chip reset² and set the sta-  
tus bit ²TO². An overflow in the HALT mode  
initializes a ²warm reset² only when the PC and  
SP are reset to zero. To clear the contents of the  
WDT (including the WDT prescaler ), there are  
three methods to be adopted; external reset (a  
low level to RES), software instruction(s), or a  
HALT instruction. The software instruction in-  
clude CLR WDT and CLR WDT1/CLR WDT2.  
S
y
s
t
e
m
C
l
o
c
k
/
4
W
D
T
P
r
e
s
c
a
l
e
r
M
a
s
k
8 -  
n
b
i
t
C
o
u
7
n
-
b
t
e
i
t
r
C
o
u
n
t
e
r
O
p
t
i
o
S
e
l
e
c
t
W
D
T
O
S
C
8
-
t
o
-
1
M
U
X
S
W
0
~
W
S
2
W
D
T
T
i
m
e
-
o
u
t
Watchdog timer  
19  
November 10, 1999  
HT99C810/HT99C811  
V
D
D
The port A wake-up and interrupt methods can  
be considered as a continuation of normal exe-  
cution. Each bit in port A can be independently  
selected to wake-up the device by mask option.  
Awakening from an I/O port stimulus, the pro-  
gram resumes execution of the next instruc-  
tion. However, if the program awakens from an  
interrupt, two sequences may occur. The pro-  
gram will resume execution at the next instruc-  
tion if the related interrupt(s) is (are) disabled  
or the interrupt(s) is enabled but the stack is  
full. A regular interrupt response may take  
place if the interrupt is enabled and the stack is  
not full.  
1
0
W
0
k
R
E
S
0
m
. F 1  
Reset circuit  
H
A
L
T
W
a
r
m
R
e
s
e
t
W
T
D
T
W
D
T
i
m
e
-
o
u
t
R
e
s
e
t
R
E
S
C
R
o
e
l
s
d
Once a wake-up event(s) occurs, it takes 1024  
tSYS (system clock period) to resume normal oper-  
S
S
T
e
t
1
0
-
s
t
a
g
e
O
S
C
1
R
i
p
p
l
e
C
o
u
n
t
e
r
ation. In other words, a dummy cycle period will  
be inserted after the wake-up. If the wake-up re-  
sults from an interrupt acknowledge, the actual  
interrupt subroutine will be delayed by one more  
cycle. If the wake-up results in next instruction  
execution, this will be executed immediately after  
a dummy period is completed. If an interrupt re-  
quest flag is set to ²1² before entering the HALT  
mode, the wake-up function of the related inter-  
rupt will be disabled.  
P
o
w
e
r
-
o
n
D
e
t
e
c
t
i
o
n
Reset configuration  
during other reset conditions. Most registers  
are reset to the ²initial condition² when the re-  
set conditions are met. By examining the PD  
and TO flags, the program can distinguish be-  
tween different ²chip resets².  
To minimize power consumption, all I/O pins  
should be carefully managed before entering the  
HALT status.  
TO  
PD  
RESET Conditions  
0
0
RES reset during power-up  
RES reset during normal  
operation  
u
0
1
1
u
1
u
1
Reset  
Therearethreewaysinwhicharesetcanoccur:  
RES wake-up HALT  
·
·
·
RES reset during normal operation  
RES reset during HALT  
WDT time-out during normal  
operation  
WDT time-out reset during normal operation  
WDT wake-up HALT  
V
D
D
R
E
S
Note: ²u² means ²unchanged²  
t
S
S
T
To guarantee that the system oscillator has  
started and stabilized, the SST (System  
Start-up Timer) provides an extra-delay, to de-  
S
S
T
T
i
m
e
-
o
u
t
C
h
i
p
R
e
s
e
t
t
S
S
:
T
d
e
p
e
n
d
s
o
n
O
S
C
a
s
k
o
p
t
i
o
n
m lay 1024 system clock pulses when the system  
Reset timing chart  
powers up or awakes from the HALT state.  
The WDT time-out during HALT is different  
from other chip reset conditions, since it can  
perform a ²warm reset² that just resets the PC  
and SP, leaving the other circuits in their origi-  
nal state. Some registers remain unchanged  
When the system power-up occurs, the SST de-  
lay is added during the reset period. But when  
the reset comes from the RES pin, the SST de-  
lay is disabled. Any wake-up from HALT will  
enable the SST delay.  
20  
November 10, 1999  
HT99C810/HT99C811  
The states of the registers are summarized in the following table:  
WDT  
RES Reset  
(Normal  
Operation)  
WDT  
RES Reset  
Time-Out*  
(HALT)  
Reset  
(Power On)  
Time-Out  
(Normal  
Operation)  
Register  
(HALT)  
TMR1H  
xxxx xxxx  
xxxx xxxx  
00-0 1---  
uuuu uuuu  
uuuu uuuu  
00-0 1---  
uuuu uuuu  
uuuu uuuu  
00-0 1---  
uuuu uuuu  
uuuu uuuu  
00-0 1---  
uuuu uuuu  
uuuu uuuu  
uu-u u---  
TMR1L  
TMR1C  
TMR0H  
TMR0L  
TMR0C  
PC  
xxxx xxxx  
xxxx xxxx  
00-0 1---  
uuuu uuuu  
uuuu uuuu  
00-0 1---  
uuuu uuuu  
uuuu uuuu  
00-0 1---  
uuuu uuuu  
uuuu uuuu  
00-0 1---  
uuuu uuuu  
uuuu uuuu  
uu-u u---  
0000H  
0000H  
0000H  
0000H  
0000H  
MP0  
xxxx xxxx  
xxxx xxxx  
xxxx xxxx  
xxxx xxxx  
xxxx xxxx  
--00 xxxx  
-000 0000  
0000 0111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
--1u uuuu  
-000 0000  
0000 0111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
--uu uuuu  
-000 0000  
0000 0111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
--01 uuuu  
-000 0000  
0000 0111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
--11 uuuu  
MP1  
ACC  
TBLP  
TBLH  
STATUS  
INTC  
-uuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
WDTS  
PA  
PAC  
PB  
PBC  
D/A Output Register  
D/A Control Register 1111 1111  
PD  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
PDC  
PE  
PEC  
PF  
PFC  
PG  
PGC  
Note: ²*² means ²warm reset²  
²x² means ²unknown²  
²u² means ²unchanged² .  
²-² means ²undefined²  
The bits of the special function registers are denoted as ²-² if they are not defined  
in the microcontrollers.  
21  
November 10, 1999  
HT99C810/HT99C811  
The functional unit chip reset status is shown  
in the following table.  
timer/event counter 0; TMR0H (0CH), TMR0L  
(0DH), TMR0C (0EH). Writing TMR0L only  
writes the data into a low byte buffer, and writ-  
ing TMR0H will simultaneously write the data  
and the contents of the low byte buffer into the  
timer/event counter 0 preload register (16-bit).  
The timer/event counter 0 preload register is  
changed by writing TMR0H operations and  
writing TMR0L will keep the timer/event coun-  
ter 0 preload register unchanged.  
PC  
Interrupt  
000H  
Disabled  
Cleared  
Prescaler  
Cleared. After master  
reset, WDT starts  
counting  
WDT  
Reading TMR0H will also latch the TMR0L  
into the low byte buffer to avoid the false timing  
problem. Reading TMR0L returns the contents  
of the low byte buffer. In other words, the low  
byte of timer/event counter 0 cannot be read di-  
rectly. It must read the TMR0H first to make  
the low byte contents of timer/event counter 0  
latched into the buffer.  
Timer/event  
counter (0/1)  
Off  
Input/output ports Input mode  
Points to the top of the  
stack  
SP  
Timer/event counter  
There are three registers related to timer/event  
counter 1; TMR1H (0FH), TMR1L (10H),  
TMR1C (11H). The timer/event counter 1 oper-  
ates in the same manner as with timer/event  
counter 0.  
Two timer/event counters are implemented in  
the HT99C810/HT99C811. The timer/event  
counter 0 and timer/event counter 1 contain  
16-bit programmable count-up counters and  
the clock may come from an external source or  
the system clock divided by 4.  
The TMR0C is the timer/event counter 0 con-  
trol register, which defines the timer/event  
counter 0 options. The timer/event counter 1  
has the same options as the timer/event coun-  
ter 0 and is defined by TMR1C.  
Using the internal instruction clock, there is  
only one reference time-base. The external  
clock input allows the user to count external  
events, measure time intervals or pulse width,  
or generate an accurate time base.  
The timer/event counter control registers de-  
fine the operation mode, counting enable or dis-  
able and active edge.  
There are three registers related to the  
Label (TMRC)  
Bits  
Function  
0~2  
¾
Unused bits, read as ²0²  
To define the TMR active edge of the timer/event counter  
(0=active on low to high; 1=active on high to low)  
TE  
3
To enable/disable timer counting  
(0=disabled; 1=enabled)  
TON  
4
5
¾
Unused bits, read as ²0²  
To define the operation mode  
01=Event count mode (external clock)  
10=Timer mode (internal clock)  
11=Pulse width measurement mode  
00=Unused  
TM0  
TM1  
6
7
TMR0C/TMR1C register  
22  
November 10, 1999  
HT99C810/HT99C811  
The TM0, TM1 bits define the operation mode.  
The event count mode is used to count external  
events, which means the clock source comes  
from an external (TMR0/TMR1) pin. The timer  
mode functions as a normal timer with the  
clock source coming from the instruction clock.  
The pulse width measurement mode can be  
used to count the high or low level duration of  
the external signal (TMR0/TMR1). The count-  
ing is based on the instruction clock.  
two modes.  
To enable the counting operation, the Timer ON  
bit (TON; bit 4 of TMR0C/TMR1C) should be  
set to 1. In the pulse width measurement mode,  
the TON will automatically be cleared after the  
measurement cycle is completed. But in the  
other two modes, the TON can only be reset by  
instruction. The overflow of the timer/event  
counter is one of the wake-up sources. No mat-  
ter what type of operation mode is, writing a 0  
to ET0I/ET1I can disable the corresponding in-  
terrupt service.  
In the Event count or Timer mode, once the  
timer/event counter starts counting, it will  
count from the current contents in the  
timer/event counter to FFFFH. Once overflow  
occurs, the counter is reloaded from the  
timer/event counter preload register and gener-  
ates the corresponding interrupt request flag  
(T0F/T1F; bit 5/6 of INTC) at the same time.  
In the case of timer/event counter OFF condi-  
tion, writing data to the timer/event counter  
preload register will also reload that data to  
timer/event counter. But if the timer/event  
counter is turned on, data written to the  
timer/event counter will only be kept in the  
timer/event counter preload register. The  
timer/event counter will still operate until  
an overflow occurs.  
In the pulse width measurement mode, the TON  
and TE bits are equal to one. Once the  
TMR0/TMR1 has received a transient from low  
to high (or high to low; if the TE bit is 0) it will  
start counting until the TMR0/TMR1 returns to  
the original level and resets the TON. The mea-  
sured result will remain in the timer/event coun-  
ter even if the activated transient occurs again.  
In other words, only one cycle measurements  
can be made until the TON is set. The cycle mea-  
surement will function again as long as it re-  
ceives further transient pulse. Note that, in this  
operation mode, the timer/event counter starts  
counting not according to the logic level but ac-  
cording to the transient edges. In the case of  
counter overflows, the counter is reloaded from  
the timer/event counter preload register and is-  
sues an interrupt request similar to the other  
When the timer/event counter (reading  
TMR0H/TMR1H) is read, the clock will be  
blocked to avoid errors. As this may results  
in a counting error, this must be taken into  
consideration by the programmer.  
Input/output ports  
There are 48 bidirectional input/output lines in  
the HT99C810/HT99C811, labeled from PA to  
PG except PC, which are mapped to the data  
memory of [12H], [14H], [18H], [1AH], [1CH]  
and [1EH] respectively. All these I/O ports can  
be used for input and output operations. For in-  
put operation, these ports are non-latching,  
D
a
t
a
B
u
s
S
y
s
t
e
m
C
l
o
c
k
/
4
T
T
M
M
1
0
R
e
l
o
a
d
o u  
t
T
i
m
e
r
/
E
v
e
n
t
C
n
t
e
r
0
P
r
e
l
o
a
d
R
e
g
i
s
e
r
T
T
M
M
R
R
0
1
T
E
P
u
l
s
e
W
i
d
t
h
T
i
m
e
r
/
E
v
e
n
t
T
T
T
M
M
1
0
M
e
a
s
u
r
e
m
e
n
t
C
o
u
n
t
e
r
0
O
t
v
e
r
f
l
o
w
M
o
d
e
C
o
n
t
r
o
l
O
N
o
I
n
t
e
r
r
u
p
t
L
o
w
B
y
t
e
B
u
f
f
e
r
Timer/event counter0/1  
23  
November 10, 1999  
HT99C810/HT99C811  
V
D
D
D
C
D
a
t
a
B
u
s
Q
W
P
e
a
k
K
W
r
i
t
e
C
o
n
t
r
o
l
R
Q
e
g
i
s
t
e
r
u
l
l
-
u
p
P
e
A
t
o
P
G
S
V
D
D
x
c
e
p
t
P
B
,
P
C
C
h
i
p
R
e
s
e
t
M
a
s
k
O
p
t
i
o
n
R
e
a
d
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
P
P
P
P
P
P
A
B
D
E
F
G
0
0
~
~
P
P
A
B
7
7
D
C
Q
0
~
P
D
7
0
~
P
E
7
K
O
Q
W
r
i
t
e
I
/
0
~
P
F
7
S
0
~
P
G
7
M
U
X
R
e
a
d
I
/
O
S
y
s
t
e
m
W
a
k
e
-
u
p
(
P
A
o
n
l
y
)
M
a
s
k
O
p
t
i
o
n
Input/output ports  
that is, the inputs must be ready at the T2 ris-  
ing edge of instruction MOV A,[m] (m=12H,  
14H, 18H, 1AH, 1CH or 1EH). For output oper-  
ation, all data is latched and remains un-  
changed until the output latch is rewritten.  
mapped to locations 13H, 15H, 19H, 1BH, 1DH  
and1FH.  
After a chip reset, these input/output lines stay  
at high levels or floating (mask option). Each  
bit of these input/output latches can be set or  
cleared by the SET [m].i or CLR [m].i (m=12H,  
14H, 18H, 1AH, 1CH or 1EH) instruction.  
Each I/O line has its own control register (PAC,  
PBC, PDC, PEC, PFC, PGC) to control the in-  
put/output configuration. With this control reg-  
ister, CMOS output or schmitt trigger input  
with or without pull-high resistor (mask option)  
structurescanbereconfigureddynamically(i.e.,  
on-the-fly) under software control. To function  
as an input, the corresponding latch of the con-  
trol register must write a ²1². The pull-high re-  
sistance will exhibit automatically if the  
pull-high option is selected. The input source(s)  
also depend(s) on the control register. If the con-  
trol register bit is ²1², input will read the pad  
state. If the control register bit is ²0², the con-  
tents of the latches will move to the internal bus.  
The latter is possible in ²read-modify-write² in-  
struction. For outputfunction, CMOSistheonly  
configuration. These control registers are  
Some instructions first input data and then fol-  
low the output operations. For example, the  
SET [m].i, CLR [m].i, CPL [m] and CPLA [m]  
instructions read the entire port states into the  
CPU, execute the defined operations  
(bit-operation), and then write the results back  
to the latches or the accumulator.  
Each line of port A has the capability to  
wake-up the device.  
The 8-bit D/A output register is mapped to the  
data memory of [16H] and its corresponding  
control register is mapped to location [17H]  
which must be set to ²0² after initialization,  
when using the D/A function.  
24  
November 10, 1999  
HT99C810/HT99C811  
Mask option  
The following table shows five kinds of mask options in the HT99C810/HT99C811. All the mask op-  
tions must be defined to ensure proper system functioning.  
No.  
Mask Option  
OSC type selection. This option is to determine whether an RC or Crystal oscillator is  
chosen as system clock. If the Crystal oscillator is selected, the XST (Crystal Start-up  
Timer) default is activated; otherwise the XST is disabled.  
1
WDT source selection. There are three types of selection: on-chip RC oscillator, instruc-  
tion clock or disable the WDT.  
2
3
CLRWDT times selection. This option defines how to clear the WDT by instruction. One  
time means that the CLR WDT instruction can clear the WDT. ²Two times² means that  
only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then the  
WDT can be cleared.  
Wake-up selection. This option defines the activity of the wake-up function. External I/O  
pins (PA only) all have the capability to wake-up the chip from a HALT.  
4
5
Pull-high selection. This option is to determine whether the pull-high resistance is visi-  
ble or not in the input mode of the I/O ports. Each bit of an I/O port can be independently  
selected. (See Note)  
Note: There are no pull-high selections in port B of HT99C810/HT99C811.  
There are pull-high selections in port A, port D, port E, port F and port G of HT99C810 but  
they are always pulled-high in port A, port D, port E, port F and port G of HT99C811.  
There are no mask option in port C of HT99C810/HT99C811.  
25  
November 10, 1999  
HT99C810/HT99C811  
HT99C811 PROM programming and verification  
Select the TSEL and OSEL to program and ver-  
ify the program PROM and the option PROM.  
Use the R/W(PA6) to select programming or  
verification.  
The program memory used in the HT99C811 is  
arranged into a 8K´16 bits program PROM and  
a 1´14 bits option PROM. The program code  
and option code are stored in the program  
PROM and option PROM. The programming of  
PROM can be summarized in nine steps as de-  
scribed below:  
The address is automatically incremented by  
one after a code verification cycle. If discontin-  
ued address programming or verification is car-  
ried out, the automatic addressing increment is  
disabled. For discontinued address program-  
ming and verification, the CS pin must return  
to a high level for a programming or verification  
cycle, i.e. if a discontinued address is imple-  
mented, the programming or verification cycle  
must be interrupted and restarted as well.  
·
·
·
Power on  
Set VPP (RES) to 12.5V  
Set CS (PA5) to low  
Let PA3~PA0 (AD3~AD0) be the address and  
data bus and the PA4 (CLK) be the clock input.  
The data on the AD3~AD0 pins will be clocked  
into or out the HT99C811 on the falling edge of  
PA4(CLK) for PROM programming and verifi-  
cation.  
The related pins of PROM programming and  
verification are listed in the following table.  
Pin  
Name  
Function  
Description  
The address data contains the code address (11  
bits) and two option bits. A complete write cycle  
will contain 4 CLK cycles. The first cycle, bits  
0~3 of the address are latched into the  
HT99C811. The second and third cycles, bits  
4~7 and bits 8~10 are latched respectively. The  
fourth cycle, bit 2 is the TSEL option bit and bit  
3 is the OSEL option bit. Bit 3 in the third cycle  
and bit 0~1 in the fourth cycle are undefined. If  
the TSEL is ²1² and the OSEL is ²0², the TEST  
memory will be read. If the TSEL is ²0² and the  
OSEL is ²1², the option PROM will be accessed.  
If both the TSEL and OSEL are ²0², the pro-  
gram PROM will be managed.  
PA0  
Bit 0 of address/data bus  
Bit 1 of address/data bus  
Bit 2 of address/data bus  
Bit 3 of address/data bus  
AD0  
AD1  
AD2  
AD3  
PA1  
PA2  
PA3  
Serial clock input for ad-  
dress and data  
PA4  
CLK  
PA5  
PA6  
Chip select, active low  
Read/write control input  
CS  
R/W  
Programming power  
supply  
RES  
VPP  
The code data is 14 bits wide. A complete  
read/write cycle contains 4 CLK cycles. In the  
first cycle, bits 0~3 of the code data are ac-  
cessed. In the second and third, bits 4~7 and  
bits 8~11 are accessed respectively. In the  
fourth cycle, bits 12~13 are accessed. Bits  
14~15 are undefined. During code verification,  
reading will return the result ²00².  
The timing charts of programming and verifica-  
tion are as shown. There is a LOCK signal for  
code protection. If the LOCK is ²1², reading the  
code will return the result ²1². However, if the  
LOCK is ²0², the code protection is disabled and  
the code always can be read until the LOCK is  
programmed as ²1².  
26  
November 10, 1999  
HT99C810/HT99C811  
Application Circuits  
Cordless phone controller arrangement  
·
Base unit: HT99C810/HT99C811  
PA0  
PO  
PB0  
INUSE  
PD0  
MODE  
AOUT  
DTMF  
PA1  
PA2  
PA3  
DATI  
DATO  
TXEN  
PB1  
PB2  
PB3  
KT  
RING  
HKS  
PD1  
PD2  
PD3  
M/BR  
CARRY  
LED  
PA4  
PA5  
PA6  
PA7  
PWDN  
FTS  
FCD  
PB4  
PB5  
PB6  
PB7  
HDO  
PD4  
PD5  
PD6  
PD7  
D0  
D1  
D2  
D3  
HLEN  
BLEN  
SPKEN  
INT/PAGE  
A
N
T
S
P
K
T
I
P
B
a
s
e
U
n
i
t
S
p
l
i
t
t
R
e
F
r
U
n
i
t
R
e
c
e
i
v
e
r
R
I
N
G
W
a
v
e
S
h
a
p
i
n
g
S
p
e
e
c
h
M
I
C
C
C
i
i
r
r
c
c
u
u
i
i
t
t
&
D
A
T
I
H
H
y
b
r
i
d
D
O
B
L
E
N
3
.
5
8
M
H
z
X
X
2
1
S
P
K
H
L
E
N
R
I
N
G
S
P
K
E
N
C
A
R
R
Y
K
T
M
I
C
D
D
D
D
0
1
2
3
D
T
M
F
F
r
e
q
u
e
n
c
y
P
O
S
y
n
t
h
e
s
i
z
e
r
H
K
S
M
M
F
O
/
D
E
V
D
D
O
P
T
I
O
N
B
R
T
S
C
h
a
r
g
e
P
A
G
E
P
A
G
E
P
o
w
e
r
o
n
T
e
r
m
i
n
a
l
R
E
S
R
e
s
e
t
V
T
S
S
S
e
c
u
r
i
t
y
D
C
F
C
D
C
o
d
e
P
o
w
e
r
A
l
C
1
1
0
V
S
W
X
E
N
S
u
p
p
y
V
D
D
D
A
T
O
R
F
U
n
i
t
T
r
a
n
s
m
i
t
t
e
r
H
T
9
9
C
8
1
0
/
H
T
9
9
C
8
1
1
W
a
v
e
S
h
a
p
i
n
g
27  
November 10, 1999  
HT99C810/HT99C811  
Instruction Set Summary  
Mnemonic  
Description  
Flag Affected  
Arithmetic  
ADD A,[m]  
ADDM A,[m]  
ADD A,x  
Add data memory to ACC  
Add ACC to data memory  
Add immediate data to ACC  
Z,C,AC,OV  
Z,C,AC,OV  
Z,C,AC,OV  
Z,C,AC,OV  
Z,C,AC,OV  
Z,C,AC,OV  
Z,C,AC,OV  
ADC A,[m]  
ADCM A,[m]  
SUB A,x  
Add data memory to ACC with carry  
Add ACC to register with carry  
Subtract immediate data from ACC  
Subtract data memory from ACC  
SUB A,[m]  
SUBM A,[m]  
SBC A,[m]  
SBCM A,[m]  
Subtract data memory from ACC with result in data memory  
Subtract data memory from ACC with carry  
Subtract data memory from ACC with carry, result in data  
memory  
Z,C,AC,OV  
Z,C,AC,OV  
Z,C,AC,OV  
DAA [m]  
Decimal adjust ACC for addition with result in data memory  
C
Logic Operation  
AND A,[m]  
OR A,[m]  
XOR A,[m]  
ANDM A,[m]  
ORM A,[m]  
XORM A,[m]  
AND A,x  
AND data memory to ACC  
OR data memory to ACC  
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Exclusive-OR data memory to ACC  
AND ACC to data memory  
OR ACC to data memory  
Exclusive-OR ACC to data memory  
AND immediate data to ACC  
OR immediate data to ACC  
OR A,x  
XOR A,x  
Exclusive-OR immediate data to ACC  
Complement data memory  
Complement data memory with result in ACC  
CPL [m]  
CPLA [m]  
Increment and  
Decrement  
Z
Z
Z
Z
INCA [m]  
INC [m]  
Increment data memory with result in ACC  
Increment data memory  
DECA [m]  
DEC [m]  
Decrement data memory with result in ACC  
Decrement data memory  
Rotate  
RRA [m]  
RR [m]  
Rotate data memory right with result in ACC  
Rotate data memory right  
None  
None  
C
RRCA [m]  
RRC [m]  
RLA [m]  
RL [m]  
Rotate data memory right through carry with result in ACC  
Rotate data memory right through carry  
Rotate data memory left with result in ACC  
Rotate data memory left  
C
None  
None  
C
RLCA [m]  
RLC [m]  
Rotate data memory left through carry with result in ACC  
Rotate data memory left through carry  
C
28  
November 10, 1999  
HT99C810/HT99C811  
Mnemonic  
Description  
Flag Affected  
Data Move  
MOV A,[m]  
MOV [m],A  
MOV A,x  
Move data memory to ACC  
Move ACC to data memory  
Move immediate data to ACC  
None  
None  
None  
Bit Operation  
CLR [m].i  
SET [m].i  
Clear bit of data memory  
Set bit of data memory  
None  
None  
Branch  
JMP addr  
SZ [m]  
Jump unconditional  
Skip if data memory is zero  
None  
None  
SZA [m]  
SZ [m].i  
SNZ [m].i  
SIZ [m]  
SDZ [m]  
SIZA [m]  
SDZA [m]  
CALL addr  
RET  
Skip if data memory is zero with data movement to ACC  
Skip if bit i of data memory is zero  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
Skip if bit i of data memory is not zero  
Skip if increment data memory is zero  
Skip if decrement data memory is zero  
Skip if increment data memory is zero with result in ACC  
Skip if decrement data memory is zero with result in ACC  
Subroutine call  
Return from subroutine  
Return from subroutine and load immediate data to ACC  
Return from interrupt  
RET A,x  
RETI  
Table Read  
TABRDC [m]  
TABRDL [m]  
Read ROM code (current page) to data memory and TBLH  
Read ROM code (last page) to data memory and TBLH  
None  
None  
Miscellaneous  
NOP  
CLR [m]  
SET [m]  
No operation  
Clear data memory  
Set data memory  
None  
None  
None  
CLR WDT  
CLR WDT1  
CLR WDT2  
SWAP [m]  
SWAPA [m]  
HALT  
Clear the watchdog timer  
Pre-clear the watchdog timer  
Pre-clear the watchdog timer  
Swap nibbles of data memory  
Swap nibbles of data memory with result in ACC  
Enter power down mode  
TO,PD  
TO*,PD*  
TO*,PD*  
None  
None  
TO,PD  
Note: x: 8-bit immediate data  
m: 8-bit data memory address  
A: accumulator  
addr: 12-bit program memory address  
Ö : Flag(s) is affected  
-: Flag(s) is not affected  
i: 0~7 number of bits  
*: Flag(s) may be affected by the execution status  
29  
November 10, 1999  
HT99C810/HT99C811  
Instruction Definition  
ADC A,[m]  
Add data memory and carry to accumulator  
Description  
The contents of the specified data memory, accumulator and the carry flag  
are added simultaneously, leaving the result in the accumulator.  
Operation  
ACC ¬ ACC+[m]+C  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]  
Add accumulator and carry to data memory  
Description  
The contents of the specified data memory, accumulator and the carry flag  
are added simultaneously, leaving the result in the specified data memory.  
Operation  
[m] ¬ ACC+[m]+C  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]  
Add data memory to accumulator  
Description  
The contents of the specified data memory and the accumulator are added.  
The result is stored in the accumulator.  
Operation  
ACC ¬ ACC+[m]  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x  
Add immediate data to accumulator  
Description  
The contents of the accumulator and the specified data are added, leaving  
the result in the accumulator.  
Operation  
ACC ¬ ACC+x  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
30  
November 10, 1999  
HT99C810/HT99C811  
ADDM A,[m]  
Add accumulator to data memory  
Description  
The contents of the specified data memory and the accumulator are added.  
The result is stored in the data memory.  
Operation  
[m] ¬ ACC+[m]  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
AND A,[m]  
Logical AND accumulator with data memory  
Description  
Data in the accumulator and the specified data memory performs a bitwise  
logical_AND operation. The result is stored in the accumulator.  
Operation  
ACC ¬ ACC ²AND² [m]  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x  
Logical AND immediate data to accumulator  
Description  
Data in the accumulator and the specified data performs a bitwise logi-  
cal_AND operation. The result is stored in the accumulator.  
Operation  
ACC ¬ ACC ²AND² x  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]  
Logical AND data memory with accumulator  
Description  
Data in the specified data memory and the accumulator performs a bitwise  
logical_AND operation. The result is stored in the data memory.  
Operation  
[m] ¬ ACC ²AND² [m]  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
31  
November 10, 1999  
HT99C810/HT99C811  
CALL addr  
Subroutine call  
Description  
The instruction unconditionally calls a subroutine located at the indicated  
address. The program counter increments once to obtain the address of the  
next instruction, and pushes this onto the stack. The indicated address is  
then loaded. Program execution continues with the instruction at this ad-  
dress.  
Operation  
Stack ¬ PC+1  
PC ¬ addr  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m]  
Clear data memory  
Description  
Operation  
The contents of the specified data memory are cleared to zero.  
[m] ¬ 00H  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m].i  
Clear bit of data memory  
Description  
Operation  
The bit i of the specified data memory is cleared to zero.  
[m].i ¬ 0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT  
Clear the watchdog timer  
Description  
The WDT and the WDT Prescaler are cleared (re-counting from zero). The  
power down bit (PD) and time-out bit (TO) are cleared.  
Operation  
WDT and WDT Prescaler ¬ 00H  
PD and TO ¬ 0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
0
0
¾
¾
¾
¾
¾
¾
32  
November 10, 1999  
HT99C810/HT99C811  
CLR WDT1  
Preclear the watchdog timer  
Description  
The PD, TO flags, WDT and the WDT Prescaler are cleared (re-counting  
from zero), if the other preclear WDT instruction had been executed. Only  
execution of this instruction without the other preclear instruction just sets  
the indicating flag which implies that this instruction was executed and the  
PD and TO flags remain unchanged.  
Operation  
WDT and WDT Prescaler ¬ 00H*  
PD and TO ¬ 0*  
Affected flag(s)  
TC2 TC1 TO PD OV  
0* 0*  
Z
AC  
C
¾
¾
¾
¾
¾
¾
CLR WDT2  
Preclear the watchdog timer  
Description  
The PD and TO flags, WDT and the WDT Prescaler are cleared (re-counting  
from zero), if the other preclear WDT instruction had been executed. Only  
execution of this instruction without the other preclear instruction, sets the  
indicating flag which implies that this instruction was executed and the PD  
and TO flags remain unchanged.  
Operation  
WDT and WDT Prescaler ¬ 00H*  
PD and TO ¬ 0*  
Affected flag(s)  
TC2 TC1 TO PD OV  
0* 0*  
Z
AC  
C
¾
¾
¾
¾
¾
¾
CPL [m]  
Complement data memory  
Description  
Each bit of the specified data memory is logically complemented (1¢s comple-  
ment). Bits which previously contain a one are changed to zero and  
vice-versa.  
Operation  
[m] ¬ [m]  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
33  
November 10, 1999  
HT99C810/HT99C811  
CPLA [m]  
Complement data memory and place result in accumulator  
Description  
Each bit of the specified data memory is logically complemented (1¢s comple-  
ment). Bits which previously contained a one are changed to zero and  
vice-versa. The complemented result is stored in the accumulator and the  
contents of the data memory remain unchanged.  
Operation  
ACC ¬ [m]  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]  
Decimal-Adjust accumulator for addition  
Description  
The accumulator value is adjusted to the BCD (Binary Code Decimal) code.  
The accumulator is divided into two nibbles. Each nibble is adjusted to the  
BCD code and an internal carry (AC1) will be done if the low nibble of the ac-  
cumulator is greater than 9. The BCD adjustment is done by adding 6 to the  
original value if the original value is greater than 9 or a carry (AC or C) is set;  
otherwise the original value remains unchanged. The result is stored in the  
data memory and only the carry flag (C) may be affected.  
Operation  
If (ACC.3~ACC.0) >9 or AC=1  
then ([m].3~[m].0) ¬ (ACC.3~ACC.0)+6, AC1=AC  
else ([m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0  
If (ACC.7~ACC.4)+AC1 >9 or C=1  
then ([m].7~[m].4) ¬ (ACC.7~ACC.4)+6+AC1, C=1  
else ([m].7~[m].4) ¬ (ACC.7~ACC.4)+AC1, C=C  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
Ö
DEC [m]  
Decrement data memory  
Description  
Operation  
Data in the specified data memory is decremented by one.  
[m] ¬ [m]-1  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
34  
November 10, 1999  
HT99C810/HT99C811  
DECA [m]  
Decrement data memory and place result in accumulator  
Description  
Data in the specified data memory is decremented by one, leaving the result  
in the accumulator. The contents of the data memory remain unchanged.  
Operation  
ACC ¬ [m]-1  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
HALT  
Enter power down mode  
Description  
This instruction stops the program execution and turns off the system clock.  
The contents of the RAM and registers are retained. The WDT and prescaler  
are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is  
cleared.  
Operation  
PC ¬ PC+1  
PD ¬ 1  
TO ¬ 0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
0
1
¾
¾
¾
¾
¾
¾
INC [m]  
Increment data memory  
Description  
Operation  
Affected flag(s)  
Data in the specified data memory is incremented by one.  
[m] ¬ [m]+1  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]  
Increment data memory and place result in accumulator  
Description  
Data in the specified data memory is incremented by one, leaving the result  
in the accumulator. The contents of the data memory remain unchanged.  
Operation  
ACC ¬ [m]+1  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
35  
November 10, 1999  
HT99C810/HT99C811  
JMP addr  
Direct Jump  
Description  
Bits 0~11 of the program counter are replaced with the directly-specified ad-  
dress unconditionally, and control passed to this destination.  
Operation  
PC ¬ addr  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,[m]  
Description  
Operation  
Move data memory to accumulator  
The contents of the specified data memory is copied to the accumulator.  
ACC ¬ [m]  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,x  
Move immediate data to accumulator  
Description  
Operation  
The 8 bit data specified by the code is loaded into the accumulator.  
ACC ¬ x  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A  
Move accumulator to data memory  
Description  
The contents of the accumulator is copied to the specified data memory (one  
of the data memory).  
Operation  
[m] ¬ ACC  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
NOP  
No operation  
Description  
Operation  
Affected flag(s)  
No operation is performed. Execution continues with the next instruction.  
PC ¬ PC+1  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
36  
November 10, 1999  
HT99C810/HT99C811  
OR A,[m]  
Logical OR accumulator with data memory  
Description  
Data in the accumulator and the specified data memory (one of the data  
memory) performs a bitwise logical_OR operation. The result is stored in the  
accumulator.  
Operation  
ACC ¬ ACC ²OR² [m]  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x  
Logical OR immediate data to accumulator  
Description  
Data in the accumulator and the specified data performs a bitwise logi-  
cal_OR operation. The result is stored in the accumulator.  
Operation  
ACC ¬ ACC ²OR² x  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]  
Logical OR data memory with accumulator  
Description  
Data in the data memory (one of the data memory) and the accumulator per-  
forms a bitwise logical_OR operation. The result is stored in the data mem-  
ory.  
Operation  
[m] ¬ ACC ²OR² [m]  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
RET  
Return from subroutine  
Description  
The program counter is restored from the stack. This is a two cycle instruc-  
tion.  
Operation  
PC ¬ Stack  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
37  
November 10, 1999  
HT99C810/HT99C811  
RET A,x  
Return and place immediate data in accumulator  
Description  
The program counter is restored from the stack and the accumulator loaded  
with the specified 8-bit immediate data.  
Operation  
PC ¬ Stack  
ACC ¬ x  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
RETI  
Return from interrupt  
Description  
The program counter is restored from the stack, and the interrupts are en-  
abled by setting the EMI bit. EMI is the enable master (global) interrupt bit  
(bit 0; register INTC).  
Operation  
PC ¬ Stack  
EMI ¬ 1  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]  
Rotate data memory left  
Description  
The contents of the specified data memory is rotated left, one bit with bit 7  
rotated into bit 0.  
Operation  
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)  
[m].0 ¬ [m].7  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
RLA [m]  
Rotate data memory left and place result in accumulator  
Description  
Data in the specified data memory is rotated left, one bit with bit 7 rotated  
into bit 0, leaving the rotated result in the accumulator. The contents of the  
data memory remain unchanged.  
Operation  
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)  
ACC.0 ¬ [m].7  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
38  
November 10, 1999  
HT99C810/HT99C811  
RLC [m]  
Rotate data memory left through carry  
Description  
The contents of the specified data memory and the carry flag are together ro-  
tated left one bit. Bit 7 replaces the carry bit; the original carry flag is rotated  
into the bit 0 position.  
Operation  
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)  
[m].0 ¬ C  
C ¬ [m].7  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
Ö
RLCA [m]  
Rotate left through carry and place result in accumulator  
Description  
Data in the specified data memory and the carry flag are together rotated  
left one bit. Bit 7 replaces the carry bit and the original carry flag is rotated  
into bit 0 position. The rotated result is stored in the accumulator but the  
contents of the data memory remain unchanged.  
Operation  
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)  
ACC.0 ¬ C  
C ¬ [m].7  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
Ö
RR [m]  
Rotate data memory right  
Description  
The contents of the specified data memory are rotated right one bit with bit 0  
rotated to bit 7.  
Operation  
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)  
[m].7 ¬ [m].0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
39  
November 10, 1999  
HT99C810/HT99C811  
RRA [m]  
Rotate right and place result in accumulator  
Description  
Data in the specified data memory is rotated right one bit with bit 0 rotated  
into bit 7, leaving the rotated result in the accumulator. The contents of the  
data memory remain unchanged.  
Operation  
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)  
ACC.7 ¬ [m].0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]  
Rotate data memory right through carry  
Description  
The contents of the specified data memory and the carry flag are together ro-  
tated right one bit. Bit 0 replaces the carry bit; the original carry flag is ro-  
tated into the bit 7 position.  
Operation  
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)  
[m].7 ¬ C  
C ¬ [m].0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
Ö
RRCA [m]  
Rotate right through carry and place result in accumulator  
Description  
Data of the specified data memory and the carry flag are together rotated  
right one bit. Bit 0 replaces the carry bit and the original carry flag is rotated  
into the bit 7 position. The rotated result is stored in the accumulator. The  
contents of the data memory remain unchanged.  
Operation  
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)  
ACC.7 ¬ C  
C ¬ [m].0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
Ö
40  
November 10, 1999  
HT99C810/HT99C811  
SBC A,[m]  
Subtract data memory and carry from accumulator  
Description  
The contents of the specified data memory and the complement of the carry  
flag are together subtracted from the accumulator, leaving the result in the  
accumulator.  
Operation  
ACC ¬ ACC+[m]+C  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]  
Subtract data memory and carry from accumulator  
Description  
The contents of the specified data memory and the complement of the carry  
flag are together subtracted from the accumulator, leaving the result in the  
data memory.  
Operation  
[m] ¬ ACC+[m]+C  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]  
Skip if decrement data memory is zero  
Description  
The contents of the specified data memory are decremented by one. If the re-  
sult is zero, the next instruction is skipped. If the result is zero, the following  
instruction, fetched during the current instruction execution, is discarded  
and a dummy cycle replaced to get the proper instruction. This makes a 2 cy-  
cle instruction. Otherwise proceed with the next instruction.  
Operation  
Skip if ([m] 1)=0, [m] ¬ ([m]-1)  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
41  
November 10, 1999  
HT99C810/HT99C811  
SDZA [m]  
Decrement data memory and place result in ACC, skip if zero  
Description  
The contents of the specified data memory are decremented by one. If the re-  
sult is zero, the next instruction is skipped. The result is stored in the accu-  
mulator but the data memory remains unchanged. If the result is zero, the  
following instruction, fetched during the current instruction execution, is  
discarded and a dummy cycle is replaced to get the proper instruction, that  
makes a 2 cycle instruction. Otherwise proceed to the next instruction.  
Operation  
Skip if ([m]-1)=0, ACC ¬ ([m]-1)  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m]  
Set data memory  
Description  
Operation  
Each bit of the specified data memory is set to one.  
[m] ¬ FFH  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m].i  
Set bit of data memory  
Description  
Operation  
Bit i of the specified data memory is set to one.  
[m].i ¬ 1  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZ [m]  
Skip if increment data memory is zero  
Description  
The contents of the specified data memory is incremented by one. If the re-  
sult is zero, the following instruction, fetched during the current instruction  
execution, is discarded and a dummy cycle is replaced to get the proper in-  
struction. This is a 2-cycle instruction. Otherwise proceed to the next in-  
struction.  
Operation  
Skip if ([m]+1)=0, [m] ¬ ([m]+1)  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
42  
November 10, 1999  
HT99C810/HT99C811  
SIZA [m]  
Increment data memory and place result in ACC, skip if zero  
Description  
The contents of the specified data memory is incremented by one. If the re-  
sult is zero, the next instruction is skipped and the result stored in the accu-  
mulator. The data memory remains unchanged. If the result is zero, the  
following instruction, fetched during the current instruction execution, is  
discarded and a dummy cycle replaced to get the proper instruction. This is a  
2-cycle instruction. Otherwise proceed to the next instruction.  
Operation  
Skip if ([m]+1)=0, ACC ¬ ([m]+1)  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
SNZ [m].i  
Skip if bit i of the data memory is not zero  
Description  
If bit i of the specified data memory is not zero, the next instruction is  
skipped. If bit i of the data memory is not zero, the following instruction,  
fetched during the current instruction execution, is discarded and a dummy  
cycle is replaced to get the proper instruction. This is a 2-cycle instruction.  
Otherwise proceed to the next instruction.  
Operation  
Skip if [m].i¹0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
SUB A,[m]  
Subtract data memory from accumulator  
Description  
The specified data memory is subtracted from the contents of the accumula-  
tor, leaving the result in the accumulator.  
Operation  
ACC ¬ ACC+[m]+1  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]  
Subtract data memory from accumulator  
Description  
The specified data memory is subtracted from the contents of the accumula-  
tor, leaving the result in the data memory.  
Operation  
[m] ¬ ACC [m]+1  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
43  
November 10, 1999  
HT99C810/HT99C811  
SUB A,x  
Subtract immediate data from accumulator  
Description  
The immediate data specified by the code is subtracted from the contents of  
the accumulator, leaving the result in the accumulator.  
Operation  
ACC ¬ ACC+x+1  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]  
Swap nibbles within the data memory  
Description  
The low-order and high-order nibbles of the specified data memory (one of  
the data memory) are interchanged.  
Operation  
[m].3~[m].0 « [m].7~[m].4  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
SWAPA [m]  
Swap data memory-place result in accumulator  
Description  
The low-order and high-order nibbles of the specified data memory are inter-  
changed, writing the result to the accumulator. The contents of the data  
memory remain unchanged.  
Operation  
ACC.3~ACC.0 ¬ [m].7~[m].4  
ACC.7~ACC.4 ¬ [m].3~[m].0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m]  
Skip if data memory is zero  
Description  
If the contents of the specified data memory is zero, the following instruc-  
tion, fetched during the current instruction execution, is discarded and a  
dummy cycle is replaced to get the proper instruction. This is a 2-cycle in-  
struction. Otherwise proceed to the next instruction.  
Operation  
Skip if [m]=0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
44  
November 10, 1999  
HT99C810/HT99C811  
SZA [m]  
Move data memory to ACC, skip if zero  
Description  
The contents of the specified data memory is copied to accumulator. If the  
contents is zero, the following instruction, fetched during the current in-  
struction execution, is discarded and a dummy cycle is replaced to get the  
proper instruction. This is a 2-cycle instruction. Otherwise proceed to the  
next instruction.  
Operation  
Skip if [m]=0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m].i  
Skip if bit i of the data memory is zero  
Description  
If bit i of the specified data memory is zero, the following instruction, fetched  
during the current instruction execution, is discarded and a dummy cycle is  
replaced to get the proper instruction. This is a 2-cycle instruction. Other-  
wise proceed to the next instruction.  
Operation  
Skip if [m].i=0  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]  
Move ROM code (current page) to TBLH and data memory  
Description  
The low byte of ROM code (current page) addressed by the table pointer  
(TBLP) is moved to the specified data memory and the high byte transferred  
to TBLH directly.  
Operation  
[m] ¬ ROM code (low byte)  
TBLH ¬ ROM code (high byte)  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDL [m]  
Move ROM code (last page) to TBLH and data memory  
Description  
The low byte of ROM code (last page) addressed by the table pointer (TBLP)  
is moved to the data memory and the high byte transferred to TBLH directly.  
Operation  
[m] ¬ ROM code (low byte)  
TBLH ¬ ROM code (high byte)  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
¾
¾
¾
45  
November 10, 1999  
HT99C810/HT99C811  
XOR A,[m]  
Logical XOR accumulator with data memory  
Description  
Data in the accumulator and the indicated data memory performs a bitwise  
logical Exclusive_OR operation and the result is stored in the accumulator.  
Operation  
ACC ¬ ACC ²XOR² [m]  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
XORM A,[m]  
Logical XOR data memory with accumulator  
Description  
Data in the indicated data memory and the accumulator perform a bitwise  
logical Exclusive_OR operation. The result is stored in the data memory. The  
zero flag is affected.  
Operation  
[m] ¬ ACC ²XOR² [m]  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x  
Logical XOR immediate data to accumulator  
Description  
Data in the the accumulator and the specified data perform a bitwise logical  
Exclusive_OR operation. The result is stored in the accumulator. The zero  
flag is affected.  
Operation  
ACC ¬ ACC ²XOR² x  
Affected flag(s)  
TC2 TC1 TO PD OV  
Z
AC  
C
¾
¾
¾
¾
¾
Ö
¾
¾
46  
November 10, 1999  
HT99C810/HT99C811  
Holtek Semiconductor Inc. (Headquarters)  
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.  
Tel: 886-3-563-1999  
Fax: 886-3-563-1189  
Holtek Semiconductor Inc. (Taipei Office)  
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.  
Tel: 886-2-2782-9635  
Fax: 886-2-2782-9636  
Fax: 886-2-2782-7128 (International sales hotline)  
Holtek Semiconductor (Hong Kong) Ltd.  
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong  
Tel: 852-2-745-8288  
Fax: 852-2-742-8657  
Copyright Ó 1999 by HOLTEK SEMICONDUCTOR INC.  
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek  
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are  
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications  
will be suitable without further modification, nor recommends the use of its products for application that may pres-  
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior  
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.  
47  
November 10, 1999  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明