L6713A_技术文档

L6713A

2/3 Phase controller with embedded drivers for Intel VR10, VR11

and AMD 6 bit CPUs

General features

■ Load transient boost (LTB) technology™ to

minimize the number of output capacitors

(patent pending)

■ Dual-edge asynchronous PWM

TQFP64 (Exposed Pad)

■ Selectable 2 or 3 phase operation

■ 0.5% Output voltage accuracy

■ 7/8 bit programmable output up to 1.60000V -

Description

Intel VR10.x, VR11 DAC

L6713A implements a two/three phase step-down

controller with 180º/120º phase-shift between

each phase with integrated high current drivers in

a compact 10x10mm body package with exposed

pad.The 2 or 3 phase operation can be easily

selected through PHASE_SEL pin.

■ 6 bit programmable output up to 1.5500V -

AMD 6 bit DAC

■ High current Integrated gate drivers

■ Full differential current sensing across inductor

■ Embedded VRD thermal monitor

■ Differential remote voltage sensing

■ Dynamic VID management

Load Transient Boost (LTB) Technology™ (Patent

Pending) reduces system cost by providing the

fastest response to load transition therefore

requiring less bulk and ceramic output capacitors

to satisfy load transient requirements.

■ Adjustable voltage offset

■ Low-side-less startup

■ Programmable soft start

LTB Technology™ can be disabled and in this

condition the device works as a dual-edge

asynchronous PWM.

■ Programmable over voltage protection

■ Preliminary over voltage protection

■ Programmable over current protection

■ Adjustable switching frequency

■ Output enable

The device embeds selectable DACs: the output

voltage ranges up to 1.60000V (both Intel VR10.x

and VR11 DAC) or up to 1.5500V (AMD 6BIT

DAC) managing D-VID with 0.5% output voltage

accuracy over line and temperature variations.

■ SS_END / PGOOD signal

The controller assures fast protection against load

over current and under / over voltage (in this last

case also before UVLO). In case of over-current

the device turns off all MOSFET and latches the

condition.

■ TQFP64 10x10mm package with exposed pad

Applications

■ High current VRD for desktop CPUs

■ Workstation and server CPU power supply

■ VRM modules

System Thermal Monitor is also provided allowing

system protection from over-temperature

conditions.

Order codes

Part number

Package

TQFP64 (Exposed Pad)

Packaging

L6713A

Tube

L6713ATR

TQFP64 (Exposed Pad)

Rev 2

Tape and reel

November 2006

1/64

www.st.com

64

Contents

L6713A

Contents

1

2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

2.2

Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3

Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1

3.2

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4

5

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1

5.2

5.3

5.4

5.5

Mapping for the Intel VR11 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Voltage identification (VID) for Intel VR11 Mode . . . . . . . . . . . . . . . . . . . 16

Voltage identifications (VID) for Intel VR10 Mode + 6.25mV . . . . . . . . . . 18

Mapping for the AMD 6BIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Voltage identifications (VID) codes for AMD 6BIT Mode . . . . . . . . . . . . . 20

6

7

8

Reference Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Configuring the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.1

8.2

Number of phases selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DAC Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9

Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Current reading and current sharing loop . . . . . . . . . . . . . . . . . . . . . . 32

Differential remote voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10

11

2/64

L6713A

Contents

12

Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

12.1 Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

12.2 Droop function (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

TM

13

Load Transient Boost Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

13.1 LTB Gain mofidication (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

14

15

16

16.1 Intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

16.1.1 SS/LTB/AMD connections when using LTB Gain = 2 . . . . . . . . . . . . . . . 43

16.1.2 SS/LTB/AMD connections when using LTB Gain < 2 . . . . . . . . . . . . . . . 44

16.2 AMD mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

16.3 Low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

17

Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 47

17.1 Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

17.2 Preliminary over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

17.3 Over voltage and programmable OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

17.4 PGOOD (only for AMD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

18

19

20

21

22

Over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Thermal monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3/64

Contents

L6713A

23

Tolerance band (TOB) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

23.1 Controller tolerance (TOB_Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

23.2 Ext. current sense circuit tolerance (TOB_CurrSense) . . . . . . . . . . . . . . . . . 56

23.3 Time constant matching error tolerance (TOB_TCMatching) . . . . . . . . . . . . . 56

23.4 Temperature measurement error (V_TC) . . . . . . . . . . . . . . . . . . . . . . . . . . 57

24

Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

24.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

24.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 59

25

26

27

Embedding L6713A - based VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4/64

L6713A

Block diagram

1

Block diagram

Figure 1. Block diagram

VR_HOT

VR_FAN

SS_END / PGOOD

HS1

LS1

HS2

LTB

LS2

HS3

LTB

LS3

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

CURRENT SHARING

CORRECTION

CURRENT SHARING

CORRECTION

CURRENT SHARING

CORRECTION

OSC / FAULT

LTB

TM

PWM1

PWM2

PWM3

SS/ LTBG/ AMD

PWM1

PWM3

PWM2

CS1-

CH1 CURRENT

DIGITAL

SOFT START

CS1+

READING

VCC

VCCDR

L6713A

OCP

OUTEN

CONTROL LOGIC

AND PROTECTIONS

CS2-

CH2 CURRENT

READING

SSOSC/AMD

CS2+

VID0

VID1

VID2

CS3-

CH3 CURRENT

READING

VID3

CS3+

TOTAL DELIVERED CURRENT

+175mV / 1.800V / OVP

VID4

VID5

VCC

OVP

COMPARATOR

VID6

VCC

VID7 / D-VID

SGND

TO OCP

+.1240V

OCP

VID_SEL

VREF

GND DROP

RECOVERY

OUTEN

COMPARATOR

ERROR

LTB

PHASE_SEL

OVP

AMPLIFIER

5/64

Pin settings

L6713A

2

Pin settings

2.1

Pin connection

Figure 2. Pin connection (top view)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

TM

SGND

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

SS / LTBG / AMD

CS1-

N.C.

CS1+

N.C.

CS3-

N.C.

CS3+

PGND2

LGATE2

VCCDR2

VCCDR3

LGATE3

PGND3

PGND1

LGATE1

VCCDR1

PHASE1

N.C.

CS2-

CS2+

N.C.

L6713A

N.C.

COMP

FB

DROOP

VSEN

SGND

LTB

OUTEN

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

6/64

L6713A

Pin settings

2.2

Pin description

Table 1. Pin description

N°

Function

Channel 1 HS driver output.

A small series resistors helps in reducing device-dissipated power.

1

UGATE1

Channel 1 HS driver supply.

Connect through a capacitor (100nF typ.) to PHASE1 and provide necessary

Bootstrap diode.A small resistor in series to the boot diode helps in reducing

Boot capacitor overcharge.

2

BOOT1

N.C.

3

4

Not internally connected.

Channel 3 HS driver return path.

PHASE3 It must be connected to the HS3 MOSFET source and provides return path for

the HS driver of channel 3.

Channel 3 HS driver output.

UGATE3

5

6

A small series resistors helps in reducing device-dissipated power.

Channel 3 HS driver supply.

Connect through a capacitor (100nF typ.) to PHASE3 and provide necessary

Bootstrap diode.A small resistor in series to the boot diode helps in reducing

BOOT3

Boot capacitor overcharge.

7

8

N.C.

Not internally connected.

Channel 2 HS driver return path.

PHASE2 It must be connected to the HS2 MOSFET source and provides return path for

the HS driver of channel 2.Leave floating when using 2 Phase operation.

Channel 2 HS driver output.

9

UGATE2 A small series resistors helps in reducing device-dissipated power.

Leave floating when using 2 Phase operation.

Channel 2 HS driver supply.

Connect through a capacitor (100nF typ.) to PHASE2 and provide necessary

Bootstrap diode.A small resistor in series to the boot diode helps in reducing

10

BOOT2

Boot capacitor overcharge.Leave floating when using 2 Phase operation.

11

12

13

14

N.C.

Not internally connected.

Device Supply Voltage. The operative voltage is 12V 15%. Filter with 1µF (typ)

MLCC vs. SGND.

15

16

VCC

PHASE SELection Pin.Internally pulled up by 12.5µA(typ) to 5V.

It allows selecting between 2 Phase and 3 Phase operation.See Table 10 for

details.

PHASE_

SEL

OUTput ENable Pin.Internally pulled up by 12.5µA(typ) to 5V.

Forced low, the device stops operations with all MOSFETs OFF: all the

protections are disabled except for Preliminary over voltage.

Leave floating, the device starts-up implementing soft-start up to the selected

VID code.

17

OUTEN

Cycle this pin to recover latch from protections; filter with 1nF (typ) vs. SGND.

7/64

Pin settings

L6713A

Table 1. Pin description

N°

Function

Load Transient Boost Pin.

Internally fixed at 1V, connecting a R_LTB- C_LTBvs. VOUT allows to enable the

18

LTB

Load Transient Boost Technology™: as soon as the device detects a transient

load it turns on all the PHASEs at the same time. Short to SGND to disable the

function.

All the internal references are referred to this pin. Connect to the PCB Signal

Ground.

19

20

SGND

VSEN

It manages OVP and UVP protections and PGOOD (when applicable).

See “Output voltage monitor and protections” Section.

100µA constant current (I_OFFSET, See Table 4) is sunk by VSEN pin in order to

generate a positive offset in according to the R_OFFSETresistor between VSEN

pin and VOUT. See “Offset (Optional)” Section for details.

A current proportional to the total current read is sourced from this pin

according to the Current Reading Gain.

21

DROOP

Short to FB to implement Droop Function or Short to SGND to disable the

function.Connecting to SGND through a resistor and filtering with a capacitor,

the current info can be used for other purposes.

Error Amplifier Inverting Input. Connect with a resistor R_FBvs. VSEN and with

an R_F- C_Fvs. COMP.

22

23

FB

Error Amplifier Output. Connect with an R_F- C_Fvs. FB.

The device cannot be disabled by pulling down this pin.

COMP

24

25

N.C.

Not internally connected.

Channel 2 Current Sense Positive Input.

Connect through an R-C filter to the phase-side of the channel 2 inductor.

Short to SGND or to V_OUTwhen using 2 Phase operation.

See “Layout guidelines” Section for proper layout of this connection.

26

27

CS2+

CS2-

Channel 2 Current Sense Negative Input.

Connect through a Rg resistor to the output-side of the channel 2 inductor.

Leave floating when using 2 Phase operation.

See “Layout guidelines” Section for proper layout of this connection.

Channel 3 Current Sense Positive Input.

28

29

30

31

CS3+

CS3-

CS1+

CS1-

Connect through an R-C filter to the phase-side of the channel 3 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 3 Current Sense Negative Input.

Connect through a Rg resistor to the output-side of the channel 3 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 1 Current Sense Positive Input.

Connect through an R-C filter to the phase-side of the channel 1 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 1 Current Sense Negative Input.

Connect through a Rg resistor to the output-side of the channel 1 inductor.

See “Layout guidelines” Section for proper layout of this connection.

8/64

L6713A

Pin settings

Table 1. Pin description

N°

Function

Soft Start OSCillator, LTB Gain and AMD selection Pin.

It allows selecting between INTEL DACs and AMD DAC.

SS/ LTBG/ Short to SGND to select AMD DAC otherwise INTEL mode is selected.

32

AMD

When INTEL mode is selected trough this pin it is possible to select the Soft

Start Time and also the Gain of LTB Technology™. See “Soft start” Section”

and See “Load Transient Boost TechnologyTM” Section for details.

Over Voltage Programming Pin. Internally pulled up by 12.5µA(typ) to 5V.

Leave floating to use built-in protection thresholds as reported into Table 11.

Connect to SGND through a R_OVPresistor and filter with 100pF (max) to set the

OVP threshold to a fixed voltage according to the R_OVPresistor.

See “Over voltage and programmable OVP” Section Section for details.

33

34

OVP

Intel Mode.Internally pulled up by 12.5µA(typ) to 5V.

It allows selecting between VR10 (short to SGND, Table 7) or VR11 (floating,

See Table 6) DACs. See “Configuring the device” Section for details.

AMD Mode. Not Applicable. Needs to be shorted to SGND.

VID_SEL

Over Current SET Pin.

Connect to SGND through a R_OCSETresistor to set the OCP threshold.Connect

also a C_OCSETcapacitor to set a delay for the OCP intervention.

See “Over current protection” Section for details.

35

36

OCSET

FBG

Connect to the negative side of the load to perform remote sense.

See “Layout guidelines” Section for proper layout of this connection.

Oscillator Pin.

It allows programming the switching frequency F_SWof each channel: the

equivalent switching frequency at the load side results in being multiplied by the

phase number N.

OSC/

FAULT

37

Frequency is programmed according to the resistor connected from the pin vs.

SGND or VCC with a gain of 6kHz/µA (see relevant section for details). Leaving

the pin floating programs a switching frequency of 200kHz per phase.

The pin is forced high (5V) to signal an OVP FAULT: to recover from this

condition, cycle VCC or the OUTEN pin. See “Oscillator” Section for details.

VID7 - Intel Mode. See VID5 to VID0 Section.

DVID - AMD Mode. DVID Output.

38

39

VID7/DVID CMOS output pulled high when the controller is performing a D-VID transition

(with 32 clock cycle delay after the transition has finished). See “Dynamic VID

transitions” Section Section for details.

Intel Mode. See VID5 to VID0 Section.

VID6

AMD Mode. Not Applicable. Needs to be shorted to SGND.

9/64

Pin settings

L6713A

Table 1. Pin description

N°

Function

Intel Mode. Voltage IDentification Pins (also applies to VID6, VID7).

Internally pulled up by 25µA to 5V, connect to SGND to program a '0' or leave

floating to program a '1'.

They allow programming output voltage as specified in Table 6 and Table 7

according to VID_SEL status. OVP and UVP protection comes as a

consequence of the programmed code (See Table 11).

AMD Mode. Voltage IDentification Pins.

40 to

45

VID5 to

VID0

Internally pulled down by 12.5µA, leave floating to program a '0' while pull up to

more than 1.4V to program a '1'.

They allow programming the output voltage as specified in Table 9 (VID7

doesn’t care). OVP and UVP protection comes as a consequence of the

programmed code (See Table 11).

Note. VID6 not used, need to be shorted to SGND.

SSEND - Intel Mode. Soft Start END Signal.

Open Drain Output sets free after SS has finished and pulled low when

triggering any protection. Pull up to a voltage lower than 5V (typ), if not used it

SS_END/ can be left floating.

46

PGOOD

PGOOD - AMD Mode.

Open Drain Output set free after SS has finished and pulled low when VSEN is

lower than the relative threshold. Pull up to a voltage lower than 5V (typ), if not

used it can be left floating.

Voltage Regulator HOT. Over Temperature Alarm Signal.

Open Drain Output, set free when TM overcomes the Alarm Threshold.

Thermal Monitoring Output enabled if Vcc > UVLO_VCC.

47

48

VR_HOT

VR_FAN

See “Thermal monitor” Section for details and typical connections.

Voltage Regulator FAN. Over Temperature Warning Signal.

Open Drain Output, set free when TM overcomes the Warning Threshold.

Thermal Monitoring Output enabled if Vcc > UVLO_VCC.

See “Thermal monitor” Section for details and typical connections.

Thermal Monitor Input.

It senses the regulator temperature through apposite network and drives

VR_FAN and VR_HOT accordingly.Short TM pin to SGND if not used.

See “Thermal monitor” Section for details and typical connections.

49

50

TM

All the internal references are referred to this pin. Connect to the PCB Signal

Ground.

SGND

51

52

53

N.C.

Not internally connected.

Channel 2 LS Driver return path. Connect to Power ground Plane.

It must be connected to Power ground Plane also when using 2-Phase

Operation.

54

55

PGND2

LGATE2

Channel 2 LS Driver Output.A small series resistor helps in reducing device-

dissipated power.

Leave floating when using 2 Phase operation.

10/64

L6713A

Pin settings

Table 1. Pin description

N°

Function

Channel 2 LS Driver Supply.

It must be connected to others VCCDRx pins also when using 2-Phase

VCCDR2 Operation.

LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap

56

vs. PGND2.

Channel 3 LS Driver Supply.

It must be connected to others VCCDRx pins.

LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap

vs. PGND3.

57

58

VCCDR3

LGATE3

Channel 3 LS Driver Output.A small series resistor helps in reducing device-

dissipated power.

59

60

PGND3

PGND1

Channel 3 LS Driver return path. Connect to Power ground Plane.

Channel 1 LS Driver return path. Connect to Power ground Plane.

Channel 1 LS Driver Output.A small series resistor helps in reducing device-

dissipated power.

61

LGATE1

Channel 1 LS Driver Supply.

It must be connected to others VCCDRx pins.

LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap

vs. PGND1.

62

VCCDR1

Channel 1 HS driver return path.

63

64

PHASE1 It must be connected to the HS1 MOSFET source and provides return path for

the HS driver of channel 1.

N.C.

Not internally connected.

Thermal pad connects the Silicon substrate and makes good thermal contact

with the PCB to dissipate the power necessary to drive the external MOSFETs.

Connect to the PGND plane with several VIAs to improve thermal conductivity.

THERMAL

PAD

11/64

Electrical data

L6713A

3

Electrical data

3.1

Maximum ratings

Table 2. Absolute maximum ratings

Symbol

Parameter

Value

Unit

V

V_CC, V_CCDRx

to PGNDx

15

V

_BOOTx- V_PHASExBoot voltage

V_UGATEx- V_PHASEx

V_CC- V_BOOTx

15

V

7.5

V

LGATEx, PHASEx, to PGNDx

VID0 to VID7, VID_SEL

All other Pins to PGNDx

-0.3 to V_CC+ 0.3

-0.3 to 5

-0.3 to 7

V

Static condition to PGNDx,

VCC = 14V, BOOTx = 7V,

PHASEx = -7.5V

-7.5

26

V

V_PHASEx

Positive peak voltage to PGNDx;

T < 20ns @ 600kHz

3.2

Thermal data

Table 3. Thermal data

Symbol

Parameter

Value

Unit

Thermal resistance junction to ambient

(Device soldered on 2s2p PC Board)

R_thJA

40

°C/W

T_MAX

T_STG

T_J

Maximum junction temperature

Storage temperature range

150

-40 to 150

0 to 125

2.5

°C

W

Junction temperature range

Maximum power dissipation at T_A= 25°C

P_TOT

12/64

L6713A

Electrical characteristics

4

Electrical characteristics

V

= 12V 15%, T = 0°C to 70°C, unless otherwise specified

J

CC

Table 4. Electrical characteristics

Symbol

Parameter

Test condition

Min.

Typ. Max.

Unit

Supply current

HGATEx and LGATEx = OPEN

VCCDRx = BOOTx = 12V

I_CC

VCC supply current

17

1

mA

I_CCDRx

I_BOOTx

VCCDRx supply current

BOOTx supply current

LGATEx = OPEN; VCCDRx = 12V

HGATEx = OPEN; PHASEx to

PGNDx VCC = BOOTx = 12V

0.75

Power-ON

VCC Turn-ON

VCC Rising; VCCDRx = 5V

VCC Falling; VCCDRx = 5V

VCCDRx Rising; VCC = 12V

VCCDRx Falling; VCC = 12V

VCC Rising; VCCDRx = 5V

VCC Falling; VCCDRx = 5V

8.9

7.7

4.5

4.3

3.6

3.3

9.3

4.8

V

UVLO_VCC

VCC Turn-OFF

7.3

4

VCCDR Turn-ON

VCCDR Turn-OFF

Pre-OVP Turn-ON

Pre-OVP Turn-OFF

UVLO_VCCDR

UVLO_OVP

3.85

3.05

Oscillator and inhibit

180

175

200

500

220

225

OSC = OPEN

OSC = OPEN; T_J= 0°C to 125°C

F_OSC

Main oscillator accuracy

kHz

T₁

T₂

T₃

SS delay time

SS Time T₂

Intel mode

1

ms

Intel mode; R_SSOSC= 25kΩ

µs

SS Time T₃

Intel mode

50

µs

V

Rising thresholds voltage

Hysteresis

0.80

0.85

100

0.90

0.80

Output enable intel mode

mV

V

OUTEN

Input low

Output enable AMD mode

Input high

1.40

V

OUTEN Pull-up current

PWMx Ramp amplitude

Voltage at Pin OSC

OUTEN to SGND

12.5

3

µA

V

∆V_OSC

FAULT

OVP Active

5

V

13/64

Electrical characteristics

L6713A

Unit

Table 4. Electrical characteristics

Symbol

Parameter

Test condition

Min.

Typ. Max.

Reference and DAC

Intel mode

VID=1.000V to VID=1.600V

FB = VOUT; FBG = GNDOUT

-0.5

-0.6

-

0.5

0.6

%

k_VID

Output voltage accuracy

AMD mode

VID=1.000V to VID=1.550V

FB = VOUT; FBG = GNDOUT

V_BOOT

I_VID

Boot voltage

Intel mode

1.081

25

V

VID Pull-up current

VID Pull-down current

Intel mode; VIDx to SGND

AMD mode; VIDx to 5.4V

µA

12.5

0.3

0.8

Intel mode; Input low

AMD mode; Input low

VID_IL

VID_IH

V

VID Thresholds

0.8

Intel mode; Input high

AMD mode; Input high

1.35

0.3

VID_SEL Threshold

(Intel Mode)

Input low

Input high

V

0.8

VID_SEL

VID_SEL Pull-up current

VIDSEL to SGND

12.5

µA

Error amplifier

A₀

EA DC gain

EA Slew rate

80

20

dB

SR

COMP = 10pF to SGND

V/µs

Differential current sensing and offset

I_CSx+

Bias current

Inductor sense

0

-

µA

%

V

I

– I

INFOx AVG

-----------------------------------------

Rg = 1kΩ; I_INFOx=25µA

Current sense mismatch

Over current threshold

-3

3

I

AVG

V_OCSET(OCP)

V_OCTH

1.230 1.240 1.250

Rg = 1kΩ

2-PHASE, I_OCSET= 80µA;

K_IOCSET

OCSET current accuracy

-15

-

15

%

3-PHASE, I_OCSET= 120µA;

Rg = 1kΩ

Droop current deviation from

nominal value

2-PHASE, I_DROOP= 0 to 40µA;

k_IDROOP

-1

-

1

µA

3-PHASE, I_DROOP= 0 to 60µA;

I_OFFSET

Offset current

VSEN = 0.500V to 1.600V

90

100

110

Gate driver

BOOTx - PHASEx = 10V;

C_UGATExto PHASEx = 3.3nF

t_{RISE_UGATEx}HS Rise time

15

30

ns

I_UGATEx

HS Source current

HS Sink resistance

BOOTx - PHASEx = 10V

BOOTx - PHASEx = 12V

2

A

R_UGATEx

1.5

2.5

Ω

14/64

L6713A

Electrical characteristics

Table 4. Electrical characteristics

Symbol

Parameter

Test condition

VCCDRx = 10V;

Min.

Typ. Max.

Unit

t_{RISE_LGATEx}LS Rise time

30

55

ns

C_LGATExto PGNDx = 5.6nF

I_LGATEx

LS Source current

VCCDRx = 10V

VCCDRx = 12V

1.8

1.1

A

R_LGATEx

LS Sink resistance

0.7

1.5

Ω

Protections

Intel mode; Before V_BOOT

1.300

200

V

mV

V

Over voltage protection

(VSEN rising)

OVP

Intel mode; Above VID

AMD mode

150

175

1.750 1.800 1.850

I

_OVPcurrent

OVP = SGND

OVP = 1.8V

11.5

-20

12.5

0

13.5

20

µA

mV

Program-

mable OVP

Comparator offset voltage

UVLO_OVP< VCC < UVLO_VCC

VCC> UVLO_VCC& OUTEN = SGND

1.800

V

Preliminary over voltage

protection

Pre-OVP

Hysteresis

350

-750

-300

mV

UVP

Under voltage protection

PGOOD Threshold

VSEN Falling; Below VID

AMD Mode;

VSEN Falling; Below VID

PGOOD

mV

V

V_SSEND/

SSEND / PGOOD

voltage low

I = -4mA

0.4

PGOOD

Thermal monitor

TM Warning (VR_FAN)

V_TMRising

3.2

3.6

V

V_TM

V_TMRising

TM Alarm (VR_HOT)

TM Hysteresis

100

mV

0.4

V

V_{VR_HOT}

V_{VR_FAN}

;

VR_HOT Voltage low;

VR_FAN Voltage low

I = -4mA

15/64

VID Tables

L6713A

5

VID Tables

5.1

Mapping for the Intel VR11 Mode

Table 5. Voltage identification (VID) Mapping for Intel VR11 Mode

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

800mV

400mV

200mV

100mV

50mV

25mV

12.5mV

6.25mV

5.2

Voltage identification (VID) for Intel VR11 Mode

Table 6. Voltage identification (VID) for Intel VR11 Mode (See Note).

Output Output Output

Output

HEX Code Voltage HEX Code Voltage HEX Code Voltage HEX Code Voltage

(1)

(

1)

(

1)

(1)

0

1

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

OFF

4

5

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

1.08750

1.08125

1.07500

8

9

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

0.75000

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

C

D

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

0.41250

0.40625

0.40000

0.39375

0.38750

0.38125

0.37500

0.36875

0.36250

0.35625

0.35000

0.34375

0.33750

0.33125

0.32500

0.31875

0.31250

0.30625

0.30000

0.29375

0.28750

0.28125

0.27500

OFF

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

16/64

L6713A

VID Tables

Table 6. Voltage identification (VID) for Intel VR11 Mode (See Note). (continued)

Output Output Output Output

HEX Code Voltage HEX Code Voltage HEX Code Voltage HEX Code Voltage

(1)

(

1)

(

1)

(1)

1

2

3

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

9

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

0.66875

0.66250

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

0.57500

0.56875

0.56250

0.55625

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

0.49375

0.48750

0.48125

0.47500

0.46875

D

E

F

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

0.26875

0.26250

0.25625

0.25000

0.24375

0.23750

0.23125

0.22500

0.21875

0.21250

0.20625

0.20000

0.19375

0.18750

0.18125

0.17500

0.16875

0.16250

0.15625

0.15000

0.14375

0.13750

0.13125

0.12500

0.11875

0.11250

0.10625

0.10000

0.09375

0.08750

0.08125

0.07500

0.06875

9

A

B

17/64

VID Tables

L6713A

Table 6. Voltage identification (VID) for Intel VR11 Mode (See Note). (continued)

Output Output Output Output

HEX Code Voltage HEX Code Voltage HEX Code Voltage HEX Code Voltage

(1)

(

1)

(

1)

(1)

3

8

9

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

7

8

9

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

B

8

9

0.46250

0.45625

0.45000

0.44375

0.43750

0.43125

0.42500

0.41875

F

8

9

0.06250

0.05625

0.05000

0.04375

0.03750

0.03125

OFF

A

B

C

D

E

F

A

B

C

D

E

F

A

B

C

D

E

F

A

B

C

D

E

F

OFF

1. According to VR11 specs, the device automatically regulates output voltage 19mV lower to avoid any

external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage

is than what extracted from the table lowered by 19mV built-in offset.

5.3

Voltage identifications (VID) for Intel VR10 Mode + 6.25mV

(VID7 does not care)

Table 7. Voltage identifications (VID) for Intel VR10 Mode + 6.25mV (See Note).

Output

VID VID VID VID VID VID VID

Voltage

4

3

2

1

0

5

6

4

3

2

1

0

5

6

(1)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

18/64

L6713A

VID Tables

Table 7. Voltage identifications (VID) for Intel VR10 Mode + 6.25mV (See Note).

Output

VID VID VID VID VID VID VID

Voltage

4

3

2

1

0

5

6

4

3

2

1

0

5

6

(1)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.10000

1.09375

OFF

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

19/64

VID Tables

L6713A

Output

Table 7. Voltage identifications (VID) for Intel VR10 Mode + 6.25mV (See Note).

Output

VID VID VID VID VID VID VID

Voltage

4

3

2

1

0

5

6

4

3

2

1

0

5

6

(1)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

1. According to VR10.x specs, the device automatically regulates output voltage 19mV lower to avoid any

external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage

is than what extracted from the table lowered by 19mVbuilt-in offset. VID7 doesn’t care.

5.4

5.5

Mapping for the AMD 6BIT Mode

Table 8. Voltage identifications (VID) mapping for AMD 6BIT Mode

VID4

VID3

VID2

VID1

VID0

400mV

200mV

100mV

50mV

25mV

Voltage identifications (VID) codes for AMD 6BIT Mode

Table 9. Voltage identifications (VID) codes for AMD 6BIT Mode (See Note).

Output

Voltage

VID VID VID VID VID VID

Voltage

5

4

3

2

1

0

5

4

3

2

1

0

(1)

0

1

0

1

0

1

1.5500

1.5250

1.5000

1.4750

1

0

1

0

1

0

1

0.7625

0.7500

0.7375

0.7250

20/64

L6713A

VID Tables

Table 9. Voltage identifications (VID) codes for AMD 6BIT Mode (See Note). (continued)

Output

Voltage

VID VID VID VID VID VID

Voltage

5

4

3

2

1

0

5

4

3

2

1

0

(1)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.4500

1.4250

1.4000

1.3750

1.3500

1.3250

1.3000

1.2750

1.2500

1.2250

1.2000

1.1750

1.1500

1.1250

1.1000

1.0750

1.0500

1.0250

1.0000

0.9750

0.9500

0.9250

0.9000

0.8750

0.8500

0.8250

0.8000

0.7750

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

1. VID6 Not Applicable, need to be left unconnected.

21/64

Reference Schematic

L6713A

6

Reference Schematic

Figure 3. Reference Schematic - Intel VR10.x, VR11 - 3-Phase Operation

VIN

LIN

to BOOT1

to BOOT2

to BOOT3

GNDIN

62

56

2

CIN

VIN

VCCDR1

VCCDR2

BOOT1

UGATE1

PHASE1

LGATE1

1

HS1

57

VCCDR3

63,64

61

L1

C

R

15

LS1

VCC

60

31

30

PGND1

CS1-

19,50

33

SGND

OVP

Rg

CS1+

10

9

VIN

16

35

BOOT2

UGATE2

PHASE2

LGATE2

PHASE_SEL

OCSET

HS2

7,8

55

L2

C

37

32

OSC/FAULT

R

to SSEND

LS2

SS/LTBG/AMD

RSSOSC

54

27

26

PGND2

CS2-

VID7 / DVID

VID6

39

40

41

42

43

44

45

Rg

VID5

CS2+

VID4

VID3

Vcc_core

VID2

6

COUT

VIN

BOOT3

UGATE3

PHASE3

LGATE3

LOAD

GND_core

VID1

VID0

5

HS3

34

17

VID_SEL

OUTEN

VID_SEL

OUTEN

3,4

58

L3

R

LS3

18

23

59

29

28

LTB

PGND3

CS3-

C

Rg

CLTB

RLTB

COMP

CS3+

CF

RF

CP

46

47

SS_END

SS_END / PGOOD

VR_HOT

22

21

FB

DROOP

VR_FAN 48

+5V

CI

RI

NTC

RFB

49

TM

20

VSEN

FBG

RTM

ROFFSET

36

L6713A REF.SCH:

Intel Mode - 3-Phase Operation

22/64

L6713A

Reference Schematic

Figure 4. Reference Schematic - Intel VR10.x, VR11 - 2-Phase Operation

VIN

LIN

to BOOT1

to BOOT3

GNDIN

62

56

2

CIN

VIN

VCCDR1

VCCDR2

BOOT1

UGATE1

PHASE1

LGATE1

1

HS1

57

VCCDR3

63,64

61

L1

C

R

15

LS1

VCC

60

31

30

PGND1

CS1-

19,50

33

SGND

OVP

Rg

CS1+

10

9

16

35

BOOT2

UGATE2

PHASE2

LGATE2

PHASE_SEL

OCSET

7,8

55

37

32

OSC/FAULT

to SSEND

SS/LTBG/AMD

R^SSOSC

54

27

PGND2

CS2-

VID7 / DVID

VID6

39

40

41

42

43

44

45

VID5

26 Short to SGND (or to VOUT)

CS2+

VID4

VID3

Vcc_core

VID2

6

COUT

VIN

BOOT3

UGATE3

PHASE3

LGATE3

LOAD

VID1

GND_core

VID0

5

HS3

34

17

VID_SEL

OUTEN

VID_SEL

OUTEN

3,4

L3

C

58

R

LS3

18

23

59

LTB

PGND3

CS3-

29

28

Rg

CLTB

RLTB

COMP

CS3+

CF

RF

CP

46

47

SS_END

SS_END / PGOOD

VR_HOT

22

21

FB

DROOP

VR_FAN 48

+5V

CI

RI

RFB

NTC

49

TM

20

VSEN

FBG

RTM

ROFFSET

36

L6713A REF.SCH:

Intel Mode -2-Phase Operation

23/64

Reference Schematic

Figure 5. Reference Schematic - AMD 6BIT - 3-Phase Operation

L6713A

VIN

LIN

to BOOT1

to BOOT2

to BOOT3

GNDIN

62

56

2

CIN

VIN

VCCDR1

VCCDR2

BOOT1

UGATE1

PHASE1

LGATE1

1

HS1

57

VCCDR3

63,64

61

L1

C

R

15

LS1

VCC

60

31

30

PGND1

CS1-

19,50

33

SGND

OVP

Rg

CS1+

10

9

VIN

16

35

BOOT2

UGATE2

PHASE2

LGATE2

PHASE_SEL

OCSET

HS2

37

32

7,8

55

L2

C

OSC/FAULT

SS/LTBG/AMD

R

LS2

54

27

26

38

39

40

41

42

43

44

45

PGND2

CS2-

VID7 / DVID

VID6

Rg

VID5

CS2+

VID4

VID3

Vcc_core

VID2

6

COUT

VIN

BOOT3

UGATE3

PHASE3

LGATE3

LOAD

GND_core

VID1

VID0

5

HS3

34

17

VID_SEL

OUTEN

3,4

58

L3

OUTEN

R

LS3

18

23

59

29

28

LTB

PGND3

CS3-

C

Rg

CLTB

RLTB

COMP

CS3+

CF

RF

CP

46

47

PGOOD

SS_END / PGOOD

VR_HOT

22

21

FB

DROOP

VR_FAN 48

+5V

CI

RI

RFB

NTC

49

TM

20

VSEN

FBG

RTM

ROFFSET

36

L6713A REF.SCH:

AMD Mode - 3-Phase Operation

24/64

L6713A

Reference Schematic

Figure 6. Reference Schematic - AMD 6BIT - 2-Phase Operation

VIN

LIN

to BOOT1

to BOOT3

GNDIN

62

56

2

CIN

VIN

VCCDR1

VCCDR2

BOOT1

UGATE1

PHASE1

LGATE1

1

HS1

57

VCCDR3

63,64

61

L1

C

R

15

LS1

VCC

60

31

30

PGND1

CS1-

19,50

33

SGND

OVP

Rg

CS1+

10

9

16

35

BOOT2

UGATE2

PHASE2

LGATE2

PHASE_SEL

OCSET

37

32

7,8

55

OSC/FAULT

SS/LTBG/AMD

54

27

38

39

40

41

42

43

44

45

PGND2

CS2-

VID7 / DVID

VID6

VID5

26 Short to SGND (or to VOUT)

CS2+

VID4

VID3

Vcc_core

VID2

6

COUT

VIN

BOOT3

UGATE3

PHASE3

LGATE3

LOAD

VID1

GND_core

VID0

5

HS3

34

17

VID_SEL

OUTEN

3,4

L3

OUTEN

58

R

LS3

18

23

59

LTB

PGND3

CS3-

C

29

28

Rg

CLTB

RLTB

COMP

CS3+

CF

RF

CP

46

47

PGOOD

SS_END / PGOOD

VR_HOT

22

21

FB

DROOP

VR_FAN 48

+5V

CI

RI

NTC

RFB

49

TM

20

VSEN

FBG

RTM

ROFFSET

36

L6713A REF.SCH:

AMD Mode - 2-Phase Operation

25/64

Device description

L6713A

7

Device description

L6713A is two/three phase PWM controller with embedded high current drivers providing

complete control logic and protections for a high performance step-down DC-DC voltage

regulator optimized for advanced microprocessor power supply.

Multi phase buck is the simplest and most cost-effective topology employable to satisfy the

increasing current demand of newer microprocessors and modern high current VRM

modules.

It allows distributing equally load and power between the phases using smaller, cheaper and

most common external power MOSFETs and inductors. Moreover, thanks to the equal

phase shift between each phase, the input and output capacitor count results in being

reduced. Phase interleaving causes in fact input rms current and output ripple voltage

reduction and show an effective output switching frequency increase: the 200kHz free-

running frequency per phase, externally adjustable through a resistor, results multiplied on

the output by the number of phases.

L6713A is a dual-edge asynchronous PWM controller featuring Load Transient Boost (LTB)

Technology™ (Patent Pending): the device turns on simultaneously all the phases as soon

as a load transient is detected allowing to minimize system cost by providing the fastest

response to load transition.

Load transition is detected (through LTB pin) measuring the derivate dV/dt of the output

voltage and the dV/dt can be easily programmed extending the system design flexibility.

Moreover, Load Transient Boost(LTB) Technology™ Gain can be easily modified in order to

keep under control the output voltage ring back.

LTB Technology™ can be disabled and in this condition the device works as a dual-edge

asynchronous PWM.

The controller allows to implement a scalable design: a three phase design can be easily

downgraded to two phase simply by leaving one phase not mounted and leaving

PHASE_SEL pin floating.

The same design can be used for more than one project saving development and debug

time. In the same manner, a two phase design can be further upgraded to three phase

facing with newer and highly-current-demanding applications.

L6713A permits easy system design by allowing current reading across inductor in fully

differential mode. Also a sense resistor in series to the inductor can be considered to

improve reading precision.

The current information read corrects the PWM output in order to equalize the average

current carried by each phase limiting the error to 3% over static and dynamic conditions

unless considering the sensing element spread.

The controller includes multiple DACs, selectable through an apposite pin, allowing

compatibility with both Intel VR10,VR11 and AMD 6BIT processors specifications, also

performing D-VID transitions accordingly.

Low-Side-Less start-up allows soft start over pre-biased output avoiding dangerous current

return through the main inductors as well as negative spike at the load side.

26/64

L6713A

Device description

L6713A provides a programmable Over-Voltage protection to protect the load from

dangerous over stress. It can be externally set to a fixed voltage through an apposite

resistor, or it can be set internally, latching immediately by turning ON the lower driver and

driving high the FAULT pin.

Furthermore, preliminary OVP protection also allows the device to protect load from

dangerous OVP when VCC is not above the UVLO threshold.

The Over-Current protection is on the total delivered current and causes the device turns

OFF all MOSFETs and latches the condition.

L6713A provides also system Thermal Monitoring: through an apposite pin the device

senses the temperature of the hottest component in the application driving the Warning and

the Alarm signal as a consequence.

A compact 10 x 10mm body TQFP64 package with exposed thermal pad allows dissipating

the power to drive the external MOSFET through the system board.

27/64

Configuring the device

L6713A

8

Configuring the device

Number of Phases and Multiple DACs need to be configured before the system starts-up by

programming the apposite pin PHASE_SEL and SS/LTBG/AMD pin.

The configuration of this pin identifies two main working areas (See Table 11) distinguishing

between compliancy with Intel VR10,VR11 or AMD 6BIT specifications. According to the

main specification considered, further customizazions can be done: main differences are

regarding the DAC table, soft-start implementation, protection management and Dynamic

VID Transitions. See Table 12 and See Table 13 for further details about the device

configuration.

8.1

Number of phases selection

L6713A allows to select between two and three phase operation simply using the

PHASE_SEL pin, as shown in the following table.

Table 10. Number of phases setting.

PHASE_SEL pin

Floating

Number of phases

2-PHASE

Phases used

Phase1, Phase3

Short to SGND

3-PHASE

Phase1, Phase2, Phase3

8.2

DAC Selection

L6713A embeds a selectable DAC (through SS/LTBG/AMD pin, See Table 11) that allows to

regulate the output voltage with a tolerance of 0.5% ( 0.6% for AMD DAC) recovering from

offsets and manufacturing variations. In case of selecting Intel Mode, the device

automatically introduces a -19mV (both VRD10.x and VR11) offset to the regulated voltage

in order to avoid any external offset circuitry to worsen the guaranteed accuracy and, as a

consequence, the calculated system TOB.

Table 11. DAC Settings (See Note).

SS / LTBG / AMD

Resistor(R_SSOSC

)

DAC

Soft start time

LTB™Gain

OVP

UVP

vs. SGND

1.800V (typ)

Fixed

Not

or

-750mV

(typ)

0 (Short)

AMD

Programmable

(LTB™Gain=2)

VID + 175mV

(typ)

Programmable

trough R_SSOSC

Programmable

trough R_SSOSC

-750mV

(typ)

> 2.4 kΩ

Intel

or

(LTB™Gain≤2)

Programmable

Note:

When selecting Intel Mode, SS/LTBG/AMD pin is used to select both Soft Start Time and

LTB™ Gain (see dedicated sections).

28/64

L6713A

Configuring the device

Output voltage is programmed through the VID pins: they are inputs of an internal DAC that

is realized by means of a series of resistors providing a partition of the internal voltage

reference. The VID code drives a multiplexer that selects a voltage on a precise point of the

divider. The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the

set-point of the error amplifier, V_REF).

Table 12. Intel Mode Configuration (See Note).

1)

Function ⁽

Typical Connection

It allows programming the soft-start time T_SS

R_SSOSCResistor in series to

SS / LTBG /

and also the LTB Technology™ Gain. See “Soft Signal Diode vs. SSEND pin.

AMD

start” Section and See “Load Transient Boost

TechnologyTM” Section for details.

(LTB™Gain = 2, default value).

It allows selecting between VR11 DAC or

VR10.x + 6.25mV extended DAC.

Static info, no dynamic changes allowed.

Open: VR11 (Table 6 ).

Short to SGND: VR10.x

(Table 7 ).

VID_SEL

They allow programming the Output Voltage

according to Table 6 and Table 7.

Dynamic transitions managed, See “Dynamic

VID transitions” Section for details.

Open: Logic “1” (25µA pull-up)

Short to SGND: “0”

VID7 to VID0

SSEND /

PGOOD

Soft Start end signal set free after soft-start has Pull-up to anything lower than

finished. It only indicates soft-start has finished. 5V.

Note:

VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes

according to the selected DAC: See Table 4 for details.

Table 13. AMD Mode Configuration (See Note).

Function

It allows programming AMD 6 BIT DAC.

Not Applicable

Typical Connection

Short to SGND.

SS / LTBG /

AMD

VID_SEL

VID7 / DVID

VID6

Need to be shorted to SGND.

Not Applicable

Pulled high when performing a D-VID transition.

The pin is kept high with a 32 clock cycles delay.

Not Applicable

Need to be shorted to SGND.

They allow programming the Output Voltage

according to Table 9.

Open: “0” (12.5µA pull-down)

VID5 to VID0

Dynamic transitions managed, See “Dynamic

VID transitions” Section for details.

Pull-up to V > 1.4V: “1”

Power Good signal set free after soft-start has

finished whenever the output voltage is within

limits.

SSEND /

PGOOD

Pull-up to anything lower than

5V.

Note:

VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes

according to the selected DAC: See Table 4 for details.

29/64

Power dissipation

L6713A

9

Power dissipation

L6713A embeds high current MOSFET drivers for both high side and low side MOSFETs: it

is then important to consider the power the device is going to dissipate in driving them in

order to avoid overcoming the maximum junction operative temperature. In addition, since

the device has an exposed pad to better dissipate the power, the thermal resistance

between junction and ambient consequent to the layout is also important: thermal pad

needs to be soldered to the PCB ground plane through several VIAs in order to facilitate the

heat dissipation.

Two main terms contribute in the device power dissipation: bias power and drivers' power.

The first one (P_DC) depends on the static consumption of the device through the supply pins

and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same

VCC of the device):

P_DC= V_CC⋅ (I_CC+ N ⋅ I_CCDRx+ N ⋅ I_BOOTx

)

where N is the number of phases.

Drivers' power is the power needed by the driver to continuously switch on and off the

external MOSFETs; it is a function of the switching frequency and total gate charge of the

selected MOSFETs. It can be quantified considering that the total power P_SWdissipated to

switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate

resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This

last term is the important one to be determined to calculate the device power dissipation.

The total power dissipated to switch the MOSFETs results:

P_SW= N ⋅ F_SW⋅ (Q_GHS⋅ V_BOOT+ Q_GLS⋅ V_CCDRx

)

External gate resistors helps the device to dissipate the switching power since the same

power P_SWwill be shared between the internal driver impedance and the external resistor

resulting in a general cooling of the device. When driving multiple MOSFETs in parallel, it is

suggested to use one gate resistor for each MOSFET.

30/64

L6713A

Power dissipation

Figure 7. L6713A Dissipated power (quiescent + switching).

2-PHASE Operation; Rgate=0; Rmosfet=0

2-PHASE Operation; Rhs=2.2; Rls=3.3; Rmosfet=1

4500

4000

HS=1xSTD38NH02L; LS=1xSTD90NH02L

HS=2xSTD38NH02L; LS=2xSTD90NH02L

HS=1xSTD55NH2LL; LS=1xSTD95NH02L

HS=2xSTD55NH2LL; LS=2xSTD95NH02L

HS=3xSTD55NH22L; LS=3xSTD95NH02L

HS=1xSTD38NH02L; LS=1xSTD90NH02L

HS=2xSTD38NH02L; LS=2xSTD90NH02L

HS=1xSTD55NH2LL; LS=1xSTD95NH02L

HS=2xSTD55NH2LL; LS=2xSTD95NH02L

HS=3xSTD55NH22L; LS=3xSTD95NH02L

4000

3500

3000

2500

2000

1500

1000

500

3500

3000

2500

2000

1500

1000

500

0

50

150

250

350

450

550

650

750

850

950

1050

50

150

250

350

450

550

650

750

850

950

1050

Switching frequency[kHz] per phase

3-PHASE Operation; Rgate=0; Rmosfet=0

3-PHASE Operation; Rhs=2.2; Rls=3.3; Rmosfet=1

4000

3500

3000

2500

2000

1500

1000

500

7000

6000

5000

4000

3000

2000

1000

0

HS=1xSTD38NH02L; LS=1xSTD90NH02L

HS=2xSTD38NH02L; LS=2xSTD90NH02L

HS=1xSTD55NH2LL; LS=1xSTD95NH02L

HS=2xSTD55NH2LL; LS=2xSTD95NH02L

HS=3xSTD55NH22L; LS=3xSTD95NH02L

HS=1xSTD38NH02L; LS=1xSTD90NH02L

HS=2xSTD38NH02L; LS=2xSTD90NH02L

HS=1xSTD55NH2LL; LS=1xSTD95NH02L

HS=2xSTD55NH2LL; LS=2xSTD95NH02L

HS=3xSTD55NH22L; LS=3xSTD95NH02L

0

50

150

250

350

450

550

650

750

850

950

1050

50

150

250

350

450

550

650

750

850

950

1050

Switching frequency [kHz] per phase

31/64

Current reading and current sharing loop

L6713A

10

Current reading and current sharing loop

L6713A embeds a flexible, fully-differential current sense circuitry that is able to read across

inductor parasitic resistance or across a sense resistor placed in series to the inductor

element. The fully-differential current reading rejects noise and allows placing sensing

element in different locations without affecting the measurement's accuracy.

Reading current across the inductor DCR, the current flowing trough each phase is read

using the voltage drop across the output inductor or across a sense resistor in its series and

internally converted into a current. The trans-conductance ratio is issued by the external

resistor Rg placed outside the chip between CSx- pin toward the reading points.

The current sense circuit always tracks the current information, no bias current is sourced

from the CSx+ pin: this pin is used as a reference keeping the CSx- pin to this voltage. To

correctly reproduce the inductor current an R-C filtering network must be introduced in

parallel to the sensing element.

The current that flows from the CSx- pin is then given by the following equation (See

Figure 8):

DCR 1 + s ⋅ L ⁄ (DCR)

------------- ------------------------------------------------

⋅ I

PHASEx

I_CSx-

=

⋅

Rg

1 + s ⋅ R ⋅ C

Where I_PHASExis the current carried by the relative phase.

Figure 8. Current reading connections.

I_PHASEx

Lx DCR_x

PHASEx

CSx+

R

C

NO Bias

I_CSx-=I_INFOx

CSx-

Rg

Inductor DCR Current Sense

Considering now to match the time constant between the inductor and the R-C filter applied

(Time constant mismatches cause the introduction of poles into the current reading network

causing instability. In addition, it is also important for the load transient response and to let

the system show resistive equivalent output impedance), it results:

DCR

Rg

DCR

Rg

L

-------------

⋅ I_PHASEx

------------- = R ⋅ C

⇒

I_CSx-

=

⋅ I_PHASEx= I_INFOx

⇒

I_INFOX

=

DCR

Where I_INFOxis the current information reproduced internally.

32/64

L6713A

Current reading and current sharing loop

The Rg trans-conductance resistor has to be selected using the following formula, in order

to guarantee the correct funcionality of internal current reading circuitry:

I

(MAX)

N

DCR(MAX)

-------------------------------- --^O----^U----^T--------------------

Rg =

⋅

20µA

Current sharing control loop reported in Figure 9: it considers a current I_INFOxproportional to

the current delivered by each phase and the average current_AVG= ΣI_INFOx⁄ N. The error

between the read current I_INFOxand the reference I_AVGis then converted into a voltage that

with a proper gain is used to adjust the duty cycle whose dominant value is set by the

voltage error amplifier in order to equalize the current carried by each phase. Details about

connections are shown in Figure 8.

Figure 9. Current sharing loop.

I_INFO1

PWM1 Out

I_AVG

I_INFO2

AVG

PWM2 Out

From EA

I_INFO3

PWM3 Out

(PHASE2 Only when using 3-PHASE Operation)

33/64

Differential remote voltage sensing

L6713A

11

Differential remote voltage sensing

The output voltage is sensed in fully-differential mode between the FB and FBG pin. The FB

pin has to be connected through a resistor to the regulation point while the FBG pin has to

be connected directly to the remote sense ground point.

In this way, the output voltage programmed is regulated between the remote sense point

compensating motherboard or connector losses.

Keeping the FB and FBG traces parallel and guarded by a power plane results in common

mode coupling for any picked-up noise.

Figure 10. Differential remote voltage sensing connections

V_PROG

ERROR AMPLIFIER

V_REF

GND DROP

RECOVERY

I_OFFSET

I_DROOP

FBG

VSEN

DROOP

FB

COMP

R_OFFSET

R_FB

R_F

C_F

To GND_core

(Remote Sense)

To VCC_core

(Remote Sense)

C_P

34/64

L6713A

Voltage positioning

12

Voltage positioning

Output voltage positioning is performed by selecting the reference DAC and by

programming the Droop Function and Offset to the reference (See Figure 11). The currents

sourced from DROOP and sunk from VSEN pins cause the output voltage to vary according

to the external R_FBand R_OFFSETresistor.

The output voltage is then driven by the following relationship:

V_OUT= V_REF– (R_FB+ R_OFFSET) ⋅ (I_DROOP) + (R_OFFSET) ⋅ (I_OFFSET

)

⎧

⎨

⎩

VID – 19mV VR10 - VR11

VID AMD 6BIT

V_REF

=

DROOP function can be disabled as well as the OFFSET: connecting DROOP pin and FB

pin together implements the load regulation dependence while, if this effect is not desired,

by shorting DROOP pin to SGND it is possible for the device to operate as a classic Voltage

Mode Buck converter. The DROOP pin can also be connected to SGND through a resistor

obtaining a voltage proportional to the delivered current usable for monitoring purposes.

OFFSET can be disabled by using R_OFFSETequal to zero.

Figure 11. Voltage positioning (left) and droop function (right)

V_PROG

ERROR AMPLIFIER

V_REF

ESR Drop

GND DROP

RECOVERY

V

MAX

I_OFFSET

I_DROOP

NOM

V

MIN

FBG

VSEN

DROOP

FB

COMP

RESPONSE WITHOUT DROOP

RESPONSE WITH DROOP

R_OFFSET

R_FB

R_F

C_F

To GND_core

(Remote Sense)

To VCC_core

(Remote Sense)

C_P

12.1

Offset (Optional)

The I_OFFSETcurrent (See Table 4) sunk from the VSEN pin allows programming a positive

offset (V_OS) for the output voltage by connecting a resistor R_OFFSETbetween VSEN pin and

VOUT, as shown in the Figure 11; this offset has to be considered in addition to the one

already introduced during the production stage for the Intel VR10,VR11 Mode.

The output voltage is then programmed as follow:

V_OUT= V_REF– (R_FB+ R_OFFSET) ⋅ (I_DROOP) + (R_OFFSET) ⋅ (I_OFFSET

)

Offset resistor can be designed by considering the following relationship:

V_OS

R_OFFSET= ---------------------

I_OFFSET

Offset automatically given by the DAC selection differs from the offset implemented through

the I_OFFSETcurrent: the built-in feature is trimmed in production and assures 0.5% error

( 0.6% for the AMD DAC) over load and line variations.

35/64

Voltage positioning

L6713A

12.2

Droop function (Optional)

This method "recovers" part of the drop due to the output capacitor ESR in the load

transient, introducing a dependence of the output voltage on the load current: a static error

proportional to the output current causes the output voltage to vary according to the sensed

current.

As shown in Figure 11, the ESR drop is present in any case, but using the droop function

the total deviation of the output voltage is minimized.Moreover, more and more high-

performance CPUs require precise load-line regulation to perform in the proper way.

DROOP function is not then required only to optimize the output filter, but also beacomes a

requirement of the load.

Connecting DROOP pin and FB pin together, the device forces a current I_DROOP

,

proportional to the read current, into the feedback resistor (R_FB+R_OFFSET) implementing the

load regulation dependence. Since I_DROOPdepends on the current information about the N

phases, the output characteristic vs. load current is then given by (neglecting the OFFSET

voltage term):

V_OUT= V_REF– (R_FB+ R_OFFSET) ⋅ I_DROOP

DCR

Rg

-------------

⋅ I_OUT= V_REF– R_DROOP⋅ I_OUT

V

_REF– (R_FB+ R_OFFSET) ⋅

Where DCR is the inductor parasite resistance (or sense resistor when used) and I_OUTis the

output current of the system. The whole power supply can be then represented by a "real"

voltage generator with an equivalent output resistance R_DROOPand a voltage value of V_REF

.

R

_FBresistor can be also designed according to the R_DROOPspecifications as follow:

Rg

R_FB= R_DROOP⋅ ------------- – R_OFFSET

DCR

Droop function is optional, in case it is not desired, the DROOP pin can be disconnected

from the FB and an information about the total delivered current becomes available for

debugging, and/or current monitoring. When not used, the pin can be shorted to SGND.

36/64

L6713A

Load Transient Boost TechnologyTM

13

Load Transient Boost Technology^TM

Load Transient Boost (LTB) Technology™ (Patent Pending) is a L6713A feature to minimize

the count of output filter capacitors (MLCC and Bulk capacitors) to respect the load transient

specifications.

The device turns on simultaneously all the phases as soon as a load transient is detected

and keep them on for the necessary time to supply the extra energy to the load.This time

depends on the COMP pin voltage and on a internal gain, in order to keep under control the

output voltage ring back.

Load Transition is detected through LTB pin connecting a R -C

vs. VOUT: the device

LTB LTB

measures the derivate dV/dt of the output voltage and so it is able to turns on all the phases

immediately after a load transition detection, minimizing the delay intervention.

Modifying the R -C

values the dV/dt can be easily programmed, extending the system

LTB LTB

design flexibility

dV_OUT

R_LTB= -----------------

50µA

1

C_LTB= ----------------------------------------------------------------

2 ⋅ π ⋅ R_LTB⋅ N ⋅ F_SW

where dV

is the output voltage drop due to load transition.

OUT

Moreover, Load Transient Boost (LTB) Technology™ Gain can be easily modified in order to

keep under control the output voltage ring back.

Figure 12. LTB connections (left) and waveform (right).

LTB

To VCC_Core

RLTB

CLTB

Short LTB pin to SGND to disable the LTB Technology™: in this condition the device works

as a dual-edge asynchronous PWM controller.

37/64

Load Transient Boost TechnologyTM

L6713A

13.1

LTB Gain modification (Optional)

The internal gain can be modified through the SS/LTBG/AMD pin, as shown in the

Figure 13.

The SS/LTBG/AMD pin is also used to set the Soft Start time, so the current flowing from

SS/LTBG/AMD pin has to be modified only after the Soft Start has been finished.

Using the D diode and R3 resistor (red square in Figure 13), after the Soft Start the current

flowing from SS/LTBG/AMD pin versus SGND is zero, so the internal gain is not modified.As

a consequence the LTB gain is the default value (LTB Gain = 2).

To decrease the LTB gain it is necessary to use the circuit composed by Q, R1 and R2 (blue

square in Figure 13.)

After the Soft-Start the current flowing from SS/LTBG/AMD pin depends only on R1 resistor,

so reducing the R1 resistor value the LTB gain can be reduced. The sum of R1 and R2

resistors have to be selected to have the desiderated Soft Start time.

Figure 13. SS/OSC/LTB connections to modify LTB Gain when using INTEL mode.

SS_END

SS/LTBG/ AMD

LTB GAIN=2

LTB GAIN <2

V

Pull-Up(1.2V)

D

R3

RPull-Up(1k)

R1

R2

Q

to SSEND Logic

Rb(10k)

38/64

L6713A

Dynamic VID transitions

14

Dynamic VID transitions

The device is able to manage Dynamic VID Code changes that allow Output Voltage

modification during normal device operation. OVP and UVP signals (and PGOOD in case of

AMD Mode) are masked during every VID transition and they are re-activated after the

transition finishes with a 32 clock cycles delay to prevent from false triggering due to the

transition.

When changing dynamically the regulated voltage (D-VID), the system needs to charge or

discharge the output capacitor accordingly. This means that an extra-current I_D-VIDneeds to

be delivered, especially when increasing the output regulated voltage and it must be

considered when setting the over current threshold. This current can be estimated using the

following relationships:

dV_OUT

-----------------

⋅

I_{D – VID}= C_OUT

dT_VID

where dV_OUTis the selected DAC LSB (6.25mV for VR11 and VR10 Extended DAC or

25mV for AMD DAC) and T_VIDis the time interval between each LSB transition (externally

driven). Overcoming the OC threshold during the dynamic VID causes the device to enter

the constant current limitation slowing down the output voltage dV/dt also causing the failure

in the D-VID test.

L6713A checks for VID code modifications (See Figure 14) on the rising edge of an internal

additional DVID-clock and waits for a confirmation on the following falling edge. Once the

new code is stable, on the next rising edge, the reference starts stepping up or down in LSB

increments every VID-clock cycle until the new VID code is reached. During the transition,

VID code changes are ignored; the device re-starts monitoring VID after the transition has

finished on the next rising edge available. VID-clock frequency (F_DVID) depends on the

operative mode selected: for Intel Mode it is in the range of 1MHz to assure compatibility

with the specifications while, for AMD Mode, this frequency is lowered to about 250kHz.

When L6713A performs a D-VID transition in AMD Mode, DVID pin is pulled high as long as

the device is performing the transition (also including the additional 32clocks delay)

Warning: Warning: if the new VID code is more than 1 LSB different

from the previous, the device will execute the transition

stepping the reference with the DVID-clock frequency F_DVID

until the new code has reached: for this reason it is

recommended to carefully control the VID change rate in

order to carefully control the slope of the output voltage

variation especially in Intel Mode.

39/64

Dynamic VID transitions

Figure 14. Dynaminc VID Transitions.

L6713A

VID Clock

VID [0,7]

t

Int. Reference

T_DVID

T

sw

t

V

out

T_VID

x 4 Step VID Transition

4 x 1 Step VID Transition

Vout Slope Controlled by internal

DVID-Clock Oscillator

Vout Slope Controlled by external

driving circuit (T_VID

)

40/64

L6713A

Enable and disable

15

Enable and disable

L6713A has three different supplies: VCC pin to supply the internal control logic, VCCDRx

to supply the low side drivers and BOOTx to supply the high side drivers. If the voltage at

pins VCC and VCCDRx are not above the turn on thresholds specified in the Electrical

characteristics, the device is shut down: all drivers keep the MOSFETs OFF to show high

impedance to the load. Once the device is correctly supplied, proper operation is assured

and the device can be driven by the OUTEN pin to control the power sequencing. Setting

the pin free, the device implements a soft start up to the programmed voltage. Shorting the

pin to SGND, it resets the device (SS_END/PGOOD is shorted to SGND in this condition)

from any latched condition and also disables the device keeping all the MOSFET turned

OFF to show high impedance to the load.

41/64

Soft start

L6713A

16

Soft start

L6713A implements a soft-start to smoothly charge the output filter avoiding high in-rush

currents to be required to the input power supply. The device increases the reference from

zero up to the programmed value in different ways according to the selected Operative

Mode and the output voltage increases accordingly with closed loop regulation.

The device implements Soft-Start only when all the power supplies are above their own turn-

on thresholds and the OUTEN pin is set free.

At the end of the digital Soft-Start, SS_END/PGOOD signal is set free. Protections are

active during this phase; Under Voltage is enabled when the reference voltage reaches 0.6V

while Over Voltage is always enabled with a threshold dependent on the selected Operative

Mode or with the fixed threshold programmed by R_OVP(See “Over voltage and

programmable OVP” Section).

Figure 15. Soft Start

Intel Mode

AMD 6BIT Mode

OUTEN

V

OVP

t

V

t

OUT

OVP

SS_END

PGOOD

T

T T

4

t

1

2

3

T

SS

T

SS

16.1

Intel mode

Once L6713A receives all the correct supplies and enables, and Intel Mode has been

selected, it initiates the Soft-Start phase with a T₁=1ms_(min)delay. After that, the reference

ramps up to V_BOOT=1.081V (1.100V - 19mV) in T₂according to the SS/LTBG/AMD settings

and waits for T₃=75µsec_(typ)during which the device reads the VID lines. Output voltage will

then ramps up to the programmed value in T₄with the same slope as before (See

Figure 15).

SS/LTB/AMD defines the frequency of an internal additional Soft-Start-oscillator used to

step the reference from zero up to the programmed value; this oscillator is independent from

the main oscillator whose frequency is programmed through the OSC pin.

In particular, it allows to precisely programming the start-up time up to V_BOOT(T₂) since it is

a fixed voltage independent by the programmed VID. Total Soft-Start time dependence on

the programmed VID results (See Figure 17 and See Figure 19).

42/64

L6713A

Soft start

Protections are active during Soft-Start, UVP is enabled after the reference reaches 0.6V

while OVP is always active with a fixed 1.24V threshold before V_BOOTand with the threshold

coming from the VID (or the programmed V_OVP) after V_BOOT(See red-dashed line in

Figure 15).

Note:

If during T₃the programmed VID selects an output voltage lower than V_BOOT, the output

voltage will ramp to the programmed voltage starting from V_BOOT

.

16.1.1

SS/LTB/AMD connections when using LTB Gain = 2

SS/LTB/AMD pin sets then the Output Voltage dV/dt during Soft-Start according to the

resistor R_SSOSCconnected vs. SSEND/PGOOD pin through a signal diode(See Figure 16).

Figure 16. SS/LTBG/AMD connections for INTEL mode, when using LTB Gain = 2

SSEND/PGOOD

SS/LTBG/AMD

V

Pull-Up

R

SSOSC

R

Pull-Up

to SSEND Logic

1.24 – V_DIODE[V]

----------------------------------------------

1.24

R_SSOSC[kΩ] = T₂[µs] ⋅ 4.9783 ⋅ 10^–2

⋅

⎧

⎪

⎨

⎪

⎩

R_SSOSC[kΩ]

5.3816 ⋅ 10^–2

1.24

a)

b)

------------------------------------- ----------------------------------------------

⋅

⋅ V_SS

1.24 – V_DIODE[V]

T_SS[µs] = 1075[µs] +

R_SSOSC[kΩ]

1.24

------------------------------------- ----------------------------------------------

⋅

⋅ [V_BOOT+ (V_BOOT– V_SS)]

5.3816 ⋅ 10^–2

1.24 – V_DIODE[V]

⎧

a) if(V_SS>V_BOOT

)

⎪

⎨

⎪

⎩

b) if(V_SS< V_BOOT

)

where T_SSis the time spent to reach the programmed voltage V_SSand R_SSOSCthe resistor

connected between SS/LTBG/AMD and SSEND (through a signal diode) in kΩ.

43/64

Soft start

L6713A

, diode versus SSEND.

Figure 17. Soft-start time for Intel mode when using R

SSOSC

7

6

Time to Vboot

Time to 1.6000V

5

4

3

2

1

0

1

10

100

1000

Rssosc [kOhms] vs. SSEND through sognal diode

16.1.2

SS/LTB/AMD connections when using LTB Gain < 2

When using LTB Gain <2, the equivalent R

resistance is composed by the sum of

SSOSC

R +R ) because until the Soft Start is not finished the Q transistor is OFF (See Figure 18).

1

2

Figure 18. SS/LTBG/AMD connections for INTEL mode, when using LTB Gain < 2

SS_END

SS/LTBG/ AMD

VPull-Up(1.2V)

RPull-Up(1k)

R1

R2

Q

RSSOSC=R1+R2

to SSEND Logic

Rb(10k)

R_SSOSC[kΩ] = T₂[µs] ⋅ 4.9783 ⋅ 10^–2

⎧

R_SSOSC[kΩ]

5.3816 ⋅ 10^–2

-------------------------------------

⎪

⎨

⎪

⎩

⋅ V_SS

if(V_SS>V_BOOT

)

T_SS[µs] = 1075[µs] +

R_SSOSC[kΩ]

-------------------------------------

⋅ [V_BOOT+ (V_BOOT– V_SS)] if(V_SS< V_BOOT

)

5.3816 ⋅ 10^–2

where T_SSis the time spent to reach the programmed voltage V_SSand R_SSOSCthe resistor

connected between SS/LTBG/AMD and SGND (R_SSOSC= R₁R₂) in kΩ.

+

44/64

L6713A

Soft start

Figure 19. Soft-start time for Intel mode when using R

versus SGND.

SSOSC

5

4.5

Time to Vboot

4

Time to 1.6000V

3.5

3

2.5

2

1.5

1

0.5

0

1

10

100

1000

Rssosc [kOhms] vs. SGND

16.2

AMD mode

Once L6713A receives all the correct supplies and enables, and AMD Mode has been

selected, it initiates the Soft-Start by stepping the reference from zero up to the programmed

VID code (See Figure 15); the clock now used to step the reference is the same as the main

oscillator programmed by the OSC pin, SSOSC pin is not applicable in this case. The Soft-

Start time results then (See Figure 20):

dV_OUT

----------------- = 3.125 ⋅ F_SW[kkHz] ⇒T_SS= -------------------------------------------------

dT 3.125 ⋅ F_SW[kHz]

V_SS

where T_SSis the time spent to reach V_SSand F_SWis the main switching frequency

programmed by OSC pin. Protections are active during Soft-Start, UVP is enabled after the

reference reaches 0.6V while OVP is always active with the fixed 1.800V threshold (or the

programmed V_OVP).

Figure 20. Soft-Start time for AMD mode

4

3.5

3

550

500

450

400

350

300

250

200

150

4

3.5

3

550

500

450

400

350

300

250

200

150

2.5

2

2.5

2

1.5

1

1.5

1

Time to 1.6000V

Time to 1.1000V

Switching Frequency per phase

0.5

0

0.5

0

200

400

600

800

1000

0

200

400

600

800

1000

Rosc [kOhms] to SGND

45/64

Soft start

L6713A

16.3

Low-side-less startup

In order to avoid any kind of negative undershoot on the load side during start-up, L6713A

performs a special sequence in enabling LS driver to switch: during the soft-start phase, the

LS driver results disabled (LS = OFF) until the HS starts to switch. This avoid the dangerous

negative spike on the output voltage that can happen if starting over a pre-biased output

(See Figure 21).

This particular feature of the device masks the LS turn-ON only from the control loop point of

view: protections are still allowed to turn-ON the LS MOSFET in case of over voltage if

needed.

Figure 21. Low-side-less start-up comparison

46/64

L6713A

Output voltage monitor and protections

17

Output voltage monitor and protections

L6713A monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP

and PGOOD (when applicable) conditions. The device shows different thresholds when

programming different operation mode (Intel or AMD, See Table 11) but the behavior in

response to a protection event is still the same as described below.

When using OFFSET funcionality the OVP, UVP and PGOOD thresholds change in according to

the OFFSET voltage:

V_SEN= V_OUT– (R_OFFSET) ⋅ (I_OFFSET) ⇒V_OUT[TH] = V_SEN[TH] + (R_OFFSET) ⋅ I_OFFSET

Protections are active also during soft-start (See “Soft start” Section) while are masked

during D-VID transitions with an additional 32 clock cycle delay after the transition has

finished to avoid false triggering.

17.1

17.2

Under voltage

If the output voltage monitored by VSEN drops more than -750mV below the programmed

reference for more than one clock period, L6713A turns OFF all MOSFETs and latches the

condition: to recover it is required to cycle Vcc or the OUTEN pin. This is independent of the

selected operative mode.

Preliminary over voltage

To provide a protection while VCC is below the UVLO_VCCthreshold is fundamental to avoid

damage to the CPU in case of failed HS MOSFETs. In fact, since the device is supplied from

the 12V bus, it is basically “blind” for any voltage below the turn-ON threshold (UVLO_VCC). In

order to give full protection to the load, a preliminary-OVP protection is provided while VCC

is within UVLO_VCCand UVLO_OVP

.

This protection turns-ON the low side MOSFETs as long as the VSEN pin voltage is greater

than 1.800V with a 350mV hysteresis. When set, the protection drives the LS MOSFET with

a gate-to-source voltage depending on the voltage applied to VCCDRx and independently

by the turn-ON threshold across these pins (UVLO_VCCDR). This protection depends also on

the OUTEN pin status as detailed in Figure 22.

A simple way to provide protection to the output in all conditions when the device is OFF

(then avoiding the unprotected red region in Figure 22-Left) consists in supplying the

controller through the 5V_SBbus as shown in Figure 22-Right: 5V_SBis always present before

+12V and, in case of HS short, the LS MOSFET is driven with 5V assuring a reliable

protection of the load. Preliminary OVP is always active before UVLO_VCCfor both Intel and

AMD Modes.

47/64

Output voltage monitor and protections

Figure 22. Output voltage protections and typical principle connections

L6713A

+5V_SB

(OUTEN = 0)

Preliminary OVP

VSEN Monitored

(OUTEN = 1)

Programmable OVP

VSEN Monitored

+12V

VCC

V

cc

UVLO

VCC

VCCDR1

VCCDR2

VCCDR3

Preliminary OVP Enabled

VSEN Monitored

OVP

No Protection

Provided

17.3

Over voltage and programmable OVP

Once VCC crosses the turn-ON threshold and the device is enabled (OUTEN = 1), L6713A

provides an Over Voltage Protection: when the voltage sensed by VSEN overcomes the

OVP threshold, the controller permanently switches on all the low-side MOSFETs and

switches OFF all the high-side MOSFETs in order to protect the load. The OSC/ FAULT pin

is driven high (5V) and power supply or OUTEN pin cycling is required to restart

operations.The OVP Threshold varies according to the operative mode selected (See

Table 11).

The OVP threshold can be also programmed through the OVP pin: leaving the pin floating, it

is internally pulled-up and the OVP threshold is set according to Table 11. Connecting the

OVP pin to SGND through a resistor R_OVP, the OVP threshold becomes the voltage present

at the pin. Since the OVP pin sources a constant I_OVP=12.5µA current(See Table 4), the

programmed voltage becomes:

OVP_TH

OVP_TH= R_OVP⋅ 12.5µA

Filter OVP pin with 100pF(max) vs. SGND.

⇒

R_OVP= -------------------

12.5µA

17.4

PGOOD (only for AMD mode)

It is an open-drain signal set free after the soft-start sequence has finished. It is pulled low

when the output voltage drops below -300mV of the programmed voltage.

48/64

L6713A

Over current protection

18

Over current protection

The device limits the total delivered current turning OFF all the MOSFETs as soon as the

delivery current is higher than an adjustable thresholds.This condition is lathed and power

supply or OUTEN pin cycling is required to restart operations.

The device sources a copy of I

current from the OCSET pin: connecting a resistor

DROOP

R

between OCSET pin and SGND the voltage at the OCSET pin depends on the total

OCP

delivery output current, as shown in the following relationships:

DCR

R_G

-------------

⋅ I_OUT

V_OCSET= R_OCP⋅ I_DROOP= R_OCP

⋅

Figure 23. OCP Connections (left) and waveforms (right).

VOUT

OCSET

I_DROOP

OCSET

OCP

COMPARATOR

UGATE

LGATE

R_OCP

C_OCP

V_OCTH=1.240V

As soon as the OCSET pin voltage is higher than the internal fixed thresholds V

(1.24V

OCTH

TYP, See Table 4), the device turns OFF all the MOSFETs and latches the condition.

The OCP threshold can be easily programmed through the R resistor:

OCP

R_G

V_OCTH

------------- --------------------------

R_OCP

=

⋅

DCR I_OUT(OCP)

The Output Over Current threshold has to be programmed, by designing the R

resistors,

OCP

to a safe value, in order to be sure that the device doesn't enter OCP during normal

operation of the device. This value must take into consideration also the extra current

needed during the Dynamic VID Transition I_D-VIDand, since the device reads across

inductor DCR, the process spread and temperature variations of these sensing elements.

Moreover, since also the internal threshold spreads, the R

minimum value V_OCTH(min)of the threshold as follow:

design has to consider the

OCP

R

V_OCTH(min)

I_OUT(OCP)

----------------^G-------------- ---------------------------------

R_OCP

=

⋅

DCR(max)

where I_OUT(OCP)is the total delivery current for the Over Current condition and it must be

calculated considering the maximum delivery current and I_D-VID(when D-VID are

implemented):

I

_OUT(OCP)>I_OUT^MAX+ I_D–VID

When it is necessary, filter OCSET pin to introduce a small delay in the Over Current

intervention.

49/64

Oscillator

L6713A

19

Oscillator

L6713A embeds two/three phase oscillator with optimized phase-shift (180º/120º phase-

shift) in order to reduce the input rms current and optimize the output filter definition.

The internal oscillator generates the triangular waveform for the PWM charging and

discharging with a constant current an internal capacitor. The switching frequency for each

channel, F_SW, is internally fixed at 200kHz so that the resulting switching frequency at the

load side results in being multiplied by N (number of phases).

The current delivered to the oscillator is typically 25µA (corresponding to the free running

frequency F_SW=200kHz) and it may be varied using an external resistor (R_OSC) connected

between the OSC pin and SGND or VCC (or a fixed voltage greater than 1.24V). Since the

OSC pin is fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced)

from (into) the pin considering the internal gain of 6KHz/µA.

In particular connecting R_OSCto SGND the frequency is increased (current is sunk from the

pin), while connecting R_OSCto VCC=12V the frequency is reduced (current is forced into the

pin), according the following relationships:

R

vs. SGND

OSC

1.240V

R_OSC(kΩ)

kHz

µA

7.422 ⋅ 10³

---------------------------

----------

-------------------------------

⇒R_OSC(kΩ)

F_SW= 200(kHz) +

7.422 ⋅ 10³

⋅ 6

= 200(kHz) +

R_OSC(kΩ)

7.422 ⋅ 10³

kHz

----------

-------------------------------

6

= 200(kHz) +

⇒R_OSC(kΩ) = -----------------------------------------------------------[kΩ]

F_SW(kHz) – 200(kHz)

µA

R_OSC(kΩ)

R

vs. +12V

OSC

6.456 ⋅ 10⁴

12V – 1.240V

R_OSC(kΩ)

kHz

µA

-----------------------------------

----------

F_SW= 200(kHz) –

⋅ 6

= 200(kHz)–------------------------------- ⇒R_OSC(kΩ) =

R_OSC(kΩ)

2

6.456 ⋅ 10⁴

kHz

µA

----------

6

= 200(kHz)–------------------------------- ⇒R_OSC(kΩ) = -----------------------------------------------------------[kΩ]

R_OSC(kΩ)

200(kHz) – F_SW(kHz)

Maximum programmable switching frequency per phase must be limited to 1MHz to avoid

minimum Ton limitation. Anyway, device power dissipation must be checked prior to design

high switching frequency systems.

Figure 24. R_OSCvs. Switching Frequency

400

350

300

250

200

150

100

50

7000

6000

5000

4000

3000

2000

1000

0

150

250

350

450

550

650

750

850

950

1050

25

50

75

100

125

150

175

200

Fsw [kHz] Programmed

50/64

L6713A

Driver section

20

Driver section

The integrated high-current drivers allow using different types of power MOS (also multiple

MOS to reduce the equivalent R_dsON), maintaining fast switching transition.

The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for

return. The drivers for the low-side MOSFETs use VCCDRx pin for supply and PGNDx pin

for return. A minimum voltage at VCCDRx pin is required to start operations of the device.

VCCDRx pins must be connected together.

The controller embodies a sophisticated anti-shoot-through system to minimize low side

body diode conduction time maintaining good efficiency saving the use of Schottky diodes:

when the high-side MOSFET turns OFF, the voltage on its source begins to fall; when the

voltage reaches 2V, the low-side MOSFET gate drive is suddenly applied. When the low-

side MOSFET turns OFF, the voltage at LGATEx pin is sensed. When it drops below 1V, the

high-side MOSFET gate drive is suddenly applied.

If the current flowing in the inductor is negative, the source of high-side MOSFET will never

drop. To allow the turning on of the low-side MOSFET even in this case, a watchdog

controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side

MOSFET is switched on so allowing the negative current of the inductor to recirculate. This

mechanism allows the system to regulate even if the current is negative.

The BOOTx and VCCDRx pins are separated from IC's power supply (VCC pin) as well as

signal ground (SGND pin) and power ground (PGNDx pin) in order to maximize the

switching noise immunity. The separated supply for the different drivers gives high flexibility

in MOSFET choice, allowing the use of logic-level MOSFET. Several combination of supply

can be chosen to optimize performance and efficiency of the application.

Power conversion input is also flexible; 5V, 12V bus or any bus that allows the conversion

(See maximum duty cycle limitations) can be chosen freely.

51/64

System control loop compensation

L6713A

21

System control loop compensation

The control loop is composed by the Current Sharing control loop (See Figure 9) and the

Average Current Mode control loop. Each loop gives, with a proper gain, the correction to

the PWM in order to minimize the error in its regulation: the Current Sharing control loop

equalize the currents in the inductors while the Average Current Mode control loop fixes the

output voltage equal to the reference programmed by VID. Figure 25 shows the block

diagram of the system control loop.

The system Control Loop is reported in Figure 26. The current information I_DROOPsourced

by the DROOP pin flows into R_FBimplementing the dependence of the output voltage from

the read current.

Figure 25. Main control loop

L3

PWM3

1 / 5

L2

PWM2

PWM1

C

R

OUT

1 / 5

L1

ERROR AMPLIFIER

V

REF

4 / 5

I

DROOP

I

INFO1

INFO2

INFO3

CURRENT SHARING

DUTY CYCLE

CORRECTION

COMP

FB

DROOP

Z (s)

Z

(s)

FB

F

(PHASE2 Only applies when using 3-PHASE Operation)

The system can be modeled with an equivalent single phase converter which only

difference is the equivalent inductor L/N (where each phase has an L inductor).The Control

Loop gain results (obtained opening the loop after the COMP pin):

PWM ⋅ Z_F(s) ⋅ (R_DROOP+ Z_P(s))

G_LOOP(s) = –------------------------------------------------------------------------------------------------------------------------

Z_F(s)

A(s)

1

⎛

⎞

[Z_P(s) + Z_L(s)] ⋅ -------------- + 1 + ----------- ⋅ R_FB

⎝

⎠

A(s)

Where:

●

DCR is the Inductor parasitic resistance;

DCR

-------------

⋅ R_FBis the equivalent output resistance determined by the droop

●

R_DROOP

function;

=

Rg

●

Z_P(s) is the impedance resulting by the parallel of the output capacitor (and its ESR)

and the applied load R_O;

●

Z_F(s) is the compensation network impedance;

Z_L(s) is the parallel of the N inductor impedance;

A(s) is the error amplifier gain;

V_IN

-- ------------------

4

PWM =

⋅

is the PWM transfer function where ∆V_OSCis the oscillator ramp

5

∆V_OSC

amplitude and has a typical value of 3V.

52/64

L6713A

System control loop compensation

Removing the dependence from the Error Amplifier gain, so assuming this gain high

enough, and with further simplifications, the control loop gain results:

V

Z

(s)

R

+ R

1 + s ⋅

C

⋅

(R

//R + ESR)

4

5

IN

F

O

DROOP

O

DROOP O

-- --------------------- --------------- ------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------

G

(s) = –

⋅

LOOP

∆V

R

2

OSC

FB

L

R

+ -------

----

-------

s

⋅

C

⋅

--------------------- + C

N ⋅

⋅

ESR + C

⋅

O

+ 1

N ^{+ s ⋅}

N

O

N

R

O

The system Control Loop gain (See Figure 26) is designed in order to obtain a high DC gain

to minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the

desired crossover frequency ω . Neglecting the effect of Z_F(s), the transfer function has one

T

zero and two poles; both the poles are fixed once the output filter is designed (LC filter

resonance ω ) and the zero (ω_ESR) is fixed by ESR and the Droop resistance.

LC

Figure 26. Equivalent Control Loop Block Diagram (left) and Bode Diagram (right).

d V_OUTL / N

V_OUT

PWM

dB

ESR

C_O

R_O

VREF

G_LOOP(s)

K

DROOP

FB

COMP

C_F

VSEN

FBG

Z_F(s)

R_F[dB]

R_F

Z_F(s)

C_P

ω

ω_LC

=

ω_F

ω_ESR

Z

_FB(s)

R_FB

ω_T

To obtain the desired shape an R_F-C_Fseries network is considered for the Z_F(s)

implementation. A zero at ω =1/R_FC_Fis then introduced together with an integrator. This

F

integrator minimizes the static error while placing the zero ω in correspondence with the L-

F

C resonance assures a simple -20dB/dec shape of the gain.

In fact, considering the usual value for the output filter, the LC resonance results to be at

frequency lower than the above reported zero.

Compensation network can be simply designed placing ω = ω_LCand imposing the cross-

F

over frequency ω as desired obtaining (always considering that ω might be not higher than

T

1/10th of the switching frequency F_SW):

R_FB⋅ ∆V_OSC

5

4

L

------------------------------------ --

----------------------------------------------------------

R_F

=

⋅

⋅ ω ⋅

T

V_IN

N ⋅ (R_DROOP+ ESR)

L

---

C_O

⋅

N

C_F= -----------------------

R_F

Moreover, it is suggested to filter the high frequency ripple on the COMP pin adding also a

capacitor between COMP pin and FB pin (it does not change the system bandwidth:

1

C_P= ----------------------------------------------------------

2 ⋅ π ⋅ R_F⋅ N ⋅ F_SW

53/64

Thermal monitor

L6713A

22

Thermal monitor

L6713A continuously senses the system temperature through TM pin: depending on the

voltage sensed by this pin, the device sets free the VR_FAN pin as a warning and, after

further temperature increase, also the VR_HOT pin as an alarm condition.

These signals can be used to give a boost to the system fan (VR_FAN) and improve the VR

cooling, or to initiate the CPU low power state (VR_HOT) in order to reduce the current

demand from the processor so reducing also the VR temperature. In a different manner,

VR_FAN can be used to initiate the CPU low power state so reducing the processor current

requirements and VR_HOT to reset the system in case of further dangerous temperature

increase.

Thermal sensors is external to the PWM control IC since the controller is normally not

located near the heat generating components: it is basically composed by a NTC resistor

and a proper biasing resistor R_TM. NTC must be connected as close as possible at the

system hot-spot in order to be sure to control the hottest point of the VR.

Typical connection is reported in Figure 27 that also shows how the trip point can be easily

programmed by modifying the divider values in order to cross the VR_FAN and VR_HOT

thresholds at the desired temperatures.

Both VR_HOT and VR_FAN are active high and open drain outputs. Thermal Monitor

function is enabled if V >>UVLO

.

CC

VCC

Figure 27. System thermal monitor typical connections.

TM Voltage - NTC=3300/4250K

4.00

3.80

3.60

3.40

3.20

3.00

2.80

2.60

2.40

2.20

2.00

+5V

Sense Element

(Place remotely, near Hot Spot)

TM

Rtm = 330

Rtm = 390

Rtm = 470

R_TM

80

85

90

95

100

105

110

115

120

Temperature [degC]

54/64

L6713A

Tolerance band (TOB) definition

23

Tolerance band (TOB) definition

Output voltage load-line varies considering component process variation, system

temperature extremes, and age degradation limits. Moreover, individual tolerance of the

components also varies among designs: it is then possible to define a Manufacturing

Tolerance Band (TOB_Manuf) that defines the possible output voltage spread across the

nominal load line characteristic.

TOB_Manufcan be sliced into different three main categories: Controller Tolerance, External

Current Sense Circuit Tolerance and Time Constant Matching Error Tolerance. All these

parameters can be composed thanks to the RSS analysis so that the manufacturing

variation on TOB results to be:

TOB_Manuf

=

TOB²_Controller+ TOB²_CurrSense+ TOB_T²_CMatching

Output voltage ripple (V_P=V_PP/2) and temperature measurement error (V_TC) must be added

to the Manufacturing TOB in order to get the system Tolerance Band as follow:

TOB = TOB_Manuf+ V_P+ V_TC

All the component spreads and variations are usually considered at 3σ. Here follows an

explanation on how to calculate these parameters for a reference L6713A application.

23.1

Controller tolerance (TOB_Controller)

It can be further sliced as follow:

●

Reference tolerance. L6713A is trimmed during the production stage to ensure the

output voltage to be within k_VID= 0.5% ( 0.6% for AMD DAC) over temperature and

line variations. In addition, the device automatically adds a -19mV offset (Only for Intel

Mode) avoiding the use of any external component. This offset is already included

during the trimming process in order to avoid the use of any external circuit to generate

this offsets and, moreover, avoiding the introduction of any further error to be

considered in the TOB calculation.

●

Current Reading Circuit. The device reads the current flowing across the inductor DCR

by using its dedicated differential inputs. The current sourced by the VRD is then

reproduced and sourced from the DROOP pin scaled down by a proper designed gain

as follow:

DCR

-------------

⋅ I_OUT

I_DROOP

=

Rg

This current multiplied by the R_FBresistor connected from FB pin vs. the load allows

programming the droop function according to the selected DCR/Rg gain and R_FB

resistor. Deviations in the current sourced due to errors in the current reading, impacts

on the output voltage depending on the size of R_FBresistor. The device is trimmed

during the production stage in order to guarantee a maximum deviation of k_IFB= 1µA

from the nominal value.

Controller tolerance results then to be:

TOB_Controller

[(VID – 19mV) ⋅ k_VID]²+ (k_IDROOP⋅ R_FB

2

=

)

55/64

Tolerance band (TOB) definition

L6713A

23.2

Ext. current sense circuit tolerance (TOB_CurrSense)

It can be further sliced as follow:

●

Inductor DCR Tolerance (k_DCR). Variations in the inductor DCR impacts on the output

voltage since the device reads a current that is different from the real current flowing

into the sense element. As a results, the controller will source a I_DROOPcurrent different

from the nominal. The results will be an AVP different from the nominal in the same

percentage as the DCR is different from the nominal. Since all the sense elements

results to be in parallel, the error related to the inductor DCR has to be divided by the

number of phases (N).

●

Trans-conductance resistors tolerance (k_Rg). Variations in the Rg resistors impacts in

the current reading circuit gain and so impacts on the output voltage. The results will be

an AVP different from the nominal in the same percentage as the Rg is different from

the nominal. Since all the sense elements results to be in parallel, and so the three

current reading circuits, the error related to the Rg resistors has to be divided by the

number of phases (N).

●

NTC Initial Accuracy (k_{NTC_0}). Variations in the NTC nominal value at room

temperature used for the thermal compensation impacts on the AVP in the same

percentage as before. In addition, the benefit of the division by the number of phases N

cannot be applied in this case.

NTC Temperature Accuracy (k_NTC). NTC variations from room to hot also impacts on

the output voltage positioning. The impact is bigger as big is the temperature variation

from room to hot (∆T).

All these parameters impacts the AVP, so they must be weighted on the maximum voltage

swing from zero load up to the maximum electrical current (V_AVP). Total error from external

current sense circuit results:

k_D²_CRk²_Rg

2

α ⋅ ∆T ⋅ k_NTC

TOB_CurrSense

=

V²_AVP

⋅

------------- + -------- + k_N²_TC0

+

⎛

⎝

⎞

⎠

--------------------------------------

DCR

N

23.3

Time constant matching error tolerance (TOB_TCMatching)

●

Inductance and capacitance Tolerance (k_L, k_C). Variations in the inductance value and

in the value of the capacitor used for the Time Constant Matching causes over/under

shoots after a load transient appliance. This impacts the output voltage and then the

TOB. Since all the sense elements results to be in parallel, the error related to the time

constant mismatch has to be divided by the number of phases (N).

●

Capacitance Temperature Variations (k_Ct). The capacitor used for time constant

matching also vary with temperature (∆T_C) impacting on the output voltage transients

ad before. Since all the sense elements results to be in parallel, the error related to the

time constant mismatch has to be divided by the number of phases (N).

All these parameters impact the Dynamic AVP, so they must be weighted on the maximum

dynamic voltage swing (I_dyn). Total error due to time constant mismatch results:

k_L²+ k²_C+ (k_Ct⋅ ∆TC)²

TOB_TCMatching

=

V²_AVPDyn

⋅

------------------------------------------------------------

N

56/64

L6713A

Tolerance band (TOB) definition

23.4

Temperature measurement error (V_TC)

Error in the measured temperature (for thermal compensation) impacts on the output

regulated voltage since the correction form the compensation circuit is not what required to

keep the output voltage flat.

The measurement error (ε_Temp) must be multiplied by the copper temp coefficient (α) and

compared with the sensing resistance (R_SENSE): this percentage affects the AVP voltage as

follow:

α ⋅ ε_Temp

R_SENSE

--------------------------

⋅ V_AVP

V_TC

=

57/64

Layout guidelines

L6713A

24

Layout guidelines

Since the device manages control functions and high-current drivers, layout is one of the

most important things to consider when designing such high current applications. A good

layout solution can generate a benefit in lowering power dissipation on the power paths,

reducing radiation and a proper connection between signal and power ground can optimize

the performance of the control loops.

Two kind of critical components and connections have to be considered when layouting a

VRM based on L6713A: power components and connections and small signal components

connections.

24.1

Power components and connections

These are the components and connections where switching and high continuous current

flows from the input to the load. The first priority when placing components has to be

reserved to this power section, minimizing the length of each connection and loop as much

as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections

must be a part of a power plane and anyway realized by wide and thick copper traces: loop

must be anyway minimized. The critical components, i.e. the power transistors, must be

close one to the other. The use of multi-layer printed circuit board is recommended.

Figure 28 shows the details of the power connections involved and the current loops. The

input capacitance (C_IN), or at least a portion of the total capacitance needed, has to be

placed close to the power section in order to eliminate the stray inductance generated by

the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be

connected near the HS drain.

Use proper VIAs number when power traces have to move between different planes on the

PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the

same high-current trace on more than one PCB layer will reduce the parasitic resistance

associated to that connection.

Connect output bulk capacitor as near as possible to the load, minimizing parasitic

inductance and resistance associated to the copper trace also adding extra decoupling

capacitors along the way to the load when this results in being far from the bulk capacitor

bank.

Gate traces must be sized according to the driver RMS current delivered to the power

MOSFET. The device robustness allows managing applications with the power section far

from the controller without losing performances. External gate resistors help the device to

dissipate power resulting in a general cooling of the device. When driving multiple

MOSFETs in parallel, it is suggested to use one resistor for each MOSFET.

58/64

L6713A

Layout guidelines

24.2

Small signal components and connections

These are small signal components and connections to critical nodes of the application as

well as bypass capacitors for the device supply (See Figure 28). Locate the bypass

capacitor (VCC, VCCDRx and Bootstrap capacitor) close to the device and refer sensible

components such as frequency set-up resistor R_OSC, over current resistor R_OCPand OVP

resistor R_OVPto SGND. Star grounding is suggested: connect SGND to PGND plane in a

single point to avoid that drops due to the high current delivered causes errors in the device

behavior.

Warning: Boot Capacitor Extra Charge. Systems that do not use

Schottky diodes might show big negative spikes on the

phase pin. This spike can be limited as well as the positive

spike but has an additional consequence: it causes the

bootstrap capacitor to be over-charged. This extra-charge

can cause, in the worst case condition of maximum input

voltage and during particular transients, that boot-to-phase

voltage overcomes the abs. max. ratings also causing device

failures. It is then suggested in this cases to limit this extra-

charge by adding a small resistor in series to the boot diode

(one resistor can be enough for all the three diodes if placed

upstream the diode anode, See Figure 28) and by using

standard and low-capacitive diodes.

Figure 28. Power connections and related connections layout (same for all phases).

To limit C_BOOTExtra-Charge

V_IN

BOOTx

UGATEx

PHASEx

C_IN

L

PHASEx

VCC

L

LGATEx

PGNDx

LOAD

SGND

+Vcc

Remote Sensing Connection must be routed as parallel nets from the FB/VSEN pins to the

load in order to avoid the pick-up of any common mode noise. Connecting these pins in

points far from the load will cause a non-optimum load regulation, increasing output

tolerance.

Locate current reading components close to the device. The PCB traces connecting the

reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up

of any common mode noise. It's also important to avoid any offset in the measurement and,

to get a better precision, to connect the traces as close as possible to the sensing elements.

Symmetrical layout is also suggested. Small filtering capacitor can be added, near the

controller, between V_OUTand SGND, on the CSx- line to allow higher layout flexibility.

59/64

Embedding L6713A - based VR

L6713A

25

Embedding L6713A - based VR

When embedding the VRD into the application, additional care must be taken since the

whole VRD is a switching DC/DC regulator and the most common system in which it has to

work is a digital system such as MB or similar. In fact, latest MB has become faster and

powerful: high speed data bus are more and more common and switching-induced noise

produced by the VRD can affect data integrity if not following additional layout guidelines.

Few easy points must be considered mainly when routing traces in which high switching

currents flow (high switching currents cause voltage spikes across the stray inductance of

the trace causing noise that can affect the near traces):

Keep safe guarding distance between high current switching VRD traces and data buses,

especially if high-speed data bus to minimize noise coupling.

Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that

must walk near the VRD.

Possible causes of noise can be located in the PHASE connections, MOSFET gate drive

and Input voltage path (from input bulk capacitors and HS drain). Also PGND connections

must be considered if not insisting on a power ground plane. These connections must be

carefully kept far away from noise-sensitive data bus.

Since the generated noise is mainly due to the switching activity of the VRM, noise

emissions depend on how fast the current switches. To reduce noise emission levels, it is

also possible, in addition to the previous guidelines, to reduce the current slope by properly

tuning the HS gate resistor and the PHASE snubber network.

60/64

L6713A

Mechanical data

26

Mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect . The category of

second level interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com

61/64

Mechanical data

L6713A

Table 14. TQFP64 Mechanical Data

mm.

inch

Typ.

Dim.

Min.

Typ.

Max.

Min.

Max.

A

A1

A2

b

1.20

0.15

1.05

0.27

0.20

12.20

10.20

6.10

0.0472

0.006

0.05

0.95

0.17

0.09

11.80

9.80

3.50

0.002

0.0374

0.0066

0.0035

0.464

1.00

0.22

0.0393

0.0086

0.0413

0.0086

0.0078

0.480

c

D

12.00

10.00

0.472

0.394

D1

D2

D3

E

0.386

0.401

0.1378

0.2402

7.50

12.00

10.00

0.295

0.472

0.394

11.80

9.80

3.50

12.20

10.20

6.10

0.464

0.386

0.480

0.401

E1

E2

E3

e

0.1378

0.2402

7.50

0.50

0.60

1.00

3.5°

0.295

0.0197

0.0236

0.0393

3.5°

L

0.45

0°

0.75

0.0177

0°

0.0295

L1

k

7 °

7°

ccc

0.080

0.0031

Figure 29. Package Dimensions

62/64

L6713A

Revision history

27

Revision history

Table 15. Revision history

Date

Revision

Changes

03-Mar-2006

1

Initial release.

Updated D2 and E2 exposed tab measures in Table 14: TQFP64

Mechanical Data

07-Nov-2006

2

63/64

L6713A

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64/64


型号：	L6713A
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	2/3 Phase controller with embedded drivers for Intel VR10, VR11 and AMD 6 bit CPUs 与英特尔VR10 ， VR11和AMD的6位CPU的嵌入式驱动2/3相位控制器驱动控制器
文件：	总64页 (文件大小：628K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L6713A [HOLTEK]

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